1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
165 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
167 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
170 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
173 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
174 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
175 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
176 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
177 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
178 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
179 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
180 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v4t_5
=
182 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
183 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
184 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
185 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
186 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
187 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
188 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
189 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
190 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
191 static const arm_feature_set arm_ext_v6_notm
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
193 static const arm_feature_set arm_ext_v6_dsp
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
195 static const arm_feature_set arm_ext_barrier
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
197 static const arm_feature_set arm_ext_msr
=
198 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
199 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
200 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
201 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
202 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
204 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
206 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
207 static const arm_feature_set arm_ext_m
=
208 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
,
209 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
210 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
211 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
212 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
213 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
214 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
215 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
216 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
217 static const arm_feature_set arm_ext_v8m_main
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
219 /* Instructions in ARMv8-M only found in M profile architectures. */
220 static const arm_feature_set arm_ext_v8m_m_only
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
222 static const arm_feature_set arm_ext_v6t2_v8m
=
223 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
224 /* Instructions shared between ARMv8-A and ARMv8-M. */
225 static const arm_feature_set arm_ext_atomics
=
226 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
228 /* DSP instructions Tag_DSP_extension refers to. */
229 static const arm_feature_set arm_ext_dsp
=
230 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
232 static const arm_feature_set arm_ext_ras
=
233 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
234 /* FP16 instructions. */
235 static const arm_feature_set arm_ext_fp16
=
236 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
238 static const arm_feature_set arm_arch_any
= ARM_ANY
;
239 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
240 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
241 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
243 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
246 static const arm_feature_set arm_cext_iwmmxt2
=
247 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
248 static const arm_feature_set arm_cext_iwmmxt
=
249 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
250 static const arm_feature_set arm_cext_xscale
=
251 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
252 static const arm_feature_set arm_cext_maverick
=
253 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
254 static const arm_feature_set fpu_fpa_ext_v1
=
255 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
256 static const arm_feature_set fpu_fpa_ext_v2
=
257 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
258 static const arm_feature_set fpu_vfp_ext_v1xd
=
259 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
260 static const arm_feature_set fpu_vfp_ext_v1
=
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
262 static const arm_feature_set fpu_vfp_ext_v2
=
263 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
264 static const arm_feature_set fpu_vfp_ext_v3xd
=
265 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
266 static const arm_feature_set fpu_vfp_ext_v3
=
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
268 static const arm_feature_set fpu_vfp_ext_d32
=
269 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
270 static const arm_feature_set fpu_neon_ext_v1
=
271 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
272 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
273 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
275 static const arm_feature_set fpu_vfp_fp16
=
276 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
277 static const arm_feature_set fpu_neon_ext_fma
=
278 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
280 static const arm_feature_set fpu_vfp_ext_fma
=
281 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
282 static const arm_feature_set fpu_vfp_ext_armv8
=
283 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
284 static const arm_feature_set fpu_vfp_ext_armv8xd
=
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
286 static const arm_feature_set fpu_neon_ext_armv8
=
287 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
288 static const arm_feature_set fpu_crypto_ext_armv8
=
289 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
290 static const arm_feature_set crc_ext_armv8
=
291 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
292 static const arm_feature_set fpu_neon_ext_v8_1
=
293 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
295 static int mfloat_abi_opt
= -1;
296 /* Record user cpu selection for object attributes. */
297 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
298 /* Must be long enough to hold any of the names in arm_cpus. */
299 static char selected_cpu_name
[20];
301 extern FLONUM_TYPE generic_floating_point_number
;
303 /* Return if no cpu was selected on command-line. */
305 no_cpu_selected (void)
307 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
312 static int meabi_flags
= EABI_DEFAULT
;
314 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
317 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
322 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
327 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
328 symbolS
* GOT_symbol
;
331 /* 0: assemble for ARM,
332 1: assemble for Thumb,
333 2: assemble for Thumb even though target CPU does not support thumb
335 static int thumb_mode
= 0;
336 /* A value distinct from the possible values for thumb_mode that we
337 can use to record whether thumb_mode has been copied into the
338 tc_frag_data field of a frag. */
339 #define MODE_RECORDED (1 << 4)
341 /* Specifies the intrinsic IT insn behavior mode. */
342 enum implicit_it_mode
344 IMPLICIT_IT_MODE_NEVER
= 0x00,
345 IMPLICIT_IT_MODE_ARM
= 0x01,
346 IMPLICIT_IT_MODE_THUMB
= 0x02,
347 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
349 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
351 /* If unified_syntax is true, we are processing the new unified
352 ARM/Thumb syntax. Important differences from the old ARM mode:
354 - Immediate operands do not require a # prefix.
355 - Conditional affixes always appear at the end of the
356 instruction. (For backward compatibility, those instructions
357 that formerly had them in the middle, continue to accept them
359 - The IT instruction may appear, and if it does is validated
360 against subsequent conditional affixes. It does not generate
363 Important differences from the old Thumb mode:
365 - Immediate operands do not require a # prefix.
366 - Most of the V6T2 instructions are only available in unified mode.
367 - The .N and .W suffixes are recognized and honored (it is an error
368 if they cannot be honored).
369 - All instructions set the flags if and only if they have an 's' affix.
370 - Conditional affixes may be used. They are validated against
371 preceding IT instructions. Unlike ARM mode, you cannot use a
372 conditional affix except in the scope of an IT instruction. */
374 static bfd_boolean unified_syntax
= FALSE
;
376 /* An immediate operand can start with #, and ld*, st*, pld operands
377 can contain [ and ]. We need to tell APP not to elide whitespace
378 before a [, which can appear as the first operand for pld.
379 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
380 const char arm_symbol_chars
[] = "#[]{}";
395 enum neon_el_type type
;
399 #define NEON_MAX_TYPE_ELS 4
403 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
407 enum it_instruction_type
412 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
413 if inside, should be the last one. */
414 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
415 i.e. BKPT and NOP. */
416 IT_INSN
/* The IT insn has been parsed. */
419 /* The maximum number of operands we need. */
420 #define ARM_IT_MAX_OPERANDS 6
425 unsigned long instruction
;
429 /* "uncond_value" is set to the value in place of the conditional field in
430 unconditional versions of the instruction, or -1 if nothing is
433 struct neon_type vectype
;
434 /* This does not indicate an actual NEON instruction, only that
435 the mnemonic accepts neon-style type suffixes. */
437 /* Set to the opcode if the instruction needs relaxation.
438 Zero if the instruction is not relaxed. */
442 bfd_reloc_code_real_type type
;
447 enum it_instruction_type it_insn_type
;
453 struct neon_type_el vectype
;
454 unsigned present
: 1; /* Operand present. */
455 unsigned isreg
: 1; /* Operand was a register. */
456 unsigned immisreg
: 1; /* .imm field is a second register. */
457 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
458 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
459 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
460 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
461 instructions. This allows us to disambiguate ARM <-> vector insns. */
462 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
463 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
464 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
465 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
466 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
467 unsigned writeback
: 1; /* Operand has trailing ! */
468 unsigned preind
: 1; /* Preindexed address. */
469 unsigned postind
: 1; /* Postindexed address. */
470 unsigned negative
: 1; /* Index register was negated. */
471 unsigned shifted
: 1; /* Shift applied to operation. */
472 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
473 } operands
[ARM_IT_MAX_OPERANDS
];
476 static struct arm_it inst
;
478 #define NUM_FLOAT_VALS 8
480 const char * fp_const
[] =
482 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
485 /* Number of littlenums required to hold an extended precision number. */
486 #define MAX_LITTLENUMS 6
488 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
498 #define CP_T_X 0x00008000
499 #define CP_T_Y 0x00400000
501 #define CONDS_BIT 0x00100000
502 #define LOAD_BIT 0x00100000
504 #define DOUBLE_LOAD_FLAG 0x00000001
508 const char * template_name
;
512 #define COND_ALWAYS 0xE
516 const char * template_name
;
520 struct asm_barrier_opt
522 const char * template_name
;
524 const arm_feature_set arch
;
527 /* The bit that distinguishes CPSR and SPSR. */
528 #define SPSR_BIT (1 << 22)
530 /* The individual PSR flag bits. */
531 #define PSR_c (1 << 16)
532 #define PSR_x (1 << 17)
533 #define PSR_s (1 << 18)
534 #define PSR_f (1 << 19)
539 bfd_reloc_code_real_type reloc
;
544 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
545 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
550 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
553 /* Bits for DEFINED field in neon_typed_alias. */
554 #define NTA_HASTYPE 1
555 #define NTA_HASINDEX 2
557 struct neon_typed_alias
559 unsigned char defined
;
561 struct neon_type_el eltype
;
564 /* ARM register categories. This includes coprocessor numbers and various
565 architecture extensions' registers. */
592 /* Structure for a hash table entry for a register.
593 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
594 information which states whether a vector type or index is specified (for a
595 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
601 unsigned char builtin
;
602 struct neon_typed_alias
* neon
;
605 /* Diagnostics used when we don't get a register of the expected type. */
606 const char * const reg_expected_msgs
[] =
608 N_("ARM register expected"),
609 N_("bad or missing co-processor number"),
610 N_("co-processor register expected"),
611 N_("FPA register expected"),
612 N_("VFP single precision register expected"),
613 N_("VFP/Neon double precision register expected"),
614 N_("Neon quad precision register expected"),
615 N_("VFP single or double precision register expected"),
616 N_("Neon double or quad precision register expected"),
617 N_("VFP single, double or Neon quad precision register expected"),
618 N_("VFP system register expected"),
619 N_("Maverick MVF register expected"),
620 N_("Maverick MVD register expected"),
621 N_("Maverick MVFX register expected"),
622 N_("Maverick MVDX register expected"),
623 N_("Maverick MVAX register expected"),
624 N_("Maverick DSPSC register expected"),
625 N_("iWMMXt data register expected"),
626 N_("iWMMXt control register expected"),
627 N_("iWMMXt scalar register expected"),
628 N_("XScale accumulator register expected"),
631 /* Some well known registers that we refer to directly elsewhere. */
637 /* ARM instructions take 4bytes in the object file, Thumb instructions
643 /* Basic string to match. */
644 const char * template_name
;
646 /* Parameters to instruction. */
647 unsigned int operands
[8];
649 /* Conditional tag - see opcode_lookup. */
650 unsigned int tag
: 4;
652 /* Basic instruction code. */
653 unsigned int avalue
: 28;
655 /* Thumb-format instruction code. */
658 /* Which architecture variant provides this instruction. */
659 const arm_feature_set
* avariant
;
660 const arm_feature_set
* tvariant
;
662 /* Function to call to encode instruction in ARM format. */
663 void (* aencode
) (void);
665 /* Function to call to encode instruction in Thumb format. */
666 void (* tencode
) (void);
669 /* Defines for various bits that we will want to toggle. */
670 #define INST_IMMEDIATE 0x02000000
671 #define OFFSET_REG 0x02000000
672 #define HWOFFSET_IMM 0x00400000
673 #define SHIFT_BY_REG 0x00000010
674 #define PRE_INDEX 0x01000000
675 #define INDEX_UP 0x00800000
676 #define WRITE_BACK 0x00200000
677 #define LDM_TYPE_2_OR_3 0x00400000
678 #define CPSI_MMOD 0x00020000
680 #define LITERAL_MASK 0xf000f000
681 #define OPCODE_MASK 0xfe1fffff
682 #define V4_STR_BIT 0x00000020
683 #define VLDR_VMOV_SAME 0x0040f000
685 #define T2_SUBS_PC_LR 0xf3de8f00
687 #define DATA_OP_SHIFT 21
689 #define T2_OPCODE_MASK 0xfe1fffff
690 #define T2_DATA_OP_SHIFT 21
692 #define A_COND_MASK 0xf0000000
693 #define A_PUSH_POP_OP_MASK 0x0fff0000
695 /* Opcodes for pushing/poping registers to/from the stack. */
696 #define A1_OPCODE_PUSH 0x092d0000
697 #define A2_OPCODE_PUSH 0x052d0004
698 #define A2_OPCODE_POP 0x049d0004
700 /* Codes to distinguish the arithmetic instructions. */
711 #define OPCODE_CMP 10
712 #define OPCODE_CMN 11
713 #define OPCODE_ORR 12
714 #define OPCODE_MOV 13
715 #define OPCODE_BIC 14
716 #define OPCODE_MVN 15
718 #define T2_OPCODE_AND 0
719 #define T2_OPCODE_BIC 1
720 #define T2_OPCODE_ORR 2
721 #define T2_OPCODE_ORN 3
722 #define T2_OPCODE_EOR 4
723 #define T2_OPCODE_ADD 8
724 #define T2_OPCODE_ADC 10
725 #define T2_OPCODE_SBC 11
726 #define T2_OPCODE_SUB 13
727 #define T2_OPCODE_RSB 14
729 #define T_OPCODE_MUL 0x4340
730 #define T_OPCODE_TST 0x4200
731 #define T_OPCODE_CMN 0x42c0
732 #define T_OPCODE_NEG 0x4240
733 #define T_OPCODE_MVN 0x43c0
735 #define T_OPCODE_ADD_R3 0x1800
736 #define T_OPCODE_SUB_R3 0x1a00
737 #define T_OPCODE_ADD_HI 0x4400
738 #define T_OPCODE_ADD_ST 0xb000
739 #define T_OPCODE_SUB_ST 0xb080
740 #define T_OPCODE_ADD_SP 0xa800
741 #define T_OPCODE_ADD_PC 0xa000
742 #define T_OPCODE_ADD_I8 0x3000
743 #define T_OPCODE_SUB_I8 0x3800
744 #define T_OPCODE_ADD_I3 0x1c00
745 #define T_OPCODE_SUB_I3 0x1e00
747 #define T_OPCODE_ASR_R 0x4100
748 #define T_OPCODE_LSL_R 0x4080
749 #define T_OPCODE_LSR_R 0x40c0
750 #define T_OPCODE_ROR_R 0x41c0
751 #define T_OPCODE_ASR_I 0x1000
752 #define T_OPCODE_LSL_I 0x0000
753 #define T_OPCODE_LSR_I 0x0800
755 #define T_OPCODE_MOV_I8 0x2000
756 #define T_OPCODE_CMP_I8 0x2800
757 #define T_OPCODE_CMP_LR 0x4280
758 #define T_OPCODE_MOV_HR 0x4600
759 #define T_OPCODE_CMP_HR 0x4500
761 #define T_OPCODE_LDR_PC 0x4800
762 #define T_OPCODE_LDR_SP 0x9800
763 #define T_OPCODE_STR_SP 0x9000
764 #define T_OPCODE_LDR_IW 0x6800
765 #define T_OPCODE_STR_IW 0x6000
766 #define T_OPCODE_LDR_IH 0x8800
767 #define T_OPCODE_STR_IH 0x8000
768 #define T_OPCODE_LDR_IB 0x7800
769 #define T_OPCODE_STR_IB 0x7000
770 #define T_OPCODE_LDR_RW 0x5800
771 #define T_OPCODE_STR_RW 0x5000
772 #define T_OPCODE_LDR_RH 0x5a00
773 #define T_OPCODE_STR_RH 0x5200
774 #define T_OPCODE_LDR_RB 0x5c00
775 #define T_OPCODE_STR_RB 0x5400
777 #define T_OPCODE_PUSH 0xb400
778 #define T_OPCODE_POP 0xbc00
780 #define T_OPCODE_BRANCH 0xe000
782 #define THUMB_SIZE 2 /* Size of thumb instruction. */
783 #define THUMB_PP_PC_LR 0x0100
784 #define THUMB_LOAD_BIT 0x0800
785 #define THUMB2_LOAD_BIT 0x00100000
787 #define BAD_ARGS _("bad arguments to instruction")
788 #define BAD_SP _("r13 not allowed here")
789 #define BAD_PC _("r15 not allowed here")
790 #define BAD_COND _("instruction cannot be conditional")
791 #define BAD_OVERLAP _("registers may not be the same")
792 #define BAD_HIREG _("lo register required")
793 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
794 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
795 #define BAD_BRANCH _("branch must be last instruction in IT block")
796 #define BAD_NOT_IT _("instruction not allowed in IT block")
797 #define BAD_FPU _("selected FPU does not support instruction")
798 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
799 #define BAD_IT_COND _("incorrect condition in IT block")
800 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
801 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
802 #define BAD_PC_ADDRESSING \
803 _("cannot use register index with PC-relative addressing")
804 #define BAD_PC_WRITEBACK \
805 _("cannot use writeback with PC-relative addressing")
806 #define BAD_RANGE _("branch out of range")
807 #define BAD_FP16 _("selected processor does not support fp16 instruction")
808 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
809 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
811 static struct hash_control
* arm_ops_hsh
;
812 static struct hash_control
* arm_cond_hsh
;
813 static struct hash_control
* arm_shift_hsh
;
814 static struct hash_control
* arm_psr_hsh
;
815 static struct hash_control
* arm_v7m_psr_hsh
;
816 static struct hash_control
* arm_reg_hsh
;
817 static struct hash_control
* arm_reloc_hsh
;
818 static struct hash_control
* arm_barrier_opt_hsh
;
820 /* Stuff needed to resolve the label ambiguity
829 symbolS
* last_label_seen
;
830 static int label_is_thumb_function_name
= FALSE
;
832 /* Literal pool structure. Held on a per-section
833 and per-sub-section basis. */
835 #define MAX_LITERAL_POOL_SIZE 1024
836 typedef struct literal_pool
838 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
839 unsigned int next_free_entry
;
845 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
847 struct literal_pool
* next
;
848 unsigned int alignment
;
851 /* Pointer to a linked list of literal pools. */
852 literal_pool
* list_of_pools
= NULL
;
854 typedef enum asmfunc_states
857 WAITING_ASMFUNC_NAME
,
861 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
864 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
866 static struct current_it now_it
;
870 now_it_compatible (int cond
)
872 return (cond
& ~1) == (now_it
.cc
& ~1);
876 conditional_insn (void)
878 return inst
.cond
!= COND_ALWAYS
;
881 static int in_it_block (void);
883 static int handle_it_state (void);
885 static void force_automatic_it_block_close (void);
887 static void it_fsm_post_encode (void);
889 #define set_it_insn_type(type) \
892 inst.it_insn_type = type; \
893 if (handle_it_state () == FAIL) \
898 #define set_it_insn_type_nonvoid(type, failret) \
901 inst.it_insn_type = type; \
902 if (handle_it_state () == FAIL) \
907 #define set_it_insn_type_last() \
910 if (inst.cond == COND_ALWAYS) \
911 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
913 set_it_insn_type (INSIDE_IT_LAST_INSN); \
919 /* This array holds the chars that always start a comment. If the
920 pre-processor is disabled, these aren't very useful. */
921 char arm_comment_chars
[] = "@";
923 /* This array holds the chars that only start a comment at the beginning of
924 a line. If the line seems to have the form '# 123 filename'
925 .line and .file directives will appear in the pre-processed output. */
926 /* Note that input_file.c hand checks for '#' at the beginning of the
927 first line of the input file. This is because the compiler outputs
928 #NO_APP at the beginning of its output. */
929 /* Also note that comments like this one will always work. */
930 const char line_comment_chars
[] = "#";
932 char arm_line_separator_chars
[] = ";";
934 /* Chars that can be used to separate mant
935 from exp in floating point numbers. */
936 const char EXP_CHARS
[] = "eE";
938 /* Chars that mean this number is a floating point constant. */
942 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
944 /* Prefix characters that indicate the start of an immediate
946 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
948 /* Separator character handling. */
950 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
953 skip_past_char (char ** str
, char c
)
955 /* PR gas/14987: Allow for whitespace before the expected character. */
956 skip_whitespace (*str
);
967 #define skip_past_comma(str) skip_past_char (str, ',')
969 /* Arithmetic expressions (possibly involving symbols). */
971 /* Return TRUE if anything in the expression is a bignum. */
974 walk_no_bignums (symbolS
* sp
)
976 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
979 if (symbol_get_value_expression (sp
)->X_add_symbol
)
981 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
982 || (symbol_get_value_expression (sp
)->X_op_symbol
983 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
989 static int in_my_get_expression
= 0;
991 /* Third argument to my_get_expression. */
992 #define GE_NO_PREFIX 0
993 #define GE_IMM_PREFIX 1
994 #define GE_OPT_PREFIX 2
995 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
996 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
997 #define GE_OPT_PREFIX_BIG 3
1000 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1005 /* In unified syntax, all prefixes are optional. */
1007 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1010 switch (prefix_mode
)
1012 case GE_NO_PREFIX
: break;
1014 if (!is_immediate_prefix (**str
))
1016 inst
.error
= _("immediate expression requires a # prefix");
1022 case GE_OPT_PREFIX_BIG
:
1023 if (is_immediate_prefix (**str
))
1029 memset (ep
, 0, sizeof (expressionS
));
1031 save_in
= input_line_pointer
;
1032 input_line_pointer
= *str
;
1033 in_my_get_expression
= 1;
1034 seg
= expression (ep
);
1035 in_my_get_expression
= 0;
1037 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1039 /* We found a bad or missing expression in md_operand(). */
1040 *str
= input_line_pointer
;
1041 input_line_pointer
= save_in
;
1042 if (inst
.error
== NULL
)
1043 inst
.error
= (ep
->X_op
== O_absent
1044 ? _("missing expression") :_("bad expression"));
1049 if (seg
!= absolute_section
1050 && seg
!= text_section
1051 && seg
!= data_section
1052 && seg
!= bss_section
1053 && seg
!= undefined_section
)
1055 inst
.error
= _("bad segment");
1056 *str
= input_line_pointer
;
1057 input_line_pointer
= save_in
;
1064 /* Get rid of any bignums now, so that we don't generate an error for which
1065 we can't establish a line number later on. Big numbers are never valid
1066 in instructions, which is where this routine is always called. */
1067 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1068 && (ep
->X_op
== O_big
1069 || (ep
->X_add_symbol
1070 && (walk_no_bignums (ep
->X_add_symbol
)
1072 && walk_no_bignums (ep
->X_op_symbol
))))))
1074 inst
.error
= _("invalid constant");
1075 *str
= input_line_pointer
;
1076 input_line_pointer
= save_in
;
1080 *str
= input_line_pointer
;
1081 input_line_pointer
= save_in
;
1085 /* Turn a string in input_line_pointer into a floating point constant
1086 of type TYPE, and store the appropriate bytes in *LITP. The number
1087 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1088 returned, or NULL on OK.
1090 Note that fp constants aren't represent in the normal way on the ARM.
1091 In big endian mode, things are as expected. However, in little endian
1092 mode fp constants are big-endian word-wise, and little-endian byte-wise
1093 within the words. For example, (double) 1.1 in big endian mode is
1094 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1095 the byte sequence 99 99 f1 3f 9a 99 99 99.
1097 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1100 md_atof (int type
, char * litP
, int * sizeP
)
1103 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1135 return _("Unrecognized or unsupported floating point constant");
1138 t
= atof_ieee (input_line_pointer
, type
, words
);
1140 input_line_pointer
= t
;
1141 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1143 if (target_big_endian
)
1145 for (i
= 0; i
< prec
; i
++)
1147 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1148 litP
+= sizeof (LITTLENUM_TYPE
);
1153 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1154 for (i
= prec
- 1; i
>= 0; i
--)
1156 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1157 litP
+= sizeof (LITTLENUM_TYPE
);
1160 /* For a 4 byte float the order of elements in `words' is 1 0.
1161 For an 8 byte float the order is 1 0 3 2. */
1162 for (i
= 0; i
< prec
; i
+= 2)
1164 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1165 sizeof (LITTLENUM_TYPE
));
1166 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1167 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1168 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1175 /* We handle all bad expressions here, so that we can report the faulty
1176 instruction in the error message. */
1178 md_operand (expressionS
* exp
)
1180 if (in_my_get_expression
)
1181 exp
->X_op
= O_illegal
;
1184 /* Immediate values. */
1186 /* Generic immediate-value read function for use in directives.
1187 Accepts anything that 'expression' can fold to a constant.
1188 *val receives the number. */
1191 immediate_for_directive (int *val
)
1194 exp
.X_op
= O_illegal
;
1196 if (is_immediate_prefix (*input_line_pointer
))
1198 input_line_pointer
++;
1202 if (exp
.X_op
!= O_constant
)
1204 as_bad (_("expected #constant"));
1205 ignore_rest_of_line ();
1208 *val
= exp
.X_add_number
;
1213 /* Register parsing. */
1215 /* Generic register parser. CCP points to what should be the
1216 beginning of a register name. If it is indeed a valid register
1217 name, advance CCP over it and return the reg_entry structure;
1218 otherwise return NULL. Does not issue diagnostics. */
1220 static struct reg_entry
*
1221 arm_reg_parse_multi (char **ccp
)
1225 struct reg_entry
*reg
;
1227 skip_whitespace (start
);
1229 #ifdef REGISTER_PREFIX
1230 if (*start
!= REGISTER_PREFIX
)
1234 #ifdef OPTIONAL_REGISTER_PREFIX
1235 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1240 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1245 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1247 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1257 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1258 enum arm_reg_type type
)
1260 /* Alternative syntaxes are accepted for a few register classes. */
1267 /* Generic coprocessor register names are allowed for these. */
1268 if (reg
&& reg
->type
== REG_TYPE_CN
)
1273 /* For backward compatibility, a bare number is valid here. */
1275 unsigned long processor
= strtoul (start
, ccp
, 10);
1276 if (*ccp
!= start
&& processor
<= 15)
1280 case REG_TYPE_MMXWC
:
1281 /* WC includes WCG. ??? I'm not sure this is true for all
1282 instructions that take WC registers. */
1283 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1294 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1295 return value is the register number or FAIL. */
1298 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1301 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1304 /* Do not allow a scalar (reg+index) to parse as a register. */
1305 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1308 if (reg
&& reg
->type
== type
)
1311 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1318 /* Parse a Neon type specifier. *STR should point at the leading '.'
1319 character. Does no verification at this stage that the type fits the opcode
1326 Can all be legally parsed by this function.
1328 Fills in neon_type struct pointer with parsed information, and updates STR
1329 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1330 type, FAIL if not. */
1333 parse_neon_type (struct neon_type
*type
, char **str
)
1340 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1342 enum neon_el_type thistype
= NT_untyped
;
1343 unsigned thissize
= -1u;
1350 /* Just a size without an explicit type. */
1354 switch (TOLOWER (*ptr
))
1356 case 'i': thistype
= NT_integer
; break;
1357 case 'f': thistype
= NT_float
; break;
1358 case 'p': thistype
= NT_poly
; break;
1359 case 's': thistype
= NT_signed
; break;
1360 case 'u': thistype
= NT_unsigned
; break;
1362 thistype
= NT_float
;
1367 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1373 /* .f is an abbreviation for .f32. */
1374 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1379 thissize
= strtoul (ptr
, &ptr
, 10);
1381 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1384 as_bad (_("bad size %d in type specifier"), thissize
);
1392 type
->el
[type
->elems
].type
= thistype
;
1393 type
->el
[type
->elems
].size
= thissize
;
1398 /* Empty/missing type is not a successful parse. */
1399 if (type
->elems
== 0)
1407 /* Errors may be set multiple times during parsing or bit encoding
1408 (particularly in the Neon bits), but usually the earliest error which is set
1409 will be the most meaningful. Avoid overwriting it with later (cascading)
1410 errors by calling this function. */
1413 first_error (const char *err
)
1419 /* Parse a single type, e.g. ".s32", leading period included. */
1421 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1424 struct neon_type optype
;
1428 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1430 if (optype
.elems
== 1)
1431 *vectype
= optype
.el
[0];
1434 first_error (_("only one type should be specified for operand"));
1440 first_error (_("vector type expected"));
1452 /* Special meanings for indices (which have a range of 0-7), which will fit into
1455 #define NEON_ALL_LANES 15
1456 #define NEON_INTERLEAVE_LANES 14
1458 /* Parse either a register or a scalar, with an optional type. Return the
1459 register number, and optionally fill in the actual type of the register
1460 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1461 type/index information in *TYPEINFO. */
1464 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1465 enum arm_reg_type
*rtype
,
1466 struct neon_typed_alias
*typeinfo
)
1469 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1470 struct neon_typed_alias atype
;
1471 struct neon_type_el parsetype
;
1475 atype
.eltype
.type
= NT_invtype
;
1476 atype
.eltype
.size
= -1;
1478 /* Try alternate syntax for some types of register. Note these are mutually
1479 exclusive with the Neon syntax extensions. */
1482 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1490 /* Undo polymorphism when a set of register types may be accepted. */
1491 if ((type
== REG_TYPE_NDQ
1492 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1493 || (type
== REG_TYPE_VFSD
1494 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1495 || (type
== REG_TYPE_NSDQ
1496 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1497 || reg
->type
== REG_TYPE_NQ
))
1498 || (type
== REG_TYPE_MMXWC
1499 && (reg
->type
== REG_TYPE_MMXWCG
)))
1500 type
= (enum arm_reg_type
) reg
->type
;
1502 if (type
!= reg
->type
)
1508 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1510 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1512 first_error (_("can't redefine type for operand"));
1515 atype
.defined
|= NTA_HASTYPE
;
1516 atype
.eltype
= parsetype
;
1519 if (skip_past_char (&str
, '[') == SUCCESS
)
1521 if (type
!= REG_TYPE_VFD
)
1523 first_error (_("only D registers may be indexed"));
1527 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1529 first_error (_("can't change index for operand"));
1533 atype
.defined
|= NTA_HASINDEX
;
1535 if (skip_past_char (&str
, ']') == SUCCESS
)
1536 atype
.index
= NEON_ALL_LANES
;
1541 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1543 if (exp
.X_op
!= O_constant
)
1545 first_error (_("constant expression required"));
1549 if (skip_past_char (&str
, ']') == FAIL
)
1552 atype
.index
= exp
.X_add_number
;
1567 /* Like arm_reg_parse, but allow allow the following extra features:
1568 - If RTYPE is non-zero, return the (possibly restricted) type of the
1569 register (e.g. Neon double or quad reg when either has been requested).
1570 - If this is a Neon vector type with additional type information, fill
1571 in the struct pointed to by VECTYPE (if non-NULL).
1572 This function will fault on encountering a scalar. */
1575 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1576 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1578 struct neon_typed_alias atype
;
1580 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1585 /* Do not allow regname(... to parse as a register. */
1589 /* Do not allow a scalar (reg+index) to parse as a register. */
1590 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1592 first_error (_("register operand expected, but got scalar"));
1597 *vectype
= atype
.eltype
;
1604 #define NEON_SCALAR_REG(X) ((X) >> 4)
1605 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1607 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1608 have enough information to be able to do a good job bounds-checking. So, we
1609 just do easy checks here, and do further checks later. */
1612 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1616 struct neon_typed_alias atype
;
1618 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1620 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1623 if (atype
.index
== NEON_ALL_LANES
)
1625 first_error (_("scalar must have an index"));
1628 else if (atype
.index
>= 64 / elsize
)
1630 first_error (_("scalar index out of range"));
1635 *type
= atype
.eltype
;
1639 return reg
* 16 + atype
.index
;
1642 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1645 parse_reg_list (char ** strp
)
1647 char * str
= * strp
;
1651 /* We come back here if we get ranges concatenated by '+' or '|'. */
1654 skip_whitespace (str
);
1668 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1670 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1680 first_error (_("bad range in register list"));
1684 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1686 if (range
& (1 << i
))
1688 (_("Warning: duplicated register (r%d) in register list"),
1696 if (range
& (1 << reg
))
1697 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1699 else if (reg
<= cur_reg
)
1700 as_tsktsk (_("Warning: register range not in ascending order"));
1705 while (skip_past_comma (&str
) != FAIL
1706 || (in_range
= 1, *str
++ == '-'));
1709 if (skip_past_char (&str
, '}') == FAIL
)
1711 first_error (_("missing `}'"));
1719 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1722 if (exp
.X_op
== O_constant
)
1724 if (exp
.X_add_number
1725 != (exp
.X_add_number
& 0x0000ffff))
1727 inst
.error
= _("invalid register mask");
1731 if ((range
& exp
.X_add_number
) != 0)
1733 int regno
= range
& exp
.X_add_number
;
1736 regno
= (1 << regno
) - 1;
1738 (_("Warning: duplicated register (r%d) in register list"),
1742 range
|= exp
.X_add_number
;
1746 if (inst
.reloc
.type
!= 0)
1748 inst
.error
= _("expression too complex");
1752 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1753 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1754 inst
.reloc
.pc_rel
= 0;
1758 if (*str
== '|' || *str
== '+')
1764 while (another_range
);
1770 /* Types of registers in a list. */
1779 /* Parse a VFP register list. If the string is invalid return FAIL.
1780 Otherwise return the number of registers, and set PBASE to the first
1781 register. Parses registers of type ETYPE.
1782 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1783 - Q registers can be used to specify pairs of D registers
1784 - { } can be omitted from around a singleton register list
1785 FIXME: This is not implemented, as it would require backtracking in
1788 This could be done (the meaning isn't really ambiguous), but doesn't
1789 fit in well with the current parsing framework.
1790 - 32 D registers may be used (also true for VFPv3).
1791 FIXME: Types are ignored in these register lists, which is probably a
1795 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1800 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1804 unsigned long mask
= 0;
1807 if (skip_past_char (&str
, '{') == FAIL
)
1809 inst
.error
= _("expecting {");
1816 regtype
= REG_TYPE_VFS
;
1821 regtype
= REG_TYPE_VFD
;
1824 case REGLIST_NEON_D
:
1825 regtype
= REG_TYPE_NDQ
;
1829 if (etype
!= REGLIST_VFP_S
)
1831 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1832 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1836 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1839 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1846 base_reg
= max_regs
;
1850 int setmask
= 1, addregs
= 1;
1852 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1854 if (new_base
== FAIL
)
1856 first_error (_(reg_expected_msgs
[regtype
]));
1860 if (new_base
>= max_regs
)
1862 first_error (_("register out of range in list"));
1866 /* Note: a value of 2 * n is returned for the register Q<n>. */
1867 if (regtype
== REG_TYPE_NQ
)
1873 if (new_base
< base_reg
)
1874 base_reg
= new_base
;
1876 if (mask
& (setmask
<< new_base
))
1878 first_error (_("invalid register list"));
1882 if ((mask
>> new_base
) != 0 && ! warned
)
1884 as_tsktsk (_("register list not in ascending order"));
1888 mask
|= setmask
<< new_base
;
1891 if (*str
== '-') /* We have the start of a range expression */
1897 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1900 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1904 if (high_range
>= max_regs
)
1906 first_error (_("register out of range in list"));
1910 if (regtype
== REG_TYPE_NQ
)
1911 high_range
= high_range
+ 1;
1913 if (high_range
<= new_base
)
1915 inst
.error
= _("register range not in ascending order");
1919 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1921 if (mask
& (setmask
<< new_base
))
1923 inst
.error
= _("invalid register list");
1927 mask
|= setmask
<< new_base
;
1932 while (skip_past_comma (&str
) != FAIL
);
1936 /* Sanity check -- should have raised a parse error above. */
1937 if (count
== 0 || count
> max_regs
)
1942 /* Final test -- the registers must be consecutive. */
1944 for (i
= 0; i
< count
; i
++)
1946 if ((mask
& (1u << i
)) == 0)
1948 inst
.error
= _("non-contiguous register range");
1958 /* True if two alias types are the same. */
1961 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1969 if (a
->defined
!= b
->defined
)
1972 if ((a
->defined
& NTA_HASTYPE
) != 0
1973 && (a
->eltype
.type
!= b
->eltype
.type
1974 || a
->eltype
.size
!= b
->eltype
.size
))
1977 if ((a
->defined
& NTA_HASINDEX
) != 0
1978 && (a
->index
!= b
->index
))
1984 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1985 The base register is put in *PBASE.
1986 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1988 The register stride (minus one) is put in bit 4 of the return value.
1989 Bits [6:5] encode the list length (minus one).
1990 The type of the list elements is put in *ELTYPE, if non-NULL. */
1992 #define NEON_LANE(X) ((X) & 0xf)
1993 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1994 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1997 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1998 struct neon_type_el
*eltype
)
2005 int leading_brace
= 0;
2006 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2007 const char *const incr_error
= _("register stride must be 1 or 2");
2008 const char *const type_error
= _("mismatched element/structure types in list");
2009 struct neon_typed_alias firsttype
;
2010 firsttype
.defined
= 0;
2011 firsttype
.eltype
.type
= NT_invtype
;
2012 firsttype
.eltype
.size
= -1;
2013 firsttype
.index
= -1;
2015 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2020 struct neon_typed_alias atype
;
2021 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2025 first_error (_(reg_expected_msgs
[rtype
]));
2032 if (rtype
== REG_TYPE_NQ
)
2038 else if (reg_incr
== -1)
2040 reg_incr
= getreg
- base_reg
;
2041 if (reg_incr
< 1 || reg_incr
> 2)
2043 first_error (_(incr_error
));
2047 else if (getreg
!= base_reg
+ reg_incr
* count
)
2049 first_error (_(incr_error
));
2053 if (! neon_alias_types_same (&atype
, &firsttype
))
2055 first_error (_(type_error
));
2059 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2063 struct neon_typed_alias htype
;
2064 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2066 lane
= NEON_INTERLEAVE_LANES
;
2067 else if (lane
!= NEON_INTERLEAVE_LANES
)
2069 first_error (_(type_error
));
2074 else if (reg_incr
!= 1)
2076 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2080 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2083 first_error (_(reg_expected_msgs
[rtype
]));
2086 if (! neon_alias_types_same (&htype
, &firsttype
))
2088 first_error (_(type_error
));
2091 count
+= hireg
+ dregs
- getreg
;
2095 /* If we're using Q registers, we can't use [] or [n] syntax. */
2096 if (rtype
== REG_TYPE_NQ
)
2102 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2106 else if (lane
!= atype
.index
)
2108 first_error (_(type_error
));
2112 else if (lane
== -1)
2113 lane
= NEON_INTERLEAVE_LANES
;
2114 else if (lane
!= NEON_INTERLEAVE_LANES
)
2116 first_error (_(type_error
));
2121 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2123 /* No lane set by [x]. We must be interleaving structures. */
2125 lane
= NEON_INTERLEAVE_LANES
;
2128 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2129 || (count
> 1 && reg_incr
== -1))
2131 first_error (_("error parsing element/structure list"));
2135 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2137 first_error (_("expected }"));
2145 *eltype
= firsttype
.eltype
;
2150 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2153 /* Parse an explicit relocation suffix on an expression. This is
2154 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2155 arm_reloc_hsh contains no entries, so this function can only
2156 succeed if there is no () after the word. Returns -1 on error,
2157 BFD_RELOC_UNUSED if there wasn't any suffix. */
2160 parse_reloc (char **str
)
2162 struct reloc_entry
*r
;
2166 return BFD_RELOC_UNUSED
;
2171 while (*q
&& *q
!= ')' && *q
!= ',')
2176 if ((r
= (struct reloc_entry
*)
2177 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2184 /* Directives: register aliases. */
2186 static struct reg_entry
*
2187 insert_reg_alias (char *str
, unsigned number
, int type
)
2189 struct reg_entry
*new_reg
;
2192 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2194 if (new_reg
->builtin
)
2195 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2197 /* Only warn about a redefinition if it's not defined as the
2199 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2200 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2205 name
= xstrdup (str
);
2206 new_reg
= XNEW (struct reg_entry
);
2208 new_reg
->name
= name
;
2209 new_reg
->number
= number
;
2210 new_reg
->type
= type
;
2211 new_reg
->builtin
= FALSE
;
2212 new_reg
->neon
= NULL
;
2214 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2221 insert_neon_reg_alias (char *str
, int number
, int type
,
2222 struct neon_typed_alias
*atype
)
2224 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2228 first_error (_("attempt to redefine typed alias"));
2234 reg
->neon
= XNEW (struct neon_typed_alias
);
2235 *reg
->neon
= *atype
;
2239 /* Look for the .req directive. This is of the form:
2241 new_register_name .req existing_register_name
2243 If we find one, or if it looks sufficiently like one that we want to
2244 handle any error here, return TRUE. Otherwise return FALSE. */
2247 create_register_alias (char * newname
, char *p
)
2249 struct reg_entry
*old
;
2250 char *oldname
, *nbuf
;
2253 /* The input scrubber ensures that whitespace after the mnemonic is
2254 collapsed to single spaces. */
2256 if (strncmp (oldname
, " .req ", 6) != 0)
2260 if (*oldname
== '\0')
2263 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2266 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2270 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2271 the desired alias name, and p points to its end. If not, then
2272 the desired alias name is in the global original_case_string. */
2273 #ifdef TC_CASE_SENSITIVE
2276 newname
= original_case_string
;
2277 nlen
= strlen (newname
);
2280 nbuf
= xmemdup0 (newname
, nlen
);
2282 /* Create aliases under the new name as stated; an all-lowercase
2283 version of the new name; and an all-uppercase version of the new
2285 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2287 for (p
= nbuf
; *p
; p
++)
2290 if (strncmp (nbuf
, newname
, nlen
))
2292 /* If this attempt to create an additional alias fails, do not bother
2293 trying to create the all-lower case alias. We will fail and issue
2294 a second, duplicate error message. This situation arises when the
2295 programmer does something like:
2298 The second .req creates the "Foo" alias but then fails to create
2299 the artificial FOO alias because it has already been created by the
2301 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2308 for (p
= nbuf
; *p
; p
++)
2311 if (strncmp (nbuf
, newname
, nlen
))
2312 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2319 /* Create a Neon typed/indexed register alias using directives, e.g.:
2324 These typed registers can be used instead of the types specified after the
2325 Neon mnemonic, so long as all operands given have types. Types can also be
2326 specified directly, e.g.:
2327 vadd d0.s32, d1.s32, d2.s32 */
2330 create_neon_reg_alias (char *newname
, char *p
)
2332 enum arm_reg_type basetype
;
2333 struct reg_entry
*basereg
;
2334 struct reg_entry mybasereg
;
2335 struct neon_type ntype
;
2336 struct neon_typed_alias typeinfo
;
2337 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2340 typeinfo
.defined
= 0;
2341 typeinfo
.eltype
.type
= NT_invtype
;
2342 typeinfo
.eltype
.size
= -1;
2343 typeinfo
.index
= -1;
2347 if (strncmp (p
, " .dn ", 5) == 0)
2348 basetype
= REG_TYPE_VFD
;
2349 else if (strncmp (p
, " .qn ", 5) == 0)
2350 basetype
= REG_TYPE_NQ
;
2359 basereg
= arm_reg_parse_multi (&p
);
2361 if (basereg
&& basereg
->type
!= basetype
)
2363 as_bad (_("bad type for register"));
2367 if (basereg
== NULL
)
2370 /* Try parsing as an integer. */
2371 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2372 if (exp
.X_op
!= O_constant
)
2374 as_bad (_("expression must be constant"));
2377 basereg
= &mybasereg
;
2378 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2384 typeinfo
= *basereg
->neon
;
2386 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2388 /* We got a type. */
2389 if (typeinfo
.defined
& NTA_HASTYPE
)
2391 as_bad (_("can't redefine the type of a register alias"));
2395 typeinfo
.defined
|= NTA_HASTYPE
;
2396 if (ntype
.elems
!= 1)
2398 as_bad (_("you must specify a single type only"));
2401 typeinfo
.eltype
= ntype
.el
[0];
2404 if (skip_past_char (&p
, '[') == SUCCESS
)
2407 /* We got a scalar index. */
2409 if (typeinfo
.defined
& NTA_HASINDEX
)
2411 as_bad (_("can't redefine the index of a scalar alias"));
2415 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2417 if (exp
.X_op
!= O_constant
)
2419 as_bad (_("scalar index must be constant"));
2423 typeinfo
.defined
|= NTA_HASINDEX
;
2424 typeinfo
.index
= exp
.X_add_number
;
2426 if (skip_past_char (&p
, ']') == FAIL
)
2428 as_bad (_("expecting ]"));
2433 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2434 the desired alias name, and p points to its end. If not, then
2435 the desired alias name is in the global original_case_string. */
2436 #ifdef TC_CASE_SENSITIVE
2437 namelen
= nameend
- newname
;
2439 newname
= original_case_string
;
2440 namelen
= strlen (newname
);
2443 namebuf
= xmemdup0 (newname
, namelen
);
2445 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2446 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2448 /* Insert name in all uppercase. */
2449 for (p
= namebuf
; *p
; p
++)
2452 if (strncmp (namebuf
, newname
, namelen
))
2453 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2454 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2456 /* Insert name in all lowercase. */
2457 for (p
= namebuf
; *p
; p
++)
2460 if (strncmp (namebuf
, newname
, namelen
))
2461 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2462 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2468 /* Should never be called, as .req goes between the alias and the
2469 register name, not at the beginning of the line. */
2472 s_req (int a ATTRIBUTE_UNUSED
)
2474 as_bad (_("invalid syntax for .req directive"));
2478 s_dn (int a ATTRIBUTE_UNUSED
)
2480 as_bad (_("invalid syntax for .dn directive"));
2484 s_qn (int a ATTRIBUTE_UNUSED
)
2486 as_bad (_("invalid syntax for .qn directive"));
2489 /* The .unreq directive deletes an alias which was previously defined
2490 by .req. For example:
2496 s_unreq (int a ATTRIBUTE_UNUSED
)
2501 name
= input_line_pointer
;
2503 while (*input_line_pointer
!= 0
2504 && *input_line_pointer
!= ' '
2505 && *input_line_pointer
!= '\n')
2506 ++input_line_pointer
;
2508 saved_char
= *input_line_pointer
;
2509 *input_line_pointer
= 0;
2512 as_bad (_("invalid syntax for .unreq directive"));
2515 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2519 as_bad (_("unknown register alias '%s'"), name
);
2520 else if (reg
->builtin
)
2521 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2528 hash_delete (arm_reg_hsh
, name
, FALSE
);
2529 free ((char *) reg
->name
);
2534 /* Also locate the all upper case and all lower case versions.
2535 Do not complain if we cannot find one or the other as it
2536 was probably deleted above. */
2538 nbuf
= strdup (name
);
2539 for (p
= nbuf
; *p
; p
++)
2541 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2544 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2545 free ((char *) reg
->name
);
2551 for (p
= nbuf
; *p
; p
++)
2553 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2556 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2557 free ((char *) reg
->name
);
2567 *input_line_pointer
= saved_char
;
2568 demand_empty_rest_of_line ();
2571 /* Directives: Instruction set selection. */
2574 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2575 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2576 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2577 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2579 /* Create a new mapping symbol for the transition to STATE. */
2582 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2585 const char * symname
;
2592 type
= BSF_NO_FLAGS
;
2596 type
= BSF_NO_FLAGS
;
2600 type
= BSF_NO_FLAGS
;
2606 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2607 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2612 THUMB_SET_FUNC (symbolP
, 0);
2613 ARM_SET_THUMB (symbolP
, 0);
2614 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2618 THUMB_SET_FUNC (symbolP
, 1);
2619 ARM_SET_THUMB (symbolP
, 1);
2620 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2628 /* Save the mapping symbols for future reference. Also check that
2629 we do not place two mapping symbols at the same offset within a
2630 frag. We'll handle overlap between frags in
2631 check_mapping_symbols.
2633 If .fill or other data filling directive generates zero sized data,
2634 the mapping symbol for the following code will have the same value
2635 as the one generated for the data filling directive. In this case,
2636 we replace the old symbol with the new one at the same address. */
2639 if (frag
->tc_frag_data
.first_map
!= NULL
)
2641 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2642 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2644 frag
->tc_frag_data
.first_map
= symbolP
;
2646 if (frag
->tc_frag_data
.last_map
!= NULL
)
2648 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2649 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2650 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2652 frag
->tc_frag_data
.last_map
= symbolP
;
2655 /* We must sometimes convert a region marked as code to data during
2656 code alignment, if an odd number of bytes have to be padded. The
2657 code mapping symbol is pushed to an aligned address. */
2660 insert_data_mapping_symbol (enum mstate state
,
2661 valueT value
, fragS
*frag
, offsetT bytes
)
2663 /* If there was already a mapping symbol, remove it. */
2664 if (frag
->tc_frag_data
.last_map
!= NULL
2665 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2667 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2671 know (frag
->tc_frag_data
.first_map
== symp
);
2672 frag
->tc_frag_data
.first_map
= NULL
;
2674 frag
->tc_frag_data
.last_map
= NULL
;
2675 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2678 make_mapping_symbol (MAP_DATA
, value
, frag
);
2679 make_mapping_symbol (state
, value
+ bytes
, frag
);
2682 static void mapping_state_2 (enum mstate state
, int max_chars
);
2684 /* Set the mapping state to STATE. Only call this when about to
2685 emit some STATE bytes to the file. */
2687 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2689 mapping_state (enum mstate state
)
2691 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2693 if (mapstate
== state
)
2694 /* The mapping symbol has already been emitted.
2695 There is nothing else to do. */
2698 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2700 All ARM instructions require 4-byte alignment.
2701 (Almost) all Thumb instructions require 2-byte alignment.
2703 When emitting instructions into any section, mark the section
2706 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2707 but themselves require 2-byte alignment; this applies to some
2708 PC- relative forms. However, these cases will invovle implicit
2709 literal pool generation or an explicit .align >=2, both of
2710 which will cause the section to me marked with sufficient
2711 alignment. Thus, we don't handle those cases here. */
2712 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2714 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2715 /* This case will be evaluated later. */
2718 mapping_state_2 (state
, 0);
2721 /* Same as mapping_state, but MAX_CHARS bytes have already been
2722 allocated. Put the mapping symbol that far back. */
2725 mapping_state_2 (enum mstate state
, int max_chars
)
2727 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2729 if (!SEG_NORMAL (now_seg
))
2732 if (mapstate
== state
)
2733 /* The mapping symbol has already been emitted.
2734 There is nothing else to do. */
2737 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2738 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2740 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2741 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2744 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2747 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2748 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2752 #define mapping_state(x) ((void)0)
2753 #define mapping_state_2(x, y) ((void)0)
2756 /* Find the real, Thumb encoded start of a Thumb function. */
2760 find_real_start (symbolS
* symbolP
)
2763 const char * name
= S_GET_NAME (symbolP
);
2764 symbolS
* new_target
;
2766 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2767 #define STUB_NAME ".real_start_of"
2772 /* The compiler may generate BL instructions to local labels because
2773 it needs to perform a branch to a far away location. These labels
2774 do not have a corresponding ".real_start_of" label. We check
2775 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2776 the ".real_start_of" convention for nonlocal branches. */
2777 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2780 real_start
= concat (STUB_NAME
, name
, NULL
);
2781 new_target
= symbol_find (real_start
);
2784 if (new_target
== NULL
)
2786 as_warn (_("Failed to find real start of function: %s\n"), name
);
2787 new_target
= symbolP
;
2795 opcode_select (int width
)
2802 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2803 as_bad (_("selected processor does not support THUMB opcodes"));
2806 /* No need to force the alignment, since we will have been
2807 coming from ARM mode, which is word-aligned. */
2808 record_alignment (now_seg
, 1);
2815 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2816 as_bad (_("selected processor does not support ARM opcodes"));
2821 frag_align (2, 0, 0);
2823 record_alignment (now_seg
, 1);
2828 as_bad (_("invalid instruction size selected (%d)"), width
);
2833 s_arm (int ignore ATTRIBUTE_UNUSED
)
2836 demand_empty_rest_of_line ();
2840 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2843 demand_empty_rest_of_line ();
2847 s_code (int unused ATTRIBUTE_UNUSED
)
2851 temp
= get_absolute_expression ();
2856 opcode_select (temp
);
2860 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2865 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2867 /* If we are not already in thumb mode go into it, EVEN if
2868 the target processor does not support thumb instructions.
2869 This is used by gcc/config/arm/lib1funcs.asm for example
2870 to compile interworking support functions even if the
2871 target processor should not support interworking. */
2875 record_alignment (now_seg
, 1);
2878 demand_empty_rest_of_line ();
2882 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2886 /* The following label is the name/address of the start of a Thumb function.
2887 We need to know this for the interworking support. */
2888 label_is_thumb_function_name
= TRUE
;
2891 /* Perform a .set directive, but also mark the alias as
2892 being a thumb function. */
2895 s_thumb_set (int equiv
)
2897 /* XXX the following is a duplicate of the code for s_set() in read.c
2898 We cannot just call that code as we need to get at the symbol that
2905 /* Especial apologies for the random logic:
2906 This just grew, and could be parsed much more simply!
2908 delim
= get_symbol_name (& name
);
2909 end_name
= input_line_pointer
;
2910 (void) restore_line_pointer (delim
);
2912 if (*input_line_pointer
!= ',')
2915 as_bad (_("expected comma after name \"%s\""), name
);
2917 ignore_rest_of_line ();
2921 input_line_pointer
++;
2924 if (name
[0] == '.' && name
[1] == '\0')
2926 /* XXX - this should not happen to .thumb_set. */
2930 if ((symbolP
= symbol_find (name
)) == NULL
2931 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2934 /* When doing symbol listings, play games with dummy fragments living
2935 outside the normal fragment chain to record the file and line info
2937 if (listing
& LISTING_SYMBOLS
)
2939 extern struct list_info_struct
* listing_tail
;
2940 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2942 memset (dummy_frag
, 0, sizeof (fragS
));
2943 dummy_frag
->fr_type
= rs_fill
;
2944 dummy_frag
->line
= listing_tail
;
2945 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2946 dummy_frag
->fr_symbol
= symbolP
;
2950 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2953 /* "set" symbols are local unless otherwise specified. */
2954 SF_SET_LOCAL (symbolP
);
2955 #endif /* OBJ_COFF */
2956 } /* Make a new symbol. */
2958 symbol_table_insert (symbolP
);
2963 && S_IS_DEFINED (symbolP
)
2964 && S_GET_SEGMENT (symbolP
) != reg_section
)
2965 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2967 pseudo_set (symbolP
);
2969 demand_empty_rest_of_line ();
2971 /* XXX Now we come to the Thumb specific bit of code. */
2973 THUMB_SET_FUNC (symbolP
, 1);
2974 ARM_SET_THUMB (symbolP
, 1);
2975 #if defined OBJ_ELF || defined OBJ_COFF
2976 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2980 /* Directives: Mode selection. */
2982 /* .syntax [unified|divided] - choose the new unified syntax
2983 (same for Arm and Thumb encoding, modulo slight differences in what
2984 can be represented) or the old divergent syntax for each mode. */
2986 s_syntax (int unused ATTRIBUTE_UNUSED
)
2990 delim
= get_symbol_name (& name
);
2992 if (!strcasecmp (name
, "unified"))
2993 unified_syntax
= TRUE
;
2994 else if (!strcasecmp (name
, "divided"))
2995 unified_syntax
= FALSE
;
2998 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3001 (void) restore_line_pointer (delim
);
3002 demand_empty_rest_of_line ();
3005 /* Directives: sectioning and alignment. */
3008 s_bss (int ignore ATTRIBUTE_UNUSED
)
3010 /* We don't support putting frags in the BSS segment, we fake it by
3011 marking in_bss, then looking at s_skip for clues. */
3012 subseg_set (bss_section
, 0);
3013 demand_empty_rest_of_line ();
3015 #ifdef md_elf_section_change_hook
3016 md_elf_section_change_hook ();
3021 s_even (int ignore ATTRIBUTE_UNUSED
)
3023 /* Never make frag if expect extra pass. */
3025 frag_align (1, 0, 0);
3027 record_alignment (now_seg
, 1);
3029 demand_empty_rest_of_line ();
3032 /* Directives: CodeComposer Studio. */
3034 /* .ref (for CodeComposer Studio syntax only). */
3036 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3038 if (codecomposer_syntax
)
3039 ignore_rest_of_line ();
3041 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3044 /* If name is not NULL, then it is used for marking the beginning of a
3045 function, wherease if it is NULL then it means the function end. */
3047 asmfunc_debug (const char * name
)
3049 static const char * last_name
= NULL
;
3053 gas_assert (last_name
== NULL
);
3056 if (debug_type
== DEBUG_STABS
)
3057 stabs_generate_asm_func (name
, name
);
3061 gas_assert (last_name
!= NULL
);
3063 if (debug_type
== DEBUG_STABS
)
3064 stabs_generate_asm_endfunc (last_name
, last_name
);
3071 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3073 if (codecomposer_syntax
)
3075 switch (asmfunc_state
)
3077 case OUTSIDE_ASMFUNC
:
3078 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3081 case WAITING_ASMFUNC_NAME
:
3082 as_bad (_(".asmfunc repeated."));
3085 case WAITING_ENDASMFUNC
:
3086 as_bad (_(".asmfunc without function."));
3089 demand_empty_rest_of_line ();
3092 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3096 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3098 if (codecomposer_syntax
)
3100 switch (asmfunc_state
)
3102 case OUTSIDE_ASMFUNC
:
3103 as_bad (_(".endasmfunc without a .asmfunc."));
3106 case WAITING_ASMFUNC_NAME
:
3107 as_bad (_(".endasmfunc without function."));
3110 case WAITING_ENDASMFUNC
:
3111 asmfunc_state
= OUTSIDE_ASMFUNC
;
3112 asmfunc_debug (NULL
);
3115 demand_empty_rest_of_line ();
3118 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3122 s_ccs_def (int name
)
3124 if (codecomposer_syntax
)
3127 as_bad (_(".def pseudo-op only available with -mccs flag."));
3130 /* Directives: Literal pools. */
3132 static literal_pool
*
3133 find_literal_pool (void)
3135 literal_pool
* pool
;
3137 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3139 if (pool
->section
== now_seg
3140 && pool
->sub_section
== now_subseg
)
3147 static literal_pool
*
3148 find_or_make_literal_pool (void)
3150 /* Next literal pool ID number. */
3151 static unsigned int latest_pool_num
= 1;
3152 literal_pool
* pool
;
3154 pool
= find_literal_pool ();
3158 /* Create a new pool. */
3159 pool
= XNEW (literal_pool
);
3163 pool
->next_free_entry
= 0;
3164 pool
->section
= now_seg
;
3165 pool
->sub_section
= now_subseg
;
3166 pool
->next
= list_of_pools
;
3167 pool
->symbol
= NULL
;
3168 pool
->alignment
= 2;
3170 /* Add it to the list. */
3171 list_of_pools
= pool
;
3174 /* New pools, and emptied pools, will have a NULL symbol. */
3175 if (pool
->symbol
== NULL
)
3177 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3178 (valueT
) 0, &zero_address_frag
);
3179 pool
->id
= latest_pool_num
++;
3186 /* Add the literal in the global 'inst'
3187 structure to the relevant literal pool. */
3190 add_to_lit_pool (unsigned int nbytes
)
3192 #define PADDING_SLOT 0x1
3193 #define LIT_ENTRY_SIZE_MASK 0xFF
3194 literal_pool
* pool
;
3195 unsigned int entry
, pool_size
= 0;
3196 bfd_boolean padding_slot_p
= FALSE
;
3202 imm1
= inst
.operands
[1].imm
;
3203 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3204 : inst
.reloc
.exp
.X_unsigned
? 0
3205 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3206 if (target_big_endian
)
3209 imm2
= inst
.operands
[1].imm
;
3213 pool
= find_or_make_literal_pool ();
3215 /* Check if this literal value is already in the pool. */
3216 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3220 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3221 && (inst
.reloc
.exp
.X_op
== O_constant
)
3222 && (pool
->literals
[entry
].X_add_number
3223 == inst
.reloc
.exp
.X_add_number
)
3224 && (pool
->literals
[entry
].X_md
== nbytes
)
3225 && (pool
->literals
[entry
].X_unsigned
3226 == inst
.reloc
.exp
.X_unsigned
))
3229 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3230 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3231 && (pool
->literals
[entry
].X_add_number
3232 == inst
.reloc
.exp
.X_add_number
)
3233 && (pool
->literals
[entry
].X_add_symbol
3234 == inst
.reloc
.exp
.X_add_symbol
)
3235 && (pool
->literals
[entry
].X_op_symbol
3236 == inst
.reloc
.exp
.X_op_symbol
)
3237 && (pool
->literals
[entry
].X_md
== nbytes
))
3240 else if ((nbytes
== 8)
3241 && !(pool_size
& 0x7)
3242 && ((entry
+ 1) != pool
->next_free_entry
)
3243 && (pool
->literals
[entry
].X_op
== O_constant
)
3244 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3245 && (pool
->literals
[entry
].X_unsigned
3246 == inst
.reloc
.exp
.X_unsigned
)
3247 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3248 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3249 && (pool
->literals
[entry
+ 1].X_unsigned
3250 == inst
.reloc
.exp
.X_unsigned
))
3253 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3254 if (padding_slot_p
&& (nbytes
== 4))
3260 /* Do we need to create a new entry? */
3261 if (entry
== pool
->next_free_entry
)
3263 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3265 inst
.error
= _("literal pool overflow");
3271 /* For 8-byte entries, we align to an 8-byte boundary,
3272 and split it into two 4-byte entries, because on 32-bit
3273 host, 8-byte constants are treated as big num, thus
3274 saved in "generic_bignum" which will be overwritten
3275 by later assignments.
3277 We also need to make sure there is enough space for
3280 We also check to make sure the literal operand is a
3282 if (!(inst
.reloc
.exp
.X_op
== O_constant
3283 || inst
.reloc
.exp
.X_op
== O_big
))
3285 inst
.error
= _("invalid type for literal pool");
3288 else if (pool_size
& 0x7)
3290 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3292 inst
.error
= _("literal pool overflow");
3296 pool
->literals
[entry
] = inst
.reloc
.exp
;
3297 pool
->literals
[entry
].X_op
= O_constant
;
3298 pool
->literals
[entry
].X_add_number
= 0;
3299 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3300 pool
->next_free_entry
+= 1;
3303 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3305 inst
.error
= _("literal pool overflow");
3309 pool
->literals
[entry
] = inst
.reloc
.exp
;
3310 pool
->literals
[entry
].X_op
= O_constant
;
3311 pool
->literals
[entry
].X_add_number
= imm1
;
3312 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3313 pool
->literals
[entry
++].X_md
= 4;
3314 pool
->literals
[entry
] = inst
.reloc
.exp
;
3315 pool
->literals
[entry
].X_op
= O_constant
;
3316 pool
->literals
[entry
].X_add_number
= imm2
;
3317 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3318 pool
->literals
[entry
].X_md
= 4;
3319 pool
->alignment
= 3;
3320 pool
->next_free_entry
+= 1;
3324 pool
->literals
[entry
] = inst
.reloc
.exp
;
3325 pool
->literals
[entry
].X_md
= 4;
3329 /* PR ld/12974: Record the location of the first source line to reference
3330 this entry in the literal pool. If it turns out during linking that the
3331 symbol does not exist we will be able to give an accurate line number for
3332 the (first use of the) missing reference. */
3333 if (debug_type
== DEBUG_DWARF2
)
3334 dwarf2_where (pool
->locs
+ entry
);
3336 pool
->next_free_entry
+= 1;
3338 else if (padding_slot_p
)
3340 pool
->literals
[entry
] = inst
.reloc
.exp
;
3341 pool
->literals
[entry
].X_md
= nbytes
;
3344 inst
.reloc
.exp
.X_op
= O_symbol
;
3345 inst
.reloc
.exp
.X_add_number
= pool_size
;
3346 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3352 tc_start_label_without_colon (void)
3354 bfd_boolean ret
= TRUE
;
3356 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3358 const char *label
= input_line_pointer
;
3360 while (!is_end_of_line
[(int) label
[-1]])
3365 as_bad (_("Invalid label '%s'"), label
);
3369 asmfunc_debug (label
);
3371 asmfunc_state
= WAITING_ENDASMFUNC
;
3377 /* Can't use symbol_new here, so have to create a symbol and then at
3378 a later date assign it a value. Thats what these functions do. */
3381 symbol_locate (symbolS
* symbolP
,
3382 const char * name
, /* It is copied, the caller can modify. */
3383 segT segment
, /* Segment identifier (SEG_<something>). */
3384 valueT valu
, /* Symbol value. */
3385 fragS
* frag
) /* Associated fragment. */
3388 char * preserved_copy_of_name
;
3390 name_length
= strlen (name
) + 1; /* +1 for \0. */
3391 obstack_grow (¬es
, name
, name_length
);
3392 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3394 #ifdef tc_canonicalize_symbol_name
3395 preserved_copy_of_name
=
3396 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3399 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3401 S_SET_SEGMENT (symbolP
, segment
);
3402 S_SET_VALUE (symbolP
, valu
);
3403 symbol_clear_list_pointers (symbolP
);
3405 symbol_set_frag (symbolP
, frag
);
3407 /* Link to end of symbol chain. */
3409 extern int symbol_table_frozen
;
3411 if (symbol_table_frozen
)
3415 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3417 obj_symbol_new_hook (symbolP
);
3419 #ifdef tc_symbol_new_hook
3420 tc_symbol_new_hook (symbolP
);
3424 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3425 #endif /* DEBUG_SYMS */
3429 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3432 literal_pool
* pool
;
3435 pool
= find_literal_pool ();
3437 || pool
->symbol
== NULL
3438 || pool
->next_free_entry
== 0)
3441 /* Align pool as you have word accesses.
3442 Only make a frag if we have to. */
3444 frag_align (pool
->alignment
, 0, 0);
3446 record_alignment (now_seg
, 2);
3449 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3450 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3452 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3454 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3455 (valueT
) frag_now_fix (), frag_now
);
3456 symbol_table_insert (pool
->symbol
);
3458 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3460 #if defined OBJ_COFF || defined OBJ_ELF
3461 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3464 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3467 if (debug_type
== DEBUG_DWARF2
)
3468 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3470 /* First output the expression in the instruction to the pool. */
3471 emit_expr (&(pool
->literals
[entry
]),
3472 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3475 /* Mark the pool as empty. */
3476 pool
->next_free_entry
= 0;
3477 pool
->symbol
= NULL
;
3481 /* Forward declarations for functions below, in the MD interface
3483 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3484 static valueT
create_unwind_entry (int);
3485 static void start_unwind_section (const segT
, int);
3486 static void add_unwind_opcode (valueT
, int);
3487 static void flush_pending_unwind (void);
3489 /* Directives: Data. */
3492 s_arm_elf_cons (int nbytes
)
3496 #ifdef md_flush_pending_output
3497 md_flush_pending_output ();
3500 if (is_it_end_of_statement ())
3502 demand_empty_rest_of_line ();
3506 #ifdef md_cons_align
3507 md_cons_align (nbytes
);
3510 mapping_state (MAP_DATA
);
3514 char *base
= input_line_pointer
;
3518 if (exp
.X_op
!= O_symbol
)
3519 emit_expr (&exp
, (unsigned int) nbytes
);
3522 char *before_reloc
= input_line_pointer
;
3523 reloc
= parse_reloc (&input_line_pointer
);
3526 as_bad (_("unrecognized relocation suffix"));
3527 ignore_rest_of_line ();
3530 else if (reloc
== BFD_RELOC_UNUSED
)
3531 emit_expr (&exp
, (unsigned int) nbytes
);
3534 reloc_howto_type
*howto
= (reloc_howto_type
*)
3535 bfd_reloc_type_lookup (stdoutput
,
3536 (bfd_reloc_code_real_type
) reloc
);
3537 int size
= bfd_get_reloc_size (howto
);
3539 if (reloc
== BFD_RELOC_ARM_PLT32
)
3541 as_bad (_("(plt) is only valid on branch targets"));
3542 reloc
= BFD_RELOC_UNUSED
;
3547 as_bad (_("%s relocations do not fit in %d bytes"),
3548 howto
->name
, nbytes
);
3551 /* We've parsed an expression stopping at O_symbol.
3552 But there may be more expression left now that we
3553 have parsed the relocation marker. Parse it again.
3554 XXX Surely there is a cleaner way to do this. */
3555 char *p
= input_line_pointer
;
3557 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3559 memcpy (save_buf
, base
, input_line_pointer
- base
);
3560 memmove (base
+ (input_line_pointer
- before_reloc
),
3561 base
, before_reloc
- base
);
3563 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3565 memcpy (base
, save_buf
, p
- base
);
3567 offset
= nbytes
- size
;
3568 p
= frag_more (nbytes
);
3569 memset (p
, 0, nbytes
);
3570 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3571 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3577 while (*input_line_pointer
++ == ',');
3579 /* Put terminator back into stream. */
3580 input_line_pointer
--;
3581 demand_empty_rest_of_line ();
3584 /* Emit an expression containing a 32-bit thumb instruction.
3585 Implementation based on put_thumb32_insn. */
3588 emit_thumb32_expr (expressionS
* exp
)
3590 expressionS exp_high
= *exp
;
3592 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3593 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3594 exp
->X_add_number
&= 0xffff;
3595 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3598 /* Guess the instruction size based on the opcode. */
3601 thumb_insn_size (int opcode
)
3603 if ((unsigned int) opcode
< 0xe800u
)
3605 else if ((unsigned int) opcode
>= 0xe8000000u
)
3612 emit_insn (expressionS
*exp
, int nbytes
)
3616 if (exp
->X_op
== O_constant
)
3621 size
= thumb_insn_size (exp
->X_add_number
);
3625 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3627 as_bad (_(".inst.n operand too big. "\
3628 "Use .inst.w instead"));
3633 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3634 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3636 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3638 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3639 emit_thumb32_expr (exp
);
3641 emit_expr (exp
, (unsigned int) size
);
3643 it_fsm_post_encode ();
3647 as_bad (_("cannot determine Thumb instruction size. " \
3648 "Use .inst.n/.inst.w instead"));
3651 as_bad (_("constant expression required"));
3656 /* Like s_arm_elf_cons but do not use md_cons_align and
3657 set the mapping state to MAP_ARM/MAP_THUMB. */
3660 s_arm_elf_inst (int nbytes
)
3662 if (is_it_end_of_statement ())
3664 demand_empty_rest_of_line ();
3668 /* Calling mapping_state () here will not change ARM/THUMB,
3669 but will ensure not to be in DATA state. */
3672 mapping_state (MAP_THUMB
);
3677 as_bad (_("width suffixes are invalid in ARM mode"));
3678 ignore_rest_of_line ();
3684 mapping_state (MAP_ARM
);
3693 if (! emit_insn (& exp
, nbytes
))
3695 ignore_rest_of_line ();
3699 while (*input_line_pointer
++ == ',');
3701 /* Put terminator back into stream. */
3702 input_line_pointer
--;
3703 demand_empty_rest_of_line ();
3706 /* Parse a .rel31 directive. */
3709 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3716 if (*input_line_pointer
== '1')
3717 highbit
= 0x80000000;
3718 else if (*input_line_pointer
!= '0')
3719 as_bad (_("expected 0 or 1"));
3721 input_line_pointer
++;
3722 if (*input_line_pointer
!= ',')
3723 as_bad (_("missing comma"));
3724 input_line_pointer
++;
3726 #ifdef md_flush_pending_output
3727 md_flush_pending_output ();
3730 #ifdef md_cons_align
3734 mapping_state (MAP_DATA
);
3739 md_number_to_chars (p
, highbit
, 4);
3740 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3741 BFD_RELOC_ARM_PREL31
);
3743 demand_empty_rest_of_line ();
3746 /* Directives: AEABI stack-unwind tables. */
3748 /* Parse an unwind_fnstart directive. Simply records the current location. */
3751 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3753 demand_empty_rest_of_line ();
3754 if (unwind
.proc_start
)
3756 as_bad (_("duplicate .fnstart directive"));
3760 /* Mark the start of the function. */
3761 unwind
.proc_start
= expr_build_dot ();
3763 /* Reset the rest of the unwind info. */
3764 unwind
.opcode_count
= 0;
3765 unwind
.table_entry
= NULL
;
3766 unwind
.personality_routine
= NULL
;
3767 unwind
.personality_index
= -1;
3768 unwind
.frame_size
= 0;
3769 unwind
.fp_offset
= 0;
3770 unwind
.fp_reg
= REG_SP
;
3772 unwind
.sp_restored
= 0;
3776 /* Parse a handlerdata directive. Creates the exception handling table entry
3777 for the function. */
3780 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3782 demand_empty_rest_of_line ();
3783 if (!unwind
.proc_start
)
3784 as_bad (MISSING_FNSTART
);
3786 if (unwind
.table_entry
)
3787 as_bad (_("duplicate .handlerdata directive"));
3789 create_unwind_entry (1);
3792 /* Parse an unwind_fnend directive. Generates the index table entry. */
3795 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3800 unsigned int marked_pr_dependency
;
3802 demand_empty_rest_of_line ();
3804 if (!unwind
.proc_start
)
3806 as_bad (_(".fnend directive without .fnstart"));
3810 /* Add eh table entry. */
3811 if (unwind
.table_entry
== NULL
)
3812 val
= create_unwind_entry (0);
3816 /* Add index table entry. This is two words. */
3817 start_unwind_section (unwind
.saved_seg
, 1);
3818 frag_align (2, 0, 0);
3819 record_alignment (now_seg
, 2);
3821 ptr
= frag_more (8);
3823 where
= frag_now_fix () - 8;
3825 /* Self relative offset of the function start. */
3826 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3827 BFD_RELOC_ARM_PREL31
);
3829 /* Indicate dependency on EHABI-defined personality routines to the
3830 linker, if it hasn't been done already. */
3831 marked_pr_dependency
3832 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3833 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3834 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3836 static const char *const name
[] =
3838 "__aeabi_unwind_cpp_pr0",
3839 "__aeabi_unwind_cpp_pr1",
3840 "__aeabi_unwind_cpp_pr2"
3842 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3843 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3844 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3845 |= 1 << unwind
.personality_index
;
3849 /* Inline exception table entry. */
3850 md_number_to_chars (ptr
+ 4, val
, 4);
3852 /* Self relative offset of the table entry. */
3853 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3854 BFD_RELOC_ARM_PREL31
);
3856 /* Restore the original section. */
3857 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3859 unwind
.proc_start
= NULL
;
3863 /* Parse an unwind_cantunwind directive. */
3866 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3868 demand_empty_rest_of_line ();
3869 if (!unwind
.proc_start
)
3870 as_bad (MISSING_FNSTART
);
3872 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3873 as_bad (_("personality routine specified for cantunwind frame"));
3875 unwind
.personality_index
= -2;
3879 /* Parse a personalityindex directive. */
3882 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3886 if (!unwind
.proc_start
)
3887 as_bad (MISSING_FNSTART
);
3889 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3890 as_bad (_("duplicate .personalityindex directive"));
3894 if (exp
.X_op
!= O_constant
3895 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3897 as_bad (_("bad personality routine number"));
3898 ignore_rest_of_line ();
3902 unwind
.personality_index
= exp
.X_add_number
;
3904 demand_empty_rest_of_line ();
3908 /* Parse a personality directive. */
3911 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3915 if (!unwind
.proc_start
)
3916 as_bad (MISSING_FNSTART
);
3918 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3919 as_bad (_("duplicate .personality directive"));
3921 c
= get_symbol_name (& name
);
3922 p
= input_line_pointer
;
3924 ++ input_line_pointer
;
3925 unwind
.personality_routine
= symbol_find_or_make (name
);
3927 demand_empty_rest_of_line ();
3931 /* Parse a directive saving core registers. */
3934 s_arm_unwind_save_core (void)
3940 range
= parse_reg_list (&input_line_pointer
);
3943 as_bad (_("expected register list"));
3944 ignore_rest_of_line ();
3948 demand_empty_rest_of_line ();
3950 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3951 into .unwind_save {..., sp...}. We aren't bothered about the value of
3952 ip because it is clobbered by calls. */
3953 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3954 && (range
& 0x3000) == 0x1000)
3956 unwind
.opcode_count
--;
3957 unwind
.sp_restored
= 0;
3958 range
= (range
| 0x2000) & ~0x1000;
3959 unwind
.pending_offset
= 0;
3965 /* See if we can use the short opcodes. These pop a block of up to 8
3966 registers starting with r4, plus maybe r14. */
3967 for (n
= 0; n
< 8; n
++)
3969 /* Break at the first non-saved register. */
3970 if ((range
& (1 << (n
+ 4))) == 0)
3973 /* See if there are any other bits set. */
3974 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3976 /* Use the long form. */
3977 op
= 0x8000 | ((range
>> 4) & 0xfff);
3978 add_unwind_opcode (op
, 2);
3982 /* Use the short form. */
3984 op
= 0xa8; /* Pop r14. */
3986 op
= 0xa0; /* Do not pop r14. */
3988 add_unwind_opcode (op
, 1);
3995 op
= 0xb100 | (range
& 0xf);
3996 add_unwind_opcode (op
, 2);
3999 /* Record the number of bytes pushed. */
4000 for (n
= 0; n
< 16; n
++)
4002 if (range
& (1 << n
))
4003 unwind
.frame_size
+= 4;
4008 /* Parse a directive saving FPA registers. */
4011 s_arm_unwind_save_fpa (int reg
)
4017 /* Get Number of registers to transfer. */
4018 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4021 exp
.X_op
= O_illegal
;
4023 if (exp
.X_op
!= O_constant
)
4025 as_bad (_("expected , <constant>"));
4026 ignore_rest_of_line ();
4030 num_regs
= exp
.X_add_number
;
4032 if (num_regs
< 1 || num_regs
> 4)
4034 as_bad (_("number of registers must be in the range [1:4]"));
4035 ignore_rest_of_line ();
4039 demand_empty_rest_of_line ();
4044 op
= 0xb4 | (num_regs
- 1);
4045 add_unwind_opcode (op
, 1);
4050 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4051 add_unwind_opcode (op
, 2);
4053 unwind
.frame_size
+= num_regs
* 12;
4057 /* Parse a directive saving VFP registers for ARMv6 and above. */
4060 s_arm_unwind_save_vfp_armv6 (void)
4065 int num_vfpv3_regs
= 0;
4066 int num_regs_below_16
;
4068 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4071 as_bad (_("expected register list"));
4072 ignore_rest_of_line ();
4076 demand_empty_rest_of_line ();
4078 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4079 than FSTMX/FLDMX-style ones). */
4081 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4083 num_vfpv3_regs
= count
;
4084 else if (start
+ count
> 16)
4085 num_vfpv3_regs
= start
+ count
- 16;
4087 if (num_vfpv3_regs
> 0)
4089 int start_offset
= start
> 16 ? start
- 16 : 0;
4090 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4091 add_unwind_opcode (op
, 2);
4094 /* Generate opcode for registers numbered in the range 0 .. 15. */
4095 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4096 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4097 if (num_regs_below_16
> 0)
4099 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4100 add_unwind_opcode (op
, 2);
4103 unwind
.frame_size
+= count
* 8;
4107 /* Parse a directive saving VFP registers for pre-ARMv6. */
4110 s_arm_unwind_save_vfp (void)
4116 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4119 as_bad (_("expected register list"));
4120 ignore_rest_of_line ();
4124 demand_empty_rest_of_line ();
4129 op
= 0xb8 | (count
- 1);
4130 add_unwind_opcode (op
, 1);
4135 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4136 add_unwind_opcode (op
, 2);
4138 unwind
.frame_size
+= count
* 8 + 4;
4142 /* Parse a directive saving iWMMXt data registers. */
4145 s_arm_unwind_save_mmxwr (void)
4153 if (*input_line_pointer
== '{')
4154 input_line_pointer
++;
4158 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4162 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4167 as_tsktsk (_("register list not in ascending order"));
4170 if (*input_line_pointer
== '-')
4172 input_line_pointer
++;
4173 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4176 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4179 else if (reg
>= hi_reg
)
4181 as_bad (_("bad register range"));
4184 for (; reg
< hi_reg
; reg
++)
4188 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4190 skip_past_char (&input_line_pointer
, '}');
4192 demand_empty_rest_of_line ();
4194 /* Generate any deferred opcodes because we're going to be looking at
4196 flush_pending_unwind ();
4198 for (i
= 0; i
< 16; i
++)
4200 if (mask
& (1 << i
))
4201 unwind
.frame_size
+= 8;
4204 /* Attempt to combine with a previous opcode. We do this because gcc
4205 likes to output separate unwind directives for a single block of
4207 if (unwind
.opcode_count
> 0)
4209 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4210 if ((i
& 0xf8) == 0xc0)
4213 /* Only merge if the blocks are contiguous. */
4216 if ((mask
& 0xfe00) == (1 << 9))
4218 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4219 unwind
.opcode_count
--;
4222 else if (i
== 6 && unwind
.opcode_count
>= 2)
4224 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4228 op
= 0xffff << (reg
- 1);
4230 && ((mask
& op
) == (1u << (reg
- 1))))
4232 op
= (1 << (reg
+ i
+ 1)) - 1;
4233 op
&= ~((1 << reg
) - 1);
4235 unwind
.opcode_count
-= 2;
4242 /* We want to generate opcodes in the order the registers have been
4243 saved, ie. descending order. */
4244 for (reg
= 15; reg
>= -1; reg
--)
4246 /* Save registers in blocks. */
4248 || !(mask
& (1 << reg
)))
4250 /* We found an unsaved reg. Generate opcodes to save the
4257 op
= 0xc0 | (hi_reg
- 10);
4258 add_unwind_opcode (op
, 1);
4263 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4264 add_unwind_opcode (op
, 2);
4273 ignore_rest_of_line ();
4277 s_arm_unwind_save_mmxwcg (void)
4284 if (*input_line_pointer
== '{')
4285 input_line_pointer
++;
4287 skip_whitespace (input_line_pointer
);
4291 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4295 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4301 as_tsktsk (_("register list not in ascending order"));
4304 if (*input_line_pointer
== '-')
4306 input_line_pointer
++;
4307 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4310 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4313 else if (reg
>= hi_reg
)
4315 as_bad (_("bad register range"));
4318 for (; reg
< hi_reg
; reg
++)
4322 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4324 skip_past_char (&input_line_pointer
, '}');
4326 demand_empty_rest_of_line ();
4328 /* Generate any deferred opcodes because we're going to be looking at
4330 flush_pending_unwind ();
4332 for (reg
= 0; reg
< 16; reg
++)
4334 if (mask
& (1 << reg
))
4335 unwind
.frame_size
+= 4;
4338 add_unwind_opcode (op
, 2);
4341 ignore_rest_of_line ();
4345 /* Parse an unwind_save directive.
4346 If the argument is non-zero, this is a .vsave directive. */
4349 s_arm_unwind_save (int arch_v6
)
4352 struct reg_entry
*reg
;
4353 bfd_boolean had_brace
= FALSE
;
4355 if (!unwind
.proc_start
)
4356 as_bad (MISSING_FNSTART
);
4358 /* Figure out what sort of save we have. */
4359 peek
= input_line_pointer
;
4367 reg
= arm_reg_parse_multi (&peek
);
4371 as_bad (_("register expected"));
4372 ignore_rest_of_line ();
4381 as_bad (_("FPA .unwind_save does not take a register list"));
4382 ignore_rest_of_line ();
4385 input_line_pointer
= peek
;
4386 s_arm_unwind_save_fpa (reg
->number
);
4390 s_arm_unwind_save_core ();
4395 s_arm_unwind_save_vfp_armv6 ();
4397 s_arm_unwind_save_vfp ();
4400 case REG_TYPE_MMXWR
:
4401 s_arm_unwind_save_mmxwr ();
4404 case REG_TYPE_MMXWCG
:
4405 s_arm_unwind_save_mmxwcg ();
4409 as_bad (_(".unwind_save does not support this kind of register"));
4410 ignore_rest_of_line ();
4415 /* Parse an unwind_movsp directive. */
4418 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4424 if (!unwind
.proc_start
)
4425 as_bad (MISSING_FNSTART
);
4427 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4430 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4431 ignore_rest_of_line ();
4435 /* Optional constant. */
4436 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4438 if (immediate_for_directive (&offset
) == FAIL
)
4444 demand_empty_rest_of_line ();
4446 if (reg
== REG_SP
|| reg
== REG_PC
)
4448 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4452 if (unwind
.fp_reg
!= REG_SP
)
4453 as_bad (_("unexpected .unwind_movsp directive"));
4455 /* Generate opcode to restore the value. */
4457 add_unwind_opcode (op
, 1);
4459 /* Record the information for later. */
4460 unwind
.fp_reg
= reg
;
4461 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4462 unwind
.sp_restored
= 1;
4465 /* Parse an unwind_pad directive. */
4468 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4472 if (!unwind
.proc_start
)
4473 as_bad (MISSING_FNSTART
);
4475 if (immediate_for_directive (&offset
) == FAIL
)
4480 as_bad (_("stack increment must be multiple of 4"));
4481 ignore_rest_of_line ();
4485 /* Don't generate any opcodes, just record the details for later. */
4486 unwind
.frame_size
+= offset
;
4487 unwind
.pending_offset
+= offset
;
4489 demand_empty_rest_of_line ();
4492 /* Parse an unwind_setfp directive. */
4495 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4501 if (!unwind
.proc_start
)
4502 as_bad (MISSING_FNSTART
);
4504 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4505 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4508 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4510 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4512 as_bad (_("expected <reg>, <reg>"));
4513 ignore_rest_of_line ();
4517 /* Optional constant. */
4518 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4520 if (immediate_for_directive (&offset
) == FAIL
)
4526 demand_empty_rest_of_line ();
4528 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4530 as_bad (_("register must be either sp or set by a previous"
4531 "unwind_movsp directive"));
4535 /* Don't generate any opcodes, just record the information for later. */
4536 unwind
.fp_reg
= fp_reg
;
4538 if (sp_reg
== REG_SP
)
4539 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4541 unwind
.fp_offset
-= offset
;
4544 /* Parse an unwind_raw directive. */
4547 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4550 /* This is an arbitrary limit. */
4551 unsigned char op
[16];
4554 if (!unwind
.proc_start
)
4555 as_bad (MISSING_FNSTART
);
4558 if (exp
.X_op
== O_constant
4559 && skip_past_comma (&input_line_pointer
) != FAIL
)
4561 unwind
.frame_size
+= exp
.X_add_number
;
4565 exp
.X_op
= O_illegal
;
4567 if (exp
.X_op
!= O_constant
)
4569 as_bad (_("expected <offset>, <opcode>"));
4570 ignore_rest_of_line ();
4576 /* Parse the opcode. */
4581 as_bad (_("unwind opcode too long"));
4582 ignore_rest_of_line ();
4584 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4586 as_bad (_("invalid unwind opcode"));
4587 ignore_rest_of_line ();
4590 op
[count
++] = exp
.X_add_number
;
4592 /* Parse the next byte. */
4593 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4599 /* Add the opcode bytes in reverse order. */
4601 add_unwind_opcode (op
[count
], 1);
4603 demand_empty_rest_of_line ();
4607 /* Parse a .eabi_attribute directive. */
4610 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4612 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4614 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4615 attributes_set_explicitly
[tag
] = 1;
4618 /* Emit a tls fix for the symbol. */
4621 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4625 #ifdef md_flush_pending_output
4626 md_flush_pending_output ();
4629 #ifdef md_cons_align
4633 /* Since we're just labelling the code, there's no need to define a
4636 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4637 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4638 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4639 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4641 #endif /* OBJ_ELF */
4643 static void s_arm_arch (int);
4644 static void s_arm_object_arch (int);
4645 static void s_arm_cpu (int);
4646 static void s_arm_fpu (int);
4647 static void s_arm_arch_extension (int);
4652 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4659 if (exp
.X_op
== O_symbol
)
4660 exp
.X_op
= O_secrel
;
4662 emit_expr (&exp
, 4);
4664 while (*input_line_pointer
++ == ',');
4666 input_line_pointer
--;
4667 demand_empty_rest_of_line ();
4671 /* This table describes all the machine specific pseudo-ops the assembler
4672 has to support. The fields are:
4673 pseudo-op name without dot
4674 function to call to execute this pseudo-op
4675 Integer arg to pass to the function. */
4677 const pseudo_typeS md_pseudo_table
[] =
4679 /* Never called because '.req' does not start a line. */
4680 { "req", s_req
, 0 },
4681 /* Following two are likewise never called. */
4684 { "unreq", s_unreq
, 0 },
4685 { "bss", s_bss
, 0 },
4686 { "align", s_align_ptwo
, 2 },
4687 { "arm", s_arm
, 0 },
4688 { "thumb", s_thumb
, 0 },
4689 { "code", s_code
, 0 },
4690 { "force_thumb", s_force_thumb
, 0 },
4691 { "thumb_func", s_thumb_func
, 0 },
4692 { "thumb_set", s_thumb_set
, 0 },
4693 { "even", s_even
, 0 },
4694 { "ltorg", s_ltorg
, 0 },
4695 { "pool", s_ltorg
, 0 },
4696 { "syntax", s_syntax
, 0 },
4697 { "cpu", s_arm_cpu
, 0 },
4698 { "arch", s_arm_arch
, 0 },
4699 { "object_arch", s_arm_object_arch
, 0 },
4700 { "fpu", s_arm_fpu
, 0 },
4701 { "arch_extension", s_arm_arch_extension
, 0 },
4703 { "word", s_arm_elf_cons
, 4 },
4704 { "long", s_arm_elf_cons
, 4 },
4705 { "inst.n", s_arm_elf_inst
, 2 },
4706 { "inst.w", s_arm_elf_inst
, 4 },
4707 { "inst", s_arm_elf_inst
, 0 },
4708 { "rel31", s_arm_rel31
, 0 },
4709 { "fnstart", s_arm_unwind_fnstart
, 0 },
4710 { "fnend", s_arm_unwind_fnend
, 0 },
4711 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4712 { "personality", s_arm_unwind_personality
, 0 },
4713 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4714 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4715 { "save", s_arm_unwind_save
, 0 },
4716 { "vsave", s_arm_unwind_save
, 1 },
4717 { "movsp", s_arm_unwind_movsp
, 0 },
4718 { "pad", s_arm_unwind_pad
, 0 },
4719 { "setfp", s_arm_unwind_setfp
, 0 },
4720 { "unwind_raw", s_arm_unwind_raw
, 0 },
4721 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4722 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4726 /* These are used for dwarf. */
4730 /* These are used for dwarf2. */
4731 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4732 { "loc", dwarf2_directive_loc
, 0 },
4733 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4735 { "extend", float_cons
, 'x' },
4736 { "ldouble", float_cons
, 'x' },
4737 { "packed", float_cons
, 'p' },
4739 {"secrel32", pe_directive_secrel
, 0},
4742 /* These are for compatibility with CodeComposer Studio. */
4743 {"ref", s_ccs_ref
, 0},
4744 {"def", s_ccs_def
, 0},
4745 {"asmfunc", s_ccs_asmfunc
, 0},
4746 {"endasmfunc", s_ccs_endasmfunc
, 0},
4751 /* Parser functions used exclusively in instruction operands. */
4753 /* Generic immediate-value read function for use in insn parsing.
4754 STR points to the beginning of the immediate (the leading #);
4755 VAL receives the value; if the value is outside [MIN, MAX]
4756 issue an error. PREFIX_OPT is true if the immediate prefix is
4760 parse_immediate (char **str
, int *val
, int min
, int max
,
4761 bfd_boolean prefix_opt
)
4764 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4765 if (exp
.X_op
!= O_constant
)
4767 inst
.error
= _("constant expression required");
4771 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4773 inst
.error
= _("immediate value out of range");
4777 *val
= exp
.X_add_number
;
4781 /* Less-generic immediate-value read function with the possibility of loading a
4782 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4783 instructions. Puts the result directly in inst.operands[i]. */
4786 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4787 bfd_boolean allow_symbol_p
)
4790 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4793 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4795 if (exp_p
->X_op
== O_constant
)
4797 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4798 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4799 O_constant. We have to be careful not to break compilation for
4800 32-bit X_add_number, though. */
4801 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4803 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4804 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4806 inst
.operands
[i
].regisimm
= 1;
4809 else if (exp_p
->X_op
== O_big
4810 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4812 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4814 /* Bignums have their least significant bits in
4815 generic_bignum[0]. Make sure we put 32 bits in imm and
4816 32 bits in reg, in a (hopefully) portable way. */
4817 gas_assert (parts
!= 0);
4819 /* Make sure that the number is not too big.
4820 PR 11972: Bignums can now be sign-extended to the
4821 size of a .octa so check that the out of range bits
4822 are all zero or all one. */
4823 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4825 LITTLENUM_TYPE m
= -1;
4827 if (generic_bignum
[parts
* 2] != 0
4828 && generic_bignum
[parts
* 2] != m
)
4831 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4832 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4836 inst
.operands
[i
].imm
= 0;
4837 for (j
= 0; j
< parts
; j
++, idx
++)
4838 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4839 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4840 inst
.operands
[i
].reg
= 0;
4841 for (j
= 0; j
< parts
; j
++, idx
++)
4842 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4843 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4844 inst
.operands
[i
].regisimm
= 1;
4846 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4854 /* Returns the pseudo-register number of an FPA immediate constant,
4855 or FAIL if there isn't a valid constant here. */
4858 parse_fpa_immediate (char ** str
)
4860 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4866 /* First try and match exact strings, this is to guarantee
4867 that some formats will work even for cross assembly. */
4869 for (i
= 0; fp_const
[i
]; i
++)
4871 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4875 *str
+= strlen (fp_const
[i
]);
4876 if (is_end_of_line
[(unsigned char) **str
])
4882 /* Just because we didn't get a match doesn't mean that the constant
4883 isn't valid, just that it is in a format that we don't
4884 automatically recognize. Try parsing it with the standard
4885 expression routines. */
4887 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4889 /* Look for a raw floating point number. */
4890 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4891 && is_end_of_line
[(unsigned char) *save_in
])
4893 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4895 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4897 if (words
[j
] != fp_values
[i
][j
])
4901 if (j
== MAX_LITTLENUMS
)
4909 /* Try and parse a more complex expression, this will probably fail
4910 unless the code uses a floating point prefix (eg "0f"). */
4911 save_in
= input_line_pointer
;
4912 input_line_pointer
= *str
;
4913 if (expression (&exp
) == absolute_section
4914 && exp
.X_op
== O_big
4915 && exp
.X_add_number
< 0)
4917 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4919 #define X_PRECISION 5
4920 #define E_PRECISION 15L
4921 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4923 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4925 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4927 if (words
[j
] != fp_values
[i
][j
])
4931 if (j
== MAX_LITTLENUMS
)
4933 *str
= input_line_pointer
;
4934 input_line_pointer
= save_in
;
4941 *str
= input_line_pointer
;
4942 input_line_pointer
= save_in
;
4943 inst
.error
= _("invalid FPA immediate expression");
4947 /* Returns 1 if a number has "quarter-precision" float format
4948 0baBbbbbbc defgh000 00000000 00000000. */
4951 is_quarter_float (unsigned imm
)
4953 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4954 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4958 /* Detect the presence of a floating point or integer zero constant,
4962 parse_ifimm_zero (char **in
)
4966 if (!is_immediate_prefix (**in
))
4971 /* Accept #0x0 as a synonym for #0. */
4972 if (strncmp (*in
, "0x", 2) == 0)
4975 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4980 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4981 &generic_floating_point_number
);
4984 && generic_floating_point_number
.sign
== '+'
4985 && (generic_floating_point_number
.low
4986 > generic_floating_point_number
.leader
))
4992 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4993 0baBbbbbbc defgh000 00000000 00000000.
4994 The zero and minus-zero cases need special handling, since they can't be
4995 encoded in the "quarter-precision" float format, but can nonetheless be
4996 loaded as integer constants. */
4999 parse_qfloat_immediate (char **ccp
, int *immed
)
5003 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5004 int found_fpchar
= 0;
5006 skip_past_char (&str
, '#');
5008 /* We must not accidentally parse an integer as a floating-point number. Make
5009 sure that the value we parse is not an integer by checking for special
5010 characters '.' or 'e'.
5011 FIXME: This is a horrible hack, but doing better is tricky because type
5012 information isn't in a very usable state at parse time. */
5014 skip_whitespace (fpnum
);
5016 if (strncmp (fpnum
, "0x", 2) == 0)
5020 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5021 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5031 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5033 unsigned fpword
= 0;
5036 /* Our FP word must be 32 bits (single-precision FP). */
5037 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5039 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5043 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5056 /* Shift operands. */
5059 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5062 struct asm_shift_name
5065 enum shift_kind kind
;
5068 /* Third argument to parse_shift. */
5069 enum parse_shift_mode
5071 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5072 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5073 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5074 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5075 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5078 /* Parse a <shift> specifier on an ARM data processing instruction.
5079 This has three forms:
5081 (LSL|LSR|ASL|ASR|ROR) Rs
5082 (LSL|LSR|ASL|ASR|ROR) #imm
5085 Note that ASL is assimilated to LSL in the instruction encoding, and
5086 RRX to ROR #0 (which cannot be written as such). */
5089 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5091 const struct asm_shift_name
*shift_name
;
5092 enum shift_kind shift
;
5097 for (p
= *str
; ISALPHA (*p
); p
++)
5102 inst
.error
= _("shift expression expected");
5106 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5109 if (shift_name
== NULL
)
5111 inst
.error
= _("shift expression expected");
5115 shift
= shift_name
->kind
;
5119 case NO_SHIFT_RESTRICT
:
5120 case SHIFT_IMMEDIATE
: break;
5122 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5123 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5125 inst
.error
= _("'LSL' or 'ASR' required");
5130 case SHIFT_LSL_IMMEDIATE
:
5131 if (shift
!= SHIFT_LSL
)
5133 inst
.error
= _("'LSL' required");
5138 case SHIFT_ASR_IMMEDIATE
:
5139 if (shift
!= SHIFT_ASR
)
5141 inst
.error
= _("'ASR' required");
5149 if (shift
!= SHIFT_RRX
)
5151 /* Whitespace can appear here if the next thing is a bare digit. */
5152 skip_whitespace (p
);
5154 if (mode
== NO_SHIFT_RESTRICT
5155 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5157 inst
.operands
[i
].imm
= reg
;
5158 inst
.operands
[i
].immisreg
= 1;
5160 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5163 inst
.operands
[i
].shift_kind
= shift
;
5164 inst
.operands
[i
].shifted
= 1;
5169 /* Parse a <shifter_operand> for an ARM data processing instruction:
5172 #<immediate>, <rotate>
5176 where <shift> is defined by parse_shift above, and <rotate> is a
5177 multiple of 2 between 0 and 30. Validation of immediate operands
5178 is deferred to md_apply_fix. */
5181 parse_shifter_operand (char **str
, int i
)
5186 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5188 inst
.operands
[i
].reg
= value
;
5189 inst
.operands
[i
].isreg
= 1;
5191 /* parse_shift will override this if appropriate */
5192 inst
.reloc
.exp
.X_op
= O_constant
;
5193 inst
.reloc
.exp
.X_add_number
= 0;
5195 if (skip_past_comma (str
) == FAIL
)
5198 /* Shift operation on register. */
5199 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5202 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5205 if (skip_past_comma (str
) == SUCCESS
)
5207 /* #x, y -- ie explicit rotation by Y. */
5208 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5211 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5213 inst
.error
= _("constant expression expected");
5217 value
= exp
.X_add_number
;
5218 if (value
< 0 || value
> 30 || value
% 2 != 0)
5220 inst
.error
= _("invalid rotation");
5223 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5225 inst
.error
= _("invalid constant");
5229 /* Encode as specified. */
5230 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5234 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5235 inst
.reloc
.pc_rel
= 0;
5239 /* Group relocation information. Each entry in the table contains the
5240 textual name of the relocation as may appear in assembler source
5241 and must end with a colon.
5242 Along with this textual name are the relocation codes to be used if
5243 the corresponding instruction is an ALU instruction (ADD or SUB only),
5244 an LDR, an LDRS, or an LDC. */
5246 struct group_reloc_table_entry
5257 /* Varieties of non-ALU group relocation. */
5264 static struct group_reloc_table_entry group_reloc_table
[] =
5265 { /* Program counter relative: */
5267 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5272 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5273 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5274 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5275 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5277 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5282 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5283 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5284 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5285 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5287 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5288 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5289 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5290 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5291 /* Section base relative */
5293 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5298 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5299 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5300 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5301 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5303 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5308 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5309 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5310 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5311 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5313 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5314 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5315 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5316 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5317 /* Absolute thumb alu relocations. */
5319 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5324 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5329 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5334 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5339 /* Given the address of a pointer pointing to the textual name of a group
5340 relocation as may appear in assembler source, attempt to find its details
5341 in group_reloc_table. The pointer will be updated to the character after
5342 the trailing colon. On failure, FAIL will be returned; SUCCESS
5343 otherwise. On success, *entry will be updated to point at the relevant
5344 group_reloc_table entry. */
5347 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5350 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5352 int length
= strlen (group_reloc_table
[i
].name
);
5354 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5355 && (*str
)[length
] == ':')
5357 *out
= &group_reloc_table
[i
];
5358 *str
+= (length
+ 1);
5366 /* Parse a <shifter_operand> for an ARM data processing instruction
5367 (as for parse_shifter_operand) where group relocations are allowed:
5370 #<immediate>, <rotate>
5371 #:<group_reloc>:<expression>
5375 where <group_reloc> is one of the strings defined in group_reloc_table.
5376 The hashes are optional.
5378 Everything else is as for parse_shifter_operand. */
5380 static parse_operand_result
5381 parse_shifter_operand_group_reloc (char **str
, int i
)
5383 /* Determine if we have the sequence of characters #: or just :
5384 coming next. If we do, then we check for a group relocation.
5385 If we don't, punt the whole lot to parse_shifter_operand. */
5387 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5388 || (*str
)[0] == ':')
5390 struct group_reloc_table_entry
*entry
;
5392 if ((*str
)[0] == '#')
5397 /* Try to parse a group relocation. Anything else is an error. */
5398 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5400 inst
.error
= _("unknown group relocation");
5401 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5404 /* We now have the group relocation table entry corresponding to
5405 the name in the assembler source. Next, we parse the expression. */
5406 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5407 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5409 /* Record the relocation type (always the ALU variant here). */
5410 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5411 gas_assert (inst
.reloc
.type
!= 0);
5413 return PARSE_OPERAND_SUCCESS
;
5416 return parse_shifter_operand (str
, i
) == SUCCESS
5417 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5419 /* Never reached. */
5422 /* Parse a Neon alignment expression. Information is written to
5423 inst.operands[i]. We assume the initial ':' has been skipped.
5425 align .imm = align << 8, .immisalign=1, .preind=0 */
5426 static parse_operand_result
5427 parse_neon_alignment (char **str
, int i
)
5432 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5434 if (exp
.X_op
!= O_constant
)
5436 inst
.error
= _("alignment must be constant");
5437 return PARSE_OPERAND_FAIL
;
5440 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5441 inst
.operands
[i
].immisalign
= 1;
5442 /* Alignments are not pre-indexes. */
5443 inst
.operands
[i
].preind
= 0;
5446 return PARSE_OPERAND_SUCCESS
;
5449 /* Parse all forms of an ARM address expression. Information is written
5450 to inst.operands[i] and/or inst.reloc.
5452 Preindexed addressing (.preind=1):
5454 [Rn, #offset] .reg=Rn .reloc.exp=offset
5455 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5456 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5457 .shift_kind=shift .reloc.exp=shift_imm
5459 These three may have a trailing ! which causes .writeback to be set also.
5461 Postindexed addressing (.postind=1, .writeback=1):
5463 [Rn], #offset .reg=Rn .reloc.exp=offset
5464 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5465 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5466 .shift_kind=shift .reloc.exp=shift_imm
5468 Unindexed addressing (.preind=0, .postind=0):
5470 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5474 [Rn]{!} shorthand for [Rn,#0]{!}
5475 =immediate .isreg=0 .reloc.exp=immediate
5476 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5478 It is the caller's responsibility to check for addressing modes not
5479 supported by the instruction, and to set inst.reloc.type. */
5481 static parse_operand_result
5482 parse_address_main (char **str
, int i
, int group_relocations
,
5483 group_reloc_type group_type
)
5488 if (skip_past_char (&p
, '[') == FAIL
)
5490 if (skip_past_char (&p
, '=') == FAIL
)
5492 /* Bare address - translate to PC-relative offset. */
5493 inst
.reloc
.pc_rel
= 1;
5494 inst
.operands
[i
].reg
= REG_PC
;
5495 inst
.operands
[i
].isreg
= 1;
5496 inst
.operands
[i
].preind
= 1;
5498 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5499 return PARSE_OPERAND_FAIL
;
5501 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5502 /*allow_symbol_p=*/TRUE
))
5503 return PARSE_OPERAND_FAIL
;
5506 return PARSE_OPERAND_SUCCESS
;
5509 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5510 skip_whitespace (p
);
5512 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5514 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5515 return PARSE_OPERAND_FAIL
;
5517 inst
.operands
[i
].reg
= reg
;
5518 inst
.operands
[i
].isreg
= 1;
5520 if (skip_past_comma (&p
) == SUCCESS
)
5522 inst
.operands
[i
].preind
= 1;
5525 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5527 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5529 inst
.operands
[i
].imm
= reg
;
5530 inst
.operands
[i
].immisreg
= 1;
5532 if (skip_past_comma (&p
) == SUCCESS
)
5533 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5534 return PARSE_OPERAND_FAIL
;
5536 else if (skip_past_char (&p
, ':') == SUCCESS
)
5538 /* FIXME: '@' should be used here, but it's filtered out by generic
5539 code before we get to see it here. This may be subject to
5541 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5543 if (result
!= PARSE_OPERAND_SUCCESS
)
5548 if (inst
.operands
[i
].negative
)
5550 inst
.operands
[i
].negative
= 0;
5554 if (group_relocations
5555 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5557 struct group_reloc_table_entry
*entry
;
5559 /* Skip over the #: or : sequence. */
5565 /* Try to parse a group relocation. Anything else is an
5567 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5569 inst
.error
= _("unknown group relocation");
5570 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5573 /* We now have the group relocation table entry corresponding to
5574 the name in the assembler source. Next, we parse the
5576 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5577 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5579 /* Record the relocation type. */
5583 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5587 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5591 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5598 if (inst
.reloc
.type
== 0)
5600 inst
.error
= _("this group relocation is not allowed on this instruction");
5601 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5607 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5608 return PARSE_OPERAND_FAIL
;
5609 /* If the offset is 0, find out if it's a +0 or -0. */
5610 if (inst
.reloc
.exp
.X_op
== O_constant
5611 && inst
.reloc
.exp
.X_add_number
== 0)
5613 skip_whitespace (q
);
5617 skip_whitespace (q
);
5620 inst
.operands
[i
].negative
= 1;
5625 else if (skip_past_char (&p
, ':') == SUCCESS
)
5627 /* FIXME: '@' should be used here, but it's filtered out by generic code
5628 before we get to see it here. This may be subject to change. */
5629 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5631 if (result
!= PARSE_OPERAND_SUCCESS
)
5635 if (skip_past_char (&p
, ']') == FAIL
)
5637 inst
.error
= _("']' expected");
5638 return PARSE_OPERAND_FAIL
;
5641 if (skip_past_char (&p
, '!') == SUCCESS
)
5642 inst
.operands
[i
].writeback
= 1;
5644 else if (skip_past_comma (&p
) == SUCCESS
)
5646 if (skip_past_char (&p
, '{') == SUCCESS
)
5648 /* [Rn], {expr} - unindexed, with option */
5649 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5650 0, 255, TRUE
) == FAIL
)
5651 return PARSE_OPERAND_FAIL
;
5653 if (skip_past_char (&p
, '}') == FAIL
)
5655 inst
.error
= _("'}' expected at end of 'option' field");
5656 return PARSE_OPERAND_FAIL
;
5658 if (inst
.operands
[i
].preind
)
5660 inst
.error
= _("cannot combine index with option");
5661 return PARSE_OPERAND_FAIL
;
5664 return PARSE_OPERAND_SUCCESS
;
5668 inst
.operands
[i
].postind
= 1;
5669 inst
.operands
[i
].writeback
= 1;
5671 if (inst
.operands
[i
].preind
)
5673 inst
.error
= _("cannot combine pre- and post-indexing");
5674 return PARSE_OPERAND_FAIL
;
5678 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5680 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5682 /* We might be using the immediate for alignment already. If we
5683 are, OR the register number into the low-order bits. */
5684 if (inst
.operands
[i
].immisalign
)
5685 inst
.operands
[i
].imm
|= reg
;
5687 inst
.operands
[i
].imm
= reg
;
5688 inst
.operands
[i
].immisreg
= 1;
5690 if (skip_past_comma (&p
) == SUCCESS
)
5691 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5692 return PARSE_OPERAND_FAIL
;
5697 if (inst
.operands
[i
].negative
)
5699 inst
.operands
[i
].negative
= 0;
5702 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5703 return PARSE_OPERAND_FAIL
;
5704 /* If the offset is 0, find out if it's a +0 or -0. */
5705 if (inst
.reloc
.exp
.X_op
== O_constant
5706 && inst
.reloc
.exp
.X_add_number
== 0)
5708 skip_whitespace (q
);
5712 skip_whitespace (q
);
5715 inst
.operands
[i
].negative
= 1;
5721 /* If at this point neither .preind nor .postind is set, we have a
5722 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5723 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5725 inst
.operands
[i
].preind
= 1;
5726 inst
.reloc
.exp
.X_op
= O_constant
;
5727 inst
.reloc
.exp
.X_add_number
= 0;
5730 return PARSE_OPERAND_SUCCESS
;
5734 parse_address (char **str
, int i
)
5736 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5740 static parse_operand_result
5741 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5743 return parse_address_main (str
, i
, 1, type
);
5746 /* Parse an operand for a MOVW or MOVT instruction. */
5748 parse_half (char **str
)
5753 skip_past_char (&p
, '#');
5754 if (strncasecmp (p
, ":lower16:", 9) == 0)
5755 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5756 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5757 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5759 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5762 skip_whitespace (p
);
5765 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5768 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5770 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5772 inst
.error
= _("constant expression expected");
5775 if (inst
.reloc
.exp
.X_add_number
< 0
5776 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5778 inst
.error
= _("immediate value out of range");
5786 /* Miscellaneous. */
5788 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5789 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5791 parse_psr (char **str
, bfd_boolean lhs
)
5794 unsigned long psr_field
;
5795 const struct asm_psr
*psr
;
5797 bfd_boolean is_apsr
= FALSE
;
5798 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5800 /* PR gas/12698: If the user has specified -march=all then m_profile will
5801 be TRUE, but we want to ignore it in this case as we are building for any
5802 CPU type, including non-m variants. */
5803 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5806 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5807 feature for ease of use and backwards compatibility. */
5809 if (strncasecmp (p
, "SPSR", 4) == 0)
5812 goto unsupported_psr
;
5814 psr_field
= SPSR_BIT
;
5816 else if (strncasecmp (p
, "CPSR", 4) == 0)
5819 goto unsupported_psr
;
5823 else if (strncasecmp (p
, "APSR", 4) == 0)
5825 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5826 and ARMv7-R architecture CPUs. */
5835 while (ISALNUM (*p
) || *p
== '_');
5837 if (strncasecmp (start
, "iapsr", 5) == 0
5838 || strncasecmp (start
, "eapsr", 5) == 0
5839 || strncasecmp (start
, "xpsr", 4) == 0
5840 || strncasecmp (start
, "psr", 3) == 0)
5841 p
= start
+ strcspn (start
, "rR") + 1;
5843 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5849 /* If APSR is being written, a bitfield may be specified. Note that
5850 APSR itself is handled above. */
5851 if (psr
->field
<= 3)
5853 psr_field
= psr
->field
;
5859 /* M-profile MSR instructions have the mask field set to "10", except
5860 *PSR variants which modify APSR, which may use a different mask (and
5861 have been handled already). Do that by setting the PSR_f field
5863 return psr
->field
| (lhs
? PSR_f
: 0);
5866 goto unsupported_psr
;
5872 /* A suffix follows. */
5878 while (ISALNUM (*p
) || *p
== '_');
5882 /* APSR uses a notation for bits, rather than fields. */
5883 unsigned int nzcvq_bits
= 0;
5884 unsigned int g_bit
= 0;
5887 for (bit
= start
; bit
!= p
; bit
++)
5889 switch (TOLOWER (*bit
))
5892 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5896 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5900 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5904 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5908 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5912 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5916 inst
.error
= _("unexpected bit specified after APSR");
5921 if (nzcvq_bits
== 0x1f)
5926 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5928 inst
.error
= _("selected processor does not "
5929 "support DSP extension");
5936 if ((nzcvq_bits
& 0x20) != 0
5937 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5938 || (g_bit
& 0x2) != 0)
5940 inst
.error
= _("bad bitmask specified after APSR");
5946 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5951 psr_field
|= psr
->field
;
5957 goto error
; /* Garbage after "[CS]PSR". */
5959 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5960 is deprecated, but allow it anyway. */
5964 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5967 else if (!m_profile
)
5968 /* These bits are never right for M-profile devices: don't set them
5969 (only code paths which read/write APSR reach here). */
5970 psr_field
|= (PSR_c
| PSR_f
);
5976 inst
.error
= _("selected processor does not support requested special "
5977 "purpose register");
5981 inst
.error
= _("flag for {c}psr instruction expected");
5985 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5986 value suitable for splatting into the AIF field of the instruction. */
5989 parse_cps_flags (char **str
)
5998 case '\0': case ',':
6001 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6002 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6003 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6006 inst
.error
= _("unrecognized CPS flag");
6011 if (saw_a_flag
== 0)
6013 inst
.error
= _("missing CPS flags");
6021 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6022 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6025 parse_endian_specifier (char **str
)
6030 if (strncasecmp (s
, "BE", 2))
6032 else if (strncasecmp (s
, "LE", 2))
6036 inst
.error
= _("valid endian specifiers are be or le");
6040 if (ISALNUM (s
[2]) || s
[2] == '_')
6042 inst
.error
= _("valid endian specifiers are be or le");
6047 return little_endian
;
6050 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6051 value suitable for poking into the rotate field of an sxt or sxta
6052 instruction, or FAIL on error. */
6055 parse_ror (char **str
)
6060 if (strncasecmp (s
, "ROR", 3) == 0)
6064 inst
.error
= _("missing rotation field after comma");
6068 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6073 case 0: *str
= s
; return 0x0;
6074 case 8: *str
= s
; return 0x1;
6075 case 16: *str
= s
; return 0x2;
6076 case 24: *str
= s
; return 0x3;
6079 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6084 /* Parse a conditional code (from conds[] below). The value returned is in the
6085 range 0 .. 14, or FAIL. */
6087 parse_cond (char **str
)
6090 const struct asm_cond
*c
;
6092 /* Condition codes are always 2 characters, so matching up to
6093 3 characters is sufficient. */
6098 while (ISALPHA (*q
) && n
< 3)
6100 cond
[n
] = TOLOWER (*q
);
6105 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6108 inst
.error
= _("condition required");
6116 /* Record a use of the given feature. */
6118 record_feature_use (const arm_feature_set
*feature
)
6121 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6123 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6126 /* If the given feature available in the selected CPU, mark it as used.
6127 Returns TRUE iff feature is available. */
6129 mark_feature_used (const arm_feature_set
*feature
)
6131 /* Ensure the option is valid on the current architecture. */
6132 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6135 /* Add the appropriate architecture feature for the barrier option used.
6137 record_feature_use (feature
);
6142 /* Parse an option for a barrier instruction. Returns the encoding for the
6145 parse_barrier (char **str
)
6148 const struct asm_barrier_opt
*o
;
6151 while (ISALPHA (*q
))
6154 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6159 if (!mark_feature_used (&o
->arch
))
6166 /* Parse the operands of a table branch instruction. Similar to a memory
6169 parse_tb (char **str
)
6174 if (skip_past_char (&p
, '[') == FAIL
)
6176 inst
.error
= _("'[' expected");
6180 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6182 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6185 inst
.operands
[0].reg
= reg
;
6187 if (skip_past_comma (&p
) == FAIL
)
6189 inst
.error
= _("',' expected");
6193 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6195 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6198 inst
.operands
[0].imm
= reg
;
6200 if (skip_past_comma (&p
) == SUCCESS
)
6202 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6204 if (inst
.reloc
.exp
.X_add_number
!= 1)
6206 inst
.error
= _("invalid shift");
6209 inst
.operands
[0].shifted
= 1;
6212 if (skip_past_char (&p
, ']') == FAIL
)
6214 inst
.error
= _("']' expected");
6221 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6222 information on the types the operands can take and how they are encoded.
6223 Up to four operands may be read; this function handles setting the
6224 ".present" field for each read operand itself.
6225 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6226 else returns FAIL. */
6229 parse_neon_mov (char **str
, int *which_operand
)
6231 int i
= *which_operand
, val
;
6232 enum arm_reg_type rtype
;
6234 struct neon_type_el optype
;
6236 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6238 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6239 inst
.operands
[i
].reg
= val
;
6240 inst
.operands
[i
].isscalar
= 1;
6241 inst
.operands
[i
].vectype
= optype
;
6242 inst
.operands
[i
++].present
= 1;
6244 if (skip_past_comma (&ptr
) == FAIL
)
6247 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6250 inst
.operands
[i
].reg
= val
;
6251 inst
.operands
[i
].isreg
= 1;
6252 inst
.operands
[i
].present
= 1;
6254 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6257 /* Cases 0, 1, 2, 3, 5 (D only). */
6258 if (skip_past_comma (&ptr
) == FAIL
)
6261 inst
.operands
[i
].reg
= val
;
6262 inst
.operands
[i
].isreg
= 1;
6263 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6264 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6265 inst
.operands
[i
].isvec
= 1;
6266 inst
.operands
[i
].vectype
= optype
;
6267 inst
.operands
[i
++].present
= 1;
6269 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6271 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6272 Case 13: VMOV <Sd>, <Rm> */
6273 inst
.operands
[i
].reg
= val
;
6274 inst
.operands
[i
].isreg
= 1;
6275 inst
.operands
[i
].present
= 1;
6277 if (rtype
== REG_TYPE_NQ
)
6279 first_error (_("can't use Neon quad register here"));
6282 else if (rtype
!= REG_TYPE_VFS
)
6285 if (skip_past_comma (&ptr
) == FAIL
)
6287 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6289 inst
.operands
[i
].reg
= val
;
6290 inst
.operands
[i
].isreg
= 1;
6291 inst
.operands
[i
].present
= 1;
6294 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6297 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6298 Case 1: VMOV<c><q> <Dd>, <Dm>
6299 Case 8: VMOV.F32 <Sd>, <Sm>
6300 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6302 inst
.operands
[i
].reg
= val
;
6303 inst
.operands
[i
].isreg
= 1;
6304 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6305 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6306 inst
.operands
[i
].isvec
= 1;
6307 inst
.operands
[i
].vectype
= optype
;
6308 inst
.operands
[i
].present
= 1;
6310 if (skip_past_comma (&ptr
) == SUCCESS
)
6315 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6318 inst
.operands
[i
].reg
= val
;
6319 inst
.operands
[i
].isreg
= 1;
6320 inst
.operands
[i
++].present
= 1;
6322 if (skip_past_comma (&ptr
) == FAIL
)
6325 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6328 inst
.operands
[i
].reg
= val
;
6329 inst
.operands
[i
].isreg
= 1;
6330 inst
.operands
[i
].present
= 1;
6333 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6334 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6335 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6336 Case 10: VMOV.F32 <Sd>, #<imm>
6337 Case 11: VMOV.F64 <Dd>, #<imm> */
6338 inst
.operands
[i
].immisfloat
= 1;
6339 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6341 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6342 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6346 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6350 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6353 inst
.operands
[i
].reg
= val
;
6354 inst
.operands
[i
].isreg
= 1;
6355 inst
.operands
[i
++].present
= 1;
6357 if (skip_past_comma (&ptr
) == FAIL
)
6360 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6362 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6363 inst
.operands
[i
].reg
= val
;
6364 inst
.operands
[i
].isscalar
= 1;
6365 inst
.operands
[i
].present
= 1;
6366 inst
.operands
[i
].vectype
= optype
;
6368 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6370 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6371 inst
.operands
[i
].reg
= val
;
6372 inst
.operands
[i
].isreg
= 1;
6373 inst
.operands
[i
++].present
= 1;
6375 if (skip_past_comma (&ptr
) == FAIL
)
6378 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6381 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6385 inst
.operands
[i
].reg
= val
;
6386 inst
.operands
[i
].isreg
= 1;
6387 inst
.operands
[i
].isvec
= 1;
6388 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6389 inst
.operands
[i
].vectype
= optype
;
6390 inst
.operands
[i
].present
= 1;
6392 if (rtype
== REG_TYPE_VFS
)
6396 if (skip_past_comma (&ptr
) == FAIL
)
6398 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6401 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6404 inst
.operands
[i
].reg
= val
;
6405 inst
.operands
[i
].isreg
= 1;
6406 inst
.operands
[i
].isvec
= 1;
6407 inst
.operands
[i
].issingle
= 1;
6408 inst
.operands
[i
].vectype
= optype
;
6409 inst
.operands
[i
].present
= 1;
6412 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6416 inst
.operands
[i
].reg
= val
;
6417 inst
.operands
[i
].isreg
= 1;
6418 inst
.operands
[i
].isvec
= 1;
6419 inst
.operands
[i
].issingle
= 1;
6420 inst
.operands
[i
].vectype
= optype
;
6421 inst
.operands
[i
].present
= 1;
6426 first_error (_("parse error"));
6430 /* Successfully parsed the operands. Update args. */
6436 first_error (_("expected comma"));
6440 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6444 /* Use this macro when the operand constraints are different
6445 for ARM and THUMB (e.g. ldrd). */
6446 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6447 ((arm_operand) | ((thumb_operand) << 16))
6449 /* Matcher codes for parse_operands. */
6450 enum operand_parse_code
6452 OP_stop
, /* end of line */
6454 OP_RR
, /* ARM register */
6455 OP_RRnpc
, /* ARM register, not r15 */
6456 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6457 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6458 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6459 optional trailing ! */
6460 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6461 OP_RCP
, /* Coprocessor number */
6462 OP_RCN
, /* Coprocessor register */
6463 OP_RF
, /* FPA register */
6464 OP_RVS
, /* VFP single precision register */
6465 OP_RVD
, /* VFP double precision register (0..15) */
6466 OP_RND
, /* Neon double precision register (0..31) */
6467 OP_RNQ
, /* Neon quad precision register */
6468 OP_RVSD
, /* VFP single or double precision register */
6469 OP_RNDQ
, /* Neon double or quad precision register */
6470 OP_RNSDQ
, /* Neon single, double or quad precision register */
6471 OP_RNSC
, /* Neon scalar D[X] */
6472 OP_RVC
, /* VFP control register */
6473 OP_RMF
, /* Maverick F register */
6474 OP_RMD
, /* Maverick D register */
6475 OP_RMFX
, /* Maverick FX register */
6476 OP_RMDX
, /* Maverick DX register */
6477 OP_RMAX
, /* Maverick AX register */
6478 OP_RMDS
, /* Maverick DSPSC register */
6479 OP_RIWR
, /* iWMMXt wR register */
6480 OP_RIWC
, /* iWMMXt wC register */
6481 OP_RIWG
, /* iWMMXt wCG register */
6482 OP_RXA
, /* XScale accumulator register */
6484 OP_REGLST
, /* ARM register list */
6485 OP_VRSLST
, /* VFP single-precision register list */
6486 OP_VRDLST
, /* VFP double-precision register list */
6487 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6488 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6489 OP_NSTRLST
, /* Neon element/structure list */
6491 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6492 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6493 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6494 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6495 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6496 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6497 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6498 OP_VMOV
, /* Neon VMOV operands. */
6499 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6500 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6501 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6503 OP_I0
, /* immediate zero */
6504 OP_I7
, /* immediate value 0 .. 7 */
6505 OP_I15
, /* 0 .. 15 */
6506 OP_I16
, /* 1 .. 16 */
6507 OP_I16z
, /* 0 .. 16 */
6508 OP_I31
, /* 0 .. 31 */
6509 OP_I31w
, /* 0 .. 31, optional trailing ! */
6510 OP_I32
, /* 1 .. 32 */
6511 OP_I32z
, /* 0 .. 32 */
6512 OP_I63
, /* 0 .. 63 */
6513 OP_I63s
, /* -64 .. 63 */
6514 OP_I64
, /* 1 .. 64 */
6515 OP_I64z
, /* 0 .. 64 */
6516 OP_I255
, /* 0 .. 255 */
6518 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6519 OP_I7b
, /* 0 .. 7 */
6520 OP_I15b
, /* 0 .. 15 */
6521 OP_I31b
, /* 0 .. 31 */
6523 OP_SH
, /* shifter operand */
6524 OP_SHG
, /* shifter operand with possible group relocation */
6525 OP_ADDR
, /* Memory address expression (any mode) */
6526 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6527 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6528 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6529 OP_EXP
, /* arbitrary expression */
6530 OP_EXPi
, /* same, with optional immediate prefix */
6531 OP_EXPr
, /* same, with optional relocation suffix */
6532 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6534 OP_CPSF
, /* CPS flags */
6535 OP_ENDI
, /* Endianness specifier */
6536 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6537 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6538 OP_COND
, /* conditional code */
6539 OP_TB
, /* Table branch. */
6541 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6543 OP_RRnpc_I0
, /* ARM register or literal 0 */
6544 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6545 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6546 OP_RF_IF
, /* FPA register or immediate */
6547 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6548 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6550 /* Optional operands. */
6551 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6552 OP_oI31b
, /* 0 .. 31 */
6553 OP_oI32b
, /* 1 .. 32 */
6554 OP_oI32z
, /* 0 .. 32 */
6555 OP_oIffffb
, /* 0 .. 65535 */
6556 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6558 OP_oRR
, /* ARM register */
6559 OP_oRRnpc
, /* ARM register, not the PC */
6560 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6561 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6562 OP_oRND
, /* Optional Neon double precision register */
6563 OP_oRNQ
, /* Optional Neon quad precision register */
6564 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6565 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6566 OP_oSHll
, /* LSL immediate */
6567 OP_oSHar
, /* ASR immediate */
6568 OP_oSHllar
, /* LSL or ASR immediate */
6569 OP_oROR
, /* ROR 0/8/16/24 */
6570 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6572 /* Some pre-defined mixed (ARM/THUMB) operands. */
6573 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6574 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6575 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6577 OP_FIRST_OPTIONAL
= OP_oI7b
6580 /* Generic instruction operand parser. This does no encoding and no
6581 semantic validation; it merely squirrels values away in the inst
6582 structure. Returns SUCCESS or FAIL depending on whether the
6583 specified grammar matched. */
6585 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6587 unsigned const int *upat
= pattern
;
6588 char *backtrack_pos
= 0;
6589 const char *backtrack_error
= 0;
6590 int i
, val
= 0, backtrack_index
= 0;
6591 enum arm_reg_type rtype
;
6592 parse_operand_result result
;
6593 unsigned int op_parse_code
;
6595 #define po_char_or_fail(chr) \
6598 if (skip_past_char (&str, chr) == FAIL) \
6603 #define po_reg_or_fail(regtype) \
6606 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6607 & inst.operands[i].vectype); \
6610 first_error (_(reg_expected_msgs[regtype])); \
6613 inst.operands[i].reg = val; \
6614 inst.operands[i].isreg = 1; \
6615 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6616 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6617 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6618 || rtype == REG_TYPE_VFD \
6619 || rtype == REG_TYPE_NQ); \
6623 #define po_reg_or_goto(regtype, label) \
6626 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6627 & inst.operands[i].vectype); \
6631 inst.operands[i].reg = val; \
6632 inst.operands[i].isreg = 1; \
6633 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6634 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6635 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6636 || rtype == REG_TYPE_VFD \
6637 || rtype == REG_TYPE_NQ); \
6641 #define po_imm_or_fail(min, max, popt) \
6644 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6646 inst.operands[i].imm = val; \
6650 #define po_scalar_or_goto(elsz, label) \
6653 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6656 inst.operands[i].reg = val; \
6657 inst.operands[i].isscalar = 1; \
6661 #define po_misc_or_fail(expr) \
6669 #define po_misc_or_fail_no_backtrack(expr) \
6673 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6674 backtrack_pos = 0; \
6675 if (result != PARSE_OPERAND_SUCCESS) \
6680 #define po_barrier_or_imm(str) \
6683 val = parse_barrier (&str); \
6684 if (val == FAIL && ! ISALPHA (*str)) \
6687 /* ISB can only take SY as an option. */ \
6688 || ((inst.instruction & 0xf0) == 0x60 \
6691 inst.error = _("invalid barrier type"); \
6692 backtrack_pos = 0; \
6698 skip_whitespace (str
);
6700 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6702 op_parse_code
= upat
[i
];
6703 if (op_parse_code
>= 1<<16)
6704 op_parse_code
= thumb
? (op_parse_code
>> 16)
6705 : (op_parse_code
& ((1<<16)-1));
6707 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6709 /* Remember where we are in case we need to backtrack. */
6710 gas_assert (!backtrack_pos
);
6711 backtrack_pos
= str
;
6712 backtrack_error
= inst
.error
;
6713 backtrack_index
= i
;
6716 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6717 po_char_or_fail (',');
6719 switch (op_parse_code
)
6727 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6728 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6729 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6730 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6731 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6732 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6734 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6736 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6738 /* Also accept generic coprocessor regs for unknown registers. */
6740 po_reg_or_fail (REG_TYPE_CN
);
6742 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6743 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6744 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6745 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6746 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6747 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6748 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6749 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6750 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6751 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6753 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6755 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6756 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6758 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6760 /* Neon scalar. Using an element size of 8 means that some invalid
6761 scalars are accepted here, so deal with those in later code. */
6762 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6766 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6769 po_imm_or_fail (0, 0, TRUE
);
6774 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6779 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6782 if (parse_ifimm_zero (&str
))
6783 inst
.operands
[i
].imm
= 0;
6787 = _("only floating point zero is allowed as immediate value");
6795 po_scalar_or_goto (8, try_rr
);
6798 po_reg_or_fail (REG_TYPE_RN
);
6804 po_scalar_or_goto (8, try_nsdq
);
6807 po_reg_or_fail (REG_TYPE_NSDQ
);
6813 po_scalar_or_goto (8, try_ndq
);
6816 po_reg_or_fail (REG_TYPE_NDQ
);
6822 po_scalar_or_goto (8, try_vfd
);
6825 po_reg_or_fail (REG_TYPE_VFD
);
6830 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6831 not careful then bad things might happen. */
6832 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6837 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6840 /* There's a possibility of getting a 64-bit immediate here, so
6841 we need special handling. */
6842 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6845 inst
.error
= _("immediate value is out of range");
6853 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6856 po_imm_or_fail (0, 63, TRUE
);
6861 po_char_or_fail ('[');
6862 po_reg_or_fail (REG_TYPE_RN
);
6863 po_char_or_fail (']');
6869 po_reg_or_fail (REG_TYPE_RN
);
6870 if (skip_past_char (&str
, '!') == SUCCESS
)
6871 inst
.operands
[i
].writeback
= 1;
6875 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6876 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6877 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6878 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6879 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6880 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6881 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6882 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6883 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6884 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6885 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6886 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6888 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6890 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6891 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6893 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6894 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6895 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6896 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6898 /* Immediate variants */
6900 po_char_or_fail ('{');
6901 po_imm_or_fail (0, 255, TRUE
);
6902 po_char_or_fail ('}');
6906 /* The expression parser chokes on a trailing !, so we have
6907 to find it first and zap it. */
6910 while (*s
&& *s
!= ',')
6915 inst
.operands
[i
].writeback
= 1;
6917 po_imm_or_fail (0, 31, TRUE
);
6925 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6930 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6935 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6937 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6939 val
= parse_reloc (&str
);
6942 inst
.error
= _("unrecognized relocation suffix");
6945 else if (val
!= BFD_RELOC_UNUSED
)
6947 inst
.operands
[i
].imm
= val
;
6948 inst
.operands
[i
].hasreloc
= 1;
6953 /* Operand for MOVW or MOVT. */
6955 po_misc_or_fail (parse_half (&str
));
6958 /* Register or expression. */
6959 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6960 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6962 /* Register or immediate. */
6963 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6964 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6966 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6968 if (!is_immediate_prefix (*str
))
6971 val
= parse_fpa_immediate (&str
);
6974 /* FPA immediates are encoded as registers 8-15.
6975 parse_fpa_immediate has already applied the offset. */
6976 inst
.operands
[i
].reg
= val
;
6977 inst
.operands
[i
].isreg
= 1;
6980 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6981 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6983 /* Two kinds of register. */
6986 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6988 || (rege
->type
!= REG_TYPE_MMXWR
6989 && rege
->type
!= REG_TYPE_MMXWC
6990 && rege
->type
!= REG_TYPE_MMXWCG
))
6992 inst
.error
= _("iWMMXt data or control register expected");
6995 inst
.operands
[i
].reg
= rege
->number
;
6996 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7002 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7004 || (rege
->type
!= REG_TYPE_MMXWC
7005 && rege
->type
!= REG_TYPE_MMXWCG
))
7007 inst
.error
= _("iWMMXt control register expected");
7010 inst
.operands
[i
].reg
= rege
->number
;
7011 inst
.operands
[i
].isreg
= 1;
7016 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7017 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7018 case OP_oROR
: val
= parse_ror (&str
); break;
7019 case OP_COND
: val
= parse_cond (&str
); break;
7020 case OP_oBARRIER_I15
:
7021 po_barrier_or_imm (str
); break;
7023 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7029 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7030 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7032 inst
.error
= _("Banked registers are not available with this "
7038 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7042 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7045 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7047 if (strncasecmp (str
, "APSR_", 5) == 0)
7054 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7055 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7056 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7057 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7058 default: found
= 16;
7062 inst
.operands
[i
].isvec
= 1;
7063 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7064 inst
.operands
[i
].reg
= REG_PC
;
7071 po_misc_or_fail (parse_tb (&str
));
7074 /* Register lists. */
7076 val
= parse_reg_list (&str
);
7079 inst
.operands
[i
].writeback
= 1;
7085 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7089 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7093 /* Allow Q registers too. */
7094 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7099 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7101 inst
.operands
[i
].issingle
= 1;
7106 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7111 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7112 &inst
.operands
[i
].vectype
);
7115 /* Addressing modes */
7117 po_misc_or_fail (parse_address (&str
, i
));
7121 po_misc_or_fail_no_backtrack (
7122 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7126 po_misc_or_fail_no_backtrack (
7127 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7131 po_misc_or_fail_no_backtrack (
7132 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7136 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7140 po_misc_or_fail_no_backtrack (
7141 parse_shifter_operand_group_reloc (&str
, i
));
7145 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7149 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7153 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7157 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7160 /* Various value-based sanity checks and shared operations. We
7161 do not signal immediate failures for the register constraints;
7162 this allows a syntax error to take precedence. */
7163 switch (op_parse_code
)
7171 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7172 inst
.error
= BAD_PC
;
7177 if (inst
.operands
[i
].isreg
)
7179 if (inst
.operands
[i
].reg
== REG_PC
)
7180 inst
.error
= BAD_PC
;
7181 else if (inst
.operands
[i
].reg
== REG_SP
)
7182 inst
.error
= BAD_SP
;
7187 if (inst
.operands
[i
].isreg
7188 && inst
.operands
[i
].reg
== REG_PC
7189 && (inst
.operands
[i
].writeback
|| thumb
))
7190 inst
.error
= BAD_PC
;
7199 case OP_oBARRIER_I15
:
7208 inst
.operands
[i
].imm
= val
;
7215 /* If we get here, this operand was successfully parsed. */
7216 inst
.operands
[i
].present
= 1;
7220 inst
.error
= BAD_ARGS
;
7225 /* The parse routine should already have set inst.error, but set a
7226 default here just in case. */
7228 inst
.error
= _("syntax error");
7232 /* Do not backtrack over a trailing optional argument that
7233 absorbed some text. We will only fail again, with the
7234 'garbage following instruction' error message, which is
7235 probably less helpful than the current one. */
7236 if (backtrack_index
== i
&& backtrack_pos
!= str
7237 && upat
[i
+1] == OP_stop
)
7240 inst
.error
= _("syntax error");
7244 /* Try again, skipping the optional argument at backtrack_pos. */
7245 str
= backtrack_pos
;
7246 inst
.error
= backtrack_error
;
7247 inst
.operands
[backtrack_index
].present
= 0;
7248 i
= backtrack_index
;
7252 /* Check that we have parsed all the arguments. */
7253 if (*str
!= '\0' && !inst
.error
)
7254 inst
.error
= _("garbage following instruction");
7256 return inst
.error
? FAIL
: SUCCESS
;
7259 #undef po_char_or_fail
7260 #undef po_reg_or_fail
7261 #undef po_reg_or_goto
7262 #undef po_imm_or_fail
7263 #undef po_scalar_or_fail
7264 #undef po_barrier_or_imm
7266 /* Shorthand macro for instruction encoding functions issuing errors. */
7267 #define constraint(expr, err) \
7278 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7279 instructions are unpredictable if these registers are used. This
7280 is the BadReg predicate in ARM's Thumb-2 documentation. */
7281 #define reject_bad_reg(reg) \
7283 if (reg == REG_SP || reg == REG_PC) \
7285 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7290 /* If REG is R13 (the stack pointer), warn that its use is
7292 #define warn_deprecated_sp(reg) \
7294 if (warn_on_deprecated && reg == REG_SP) \
7295 as_tsktsk (_("use of r13 is deprecated")); \
7298 /* Functions for operand encoding. ARM, then Thumb. */
7300 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7302 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7304 The only binary encoding difference is the Coprocessor number. Coprocessor
7305 9 is used for half-precision calculations or conversions. The format of the
7306 instruction is the same as the equivalent Coprocessor 10 instuction that
7307 exists for Single-Precision operation. */
7310 do_scalar_fp16_v82_encode (void)
7312 if (inst
.cond
!= COND_ALWAYS
)
7313 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7314 " the behaviour is UNPREDICTABLE"));
7315 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7318 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7319 mark_feature_used (&arm_ext_fp16
);
7322 /* If VAL can be encoded in the immediate field of an ARM instruction,
7323 return the encoded form. Otherwise, return FAIL. */
7326 encode_arm_immediate (unsigned int val
)
7333 for (i
= 2; i
< 32; i
+= 2)
7334 if ((a
= rotate_left (val
, i
)) <= 0xff)
7335 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7340 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7341 return the encoded form. Otherwise, return FAIL. */
7343 encode_thumb32_immediate (unsigned int val
)
7350 for (i
= 1; i
<= 24; i
++)
7353 if ((val
& ~(0xff << i
)) == 0)
7354 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7358 if (val
== ((a
<< 16) | a
))
7360 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7364 if (val
== ((a
<< 16) | a
))
7365 return 0x200 | (a
>> 8);
7369 /* Encode a VFP SP or DP register number into inst.instruction. */
7372 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7374 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7377 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7380 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7383 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7388 first_error (_("D register out of range for selected VFP version"));
7396 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7400 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7404 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7408 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7412 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7416 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7424 /* Encode a <shift> in an ARM-format instruction. The immediate,
7425 if any, is handled by md_apply_fix. */
7427 encode_arm_shift (int i
)
7429 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7430 inst
.instruction
|= SHIFT_ROR
<< 5;
7433 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7434 if (inst
.operands
[i
].immisreg
)
7436 inst
.instruction
|= SHIFT_BY_REG
;
7437 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7440 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7445 encode_arm_shifter_operand (int i
)
7447 if (inst
.operands
[i
].isreg
)
7449 inst
.instruction
|= inst
.operands
[i
].reg
;
7450 encode_arm_shift (i
);
7454 inst
.instruction
|= INST_IMMEDIATE
;
7455 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7456 inst
.instruction
|= inst
.operands
[i
].imm
;
7460 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7462 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7465 Generate an error if the operand is not a register. */
7466 constraint (!inst
.operands
[i
].isreg
,
7467 _("Instruction does not support =N addresses"));
7469 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7471 if (inst
.operands
[i
].preind
)
7475 inst
.error
= _("instruction does not accept preindexed addressing");
7478 inst
.instruction
|= PRE_INDEX
;
7479 if (inst
.operands
[i
].writeback
)
7480 inst
.instruction
|= WRITE_BACK
;
7483 else if (inst
.operands
[i
].postind
)
7485 gas_assert (inst
.operands
[i
].writeback
);
7487 inst
.instruction
|= WRITE_BACK
;
7489 else /* unindexed - only for coprocessor */
7491 inst
.error
= _("instruction does not accept unindexed addressing");
7495 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7496 && (((inst
.instruction
& 0x000f0000) >> 16)
7497 == ((inst
.instruction
& 0x0000f000) >> 12)))
7498 as_warn ((inst
.instruction
& LOAD_BIT
)
7499 ? _("destination register same as write-back base")
7500 : _("source register same as write-back base"));
7503 /* inst.operands[i] was set up by parse_address. Encode it into an
7504 ARM-format mode 2 load or store instruction. If is_t is true,
7505 reject forms that cannot be used with a T instruction (i.e. not
7508 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7510 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7512 encode_arm_addr_mode_common (i
, is_t
);
7514 if (inst
.operands
[i
].immisreg
)
7516 constraint ((inst
.operands
[i
].imm
== REG_PC
7517 || (is_pc
&& inst
.operands
[i
].writeback
)),
7519 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7520 inst
.instruction
|= inst
.operands
[i
].imm
;
7521 if (!inst
.operands
[i
].negative
)
7522 inst
.instruction
|= INDEX_UP
;
7523 if (inst
.operands
[i
].shifted
)
7525 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7526 inst
.instruction
|= SHIFT_ROR
<< 5;
7529 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7530 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7534 else /* immediate offset in inst.reloc */
7536 if (is_pc
&& !inst
.reloc
.pc_rel
)
7538 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7540 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7541 cannot use PC in addressing.
7542 PC cannot be used in writeback addressing, either. */
7543 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7546 /* Use of PC in str is deprecated for ARMv7. */
7547 if (warn_on_deprecated
7549 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7550 as_tsktsk (_("use of PC in this instruction is deprecated"));
7553 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7555 /* Prefer + for zero encoded value. */
7556 if (!inst
.operands
[i
].negative
)
7557 inst
.instruction
|= INDEX_UP
;
7558 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7563 /* inst.operands[i] was set up by parse_address. Encode it into an
7564 ARM-format mode 3 load or store instruction. Reject forms that
7565 cannot be used with such instructions. If is_t is true, reject
7566 forms that cannot be used with a T instruction (i.e. not
7569 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7571 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7573 inst
.error
= _("instruction does not accept scaled register index");
7577 encode_arm_addr_mode_common (i
, is_t
);
7579 if (inst
.operands
[i
].immisreg
)
7581 constraint ((inst
.operands
[i
].imm
== REG_PC
7582 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7584 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7586 inst
.instruction
|= inst
.operands
[i
].imm
;
7587 if (!inst
.operands
[i
].negative
)
7588 inst
.instruction
|= INDEX_UP
;
7590 else /* immediate offset in inst.reloc */
7592 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7593 && inst
.operands
[i
].writeback
),
7595 inst
.instruction
|= HWOFFSET_IMM
;
7596 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7598 /* Prefer + for zero encoded value. */
7599 if (!inst
.operands
[i
].negative
)
7600 inst
.instruction
|= INDEX_UP
;
7602 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7607 /* Write immediate bits [7:0] to the following locations:
7609 |28/24|23 19|18 16|15 4|3 0|
7610 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7612 This function is used by VMOV/VMVN/VORR/VBIC. */
7615 neon_write_immbits (unsigned immbits
)
7617 inst
.instruction
|= immbits
& 0xf;
7618 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7619 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7622 /* Invert low-order SIZE bits of XHI:XLO. */
7625 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7627 unsigned immlo
= xlo
? *xlo
: 0;
7628 unsigned immhi
= xhi
? *xhi
: 0;
7633 immlo
= (~immlo
) & 0xff;
7637 immlo
= (~immlo
) & 0xffff;
7641 immhi
= (~immhi
) & 0xffffffff;
7645 immlo
= (~immlo
) & 0xffffffff;
7659 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7663 neon_bits_same_in_bytes (unsigned imm
)
7665 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7666 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7667 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7668 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7671 /* For immediate of above form, return 0bABCD. */
7674 neon_squash_bits (unsigned imm
)
7676 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7677 | ((imm
& 0x01000000) >> 21);
7680 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7683 neon_qfloat_bits (unsigned imm
)
7685 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7688 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7689 the instruction. *OP is passed as the initial value of the op field, and
7690 may be set to a different value depending on the constant (i.e.
7691 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7692 MVN). If the immediate looks like a repeated pattern then also
7693 try smaller element sizes. */
7696 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7697 unsigned *immbits
, int *op
, int size
,
7698 enum neon_el_type type
)
7700 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7702 if (type
== NT_float
&& !float_p
)
7705 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7707 if (size
!= 32 || *op
== 1)
7709 *immbits
= neon_qfloat_bits (immlo
);
7715 if (neon_bits_same_in_bytes (immhi
)
7716 && neon_bits_same_in_bytes (immlo
))
7720 *immbits
= (neon_squash_bits (immhi
) << 4)
7721 | neon_squash_bits (immlo
);
7732 if (immlo
== (immlo
& 0x000000ff))
7737 else if (immlo
== (immlo
& 0x0000ff00))
7739 *immbits
= immlo
>> 8;
7742 else if (immlo
== (immlo
& 0x00ff0000))
7744 *immbits
= immlo
>> 16;
7747 else if (immlo
== (immlo
& 0xff000000))
7749 *immbits
= immlo
>> 24;
7752 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7754 *immbits
= (immlo
>> 8) & 0xff;
7757 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7759 *immbits
= (immlo
>> 16) & 0xff;
7763 if ((immlo
& 0xffff) != (immlo
>> 16))
7770 if (immlo
== (immlo
& 0x000000ff))
7775 else if (immlo
== (immlo
& 0x0000ff00))
7777 *immbits
= immlo
>> 8;
7781 if ((immlo
& 0xff) != (immlo
>> 8))
7786 if (immlo
== (immlo
& 0x000000ff))
7788 /* Don't allow MVN with 8-bit immediate. */
7798 #if defined BFD_HOST_64_BIT
7799 /* Returns TRUE if double precision value V may be cast
7800 to single precision without loss of accuracy. */
7803 is_double_a_single (bfd_int64_t v
)
7805 int exp
= (int)((v
>> 52) & 0x7FF);
7806 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7808 return (exp
== 0 || exp
== 0x7FF
7809 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7810 && (mantissa
& 0x1FFFFFFFl
) == 0;
7813 /* Returns a double precision value casted to single precision
7814 (ignoring the least significant bits in exponent and mantissa). */
7817 double_to_single (bfd_int64_t v
)
7819 int sign
= (int) ((v
>> 63) & 1l);
7820 int exp
= (int) ((v
>> 52) & 0x7FF);
7821 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7827 exp
= exp
- 1023 + 127;
7836 /* No denormalized numbers. */
7842 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7844 #endif /* BFD_HOST_64_BIT */
7853 static void do_vfp_nsyn_opcode (const char *);
7855 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7856 Determine whether it can be performed with a move instruction; if
7857 it can, convert inst.instruction to that move instruction and
7858 return TRUE; if it can't, convert inst.instruction to a literal-pool
7859 load and return FALSE. If this is not a valid thing to do in the
7860 current context, set inst.error and return TRUE.
7862 inst.operands[i] describes the destination register. */
7865 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7868 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7869 bfd_boolean arm_p
= (t
== CONST_ARM
);
7872 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7876 if ((inst
.instruction
& tbit
) == 0)
7878 inst
.error
= _("invalid pseudo operation");
7882 if (inst
.reloc
.exp
.X_op
!= O_constant
7883 && inst
.reloc
.exp
.X_op
!= O_symbol
7884 && inst
.reloc
.exp
.X_op
!= O_big
)
7886 inst
.error
= _("constant expression expected");
7890 if (inst
.reloc
.exp
.X_op
== O_constant
7891 || inst
.reloc
.exp
.X_op
== O_big
)
7893 #if defined BFD_HOST_64_BIT
7898 if (inst
.reloc
.exp
.X_op
== O_big
)
7900 LITTLENUM_TYPE w
[X_PRECISION
];
7903 if (inst
.reloc
.exp
.X_add_number
== -1)
7905 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7907 /* FIXME: Should we check words w[2..5] ? */
7912 #if defined BFD_HOST_64_BIT
7914 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7915 << LITTLENUM_NUMBER_OF_BITS
)
7916 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7917 << LITTLENUM_NUMBER_OF_BITS
)
7918 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7919 << LITTLENUM_NUMBER_OF_BITS
)
7920 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7922 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7923 | (l
[0] & LITTLENUM_MASK
);
7927 v
= inst
.reloc
.exp
.X_add_number
;
7929 if (!inst
.operands
[i
].issingle
)
7933 /* This can be encoded only for a low register. */
7934 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7936 /* This can be done with a mov(1) instruction. */
7937 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7938 inst
.instruction
|= v
;
7942 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7943 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7945 /* Check if on thumb2 it can be done with a mov.w, mvn or
7946 movw instruction. */
7947 unsigned int newimm
;
7948 bfd_boolean isNegated
;
7950 newimm
= encode_thumb32_immediate (v
);
7951 if (newimm
!= (unsigned int) FAIL
)
7955 newimm
= encode_thumb32_immediate (~v
);
7956 if (newimm
!= (unsigned int) FAIL
)
7960 /* The number can be loaded with a mov.w or mvn
7962 if (newimm
!= (unsigned int) FAIL
7963 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7965 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7966 | (inst
.operands
[i
].reg
<< 8));
7967 /* Change to MOVN. */
7968 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7969 inst
.instruction
|= (newimm
& 0x800) << 15;
7970 inst
.instruction
|= (newimm
& 0x700) << 4;
7971 inst
.instruction
|= (newimm
& 0x0ff);
7974 /* The number can be loaded with a movw instruction. */
7975 else if ((v
& ~0xFFFF) == 0
7976 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7978 int imm
= v
& 0xFFFF;
7980 inst
.instruction
= 0xf2400000; /* MOVW. */
7981 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7982 inst
.instruction
|= (imm
& 0xf000) << 4;
7983 inst
.instruction
|= (imm
& 0x0800) << 15;
7984 inst
.instruction
|= (imm
& 0x0700) << 4;
7985 inst
.instruction
|= (imm
& 0x00ff);
7992 int value
= encode_arm_immediate (v
);
7996 /* This can be done with a mov instruction. */
7997 inst
.instruction
&= LITERAL_MASK
;
7998 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7999 inst
.instruction
|= value
& 0xfff;
8003 value
= encode_arm_immediate (~ v
);
8006 /* This can be done with a mvn instruction. */
8007 inst
.instruction
&= LITERAL_MASK
;
8008 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8009 inst
.instruction
|= value
& 0xfff;
8013 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8016 unsigned immbits
= 0;
8017 unsigned immlo
= inst
.operands
[1].imm
;
8018 unsigned immhi
= inst
.operands
[1].regisimm
8019 ? inst
.operands
[1].reg
8020 : inst
.reloc
.exp
.X_unsigned
8022 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8023 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8024 &op
, 64, NT_invtype
);
8028 neon_invert_size (&immlo
, &immhi
, 64);
8030 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8031 &op
, 64, NT_invtype
);
8036 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8042 /* Fill other bits in vmov encoding for both thumb and arm. */
8044 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8046 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8047 neon_write_immbits (immbits
);
8055 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8056 if (inst
.operands
[i
].issingle
8057 && is_quarter_float (inst
.operands
[1].imm
)
8058 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8060 inst
.operands
[1].imm
=
8061 neon_qfloat_bits (v
);
8062 do_vfp_nsyn_opcode ("fconsts");
8066 /* If our host does not support a 64-bit type then we cannot perform
8067 the following optimization. This mean that there will be a
8068 discrepancy between the output produced by an assembler built for
8069 a 32-bit-only host and the output produced from a 64-bit host, but
8070 this cannot be helped. */
8071 #if defined BFD_HOST_64_BIT
8072 else if (!inst
.operands
[1].issingle
8073 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8075 if (is_double_a_single (v
)
8076 && is_quarter_float (double_to_single (v
)))
8078 inst
.operands
[1].imm
=
8079 neon_qfloat_bits (double_to_single (v
));
8080 do_vfp_nsyn_opcode ("fconstd");
8088 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8089 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8092 inst
.operands
[1].reg
= REG_PC
;
8093 inst
.operands
[1].isreg
= 1;
8094 inst
.operands
[1].preind
= 1;
8095 inst
.reloc
.pc_rel
= 1;
8096 inst
.reloc
.type
= (thumb_p
8097 ? BFD_RELOC_ARM_THUMB_OFFSET
8099 ? BFD_RELOC_ARM_HWLITERAL
8100 : BFD_RELOC_ARM_LITERAL
));
8104 /* inst.operands[i] was set up by parse_address. Encode it into an
8105 ARM-format instruction. Reject all forms which cannot be encoded
8106 into a coprocessor load/store instruction. If wb_ok is false,
8107 reject use of writeback; if unind_ok is false, reject use of
8108 unindexed addressing. If reloc_override is not 0, use it instead
8109 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8110 (in which case it is preserved). */
8113 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8115 if (!inst
.operands
[i
].isreg
)
8118 if (! inst
.operands
[0].isvec
)
8120 inst
.error
= _("invalid co-processor operand");
8123 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8127 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8129 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8131 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8133 gas_assert (!inst
.operands
[i
].writeback
);
8136 inst
.error
= _("instruction does not support unindexed addressing");
8139 inst
.instruction
|= inst
.operands
[i
].imm
;
8140 inst
.instruction
|= INDEX_UP
;
8144 if (inst
.operands
[i
].preind
)
8145 inst
.instruction
|= PRE_INDEX
;
8147 if (inst
.operands
[i
].writeback
)
8149 if (inst
.operands
[i
].reg
== REG_PC
)
8151 inst
.error
= _("pc may not be used with write-back");
8156 inst
.error
= _("instruction does not support writeback");
8159 inst
.instruction
|= WRITE_BACK
;
8163 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8164 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8165 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8166 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8169 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8171 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8174 /* Prefer + for zero encoded value. */
8175 if (!inst
.operands
[i
].negative
)
8176 inst
.instruction
|= INDEX_UP
;
8181 /* Functions for instruction encoding, sorted by sub-architecture.
8182 First some generics; their names are taken from the conventional
8183 bit positions for register arguments in ARM format instructions. */
8193 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8199 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8205 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8206 inst
.instruction
|= inst
.operands
[1].reg
;
8212 inst
.instruction
|= inst
.operands
[0].reg
;
8213 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8220 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8226 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8227 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8233 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8234 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8238 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8240 if (ARM_CPU_IS_ANY (cpu_variant
))
8242 as_tsktsk ("%s", msg
);
8245 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8257 unsigned Rn
= inst
.operands
[2].reg
;
8258 /* Enforce restrictions on SWP instruction. */
8259 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8261 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8262 _("Rn must not overlap other operands"));
8264 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8266 if (!check_obsolete (&arm_ext_v8
,
8267 _("swp{b} use is obsoleted for ARMv8 and later"))
8268 && warn_on_deprecated
8269 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8270 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8273 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8274 inst
.instruction
|= inst
.operands
[1].reg
;
8275 inst
.instruction
|= Rn
<< 16;
8281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8282 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8283 inst
.instruction
|= inst
.operands
[2].reg
;
8289 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8290 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8291 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8292 || inst
.reloc
.exp
.X_add_number
!= 0),
8294 inst
.instruction
|= inst
.operands
[0].reg
;
8295 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8296 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8302 inst
.instruction
|= inst
.operands
[0].imm
;
8308 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8309 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8312 /* ARM instructions, in alphabetical order by function name (except
8313 that wrapper functions appear immediately after the function they
8316 /* This is a pseudo-op of the form "adr rd, label" to be converted
8317 into a relative address of the form "add rd, pc, #label-.-8". */
8322 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8324 /* Frag hacking will turn this into a sub instruction if the offset turns
8325 out to be negative. */
8326 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8327 inst
.reloc
.pc_rel
= 1;
8328 inst
.reloc
.exp
.X_add_number
-= 8;
8331 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8332 into a relative address of the form:
8333 add rd, pc, #low(label-.-8)"
8334 add rd, rd, #high(label-.-8)" */
8339 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8341 /* Frag hacking will turn this into a sub instruction if the offset turns
8342 out to be negative. */
8343 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8344 inst
.reloc
.pc_rel
= 1;
8345 inst
.size
= INSN_SIZE
* 2;
8346 inst
.reloc
.exp
.X_add_number
-= 8;
8352 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8353 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8355 if (!inst
.operands
[1].present
)
8356 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8358 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8359 encode_arm_shifter_operand (2);
8365 if (inst
.operands
[0].present
)
8366 inst
.instruction
|= inst
.operands
[0].imm
;
8368 inst
.instruction
|= 0xf;
8374 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8375 constraint (msb
> 32, _("bit-field extends past end of register"));
8376 /* The instruction encoding stores the LSB and MSB,
8377 not the LSB and width. */
8378 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8379 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8380 inst
.instruction
|= (msb
- 1) << 16;
8388 /* #0 in second position is alternative syntax for bfc, which is
8389 the same instruction but with REG_PC in the Rm field. */
8390 if (!inst
.operands
[1].isreg
)
8391 inst
.operands
[1].reg
= REG_PC
;
8393 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8394 constraint (msb
> 32, _("bit-field extends past end of register"));
8395 /* The instruction encoding stores the LSB and MSB,
8396 not the LSB and width. */
8397 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8398 inst
.instruction
|= inst
.operands
[1].reg
;
8399 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8400 inst
.instruction
|= (msb
- 1) << 16;
8406 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8407 _("bit-field extends past end of register"));
8408 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8409 inst
.instruction
|= inst
.operands
[1].reg
;
8410 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8411 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8414 /* ARM V5 breakpoint instruction (argument parse)
8415 BKPT <16 bit unsigned immediate>
8416 Instruction is not conditional.
8417 The bit pattern given in insns[] has the COND_ALWAYS condition,
8418 and it is an error if the caller tried to override that. */
8423 /* Top 12 of 16 bits to bits 19:8. */
8424 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8426 /* Bottom 4 of 16 bits to bits 3:0. */
8427 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8431 encode_branch (int default_reloc
)
8433 if (inst
.operands
[0].hasreloc
)
8435 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8436 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8437 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8438 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8439 ? BFD_RELOC_ARM_PLT32
8440 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8443 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8444 inst
.reloc
.pc_rel
= 1;
8451 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8452 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8455 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8462 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8464 if (inst
.cond
== COND_ALWAYS
)
8465 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8467 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8471 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8474 /* ARM V5 branch-link-exchange instruction (argument parse)
8475 BLX <target_addr> ie BLX(1)
8476 BLX{<condition>} <Rm> ie BLX(2)
8477 Unfortunately, there are two different opcodes for this mnemonic.
8478 So, the insns[].value is not used, and the code here zaps values
8479 into inst.instruction.
8480 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8485 if (inst
.operands
[0].isreg
)
8487 /* Arg is a register; the opcode provided by insns[] is correct.
8488 It is not illegal to do "blx pc", just useless. */
8489 if (inst
.operands
[0].reg
== REG_PC
)
8490 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8492 inst
.instruction
|= inst
.operands
[0].reg
;
8496 /* Arg is an address; this instruction cannot be executed
8497 conditionally, and the opcode must be adjusted.
8498 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8499 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8500 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8501 inst
.instruction
= 0xfa000000;
8502 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8509 bfd_boolean want_reloc
;
8511 if (inst
.operands
[0].reg
== REG_PC
)
8512 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8514 inst
.instruction
|= inst
.operands
[0].reg
;
8515 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8516 it is for ARMv4t or earlier. */
8517 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8518 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8522 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8527 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8531 /* ARM v5TEJ. Jump to Jazelle code. */
8536 if (inst
.operands
[0].reg
== REG_PC
)
8537 as_tsktsk (_("use of r15 in bxj is not really useful"));
8539 inst
.instruction
|= inst
.operands
[0].reg
;
8542 /* Co-processor data operation:
8543 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8544 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8548 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8549 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8550 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8551 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8552 inst
.instruction
|= inst
.operands
[4].reg
;
8553 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8559 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8560 encode_arm_shifter_operand (1);
8563 /* Transfer between coprocessor and ARM registers.
8564 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8569 No special properties. */
8571 struct deprecated_coproc_regs_s
8578 arm_feature_set deprecated
;
8579 arm_feature_set obsoleted
;
8580 const char *dep_msg
;
8581 const char *obs_msg
;
8584 #define DEPR_ACCESS_V8 \
8585 N_("This coprocessor register access is deprecated in ARMv8")
8587 /* Table of all deprecated coprocessor registers. */
8588 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8590 {15, 0, 7, 10, 5, /* CP15DMB. */
8591 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8592 DEPR_ACCESS_V8
, NULL
},
8593 {15, 0, 7, 10, 4, /* CP15DSB. */
8594 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8595 DEPR_ACCESS_V8
, NULL
},
8596 {15, 0, 7, 5, 4, /* CP15ISB. */
8597 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8598 DEPR_ACCESS_V8
, NULL
},
8599 {14, 6, 1, 0, 0, /* TEEHBR. */
8600 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8601 DEPR_ACCESS_V8
, NULL
},
8602 {14, 6, 0, 0, 0, /* TEECR. */
8603 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8604 DEPR_ACCESS_V8
, NULL
},
8607 #undef DEPR_ACCESS_V8
8609 static const size_t deprecated_coproc_reg_count
=
8610 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8618 Rd
= inst
.operands
[2].reg
;
8621 if (inst
.instruction
== 0xee000010
8622 || inst
.instruction
== 0xfe000010)
8624 reject_bad_reg (Rd
);
8627 constraint (Rd
== REG_SP
, BAD_SP
);
8632 if (inst
.instruction
== 0xe000010)
8633 constraint (Rd
== REG_PC
, BAD_PC
);
8636 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8638 const struct deprecated_coproc_regs_s
*r
=
8639 deprecated_coproc_regs
+ i
;
8641 if (inst
.operands
[0].reg
== r
->cp
8642 && inst
.operands
[1].imm
== r
->opc1
8643 && inst
.operands
[3].reg
== r
->crn
8644 && inst
.operands
[4].reg
== r
->crm
8645 && inst
.operands
[5].imm
== r
->opc2
)
8647 if (! ARM_CPU_IS_ANY (cpu_variant
)
8648 && warn_on_deprecated
8649 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8650 as_tsktsk ("%s", r
->dep_msg
);
8654 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8655 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8656 inst
.instruction
|= Rd
<< 12;
8657 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8658 inst
.instruction
|= inst
.operands
[4].reg
;
8659 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8662 /* Transfer between coprocessor register and pair of ARM registers.
8663 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8668 Two XScale instructions are special cases of these:
8670 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8671 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8673 Result unpredictable if Rd or Rn is R15. */
8680 Rd
= inst
.operands
[2].reg
;
8681 Rn
= inst
.operands
[3].reg
;
8685 reject_bad_reg (Rd
);
8686 reject_bad_reg (Rn
);
8690 constraint (Rd
== REG_PC
, BAD_PC
);
8691 constraint (Rn
== REG_PC
, BAD_PC
);
8694 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8695 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8696 inst
.instruction
|= Rd
<< 12;
8697 inst
.instruction
|= Rn
<< 16;
8698 inst
.instruction
|= inst
.operands
[4].reg
;
8704 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8705 if (inst
.operands
[1].present
)
8707 inst
.instruction
|= CPSI_MMOD
;
8708 inst
.instruction
|= inst
.operands
[1].imm
;
8715 inst
.instruction
|= inst
.operands
[0].imm
;
8721 unsigned Rd
, Rn
, Rm
;
8723 Rd
= inst
.operands
[0].reg
;
8724 Rn
= (inst
.operands
[1].present
8725 ? inst
.operands
[1].reg
: Rd
);
8726 Rm
= inst
.operands
[2].reg
;
8728 constraint ((Rd
== REG_PC
), BAD_PC
);
8729 constraint ((Rn
== REG_PC
), BAD_PC
);
8730 constraint ((Rm
== REG_PC
), BAD_PC
);
8732 inst
.instruction
|= Rd
<< 16;
8733 inst
.instruction
|= Rn
<< 0;
8734 inst
.instruction
|= Rm
<< 8;
8740 /* There is no IT instruction in ARM mode. We
8741 process it to do the validation as if in
8742 thumb mode, just in case the code gets
8743 assembled for thumb using the unified syntax. */
8748 set_it_insn_type (IT_INSN
);
8749 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8750 now_it
.cc
= inst
.operands
[0].imm
;
8754 /* If there is only one register in the register list,
8755 then return its register number. Otherwise return -1. */
8757 only_one_reg_in_list (int range
)
8759 int i
= ffs (range
) - 1;
8760 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8764 encode_ldmstm(int from_push_pop_mnem
)
8766 int base_reg
= inst
.operands
[0].reg
;
8767 int range
= inst
.operands
[1].imm
;
8770 inst
.instruction
|= base_reg
<< 16;
8771 inst
.instruction
|= range
;
8773 if (inst
.operands
[1].writeback
)
8774 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8776 if (inst
.operands
[0].writeback
)
8778 inst
.instruction
|= WRITE_BACK
;
8779 /* Check for unpredictable uses of writeback. */
8780 if (inst
.instruction
& LOAD_BIT
)
8782 /* Not allowed in LDM type 2. */
8783 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8784 && ((range
& (1 << REG_PC
)) == 0))
8785 as_warn (_("writeback of base register is UNPREDICTABLE"));
8786 /* Only allowed if base reg not in list for other types. */
8787 else if (range
& (1 << base_reg
))
8788 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8792 /* Not allowed for type 2. */
8793 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8794 as_warn (_("writeback of base register is UNPREDICTABLE"));
8795 /* Only allowed if base reg not in list, or first in list. */
8796 else if ((range
& (1 << base_reg
))
8797 && (range
& ((1 << base_reg
) - 1)))
8798 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8802 /* If PUSH/POP has only one register, then use the A2 encoding. */
8803 one_reg
= only_one_reg_in_list (range
);
8804 if (from_push_pop_mnem
&& one_reg
>= 0)
8806 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8808 inst
.instruction
&= A_COND_MASK
;
8809 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8810 inst
.instruction
|= one_reg
<< 12;
8817 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8820 /* ARMv5TE load-consecutive (argument parse)
8829 constraint (inst
.operands
[0].reg
% 2 != 0,
8830 _("first transfer register must be even"));
8831 constraint (inst
.operands
[1].present
8832 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8833 _("can only transfer two consecutive registers"));
8834 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8835 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8837 if (!inst
.operands
[1].present
)
8838 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8840 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8841 register and the first register written; we have to diagnose
8842 overlap between the base and the second register written here. */
8844 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8845 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8846 as_warn (_("base register written back, and overlaps "
8847 "second transfer register"));
8849 if (!(inst
.instruction
& V4_STR_BIT
))
8851 /* For an index-register load, the index register must not overlap the
8852 destination (even if not write-back). */
8853 if (inst
.operands
[2].immisreg
8854 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8855 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8856 as_warn (_("index register overlaps transfer register"));
8858 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8859 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8865 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8866 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8867 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8868 || inst
.operands
[1].negative
8869 /* This can arise if the programmer has written
8871 or if they have mistakenly used a register name as the last
8874 It is very difficult to distinguish between these two cases
8875 because "rX" might actually be a label. ie the register
8876 name has been occluded by a symbol of the same name. So we
8877 just generate a general 'bad addressing mode' type error
8878 message and leave it up to the programmer to discover the
8879 true cause and fix their mistake. */
8880 || (inst
.operands
[1].reg
== REG_PC
),
8883 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8884 || inst
.reloc
.exp
.X_add_number
!= 0,
8885 _("offset must be zero in ARM encoding"));
8887 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8889 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8890 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8891 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8897 constraint (inst
.operands
[0].reg
% 2 != 0,
8898 _("even register required"));
8899 constraint (inst
.operands
[1].present
8900 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8901 _("can only load two consecutive registers"));
8902 /* If op 1 were present and equal to PC, this function wouldn't
8903 have been called in the first place. */
8904 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8907 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8910 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8911 which is not a multiple of four is UNPREDICTABLE. */
8913 check_ldr_r15_aligned (void)
8915 constraint (!(inst
.operands
[1].immisreg
)
8916 && (inst
.operands
[0].reg
== REG_PC
8917 && inst
.operands
[1].reg
== REG_PC
8918 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8919 _("ldr to register 15 must be 4-byte alligned"));
8925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8926 if (!inst
.operands
[1].isreg
)
8927 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8929 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8930 check_ldr_r15_aligned ();
8936 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8938 if (inst
.operands
[1].preind
)
8940 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8941 || inst
.reloc
.exp
.X_add_number
!= 0,
8942 _("this instruction requires a post-indexed address"));
8944 inst
.operands
[1].preind
= 0;
8945 inst
.operands
[1].postind
= 1;
8946 inst
.operands
[1].writeback
= 1;
8948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8949 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8952 /* Halfword and signed-byte load/store operations. */
8957 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8958 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8959 if (!inst
.operands
[1].isreg
)
8960 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8962 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8968 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8970 if (inst
.operands
[1].preind
)
8972 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8973 || inst
.reloc
.exp
.X_add_number
!= 0,
8974 _("this instruction requires a post-indexed address"));
8976 inst
.operands
[1].preind
= 0;
8977 inst
.operands
[1].postind
= 1;
8978 inst
.operands
[1].writeback
= 1;
8980 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8981 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8984 /* Co-processor register load/store.
8985 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8989 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8990 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8991 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8997 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8998 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8999 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9000 && !(inst
.instruction
& 0x00400000))
9001 as_tsktsk (_("Rd and Rm should be different in mla"));
9003 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9004 inst
.instruction
|= inst
.operands
[1].reg
;
9005 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9006 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9012 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9013 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9015 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9016 encode_arm_shifter_operand (1);
9019 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9026 top
= (inst
.instruction
& 0x00400000) != 0;
9027 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9028 _(":lower16: not allowed this instruction"));
9029 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9030 _(":upper16: not allowed instruction"));
9031 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9032 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9034 imm
= inst
.reloc
.exp
.X_add_number
;
9035 /* The value is in two pieces: 0:11, 16:19. */
9036 inst
.instruction
|= (imm
& 0x00000fff);
9037 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9042 do_vfp_nsyn_mrs (void)
9044 if (inst
.operands
[0].isvec
)
9046 if (inst
.operands
[1].reg
!= 1)
9047 first_error (_("operand 1 must be FPSCR"));
9048 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9049 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9050 do_vfp_nsyn_opcode ("fmstat");
9052 else if (inst
.operands
[1].isvec
)
9053 do_vfp_nsyn_opcode ("fmrx");
9061 do_vfp_nsyn_msr (void)
9063 if (inst
.operands
[0].isvec
)
9064 do_vfp_nsyn_opcode ("fmxr");
9074 unsigned Rt
= inst
.operands
[0].reg
;
9076 if (thumb_mode
&& Rt
== REG_SP
)
9078 inst
.error
= BAD_SP
;
9082 /* APSR_ sets isvec. All other refs to PC are illegal. */
9083 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9085 inst
.error
= BAD_PC
;
9089 /* If we get through parsing the register name, we just insert the number
9090 generated into the instruction without further validation. */
9091 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9092 inst
.instruction
|= (Rt
<< 12);
9098 unsigned Rt
= inst
.operands
[1].reg
;
9101 reject_bad_reg (Rt
);
9102 else if (Rt
== REG_PC
)
9104 inst
.error
= BAD_PC
;
9108 /* If we get through parsing the register name, we just insert the number
9109 generated into the instruction without further validation. */
9110 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9111 inst
.instruction
|= (Rt
<< 12);
9119 if (do_vfp_nsyn_mrs () == SUCCESS
)
9122 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9125 if (inst
.operands
[1].isreg
)
9127 br
= inst
.operands
[1].reg
;
9128 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9129 as_bad (_("bad register for mrs"));
9133 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9134 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9136 _("'APSR', 'CPSR' or 'SPSR' expected"));
9137 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9140 inst
.instruction
|= br
;
9143 /* Two possible forms:
9144 "{C|S}PSR_<field>, Rm",
9145 "{C|S}PSR_f, #expression". */
9150 if (do_vfp_nsyn_msr () == SUCCESS
)
9153 inst
.instruction
|= inst
.operands
[0].imm
;
9154 if (inst
.operands
[1].isreg
)
9155 inst
.instruction
|= inst
.operands
[1].reg
;
9158 inst
.instruction
|= INST_IMMEDIATE
;
9159 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9160 inst
.reloc
.pc_rel
= 0;
9167 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9169 if (!inst
.operands
[2].present
)
9170 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9171 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9172 inst
.instruction
|= inst
.operands
[1].reg
;
9173 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9175 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9176 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9177 as_tsktsk (_("Rd and Rm should be different in mul"));
9180 /* Long Multiply Parser
9181 UMULL RdLo, RdHi, Rm, Rs
9182 SMULL RdLo, RdHi, Rm, Rs
9183 UMLAL RdLo, RdHi, Rm, Rs
9184 SMLAL RdLo, RdHi, Rm, Rs. */
9189 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9190 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9191 inst
.instruction
|= inst
.operands
[2].reg
;
9192 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9194 /* rdhi and rdlo must be different. */
9195 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9196 as_tsktsk (_("rdhi and rdlo must be different"));
9198 /* rdhi, rdlo and rm must all be different before armv6. */
9199 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9200 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9201 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9202 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9208 if (inst
.operands
[0].present
9209 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9211 /* Architectural NOP hints are CPSR sets with no bits selected. */
9212 inst
.instruction
&= 0xf0000000;
9213 inst
.instruction
|= 0x0320f000;
9214 if (inst
.operands
[0].present
)
9215 inst
.instruction
|= inst
.operands
[0].imm
;
9219 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9220 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9221 Condition defaults to COND_ALWAYS.
9222 Error if Rd, Rn or Rm are R15. */
9227 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9228 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9229 inst
.instruction
|= inst
.operands
[2].reg
;
9230 if (inst
.operands
[3].present
)
9231 encode_arm_shift (3);
9234 /* ARM V6 PKHTB (Argument Parse). */
9239 if (!inst
.operands
[3].present
)
9241 /* If the shift specifier is omitted, turn the instruction
9242 into pkhbt rd, rm, rn. */
9243 inst
.instruction
&= 0xfff00010;
9244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9245 inst
.instruction
|= inst
.operands
[1].reg
;
9246 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9250 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9251 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9252 inst
.instruction
|= inst
.operands
[2].reg
;
9253 encode_arm_shift (3);
9257 /* ARMv5TE: Preload-Cache
9258 MP Extensions: Preload for write
9262 Syntactically, like LDR with B=1, W=0, L=1. */
9267 constraint (!inst
.operands
[0].isreg
,
9268 _("'[' expected after PLD mnemonic"));
9269 constraint (inst
.operands
[0].postind
,
9270 _("post-indexed expression used in preload instruction"));
9271 constraint (inst
.operands
[0].writeback
,
9272 _("writeback used in preload instruction"));
9273 constraint (!inst
.operands
[0].preind
,
9274 _("unindexed addressing used in preload instruction"));
9275 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9278 /* ARMv7: PLI <addr_mode> */
9282 constraint (!inst
.operands
[0].isreg
,
9283 _("'[' expected after PLI mnemonic"));
9284 constraint (inst
.operands
[0].postind
,
9285 _("post-indexed expression used in preload instruction"));
9286 constraint (inst
.operands
[0].writeback
,
9287 _("writeback used in preload instruction"));
9288 constraint (!inst
.operands
[0].preind
,
9289 _("unindexed addressing used in preload instruction"));
9290 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9291 inst
.instruction
&= ~PRE_INDEX
;
9297 constraint (inst
.operands
[0].writeback
,
9298 _("push/pop do not support {reglist}^"));
9299 inst
.operands
[1] = inst
.operands
[0];
9300 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9301 inst
.operands
[0].isreg
= 1;
9302 inst
.operands
[0].writeback
= 1;
9303 inst
.operands
[0].reg
= REG_SP
;
9304 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9307 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9308 word at the specified address and the following word
9310 Unconditionally executed.
9311 Error if Rn is R15. */
9316 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9317 if (inst
.operands
[0].writeback
)
9318 inst
.instruction
|= WRITE_BACK
;
9321 /* ARM V6 ssat (argument parse). */
9326 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9327 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9328 inst
.instruction
|= inst
.operands
[2].reg
;
9330 if (inst
.operands
[3].present
)
9331 encode_arm_shift (3);
9334 /* ARM V6 usat (argument parse). */
9339 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9340 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9341 inst
.instruction
|= inst
.operands
[2].reg
;
9343 if (inst
.operands
[3].present
)
9344 encode_arm_shift (3);
9347 /* ARM V6 ssat16 (argument parse). */
9352 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9353 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9354 inst
.instruction
|= inst
.operands
[2].reg
;
9360 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9361 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9362 inst
.instruction
|= inst
.operands
[2].reg
;
9365 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9366 preserving the other bits.
9368 setend <endian_specifier>, where <endian_specifier> is either
9374 if (warn_on_deprecated
9375 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9376 as_tsktsk (_("setend use is deprecated for ARMv8"));
9378 if (inst
.operands
[0].imm
)
9379 inst
.instruction
|= 0x200;
9385 unsigned int Rm
= (inst
.operands
[1].present
9386 ? inst
.operands
[1].reg
9387 : inst
.operands
[0].reg
);
9389 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9390 inst
.instruction
|= Rm
;
9391 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9393 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9394 inst
.instruction
|= SHIFT_BY_REG
;
9395 /* PR 12854: Error on extraneous shifts. */
9396 constraint (inst
.operands
[2].shifted
,
9397 _("extraneous shift as part of operand to shift insn"));
9400 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9406 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9407 inst
.reloc
.pc_rel
= 0;
9413 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9414 inst
.reloc
.pc_rel
= 0;
9420 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9421 inst
.reloc
.pc_rel
= 0;
9427 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9428 _("selected processor does not support SETPAN instruction"));
9430 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9436 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9437 _("selected processor does not support SETPAN instruction"));
9439 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9442 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9443 SMLAxy{cond} Rd,Rm,Rs,Rn
9444 SMLAWy{cond} Rd,Rm,Rs,Rn
9445 Error if any register is R15. */
9450 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9451 inst
.instruction
|= inst
.operands
[1].reg
;
9452 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9453 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9456 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9457 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9458 Error if any register is R15.
9459 Warning if Rdlo == Rdhi. */
9464 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9465 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9466 inst
.instruction
|= inst
.operands
[2].reg
;
9467 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9469 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9470 as_tsktsk (_("rdhi and rdlo must be different"));
9473 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9474 SMULxy{cond} Rd,Rm,Rs
9475 Error if any register is R15. */
9480 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9481 inst
.instruction
|= inst
.operands
[1].reg
;
9482 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9485 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9486 the same for both ARM and Thumb-2. */
9493 if (inst
.operands
[0].present
)
9495 reg
= inst
.operands
[0].reg
;
9496 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9501 inst
.instruction
|= reg
<< 16;
9502 inst
.instruction
|= inst
.operands
[1].imm
;
9503 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9504 inst
.instruction
|= WRITE_BACK
;
9507 /* ARM V6 strex (argument parse). */
9512 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9513 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9514 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9515 || inst
.operands
[2].negative
9516 /* See comment in do_ldrex(). */
9517 || (inst
.operands
[2].reg
== REG_PC
),
9520 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9521 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9523 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9524 || inst
.reloc
.exp
.X_add_number
!= 0,
9525 _("offset must be zero in ARM encoding"));
9527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9528 inst
.instruction
|= inst
.operands
[1].reg
;
9529 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9530 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9536 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9537 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9538 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9539 || inst
.operands
[2].negative
,
9542 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9543 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9551 constraint (inst
.operands
[1].reg
% 2 != 0,
9552 _("even register required"));
9553 constraint (inst
.operands
[2].present
9554 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9555 _("can only store two consecutive registers"));
9556 /* If op 2 were present and equal to PC, this function wouldn't
9557 have been called in the first place. */
9558 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9560 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9561 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9562 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9565 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9566 inst
.instruction
|= inst
.operands
[1].reg
;
9567 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9574 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9575 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9583 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9584 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9589 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9590 extends it to 32-bits, and adds the result to a value in another
9591 register. You can specify a rotation by 0, 8, 16, or 24 bits
9592 before extracting the 16-bit value.
9593 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9594 Condition defaults to COND_ALWAYS.
9595 Error if any register uses R15. */
9600 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9601 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9602 inst
.instruction
|= inst
.operands
[2].reg
;
9603 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9608 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9609 Condition defaults to COND_ALWAYS.
9610 Error if any register uses R15. */
9615 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9616 inst
.instruction
|= inst
.operands
[1].reg
;
9617 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9620 /* VFP instructions. In a logical order: SP variant first, monad
9621 before dyad, arithmetic then move then load/store. */
9624 do_vfp_sp_monadic (void)
9626 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9627 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9631 do_vfp_sp_dyadic (void)
9633 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9634 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9635 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9639 do_vfp_sp_compare_z (void)
9641 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9645 do_vfp_dp_sp_cvt (void)
9647 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9648 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9652 do_vfp_sp_dp_cvt (void)
9654 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9655 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9659 do_vfp_reg_from_sp (void)
9661 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9662 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9666 do_vfp_reg2_from_sp2 (void)
9668 constraint (inst
.operands
[2].imm
!= 2,
9669 _("only two consecutive VFP SP registers allowed here"));
9670 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9671 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9672 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9676 do_vfp_sp_from_reg (void)
9678 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9679 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9683 do_vfp_sp2_from_reg2 (void)
9685 constraint (inst
.operands
[0].imm
!= 2,
9686 _("only two consecutive VFP SP registers allowed here"));
9687 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9688 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9689 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9693 do_vfp_sp_ldst (void)
9695 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9696 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9700 do_vfp_dp_ldst (void)
9702 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9703 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9708 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9710 if (inst
.operands
[0].writeback
)
9711 inst
.instruction
|= WRITE_BACK
;
9713 constraint (ldstm_type
!= VFP_LDSTMIA
,
9714 _("this addressing mode requires base-register writeback"));
9715 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9716 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9717 inst
.instruction
|= inst
.operands
[1].imm
;
9721 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9725 if (inst
.operands
[0].writeback
)
9726 inst
.instruction
|= WRITE_BACK
;
9728 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9729 _("this addressing mode requires base-register writeback"));
9731 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9732 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9734 count
= inst
.operands
[1].imm
<< 1;
9735 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9738 inst
.instruction
|= count
;
9742 do_vfp_sp_ldstmia (void)
9744 vfp_sp_ldstm (VFP_LDSTMIA
);
9748 do_vfp_sp_ldstmdb (void)
9750 vfp_sp_ldstm (VFP_LDSTMDB
);
9754 do_vfp_dp_ldstmia (void)
9756 vfp_dp_ldstm (VFP_LDSTMIA
);
9760 do_vfp_dp_ldstmdb (void)
9762 vfp_dp_ldstm (VFP_LDSTMDB
);
9766 do_vfp_xp_ldstmia (void)
9768 vfp_dp_ldstm (VFP_LDSTMIAX
);
9772 do_vfp_xp_ldstmdb (void)
9774 vfp_dp_ldstm (VFP_LDSTMDBX
);
9778 do_vfp_dp_rd_rm (void)
9780 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9781 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9785 do_vfp_dp_rn_rd (void)
9787 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9788 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9792 do_vfp_dp_rd_rn (void)
9794 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9795 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9799 do_vfp_dp_rd_rn_rm (void)
9801 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9802 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9803 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9809 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9813 do_vfp_dp_rm_rd_rn (void)
9815 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9816 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9817 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9820 /* VFPv3 instructions. */
9822 do_vfp_sp_const (void)
9824 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9825 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9826 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9830 do_vfp_dp_const (void)
9832 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9833 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9834 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9838 vfp_conv (int srcsize
)
9840 int immbits
= srcsize
- inst
.operands
[1].imm
;
9842 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9844 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9845 i.e. immbits must be in range 0 - 16. */
9846 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9849 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9851 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9852 i.e. immbits must be in range 0 - 31. */
9853 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9857 inst
.instruction
|= (immbits
& 1) << 5;
9858 inst
.instruction
|= (immbits
>> 1);
9862 do_vfp_sp_conv_16 (void)
9864 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9869 do_vfp_dp_conv_16 (void)
9871 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9876 do_vfp_sp_conv_32 (void)
9878 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9883 do_vfp_dp_conv_32 (void)
9885 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9889 /* FPA instructions. Also in a logical order. */
9894 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9895 inst
.instruction
|= inst
.operands
[1].reg
;
9899 do_fpa_ldmstm (void)
9901 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9902 switch (inst
.operands
[1].imm
)
9904 case 1: inst
.instruction
|= CP_T_X
; break;
9905 case 2: inst
.instruction
|= CP_T_Y
; break;
9906 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9911 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9913 /* The instruction specified "ea" or "fd", so we can only accept
9914 [Rn]{!}. The instruction does not really support stacking or
9915 unstacking, so we have to emulate these by setting appropriate
9916 bits and offsets. */
9917 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9918 || inst
.reloc
.exp
.X_add_number
!= 0,
9919 _("this instruction does not support indexing"));
9921 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9922 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9924 if (!(inst
.instruction
& INDEX_UP
))
9925 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9927 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9929 inst
.operands
[2].preind
= 0;
9930 inst
.operands
[2].postind
= 1;
9934 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9937 /* iWMMXt instructions: strictly in alphabetical order. */
9940 do_iwmmxt_tandorc (void)
9942 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9946 do_iwmmxt_textrc (void)
9948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9949 inst
.instruction
|= inst
.operands
[1].imm
;
9953 do_iwmmxt_textrm (void)
9955 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9956 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9957 inst
.instruction
|= inst
.operands
[2].imm
;
9961 do_iwmmxt_tinsr (void)
9963 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9964 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9965 inst
.instruction
|= inst
.operands
[2].imm
;
9969 do_iwmmxt_tmia (void)
9971 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9972 inst
.instruction
|= inst
.operands
[1].reg
;
9973 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9977 do_iwmmxt_waligni (void)
9979 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9980 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9981 inst
.instruction
|= inst
.operands
[2].reg
;
9982 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9986 do_iwmmxt_wmerge (void)
9988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9989 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9990 inst
.instruction
|= inst
.operands
[2].reg
;
9991 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9995 do_iwmmxt_wmov (void)
9997 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9998 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9999 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10000 inst
.instruction
|= inst
.operands
[1].reg
;
10004 do_iwmmxt_wldstbh (void)
10007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10009 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10011 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10012 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10016 do_iwmmxt_wldstw (void)
10018 /* RIWR_RIWC clears .isreg for a control register. */
10019 if (!inst
.operands
[0].isreg
)
10021 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10022 inst
.instruction
|= 0xf0000000;
10025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10026 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10030 do_iwmmxt_wldstd (void)
10032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10033 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10034 && inst
.operands
[1].immisreg
)
10036 inst
.instruction
&= ~0x1a000ff;
10037 inst
.instruction
|= (0xfU
<< 28);
10038 if (inst
.operands
[1].preind
)
10039 inst
.instruction
|= PRE_INDEX
;
10040 if (!inst
.operands
[1].negative
)
10041 inst
.instruction
|= INDEX_UP
;
10042 if (inst
.operands
[1].writeback
)
10043 inst
.instruction
|= WRITE_BACK
;
10044 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10045 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10046 inst
.instruction
|= inst
.operands
[1].imm
;
10049 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10053 do_iwmmxt_wshufh (void)
10055 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10056 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10057 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10058 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10062 do_iwmmxt_wzero (void)
10064 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10065 inst
.instruction
|= inst
.operands
[0].reg
;
10066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10067 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10071 do_iwmmxt_wrwrwr_or_imm5 (void)
10073 if (inst
.operands
[2].isreg
)
10076 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10077 _("immediate operand requires iWMMXt2"));
10079 if (inst
.operands
[2].imm
== 0)
10081 switch ((inst
.instruction
>> 20) & 0xf)
10087 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10088 inst
.operands
[2].imm
= 16;
10089 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10095 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10096 inst
.operands
[2].imm
= 32;
10097 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10104 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10106 wrn
= (inst
.instruction
>> 16) & 0xf;
10107 inst
.instruction
&= 0xff0fff0f;
10108 inst
.instruction
|= wrn
;
10109 /* Bail out here; the instruction is now assembled. */
10114 /* Map 32 -> 0, etc. */
10115 inst
.operands
[2].imm
&= 0x1f;
10116 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10120 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10121 operations first, then control, shift, and load/store. */
10123 /* Insns like "foo X,Y,Z". */
10126 do_mav_triple (void)
10128 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10129 inst
.instruction
|= inst
.operands
[1].reg
;
10130 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10133 /* Insns like "foo W,X,Y,Z".
10134 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10139 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10140 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10141 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10142 inst
.instruction
|= inst
.operands
[3].reg
;
10145 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10147 do_mav_dspsc (void)
10149 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10152 /* Maverick shift immediate instructions.
10153 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10154 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10157 do_mav_shift (void)
10159 int imm
= inst
.operands
[2].imm
;
10161 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10162 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10164 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10165 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10166 Bit 4 should be 0. */
10167 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10169 inst
.instruction
|= imm
;
10172 /* XScale instructions. Also sorted arithmetic before move. */
10174 /* Xscale multiply-accumulate (argument parse)
10177 MIAxycc acc0,Rm,Rs. */
10182 inst
.instruction
|= inst
.operands
[1].reg
;
10183 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10186 /* Xscale move-accumulator-register (argument parse)
10188 MARcc acc0,RdLo,RdHi. */
10193 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10194 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10197 /* Xscale move-register-accumulator (argument parse)
10199 MRAcc RdLo,RdHi,acc0. */
10204 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10205 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10206 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10209 /* Encoding functions relevant only to Thumb. */
10211 /* inst.operands[i] is a shifted-register operand; encode
10212 it into inst.instruction in the format used by Thumb32. */
10215 encode_thumb32_shifted_operand (int i
)
10217 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10218 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10220 constraint (inst
.operands
[i
].immisreg
,
10221 _("shift by register not allowed in thumb mode"));
10222 inst
.instruction
|= inst
.operands
[i
].reg
;
10223 if (shift
== SHIFT_RRX
)
10224 inst
.instruction
|= SHIFT_ROR
<< 4;
10227 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10228 _("expression too complex"));
10230 constraint (value
> 32
10231 || (value
== 32 && (shift
== SHIFT_LSL
10232 || shift
== SHIFT_ROR
)),
10233 _("shift expression is too large"));
10237 else if (value
== 32)
10240 inst
.instruction
|= shift
<< 4;
10241 inst
.instruction
|= (value
& 0x1c) << 10;
10242 inst
.instruction
|= (value
& 0x03) << 6;
10247 /* inst.operands[i] was set up by parse_address. Encode it into a
10248 Thumb32 format load or store instruction. Reject forms that cannot
10249 be used with such instructions. If is_t is true, reject forms that
10250 cannot be used with a T instruction; if is_d is true, reject forms
10251 that cannot be used with a D instruction. If it is a store insn,
10252 reject PC in Rn. */
10255 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10257 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10259 constraint (!inst
.operands
[i
].isreg
,
10260 _("Instruction does not support =N addresses"));
10262 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10263 if (inst
.operands
[i
].immisreg
)
10265 constraint (is_pc
, BAD_PC_ADDRESSING
);
10266 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10267 constraint (inst
.operands
[i
].negative
,
10268 _("Thumb does not support negative register indexing"));
10269 constraint (inst
.operands
[i
].postind
,
10270 _("Thumb does not support register post-indexing"));
10271 constraint (inst
.operands
[i
].writeback
,
10272 _("Thumb does not support register indexing with writeback"));
10273 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10274 _("Thumb supports only LSL in shifted register indexing"));
10276 inst
.instruction
|= inst
.operands
[i
].imm
;
10277 if (inst
.operands
[i
].shifted
)
10279 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10280 _("expression too complex"));
10281 constraint (inst
.reloc
.exp
.X_add_number
< 0
10282 || inst
.reloc
.exp
.X_add_number
> 3,
10283 _("shift out of range"));
10284 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10286 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10288 else if (inst
.operands
[i
].preind
)
10290 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10291 constraint (is_t
&& inst
.operands
[i
].writeback
,
10292 _("cannot use writeback with this instruction"));
10293 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10294 BAD_PC_ADDRESSING
);
10298 inst
.instruction
|= 0x01000000;
10299 if (inst
.operands
[i
].writeback
)
10300 inst
.instruction
|= 0x00200000;
10304 inst
.instruction
|= 0x00000c00;
10305 if (inst
.operands
[i
].writeback
)
10306 inst
.instruction
|= 0x00000100;
10308 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10310 else if (inst
.operands
[i
].postind
)
10312 gas_assert (inst
.operands
[i
].writeback
);
10313 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10314 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10317 inst
.instruction
|= 0x00200000;
10319 inst
.instruction
|= 0x00000900;
10320 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10322 else /* unindexed - only for coprocessor */
10323 inst
.error
= _("instruction does not accept unindexed addressing");
10326 /* Table of Thumb instructions which exist in both 16- and 32-bit
10327 encodings (the latter only in post-V6T2 cores). The index is the
10328 value used in the insns table below. When there is more than one
10329 possible 16-bit encoding for the instruction, this table always
10331 Also contains several pseudo-instructions used during relaxation. */
10332 #define T16_32_TAB \
10333 X(_adc, 4140, eb400000), \
10334 X(_adcs, 4140, eb500000), \
10335 X(_add, 1c00, eb000000), \
10336 X(_adds, 1c00, eb100000), \
10337 X(_addi, 0000, f1000000), \
10338 X(_addis, 0000, f1100000), \
10339 X(_add_pc,000f, f20f0000), \
10340 X(_add_sp,000d, f10d0000), \
10341 X(_adr, 000f, f20f0000), \
10342 X(_and, 4000, ea000000), \
10343 X(_ands, 4000, ea100000), \
10344 X(_asr, 1000, fa40f000), \
10345 X(_asrs, 1000, fa50f000), \
10346 X(_b, e000, f000b000), \
10347 X(_bcond, d000, f0008000), \
10348 X(_bic, 4380, ea200000), \
10349 X(_bics, 4380, ea300000), \
10350 X(_cmn, 42c0, eb100f00), \
10351 X(_cmp, 2800, ebb00f00), \
10352 X(_cpsie, b660, f3af8400), \
10353 X(_cpsid, b670, f3af8600), \
10354 X(_cpy, 4600, ea4f0000), \
10355 X(_dec_sp,80dd, f1ad0d00), \
10356 X(_eor, 4040, ea800000), \
10357 X(_eors, 4040, ea900000), \
10358 X(_inc_sp,00dd, f10d0d00), \
10359 X(_ldmia, c800, e8900000), \
10360 X(_ldr, 6800, f8500000), \
10361 X(_ldrb, 7800, f8100000), \
10362 X(_ldrh, 8800, f8300000), \
10363 X(_ldrsb, 5600, f9100000), \
10364 X(_ldrsh, 5e00, f9300000), \
10365 X(_ldr_pc,4800, f85f0000), \
10366 X(_ldr_pc2,4800, f85f0000), \
10367 X(_ldr_sp,9800, f85d0000), \
10368 X(_lsl, 0000, fa00f000), \
10369 X(_lsls, 0000, fa10f000), \
10370 X(_lsr, 0800, fa20f000), \
10371 X(_lsrs, 0800, fa30f000), \
10372 X(_mov, 2000, ea4f0000), \
10373 X(_movs, 2000, ea5f0000), \
10374 X(_mul, 4340, fb00f000), \
10375 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10376 X(_mvn, 43c0, ea6f0000), \
10377 X(_mvns, 43c0, ea7f0000), \
10378 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10379 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10380 X(_orr, 4300, ea400000), \
10381 X(_orrs, 4300, ea500000), \
10382 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10383 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10384 X(_rev, ba00, fa90f080), \
10385 X(_rev16, ba40, fa90f090), \
10386 X(_revsh, bac0, fa90f0b0), \
10387 X(_ror, 41c0, fa60f000), \
10388 X(_rors, 41c0, fa70f000), \
10389 X(_sbc, 4180, eb600000), \
10390 X(_sbcs, 4180, eb700000), \
10391 X(_stmia, c000, e8800000), \
10392 X(_str, 6000, f8400000), \
10393 X(_strb, 7000, f8000000), \
10394 X(_strh, 8000, f8200000), \
10395 X(_str_sp,9000, f84d0000), \
10396 X(_sub, 1e00, eba00000), \
10397 X(_subs, 1e00, ebb00000), \
10398 X(_subi, 8000, f1a00000), \
10399 X(_subis, 8000, f1b00000), \
10400 X(_sxtb, b240, fa4ff080), \
10401 X(_sxth, b200, fa0ff080), \
10402 X(_tst, 4200, ea100f00), \
10403 X(_uxtb, b2c0, fa5ff080), \
10404 X(_uxth, b280, fa1ff080), \
10405 X(_nop, bf00, f3af8000), \
10406 X(_yield, bf10, f3af8001), \
10407 X(_wfe, bf20, f3af8002), \
10408 X(_wfi, bf30, f3af8003), \
10409 X(_sev, bf40, f3af8004), \
10410 X(_sevl, bf50, f3af8005), \
10411 X(_udf, de00, f7f0a000)
10413 /* To catch errors in encoding functions, the codes are all offset by
10414 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10415 as 16-bit instructions. */
10416 #define X(a,b,c) T_MNEM##a
10417 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10420 #define X(a,b,c) 0x##b
10421 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10422 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10425 #define X(a,b,c) 0x##c
10426 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10427 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10428 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10432 /* Thumb instruction encoders, in alphabetical order. */
10434 /* ADDW or SUBW. */
10437 do_t_add_sub_w (void)
10441 Rd
= inst
.operands
[0].reg
;
10442 Rn
= inst
.operands
[1].reg
;
10444 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10445 is the SP-{plus,minus}-immediate form of the instruction. */
10447 constraint (Rd
== REG_PC
, BAD_PC
);
10449 reject_bad_reg (Rd
);
10451 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10452 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10455 /* Parse an add or subtract instruction. We get here with inst.instruction
10456 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10459 do_t_add_sub (void)
10463 Rd
= inst
.operands
[0].reg
;
10464 Rs
= (inst
.operands
[1].present
10465 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10466 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10469 set_it_insn_type_last ();
10471 if (unified_syntax
)
10474 bfd_boolean narrow
;
10477 flags
= (inst
.instruction
== T_MNEM_adds
10478 || inst
.instruction
== T_MNEM_subs
);
10480 narrow
= !in_it_block ();
10482 narrow
= in_it_block ();
10483 if (!inst
.operands
[2].isreg
)
10487 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10489 add
= (inst
.instruction
== T_MNEM_add
10490 || inst
.instruction
== T_MNEM_adds
);
10492 if (inst
.size_req
!= 4)
10494 /* Attempt to use a narrow opcode, with relaxation if
10496 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10497 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10498 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10499 opcode
= T_MNEM_add_sp
;
10500 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10501 opcode
= T_MNEM_add_pc
;
10502 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10505 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10507 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10511 inst
.instruction
= THUMB_OP16(opcode
);
10512 inst
.instruction
|= (Rd
<< 4) | Rs
;
10513 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10514 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10516 if (inst
.size_req
== 2)
10517 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10519 inst
.relax
= opcode
;
10523 constraint (inst
.size_req
== 2, BAD_HIREG
);
10525 if (inst
.size_req
== 4
10526 || (inst
.size_req
!= 2 && !opcode
))
10528 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10529 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10530 THUMB1_RELOC_ONLY
);
10533 constraint (add
, BAD_PC
);
10534 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10535 _("only SUBS PC, LR, #const allowed"));
10536 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10537 _("expression too complex"));
10538 constraint (inst
.reloc
.exp
.X_add_number
< 0
10539 || inst
.reloc
.exp
.X_add_number
> 0xff,
10540 _("immediate value out of range"));
10541 inst
.instruction
= T2_SUBS_PC_LR
10542 | inst
.reloc
.exp
.X_add_number
;
10543 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10546 else if (Rs
== REG_PC
)
10548 /* Always use addw/subw. */
10549 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10550 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10554 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10555 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10558 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10560 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10562 inst
.instruction
|= Rd
<< 8;
10563 inst
.instruction
|= Rs
<< 16;
10568 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10569 unsigned int shift
= inst
.operands
[2].shift_kind
;
10571 Rn
= inst
.operands
[2].reg
;
10572 /* See if we can do this with a 16-bit instruction. */
10573 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10575 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10580 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10581 || inst
.instruction
== T_MNEM_add
)
10583 : T_OPCODE_SUB_R3
);
10584 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10588 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10590 /* Thumb-1 cores (except v6-M) require at least one high
10591 register in a narrow non flag setting add. */
10592 if (Rd
> 7 || Rn
> 7
10593 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10594 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10601 inst
.instruction
= T_OPCODE_ADD_HI
;
10602 inst
.instruction
|= (Rd
& 8) << 4;
10603 inst
.instruction
|= (Rd
& 7);
10604 inst
.instruction
|= Rn
<< 3;
10610 constraint (Rd
== REG_PC
, BAD_PC
);
10611 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10612 constraint (Rs
== REG_PC
, BAD_PC
);
10613 reject_bad_reg (Rn
);
10615 /* If we get here, it can't be done in 16 bits. */
10616 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10617 _("shift must be constant"));
10618 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10619 inst
.instruction
|= Rd
<< 8;
10620 inst
.instruction
|= Rs
<< 16;
10621 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10622 _("shift value over 3 not allowed in thumb mode"));
10623 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10624 _("only LSL shift allowed in thumb mode"));
10625 encode_thumb32_shifted_operand (2);
10630 constraint (inst
.instruction
== T_MNEM_adds
10631 || inst
.instruction
== T_MNEM_subs
,
10634 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10636 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10637 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10640 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10641 ? 0x0000 : 0x8000);
10642 inst
.instruction
|= (Rd
<< 4) | Rs
;
10643 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10647 Rn
= inst
.operands
[2].reg
;
10648 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10650 /* We now have Rd, Rs, and Rn set to registers. */
10651 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10653 /* Can't do this for SUB. */
10654 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10655 inst
.instruction
= T_OPCODE_ADD_HI
;
10656 inst
.instruction
|= (Rd
& 8) << 4;
10657 inst
.instruction
|= (Rd
& 7);
10659 inst
.instruction
|= Rn
<< 3;
10661 inst
.instruction
|= Rs
<< 3;
10663 constraint (1, _("dest must overlap one source register"));
10667 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10668 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10669 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10679 Rd
= inst
.operands
[0].reg
;
10680 reject_bad_reg (Rd
);
10682 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10684 /* Defer to section relaxation. */
10685 inst
.relax
= inst
.instruction
;
10686 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10687 inst
.instruction
|= Rd
<< 4;
10689 else if (unified_syntax
&& inst
.size_req
!= 2)
10691 /* Generate a 32-bit opcode. */
10692 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10693 inst
.instruction
|= Rd
<< 8;
10694 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10695 inst
.reloc
.pc_rel
= 1;
10699 /* Generate a 16-bit opcode. */
10700 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10701 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10702 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10703 inst
.reloc
.pc_rel
= 1;
10705 inst
.instruction
|= Rd
<< 4;
10709 /* Arithmetic instructions for which there is just one 16-bit
10710 instruction encoding, and it allows only two low registers.
10711 For maximal compatibility with ARM syntax, we allow three register
10712 operands even when Thumb-32 instructions are not available, as long
10713 as the first two are identical. For instance, both "sbc r0,r1" and
10714 "sbc r0,r0,r1" are allowed. */
10720 Rd
= inst
.operands
[0].reg
;
10721 Rs
= (inst
.operands
[1].present
10722 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10723 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10724 Rn
= inst
.operands
[2].reg
;
10726 reject_bad_reg (Rd
);
10727 reject_bad_reg (Rs
);
10728 if (inst
.operands
[2].isreg
)
10729 reject_bad_reg (Rn
);
10731 if (unified_syntax
)
10733 if (!inst
.operands
[2].isreg
)
10735 /* For an immediate, we always generate a 32-bit opcode;
10736 section relaxation will shrink it later if possible. */
10737 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10738 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10739 inst
.instruction
|= Rd
<< 8;
10740 inst
.instruction
|= Rs
<< 16;
10741 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10745 bfd_boolean narrow
;
10747 /* See if we can do this with a 16-bit instruction. */
10748 if (THUMB_SETS_FLAGS (inst
.instruction
))
10749 narrow
= !in_it_block ();
10751 narrow
= in_it_block ();
10753 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10755 if (inst
.operands
[2].shifted
)
10757 if (inst
.size_req
== 4)
10763 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10764 inst
.instruction
|= Rd
;
10765 inst
.instruction
|= Rn
<< 3;
10769 /* If we get here, it can't be done in 16 bits. */
10770 constraint (inst
.operands
[2].shifted
10771 && inst
.operands
[2].immisreg
,
10772 _("shift must be constant"));
10773 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10774 inst
.instruction
|= Rd
<< 8;
10775 inst
.instruction
|= Rs
<< 16;
10776 encode_thumb32_shifted_operand (2);
10781 /* On its face this is a lie - the instruction does set the
10782 flags. However, the only supported mnemonic in this mode
10783 says it doesn't. */
10784 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10786 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10787 _("unshifted register required"));
10788 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10789 constraint (Rd
!= Rs
,
10790 _("dest and source1 must be the same register"));
10792 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10793 inst
.instruction
|= Rd
;
10794 inst
.instruction
|= Rn
<< 3;
10798 /* Similarly, but for instructions where the arithmetic operation is
10799 commutative, so we can allow either of them to be different from
10800 the destination operand in a 16-bit instruction. For instance, all
10801 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10808 Rd
= inst
.operands
[0].reg
;
10809 Rs
= (inst
.operands
[1].present
10810 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10811 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10812 Rn
= inst
.operands
[2].reg
;
10814 reject_bad_reg (Rd
);
10815 reject_bad_reg (Rs
);
10816 if (inst
.operands
[2].isreg
)
10817 reject_bad_reg (Rn
);
10819 if (unified_syntax
)
10821 if (!inst
.operands
[2].isreg
)
10823 /* For an immediate, we always generate a 32-bit opcode;
10824 section relaxation will shrink it later if possible. */
10825 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10826 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10827 inst
.instruction
|= Rd
<< 8;
10828 inst
.instruction
|= Rs
<< 16;
10829 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10833 bfd_boolean narrow
;
10835 /* See if we can do this with a 16-bit instruction. */
10836 if (THUMB_SETS_FLAGS (inst
.instruction
))
10837 narrow
= !in_it_block ();
10839 narrow
= in_it_block ();
10841 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10843 if (inst
.operands
[2].shifted
)
10845 if (inst
.size_req
== 4)
10852 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10853 inst
.instruction
|= Rd
;
10854 inst
.instruction
|= Rn
<< 3;
10859 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10860 inst
.instruction
|= Rd
;
10861 inst
.instruction
|= Rs
<< 3;
10866 /* If we get here, it can't be done in 16 bits. */
10867 constraint (inst
.operands
[2].shifted
10868 && inst
.operands
[2].immisreg
,
10869 _("shift must be constant"));
10870 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10871 inst
.instruction
|= Rd
<< 8;
10872 inst
.instruction
|= Rs
<< 16;
10873 encode_thumb32_shifted_operand (2);
10878 /* On its face this is a lie - the instruction does set the
10879 flags. However, the only supported mnemonic in this mode
10880 says it doesn't. */
10881 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10883 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10884 _("unshifted register required"));
10885 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10887 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10888 inst
.instruction
|= Rd
;
10891 inst
.instruction
|= Rn
<< 3;
10893 inst
.instruction
|= Rs
<< 3;
10895 constraint (1, _("dest must overlap one source register"));
10903 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10904 constraint (msb
> 32, _("bit-field extends past end of register"));
10905 /* The instruction encoding stores the LSB and MSB,
10906 not the LSB and width. */
10907 Rd
= inst
.operands
[0].reg
;
10908 reject_bad_reg (Rd
);
10909 inst
.instruction
|= Rd
<< 8;
10910 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10911 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10912 inst
.instruction
|= msb
- 1;
10921 Rd
= inst
.operands
[0].reg
;
10922 reject_bad_reg (Rd
);
10924 /* #0 in second position is alternative syntax for bfc, which is
10925 the same instruction but with REG_PC in the Rm field. */
10926 if (!inst
.operands
[1].isreg
)
10930 Rn
= inst
.operands
[1].reg
;
10931 reject_bad_reg (Rn
);
10934 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10935 constraint (msb
> 32, _("bit-field extends past end of register"));
10936 /* The instruction encoding stores the LSB and MSB,
10937 not the LSB and width. */
10938 inst
.instruction
|= Rd
<< 8;
10939 inst
.instruction
|= Rn
<< 16;
10940 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10941 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10942 inst
.instruction
|= msb
- 1;
10950 Rd
= inst
.operands
[0].reg
;
10951 Rn
= inst
.operands
[1].reg
;
10953 reject_bad_reg (Rd
);
10954 reject_bad_reg (Rn
);
10956 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10957 _("bit-field extends past end of register"));
10958 inst
.instruction
|= Rd
<< 8;
10959 inst
.instruction
|= Rn
<< 16;
10960 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10961 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10962 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10965 /* ARM V5 Thumb BLX (argument parse)
10966 BLX <target_addr> which is BLX(1)
10967 BLX <Rm> which is BLX(2)
10968 Unfortunately, there are two different opcodes for this mnemonic.
10969 So, the insns[].value is not used, and the code here zaps values
10970 into inst.instruction.
10972 ??? How to take advantage of the additional two bits of displacement
10973 available in Thumb32 mode? Need new relocation? */
10978 set_it_insn_type_last ();
10980 if (inst
.operands
[0].isreg
)
10982 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10983 /* We have a register, so this is BLX(2). */
10984 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10988 /* No register. This must be BLX(1). */
10989 inst
.instruction
= 0xf000e800;
10990 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10999 bfd_reloc_code_real_type reloc
;
11002 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11004 if (in_it_block ())
11006 /* Conditional branches inside IT blocks are encoded as unconditional
11008 cond
= COND_ALWAYS
;
11013 if (cond
!= COND_ALWAYS
)
11014 opcode
= T_MNEM_bcond
;
11016 opcode
= inst
.instruction
;
11019 && (inst
.size_req
== 4
11020 || (inst
.size_req
!= 2
11021 && (inst
.operands
[0].hasreloc
11022 || inst
.reloc
.exp
.X_op
== O_constant
))))
11024 inst
.instruction
= THUMB_OP32(opcode
);
11025 if (cond
== COND_ALWAYS
)
11026 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11029 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11030 _("selected architecture does not support "
11031 "wide conditional branch instruction"));
11033 gas_assert (cond
!= 0xF);
11034 inst
.instruction
|= cond
<< 22;
11035 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11040 inst
.instruction
= THUMB_OP16(opcode
);
11041 if (cond
== COND_ALWAYS
)
11042 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11045 inst
.instruction
|= cond
<< 8;
11046 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11048 /* Allow section relaxation. */
11049 if (unified_syntax
&& inst
.size_req
!= 2)
11050 inst
.relax
= opcode
;
11052 inst
.reloc
.type
= reloc
;
11053 inst
.reloc
.pc_rel
= 1;
11056 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11057 between the two is the maximum immediate allowed - which is passed in
11060 do_t_bkpt_hlt1 (int range
)
11062 constraint (inst
.cond
!= COND_ALWAYS
,
11063 _("instruction is always unconditional"));
11064 if (inst
.operands
[0].present
)
11066 constraint (inst
.operands
[0].imm
> range
,
11067 _("immediate value out of range"));
11068 inst
.instruction
|= inst
.operands
[0].imm
;
11071 set_it_insn_type (NEUTRAL_IT_INSN
);
11077 do_t_bkpt_hlt1 (63);
11083 do_t_bkpt_hlt1 (255);
11087 do_t_branch23 (void)
11089 set_it_insn_type_last ();
11090 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11092 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11093 this file. We used to simply ignore the PLT reloc type here --
11094 the branch encoding is now needed to deal with TLSCALL relocs.
11095 So if we see a PLT reloc now, put it back to how it used to be to
11096 keep the preexisting behaviour. */
11097 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11098 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11100 #if defined(OBJ_COFF)
11101 /* If the destination of the branch is a defined symbol which does not have
11102 the THUMB_FUNC attribute, then we must be calling a function which has
11103 the (interfacearm) attribute. We look for the Thumb entry point to that
11104 function and change the branch to refer to that function instead. */
11105 if ( inst
.reloc
.exp
.X_op
== O_symbol
11106 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11107 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11108 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11109 inst
.reloc
.exp
.X_add_symbol
=
11110 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11117 set_it_insn_type_last ();
11118 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11119 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11120 should cause the alignment to be checked once it is known. This is
11121 because BX PC only works if the instruction is word aligned. */
11129 set_it_insn_type_last ();
11130 Rm
= inst
.operands
[0].reg
;
11131 reject_bad_reg (Rm
);
11132 inst
.instruction
|= Rm
<< 16;
11141 Rd
= inst
.operands
[0].reg
;
11142 Rm
= inst
.operands
[1].reg
;
11144 reject_bad_reg (Rd
);
11145 reject_bad_reg (Rm
);
11147 inst
.instruction
|= Rd
<< 8;
11148 inst
.instruction
|= Rm
<< 16;
11149 inst
.instruction
|= Rm
;
11155 set_it_insn_type (OUTSIDE_IT_INSN
);
11156 inst
.instruction
|= inst
.operands
[0].imm
;
11162 set_it_insn_type (OUTSIDE_IT_INSN
);
11164 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11165 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11167 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11168 inst
.instruction
= 0xf3af8000;
11169 inst
.instruction
|= imod
<< 9;
11170 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11171 if (inst
.operands
[1].present
)
11172 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11176 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11177 && (inst
.operands
[0].imm
& 4),
11178 _("selected processor does not support 'A' form "
11179 "of this instruction"));
11180 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11181 _("Thumb does not support the 2-argument "
11182 "form of this instruction"));
11183 inst
.instruction
|= inst
.operands
[0].imm
;
11187 /* THUMB CPY instruction (argument parse). */
11192 if (inst
.size_req
== 4)
11194 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11195 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11196 inst
.instruction
|= inst
.operands
[1].reg
;
11200 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11201 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11202 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11209 set_it_insn_type (OUTSIDE_IT_INSN
);
11210 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11211 inst
.instruction
|= inst
.operands
[0].reg
;
11212 inst
.reloc
.pc_rel
= 1;
11213 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11219 inst
.instruction
|= inst
.operands
[0].imm
;
11225 unsigned Rd
, Rn
, Rm
;
11227 Rd
= inst
.operands
[0].reg
;
11228 Rn
= (inst
.operands
[1].present
11229 ? inst
.operands
[1].reg
: Rd
);
11230 Rm
= inst
.operands
[2].reg
;
11232 reject_bad_reg (Rd
);
11233 reject_bad_reg (Rn
);
11234 reject_bad_reg (Rm
);
11236 inst
.instruction
|= Rd
<< 8;
11237 inst
.instruction
|= Rn
<< 16;
11238 inst
.instruction
|= Rm
;
11244 if (unified_syntax
&& inst
.size_req
== 4)
11245 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11247 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11253 unsigned int cond
= inst
.operands
[0].imm
;
11255 set_it_insn_type (IT_INSN
);
11256 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11258 now_it
.warn_deprecated
= FALSE
;
11260 /* If the condition is a negative condition, invert the mask. */
11261 if ((cond
& 0x1) == 0x0)
11263 unsigned int mask
= inst
.instruction
& 0x000f;
11265 if ((mask
& 0x7) == 0)
11267 /* No conversion needed. */
11268 now_it
.block_length
= 1;
11270 else if ((mask
& 0x3) == 0)
11273 now_it
.block_length
= 2;
11275 else if ((mask
& 0x1) == 0)
11278 now_it
.block_length
= 3;
11283 now_it
.block_length
= 4;
11286 inst
.instruction
&= 0xfff0;
11287 inst
.instruction
|= mask
;
11290 inst
.instruction
|= cond
<< 4;
11293 /* Helper function used for both push/pop and ldm/stm. */
11295 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11299 load
= (inst
.instruction
& (1 << 20)) != 0;
11301 if (mask
& (1 << 13))
11302 inst
.error
= _("SP not allowed in register list");
11304 if ((mask
& (1 << base
)) != 0
11306 inst
.error
= _("having the base register in the register list when "
11307 "using write back is UNPREDICTABLE");
11311 if (mask
& (1 << 15))
11313 if (mask
& (1 << 14))
11314 inst
.error
= _("LR and PC should not both be in register list");
11316 set_it_insn_type_last ();
11321 if (mask
& (1 << 15))
11322 inst
.error
= _("PC not allowed in register list");
11325 if ((mask
& (mask
- 1)) == 0)
11327 /* Single register transfers implemented as str/ldr. */
11330 if (inst
.instruction
& (1 << 23))
11331 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11333 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11337 if (inst
.instruction
& (1 << 23))
11338 inst
.instruction
= 0x00800000; /* ia -> [base] */
11340 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11343 inst
.instruction
|= 0xf8400000;
11345 inst
.instruction
|= 0x00100000;
11347 mask
= ffs (mask
) - 1;
11350 else if (writeback
)
11351 inst
.instruction
|= WRITE_BACK
;
11353 inst
.instruction
|= mask
;
11354 inst
.instruction
|= base
<< 16;
11360 /* This really doesn't seem worth it. */
11361 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11362 _("expression too complex"));
11363 constraint (inst
.operands
[1].writeback
,
11364 _("Thumb load/store multiple does not support {reglist}^"));
11366 if (unified_syntax
)
11368 bfd_boolean narrow
;
11372 /* See if we can use a 16-bit instruction. */
11373 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11374 && inst
.size_req
!= 4
11375 && !(inst
.operands
[1].imm
& ~0xff))
11377 mask
= 1 << inst
.operands
[0].reg
;
11379 if (inst
.operands
[0].reg
<= 7)
11381 if (inst
.instruction
== T_MNEM_stmia
11382 ? inst
.operands
[0].writeback
11383 : (inst
.operands
[0].writeback
11384 == !(inst
.operands
[1].imm
& mask
)))
11386 if (inst
.instruction
== T_MNEM_stmia
11387 && (inst
.operands
[1].imm
& mask
)
11388 && (inst
.operands
[1].imm
& (mask
- 1)))
11389 as_warn (_("value stored for r%d is UNKNOWN"),
11390 inst
.operands
[0].reg
);
11392 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11393 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11394 inst
.instruction
|= inst
.operands
[1].imm
;
11397 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11399 /* This means 1 register in reg list one of 3 situations:
11400 1. Instruction is stmia, but without writeback.
11401 2. lmdia without writeback, but with Rn not in
11403 3. ldmia with writeback, but with Rn in reglist.
11404 Case 3 is UNPREDICTABLE behaviour, so we handle
11405 case 1 and 2 which can be converted into a 16-bit
11406 str or ldr. The SP cases are handled below. */
11407 unsigned long opcode
;
11408 /* First, record an error for Case 3. */
11409 if (inst
.operands
[1].imm
& mask
11410 && inst
.operands
[0].writeback
)
11412 _("having the base register in the register list when "
11413 "using write back is UNPREDICTABLE");
11415 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11417 inst
.instruction
= THUMB_OP16 (opcode
);
11418 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11419 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11423 else if (inst
.operands
[0] .reg
== REG_SP
)
11425 if (inst
.operands
[0].writeback
)
11428 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11429 ? T_MNEM_push
: T_MNEM_pop
);
11430 inst
.instruction
|= inst
.operands
[1].imm
;
11433 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11436 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11437 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11438 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11446 if (inst
.instruction
< 0xffff)
11447 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11449 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11450 inst
.operands
[0].writeback
);
11455 constraint (inst
.operands
[0].reg
> 7
11456 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11457 constraint (inst
.instruction
!= T_MNEM_ldmia
11458 && inst
.instruction
!= T_MNEM_stmia
,
11459 _("Thumb-2 instruction only valid in unified syntax"));
11460 if (inst
.instruction
== T_MNEM_stmia
)
11462 if (!inst
.operands
[0].writeback
)
11463 as_warn (_("this instruction will write back the base register"));
11464 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11465 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11466 as_warn (_("value stored for r%d is UNKNOWN"),
11467 inst
.operands
[0].reg
);
11471 if (!inst
.operands
[0].writeback
11472 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11473 as_warn (_("this instruction will write back the base register"));
11474 else if (inst
.operands
[0].writeback
11475 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11476 as_warn (_("this instruction will not write back the base register"));
11479 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11480 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11481 inst
.instruction
|= inst
.operands
[1].imm
;
11488 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11489 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11490 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11491 || inst
.operands
[1].negative
,
11494 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11496 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11497 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11498 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11504 if (!inst
.operands
[1].present
)
11506 constraint (inst
.operands
[0].reg
== REG_LR
,
11507 _("r14 not allowed as first register "
11508 "when second register is omitted"));
11509 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11511 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11515 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11516 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11522 unsigned long opcode
;
11525 if (inst
.operands
[0].isreg
11526 && !inst
.operands
[0].preind
11527 && inst
.operands
[0].reg
== REG_PC
)
11528 set_it_insn_type_last ();
11530 opcode
= inst
.instruction
;
11531 if (unified_syntax
)
11533 if (!inst
.operands
[1].isreg
)
11535 if (opcode
<= 0xffff)
11536 inst
.instruction
= THUMB_OP32 (opcode
);
11537 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11540 if (inst
.operands
[1].isreg
11541 && !inst
.operands
[1].writeback
11542 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11543 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11544 && opcode
<= 0xffff
11545 && inst
.size_req
!= 4)
11547 /* Insn may have a 16-bit form. */
11548 Rn
= inst
.operands
[1].reg
;
11549 if (inst
.operands
[1].immisreg
)
11551 inst
.instruction
= THUMB_OP16 (opcode
);
11553 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11555 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11556 reject_bad_reg (inst
.operands
[1].imm
);
11558 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11559 && opcode
!= T_MNEM_ldrsb
)
11560 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11561 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11568 if (inst
.reloc
.pc_rel
)
11569 opcode
= T_MNEM_ldr_pc2
;
11571 opcode
= T_MNEM_ldr_pc
;
11575 if (opcode
== T_MNEM_ldr
)
11576 opcode
= T_MNEM_ldr_sp
;
11578 opcode
= T_MNEM_str_sp
;
11580 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11584 inst
.instruction
= inst
.operands
[0].reg
;
11585 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11587 inst
.instruction
|= THUMB_OP16 (opcode
);
11588 if (inst
.size_req
== 2)
11589 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11591 inst
.relax
= opcode
;
11595 /* Definitely a 32-bit variant. */
11597 /* Warning for Erratum 752419. */
11598 if (opcode
== T_MNEM_ldr
11599 && inst
.operands
[0].reg
== REG_SP
11600 && inst
.operands
[1].writeback
== 1
11601 && !inst
.operands
[1].immisreg
)
11603 if (no_cpu_selected ()
11604 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11605 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11606 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11607 as_warn (_("This instruction may be unpredictable "
11608 "if executed on M-profile cores "
11609 "with interrupts enabled."));
11612 /* Do some validations regarding addressing modes. */
11613 if (inst
.operands
[1].immisreg
)
11614 reject_bad_reg (inst
.operands
[1].imm
);
11616 constraint (inst
.operands
[1].writeback
== 1
11617 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11620 inst
.instruction
= THUMB_OP32 (opcode
);
11621 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11622 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11623 check_ldr_r15_aligned ();
11627 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11629 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11631 /* Only [Rn,Rm] is acceptable. */
11632 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11633 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11634 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11635 || inst
.operands
[1].negative
,
11636 _("Thumb does not support this addressing mode"));
11637 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11641 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11642 if (!inst
.operands
[1].isreg
)
11643 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11646 constraint (!inst
.operands
[1].preind
11647 || inst
.operands
[1].shifted
11648 || inst
.operands
[1].writeback
,
11649 _("Thumb does not support this addressing mode"));
11650 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11652 constraint (inst
.instruction
& 0x0600,
11653 _("byte or halfword not valid for base register"));
11654 constraint (inst
.operands
[1].reg
== REG_PC
11655 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11656 _("r15 based store not allowed"));
11657 constraint (inst
.operands
[1].immisreg
,
11658 _("invalid base register for register offset"));
11660 if (inst
.operands
[1].reg
== REG_PC
)
11661 inst
.instruction
= T_OPCODE_LDR_PC
;
11662 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11663 inst
.instruction
= T_OPCODE_LDR_SP
;
11665 inst
.instruction
= T_OPCODE_STR_SP
;
11667 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11668 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11672 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11673 if (!inst
.operands
[1].immisreg
)
11675 /* Immediate offset. */
11676 inst
.instruction
|= inst
.operands
[0].reg
;
11677 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11678 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11682 /* Register offset. */
11683 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11684 constraint (inst
.operands
[1].negative
,
11685 _("Thumb does not support this addressing mode"));
11688 switch (inst
.instruction
)
11690 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11691 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11692 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11693 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11694 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11695 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11696 case 0x5600 /* ldrsb */:
11697 case 0x5e00 /* ldrsh */: break;
11701 inst
.instruction
|= inst
.operands
[0].reg
;
11702 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11703 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11709 if (!inst
.operands
[1].present
)
11711 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11712 constraint (inst
.operands
[0].reg
== REG_LR
,
11713 _("r14 not allowed here"));
11714 constraint (inst
.operands
[0].reg
== REG_R12
,
11715 _("r12 not allowed here"));
11718 if (inst
.operands
[2].writeback
11719 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11720 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11721 as_warn (_("base register written back, and overlaps "
11722 "one of transfer registers"));
11724 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11725 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11726 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11732 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11733 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11739 unsigned Rd
, Rn
, Rm
, Ra
;
11741 Rd
= inst
.operands
[0].reg
;
11742 Rn
= inst
.operands
[1].reg
;
11743 Rm
= inst
.operands
[2].reg
;
11744 Ra
= inst
.operands
[3].reg
;
11746 reject_bad_reg (Rd
);
11747 reject_bad_reg (Rn
);
11748 reject_bad_reg (Rm
);
11749 reject_bad_reg (Ra
);
11751 inst
.instruction
|= Rd
<< 8;
11752 inst
.instruction
|= Rn
<< 16;
11753 inst
.instruction
|= Rm
;
11754 inst
.instruction
|= Ra
<< 12;
11760 unsigned RdLo
, RdHi
, Rn
, Rm
;
11762 RdLo
= inst
.operands
[0].reg
;
11763 RdHi
= inst
.operands
[1].reg
;
11764 Rn
= inst
.operands
[2].reg
;
11765 Rm
= inst
.operands
[3].reg
;
11767 reject_bad_reg (RdLo
);
11768 reject_bad_reg (RdHi
);
11769 reject_bad_reg (Rn
);
11770 reject_bad_reg (Rm
);
11772 inst
.instruction
|= RdLo
<< 12;
11773 inst
.instruction
|= RdHi
<< 8;
11774 inst
.instruction
|= Rn
<< 16;
11775 inst
.instruction
|= Rm
;
11779 do_t_mov_cmp (void)
11783 Rn
= inst
.operands
[0].reg
;
11784 Rm
= inst
.operands
[1].reg
;
11787 set_it_insn_type_last ();
11789 if (unified_syntax
)
11791 int r0off
= (inst
.instruction
== T_MNEM_mov
11792 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11793 unsigned long opcode
;
11794 bfd_boolean narrow
;
11795 bfd_boolean low_regs
;
11797 low_regs
= (Rn
<= 7 && Rm
<= 7);
11798 opcode
= inst
.instruction
;
11799 if (in_it_block ())
11800 narrow
= opcode
!= T_MNEM_movs
;
11802 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11803 if (inst
.size_req
== 4
11804 || inst
.operands
[1].shifted
)
11807 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11808 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11809 && !inst
.operands
[1].shifted
11813 inst
.instruction
= T2_SUBS_PC_LR
;
11817 if (opcode
== T_MNEM_cmp
)
11819 constraint (Rn
== REG_PC
, BAD_PC
);
11822 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11824 warn_deprecated_sp (Rm
);
11825 /* R15 was documented as a valid choice for Rm in ARMv6,
11826 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11827 tools reject R15, so we do too. */
11828 constraint (Rm
== REG_PC
, BAD_PC
);
11831 reject_bad_reg (Rm
);
11833 else if (opcode
== T_MNEM_mov
11834 || opcode
== T_MNEM_movs
)
11836 if (inst
.operands
[1].isreg
)
11838 if (opcode
== T_MNEM_movs
)
11840 reject_bad_reg (Rn
);
11841 reject_bad_reg (Rm
);
11845 /* This is mov.n. */
11846 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11847 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11849 as_tsktsk (_("Use of r%u as a source register is "
11850 "deprecated when r%u is the destination "
11851 "register."), Rm
, Rn
);
11856 /* This is mov.w. */
11857 constraint (Rn
== REG_PC
, BAD_PC
);
11858 constraint (Rm
== REG_PC
, BAD_PC
);
11859 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11863 reject_bad_reg (Rn
);
11866 if (!inst
.operands
[1].isreg
)
11868 /* Immediate operand. */
11869 if (!in_it_block () && opcode
== T_MNEM_mov
)
11871 if (low_regs
&& narrow
)
11873 inst
.instruction
= THUMB_OP16 (opcode
);
11874 inst
.instruction
|= Rn
<< 8;
11875 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11876 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11878 if (inst
.size_req
== 2)
11879 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11881 inst
.relax
= opcode
;
11886 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11887 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11888 THUMB1_RELOC_ONLY
);
11890 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11891 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11892 inst
.instruction
|= Rn
<< r0off
;
11893 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11896 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11897 && (inst
.instruction
== T_MNEM_mov
11898 || inst
.instruction
== T_MNEM_movs
))
11900 /* Register shifts are encoded as separate shift instructions. */
11901 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11903 if (in_it_block ())
11908 if (inst
.size_req
== 4)
11911 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11917 switch (inst
.operands
[1].shift_kind
)
11920 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11923 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11926 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11929 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11935 inst
.instruction
= opcode
;
11938 inst
.instruction
|= Rn
;
11939 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11944 inst
.instruction
|= CONDS_BIT
;
11946 inst
.instruction
|= Rn
<< 8;
11947 inst
.instruction
|= Rm
<< 16;
11948 inst
.instruction
|= inst
.operands
[1].imm
;
11953 /* Some mov with immediate shift have narrow variants.
11954 Register shifts are handled above. */
11955 if (low_regs
&& inst
.operands
[1].shifted
11956 && (inst
.instruction
== T_MNEM_mov
11957 || inst
.instruction
== T_MNEM_movs
))
11959 if (in_it_block ())
11960 narrow
= (inst
.instruction
== T_MNEM_mov
);
11962 narrow
= (inst
.instruction
== T_MNEM_movs
);
11967 switch (inst
.operands
[1].shift_kind
)
11969 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11970 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11971 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11972 default: narrow
= FALSE
; break;
11978 inst
.instruction
|= Rn
;
11979 inst
.instruction
|= Rm
<< 3;
11980 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11984 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11985 inst
.instruction
|= Rn
<< r0off
;
11986 encode_thumb32_shifted_operand (1);
11990 switch (inst
.instruction
)
11993 /* In v4t or v5t a move of two lowregs produces unpredictable
11994 results. Don't allow this. */
11997 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11998 "MOV Rd, Rs with two low registers is not "
11999 "permitted on this architecture");
12000 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12004 inst
.instruction
= T_OPCODE_MOV_HR
;
12005 inst
.instruction
|= (Rn
& 0x8) << 4;
12006 inst
.instruction
|= (Rn
& 0x7);
12007 inst
.instruction
|= Rm
<< 3;
12011 /* We know we have low registers at this point.
12012 Generate LSLS Rd, Rs, #0. */
12013 inst
.instruction
= T_OPCODE_LSL_I
;
12014 inst
.instruction
|= Rn
;
12015 inst
.instruction
|= Rm
<< 3;
12021 inst
.instruction
= T_OPCODE_CMP_LR
;
12022 inst
.instruction
|= Rn
;
12023 inst
.instruction
|= Rm
<< 3;
12027 inst
.instruction
= T_OPCODE_CMP_HR
;
12028 inst
.instruction
|= (Rn
& 0x8) << 4;
12029 inst
.instruction
|= (Rn
& 0x7);
12030 inst
.instruction
|= Rm
<< 3;
12037 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12039 /* PR 10443: Do not silently ignore shifted operands. */
12040 constraint (inst
.operands
[1].shifted
,
12041 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12043 if (inst
.operands
[1].isreg
)
12045 if (Rn
< 8 && Rm
< 8)
12047 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12048 since a MOV instruction produces unpredictable results. */
12049 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12050 inst
.instruction
= T_OPCODE_ADD_I3
;
12052 inst
.instruction
= T_OPCODE_CMP_LR
;
12054 inst
.instruction
|= Rn
;
12055 inst
.instruction
|= Rm
<< 3;
12059 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12060 inst
.instruction
= T_OPCODE_MOV_HR
;
12062 inst
.instruction
= T_OPCODE_CMP_HR
;
12068 constraint (Rn
> 7,
12069 _("only lo regs allowed with immediate"));
12070 inst
.instruction
|= Rn
<< 8;
12071 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12082 top
= (inst
.instruction
& 0x00800000) != 0;
12083 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12085 constraint (top
, _(":lower16: not allowed this instruction"));
12086 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12088 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12090 constraint (!top
, _(":upper16: not allowed this instruction"));
12091 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12094 Rd
= inst
.operands
[0].reg
;
12095 reject_bad_reg (Rd
);
12097 inst
.instruction
|= Rd
<< 8;
12098 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12100 imm
= inst
.reloc
.exp
.X_add_number
;
12101 inst
.instruction
|= (imm
& 0xf000) << 4;
12102 inst
.instruction
|= (imm
& 0x0800) << 15;
12103 inst
.instruction
|= (imm
& 0x0700) << 4;
12104 inst
.instruction
|= (imm
& 0x00ff);
12109 do_t_mvn_tst (void)
12113 Rn
= inst
.operands
[0].reg
;
12114 Rm
= inst
.operands
[1].reg
;
12116 if (inst
.instruction
== T_MNEM_cmp
12117 || inst
.instruction
== T_MNEM_cmn
)
12118 constraint (Rn
== REG_PC
, BAD_PC
);
12120 reject_bad_reg (Rn
);
12121 reject_bad_reg (Rm
);
12123 if (unified_syntax
)
12125 int r0off
= (inst
.instruction
== T_MNEM_mvn
12126 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12127 bfd_boolean narrow
;
12129 if (inst
.size_req
== 4
12130 || inst
.instruction
> 0xffff
12131 || inst
.operands
[1].shifted
12132 || Rn
> 7 || Rm
> 7)
12134 else if (inst
.instruction
== T_MNEM_cmn
12135 || inst
.instruction
== T_MNEM_tst
)
12137 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12138 narrow
= !in_it_block ();
12140 narrow
= in_it_block ();
12142 if (!inst
.operands
[1].isreg
)
12144 /* For an immediate, we always generate a 32-bit opcode;
12145 section relaxation will shrink it later if possible. */
12146 if (inst
.instruction
< 0xffff)
12147 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12148 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12149 inst
.instruction
|= Rn
<< r0off
;
12150 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12154 /* See if we can do this with a 16-bit instruction. */
12157 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12158 inst
.instruction
|= Rn
;
12159 inst
.instruction
|= Rm
<< 3;
12163 constraint (inst
.operands
[1].shifted
12164 && inst
.operands
[1].immisreg
,
12165 _("shift must be constant"));
12166 if (inst
.instruction
< 0xffff)
12167 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12168 inst
.instruction
|= Rn
<< r0off
;
12169 encode_thumb32_shifted_operand (1);
12175 constraint (inst
.instruction
> 0xffff
12176 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12177 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12178 _("unshifted register required"));
12179 constraint (Rn
> 7 || Rm
> 7,
12182 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12183 inst
.instruction
|= Rn
;
12184 inst
.instruction
|= Rm
<< 3;
12193 if (do_vfp_nsyn_mrs () == SUCCESS
)
12196 Rd
= inst
.operands
[0].reg
;
12197 reject_bad_reg (Rd
);
12198 inst
.instruction
|= Rd
<< 8;
12200 if (inst
.operands
[1].isreg
)
12202 unsigned br
= inst
.operands
[1].reg
;
12203 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12204 as_bad (_("bad register for mrs"));
12206 inst
.instruction
|= br
& (0xf << 16);
12207 inst
.instruction
|= (br
& 0x300) >> 4;
12208 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12212 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12214 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12216 /* PR gas/12698: The constraint is only applied for m_profile.
12217 If the user has specified -march=all, we want to ignore it as
12218 we are building for any CPU type, including non-m variants. */
12219 bfd_boolean m_profile
=
12220 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12221 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12222 "not support requested special purpose register"));
12225 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12227 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12228 _("'APSR', 'CPSR' or 'SPSR' expected"));
12230 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12231 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12232 inst
.instruction
|= 0xf0000;
12242 if (do_vfp_nsyn_msr () == SUCCESS
)
12245 constraint (!inst
.operands
[1].isreg
,
12246 _("Thumb encoding does not support an immediate here"));
12248 if (inst
.operands
[0].isreg
)
12249 flags
= (int)(inst
.operands
[0].reg
);
12251 flags
= inst
.operands
[0].imm
;
12253 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12255 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12257 /* PR gas/12698: The constraint is only applied for m_profile.
12258 If the user has specified -march=all, we want to ignore it as
12259 we are building for any CPU type, including non-m variants. */
12260 bfd_boolean m_profile
=
12261 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12262 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12263 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12264 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12265 && bits
!= PSR_f
)) && m_profile
,
12266 _("selected processor does not support requested special "
12267 "purpose register"));
12270 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12271 "requested special purpose register"));
12273 Rn
= inst
.operands
[1].reg
;
12274 reject_bad_reg (Rn
);
12276 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12277 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12278 inst
.instruction
|= (flags
& 0x300) >> 4;
12279 inst
.instruction
|= (flags
& 0xff);
12280 inst
.instruction
|= Rn
<< 16;
12286 bfd_boolean narrow
;
12287 unsigned Rd
, Rn
, Rm
;
12289 if (!inst
.operands
[2].present
)
12290 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12292 Rd
= inst
.operands
[0].reg
;
12293 Rn
= inst
.operands
[1].reg
;
12294 Rm
= inst
.operands
[2].reg
;
12296 if (unified_syntax
)
12298 if (inst
.size_req
== 4
12304 else if (inst
.instruction
== T_MNEM_muls
)
12305 narrow
= !in_it_block ();
12307 narrow
= in_it_block ();
12311 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12312 constraint (Rn
> 7 || Rm
> 7,
12319 /* 16-bit MULS/Conditional MUL. */
12320 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12321 inst
.instruction
|= Rd
;
12324 inst
.instruction
|= Rm
<< 3;
12326 inst
.instruction
|= Rn
<< 3;
12328 constraint (1, _("dest must overlap one source register"));
12332 constraint (inst
.instruction
!= T_MNEM_mul
,
12333 _("Thumb-2 MUL must not set flags"));
12335 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12336 inst
.instruction
|= Rd
<< 8;
12337 inst
.instruction
|= Rn
<< 16;
12338 inst
.instruction
|= Rm
<< 0;
12340 reject_bad_reg (Rd
);
12341 reject_bad_reg (Rn
);
12342 reject_bad_reg (Rm
);
12349 unsigned RdLo
, RdHi
, Rn
, Rm
;
12351 RdLo
= inst
.operands
[0].reg
;
12352 RdHi
= inst
.operands
[1].reg
;
12353 Rn
= inst
.operands
[2].reg
;
12354 Rm
= inst
.operands
[3].reg
;
12356 reject_bad_reg (RdLo
);
12357 reject_bad_reg (RdHi
);
12358 reject_bad_reg (Rn
);
12359 reject_bad_reg (Rm
);
12361 inst
.instruction
|= RdLo
<< 12;
12362 inst
.instruction
|= RdHi
<< 8;
12363 inst
.instruction
|= Rn
<< 16;
12364 inst
.instruction
|= Rm
;
12367 as_tsktsk (_("rdhi and rdlo must be different"));
12373 set_it_insn_type (NEUTRAL_IT_INSN
);
12375 if (unified_syntax
)
12377 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12379 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12380 inst
.instruction
|= inst
.operands
[0].imm
;
12384 /* PR9722: Check for Thumb2 availability before
12385 generating a thumb2 nop instruction. */
12386 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12388 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12389 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12392 inst
.instruction
= 0x46c0;
12397 constraint (inst
.operands
[0].present
,
12398 _("Thumb does not support NOP with hints"));
12399 inst
.instruction
= 0x46c0;
12406 if (unified_syntax
)
12408 bfd_boolean narrow
;
12410 if (THUMB_SETS_FLAGS (inst
.instruction
))
12411 narrow
= !in_it_block ();
12413 narrow
= in_it_block ();
12414 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12416 if (inst
.size_req
== 4)
12421 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12422 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12423 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12427 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12428 inst
.instruction
|= inst
.operands
[0].reg
;
12429 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12434 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12436 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12438 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12439 inst
.instruction
|= inst
.operands
[0].reg
;
12440 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12449 Rd
= inst
.operands
[0].reg
;
12450 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12452 reject_bad_reg (Rd
);
12453 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12454 reject_bad_reg (Rn
);
12456 inst
.instruction
|= Rd
<< 8;
12457 inst
.instruction
|= Rn
<< 16;
12459 if (!inst
.operands
[2].isreg
)
12461 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12462 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12468 Rm
= inst
.operands
[2].reg
;
12469 reject_bad_reg (Rm
);
12471 constraint (inst
.operands
[2].shifted
12472 && inst
.operands
[2].immisreg
,
12473 _("shift must be constant"));
12474 encode_thumb32_shifted_operand (2);
12481 unsigned Rd
, Rn
, Rm
;
12483 Rd
= inst
.operands
[0].reg
;
12484 Rn
= inst
.operands
[1].reg
;
12485 Rm
= inst
.operands
[2].reg
;
12487 reject_bad_reg (Rd
);
12488 reject_bad_reg (Rn
);
12489 reject_bad_reg (Rm
);
12491 inst
.instruction
|= Rd
<< 8;
12492 inst
.instruction
|= Rn
<< 16;
12493 inst
.instruction
|= Rm
;
12494 if (inst
.operands
[3].present
)
12496 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12497 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12498 _("expression too complex"));
12499 inst
.instruction
|= (val
& 0x1c) << 10;
12500 inst
.instruction
|= (val
& 0x03) << 6;
12507 if (!inst
.operands
[3].present
)
12511 inst
.instruction
&= ~0x00000020;
12513 /* PR 10168. Swap the Rm and Rn registers. */
12514 Rtmp
= inst
.operands
[1].reg
;
12515 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12516 inst
.operands
[2].reg
= Rtmp
;
12524 if (inst
.operands
[0].immisreg
)
12525 reject_bad_reg (inst
.operands
[0].imm
);
12527 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12531 do_t_push_pop (void)
12535 constraint (inst
.operands
[0].writeback
,
12536 _("push/pop do not support {reglist}^"));
12537 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12538 _("expression too complex"));
12540 mask
= inst
.operands
[0].imm
;
12541 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12542 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12543 else if (inst
.size_req
!= 4
12544 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12545 ? REG_LR
: REG_PC
)))
12547 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12548 inst
.instruction
|= THUMB_PP_PC_LR
;
12549 inst
.instruction
|= mask
& 0xff;
12551 else if (unified_syntax
)
12553 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12554 encode_thumb2_ldmstm (13, mask
, TRUE
);
12558 inst
.error
= _("invalid register list to push/pop instruction");
12568 Rd
= inst
.operands
[0].reg
;
12569 Rm
= inst
.operands
[1].reg
;
12571 reject_bad_reg (Rd
);
12572 reject_bad_reg (Rm
);
12574 inst
.instruction
|= Rd
<< 8;
12575 inst
.instruction
|= Rm
<< 16;
12576 inst
.instruction
|= Rm
;
12584 Rd
= inst
.operands
[0].reg
;
12585 Rm
= inst
.operands
[1].reg
;
12587 reject_bad_reg (Rd
);
12588 reject_bad_reg (Rm
);
12590 if (Rd
<= 7 && Rm
<= 7
12591 && inst
.size_req
!= 4)
12593 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12594 inst
.instruction
|= Rd
;
12595 inst
.instruction
|= Rm
<< 3;
12597 else if (unified_syntax
)
12599 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12600 inst
.instruction
|= Rd
<< 8;
12601 inst
.instruction
|= Rm
<< 16;
12602 inst
.instruction
|= Rm
;
12605 inst
.error
= BAD_HIREG
;
12613 Rd
= inst
.operands
[0].reg
;
12614 Rm
= inst
.operands
[1].reg
;
12616 reject_bad_reg (Rd
);
12617 reject_bad_reg (Rm
);
12619 inst
.instruction
|= Rd
<< 8;
12620 inst
.instruction
|= Rm
;
12628 Rd
= inst
.operands
[0].reg
;
12629 Rs
= (inst
.operands
[1].present
12630 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12631 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12633 reject_bad_reg (Rd
);
12634 reject_bad_reg (Rs
);
12635 if (inst
.operands
[2].isreg
)
12636 reject_bad_reg (inst
.operands
[2].reg
);
12638 inst
.instruction
|= Rd
<< 8;
12639 inst
.instruction
|= Rs
<< 16;
12640 if (!inst
.operands
[2].isreg
)
12642 bfd_boolean narrow
;
12644 if ((inst
.instruction
& 0x00100000) != 0)
12645 narrow
= !in_it_block ();
12647 narrow
= in_it_block ();
12649 if (Rd
> 7 || Rs
> 7)
12652 if (inst
.size_req
== 4 || !unified_syntax
)
12655 if (inst
.reloc
.exp
.X_op
!= O_constant
12656 || inst
.reloc
.exp
.X_add_number
!= 0)
12659 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12660 relaxation, but it doesn't seem worth the hassle. */
12663 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12664 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12665 inst
.instruction
|= Rs
<< 3;
12666 inst
.instruction
|= Rd
;
12670 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12671 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12675 encode_thumb32_shifted_operand (2);
12681 if (warn_on_deprecated
12682 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12683 as_tsktsk (_("setend use is deprecated for ARMv8"));
12685 set_it_insn_type (OUTSIDE_IT_INSN
);
12686 if (inst
.operands
[0].imm
)
12687 inst
.instruction
|= 0x8;
12693 if (!inst
.operands
[1].present
)
12694 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12696 if (unified_syntax
)
12698 bfd_boolean narrow
;
12701 switch (inst
.instruction
)
12704 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12706 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12708 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12710 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12714 if (THUMB_SETS_FLAGS (inst
.instruction
))
12715 narrow
= !in_it_block ();
12717 narrow
= in_it_block ();
12718 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12720 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12722 if (inst
.operands
[2].isreg
12723 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12724 || inst
.operands
[2].reg
> 7))
12726 if (inst
.size_req
== 4)
12729 reject_bad_reg (inst
.operands
[0].reg
);
12730 reject_bad_reg (inst
.operands
[1].reg
);
12734 if (inst
.operands
[2].isreg
)
12736 reject_bad_reg (inst
.operands
[2].reg
);
12737 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12738 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12739 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12740 inst
.instruction
|= inst
.operands
[2].reg
;
12742 /* PR 12854: Error on extraneous shifts. */
12743 constraint (inst
.operands
[2].shifted
,
12744 _("extraneous shift as part of operand to shift insn"));
12748 inst
.operands
[1].shifted
= 1;
12749 inst
.operands
[1].shift_kind
= shift_kind
;
12750 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12751 ? T_MNEM_movs
: T_MNEM_mov
);
12752 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12753 encode_thumb32_shifted_operand (1);
12754 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12755 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12760 if (inst
.operands
[2].isreg
)
12762 switch (shift_kind
)
12764 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12765 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12766 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12767 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12771 inst
.instruction
|= inst
.operands
[0].reg
;
12772 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12774 /* PR 12854: Error on extraneous shifts. */
12775 constraint (inst
.operands
[2].shifted
,
12776 _("extraneous shift as part of operand to shift insn"));
12780 switch (shift_kind
)
12782 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12783 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12784 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12787 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12788 inst
.instruction
|= inst
.operands
[0].reg
;
12789 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12795 constraint (inst
.operands
[0].reg
> 7
12796 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12797 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12799 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12801 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12802 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12803 _("source1 and dest must be same register"));
12805 switch (inst
.instruction
)
12807 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12808 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12809 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12810 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12814 inst
.instruction
|= inst
.operands
[0].reg
;
12815 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12817 /* PR 12854: Error on extraneous shifts. */
12818 constraint (inst
.operands
[2].shifted
,
12819 _("extraneous shift as part of operand to shift insn"));
12823 switch (inst
.instruction
)
12825 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12826 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12827 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12828 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12831 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12832 inst
.instruction
|= inst
.operands
[0].reg
;
12833 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12841 unsigned Rd
, Rn
, Rm
;
12843 Rd
= inst
.operands
[0].reg
;
12844 Rn
= inst
.operands
[1].reg
;
12845 Rm
= inst
.operands
[2].reg
;
12847 reject_bad_reg (Rd
);
12848 reject_bad_reg (Rn
);
12849 reject_bad_reg (Rm
);
12851 inst
.instruction
|= Rd
<< 8;
12852 inst
.instruction
|= Rn
<< 16;
12853 inst
.instruction
|= Rm
;
12859 unsigned Rd
, Rn
, Rm
;
12861 Rd
= inst
.operands
[0].reg
;
12862 Rm
= inst
.operands
[1].reg
;
12863 Rn
= inst
.operands
[2].reg
;
12865 reject_bad_reg (Rd
);
12866 reject_bad_reg (Rn
);
12867 reject_bad_reg (Rm
);
12869 inst
.instruction
|= Rd
<< 8;
12870 inst
.instruction
|= Rn
<< 16;
12871 inst
.instruction
|= Rm
;
12877 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12878 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12879 _("SMC is not permitted on this architecture"));
12880 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12881 _("expression too complex"));
12882 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12883 inst
.instruction
|= (value
& 0xf000) >> 12;
12884 inst
.instruction
|= (value
& 0x0ff0);
12885 inst
.instruction
|= (value
& 0x000f) << 16;
12886 /* PR gas/15623: SMC instructions must be last in an IT block. */
12887 set_it_insn_type_last ();
12893 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12895 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12896 inst
.instruction
|= (value
& 0x0fff);
12897 inst
.instruction
|= (value
& 0xf000) << 4;
12901 do_t_ssat_usat (int bias
)
12905 Rd
= inst
.operands
[0].reg
;
12906 Rn
= inst
.operands
[2].reg
;
12908 reject_bad_reg (Rd
);
12909 reject_bad_reg (Rn
);
12911 inst
.instruction
|= Rd
<< 8;
12912 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12913 inst
.instruction
|= Rn
<< 16;
12915 if (inst
.operands
[3].present
)
12917 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12919 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12921 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12922 _("expression too complex"));
12924 if (shift_amount
!= 0)
12926 constraint (shift_amount
> 31,
12927 _("shift expression is too large"));
12929 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12930 inst
.instruction
|= 0x00200000; /* sh bit. */
12932 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12933 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12941 do_t_ssat_usat (1);
12949 Rd
= inst
.operands
[0].reg
;
12950 Rn
= inst
.operands
[2].reg
;
12952 reject_bad_reg (Rd
);
12953 reject_bad_reg (Rn
);
12955 inst
.instruction
|= Rd
<< 8;
12956 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12957 inst
.instruction
|= Rn
<< 16;
12963 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12964 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12965 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12966 || inst
.operands
[2].negative
,
12969 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12971 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12972 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12973 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12974 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12980 if (!inst
.operands
[2].present
)
12981 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12983 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12984 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12985 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12988 inst
.instruction
|= inst
.operands
[0].reg
;
12989 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12990 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12991 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12997 unsigned Rd
, Rn
, Rm
;
12999 Rd
= inst
.operands
[0].reg
;
13000 Rn
= inst
.operands
[1].reg
;
13001 Rm
= inst
.operands
[2].reg
;
13003 reject_bad_reg (Rd
);
13004 reject_bad_reg (Rn
);
13005 reject_bad_reg (Rm
);
13007 inst
.instruction
|= Rd
<< 8;
13008 inst
.instruction
|= Rn
<< 16;
13009 inst
.instruction
|= Rm
;
13010 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13018 Rd
= inst
.operands
[0].reg
;
13019 Rm
= inst
.operands
[1].reg
;
13021 reject_bad_reg (Rd
);
13022 reject_bad_reg (Rm
);
13024 if (inst
.instruction
<= 0xffff
13025 && inst
.size_req
!= 4
13026 && Rd
<= 7 && Rm
<= 7
13027 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13029 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13030 inst
.instruction
|= Rd
;
13031 inst
.instruction
|= Rm
<< 3;
13033 else if (unified_syntax
)
13035 if (inst
.instruction
<= 0xffff)
13036 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13037 inst
.instruction
|= Rd
<< 8;
13038 inst
.instruction
|= Rm
;
13039 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13043 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13044 _("Thumb encoding does not support rotation"));
13045 constraint (1, BAD_HIREG
);
13052 /* We have to do the following check manually as ARM_EXT_OS only applies
13054 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13056 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13057 /* This only applies to the v6m howver, not later architectures. */
13058 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13059 as_bad (_("SVC is not permitted on this architecture"));
13060 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13063 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13072 half
= (inst
.instruction
& 0x10) != 0;
13073 set_it_insn_type_last ();
13074 constraint (inst
.operands
[0].immisreg
,
13075 _("instruction requires register index"));
13077 Rn
= inst
.operands
[0].reg
;
13078 Rm
= inst
.operands
[0].imm
;
13080 constraint (Rn
== REG_SP
, BAD_SP
);
13081 reject_bad_reg (Rm
);
13083 constraint (!half
&& inst
.operands
[0].shifted
,
13084 _("instruction does not allow shifted index"));
13085 inst
.instruction
|= (Rn
<< 16) | Rm
;
13091 if (!inst
.operands
[0].present
)
13092 inst
.operands
[0].imm
= 0;
13094 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13096 constraint (inst
.size_req
== 2,
13097 _("immediate value out of range"));
13098 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13099 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13100 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13104 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13105 inst
.instruction
|= inst
.operands
[0].imm
;
13108 set_it_insn_type (NEUTRAL_IT_INSN
);
13115 do_t_ssat_usat (0);
13123 Rd
= inst
.operands
[0].reg
;
13124 Rn
= inst
.operands
[2].reg
;
13126 reject_bad_reg (Rd
);
13127 reject_bad_reg (Rn
);
13129 inst
.instruction
|= Rd
<< 8;
13130 inst
.instruction
|= inst
.operands
[1].imm
;
13131 inst
.instruction
|= Rn
<< 16;
13134 /* Neon instruction encoder helpers. */
13136 /* Encodings for the different types for various Neon opcodes. */
13138 /* An "invalid" code for the following tables. */
13141 struct neon_tab_entry
13144 unsigned float_or_poly
;
13145 unsigned scalar_or_imm
;
13148 /* Map overloaded Neon opcodes to their respective encodings. */
13149 #define NEON_ENC_TAB \
13150 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13151 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13152 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13153 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13154 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13155 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13156 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13157 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13158 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13159 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13160 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13161 /* Register variants of the following two instructions are encoded as
13162 vcge / vcgt with the operands reversed. */ \
13163 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13164 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13165 X(vfma, N_INV, 0x0000c10, N_INV), \
13166 X(vfms, N_INV, 0x0200c10, N_INV), \
13167 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13168 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13169 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13170 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13171 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13172 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13173 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13174 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13175 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13176 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13177 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13178 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13179 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13180 X(vshl, 0x0000400, N_INV, 0x0800510), \
13181 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13182 X(vand, 0x0000110, N_INV, 0x0800030), \
13183 X(vbic, 0x0100110, N_INV, 0x0800030), \
13184 X(veor, 0x1000110, N_INV, N_INV), \
13185 X(vorn, 0x0300110, N_INV, 0x0800010), \
13186 X(vorr, 0x0200110, N_INV, 0x0800010), \
13187 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13188 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13189 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13190 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13191 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13192 X(vst1, 0x0000000, 0x0800000, N_INV), \
13193 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13194 X(vst2, 0x0000100, 0x0800100, N_INV), \
13195 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13196 X(vst3, 0x0000200, 0x0800200, N_INV), \
13197 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13198 X(vst4, 0x0000300, 0x0800300, N_INV), \
13199 X(vmovn, 0x1b20200, N_INV, N_INV), \
13200 X(vtrn, 0x1b20080, N_INV, N_INV), \
13201 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13202 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13203 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13204 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13205 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13206 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13207 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13208 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13209 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13210 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13211 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13212 X(vseleq, 0xe000a00, N_INV, N_INV), \
13213 X(vselvs, 0xe100a00, N_INV, N_INV), \
13214 X(vselge, 0xe200a00, N_INV, N_INV), \
13215 X(vselgt, 0xe300a00, N_INV, N_INV), \
13216 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13217 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13218 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13219 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13220 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13221 X(aes, 0x3b00300, N_INV, N_INV), \
13222 X(sha3op, 0x2000c00, N_INV, N_INV), \
13223 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13224 X(sha2op, 0x3ba0380, N_INV, N_INV)
13228 #define X(OPC,I,F,S) N_MNEM_##OPC
13233 static const struct neon_tab_entry neon_enc_tab
[] =
13235 #define X(OPC,I,F,S) { (I), (F), (S) }
13240 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13241 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13242 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13243 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13244 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13245 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13246 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13247 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13248 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13249 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13250 #define NEON_ENC_SINGLE_(X) \
13251 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13252 #define NEON_ENC_DOUBLE_(X) \
13253 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13254 #define NEON_ENC_FPV8_(X) \
13255 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13257 #define NEON_ENCODE(type, inst) \
13260 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13261 inst.is_neon = 1; \
13265 #define check_neon_suffixes \
13268 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13270 as_bad (_("invalid neon suffix for non neon instruction")); \
13276 /* Define shapes for instruction operands. The following mnemonic characters
13277 are used in this table:
13279 F - VFP S<n> register
13280 D - Neon D<n> register
13281 Q - Neon Q<n> register
13285 L - D<n> register list
13287 This table is used to generate various data:
13288 - enumerations of the form NS_DDR to be used as arguments to
13290 - a table classifying shapes into single, double, quad, mixed.
13291 - a table used to drive neon_select_shape. */
13293 #define NEON_SHAPE_DEF \
13294 X(3, (D, D, D), DOUBLE), \
13295 X(3, (Q, Q, Q), QUAD), \
13296 X(3, (D, D, I), DOUBLE), \
13297 X(3, (Q, Q, I), QUAD), \
13298 X(3, (D, D, S), DOUBLE), \
13299 X(3, (Q, Q, S), QUAD), \
13300 X(2, (D, D), DOUBLE), \
13301 X(2, (Q, Q), QUAD), \
13302 X(2, (D, S), DOUBLE), \
13303 X(2, (Q, S), QUAD), \
13304 X(2, (D, R), DOUBLE), \
13305 X(2, (Q, R), QUAD), \
13306 X(2, (D, I), DOUBLE), \
13307 X(2, (Q, I), QUAD), \
13308 X(3, (D, L, D), DOUBLE), \
13309 X(2, (D, Q), MIXED), \
13310 X(2, (Q, D), MIXED), \
13311 X(3, (D, Q, I), MIXED), \
13312 X(3, (Q, D, I), MIXED), \
13313 X(3, (Q, D, D), MIXED), \
13314 X(3, (D, Q, Q), MIXED), \
13315 X(3, (Q, Q, D), MIXED), \
13316 X(3, (Q, D, S), MIXED), \
13317 X(3, (D, Q, S), MIXED), \
13318 X(4, (D, D, D, I), DOUBLE), \
13319 X(4, (Q, Q, Q, I), QUAD), \
13320 X(2, (F, F), SINGLE), \
13321 X(3, (F, F, F), SINGLE), \
13322 X(2, (F, I), SINGLE), \
13323 X(2, (F, D), MIXED), \
13324 X(2, (D, F), MIXED), \
13325 X(3, (F, F, I), MIXED), \
13326 X(4, (R, R, F, F), SINGLE), \
13327 X(4, (F, F, R, R), SINGLE), \
13328 X(3, (D, R, R), DOUBLE), \
13329 X(3, (R, R, D), DOUBLE), \
13330 X(2, (S, R), SINGLE), \
13331 X(2, (R, S), SINGLE), \
13332 X(2, (F, R), SINGLE), \
13333 X(2, (R, F), SINGLE), \
13334 /* Half float shape supported so far. */\
13335 X (2, (H, D), MIXED), \
13336 X (2, (D, H), MIXED), \
13337 X (2, (H, F), MIXED), \
13338 X (2, (F, H), MIXED), \
13339 X (2, (H, H), HALF), \
13340 X (2, (H, R), HALF), \
13341 X (2, (R, H), HALF), \
13342 X (2, (H, I), HALF), \
13343 X (3, (H, H, H), HALF), \
13344 X (3, (H, F, I), MIXED), \
13345 X (3, (F, H, I), MIXED)
13347 #define S2(A,B) NS_##A##B
13348 #define S3(A,B,C) NS_##A##B##C
13349 #define S4(A,B,C,D) NS_##A##B##C##D
13351 #define X(N, L, C) S##N L
13364 enum neon_shape_class
13373 #define X(N, L, C) SC_##C
13375 static enum neon_shape_class neon_shape_class
[] =
13394 /* Register widths of above. */
13395 static unsigned neon_shape_el_size
[] =
13407 struct neon_shape_info
13410 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13413 #define S2(A,B) { SE_##A, SE_##B }
13414 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13415 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13417 #define X(N, L, C) { N, S##N L }
13419 static struct neon_shape_info neon_shape_tab
[] =
13429 /* Bit masks used in type checking given instructions.
13430 'N_EQK' means the type must be the same as (or based on in some way) the key
13431 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13432 set, various other bits can be set as well in order to modify the meaning of
13433 the type constraint. */
13435 enum neon_type_mask
13459 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13460 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13461 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13462 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13463 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13464 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13465 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13466 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13467 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13468 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13469 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13471 N_MAX_NONSPECIAL
= N_P64
13474 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13476 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13477 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13478 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13479 #define N_S_32 (N_S8 | N_S16 | N_S32)
13480 #define N_F_16_32 (N_F16 | N_F32)
13481 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13482 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13483 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13484 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13486 /* Pass this as the first type argument to neon_check_type to ignore types
13488 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13490 /* Select a "shape" for the current instruction (describing register types or
13491 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13492 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13493 function of operand parsing, so this function doesn't need to be called.
13494 Shapes should be listed in order of decreasing length. */
13496 static enum neon_shape
13497 neon_select_shape (enum neon_shape shape
, ...)
13500 enum neon_shape first_shape
= shape
;
13502 /* Fix missing optional operands. FIXME: we don't know at this point how
13503 many arguments we should have, so this makes the assumption that we have
13504 > 1. This is true of all current Neon opcodes, I think, but may not be
13505 true in the future. */
13506 if (!inst
.operands
[1].present
)
13507 inst
.operands
[1] = inst
.operands
[0];
13509 va_start (ap
, shape
);
13511 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13516 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13518 if (!inst
.operands
[j
].present
)
13524 switch (neon_shape_tab
[shape
].el
[j
])
13526 /* If a .f16, .16, .u16, .s16 type specifier is given over
13527 a VFP single precision register operand, it's essentially
13528 means only half of the register is used.
13530 If the type specifier is given after the mnemonics, the
13531 information is stored in inst.vectype. If the type specifier
13532 is given after register operand, the information is stored
13533 in inst.operands[].vectype.
13535 When there is only one type specifier, and all the register
13536 operands are the same type of hardware register, the type
13537 specifier applies to all register operands.
13539 If no type specifier is given, the shape is inferred from
13540 operand information.
13543 vadd.f16 s0, s1, s2: NS_HHH
13544 vabs.f16 s0, s1: NS_HH
13545 vmov.f16 s0, r1: NS_HR
13546 vmov.f16 r0, s1: NS_RH
13547 vcvt.f16 r0, s1: NS_RH
13548 vcvt.f16.s32 s2, s2, #29: NS_HFI
13549 vcvt.f16.s32 s2, s2: NS_HF
13552 if (!(inst
.operands
[j
].isreg
13553 && inst
.operands
[j
].isvec
13554 && inst
.operands
[j
].issingle
13555 && !inst
.operands
[j
].isquad
13556 && ((inst
.vectype
.elems
== 1
13557 && inst
.vectype
.el
[0].size
== 16)
13558 || (inst
.vectype
.elems
> 1
13559 && inst
.vectype
.el
[j
].size
== 16)
13560 || (inst
.vectype
.elems
== 0
13561 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13562 && inst
.operands
[j
].vectype
.size
== 16))))
13567 if (!(inst
.operands
[j
].isreg
13568 && inst
.operands
[j
].isvec
13569 && inst
.operands
[j
].issingle
13570 && !inst
.operands
[j
].isquad
13571 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13572 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13573 || (inst
.vectype
.elems
== 0
13574 && (inst
.operands
[j
].vectype
.size
== 32
13575 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13580 if (!(inst
.operands
[j
].isreg
13581 && inst
.operands
[j
].isvec
13582 && !inst
.operands
[j
].isquad
13583 && !inst
.operands
[j
].issingle
))
13588 if (!(inst
.operands
[j
].isreg
13589 && !inst
.operands
[j
].isvec
))
13594 if (!(inst
.operands
[j
].isreg
13595 && inst
.operands
[j
].isvec
13596 && inst
.operands
[j
].isquad
13597 && !inst
.operands
[j
].issingle
))
13602 if (!(!inst
.operands
[j
].isreg
13603 && !inst
.operands
[j
].isscalar
))
13608 if (!(!inst
.operands
[j
].isreg
13609 && inst
.operands
[j
].isscalar
))
13619 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13620 /* We've matched all the entries in the shape table, and we don't
13621 have any left over operands which have not been matched. */
13627 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13628 first_error (_("invalid instruction shape"));
13633 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13634 means the Q bit should be set). */
13637 neon_quad (enum neon_shape shape
)
13639 return neon_shape_class
[shape
] == SC_QUAD
;
13643 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13646 /* Allow modification to be made to types which are constrained to be
13647 based on the key element, based on bits set alongside N_EQK. */
13648 if ((typebits
& N_EQK
) != 0)
13650 if ((typebits
& N_HLF
) != 0)
13652 else if ((typebits
& N_DBL
) != 0)
13654 if ((typebits
& N_SGN
) != 0)
13655 *g_type
= NT_signed
;
13656 else if ((typebits
& N_UNS
) != 0)
13657 *g_type
= NT_unsigned
;
13658 else if ((typebits
& N_INT
) != 0)
13659 *g_type
= NT_integer
;
13660 else if ((typebits
& N_FLT
) != 0)
13661 *g_type
= NT_float
;
13662 else if ((typebits
& N_SIZ
) != 0)
13663 *g_type
= NT_untyped
;
13667 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13668 operand type, i.e. the single type specified in a Neon instruction when it
13669 is the only one given. */
13671 static struct neon_type_el
13672 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13674 struct neon_type_el dest
= *key
;
13676 gas_assert ((thisarg
& N_EQK
) != 0);
13678 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13683 /* Convert Neon type and size into compact bitmask representation. */
13685 static enum neon_type_mask
13686 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13693 case 8: return N_8
;
13694 case 16: return N_16
;
13695 case 32: return N_32
;
13696 case 64: return N_64
;
13704 case 8: return N_I8
;
13705 case 16: return N_I16
;
13706 case 32: return N_I32
;
13707 case 64: return N_I64
;
13715 case 16: return N_F16
;
13716 case 32: return N_F32
;
13717 case 64: return N_F64
;
13725 case 8: return N_P8
;
13726 case 16: return N_P16
;
13727 case 64: return N_P64
;
13735 case 8: return N_S8
;
13736 case 16: return N_S16
;
13737 case 32: return N_S32
;
13738 case 64: return N_S64
;
13746 case 8: return N_U8
;
13747 case 16: return N_U16
;
13748 case 32: return N_U32
;
13749 case 64: return N_U64
;
13760 /* Convert compact Neon bitmask type representation to a type and size. Only
13761 handles the case where a single bit is set in the mask. */
13764 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13765 enum neon_type_mask mask
)
13767 if ((mask
& N_EQK
) != 0)
13770 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13772 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13774 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13776 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13781 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13783 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13784 *type
= NT_unsigned
;
13785 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13786 *type
= NT_integer
;
13787 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13788 *type
= NT_untyped
;
13789 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13791 else if ((mask
& (N_F_ALL
)) != 0)
13799 /* Modify a bitmask of allowed types. This is only needed for type
13803 modify_types_allowed (unsigned allowed
, unsigned mods
)
13806 enum neon_el_type type
;
13812 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13814 if (el_type_of_type_chk (&type
, &size
,
13815 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13817 neon_modify_type_size (mods
, &type
, &size
);
13818 destmask
|= type_chk_of_el_type (type
, size
);
13825 /* Check type and return type classification.
13826 The manual states (paraphrase): If one datatype is given, it indicates the
13828 - the second operand, if there is one
13829 - the operand, if there is no second operand
13830 - the result, if there are no operands.
13831 This isn't quite good enough though, so we use a concept of a "key" datatype
13832 which is set on a per-instruction basis, which is the one which matters when
13833 only one data type is written.
13834 Note: this function has side-effects (e.g. filling in missing operands). All
13835 Neon instructions should call it before performing bit encoding. */
13837 static struct neon_type_el
13838 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13841 unsigned i
, pass
, key_el
= 0;
13842 unsigned types
[NEON_MAX_TYPE_ELS
];
13843 enum neon_el_type k_type
= NT_invtype
;
13844 unsigned k_size
= -1u;
13845 struct neon_type_el badtype
= {NT_invtype
, -1};
13846 unsigned key_allowed
= 0;
13848 /* Optional registers in Neon instructions are always (not) in operand 1.
13849 Fill in the missing operand here, if it was omitted. */
13850 if (els
> 1 && !inst
.operands
[1].present
)
13851 inst
.operands
[1] = inst
.operands
[0];
13853 /* Suck up all the varargs. */
13855 for (i
= 0; i
< els
; i
++)
13857 unsigned thisarg
= va_arg (ap
, unsigned);
13858 if (thisarg
== N_IGNORE_TYPE
)
13863 types
[i
] = thisarg
;
13864 if ((thisarg
& N_KEY
) != 0)
13869 if (inst
.vectype
.elems
> 0)
13870 for (i
= 0; i
< els
; i
++)
13871 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13873 first_error (_("types specified in both the mnemonic and operands"));
13877 /* Duplicate inst.vectype elements here as necessary.
13878 FIXME: No idea if this is exactly the same as the ARM assembler,
13879 particularly when an insn takes one register and one non-register
13881 if (inst
.vectype
.elems
== 1 && els
> 1)
13884 inst
.vectype
.elems
= els
;
13885 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13886 for (j
= 0; j
< els
; j
++)
13888 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13891 else if (inst
.vectype
.elems
== 0 && els
> 0)
13894 /* No types were given after the mnemonic, so look for types specified
13895 after each operand. We allow some flexibility here; as long as the
13896 "key" operand has a type, we can infer the others. */
13897 for (j
= 0; j
< els
; j
++)
13898 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13899 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13901 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13903 for (j
= 0; j
< els
; j
++)
13904 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13905 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13910 first_error (_("operand types can't be inferred"));
13914 else if (inst
.vectype
.elems
!= els
)
13916 first_error (_("type specifier has the wrong number of parts"));
13920 for (pass
= 0; pass
< 2; pass
++)
13922 for (i
= 0; i
< els
; i
++)
13924 unsigned thisarg
= types
[i
];
13925 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13926 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13927 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13928 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13930 /* Decay more-specific signed & unsigned types to sign-insensitive
13931 integer types if sign-specific variants are unavailable. */
13932 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13933 && (types_allowed
& N_SU_ALL
) == 0)
13934 g_type
= NT_integer
;
13936 /* If only untyped args are allowed, decay any more specific types to
13937 them. Some instructions only care about signs for some element
13938 sizes, so handle that properly. */
13939 if (((types_allowed
& N_UNT
) == 0)
13940 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13941 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13942 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13943 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13944 g_type
= NT_untyped
;
13948 if ((thisarg
& N_KEY
) != 0)
13952 key_allowed
= thisarg
& ~N_KEY
;
13954 /* Check architecture constraint on FP16 extension. */
13956 && k_type
== NT_float
13957 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13959 inst
.error
= _(BAD_FP16
);
13966 if ((thisarg
& N_VFP
) != 0)
13968 enum neon_shape_el regshape
;
13969 unsigned regwidth
, match
;
13971 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13974 first_error (_("invalid instruction shape"));
13977 regshape
= neon_shape_tab
[ns
].el
[i
];
13978 regwidth
= neon_shape_el_size
[regshape
];
13980 /* In VFP mode, operands must match register widths. If we
13981 have a key operand, use its width, else use the width of
13982 the current operand. */
13988 /* FP16 will use a single precision register. */
13989 if (regwidth
== 32 && match
== 16)
13991 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13995 inst
.error
= _(BAD_FP16
);
14000 if (regwidth
!= match
)
14002 first_error (_("operand size must match register width"));
14007 if ((thisarg
& N_EQK
) == 0)
14009 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14011 if ((given_type
& types_allowed
) == 0)
14013 first_error (_("bad type in Neon instruction"));
14019 enum neon_el_type mod_k_type
= k_type
;
14020 unsigned mod_k_size
= k_size
;
14021 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14022 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14024 first_error (_("inconsistent types in Neon instruction"));
14032 return inst
.vectype
.el
[key_el
];
14035 /* Neon-style VFP instruction forwarding. */
14037 /* Thumb VFP instructions have 0xE in the condition field. */
14040 do_vfp_cond_or_thumb (void)
14045 inst
.instruction
|= 0xe0000000;
14047 inst
.instruction
|= inst
.cond
<< 28;
14050 /* Look up and encode a simple mnemonic, for use as a helper function for the
14051 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14052 etc. It is assumed that operand parsing has already been done, and that the
14053 operands are in the form expected by the given opcode (this isn't necessarily
14054 the same as the form in which they were parsed, hence some massaging must
14055 take place before this function is called).
14056 Checks current arch version against that in the looked-up opcode. */
14059 do_vfp_nsyn_opcode (const char *opname
)
14061 const struct asm_opcode
*opcode
;
14063 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14068 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14069 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14076 inst
.instruction
= opcode
->tvalue
;
14077 opcode
->tencode ();
14081 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14082 opcode
->aencode ();
14087 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14089 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14091 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14094 do_vfp_nsyn_opcode ("fadds");
14096 do_vfp_nsyn_opcode ("fsubs");
14098 /* ARMv8.2 fp16 instruction. */
14100 do_scalar_fp16_v82_encode ();
14105 do_vfp_nsyn_opcode ("faddd");
14107 do_vfp_nsyn_opcode ("fsubd");
14111 /* Check operand types to see if this is a VFP instruction, and if so call
14115 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14117 enum neon_shape rs
;
14118 struct neon_type_el et
;
14123 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14124 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14128 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14129 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14130 N_F_ALL
| N_KEY
| N_VFP
);
14137 if (et
.type
!= NT_invtype
)
14148 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14150 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14152 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14155 do_vfp_nsyn_opcode ("fmacs");
14157 do_vfp_nsyn_opcode ("fnmacs");
14159 /* ARMv8.2 fp16 instruction. */
14161 do_scalar_fp16_v82_encode ();
14166 do_vfp_nsyn_opcode ("fmacd");
14168 do_vfp_nsyn_opcode ("fnmacd");
14173 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14175 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14177 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14180 do_vfp_nsyn_opcode ("ffmas");
14182 do_vfp_nsyn_opcode ("ffnmas");
14184 /* ARMv8.2 fp16 instruction. */
14186 do_scalar_fp16_v82_encode ();
14191 do_vfp_nsyn_opcode ("ffmad");
14193 do_vfp_nsyn_opcode ("ffnmad");
14198 do_vfp_nsyn_mul (enum neon_shape rs
)
14200 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14202 do_vfp_nsyn_opcode ("fmuls");
14204 /* ARMv8.2 fp16 instruction. */
14206 do_scalar_fp16_v82_encode ();
14209 do_vfp_nsyn_opcode ("fmuld");
14213 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14215 int is_neg
= (inst
.instruction
& 0x80) != 0;
14216 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14218 if (rs
== NS_FF
|| rs
== NS_HH
)
14221 do_vfp_nsyn_opcode ("fnegs");
14223 do_vfp_nsyn_opcode ("fabss");
14225 /* ARMv8.2 fp16 instruction. */
14227 do_scalar_fp16_v82_encode ();
14232 do_vfp_nsyn_opcode ("fnegd");
14234 do_vfp_nsyn_opcode ("fabsd");
14238 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14239 insns belong to Neon, and are handled elsewhere. */
14242 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14244 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14248 do_vfp_nsyn_opcode ("fldmdbs");
14250 do_vfp_nsyn_opcode ("fldmias");
14255 do_vfp_nsyn_opcode ("fstmdbs");
14257 do_vfp_nsyn_opcode ("fstmias");
14262 do_vfp_nsyn_sqrt (void)
14264 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14265 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14267 if (rs
== NS_FF
|| rs
== NS_HH
)
14269 do_vfp_nsyn_opcode ("fsqrts");
14271 /* ARMv8.2 fp16 instruction. */
14273 do_scalar_fp16_v82_encode ();
14276 do_vfp_nsyn_opcode ("fsqrtd");
14280 do_vfp_nsyn_div (void)
14282 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14283 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14284 N_F_ALL
| N_KEY
| N_VFP
);
14286 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14288 do_vfp_nsyn_opcode ("fdivs");
14290 /* ARMv8.2 fp16 instruction. */
14292 do_scalar_fp16_v82_encode ();
14295 do_vfp_nsyn_opcode ("fdivd");
14299 do_vfp_nsyn_nmul (void)
14301 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14302 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14303 N_F_ALL
| N_KEY
| N_VFP
);
14305 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14307 NEON_ENCODE (SINGLE
, inst
);
14308 do_vfp_sp_dyadic ();
14310 /* ARMv8.2 fp16 instruction. */
14312 do_scalar_fp16_v82_encode ();
14316 NEON_ENCODE (DOUBLE
, inst
);
14317 do_vfp_dp_rd_rn_rm ();
14319 do_vfp_cond_or_thumb ();
14324 do_vfp_nsyn_cmp (void)
14326 enum neon_shape rs
;
14327 if (inst
.operands
[1].isreg
)
14329 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14330 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14332 if (rs
== NS_FF
|| rs
== NS_HH
)
14334 NEON_ENCODE (SINGLE
, inst
);
14335 do_vfp_sp_monadic ();
14339 NEON_ENCODE (DOUBLE
, inst
);
14340 do_vfp_dp_rd_rm ();
14345 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14346 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14348 switch (inst
.instruction
& 0x0fffffff)
14351 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14354 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14360 if (rs
== NS_FI
|| rs
== NS_HI
)
14362 NEON_ENCODE (SINGLE
, inst
);
14363 do_vfp_sp_compare_z ();
14367 NEON_ENCODE (DOUBLE
, inst
);
14371 do_vfp_cond_or_thumb ();
14373 /* ARMv8.2 fp16 instruction. */
14374 if (rs
== NS_HI
|| rs
== NS_HH
)
14375 do_scalar_fp16_v82_encode ();
14379 nsyn_insert_sp (void)
14381 inst
.operands
[1] = inst
.operands
[0];
14382 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14383 inst
.operands
[0].reg
= REG_SP
;
14384 inst
.operands
[0].isreg
= 1;
14385 inst
.operands
[0].writeback
= 1;
14386 inst
.operands
[0].present
= 1;
14390 do_vfp_nsyn_push (void)
14393 if (inst
.operands
[1].issingle
)
14394 do_vfp_nsyn_opcode ("fstmdbs");
14396 do_vfp_nsyn_opcode ("fstmdbd");
14400 do_vfp_nsyn_pop (void)
14403 if (inst
.operands
[1].issingle
)
14404 do_vfp_nsyn_opcode ("fldmias");
14406 do_vfp_nsyn_opcode ("fldmiad");
14409 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14410 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14413 neon_dp_fixup (struct arm_it
* insn
)
14415 unsigned int i
= insn
->instruction
;
14420 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14431 insn
->instruction
= i
;
14434 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14438 neon_logbits (unsigned x
)
14440 return ffs (x
) - 4;
14443 #define LOW4(R) ((R) & 0xf)
14444 #define HI1(R) (((R) >> 4) & 1)
14446 /* Encode insns with bit pattern:
14448 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14449 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14451 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14452 different meaning for some instruction. */
14455 neon_three_same (int isquad
, int ubit
, int size
)
14457 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14458 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14459 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14460 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14461 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14462 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14463 inst
.instruction
|= (isquad
!= 0) << 6;
14464 inst
.instruction
|= (ubit
!= 0) << 24;
14466 inst
.instruction
|= neon_logbits (size
) << 20;
14468 neon_dp_fixup (&inst
);
14471 /* Encode instructions of the form:
14473 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14474 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14476 Don't write size if SIZE == -1. */
14479 neon_two_same (int qbit
, int ubit
, int size
)
14481 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14482 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14483 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14484 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14485 inst
.instruction
|= (qbit
!= 0) << 6;
14486 inst
.instruction
|= (ubit
!= 0) << 24;
14489 inst
.instruction
|= neon_logbits (size
) << 18;
14491 neon_dp_fixup (&inst
);
14494 /* Neon instruction encoders, in approximate order of appearance. */
14497 do_neon_dyadic_i_su (void)
14499 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14500 struct neon_type_el et
= neon_check_type (3, rs
,
14501 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14502 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14506 do_neon_dyadic_i64_su (void)
14508 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14509 struct neon_type_el et
= neon_check_type (3, rs
,
14510 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14511 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14515 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14518 unsigned size
= et
.size
>> 3;
14519 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14520 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14521 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14522 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14523 inst
.instruction
|= (isquad
!= 0) << 6;
14524 inst
.instruction
|= immbits
<< 16;
14525 inst
.instruction
|= (size
>> 3) << 7;
14526 inst
.instruction
|= (size
& 0x7) << 19;
14528 inst
.instruction
|= (uval
!= 0) << 24;
14530 neon_dp_fixup (&inst
);
14534 do_neon_shl_imm (void)
14536 if (!inst
.operands
[2].isreg
)
14538 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14539 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14540 int imm
= inst
.operands
[2].imm
;
14542 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14543 _("immediate out of range for shift"));
14544 NEON_ENCODE (IMMED
, inst
);
14545 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14549 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14550 struct neon_type_el et
= neon_check_type (3, rs
,
14551 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14554 /* VSHL/VQSHL 3-register variants have syntax such as:
14556 whereas other 3-register operations encoded by neon_three_same have
14559 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14561 tmp
= inst
.operands
[2].reg
;
14562 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14563 inst
.operands
[1].reg
= tmp
;
14564 NEON_ENCODE (INTEGER
, inst
);
14565 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14570 do_neon_qshl_imm (void)
14572 if (!inst
.operands
[2].isreg
)
14574 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14575 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14576 int imm
= inst
.operands
[2].imm
;
14578 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14579 _("immediate out of range for shift"));
14580 NEON_ENCODE (IMMED
, inst
);
14581 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14585 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14586 struct neon_type_el et
= neon_check_type (3, rs
,
14587 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14590 /* See note in do_neon_shl_imm. */
14591 tmp
= inst
.operands
[2].reg
;
14592 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14593 inst
.operands
[1].reg
= tmp
;
14594 NEON_ENCODE (INTEGER
, inst
);
14595 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14600 do_neon_rshl (void)
14602 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14603 struct neon_type_el et
= neon_check_type (3, rs
,
14604 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14607 tmp
= inst
.operands
[2].reg
;
14608 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14609 inst
.operands
[1].reg
= tmp
;
14610 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14614 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14616 /* Handle .I8 pseudo-instructions. */
14619 /* Unfortunately, this will make everything apart from zero out-of-range.
14620 FIXME is this the intended semantics? There doesn't seem much point in
14621 accepting .I8 if so. */
14622 immediate
|= immediate
<< 8;
14628 if (immediate
== (immediate
& 0x000000ff))
14630 *immbits
= immediate
;
14633 else if (immediate
== (immediate
& 0x0000ff00))
14635 *immbits
= immediate
>> 8;
14638 else if (immediate
== (immediate
& 0x00ff0000))
14640 *immbits
= immediate
>> 16;
14643 else if (immediate
== (immediate
& 0xff000000))
14645 *immbits
= immediate
>> 24;
14648 if ((immediate
& 0xffff) != (immediate
>> 16))
14649 goto bad_immediate
;
14650 immediate
&= 0xffff;
14653 if (immediate
== (immediate
& 0x000000ff))
14655 *immbits
= immediate
;
14658 else if (immediate
== (immediate
& 0x0000ff00))
14660 *immbits
= immediate
>> 8;
14665 first_error (_("immediate value out of range"));
14670 do_neon_logic (void)
14672 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14674 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14675 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14676 /* U bit and size field were set as part of the bitmask. */
14677 NEON_ENCODE (INTEGER
, inst
);
14678 neon_three_same (neon_quad (rs
), 0, -1);
14682 const int three_ops_form
= (inst
.operands
[2].present
14683 && !inst
.operands
[2].isreg
);
14684 const int immoperand
= (three_ops_form
? 2 : 1);
14685 enum neon_shape rs
= (three_ops_form
14686 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14687 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14688 struct neon_type_el et
= neon_check_type (2, rs
,
14689 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14690 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14694 if (et
.type
== NT_invtype
)
14697 if (three_ops_form
)
14698 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14699 _("first and second operands shall be the same register"));
14701 NEON_ENCODE (IMMED
, inst
);
14703 immbits
= inst
.operands
[immoperand
].imm
;
14706 /* .i64 is a pseudo-op, so the immediate must be a repeating
14708 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14709 inst
.operands
[immoperand
].reg
: 0))
14711 /* Set immbits to an invalid constant. */
14712 immbits
= 0xdeadbeef;
14719 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14723 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14727 /* Pseudo-instruction for VBIC. */
14728 neon_invert_size (&immbits
, 0, et
.size
);
14729 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14733 /* Pseudo-instruction for VORR. */
14734 neon_invert_size (&immbits
, 0, et
.size
);
14735 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14745 inst
.instruction
|= neon_quad (rs
) << 6;
14746 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14747 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14748 inst
.instruction
|= cmode
<< 8;
14749 neon_write_immbits (immbits
);
14751 neon_dp_fixup (&inst
);
14756 do_neon_bitfield (void)
14758 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14759 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14760 neon_three_same (neon_quad (rs
), 0, -1);
14764 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14767 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14768 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14770 if (et
.type
== NT_float
)
14772 NEON_ENCODE (FLOAT
, inst
);
14773 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14777 NEON_ENCODE (INTEGER
, inst
);
14778 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14783 do_neon_dyadic_if_su (void)
14785 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14789 do_neon_dyadic_if_su_d (void)
14791 /* This version only allow D registers, but that constraint is enforced during
14792 operand parsing so we don't need to do anything extra here. */
14793 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14797 do_neon_dyadic_if_i_d (void)
14799 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14800 affected if we specify unsigned args. */
14801 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14804 enum vfp_or_neon_is_neon_bits
14807 NEON_CHECK_ARCH
= 2,
14808 NEON_CHECK_ARCH8
= 4
14811 /* Call this function if an instruction which may have belonged to the VFP or
14812 Neon instruction sets, but turned out to be a Neon instruction (due to the
14813 operand types involved, etc.). We have to check and/or fix-up a couple of
14816 - Make sure the user hasn't attempted to make a Neon instruction
14818 - Alter the value in the condition code field if necessary.
14819 - Make sure that the arch supports Neon instructions.
14821 Which of these operations take place depends on bits from enum
14822 vfp_or_neon_is_neon_bits.
14824 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14825 current instruction's condition is COND_ALWAYS, the condition field is
14826 changed to inst.uncond_value. This is necessary because instructions shared
14827 between VFP and Neon may be conditional for the VFP variants only, and the
14828 unconditional Neon version must have, e.g., 0xF in the condition field. */
14831 vfp_or_neon_is_neon (unsigned check
)
14833 /* Conditions are always legal in Thumb mode (IT blocks). */
14834 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14836 if (inst
.cond
!= COND_ALWAYS
)
14838 first_error (_(BAD_COND
));
14841 if (inst
.uncond_value
!= -1)
14842 inst
.instruction
|= inst
.uncond_value
<< 28;
14845 if ((check
& NEON_CHECK_ARCH
)
14846 && !mark_feature_used (&fpu_neon_ext_v1
))
14848 first_error (_(BAD_FPU
));
14852 if ((check
& NEON_CHECK_ARCH8
)
14853 && !mark_feature_used (&fpu_neon_ext_armv8
))
14855 first_error (_(BAD_FPU
));
14863 do_neon_addsub_if_i (void)
14865 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14868 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14871 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14872 affected if we specify unsigned args. */
14873 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14876 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14878 V<op> A,B (A is operand 0, B is operand 2)
14883 so handle that case specially. */
14886 neon_exchange_operands (void)
14888 if (inst
.operands
[1].present
)
14890 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14892 /* Swap operands[1] and operands[2]. */
14893 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14894 inst
.operands
[1] = inst
.operands
[2];
14895 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14900 inst
.operands
[1] = inst
.operands
[2];
14901 inst
.operands
[2] = inst
.operands
[0];
14906 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14908 if (inst
.operands
[2].isreg
)
14911 neon_exchange_operands ();
14912 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14916 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14917 struct neon_type_el et
= neon_check_type (2, rs
,
14918 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14920 NEON_ENCODE (IMMED
, inst
);
14921 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14922 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14923 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14924 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14925 inst
.instruction
|= neon_quad (rs
) << 6;
14926 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14927 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14929 neon_dp_fixup (&inst
);
14936 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14940 do_neon_cmp_inv (void)
14942 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14948 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14951 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14952 scalars, which are encoded in 5 bits, M : Rm.
14953 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14954 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14958 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14960 unsigned regno
= NEON_SCALAR_REG (scalar
);
14961 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14966 if (regno
> 7 || elno
> 3)
14968 return regno
| (elno
<< 3);
14971 if (regno
> 15 || elno
> 1)
14973 return regno
| (elno
<< 4);
14977 first_error (_("scalar out of range for multiply instruction"));
14983 /* Encode multiply / multiply-accumulate scalar instructions. */
14986 neon_mul_mac (struct neon_type_el et
, int ubit
)
14990 /* Give a more helpful error message if we have an invalid type. */
14991 if (et
.type
== NT_invtype
)
14994 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14995 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14996 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14997 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14998 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14999 inst
.instruction
|= LOW4 (scalar
);
15000 inst
.instruction
|= HI1 (scalar
) << 5;
15001 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15002 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15003 inst
.instruction
|= (ubit
!= 0) << 24;
15005 neon_dp_fixup (&inst
);
15009 do_neon_mac_maybe_scalar (void)
15011 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15014 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15017 if (inst
.operands
[2].isscalar
)
15019 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15020 struct neon_type_el et
= neon_check_type (3, rs
,
15021 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15022 NEON_ENCODE (SCALAR
, inst
);
15023 neon_mul_mac (et
, neon_quad (rs
));
15027 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15028 affected if we specify unsigned args. */
15029 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15034 do_neon_fmac (void)
15036 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15039 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15042 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15048 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15049 struct neon_type_el et
= neon_check_type (3, rs
,
15050 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15051 neon_three_same (neon_quad (rs
), 0, et
.size
);
15054 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15055 same types as the MAC equivalents. The polynomial type for this instruction
15056 is encoded the same as the integer type. */
15061 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15064 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15067 if (inst
.operands
[2].isscalar
)
15068 do_neon_mac_maybe_scalar ();
15070 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15074 do_neon_qdmulh (void)
15076 if (inst
.operands
[2].isscalar
)
15078 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15079 struct neon_type_el et
= neon_check_type (3, rs
,
15080 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15081 NEON_ENCODE (SCALAR
, inst
);
15082 neon_mul_mac (et
, neon_quad (rs
));
15086 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15087 struct neon_type_el et
= neon_check_type (3, rs
,
15088 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15089 NEON_ENCODE (INTEGER
, inst
);
15090 /* The U bit (rounding) comes from bit mask. */
15091 neon_three_same (neon_quad (rs
), 0, et
.size
);
15096 do_neon_qrdmlah (void)
15098 /* Check we're on the correct architecture. */
15099 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15101 _("instruction form not available on this architecture.");
15102 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15104 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15105 record_feature_use (&fpu_neon_ext_v8_1
);
15108 if (inst
.operands
[2].isscalar
)
15110 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15111 struct neon_type_el et
= neon_check_type (3, rs
,
15112 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15113 NEON_ENCODE (SCALAR
, inst
);
15114 neon_mul_mac (et
, neon_quad (rs
));
15118 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15119 struct neon_type_el et
= neon_check_type (3, rs
,
15120 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15121 NEON_ENCODE (INTEGER
, inst
);
15122 /* The U bit (rounding) comes from bit mask. */
15123 neon_three_same (neon_quad (rs
), 0, et
.size
);
15128 do_neon_fcmp_absolute (void)
15130 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15131 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15132 N_F_16_32
| N_KEY
);
15133 /* Size field comes from bit mask. */
15134 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15138 do_neon_fcmp_absolute_inv (void)
15140 neon_exchange_operands ();
15141 do_neon_fcmp_absolute ();
15145 do_neon_step (void)
15147 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15148 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15149 N_F_16_32
| N_KEY
);
15150 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15154 do_neon_abs_neg (void)
15156 enum neon_shape rs
;
15157 struct neon_type_el et
;
15159 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15162 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15165 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15166 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15168 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15169 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15170 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15171 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15172 inst
.instruction
|= neon_quad (rs
) << 6;
15173 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15174 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15176 neon_dp_fixup (&inst
);
15182 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15183 struct neon_type_el et
= neon_check_type (2, rs
,
15184 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15185 int imm
= inst
.operands
[2].imm
;
15186 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15187 _("immediate out of range for insert"));
15188 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15194 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15195 struct neon_type_el et
= neon_check_type (2, rs
,
15196 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15197 int imm
= inst
.operands
[2].imm
;
15198 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15199 _("immediate out of range for insert"));
15200 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15204 do_neon_qshlu_imm (void)
15206 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15207 struct neon_type_el et
= neon_check_type (2, rs
,
15208 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15209 int imm
= inst
.operands
[2].imm
;
15210 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15211 _("immediate out of range for shift"));
15212 /* Only encodes the 'U present' variant of the instruction.
15213 In this case, signed types have OP (bit 8) set to 0.
15214 Unsigned types have OP set to 1. */
15215 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15216 /* The rest of the bits are the same as other immediate shifts. */
15217 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15221 do_neon_qmovn (void)
15223 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15224 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15225 /* Saturating move where operands can be signed or unsigned, and the
15226 destination has the same signedness. */
15227 NEON_ENCODE (INTEGER
, inst
);
15228 if (et
.type
== NT_unsigned
)
15229 inst
.instruction
|= 0xc0;
15231 inst
.instruction
|= 0x80;
15232 neon_two_same (0, 1, et
.size
/ 2);
15236 do_neon_qmovun (void)
15238 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15239 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15240 /* Saturating move with unsigned results. Operands must be signed. */
15241 NEON_ENCODE (INTEGER
, inst
);
15242 neon_two_same (0, 1, et
.size
/ 2);
15246 do_neon_rshift_sat_narrow (void)
15248 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15249 or unsigned. If operands are unsigned, results must also be unsigned. */
15250 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15251 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15252 int imm
= inst
.operands
[2].imm
;
15253 /* This gets the bounds check, size encoding and immediate bits calculation
15257 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15258 VQMOVN.I<size> <Dd>, <Qm>. */
15261 inst
.operands
[2].present
= 0;
15262 inst
.instruction
= N_MNEM_vqmovn
;
15267 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15268 _("immediate out of range"));
15269 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15273 do_neon_rshift_sat_narrow_u (void)
15275 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15276 or unsigned. If operands are unsigned, results must also be unsigned. */
15277 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15278 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15279 int imm
= inst
.operands
[2].imm
;
15280 /* This gets the bounds check, size encoding and immediate bits calculation
15284 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15285 VQMOVUN.I<size> <Dd>, <Qm>. */
15288 inst
.operands
[2].present
= 0;
15289 inst
.instruction
= N_MNEM_vqmovun
;
15294 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15295 _("immediate out of range"));
15296 /* FIXME: The manual is kind of unclear about what value U should have in
15297 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15299 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15303 do_neon_movn (void)
15305 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15306 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15307 NEON_ENCODE (INTEGER
, inst
);
15308 neon_two_same (0, 1, et
.size
/ 2);
15312 do_neon_rshift_narrow (void)
15314 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15315 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15316 int imm
= inst
.operands
[2].imm
;
15317 /* This gets the bounds check, size encoding and immediate bits calculation
15321 /* If immediate is zero then we are a pseudo-instruction for
15322 VMOVN.I<size> <Dd>, <Qm> */
15325 inst
.operands
[2].present
= 0;
15326 inst
.instruction
= N_MNEM_vmovn
;
15331 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15332 _("immediate out of range for narrowing operation"));
15333 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15337 do_neon_shll (void)
15339 /* FIXME: Type checking when lengthening. */
15340 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15341 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15342 unsigned imm
= inst
.operands
[2].imm
;
15344 if (imm
== et
.size
)
15346 /* Maximum shift variant. */
15347 NEON_ENCODE (INTEGER
, inst
);
15348 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15349 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15350 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15351 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15352 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15354 neon_dp_fixup (&inst
);
15358 /* A more-specific type check for non-max versions. */
15359 et
= neon_check_type (2, NS_QDI
,
15360 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15361 NEON_ENCODE (IMMED
, inst
);
15362 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15366 /* Check the various types for the VCVT instruction, and return which version
15367 the current instruction is. */
15369 #define CVT_FLAVOUR_VAR \
15370 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15371 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15372 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15373 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15374 /* Half-precision conversions. */ \
15375 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15376 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15377 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15378 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15379 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15380 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15381 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15382 Compared with single/double precision variants, only the co-processor \
15383 field is different, so the encoding flow is reused here. */ \
15384 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15385 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15386 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15387 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15388 /* VFP instructions. */ \
15389 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15390 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15391 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15392 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15393 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15394 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15395 /* VFP instructions with bitshift. */ \
15396 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15397 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15398 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15399 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15400 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15401 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15402 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15403 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15405 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15406 neon_cvt_flavour_##C,
15408 /* The different types of conversions we can do. */
15409 enum neon_cvt_flavour
15412 neon_cvt_flavour_invalid
,
15413 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15418 static enum neon_cvt_flavour
15419 get_neon_cvt_flavour (enum neon_shape rs
)
15421 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15422 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15423 if (et.type != NT_invtype) \
15425 inst.error = NULL; \
15426 return (neon_cvt_flavour_##C); \
15429 struct neon_type_el et
;
15430 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15431 || rs
== NS_FF
) ? N_VFP
: 0;
15432 /* The instruction versions which take an immediate take one register
15433 argument, which is extended to the width of the full register. Thus the
15434 "source" and "destination" registers must have the same width. Hack that
15435 here by making the size equal to the key (wider, in this case) operand. */
15436 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15440 return neon_cvt_flavour_invalid
;
15455 /* Neon-syntax VFP conversions. */
15458 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15460 const char *opname
= 0;
15462 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15463 || rs
== NS_FHI
|| rs
== NS_HFI
)
15465 /* Conversions with immediate bitshift. */
15466 const char *enc
[] =
15468 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15474 if (flavour
< (int) ARRAY_SIZE (enc
))
15476 opname
= enc
[flavour
];
15477 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15478 _("operands 0 and 1 must be the same register"));
15479 inst
.operands
[1] = inst
.operands
[2];
15480 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15485 /* Conversions without bitshift. */
15486 const char *enc
[] =
15488 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15494 if (flavour
< (int) ARRAY_SIZE (enc
))
15495 opname
= enc
[flavour
];
15499 do_vfp_nsyn_opcode (opname
);
15501 /* ARMv8.2 fp16 VCVT instruction. */
15502 if (flavour
== neon_cvt_flavour_s32_f16
15503 || flavour
== neon_cvt_flavour_u32_f16
15504 || flavour
== neon_cvt_flavour_f16_u32
15505 || flavour
== neon_cvt_flavour_f16_s32
)
15506 do_scalar_fp16_v82_encode ();
15510 do_vfp_nsyn_cvtz (void)
15512 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15513 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15514 const char *enc
[] =
15516 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15522 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15523 do_vfp_nsyn_opcode (enc
[flavour
]);
15527 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15528 enum neon_cvt_mode mode
)
15533 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15534 D register operands. */
15535 if (flavour
== neon_cvt_flavour_s32_f64
15536 || flavour
== neon_cvt_flavour_u32_f64
)
15537 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15540 if (flavour
== neon_cvt_flavour_s32_f16
15541 || flavour
== neon_cvt_flavour_u32_f16
)
15542 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15545 set_it_insn_type (OUTSIDE_IT_INSN
);
15549 case neon_cvt_flavour_s32_f64
:
15553 case neon_cvt_flavour_s32_f32
:
15557 case neon_cvt_flavour_s32_f16
:
15561 case neon_cvt_flavour_u32_f64
:
15565 case neon_cvt_flavour_u32_f32
:
15569 case neon_cvt_flavour_u32_f16
:
15574 first_error (_("invalid instruction shape"));
15580 case neon_cvt_mode_a
: rm
= 0; break;
15581 case neon_cvt_mode_n
: rm
= 1; break;
15582 case neon_cvt_mode_p
: rm
= 2; break;
15583 case neon_cvt_mode_m
: rm
= 3; break;
15584 default: first_error (_("invalid rounding mode")); return;
15587 NEON_ENCODE (FPV8
, inst
);
15588 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15589 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15590 inst
.instruction
|= sz
<< 8;
15592 /* ARMv8.2 fp16 VCVT instruction. */
15593 if (flavour
== neon_cvt_flavour_s32_f16
15594 ||flavour
== neon_cvt_flavour_u32_f16
)
15595 do_scalar_fp16_v82_encode ();
15596 inst
.instruction
|= op
<< 7;
15597 inst
.instruction
|= rm
<< 16;
15598 inst
.instruction
|= 0xf0000000;
15599 inst
.is_neon
= TRUE
;
15603 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15605 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15606 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15607 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15609 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15611 if (flavour
== neon_cvt_flavour_invalid
)
15614 /* PR11109: Handle round-to-zero for VCVT conversions. */
15615 if (mode
== neon_cvt_mode_z
15616 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15617 && (flavour
== neon_cvt_flavour_s16_f16
15618 || flavour
== neon_cvt_flavour_u16_f16
15619 || flavour
== neon_cvt_flavour_s32_f32
15620 || flavour
== neon_cvt_flavour_u32_f32
15621 || flavour
== neon_cvt_flavour_s32_f64
15622 || flavour
== neon_cvt_flavour_u32_f64
)
15623 && (rs
== NS_FD
|| rs
== NS_FF
))
15625 do_vfp_nsyn_cvtz ();
15629 /* ARMv8.2 fp16 VCVT conversions. */
15630 if (mode
== neon_cvt_mode_z
15631 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15632 && (flavour
== neon_cvt_flavour_s32_f16
15633 || flavour
== neon_cvt_flavour_u32_f16
)
15636 do_vfp_nsyn_cvtz ();
15637 do_scalar_fp16_v82_encode ();
15641 /* VFP rather than Neon conversions. */
15642 if (flavour
>= neon_cvt_flavour_first_fp
)
15644 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15645 do_vfp_nsyn_cvt (rs
, flavour
);
15647 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15658 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15659 0x0000100, 0x1000100, 0x0, 0x1000000};
15661 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15664 /* Fixed-point conversion with #0 immediate is encoded as an
15665 integer conversion. */
15666 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15668 NEON_ENCODE (IMMED
, inst
);
15669 if (flavour
!= neon_cvt_flavour_invalid
)
15670 inst
.instruction
|= enctab
[flavour
];
15671 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15672 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15673 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15674 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15675 inst
.instruction
|= neon_quad (rs
) << 6;
15676 inst
.instruction
|= 1 << 21;
15677 if (flavour
< neon_cvt_flavour_s16_f16
)
15679 inst
.instruction
|= 1 << 21;
15680 immbits
= 32 - inst
.operands
[2].imm
;
15681 inst
.instruction
|= immbits
<< 16;
15685 inst
.instruction
|= 3 << 20;
15686 immbits
= 16 - inst
.operands
[2].imm
;
15687 inst
.instruction
|= immbits
<< 16;
15688 inst
.instruction
&= ~(1 << 9);
15691 neon_dp_fixup (&inst
);
15697 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15699 NEON_ENCODE (FLOAT
, inst
);
15700 set_it_insn_type (OUTSIDE_IT_INSN
);
15702 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15705 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15706 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15707 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15708 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15709 inst
.instruction
|= neon_quad (rs
) << 6;
15710 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15711 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15712 inst
.instruction
|= mode
<< 8;
15713 if (flavour
== neon_cvt_flavour_u16_f16
15714 || flavour
== neon_cvt_flavour_s16_f16
)
15715 /* Mask off the original size bits and reencode them. */
15716 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15719 inst
.instruction
|= 0xfc000000;
15721 inst
.instruction
|= 0xf0000000;
15727 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15728 0x100, 0x180, 0x0, 0x080};
15730 NEON_ENCODE (INTEGER
, inst
);
15732 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15735 if (flavour
!= neon_cvt_flavour_invalid
)
15736 inst
.instruction
|= enctab
[flavour
];
15738 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15739 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15740 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15741 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15742 inst
.instruction
|= neon_quad (rs
) << 6;
15743 if (flavour
>= neon_cvt_flavour_s16_f16
15744 && flavour
<= neon_cvt_flavour_f16_u16
)
15745 /* Half precision. */
15746 inst
.instruction
|= 1 << 18;
15748 inst
.instruction
|= 2 << 18;
15750 neon_dp_fixup (&inst
);
15755 /* Half-precision conversions for Advanced SIMD -- neon. */
15760 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15762 as_bad (_("operand size must match register width"));
15767 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15769 as_bad (_("operand size must match register width"));
15774 inst
.instruction
= 0x3b60600;
15776 inst
.instruction
= 0x3b60700;
15778 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15779 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15780 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15781 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15782 neon_dp_fixup (&inst
);
15786 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15787 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15788 do_vfp_nsyn_cvt (rs
, flavour
);
15790 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15795 do_neon_cvtr (void)
15797 do_neon_cvt_1 (neon_cvt_mode_x
);
15803 do_neon_cvt_1 (neon_cvt_mode_z
);
15807 do_neon_cvta (void)
15809 do_neon_cvt_1 (neon_cvt_mode_a
);
15813 do_neon_cvtn (void)
15815 do_neon_cvt_1 (neon_cvt_mode_n
);
15819 do_neon_cvtp (void)
15821 do_neon_cvt_1 (neon_cvt_mode_p
);
15825 do_neon_cvtm (void)
15827 do_neon_cvt_1 (neon_cvt_mode_m
);
15831 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15834 mark_feature_used (&fpu_vfp_ext_armv8
);
15836 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15837 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15838 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15839 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15840 inst
.instruction
|= to
? 0x10000 : 0;
15841 inst
.instruction
|= t
? 0x80 : 0;
15842 inst
.instruction
|= is_double
? 0x100 : 0;
15843 do_vfp_cond_or_thumb ();
15847 do_neon_cvttb_1 (bfd_boolean t
)
15849 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15850 NS_DF
, NS_DH
, NS_NULL
);
15854 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15857 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15859 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15862 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15864 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15866 /* The VCVTB and VCVTT instructions with D-register operands
15867 don't work for SP only targets. */
15868 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15872 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15874 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15876 /* The VCVTB and VCVTT instructions with D-register operands
15877 don't work for SP only targets. */
15878 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15882 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15889 do_neon_cvtb (void)
15891 do_neon_cvttb_1 (FALSE
);
15896 do_neon_cvtt (void)
15898 do_neon_cvttb_1 (TRUE
);
15902 neon_move_immediate (void)
15904 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15905 struct neon_type_el et
= neon_check_type (2, rs
,
15906 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15907 unsigned immlo
, immhi
= 0, immbits
;
15908 int op
, cmode
, float_p
;
15910 constraint (et
.type
== NT_invtype
,
15911 _("operand size must be specified for immediate VMOV"));
15913 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15914 op
= (inst
.instruction
& (1 << 5)) != 0;
15916 immlo
= inst
.operands
[1].imm
;
15917 if (inst
.operands
[1].regisimm
)
15918 immhi
= inst
.operands
[1].reg
;
15920 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15921 _("immediate has bits set outside the operand size"));
15923 float_p
= inst
.operands
[1].immisfloat
;
15925 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15926 et
.size
, et
.type
)) == FAIL
)
15928 /* Invert relevant bits only. */
15929 neon_invert_size (&immlo
, &immhi
, et
.size
);
15930 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15931 with one or the other; those cases are caught by
15932 neon_cmode_for_move_imm. */
15934 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15935 &op
, et
.size
, et
.type
)) == FAIL
)
15937 first_error (_("immediate out of range"));
15942 inst
.instruction
&= ~(1 << 5);
15943 inst
.instruction
|= op
<< 5;
15945 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15946 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15947 inst
.instruction
|= neon_quad (rs
) << 6;
15948 inst
.instruction
|= cmode
<< 8;
15950 neon_write_immbits (immbits
);
15956 if (inst
.operands
[1].isreg
)
15958 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15960 NEON_ENCODE (INTEGER
, inst
);
15961 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15962 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15963 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15964 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15965 inst
.instruction
|= neon_quad (rs
) << 6;
15969 NEON_ENCODE (IMMED
, inst
);
15970 neon_move_immediate ();
15973 neon_dp_fixup (&inst
);
15976 /* Encode instructions of form:
15978 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15979 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15982 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15984 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15985 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15986 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15987 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15988 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15989 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15990 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15991 inst
.instruction
|= neon_logbits (size
) << 20;
15993 neon_dp_fixup (&inst
);
15997 do_neon_dyadic_long (void)
15999 /* FIXME: Type checking for lengthening op. */
16000 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16001 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16002 neon_mixed_length (et
, et
.size
);
16006 do_neon_abal (void)
16008 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16009 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16010 neon_mixed_length (et
, et
.size
);
16014 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16016 if (inst
.operands
[2].isscalar
)
16018 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16019 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16020 NEON_ENCODE (SCALAR
, inst
);
16021 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16025 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16026 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16027 NEON_ENCODE (INTEGER
, inst
);
16028 neon_mixed_length (et
, et
.size
);
16033 do_neon_mac_maybe_scalar_long (void)
16035 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16039 do_neon_dyadic_wide (void)
16041 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16042 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16043 neon_mixed_length (et
, et
.size
);
16047 do_neon_dyadic_narrow (void)
16049 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16050 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16051 /* Operand sign is unimportant, and the U bit is part of the opcode,
16052 so force the operand type to integer. */
16053 et
.type
= NT_integer
;
16054 neon_mixed_length (et
, et
.size
/ 2);
16058 do_neon_mul_sat_scalar_long (void)
16060 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16064 do_neon_vmull (void)
16066 if (inst
.operands
[2].isscalar
)
16067 do_neon_mac_maybe_scalar_long ();
16070 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16071 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16073 if (et
.type
== NT_poly
)
16074 NEON_ENCODE (POLY
, inst
);
16076 NEON_ENCODE (INTEGER
, inst
);
16078 /* For polynomial encoding the U bit must be zero, and the size must
16079 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16080 obviously, as 0b10). */
16083 /* Check we're on the correct architecture. */
16084 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16086 _("Instruction form not available on this architecture.");
16091 neon_mixed_length (et
, et
.size
);
16098 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16099 struct neon_type_el et
= neon_check_type (3, rs
,
16100 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16101 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16103 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16104 _("shift out of range"));
16105 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16106 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16107 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16108 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16109 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16110 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16111 inst
.instruction
|= neon_quad (rs
) << 6;
16112 inst
.instruction
|= imm
<< 8;
16114 neon_dp_fixup (&inst
);
16120 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16121 struct neon_type_el et
= neon_check_type (2, rs
,
16122 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16123 unsigned op
= (inst
.instruction
>> 7) & 3;
16124 /* N (width of reversed regions) is encoded as part of the bitmask. We
16125 extract it here to check the elements to be reversed are smaller.
16126 Otherwise we'd get a reserved instruction. */
16127 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16128 gas_assert (elsize
!= 0);
16129 constraint (et
.size
>= elsize
,
16130 _("elements must be smaller than reversal region"));
16131 neon_two_same (neon_quad (rs
), 1, et
.size
);
16137 if (inst
.operands
[1].isscalar
)
16139 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16140 struct neon_type_el et
= neon_check_type (2, rs
,
16141 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16142 unsigned sizebits
= et
.size
>> 3;
16143 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16144 int logsize
= neon_logbits (et
.size
);
16145 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16147 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16150 NEON_ENCODE (SCALAR
, inst
);
16151 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16152 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16153 inst
.instruction
|= LOW4 (dm
);
16154 inst
.instruction
|= HI1 (dm
) << 5;
16155 inst
.instruction
|= neon_quad (rs
) << 6;
16156 inst
.instruction
|= x
<< 17;
16157 inst
.instruction
|= sizebits
<< 16;
16159 neon_dp_fixup (&inst
);
16163 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16164 struct neon_type_el et
= neon_check_type (2, rs
,
16165 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16166 /* Duplicate ARM register to lanes of vector. */
16167 NEON_ENCODE (ARMREG
, inst
);
16170 case 8: inst
.instruction
|= 0x400000; break;
16171 case 16: inst
.instruction
|= 0x000020; break;
16172 case 32: inst
.instruction
|= 0x000000; break;
16175 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16176 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16177 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16178 inst
.instruction
|= neon_quad (rs
) << 21;
16179 /* The encoding for this instruction is identical for the ARM and Thumb
16180 variants, except for the condition field. */
16181 do_vfp_cond_or_thumb ();
16185 /* VMOV has particularly many variations. It can be one of:
16186 0. VMOV<c><q> <Qd>, <Qm>
16187 1. VMOV<c><q> <Dd>, <Dm>
16188 (Register operations, which are VORR with Rm = Rn.)
16189 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16190 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16192 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16193 (ARM register to scalar.)
16194 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16195 (Two ARM registers to vector.)
16196 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16197 (Scalar to ARM register.)
16198 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16199 (Vector to two ARM registers.)
16200 8. VMOV.F32 <Sd>, <Sm>
16201 9. VMOV.F64 <Dd>, <Dm>
16202 (VFP register moves.)
16203 10. VMOV.F32 <Sd>, #imm
16204 11. VMOV.F64 <Dd>, #imm
16205 (VFP float immediate load.)
16206 12. VMOV <Rd>, <Sm>
16207 (VFP single to ARM reg.)
16208 13. VMOV <Sd>, <Rm>
16209 (ARM reg to VFP single.)
16210 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16211 (Two ARM regs to two VFP singles.)
16212 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16213 (Two VFP singles to two ARM regs.)
16215 These cases can be disambiguated using neon_select_shape, except cases 1/9
16216 and 3/11 which depend on the operand type too.
16218 All the encoded bits are hardcoded by this function.
16220 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16221 Cases 5, 7 may be used with VFPv2 and above.
16223 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16224 can specify a type where it doesn't make sense to, and is ignored). */
16229 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16230 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16231 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16232 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16233 struct neon_type_el et
;
16234 const char *ldconst
= 0;
16238 case NS_DD
: /* case 1/9. */
16239 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16240 /* It is not an error here if no type is given. */
16242 if (et
.type
== NT_float
&& et
.size
== 64)
16244 do_vfp_nsyn_opcode ("fcpyd");
16247 /* fall through. */
16249 case NS_QQ
: /* case 0/1. */
16251 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16253 /* The architecture manual I have doesn't explicitly state which
16254 value the U bit should have for register->register moves, but
16255 the equivalent VORR instruction has U = 0, so do that. */
16256 inst
.instruction
= 0x0200110;
16257 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16258 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16259 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16260 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16261 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16262 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16263 inst
.instruction
|= neon_quad (rs
) << 6;
16265 neon_dp_fixup (&inst
);
16269 case NS_DI
: /* case 3/11. */
16270 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16272 if (et
.type
== NT_float
&& et
.size
== 64)
16274 /* case 11 (fconstd). */
16275 ldconst
= "fconstd";
16276 goto encode_fconstd
;
16278 /* fall through. */
16280 case NS_QI
: /* case 2/3. */
16281 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16283 inst
.instruction
= 0x0800010;
16284 neon_move_immediate ();
16285 neon_dp_fixup (&inst
);
16288 case NS_SR
: /* case 4. */
16290 unsigned bcdebits
= 0;
16292 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16293 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16295 /* .<size> is optional here, defaulting to .32. */
16296 if (inst
.vectype
.elems
== 0
16297 && inst
.operands
[0].vectype
.type
== NT_invtype
16298 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16300 inst
.vectype
.el
[0].type
= NT_untyped
;
16301 inst
.vectype
.el
[0].size
= 32;
16302 inst
.vectype
.elems
= 1;
16305 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16306 logsize
= neon_logbits (et
.size
);
16308 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16310 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16311 && et
.size
!= 32, _(BAD_FPU
));
16312 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16313 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16317 case 8: bcdebits
= 0x8; break;
16318 case 16: bcdebits
= 0x1; break;
16319 case 32: bcdebits
= 0x0; break;
16323 bcdebits
|= x
<< logsize
;
16325 inst
.instruction
= 0xe000b10;
16326 do_vfp_cond_or_thumb ();
16327 inst
.instruction
|= LOW4 (dn
) << 16;
16328 inst
.instruction
|= HI1 (dn
) << 7;
16329 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16330 inst
.instruction
|= (bcdebits
& 3) << 5;
16331 inst
.instruction
|= (bcdebits
>> 2) << 21;
16335 case NS_DRR
: /* case 5 (fmdrr). */
16336 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16339 inst
.instruction
= 0xc400b10;
16340 do_vfp_cond_or_thumb ();
16341 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16342 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16343 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16344 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16347 case NS_RS
: /* case 6. */
16350 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16351 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16352 unsigned abcdebits
= 0;
16354 /* .<dt> is optional here, defaulting to .32. */
16355 if (inst
.vectype
.elems
== 0
16356 && inst
.operands
[0].vectype
.type
== NT_invtype
16357 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16359 inst
.vectype
.el
[0].type
= NT_untyped
;
16360 inst
.vectype
.el
[0].size
= 32;
16361 inst
.vectype
.elems
= 1;
16364 et
= neon_check_type (2, NS_NULL
,
16365 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16366 logsize
= neon_logbits (et
.size
);
16368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16370 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16371 && et
.size
!= 32, _(BAD_FPU
));
16372 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16373 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16377 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16378 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16379 case 32: abcdebits
= 0x00; break;
16383 abcdebits
|= x
<< logsize
;
16384 inst
.instruction
= 0xe100b10;
16385 do_vfp_cond_or_thumb ();
16386 inst
.instruction
|= LOW4 (dn
) << 16;
16387 inst
.instruction
|= HI1 (dn
) << 7;
16388 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16389 inst
.instruction
|= (abcdebits
& 3) << 5;
16390 inst
.instruction
|= (abcdebits
>> 2) << 21;
16394 case NS_RRD
: /* case 7 (fmrrd). */
16395 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16398 inst
.instruction
= 0xc500b10;
16399 do_vfp_cond_or_thumb ();
16400 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16401 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16402 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16403 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16406 case NS_FF
: /* case 8 (fcpys). */
16407 do_vfp_nsyn_opcode ("fcpys");
16411 case NS_FI
: /* case 10 (fconsts). */
16412 ldconst
= "fconsts";
16414 if (is_quarter_float (inst
.operands
[1].imm
))
16416 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16417 do_vfp_nsyn_opcode (ldconst
);
16419 /* ARMv8.2 fp16 vmov.f16 instruction. */
16421 do_scalar_fp16_v82_encode ();
16424 first_error (_("immediate out of range"));
16428 case NS_RF
: /* case 12 (fmrs). */
16429 do_vfp_nsyn_opcode ("fmrs");
16430 /* ARMv8.2 fp16 vmov.f16 instruction. */
16432 do_scalar_fp16_v82_encode ();
16436 case NS_FR
: /* case 13 (fmsr). */
16437 do_vfp_nsyn_opcode ("fmsr");
16438 /* ARMv8.2 fp16 vmov.f16 instruction. */
16440 do_scalar_fp16_v82_encode ();
16443 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16444 (one of which is a list), but we have parsed four. Do some fiddling to
16445 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16447 case NS_RRFF
: /* case 14 (fmrrs). */
16448 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16449 _("VFP registers must be adjacent"));
16450 inst
.operands
[2].imm
= 2;
16451 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16452 do_vfp_nsyn_opcode ("fmrrs");
16455 case NS_FFRR
: /* case 15 (fmsrr). */
16456 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16457 _("VFP registers must be adjacent"));
16458 inst
.operands
[1] = inst
.operands
[2];
16459 inst
.operands
[2] = inst
.operands
[3];
16460 inst
.operands
[0].imm
= 2;
16461 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16462 do_vfp_nsyn_opcode ("fmsrr");
16466 /* neon_select_shape has determined that the instruction
16467 shape is wrong and has already set the error message. */
16476 do_neon_rshift_round_imm (void)
16478 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16479 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16480 int imm
= inst
.operands
[2].imm
;
16482 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16485 inst
.operands
[2].present
= 0;
16490 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16491 _("immediate out of range for shift"));
16492 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16497 do_neon_movhf (void)
16499 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16500 constraint (rs
!= NS_HH
, _("invalid suffix"));
16502 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16505 do_vfp_sp_monadic ();
16508 inst
.instruction
|= 0xf0000000;
16512 do_neon_movl (void)
16514 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16515 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16516 unsigned sizebits
= et
.size
>> 3;
16517 inst
.instruction
|= sizebits
<< 19;
16518 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16524 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16525 struct neon_type_el et
= neon_check_type (2, rs
,
16526 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16527 NEON_ENCODE (INTEGER
, inst
);
16528 neon_two_same (neon_quad (rs
), 1, et
.size
);
16532 do_neon_zip_uzp (void)
16534 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16535 struct neon_type_el et
= neon_check_type (2, rs
,
16536 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16537 if (rs
== NS_DD
&& et
.size
== 32)
16539 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16540 inst
.instruction
= N_MNEM_vtrn
;
16544 neon_two_same (neon_quad (rs
), 1, et
.size
);
16548 do_neon_sat_abs_neg (void)
16550 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16551 struct neon_type_el et
= neon_check_type (2, rs
,
16552 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16553 neon_two_same (neon_quad (rs
), 1, et
.size
);
16557 do_neon_pair_long (void)
16559 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16560 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16561 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16562 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16563 neon_two_same (neon_quad (rs
), 1, et
.size
);
16567 do_neon_recip_est (void)
16569 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16570 struct neon_type_el et
= neon_check_type (2, rs
,
16571 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16572 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16573 neon_two_same (neon_quad (rs
), 1, et
.size
);
16579 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16580 struct neon_type_el et
= neon_check_type (2, rs
,
16581 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16582 neon_two_same (neon_quad (rs
), 1, et
.size
);
16588 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16589 struct neon_type_el et
= neon_check_type (2, rs
,
16590 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16591 neon_two_same (neon_quad (rs
), 1, et
.size
);
16597 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16598 struct neon_type_el et
= neon_check_type (2, rs
,
16599 N_EQK
| N_INT
, N_8
| N_KEY
);
16600 neon_two_same (neon_quad (rs
), 1, et
.size
);
16606 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16607 neon_two_same (neon_quad (rs
), 1, -1);
16611 do_neon_tbl_tbx (void)
16613 unsigned listlenbits
;
16614 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16616 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16618 first_error (_("bad list length for table lookup"));
16622 listlenbits
= inst
.operands
[1].imm
- 1;
16623 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16624 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16625 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16626 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16627 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16628 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16629 inst
.instruction
|= listlenbits
<< 8;
16631 neon_dp_fixup (&inst
);
16635 do_neon_ldm_stm (void)
16637 /* P, U and L bits are part of bitmask. */
16638 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16639 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16641 if (inst
.operands
[1].issingle
)
16643 do_vfp_nsyn_ldm_stm (is_dbmode
);
16647 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16648 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16650 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16651 _("register list must contain at least 1 and at most 16 "
16654 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16655 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16656 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16657 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16659 inst
.instruction
|= offsetbits
;
16661 do_vfp_cond_or_thumb ();
16665 do_neon_ldr_str (void)
16667 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16669 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16670 And is UNPREDICTABLE in thumb mode. */
16672 && inst
.operands
[1].reg
== REG_PC
16673 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16676 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16677 else if (warn_on_deprecated
)
16678 as_tsktsk (_("Use of PC here is deprecated"));
16681 if (inst
.operands
[0].issingle
)
16684 do_vfp_nsyn_opcode ("flds");
16686 do_vfp_nsyn_opcode ("fsts");
16688 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16689 if (inst
.vectype
.el
[0].size
== 16)
16690 do_scalar_fp16_v82_encode ();
16695 do_vfp_nsyn_opcode ("fldd");
16697 do_vfp_nsyn_opcode ("fstd");
16701 /* "interleave" version also handles non-interleaving register VLD1/VST1
16705 do_neon_ld_st_interleave (void)
16707 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16708 N_8
| N_16
| N_32
| N_64
);
16709 unsigned alignbits
= 0;
16711 /* The bits in this table go:
16712 0: register stride of one (0) or two (1)
16713 1,2: register list length, minus one (1, 2, 3, 4).
16714 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16715 We use -1 for invalid entries. */
16716 const int typetable
[] =
16718 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16719 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16720 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16721 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16725 if (et
.type
== NT_invtype
)
16728 if (inst
.operands
[1].immisalign
)
16729 switch (inst
.operands
[1].imm
>> 8)
16731 case 64: alignbits
= 1; break;
16733 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16734 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16735 goto bad_alignment
;
16739 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16740 goto bad_alignment
;
16745 first_error (_("bad alignment"));
16749 inst
.instruction
|= alignbits
<< 4;
16750 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16752 /* Bits [4:6] of the immediate in a list specifier encode register stride
16753 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16754 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16755 up the right value for "type" in a table based on this value and the given
16756 list style, then stick it back. */
16757 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16758 | (((inst
.instruction
>> 8) & 3) << 3);
16760 typebits
= typetable
[idx
];
16762 constraint (typebits
== -1, _("bad list type for instruction"));
16763 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16764 _("bad element type for instruction"));
16766 inst
.instruction
&= ~0xf00;
16767 inst
.instruction
|= typebits
<< 8;
16770 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16771 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16772 otherwise. The variable arguments are a list of pairs of legal (size, align)
16773 values, terminated with -1. */
16776 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16779 int result
= FAIL
, thissize
, thisalign
;
16781 if (!inst
.operands
[1].immisalign
)
16787 va_start (ap
, do_alignment
);
16791 thissize
= va_arg (ap
, int);
16792 if (thissize
== -1)
16794 thisalign
= va_arg (ap
, int);
16796 if (size
== thissize
&& align
== thisalign
)
16799 while (result
!= SUCCESS
);
16803 if (result
== SUCCESS
)
16806 first_error (_("unsupported alignment for instruction"));
16812 do_neon_ld_st_lane (void)
16814 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16815 int align_good
, do_alignment
= 0;
16816 int logsize
= neon_logbits (et
.size
);
16817 int align
= inst
.operands
[1].imm
>> 8;
16818 int n
= (inst
.instruction
>> 8) & 3;
16819 int max_el
= 64 / et
.size
;
16821 if (et
.type
== NT_invtype
)
16824 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16825 _("bad list length"));
16826 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16827 _("scalar index out of range"));
16828 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16830 _("stride of 2 unavailable when element size is 8"));
16834 case 0: /* VLD1 / VST1. */
16835 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16837 if (align_good
== FAIL
)
16841 unsigned alignbits
= 0;
16844 case 16: alignbits
= 0x1; break;
16845 case 32: alignbits
= 0x3; break;
16848 inst
.instruction
|= alignbits
<< 4;
16852 case 1: /* VLD2 / VST2. */
16853 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16854 16, 32, 32, 64, -1);
16855 if (align_good
== FAIL
)
16858 inst
.instruction
|= 1 << 4;
16861 case 2: /* VLD3 / VST3. */
16862 constraint (inst
.operands
[1].immisalign
,
16863 _("can't use alignment with this instruction"));
16866 case 3: /* VLD4 / VST4. */
16867 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16868 16, 64, 32, 64, 32, 128, -1);
16869 if (align_good
== FAIL
)
16873 unsigned alignbits
= 0;
16876 case 8: alignbits
= 0x1; break;
16877 case 16: alignbits
= 0x1; break;
16878 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16881 inst
.instruction
|= alignbits
<< 4;
16888 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16889 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16890 inst
.instruction
|= 1 << (4 + logsize
);
16892 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16893 inst
.instruction
|= logsize
<< 10;
16896 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16899 do_neon_ld_dup (void)
16901 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16902 int align_good
, do_alignment
= 0;
16904 if (et
.type
== NT_invtype
)
16907 switch ((inst
.instruction
>> 8) & 3)
16909 case 0: /* VLD1. */
16910 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16911 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16912 &do_alignment
, 16, 16, 32, 32, -1);
16913 if (align_good
== FAIL
)
16915 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16918 case 2: inst
.instruction
|= 1 << 5; break;
16919 default: first_error (_("bad list length")); return;
16921 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16924 case 1: /* VLD2. */
16925 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16926 &do_alignment
, 8, 16, 16, 32, 32, 64,
16928 if (align_good
== FAIL
)
16930 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16931 _("bad list length"));
16932 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16933 inst
.instruction
|= 1 << 5;
16934 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16937 case 2: /* VLD3. */
16938 constraint (inst
.operands
[1].immisalign
,
16939 _("can't use alignment with this instruction"));
16940 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16941 _("bad list length"));
16942 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16943 inst
.instruction
|= 1 << 5;
16944 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16947 case 3: /* VLD4. */
16949 int align
= inst
.operands
[1].imm
>> 8;
16950 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16951 16, 64, 32, 64, 32, 128, -1);
16952 if (align_good
== FAIL
)
16954 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16955 _("bad list length"));
16956 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16957 inst
.instruction
|= 1 << 5;
16958 if (et
.size
== 32 && align
== 128)
16959 inst
.instruction
|= 0x3 << 6;
16961 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16968 inst
.instruction
|= do_alignment
<< 4;
16971 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16972 apart from bits [11:4]. */
16975 do_neon_ldx_stx (void)
16977 if (inst
.operands
[1].isreg
)
16978 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16980 switch (NEON_LANE (inst
.operands
[0].imm
))
16982 case NEON_INTERLEAVE_LANES
:
16983 NEON_ENCODE (INTERLV
, inst
);
16984 do_neon_ld_st_interleave ();
16987 case NEON_ALL_LANES
:
16988 NEON_ENCODE (DUP
, inst
);
16989 if (inst
.instruction
== N_INV
)
16991 first_error ("only loads support such operands");
16998 NEON_ENCODE (LANE
, inst
);
16999 do_neon_ld_st_lane ();
17002 /* L bit comes from bit mask. */
17003 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17004 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17005 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17007 if (inst
.operands
[1].postind
)
17009 int postreg
= inst
.operands
[1].imm
& 0xf;
17010 constraint (!inst
.operands
[1].immisreg
,
17011 _("post-index must be a register"));
17012 constraint (postreg
== 0xd || postreg
== 0xf,
17013 _("bad register for post-index"));
17014 inst
.instruction
|= postreg
;
17018 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17019 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17020 || inst
.reloc
.exp
.X_add_number
!= 0,
17023 if (inst
.operands
[1].writeback
)
17025 inst
.instruction
|= 0xd;
17028 inst
.instruction
|= 0xf;
17032 inst
.instruction
|= 0xf9000000;
17034 inst
.instruction
|= 0xf4000000;
17039 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17041 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17042 D register operands. */
17043 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17044 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17047 NEON_ENCODE (FPV8
, inst
);
17049 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17051 do_vfp_sp_dyadic ();
17053 /* ARMv8.2 fp16 instruction. */
17055 do_scalar_fp16_v82_encode ();
17058 do_vfp_dp_rd_rn_rm ();
17061 inst
.instruction
|= 0x100;
17063 inst
.instruction
|= 0xf0000000;
17069 set_it_insn_type (OUTSIDE_IT_INSN
);
17071 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17072 first_error (_("invalid instruction shape"));
17078 set_it_insn_type (OUTSIDE_IT_INSN
);
17080 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17083 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17086 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17090 do_vrint_1 (enum neon_cvt_mode mode
)
17092 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17093 struct neon_type_el et
;
17098 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17099 D register operands. */
17100 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17101 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17104 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17106 if (et
.type
!= NT_invtype
)
17108 /* VFP encodings. */
17109 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17110 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17111 set_it_insn_type (OUTSIDE_IT_INSN
);
17113 NEON_ENCODE (FPV8
, inst
);
17114 if (rs
== NS_FF
|| rs
== NS_HH
)
17115 do_vfp_sp_monadic ();
17117 do_vfp_dp_rd_rm ();
17121 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17122 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17123 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17124 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17125 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17126 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17127 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17131 inst
.instruction
|= (rs
== NS_DD
) << 8;
17132 do_vfp_cond_or_thumb ();
17134 /* ARMv8.2 fp16 vrint instruction. */
17136 do_scalar_fp16_v82_encode ();
17140 /* Neon encodings (or something broken...). */
17142 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17144 if (et
.type
== NT_invtype
)
17147 set_it_insn_type (OUTSIDE_IT_INSN
);
17148 NEON_ENCODE (FLOAT
, inst
);
17150 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17153 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17154 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17155 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17156 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17157 inst
.instruction
|= neon_quad (rs
) << 6;
17158 /* Mask off the original size bits and reencode them. */
17159 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17160 | neon_logbits (et
.size
) << 18);
17164 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17165 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17166 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17167 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17168 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17169 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17170 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17175 inst
.instruction
|= 0xfc000000;
17177 inst
.instruction
|= 0xf0000000;
17184 do_vrint_1 (neon_cvt_mode_x
);
17190 do_vrint_1 (neon_cvt_mode_z
);
17196 do_vrint_1 (neon_cvt_mode_r
);
17202 do_vrint_1 (neon_cvt_mode_a
);
17208 do_vrint_1 (neon_cvt_mode_n
);
17214 do_vrint_1 (neon_cvt_mode_p
);
17220 do_vrint_1 (neon_cvt_mode_m
);
17223 /* Crypto v1 instructions. */
17225 do_crypto_2op_1 (unsigned elttype
, int op
)
17227 set_it_insn_type (OUTSIDE_IT_INSN
);
17229 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17235 NEON_ENCODE (INTEGER
, inst
);
17236 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17237 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17238 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17239 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17241 inst
.instruction
|= op
<< 6;
17244 inst
.instruction
|= 0xfc000000;
17246 inst
.instruction
|= 0xf0000000;
17250 do_crypto_3op_1 (int u
, int op
)
17252 set_it_insn_type (OUTSIDE_IT_INSN
);
17254 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17255 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17260 NEON_ENCODE (INTEGER
, inst
);
17261 neon_three_same (1, u
, 8 << op
);
17267 do_crypto_2op_1 (N_8
, 0);
17273 do_crypto_2op_1 (N_8
, 1);
17279 do_crypto_2op_1 (N_8
, 2);
17285 do_crypto_2op_1 (N_8
, 3);
17291 do_crypto_3op_1 (0, 0);
17297 do_crypto_3op_1 (0, 1);
17303 do_crypto_3op_1 (0, 2);
17309 do_crypto_3op_1 (0, 3);
17315 do_crypto_3op_1 (1, 0);
17321 do_crypto_3op_1 (1, 1);
17325 do_sha256su1 (void)
17327 do_crypto_3op_1 (1, 2);
17333 do_crypto_2op_1 (N_32
, -1);
17339 do_crypto_2op_1 (N_32
, 0);
17343 do_sha256su0 (void)
17345 do_crypto_2op_1 (N_32
, 1);
17349 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17351 unsigned int Rd
= inst
.operands
[0].reg
;
17352 unsigned int Rn
= inst
.operands
[1].reg
;
17353 unsigned int Rm
= inst
.operands
[2].reg
;
17355 set_it_insn_type (OUTSIDE_IT_INSN
);
17356 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17357 inst
.instruction
|= LOW4 (Rn
) << 16;
17358 inst
.instruction
|= LOW4 (Rm
);
17359 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17360 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17362 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17363 as_warn (UNPRED_REG ("r15"));
17364 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17365 as_warn (UNPRED_REG ("r13"));
17405 /* Overall per-instruction processing. */
17407 /* We need to be able to fix up arbitrary expressions in some statements.
17408 This is so that we can handle symbols that are an arbitrary distance from
17409 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17410 which returns part of an address in a form which will be valid for
17411 a data instruction. We do this by pushing the expression into a symbol
17412 in the expr_section, and creating a fix for that. */
17415 fix_new_arm (fragS
* frag
,
17429 /* Create an absolute valued symbol, so we have something to
17430 refer to in the object file. Unfortunately for us, gas's
17431 generic expression parsing will already have folded out
17432 any use of .set foo/.type foo %function that may have
17433 been used to set type information of the target location,
17434 that's being specified symbolically. We have to presume
17435 the user knows what they are doing. */
17439 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17441 symbol
= symbol_find_or_make (name
);
17442 S_SET_SEGMENT (symbol
, absolute_section
);
17443 symbol_set_frag (symbol
, &zero_address_frag
);
17444 S_SET_VALUE (symbol
, exp
->X_add_number
);
17445 exp
->X_op
= O_symbol
;
17446 exp
->X_add_symbol
= symbol
;
17447 exp
->X_add_number
= 0;
17453 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17454 (enum bfd_reloc_code_real
) reloc
);
17458 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17459 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17463 /* Mark whether the fix is to a THUMB instruction, or an ARM
17465 new_fix
->tc_fix_data
= thumb_mode
;
17468 /* Create a frg for an instruction requiring relaxation. */
17470 output_relax_insn (void)
17476 /* The size of the instruction is unknown, so tie the debug info to the
17477 start of the instruction. */
17478 dwarf2_emit_insn (0);
17480 switch (inst
.reloc
.exp
.X_op
)
17483 sym
= inst
.reloc
.exp
.X_add_symbol
;
17484 offset
= inst
.reloc
.exp
.X_add_number
;
17488 offset
= inst
.reloc
.exp
.X_add_number
;
17491 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17495 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17496 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17497 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17500 /* Write a 32-bit thumb instruction to buf. */
17502 put_thumb32_insn (char * buf
, unsigned long insn
)
17504 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17505 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17509 output_inst (const char * str
)
17515 as_bad ("%s -- `%s'", inst
.error
, str
);
17520 output_relax_insn ();
17523 if (inst
.size
== 0)
17526 to
= frag_more (inst
.size
);
17527 /* PR 9814: Record the thumb mode into the current frag so that we know
17528 what type of NOP padding to use, if necessary. We override any previous
17529 setting so that if the mode has changed then the NOPS that we use will
17530 match the encoding of the last instruction in the frag. */
17531 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17533 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17535 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17536 put_thumb32_insn (to
, inst
.instruction
);
17538 else if (inst
.size
> INSN_SIZE
)
17540 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17541 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17542 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17545 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17547 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17548 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17549 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17552 dwarf2_emit_insn (inst
.size
);
17556 output_it_inst (int cond
, int mask
, char * to
)
17558 unsigned long instruction
= 0xbf00;
17561 instruction
|= mask
;
17562 instruction
|= cond
<< 4;
17566 to
= frag_more (2);
17568 dwarf2_emit_insn (2);
17572 md_number_to_chars (to
, instruction
, 2);
17577 /* Tag values used in struct asm_opcode's tag field. */
17580 OT_unconditional
, /* Instruction cannot be conditionalized.
17581 The ARM condition field is still 0xE. */
17582 OT_unconditionalF
, /* Instruction cannot be conditionalized
17583 and carries 0xF in its ARM condition field. */
17584 OT_csuffix
, /* Instruction takes a conditional suffix. */
17585 OT_csuffixF
, /* Some forms of the instruction take a conditional
17586 suffix, others place 0xF where the condition field
17588 OT_cinfix3
, /* Instruction takes a conditional infix,
17589 beginning at character index 3. (In
17590 unified mode, it becomes a suffix.) */
17591 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17592 tsts, cmps, cmns, and teqs. */
17593 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17594 character index 3, even in unified mode. Used for
17595 legacy instructions where suffix and infix forms
17596 may be ambiguous. */
17597 OT_csuf_or_in3
, /* Instruction takes either a conditional
17598 suffix or an infix at character index 3. */
17599 OT_odd_infix_unc
, /* This is the unconditional variant of an
17600 instruction that takes a conditional infix
17601 at an unusual position. In unified mode,
17602 this variant will accept a suffix. */
17603 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17604 are the conditional variants of instructions that
17605 take conditional infixes in unusual positions.
17606 The infix appears at character index
17607 (tag - OT_odd_infix_0). These are not accepted
17608 in unified mode. */
17611 /* Subroutine of md_assemble, responsible for looking up the primary
17612 opcode from the mnemonic the user wrote. STR points to the
17613 beginning of the mnemonic.
17615 This is not simply a hash table lookup, because of conditional
17616 variants. Most instructions have conditional variants, which are
17617 expressed with a _conditional affix_ to the mnemonic. If we were
17618 to encode each conditional variant as a literal string in the opcode
17619 table, it would have approximately 20,000 entries.
17621 Most mnemonics take this affix as a suffix, and in unified syntax,
17622 'most' is upgraded to 'all'. However, in the divided syntax, some
17623 instructions take the affix as an infix, notably the s-variants of
17624 the arithmetic instructions. Of those instructions, all but six
17625 have the infix appear after the third character of the mnemonic.
17627 Accordingly, the algorithm for looking up primary opcodes given
17630 1. Look up the identifier in the opcode table.
17631 If we find a match, go to step U.
17633 2. Look up the last two characters of the identifier in the
17634 conditions table. If we find a match, look up the first N-2
17635 characters of the identifier in the opcode table. If we
17636 find a match, go to step CE.
17638 3. Look up the fourth and fifth characters of the identifier in
17639 the conditions table. If we find a match, extract those
17640 characters from the identifier, and look up the remaining
17641 characters in the opcode table. If we find a match, go
17646 U. Examine the tag field of the opcode structure, in case this is
17647 one of the six instructions with its conditional infix in an
17648 unusual place. If it is, the tag tells us where to find the
17649 infix; look it up in the conditions table and set inst.cond
17650 accordingly. Otherwise, this is an unconditional instruction.
17651 Again set inst.cond accordingly. Return the opcode structure.
17653 CE. Examine the tag field to make sure this is an instruction that
17654 should receive a conditional suffix. If it is not, fail.
17655 Otherwise, set inst.cond from the suffix we already looked up,
17656 and return the opcode structure.
17658 CM. Examine the tag field to make sure this is an instruction that
17659 should receive a conditional infix after the third character.
17660 If it is not, fail. Otherwise, undo the edits to the current
17661 line of input and proceed as for case CE. */
17663 static const struct asm_opcode
*
17664 opcode_lookup (char **str
)
17668 const struct asm_opcode
*opcode
;
17669 const struct asm_cond
*cond
;
17672 /* Scan up to the end of the mnemonic, which must end in white space,
17673 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17674 for (base
= end
= *str
; *end
!= '\0'; end
++)
17675 if (*end
== ' ' || *end
== '.')
17681 /* Handle a possible width suffix and/or Neon type suffix. */
17686 /* The .w and .n suffixes are only valid if the unified syntax is in
17688 if (unified_syntax
&& end
[1] == 'w')
17690 else if (unified_syntax
&& end
[1] == 'n')
17695 inst
.vectype
.elems
= 0;
17697 *str
= end
+ offset
;
17699 if (end
[offset
] == '.')
17701 /* See if we have a Neon type suffix (possible in either unified or
17702 non-unified ARM syntax mode). */
17703 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17706 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17712 /* Look for unaffixed or special-case affixed mnemonic. */
17713 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17718 if (opcode
->tag
< OT_odd_infix_0
)
17720 inst
.cond
= COND_ALWAYS
;
17724 if (warn_on_deprecated
&& unified_syntax
)
17725 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17726 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17727 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17730 inst
.cond
= cond
->value
;
17734 /* Cannot have a conditional suffix on a mnemonic of less than two
17736 if (end
- base
< 3)
17739 /* Look for suffixed mnemonic. */
17741 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17742 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17744 if (opcode
&& cond
)
17747 switch (opcode
->tag
)
17749 case OT_cinfix3_legacy
:
17750 /* Ignore conditional suffixes matched on infix only mnemonics. */
17754 case OT_cinfix3_deprecated
:
17755 case OT_odd_infix_unc
:
17756 if (!unified_syntax
)
17758 /* else fall through */
17762 case OT_csuf_or_in3
:
17763 inst
.cond
= cond
->value
;
17766 case OT_unconditional
:
17767 case OT_unconditionalF
:
17769 inst
.cond
= cond
->value
;
17772 /* Delayed diagnostic. */
17773 inst
.error
= BAD_COND
;
17774 inst
.cond
= COND_ALWAYS
;
17783 /* Cannot have a usual-position infix on a mnemonic of less than
17784 six characters (five would be a suffix). */
17785 if (end
- base
< 6)
17788 /* Look for infixed mnemonic in the usual position. */
17790 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17794 memcpy (save
, affix
, 2);
17795 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17796 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17798 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17799 memcpy (affix
, save
, 2);
17802 && (opcode
->tag
== OT_cinfix3
17803 || opcode
->tag
== OT_cinfix3_deprecated
17804 || opcode
->tag
== OT_csuf_or_in3
17805 || opcode
->tag
== OT_cinfix3_legacy
))
17808 if (warn_on_deprecated
&& unified_syntax
17809 && (opcode
->tag
== OT_cinfix3
17810 || opcode
->tag
== OT_cinfix3_deprecated
))
17811 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17813 inst
.cond
= cond
->value
;
17820 /* This function generates an initial IT instruction, leaving its block
17821 virtually open for the new instructions. Eventually,
17822 the mask will be updated by now_it_add_mask () each time
17823 a new instruction needs to be included in the IT block.
17824 Finally, the block is closed with close_automatic_it_block ().
17825 The block closure can be requested either from md_assemble (),
17826 a tencode (), or due to a label hook. */
17829 new_automatic_it_block (int cond
)
17831 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17832 now_it
.mask
= 0x18;
17834 now_it
.block_length
= 1;
17835 mapping_state (MAP_THUMB
);
17836 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17837 now_it
.warn_deprecated
= FALSE
;
17838 now_it
.insn_cond
= TRUE
;
17841 /* Close an automatic IT block.
17842 See comments in new_automatic_it_block (). */
17845 close_automatic_it_block (void)
17847 now_it
.mask
= 0x10;
17848 now_it
.block_length
= 0;
17851 /* Update the mask of the current automatically-generated IT
17852 instruction. See comments in new_automatic_it_block (). */
17855 now_it_add_mask (int cond
)
17857 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17858 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17859 | ((bitvalue) << (nbit)))
17860 const int resulting_bit
= (cond
& 1);
17862 now_it
.mask
&= 0xf;
17863 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17865 (5 - now_it
.block_length
));
17866 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17868 ((5 - now_it
.block_length
) - 1) );
17869 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17872 #undef SET_BIT_VALUE
17875 /* The IT blocks handling machinery is accessed through the these functions:
17876 it_fsm_pre_encode () from md_assemble ()
17877 set_it_insn_type () optional, from the tencode functions
17878 set_it_insn_type_last () ditto
17879 in_it_block () ditto
17880 it_fsm_post_encode () from md_assemble ()
17881 force_automatic_it_block_close () from label habdling functions
17884 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17885 initializing the IT insn type with a generic initial value depending
17886 on the inst.condition.
17887 2) During the tencode function, two things may happen:
17888 a) The tencode function overrides the IT insn type by
17889 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17890 b) The tencode function queries the IT block state by
17891 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17893 Both set_it_insn_type and in_it_block run the internal FSM state
17894 handling function (handle_it_state), because: a) setting the IT insn
17895 type may incur in an invalid state (exiting the function),
17896 and b) querying the state requires the FSM to be updated.
17897 Specifically we want to avoid creating an IT block for conditional
17898 branches, so it_fsm_pre_encode is actually a guess and we can't
17899 determine whether an IT block is required until the tencode () routine
17900 has decided what type of instruction this actually it.
17901 Because of this, if set_it_insn_type and in_it_block have to be used,
17902 set_it_insn_type has to be called first.
17904 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17905 determines the insn IT type depending on the inst.cond code.
17906 When a tencode () routine encodes an instruction that can be
17907 either outside an IT block, or, in the case of being inside, has to be
17908 the last one, set_it_insn_type_last () will determine the proper
17909 IT instruction type based on the inst.cond code. Otherwise,
17910 set_it_insn_type can be called for overriding that logic or
17911 for covering other cases.
17913 Calling handle_it_state () may not transition the IT block state to
17914 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17915 still queried. Instead, if the FSM determines that the state should
17916 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17917 after the tencode () function: that's what it_fsm_post_encode () does.
17919 Since in_it_block () calls the state handling function to get an
17920 updated state, an error may occur (due to invalid insns combination).
17921 In that case, inst.error is set.
17922 Therefore, inst.error has to be checked after the execution of
17923 the tencode () routine.
17925 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17926 any pending state change (if any) that didn't take place in
17927 handle_it_state () as explained above. */
17930 it_fsm_pre_encode (void)
17932 if (inst
.cond
!= COND_ALWAYS
)
17933 inst
.it_insn_type
= INSIDE_IT_INSN
;
17935 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17937 now_it
.state_handled
= 0;
17940 /* IT state FSM handling function. */
17943 handle_it_state (void)
17945 now_it
.state_handled
= 1;
17946 now_it
.insn_cond
= FALSE
;
17948 switch (now_it
.state
)
17950 case OUTSIDE_IT_BLOCK
:
17951 switch (inst
.it_insn_type
)
17953 case OUTSIDE_IT_INSN
:
17956 case INSIDE_IT_INSN
:
17957 case INSIDE_IT_LAST_INSN
:
17958 if (thumb_mode
== 0)
17961 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17962 as_tsktsk (_("Warning: conditional outside an IT block"\
17967 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17968 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
17970 /* Automatically generate the IT instruction. */
17971 new_automatic_it_block (inst
.cond
);
17972 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17973 close_automatic_it_block ();
17977 inst
.error
= BAD_OUT_IT
;
17983 case IF_INSIDE_IT_LAST_INSN
:
17984 case NEUTRAL_IT_INSN
:
17988 now_it
.state
= MANUAL_IT_BLOCK
;
17989 now_it
.block_length
= 0;
17994 case AUTOMATIC_IT_BLOCK
:
17995 /* Three things may happen now:
17996 a) We should increment current it block size;
17997 b) We should close current it block (closing insn or 4 insns);
17998 c) We should close current it block and start a new one (due
17999 to incompatible conditions or
18000 4 insns-length block reached). */
18002 switch (inst
.it_insn_type
)
18004 case OUTSIDE_IT_INSN
:
18005 /* The closure of the block shall happen immediatelly,
18006 so any in_it_block () call reports the block as closed. */
18007 force_automatic_it_block_close ();
18010 case INSIDE_IT_INSN
:
18011 case INSIDE_IT_LAST_INSN
:
18012 case IF_INSIDE_IT_LAST_INSN
:
18013 now_it
.block_length
++;
18015 if (now_it
.block_length
> 4
18016 || !now_it_compatible (inst
.cond
))
18018 force_automatic_it_block_close ();
18019 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18020 new_automatic_it_block (inst
.cond
);
18024 now_it
.insn_cond
= TRUE
;
18025 now_it_add_mask (inst
.cond
);
18028 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18029 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18030 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18031 close_automatic_it_block ();
18034 case NEUTRAL_IT_INSN
:
18035 now_it
.block_length
++;
18036 now_it
.insn_cond
= TRUE
;
18038 if (now_it
.block_length
> 4)
18039 force_automatic_it_block_close ();
18041 now_it_add_mask (now_it
.cc
& 1);
18045 close_automatic_it_block ();
18046 now_it
.state
= MANUAL_IT_BLOCK
;
18051 case MANUAL_IT_BLOCK
:
18053 /* Check conditional suffixes. */
18054 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18057 now_it
.mask
&= 0x1f;
18058 is_last
= (now_it
.mask
== 0x10);
18059 now_it
.insn_cond
= TRUE
;
18061 switch (inst
.it_insn_type
)
18063 case OUTSIDE_IT_INSN
:
18064 inst
.error
= BAD_NOT_IT
;
18067 case INSIDE_IT_INSN
:
18068 if (cond
!= inst
.cond
)
18070 inst
.error
= BAD_IT_COND
;
18075 case INSIDE_IT_LAST_INSN
:
18076 case IF_INSIDE_IT_LAST_INSN
:
18077 if (cond
!= inst
.cond
)
18079 inst
.error
= BAD_IT_COND
;
18084 inst
.error
= BAD_BRANCH
;
18089 case NEUTRAL_IT_INSN
:
18090 /* The BKPT instruction is unconditional even in an IT block. */
18094 inst
.error
= BAD_IT_IT
;
18104 struct depr_insn_mask
18106 unsigned long pattern
;
18107 unsigned long mask
;
18108 const char* description
;
18111 /* List of 16-bit instruction patterns deprecated in an IT block in
18113 static const struct depr_insn_mask depr_it_insns
[] = {
18114 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18115 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18116 { 0xa000, 0xb800, N_("ADR") },
18117 { 0x4800, 0xf800, N_("Literal loads") },
18118 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18119 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18120 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18121 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18122 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18127 it_fsm_post_encode (void)
18131 if (!now_it
.state_handled
)
18132 handle_it_state ();
18134 if (now_it
.insn_cond
18135 && !now_it
.warn_deprecated
18136 && warn_on_deprecated
18137 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18139 if (inst
.instruction
>= 0x10000)
18141 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18142 "deprecated in ARMv8"));
18143 now_it
.warn_deprecated
= TRUE
;
18147 const struct depr_insn_mask
*p
= depr_it_insns
;
18149 while (p
->mask
!= 0)
18151 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18153 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18154 "of the following class are deprecated in ARMv8: "
18155 "%s"), p
->description
);
18156 now_it
.warn_deprecated
= TRUE
;
18164 if (now_it
.block_length
> 1)
18166 as_tsktsk (_("IT blocks containing more than one conditional "
18167 "instruction are deprecated in ARMv8"));
18168 now_it
.warn_deprecated
= TRUE
;
18172 is_last
= (now_it
.mask
== 0x10);
18175 now_it
.state
= OUTSIDE_IT_BLOCK
;
18181 force_automatic_it_block_close (void)
18183 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18185 close_automatic_it_block ();
18186 now_it
.state
= OUTSIDE_IT_BLOCK
;
18194 if (!now_it
.state_handled
)
18195 handle_it_state ();
18197 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18200 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18201 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18202 here, hence the "known" in the function name. */
18205 known_t32_only_insn (const struct asm_opcode
*opcode
)
18207 /* Original Thumb-1 wide instruction. */
18208 if (opcode
->tencode
== do_t_blx
18209 || opcode
->tencode
== do_t_branch23
18210 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18211 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18214 /* Wide-only instruction added to ARMv8-M Baseline. */
18215 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18216 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18217 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18218 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18224 /* Whether wide instruction variant can be used if available for a valid OPCODE
18228 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18230 if (known_t32_only_insn (opcode
))
18233 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18234 of variant T3 of B.W is checked in do_t_branch. */
18235 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18236 && opcode
->tencode
== do_t_branch
)
18239 /* Wide instruction variants of all instructions with narrow *and* wide
18240 variants become available with ARMv6t2. Other opcodes are either
18241 narrow-only or wide-only and are thus available if OPCODE is valid. */
18242 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18245 /* OPCODE with narrow only instruction variant or wide variant not
18251 md_assemble (char *str
)
18254 const struct asm_opcode
* opcode
;
18256 /* Align the previous label if needed. */
18257 if (last_label_seen
!= NULL
)
18259 symbol_set_frag (last_label_seen
, frag_now
);
18260 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18261 S_SET_SEGMENT (last_label_seen
, now_seg
);
18264 memset (&inst
, '\0', sizeof (inst
));
18265 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18267 opcode
= opcode_lookup (&p
);
18270 /* It wasn't an instruction, but it might be a register alias of
18271 the form alias .req reg, or a Neon .dn/.qn directive. */
18272 if (! create_register_alias (str
, p
)
18273 && ! create_neon_reg_alias (str
, p
))
18274 as_bad (_("bad instruction `%s'"), str
);
18279 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18280 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18282 /* The value which unconditional instructions should have in place of the
18283 condition field. */
18284 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18288 arm_feature_set variant
;
18290 variant
= cpu_variant
;
18291 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18292 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18293 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18294 /* Check that this instruction is supported for this CPU. */
18295 if (!opcode
->tvariant
18296 || (thumb_mode
== 1
18297 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18299 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18302 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18303 && opcode
->tencode
!= do_t_branch
)
18305 as_bad (_("Thumb does not support conditional execution"));
18309 /* Two things are addressed here:
18310 1) Implicit require narrow instructions on Thumb-1.
18311 This avoids relaxation accidentally introducing Thumb-2
18313 2) Reject wide instructions in non Thumb-2 cores.
18315 Only instructions with narrow and wide variants need to be handled
18316 but selecting all non wide-only instructions is easier. */
18317 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18318 && !t32_insn_ok (variant
, opcode
))
18320 if (inst
.size_req
== 0)
18322 else if (inst
.size_req
== 4)
18324 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18325 as_bad (_("selected processor does not support 32bit wide "
18326 "variant of instruction `%s'"), str
);
18328 as_bad (_("selected processor does not support `%s' in "
18329 "Thumb-2 mode"), str
);
18334 inst
.instruction
= opcode
->tvalue
;
18336 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18338 /* Prepare the it_insn_type for those encodings that don't set
18340 it_fsm_pre_encode ();
18342 opcode
->tencode ();
18344 it_fsm_post_encode ();
18347 if (!(inst
.error
|| inst
.relax
))
18349 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18350 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18351 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18353 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18358 /* Something has gone badly wrong if we try to relax a fixed size
18360 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18362 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18363 *opcode
->tvariant
);
18364 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18365 set those bits when Thumb-2 32-bit instructions are seen. The impact
18366 of relaxable instructions will be considered later after we finish all
18368 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18369 variant
= arm_arch_none
;
18371 variant
= cpu_variant
;
18372 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18373 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18376 check_neon_suffixes
;
18380 mapping_state (MAP_THUMB
);
18383 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18387 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18388 is_bx
= (opcode
->aencode
== do_bx
);
18390 /* Check that this instruction is supported for this CPU. */
18391 if (!(is_bx
&& fix_v4bx
)
18392 && !(opcode
->avariant
&&
18393 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18395 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18400 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18404 inst
.instruction
= opcode
->avalue
;
18405 if (opcode
->tag
== OT_unconditionalF
)
18406 inst
.instruction
|= 0xFU
<< 28;
18408 inst
.instruction
|= inst
.cond
<< 28;
18409 inst
.size
= INSN_SIZE
;
18410 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18412 it_fsm_pre_encode ();
18413 opcode
->aencode ();
18414 it_fsm_post_encode ();
18416 /* Arm mode bx is marked as both v4T and v5 because it's still required
18417 on a hypothetical non-thumb v5 core. */
18419 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18421 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18422 *opcode
->avariant
);
18424 check_neon_suffixes
;
18428 mapping_state (MAP_ARM
);
18433 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18441 check_it_blocks_finished (void)
18446 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18447 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18448 == MANUAL_IT_BLOCK
)
18450 as_warn (_("section '%s' finished with an open IT block."),
18454 if (now_it
.state
== MANUAL_IT_BLOCK
)
18455 as_warn (_("file finished with an open IT block."));
18459 /* Various frobbings of labels and their addresses. */
18462 arm_start_line_hook (void)
18464 last_label_seen
= NULL
;
18468 arm_frob_label (symbolS
* sym
)
18470 last_label_seen
= sym
;
18472 ARM_SET_THUMB (sym
, thumb_mode
);
18474 #if defined OBJ_COFF || defined OBJ_ELF
18475 ARM_SET_INTERWORK (sym
, support_interwork
);
18478 force_automatic_it_block_close ();
18480 /* Note - do not allow local symbols (.Lxxx) to be labelled
18481 as Thumb functions. This is because these labels, whilst
18482 they exist inside Thumb code, are not the entry points for
18483 possible ARM->Thumb calls. Also, these labels can be used
18484 as part of a computed goto or switch statement. eg gcc
18485 can generate code that looks like this:
18487 ldr r2, [pc, .Laaa]
18497 The first instruction loads the address of the jump table.
18498 The second instruction converts a table index into a byte offset.
18499 The third instruction gets the jump address out of the table.
18500 The fourth instruction performs the jump.
18502 If the address stored at .Laaa is that of a symbol which has the
18503 Thumb_Func bit set, then the linker will arrange for this address
18504 to have the bottom bit set, which in turn would mean that the
18505 address computation performed by the third instruction would end
18506 up with the bottom bit set. Since the ARM is capable of unaligned
18507 word loads, the instruction would then load the incorrect address
18508 out of the jump table, and chaos would ensue. */
18509 if (label_is_thumb_function_name
18510 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18511 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18513 /* When the address of a Thumb function is taken the bottom
18514 bit of that address should be set. This will allow
18515 interworking between Arm and Thumb functions to work
18518 THUMB_SET_FUNC (sym
, 1);
18520 label_is_thumb_function_name
= FALSE
;
18523 dwarf2_emit_label (sym
);
18527 arm_data_in_code (void)
18529 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18531 *input_line_pointer
= '/';
18532 input_line_pointer
+= 5;
18533 *input_line_pointer
= 0;
18541 arm_canonicalize_symbol_name (char * name
)
18545 if (thumb_mode
&& (len
= strlen (name
)) > 5
18546 && streq (name
+ len
- 5, "/data"))
18547 *(name
+ len
- 5) = 0;
18552 /* Table of all register names defined by default. The user can
18553 define additional names with .req. Note that all register names
18554 should appear in both upper and lowercase variants. Some registers
18555 also have mixed-case names. */
18557 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18558 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18559 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18560 #define REGSET(p,t) \
18561 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18562 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18563 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18564 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18565 #define REGSETH(p,t) \
18566 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18567 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18568 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18569 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18570 #define REGSET2(p,t) \
18571 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18572 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18573 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18574 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18575 #define SPLRBANK(base,bank,t) \
18576 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18577 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18578 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18579 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18580 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18581 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18583 static const struct reg_entry reg_names
[] =
18585 /* ARM integer registers. */
18586 REGSET(r
, RN
), REGSET(R
, RN
),
18588 /* ATPCS synonyms. */
18589 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18590 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18591 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18593 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18594 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18595 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18597 /* Well-known aliases. */
18598 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18599 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18601 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18602 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18604 /* Coprocessor numbers. */
18605 REGSET(p
, CP
), REGSET(P
, CP
),
18607 /* Coprocessor register numbers. The "cr" variants are for backward
18609 REGSET(c
, CN
), REGSET(C
, CN
),
18610 REGSET(cr
, CN
), REGSET(CR
, CN
),
18612 /* ARM banked registers. */
18613 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18614 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18615 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18616 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18617 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18618 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18619 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18621 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18622 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18623 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18624 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18625 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18626 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18627 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18628 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18630 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18631 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18632 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18633 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18634 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18635 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18636 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18637 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18638 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18640 /* FPA registers. */
18641 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18642 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18644 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18645 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18647 /* VFP SP registers. */
18648 REGSET(s
,VFS
), REGSET(S
,VFS
),
18649 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18651 /* VFP DP Registers. */
18652 REGSET(d
,VFD
), REGSET(D
,VFD
),
18653 /* Extra Neon DP registers. */
18654 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18656 /* Neon QP registers. */
18657 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18659 /* VFP control registers. */
18660 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18661 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18662 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18663 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18664 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18665 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18667 /* Maverick DSP coprocessor registers. */
18668 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18669 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18671 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18672 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18673 REGDEF(dspsc
,0,DSPSC
),
18675 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18676 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18677 REGDEF(DSPSC
,0,DSPSC
),
18679 /* iWMMXt data registers - p0, c0-15. */
18680 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18682 /* iWMMXt control registers - p1, c0-3. */
18683 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18684 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18685 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18686 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18688 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18689 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18690 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18691 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18692 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18694 /* XScale accumulator registers. */
18695 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18701 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18702 within psr_required_here. */
18703 static const struct asm_psr psrs
[] =
18705 /* Backward compatibility notation. Note that "all" is no longer
18706 truly all possible PSR bits. */
18707 {"all", PSR_c
| PSR_f
},
18711 /* Individual flags. */
18717 /* Combinations of flags. */
18718 {"fs", PSR_f
| PSR_s
},
18719 {"fx", PSR_f
| PSR_x
},
18720 {"fc", PSR_f
| PSR_c
},
18721 {"sf", PSR_s
| PSR_f
},
18722 {"sx", PSR_s
| PSR_x
},
18723 {"sc", PSR_s
| PSR_c
},
18724 {"xf", PSR_x
| PSR_f
},
18725 {"xs", PSR_x
| PSR_s
},
18726 {"xc", PSR_x
| PSR_c
},
18727 {"cf", PSR_c
| PSR_f
},
18728 {"cs", PSR_c
| PSR_s
},
18729 {"cx", PSR_c
| PSR_x
},
18730 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18731 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18732 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18733 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18734 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18735 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18736 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18737 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18738 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18739 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18740 {"scf", PSR_s
| PSR_c
| PSR_f
},
18741 {"scx", PSR_s
| PSR_c
| PSR_x
},
18742 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18743 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18744 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18745 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18746 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18747 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18748 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18749 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18750 {"csf", PSR_c
| PSR_s
| PSR_f
},
18751 {"csx", PSR_c
| PSR_s
| PSR_x
},
18752 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18753 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18754 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18755 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18756 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18757 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18758 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18759 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18760 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18761 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18762 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18763 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18764 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18765 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18766 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18767 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18768 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18769 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18770 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18771 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18772 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18773 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18774 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18775 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18776 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18777 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18780 /* Table of V7M psr names. */
18781 static const struct asm_psr v7m_psrs
[] =
18783 {"apsr", 0 }, {"APSR", 0 },
18784 {"iapsr", 1 }, {"IAPSR", 1 },
18785 {"eapsr", 2 }, {"EAPSR", 2 },
18786 {"psr", 3 }, {"PSR", 3 },
18787 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18788 {"ipsr", 5 }, {"IPSR", 5 },
18789 {"epsr", 6 }, {"EPSR", 6 },
18790 {"iepsr", 7 }, {"IEPSR", 7 },
18791 {"msp", 8 }, {"MSP", 8 }, {"msp_s", 8 }, {"MSP_S", 8 },
18792 {"psp", 9 }, {"PSP", 9 }, {"psp_s", 9 }, {"PSP_S", 9 },
18793 {"primask", 16}, {"PRIMASK", 16},
18794 {"basepri", 17}, {"BASEPRI", 17},
18795 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18796 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18797 {"faultmask", 19}, {"FAULTMASK", 19},
18798 {"control", 20}, {"CONTROL", 20},
18799 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18800 {"psp_ns", 0x89}, {"PSP_NS", 0x89}
18803 /* Table of all shift-in-operand names. */
18804 static const struct asm_shift_name shift_names
[] =
18806 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18807 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18808 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18809 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18810 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18811 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18814 /* Table of all explicit relocation names. */
18816 static struct reloc_entry reloc_names
[] =
18818 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18819 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18820 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18821 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18822 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18823 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18824 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18825 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18826 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18827 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18828 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18829 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18830 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18831 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18832 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18833 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18834 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18835 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18839 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18840 static const struct asm_cond conds
[] =
18844 {"cs", 0x2}, {"hs", 0x2},
18845 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18859 #define UL_BARRIER(L,U,CODE,FEAT) \
18860 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18861 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18863 static struct asm_barrier_opt barrier_opt_names
[] =
18865 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18866 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18867 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18868 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18869 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18870 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18871 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18872 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18873 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18874 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18875 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18876 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18877 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18878 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18879 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18880 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18885 /* Table of ARM-format instructions. */
18887 /* Macros for gluing together operand strings. N.B. In all cases
18888 other than OPS0, the trailing OP_stop comes from default
18889 zero-initialization of the unspecified elements of the array. */
18890 #define OPS0() { OP_stop, }
18891 #define OPS1(a) { OP_##a, }
18892 #define OPS2(a,b) { OP_##a,OP_##b, }
18893 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18894 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18895 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18896 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18898 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18899 This is useful when mixing operands for ARM and THUMB, i.e. using the
18900 MIX_ARM_THUMB_OPERANDS macro.
18901 In order to use these macros, prefix the number of operands with _
18903 #define OPS_1(a) { a, }
18904 #define OPS_2(a,b) { a,b, }
18905 #define OPS_3(a,b,c) { a,b,c, }
18906 #define OPS_4(a,b,c,d) { a,b,c,d, }
18907 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18908 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18910 /* These macros abstract out the exact format of the mnemonic table and
18911 save some repeated characters. */
18913 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18914 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18915 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18916 THUMB_VARIANT, do_##ae, do_##te }
18918 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18919 a T_MNEM_xyz enumerator. */
18920 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18921 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18922 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18923 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18925 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18926 infix after the third character. */
18927 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18928 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18929 THUMB_VARIANT, do_##ae, do_##te }
18930 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18931 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18932 THUMB_VARIANT, do_##ae, do_##te }
18933 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18934 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18935 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18936 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18937 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18938 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18939 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18940 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18942 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18943 field is still 0xE. Many of the Thumb variants can be executed
18944 conditionally, so this is checked separately. */
18945 #define TUE(mnem, op, top, nops, ops, ae, te) \
18946 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18947 THUMB_VARIANT, do_##ae, do_##te }
18949 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18950 Used by mnemonics that have very minimal differences in the encoding for
18951 ARM and Thumb variants and can be handled in a common function. */
18952 #define TUEc(mnem, op, top, nops, ops, en) \
18953 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18954 THUMB_VARIANT, do_##en, do_##en }
18956 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18957 condition code field. */
18958 #define TUF(mnem, op, top, nops, ops, ae, te) \
18959 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18960 THUMB_VARIANT, do_##ae, do_##te }
18962 /* ARM-only variants of all the above. */
18963 #define CE(mnem, op, nops, ops, ae) \
18964 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18966 #define C3(mnem, op, nops, ops, ae) \
18967 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18969 /* Legacy mnemonics that always have conditional infix after the third
18971 #define CL(mnem, op, nops, ops, ae) \
18972 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18973 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18975 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18976 #define cCE(mnem, op, nops, ops, ae) \
18977 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18979 /* Legacy coprocessor instructions where conditional infix and conditional
18980 suffix are ambiguous. For consistency this includes all FPA instructions,
18981 not just the potentially ambiguous ones. */
18982 #define cCL(mnem, op, nops, ops, ae) \
18983 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18984 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18986 /* Coprocessor, takes either a suffix or a position-3 infix
18987 (for an FPA corner case). */
18988 #define C3E(mnem, op, nops, ops, ae) \
18989 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18990 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18992 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18993 { m1 #m2 m3, OPS##nops ops, \
18994 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18995 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18997 #define CM(m1, m2, op, nops, ops, ae) \
18998 xCM_ (m1, , m2, op, nops, ops, ae), \
18999 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19000 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19001 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19002 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19003 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19004 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19005 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19006 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19007 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19008 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19009 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19010 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19011 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19012 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19013 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19014 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19015 xCM_ (m1, le, m2, op, nops, ops, ae), \
19016 xCM_ (m1, al, m2, op, nops, ops, ae)
19018 #define UE(mnem, op, nops, ops, ae) \
19019 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19021 #define UF(mnem, op, nops, ops, ae) \
19022 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19024 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19025 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19026 use the same encoding function for each. */
19027 #define NUF(mnem, op, nops, ops, enc) \
19028 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19029 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19031 /* Neon data processing, version which indirects through neon_enc_tab for
19032 the various overloaded versions of opcodes. */
19033 #define nUF(mnem, op, nops, ops, enc) \
19034 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19035 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19037 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19039 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19040 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19041 THUMB_VARIANT, do_##enc, do_##enc }
19043 #define NCE(mnem, op, nops, ops, enc) \
19044 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19046 #define NCEF(mnem, op, nops, ops, enc) \
19047 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19049 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19050 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19051 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19052 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19054 #define nCE(mnem, op, nops, ops, enc) \
19055 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19057 #define nCEF(mnem, op, nops, ops, enc) \
19058 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19062 static const struct asm_opcode insns
[] =
19064 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19065 #define THUMB_VARIANT & arm_ext_v4t
19066 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19067 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19068 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19069 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19070 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19071 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19072 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19073 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19074 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19075 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19076 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19077 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19078 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19079 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19080 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19081 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19083 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19084 for setting PSR flag bits. They are obsolete in V6 and do not
19085 have Thumb equivalents. */
19086 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19087 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19088 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19089 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19090 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19091 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19092 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19093 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19094 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19096 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19097 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19098 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19099 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19101 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19102 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19103 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19105 OP_ADDRGLDR
),ldst
, t_ldst
),
19106 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19108 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19109 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19110 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19111 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19112 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19113 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19115 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19116 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19117 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19118 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19121 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19122 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19123 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19124 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19126 /* Thumb-compatibility pseudo ops. */
19127 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19128 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19129 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19130 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19131 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19132 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19133 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19134 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19135 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19136 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19137 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19138 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19140 /* These may simplify to neg. */
19141 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19142 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19144 #undef THUMB_VARIANT
19145 #define THUMB_VARIANT & arm_ext_v6
19147 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19149 /* V1 instructions with no Thumb analogue prior to V6T2. */
19150 #undef THUMB_VARIANT
19151 #define THUMB_VARIANT & arm_ext_v6t2
19153 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19154 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19155 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19157 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19158 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19159 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19160 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19162 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19163 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19165 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19166 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19168 /* V1 instructions with no Thumb analogue at all. */
19169 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19170 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19172 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19173 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19174 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19175 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19176 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19177 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19178 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19179 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19182 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19183 #undef THUMB_VARIANT
19184 #define THUMB_VARIANT & arm_ext_v4t
19186 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19187 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19189 #undef THUMB_VARIANT
19190 #define THUMB_VARIANT & arm_ext_v6t2
19192 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19193 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19195 /* Generic coprocessor instructions. */
19196 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19197 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19198 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19199 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19200 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19201 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19202 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19205 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19207 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19208 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19211 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19212 #undef THUMB_VARIANT
19213 #define THUMB_VARIANT & arm_ext_msr
19215 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19216 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19219 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19220 #undef THUMB_VARIANT
19221 #define THUMB_VARIANT & arm_ext_v6t2
19223 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19224 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19225 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19226 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19227 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19228 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19229 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19230 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19233 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19234 #undef THUMB_VARIANT
19235 #define THUMB_VARIANT & arm_ext_v4t
19237 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19238 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19239 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19240 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19241 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19242 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19245 #define ARM_VARIANT & arm_ext_v4t_5
19247 /* ARM Architecture 4T. */
19248 /* Note: bx (and blx) are required on V5, even if the processor does
19249 not support Thumb. */
19250 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19253 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19254 #undef THUMB_VARIANT
19255 #define THUMB_VARIANT & arm_ext_v5t
19257 /* Note: blx has 2 variants; the .value coded here is for
19258 BLX(2). Only this variant has conditional execution. */
19259 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19260 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19262 #undef THUMB_VARIANT
19263 #define THUMB_VARIANT & arm_ext_v6t2
19265 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19266 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19267 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19268 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19269 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19270 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19271 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19272 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19275 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19276 #undef THUMB_VARIANT
19277 #define THUMB_VARIANT & arm_ext_v5exp
19279 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19280 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19281 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19282 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19284 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19285 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19287 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19288 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19289 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19290 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19292 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19293 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19294 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19295 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19297 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19298 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19300 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19301 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19302 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19303 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19306 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19307 #undef THUMB_VARIANT
19308 #define THUMB_VARIANT & arm_ext_v6t2
19310 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19311 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19313 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19314 ADDRGLDRS
), ldrd
, t_ldstd
),
19316 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19317 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19320 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19322 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19325 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19326 #undef THUMB_VARIANT
19327 #define THUMB_VARIANT & arm_ext_v6
19329 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19330 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19331 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19332 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19333 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19334 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19335 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19336 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19337 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19338 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19340 #undef THUMB_VARIANT
19341 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19343 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19344 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19346 #undef THUMB_VARIANT
19347 #define THUMB_VARIANT & arm_ext_v6t2
19349 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19350 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19352 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19353 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19355 /* ARM V6 not included in V7M. */
19356 #undef THUMB_VARIANT
19357 #define THUMB_VARIANT & arm_ext_v6_notm
19358 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19359 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19360 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19361 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19362 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19363 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19364 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19365 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19366 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19367 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19368 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19369 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19370 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19371 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19372 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19373 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19374 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19375 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19376 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19378 /* ARM V6 not included in V7M (eg. integer SIMD). */
19379 #undef THUMB_VARIANT
19380 #define THUMB_VARIANT & arm_ext_v6_dsp
19381 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19382 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19383 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19384 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19385 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19386 /* Old name for QASX. */
19387 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19388 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19389 /* Old name for QSAX. */
19390 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19391 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19392 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19393 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19394 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19395 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19396 /* Old name for SASX. */
19397 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19398 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19399 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19400 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19401 /* Old name for SHASX. */
19402 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19403 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19404 /* Old name for SHSAX. */
19405 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19406 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19407 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19408 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19409 /* Old name for SSAX. */
19410 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19411 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19412 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19413 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19414 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19415 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19416 /* Old name for UASX. */
19417 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19418 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19419 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19420 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19421 /* Old name for UHASX. */
19422 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19423 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19424 /* Old name for UHSAX. */
19425 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19426 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19427 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19428 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19429 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19430 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19431 /* Old name for UQASX. */
19432 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19433 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19434 /* Old name for UQSAX. */
19435 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19436 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19437 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19438 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19439 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19440 /* Old name for USAX. */
19441 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19442 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19443 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19444 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19445 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19446 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19447 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19448 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19449 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19450 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19451 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19452 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19453 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19454 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19455 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19456 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19457 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19458 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19459 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19460 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19461 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19462 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19463 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19464 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19465 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19466 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19467 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19468 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19469 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19470 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19471 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19472 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19473 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19474 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19477 #define ARM_VARIANT & arm_ext_v6k
19478 #undef THUMB_VARIANT
19479 #define THUMB_VARIANT & arm_ext_v6k
19481 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19482 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19483 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19484 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19486 #undef THUMB_VARIANT
19487 #define THUMB_VARIANT & arm_ext_v6_notm
19488 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19490 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19491 RRnpcb
), strexd
, t_strexd
),
19493 #undef THUMB_VARIANT
19494 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19495 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19497 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19499 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19501 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19503 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19506 #define ARM_VARIANT & arm_ext_sec
19507 #undef THUMB_VARIANT
19508 #define THUMB_VARIANT & arm_ext_sec
19510 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19513 #define ARM_VARIANT & arm_ext_virt
19514 #undef THUMB_VARIANT
19515 #define THUMB_VARIANT & arm_ext_virt
19517 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19518 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19521 #define ARM_VARIANT & arm_ext_pan
19522 #undef THUMB_VARIANT
19523 #define THUMB_VARIANT & arm_ext_pan
19525 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19528 #define ARM_VARIANT & arm_ext_v6t2
19529 #undef THUMB_VARIANT
19530 #define THUMB_VARIANT & arm_ext_v6t2
19532 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19533 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19534 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19535 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19537 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19538 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19540 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19541 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19542 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19543 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19545 #undef THUMB_VARIANT
19546 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19547 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19548 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19550 /* Thumb-only instructions. */
19552 #define ARM_VARIANT NULL
19553 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19554 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19556 /* ARM does not really have an IT instruction, so always allow it.
19557 The opcode is copied from Thumb in order to allow warnings in
19558 -mimplicit-it=[never | arm] modes. */
19560 #define ARM_VARIANT & arm_ext_v1
19561 #undef THUMB_VARIANT
19562 #define THUMB_VARIANT & arm_ext_v6t2
19564 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19565 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19566 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19567 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19568 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19569 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19570 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19571 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19572 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19573 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19574 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19575 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19576 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19577 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19578 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19579 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19580 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19581 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19583 /* Thumb2 only instructions. */
19585 #define ARM_VARIANT NULL
19587 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19588 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19589 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19590 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19591 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19592 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19594 /* Hardware division instructions. */
19596 #define ARM_VARIANT & arm_ext_adiv
19597 #undef THUMB_VARIANT
19598 #define THUMB_VARIANT & arm_ext_div
19600 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19601 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19603 /* ARM V6M/V7 instructions. */
19605 #define ARM_VARIANT & arm_ext_barrier
19606 #undef THUMB_VARIANT
19607 #define THUMB_VARIANT & arm_ext_barrier
19609 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19610 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19611 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19613 /* ARM V7 instructions. */
19615 #define ARM_VARIANT & arm_ext_v7
19616 #undef THUMB_VARIANT
19617 #define THUMB_VARIANT & arm_ext_v7
19619 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19620 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19623 #define ARM_VARIANT & arm_ext_mp
19624 #undef THUMB_VARIANT
19625 #define THUMB_VARIANT & arm_ext_mp
19627 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19629 /* AArchv8 instructions. */
19631 #define ARM_VARIANT & arm_ext_v8
19633 /* Instructions shared between armv8-a and armv8-m. */
19634 #undef THUMB_VARIANT
19635 #define THUMB_VARIANT & arm_ext_atomics
19637 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19638 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19639 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19640 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19641 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19642 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19643 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19644 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19645 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19646 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19648 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19650 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19652 #undef THUMB_VARIANT
19653 #define THUMB_VARIANT & arm_ext_v8
19655 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19656 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19657 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19659 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19661 /* ARMv8 T32 only. */
19663 #define ARM_VARIANT NULL
19664 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19665 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19666 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19668 /* FP for ARMv8. */
19670 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19671 #undef THUMB_VARIANT
19672 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19674 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19675 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19676 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19677 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19678 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19679 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19680 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19681 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19682 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19683 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19684 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19685 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19686 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19687 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19688 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19689 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19690 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19692 /* Crypto v1 extensions. */
19694 #define ARM_VARIANT & fpu_crypto_ext_armv8
19695 #undef THUMB_VARIANT
19696 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19698 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19699 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19700 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19701 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19702 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19703 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19704 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19705 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19706 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19707 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19708 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19709 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19710 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19711 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19714 #define ARM_VARIANT & crc_ext_armv8
19715 #undef THUMB_VARIANT
19716 #define THUMB_VARIANT & crc_ext_armv8
19717 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19718 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19719 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19720 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19721 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19722 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19724 /* ARMv8.2 RAS extension. */
19726 #define ARM_VARIANT & arm_ext_ras
19727 #undef THUMB_VARIANT
19728 #define THUMB_VARIANT & arm_ext_ras
19729 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19732 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19733 #undef THUMB_VARIANT
19734 #define THUMB_VARIANT NULL
19736 cCE("wfs", e200110
, 1, (RR
), rd
),
19737 cCE("rfs", e300110
, 1, (RR
), rd
),
19738 cCE("wfc", e400110
, 1, (RR
), rd
),
19739 cCE("rfc", e500110
, 1, (RR
), rd
),
19741 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19742 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19743 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19744 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19746 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19747 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19748 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19749 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19751 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19752 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19753 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19754 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19755 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19756 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19757 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19758 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19759 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19760 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19761 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19762 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19764 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19765 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19766 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19767 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19768 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19769 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19770 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19771 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19772 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19773 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19774 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19775 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19777 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19778 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19779 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19780 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19781 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19782 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19783 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19784 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19785 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19786 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19787 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19788 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19790 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19791 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19792 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19793 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19794 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19795 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19796 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19797 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19798 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19799 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19800 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19801 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19803 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19804 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19805 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19806 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19807 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19808 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19809 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19810 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19811 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19812 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19813 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19814 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19816 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19817 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19818 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19819 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19820 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19821 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19822 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19823 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19826 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19827 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19829 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19830 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19831 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19832 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19835 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19839 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19840 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19842 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19843 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19844 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19845 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19848 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19852 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19853 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19855 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19856 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19857 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19858 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19859 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19860 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19861 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19862 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19863 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19864 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19865 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19866 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19868 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19869 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19870 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19871 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19872 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19873 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19874 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19875 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19876 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19877 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19878 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19879 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19881 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19882 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19883 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19884 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19885 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19886 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19887 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19888 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19889 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19890 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19891 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19892 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19894 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19895 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19896 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19897 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19898 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19899 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19900 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19901 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19902 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19903 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19904 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19905 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19907 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19908 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19909 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19913 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19915 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19917 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19920 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19921 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19922 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19926 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19928 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19930 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19933 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19934 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19935 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19936 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19939 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19946 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19948 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19950 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19951 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19952 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19953 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19954 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19955 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19956 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19957 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19959 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19960 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19961 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19962 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19963 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19964 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19965 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19966 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19967 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19968 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19969 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19970 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19972 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19973 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19974 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19975 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19976 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19977 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19978 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19979 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19980 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19981 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19982 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19983 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19985 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19986 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19987 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19988 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19989 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19990 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19991 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19992 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19993 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19994 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19995 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19996 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19998 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19999 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20000 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20001 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20002 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20003 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20004 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20005 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20006 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20007 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20008 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20009 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20011 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20012 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20013 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20014 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20015 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20016 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20017 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20018 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20019 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20020 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20021 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20022 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20024 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20025 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20026 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20027 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20028 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20029 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20030 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20031 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20032 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20033 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20034 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20035 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20037 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20038 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20039 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20040 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20041 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20042 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20043 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20044 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20045 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20046 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20047 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20048 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20050 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20051 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20052 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20053 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20054 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20055 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20056 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20057 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20058 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20059 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20060 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20061 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20063 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20064 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20065 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20066 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20067 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20068 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20069 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20070 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20071 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20072 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20073 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20074 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20076 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20077 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20078 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20079 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20080 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20081 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20082 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20083 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20084 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20085 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20086 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20087 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20089 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20090 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20091 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20092 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20093 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20094 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20095 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20096 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20097 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20098 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20099 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20100 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20102 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20103 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20104 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20105 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20106 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20107 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20108 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20109 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20110 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20111 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20112 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20113 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20115 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20116 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20117 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20118 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20119 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20120 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20121 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20122 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20123 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20124 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20125 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20126 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20128 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20129 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20130 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20131 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20133 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20134 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20135 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20136 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20137 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20138 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20139 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20140 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20141 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20142 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20143 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20144 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20146 /* The implementation of the FIX instruction is broken on some
20147 assemblers, in that it accepts a precision specifier as well as a
20148 rounding specifier, despite the fact that this is meaningless.
20149 To be more compatible, we accept it as well, though of course it
20150 does not set any bits. */
20151 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20152 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20153 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20154 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20155 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20156 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20157 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20158 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20159 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20160 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20161 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20162 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20163 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20165 /* Instructions that were new with the real FPA, call them V2. */
20167 #define ARM_VARIANT & fpu_fpa_ext_v2
20169 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20170 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20171 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20172 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20173 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20174 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20177 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20179 /* Moves and type conversions. */
20180 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20181 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20182 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20183 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20184 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20185 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20186 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20187 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20188 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20189 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20190 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20191 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20192 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20193 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20195 /* Memory operations. */
20196 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20197 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20198 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20199 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20200 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20201 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20202 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20203 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20204 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20205 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20206 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20207 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20208 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20209 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20210 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20211 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20212 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20213 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20215 /* Monadic operations. */
20216 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20217 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20218 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20220 /* Dyadic operations. */
20221 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20222 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20223 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20224 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20225 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20226 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20227 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20228 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20229 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20232 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20233 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20234 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20235 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20237 /* Double precision load/store are still present on single precision
20238 implementations. */
20239 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20240 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20241 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20242 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20243 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20244 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20245 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20246 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20247 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20248 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20251 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20253 /* Moves and type conversions. */
20254 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20255 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20256 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20257 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20258 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20259 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20260 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20261 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20262 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20263 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20264 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20265 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20266 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20268 /* Monadic operations. */
20269 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20270 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20271 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20273 /* Dyadic operations. */
20274 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20275 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20276 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20277 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20278 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20279 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20280 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20281 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20282 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20285 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20286 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20287 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20288 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20291 #define ARM_VARIANT & fpu_vfp_ext_v2
20293 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20294 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20295 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20296 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20298 /* Instructions which may belong to either the Neon or VFP instruction sets.
20299 Individual encoder functions perform additional architecture checks. */
20301 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20302 #undef THUMB_VARIANT
20303 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20305 /* These mnemonics are unique to VFP. */
20306 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20307 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20308 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20309 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20310 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20311 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20312 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20313 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20314 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20315 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20317 /* Mnemonics shared by Neon and VFP. */
20318 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20319 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20320 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20322 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20323 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20325 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20326 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20328 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20329 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20330 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20331 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20332 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20333 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20334 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20335 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20337 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20338 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20339 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20340 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20343 /* NOTE: All VMOV encoding is special-cased! */
20344 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20345 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20348 #define ARM_VARIANT & arm_ext_fp16
20349 #undef THUMB_VARIANT
20350 #define THUMB_VARIANT & arm_ext_fp16
20351 /* New instructions added from v8.2, allowing the extraction and insertion of
20352 the upper 16 bits of a 32-bit vector register. */
20353 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20354 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20356 #undef THUMB_VARIANT
20357 #define THUMB_VARIANT & fpu_neon_ext_v1
20359 #define ARM_VARIANT & fpu_neon_ext_v1
20361 /* Data processing with three registers of the same length. */
20362 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20363 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20364 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20365 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20366 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20367 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20368 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20369 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20370 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20371 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20372 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20373 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20374 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20375 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20376 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20377 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20378 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20379 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20380 /* If not immediate, fall back to neon_dyadic_i64_su.
20381 shl_imm should accept I8 I16 I32 I64,
20382 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20383 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20384 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20385 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20386 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20387 /* Logic ops, types optional & ignored. */
20388 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20389 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20390 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20391 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20392 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20393 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20394 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20395 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20396 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20397 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20398 /* Bitfield ops, untyped. */
20399 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20400 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20401 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20402 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20403 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20404 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20405 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20406 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20407 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20408 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20409 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20410 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20411 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20412 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20413 back to neon_dyadic_if_su. */
20414 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20415 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20416 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20417 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20418 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20419 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20420 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20421 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20422 /* Comparison. Type I8 I16 I32 F32. */
20423 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20424 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20425 /* As above, D registers only. */
20426 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20427 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20428 /* Int and float variants, signedness unimportant. */
20429 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20430 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20431 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20432 /* Add/sub take types I8 I16 I32 I64 F32. */
20433 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20434 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20435 /* vtst takes sizes 8, 16, 32. */
20436 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20437 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20438 /* VMUL takes I8 I16 I32 F32 P8. */
20439 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20440 /* VQD{R}MULH takes S16 S32. */
20441 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20442 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20443 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20444 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20445 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20446 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20447 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20448 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20449 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20450 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20451 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20452 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20453 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20454 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20455 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20456 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20457 /* ARM v8.1 extension. */
20458 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20459 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20460 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20461 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20463 /* Two address, int/float. Types S8 S16 S32 F32. */
20464 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20465 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20467 /* Data processing with two registers and a shift amount. */
20468 /* Right shifts, and variants with rounding.
20469 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20470 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20471 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20472 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20473 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20474 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20475 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20476 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20477 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20478 /* Shift and insert. Sizes accepted 8 16 32 64. */
20479 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20480 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20481 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20482 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20483 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20484 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20485 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20486 /* Right shift immediate, saturating & narrowing, with rounding variants.
20487 Types accepted S16 S32 S64 U16 U32 U64. */
20488 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20489 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20490 /* As above, unsigned. Types accepted S16 S32 S64. */
20491 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20492 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20493 /* Right shift narrowing. Types accepted I16 I32 I64. */
20494 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20495 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20496 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20497 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20498 /* CVT with optional immediate for fixed-point variant. */
20499 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20501 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20502 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20504 /* Data processing, three registers of different lengths. */
20505 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20506 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20507 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20508 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20509 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20510 /* If not scalar, fall back to neon_dyadic_long.
20511 Vector types as above, scalar types S16 S32 U16 U32. */
20512 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20513 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20514 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20515 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20516 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20517 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20518 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20519 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20520 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20521 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20522 /* Saturating doubling multiplies. Types S16 S32. */
20523 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20524 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20525 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20526 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20527 S16 S32 U16 U32. */
20528 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20530 /* Extract. Size 8. */
20531 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20532 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20534 /* Two registers, miscellaneous. */
20535 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20536 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20537 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20538 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20539 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20540 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20541 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20542 /* Vector replicate. Sizes 8 16 32. */
20543 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20544 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20545 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20546 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20547 /* VMOVN. Types I16 I32 I64. */
20548 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20549 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20550 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20551 /* VQMOVUN. Types S16 S32 S64. */
20552 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20553 /* VZIP / VUZP. Sizes 8 16 32. */
20554 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20555 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20556 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20557 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20558 /* VQABS / VQNEG. Types S8 S16 S32. */
20559 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20560 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20561 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20562 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20563 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20564 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20565 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20566 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20567 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20568 /* Reciprocal estimates. Types U32 F16 F32. */
20569 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20570 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20571 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20572 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20573 /* VCLS. Types S8 S16 S32. */
20574 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20575 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20576 /* VCLZ. Types I8 I16 I32. */
20577 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20578 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20579 /* VCNT. Size 8. */
20580 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20581 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20582 /* Two address, untyped. */
20583 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20584 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20585 /* VTRN. Sizes 8 16 32. */
20586 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20587 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20589 /* Table lookup. Size 8. */
20590 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20591 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20593 #undef THUMB_VARIANT
20594 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20596 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20598 /* Neon element/structure load/store. */
20599 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20600 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20601 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20602 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20603 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20604 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20605 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20606 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20608 #undef THUMB_VARIANT
20609 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20611 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20612 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20613 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20614 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20615 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20616 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20617 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20618 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20619 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20620 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20622 #undef THUMB_VARIANT
20623 #define THUMB_VARIANT & fpu_vfp_ext_v3
20625 #define ARM_VARIANT & fpu_vfp_ext_v3
20627 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20628 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20629 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20630 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20631 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20632 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20633 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20634 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20635 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20638 #define ARM_VARIANT & fpu_vfp_ext_fma
20639 #undef THUMB_VARIANT
20640 #define THUMB_VARIANT & fpu_vfp_ext_fma
20641 /* Mnemonics shared by Neon and VFP. These are included in the
20642 VFP FMA variant; NEON and VFP FMA always includes the NEON
20643 FMA instructions. */
20644 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20645 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20646 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20647 the v form should always be used. */
20648 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20649 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20650 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20651 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20652 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20653 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20655 #undef THUMB_VARIANT
20657 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20659 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20660 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20661 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20662 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20663 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20664 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20665 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20666 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20669 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20671 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20672 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20673 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20674 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20675 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20676 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20677 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20678 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20679 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20680 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20681 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20682 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20683 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20684 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20685 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20686 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20687 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20688 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20689 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20690 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20691 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20692 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20693 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20694 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20695 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20696 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20697 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20698 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20699 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20700 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20701 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20702 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20703 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20704 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20705 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20706 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20707 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20708 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20709 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20710 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20711 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20712 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20713 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20714 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20715 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20716 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20717 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20718 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20719 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20720 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20721 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20722 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20723 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20724 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20725 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20726 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20727 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20728 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20729 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20730 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20731 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20732 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20733 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20734 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20735 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20736 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20737 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20738 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20739 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20740 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20741 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20742 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20743 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20744 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20745 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20746 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20747 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20748 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20749 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20750 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20751 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20752 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20753 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20754 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20755 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20756 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20757 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20758 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20759 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20760 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20761 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20762 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20763 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20764 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20765 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20766 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20767 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20768 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20769 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20770 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20771 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20772 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20773 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20774 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20775 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20776 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20777 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20778 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20779 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20780 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20781 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20782 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20783 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20784 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20785 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20786 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20787 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20788 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20789 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20790 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20791 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20792 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20793 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20794 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20795 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20796 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20797 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20798 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20799 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20800 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20801 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20802 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20803 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20804 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20805 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20806 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20807 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20808 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20809 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20810 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20811 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20812 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20813 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20814 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20815 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20816 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20817 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20818 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20819 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20820 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20821 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20822 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20823 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20824 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20825 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20826 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20827 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20828 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20829 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20830 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20831 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20832 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20835 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20837 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20838 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20839 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20840 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20841 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20842 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20843 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20844 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20845 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20846 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20847 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20848 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20849 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20850 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20851 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20852 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20853 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20854 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20855 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20856 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20857 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20858 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20859 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20860 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20861 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20862 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20863 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20864 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20865 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20866 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20867 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20868 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20869 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20870 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20871 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20872 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20873 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20874 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20875 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20876 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20877 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20878 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20879 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20880 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20881 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20882 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20883 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20884 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20885 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20886 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20887 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20888 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20889 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20890 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20891 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20892 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20893 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20896 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20898 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20899 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20900 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20901 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20902 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20903 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20904 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20905 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20906 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20907 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20908 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20909 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20910 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20911 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20912 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20913 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20914 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20915 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20916 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20917 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20918 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20919 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20920 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20921 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20922 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20923 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20924 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20925 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20926 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20927 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20928 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20929 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20930 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20931 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20932 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20933 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20934 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20935 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20936 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20937 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20938 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20939 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20940 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20941 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20942 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20943 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20944 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20945 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20946 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20947 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20948 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20949 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20950 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20951 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20952 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20953 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20954 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20955 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20956 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20957 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20958 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20959 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20960 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20961 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20962 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20963 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20964 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20965 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20966 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20967 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20968 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20969 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20970 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20971 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20972 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20973 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20975 /* ARMv8-M instructions. */
20977 #define ARM_VARIANT NULL
20978 #undef THUMB_VARIANT
20979 #define THUMB_VARIANT & arm_ext_v8m
20980 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
20981 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
20982 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
20983 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
20984 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
20985 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
20986 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
20988 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
20989 instructions behave as nop if no VFP is present. */
20990 #undef THUMB_VARIANT
20991 #define THUMB_VARIANT & arm_ext_v8m_main
20992 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
20993 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
20996 #undef THUMB_VARIANT
21022 /* MD interface: bits in the object file. */
21024 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21025 for use in the a.out file, and stores them in the array pointed to by buf.
21026 This knows about the endian-ness of the target machine and does
21027 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21028 2 (short) and 4 (long) Floating numbers are put out as a series of
21029 LITTLENUMS (shorts, here at least). */
21032 md_number_to_chars (char * buf
, valueT val
, int n
)
21034 if (target_big_endian
)
21035 number_to_chars_bigendian (buf
, val
, n
);
21037 number_to_chars_littleendian (buf
, val
, n
);
21041 md_chars_to_number (char * buf
, int n
)
21044 unsigned char * where
= (unsigned char *) buf
;
21046 if (target_big_endian
)
21051 result
|= (*where
++ & 255);
21059 result
|= (where
[n
] & 255);
21066 /* MD interface: Sections. */
21068 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21069 that an rs_machine_dependent frag may reach. */
21072 arm_frag_max_var (fragS
*fragp
)
21074 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21075 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21077 Note that we generate relaxable instructions even for cases that don't
21078 really need it, like an immediate that's a trivial constant. So we're
21079 overestimating the instruction size for some of those cases. Rather
21080 than putting more intelligence here, it would probably be better to
21081 avoid generating a relaxation frag in the first place when it can be
21082 determined up front that a short instruction will suffice. */
21084 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21088 /* Estimate the size of a frag before relaxing. Assume everything fits in
21092 md_estimate_size_before_relax (fragS
* fragp
,
21093 segT segtype ATTRIBUTE_UNUSED
)
21099 /* Convert a machine dependent frag. */
21102 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21104 unsigned long insn
;
21105 unsigned long old_op
;
21113 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21115 old_op
= bfd_get_16(abfd
, buf
);
21116 if (fragp
->fr_symbol
)
21118 exp
.X_op
= O_symbol
;
21119 exp
.X_add_symbol
= fragp
->fr_symbol
;
21123 exp
.X_op
= O_constant
;
21125 exp
.X_add_number
= fragp
->fr_offset
;
21126 opcode
= fragp
->fr_subtype
;
21129 case T_MNEM_ldr_pc
:
21130 case T_MNEM_ldr_pc2
:
21131 case T_MNEM_ldr_sp
:
21132 case T_MNEM_str_sp
:
21139 if (fragp
->fr_var
== 4)
21141 insn
= THUMB_OP32 (opcode
);
21142 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21144 insn
|= (old_op
& 0x700) << 4;
21148 insn
|= (old_op
& 7) << 12;
21149 insn
|= (old_op
& 0x38) << 13;
21151 insn
|= 0x00000c00;
21152 put_thumb32_insn (buf
, insn
);
21153 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21157 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21159 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21162 if (fragp
->fr_var
== 4)
21164 insn
= THUMB_OP32 (opcode
);
21165 insn
|= (old_op
& 0xf0) << 4;
21166 put_thumb32_insn (buf
, insn
);
21167 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21171 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21172 exp
.X_add_number
-= 4;
21180 if (fragp
->fr_var
== 4)
21182 int r0off
= (opcode
== T_MNEM_mov
21183 || opcode
== T_MNEM_movs
) ? 0 : 8;
21184 insn
= THUMB_OP32 (opcode
);
21185 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21186 insn
|= (old_op
& 0x700) << r0off
;
21187 put_thumb32_insn (buf
, insn
);
21188 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21192 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21197 if (fragp
->fr_var
== 4)
21199 insn
= THUMB_OP32(opcode
);
21200 put_thumb32_insn (buf
, insn
);
21201 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21204 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21208 if (fragp
->fr_var
== 4)
21210 insn
= THUMB_OP32(opcode
);
21211 insn
|= (old_op
& 0xf00) << 14;
21212 put_thumb32_insn (buf
, insn
);
21213 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21216 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21219 case T_MNEM_add_sp
:
21220 case T_MNEM_add_pc
:
21221 case T_MNEM_inc_sp
:
21222 case T_MNEM_dec_sp
:
21223 if (fragp
->fr_var
== 4)
21225 /* ??? Choose between add and addw. */
21226 insn
= THUMB_OP32 (opcode
);
21227 insn
|= (old_op
& 0xf0) << 4;
21228 put_thumb32_insn (buf
, insn
);
21229 if (opcode
== T_MNEM_add_pc
)
21230 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21232 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21235 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21243 if (fragp
->fr_var
== 4)
21245 insn
= THUMB_OP32 (opcode
);
21246 insn
|= (old_op
& 0xf0) << 4;
21247 insn
|= (old_op
& 0xf) << 16;
21248 put_thumb32_insn (buf
, insn
);
21249 if (insn
& (1 << 20))
21250 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21252 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21255 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21261 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21262 (enum bfd_reloc_code_real
) reloc_type
);
21263 fixp
->fx_file
= fragp
->fr_file
;
21264 fixp
->fx_line
= fragp
->fr_line
;
21265 fragp
->fr_fix
+= fragp
->fr_var
;
21267 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21268 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21269 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21270 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21273 /* Return the size of a relaxable immediate operand instruction.
21274 SHIFT and SIZE specify the form of the allowable immediate. */
21276 relax_immediate (fragS
*fragp
, int size
, int shift
)
21282 /* ??? Should be able to do better than this. */
21283 if (fragp
->fr_symbol
)
21286 low
= (1 << shift
) - 1;
21287 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21288 offset
= fragp
->fr_offset
;
21289 /* Force misaligned offsets to 32-bit variant. */
21292 if (offset
& ~mask
)
21297 /* Get the address of a symbol during relaxation. */
21299 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21305 sym
= fragp
->fr_symbol
;
21306 sym_frag
= symbol_get_frag (sym
);
21307 know (S_GET_SEGMENT (sym
) != absolute_section
21308 || sym_frag
== &zero_address_frag
);
21309 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21311 /* If frag has yet to be reached on this pass, assume it will
21312 move by STRETCH just as we did. If this is not so, it will
21313 be because some frag between grows, and that will force
21317 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21321 /* Adjust stretch for any alignment frag. Note that if have
21322 been expanding the earlier code, the symbol may be
21323 defined in what appears to be an earlier frag. FIXME:
21324 This doesn't handle the fr_subtype field, which specifies
21325 a maximum number of bytes to skip when doing an
21327 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21329 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21332 stretch
= - ((- stretch
)
21333 & ~ ((1 << (int) f
->fr_offset
) - 1));
21335 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21347 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21350 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21355 /* Assume worst case for symbols not known to be in the same section. */
21356 if (fragp
->fr_symbol
== NULL
21357 || !S_IS_DEFINED (fragp
->fr_symbol
)
21358 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21359 || S_IS_WEAK (fragp
->fr_symbol
))
21362 val
= relaxed_symbol_addr (fragp
, stretch
);
21363 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21364 addr
= (addr
+ 4) & ~3;
21365 /* Force misaligned targets to 32-bit variant. */
21369 if (val
< 0 || val
> 1020)
21374 /* Return the size of a relaxable add/sub immediate instruction. */
21376 relax_addsub (fragS
*fragp
, asection
*sec
)
21381 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21382 op
= bfd_get_16(sec
->owner
, buf
);
21383 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21384 return relax_immediate (fragp
, 8, 0);
21386 return relax_immediate (fragp
, 3, 0);
21389 /* Return TRUE iff the definition of symbol S could be pre-empted
21390 (overridden) at link or load time. */
21392 symbol_preemptible (symbolS
*s
)
21394 /* Weak symbols can always be pre-empted. */
21398 /* Non-global symbols cannot be pre-empted. */
21399 if (! S_IS_EXTERNAL (s
))
21403 /* In ELF, a global symbol can be marked protected, or private. In that
21404 case it can't be pre-empted (other definitions in the same link unit
21405 would violate the ODR). */
21406 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21410 /* Other global symbols might be pre-empted. */
21414 /* Return the size of a relaxable branch instruction. BITS is the
21415 size of the offset field in the narrow instruction. */
21418 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21424 /* Assume worst case for symbols not known to be in the same section. */
21425 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21426 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21427 || S_IS_WEAK (fragp
->fr_symbol
))
21431 /* A branch to a function in ARM state will require interworking. */
21432 if (S_IS_DEFINED (fragp
->fr_symbol
)
21433 && ARM_IS_FUNC (fragp
->fr_symbol
))
21437 if (symbol_preemptible (fragp
->fr_symbol
))
21440 val
= relaxed_symbol_addr (fragp
, stretch
);
21441 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21444 /* Offset is a signed value *2 */
21446 if (val
>= limit
|| val
< -limit
)
21452 /* Relax a machine dependent frag. This returns the amount by which
21453 the current size of the frag should change. */
21456 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21461 oldsize
= fragp
->fr_var
;
21462 switch (fragp
->fr_subtype
)
21464 case T_MNEM_ldr_pc2
:
21465 newsize
= relax_adr (fragp
, sec
, stretch
);
21467 case T_MNEM_ldr_pc
:
21468 case T_MNEM_ldr_sp
:
21469 case T_MNEM_str_sp
:
21470 newsize
= relax_immediate (fragp
, 8, 2);
21474 newsize
= relax_immediate (fragp
, 5, 2);
21478 newsize
= relax_immediate (fragp
, 5, 1);
21482 newsize
= relax_immediate (fragp
, 5, 0);
21485 newsize
= relax_adr (fragp
, sec
, stretch
);
21491 newsize
= relax_immediate (fragp
, 8, 0);
21494 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21497 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21499 case T_MNEM_add_sp
:
21500 case T_MNEM_add_pc
:
21501 newsize
= relax_immediate (fragp
, 8, 2);
21503 case T_MNEM_inc_sp
:
21504 case T_MNEM_dec_sp
:
21505 newsize
= relax_immediate (fragp
, 7, 2);
21511 newsize
= relax_addsub (fragp
, sec
);
21517 fragp
->fr_var
= newsize
;
21518 /* Freeze wide instructions that are at or before the same location as
21519 in the previous pass. This avoids infinite loops.
21520 Don't freeze them unconditionally because targets may be artificially
21521 misaligned by the expansion of preceding frags. */
21522 if (stretch
<= 0 && newsize
> 2)
21524 md_convert_frag (sec
->owner
, sec
, fragp
);
21528 return newsize
- oldsize
;
21531 /* Round up a section size to the appropriate boundary. */
21534 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21537 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21538 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21540 /* For a.out, force the section size to be aligned. If we don't do
21541 this, BFD will align it for us, but it will not write out the
21542 final bytes of the section. This may be a bug in BFD, but it is
21543 easier to fix it here since that is how the other a.out targets
21547 align
= bfd_get_section_alignment (stdoutput
, segment
);
21548 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21555 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21556 of an rs_align_code fragment. */
21559 arm_handle_align (fragS
* fragP
)
21561 static unsigned char const arm_noop
[2][2][4] =
21564 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21565 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21568 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21569 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21572 static unsigned char const thumb_noop
[2][2][2] =
21575 {0xc0, 0x46}, /* LE */
21576 {0x46, 0xc0}, /* BE */
21579 {0x00, 0xbf}, /* LE */
21580 {0xbf, 0x00} /* BE */
21583 static unsigned char const wide_thumb_noop
[2][4] =
21584 { /* Wide Thumb-2 */
21585 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21586 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21589 unsigned bytes
, fix
, noop_size
;
21591 const unsigned char * noop
;
21592 const unsigned char *narrow_noop
= NULL
;
21597 if (fragP
->fr_type
!= rs_align_code
)
21600 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21601 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21604 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21605 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21607 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21609 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21611 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21612 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21614 narrow_noop
= thumb_noop
[1][target_big_endian
];
21615 noop
= wide_thumb_noop
[target_big_endian
];
21618 noop
= thumb_noop
[0][target_big_endian
];
21626 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21627 ? selected_cpu
: arm_arch_none
,
21629 [target_big_endian
];
21636 fragP
->fr_var
= noop_size
;
21638 if (bytes
& (noop_size
- 1))
21640 fix
= bytes
& (noop_size
- 1);
21642 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21644 memset (p
, 0, fix
);
21651 if (bytes
& noop_size
)
21653 /* Insert a narrow noop. */
21654 memcpy (p
, narrow_noop
, noop_size
);
21656 bytes
-= noop_size
;
21660 /* Use wide noops for the remainder */
21664 while (bytes
>= noop_size
)
21666 memcpy (p
, noop
, noop_size
);
21668 bytes
-= noop_size
;
21672 fragP
->fr_fix
+= fix
;
21675 /* Called from md_do_align. Used to create an alignment
21676 frag in a code section. */
21679 arm_frag_align_code (int n
, int max
)
21683 /* We assume that there will never be a requirement
21684 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21685 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21690 _("alignments greater than %d bytes not supported in .text sections."),
21691 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21692 as_fatal ("%s", err_msg
);
21695 p
= frag_var (rs_align_code
,
21696 MAX_MEM_FOR_RS_ALIGN_CODE
,
21698 (relax_substateT
) max
,
21705 /* Perform target specific initialisation of a frag.
21706 Note - despite the name this initialisation is not done when the frag
21707 is created, but only when its type is assigned. A frag can be created
21708 and used a long time before its type is set, so beware of assuming that
21709 this initialisationis performed first. */
21713 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21715 /* Record whether this frag is in an ARM or a THUMB area. */
21716 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21719 #else /* OBJ_ELF is defined. */
21721 arm_init_frag (fragS
* fragP
, int max_chars
)
21723 int frag_thumb_mode
;
21725 /* If the current ARM vs THUMB mode has not already
21726 been recorded into this frag then do so now. */
21727 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21728 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21730 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21732 /* Record a mapping symbol for alignment frags. We will delete this
21733 later if the alignment ends up empty. */
21734 switch (fragP
->fr_type
)
21737 case rs_align_test
:
21739 mapping_state_2 (MAP_DATA
, max_chars
);
21741 case rs_align_code
:
21742 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21749 /* When we change sections we need to issue a new mapping symbol. */
21752 arm_elf_change_section (void)
21754 /* Link an unlinked unwind index table section to the .text section. */
21755 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21756 && elf_linked_to_section (now_seg
) == NULL
)
21757 elf_linked_to_section (now_seg
) = text_section
;
21761 arm_elf_section_type (const char * str
, size_t len
)
21763 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21764 return SHT_ARM_EXIDX
;
21769 /* Code to deal with unwinding tables. */
21771 static void add_unwind_adjustsp (offsetT
);
21773 /* Generate any deferred unwind frame offset. */
21776 flush_pending_unwind (void)
21780 offset
= unwind
.pending_offset
;
21781 unwind
.pending_offset
= 0;
21783 add_unwind_adjustsp (offset
);
21786 /* Add an opcode to this list for this function. Two-byte opcodes should
21787 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21791 add_unwind_opcode (valueT op
, int length
)
21793 /* Add any deferred stack adjustment. */
21794 if (unwind
.pending_offset
)
21795 flush_pending_unwind ();
21797 unwind
.sp_restored
= 0;
21799 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21801 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21802 if (unwind
.opcodes
)
21803 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21804 unwind
.opcode_alloc
);
21806 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21811 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21813 unwind
.opcode_count
++;
21817 /* Add unwind opcodes to adjust the stack pointer. */
21820 add_unwind_adjustsp (offsetT offset
)
21824 if (offset
> 0x200)
21826 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21831 /* Long form: 0xb2, uleb128. */
21832 /* This might not fit in a word so add the individual bytes,
21833 remembering the list is built in reverse order. */
21834 o
= (valueT
) ((offset
- 0x204) >> 2);
21836 add_unwind_opcode (0, 1);
21838 /* Calculate the uleb128 encoding of the offset. */
21842 bytes
[n
] = o
& 0x7f;
21848 /* Add the insn. */
21850 add_unwind_opcode (bytes
[n
- 1], 1);
21851 add_unwind_opcode (0xb2, 1);
21853 else if (offset
> 0x100)
21855 /* Two short opcodes. */
21856 add_unwind_opcode (0x3f, 1);
21857 op
= (offset
- 0x104) >> 2;
21858 add_unwind_opcode (op
, 1);
21860 else if (offset
> 0)
21862 /* Short opcode. */
21863 op
= (offset
- 4) >> 2;
21864 add_unwind_opcode (op
, 1);
21866 else if (offset
< 0)
21869 while (offset
> 0x100)
21871 add_unwind_opcode (0x7f, 1);
21874 op
= ((offset
- 4) >> 2) | 0x40;
21875 add_unwind_opcode (op
, 1);
21879 /* Finish the list of unwind opcodes for this function. */
21881 finish_unwind_opcodes (void)
21885 if (unwind
.fp_used
)
21887 /* Adjust sp as necessary. */
21888 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21889 flush_pending_unwind ();
21891 /* After restoring sp from the frame pointer. */
21892 op
= 0x90 | unwind
.fp_reg
;
21893 add_unwind_opcode (op
, 1);
21896 flush_pending_unwind ();
21900 /* Start an exception table entry. If idx is nonzero this is an index table
21904 start_unwind_section (const segT text_seg
, int idx
)
21906 const char * text_name
;
21907 const char * prefix
;
21908 const char * prefix_once
;
21909 const char * group_name
;
21917 prefix
= ELF_STRING_ARM_unwind
;
21918 prefix_once
= ELF_STRING_ARM_unwind_once
;
21919 type
= SHT_ARM_EXIDX
;
21923 prefix
= ELF_STRING_ARM_unwind_info
;
21924 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21925 type
= SHT_PROGBITS
;
21928 text_name
= segment_name (text_seg
);
21929 if (streq (text_name
, ".text"))
21932 if (strncmp (text_name
, ".gnu.linkonce.t.",
21933 strlen (".gnu.linkonce.t.")) == 0)
21935 prefix
= prefix_once
;
21936 text_name
+= strlen (".gnu.linkonce.t.");
21939 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
21945 /* Handle COMDAT group. */
21946 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21948 group_name
= elf_group_name (text_seg
);
21949 if (group_name
== NULL
)
21951 as_bad (_("Group section `%s' has no group signature"),
21952 segment_name (text_seg
));
21953 ignore_rest_of_line ();
21956 flags
|= SHF_GROUP
;
21960 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21962 /* Set the section link for index tables. */
21964 elf_linked_to_section (now_seg
) = text_seg
;
21968 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21969 personality routine data. Returns zero, or the index table value for
21970 an inline entry. */
21973 create_unwind_entry (int have_data
)
21978 /* The current word of data. */
21980 /* The number of bytes left in this word. */
21983 finish_unwind_opcodes ();
21985 /* Remember the current text section. */
21986 unwind
.saved_seg
= now_seg
;
21987 unwind
.saved_subseg
= now_subseg
;
21989 start_unwind_section (now_seg
, 0);
21991 if (unwind
.personality_routine
== NULL
)
21993 if (unwind
.personality_index
== -2)
21996 as_bad (_("handlerdata in cantunwind frame"));
21997 return 1; /* EXIDX_CANTUNWIND. */
22000 /* Use a default personality routine if none is specified. */
22001 if (unwind
.personality_index
== -1)
22003 if (unwind
.opcode_count
> 3)
22004 unwind
.personality_index
= 1;
22006 unwind
.personality_index
= 0;
22009 /* Space for the personality routine entry. */
22010 if (unwind
.personality_index
== 0)
22012 if (unwind
.opcode_count
> 3)
22013 as_bad (_("too many unwind opcodes for personality routine 0"));
22017 /* All the data is inline in the index table. */
22020 while (unwind
.opcode_count
> 0)
22022 unwind
.opcode_count
--;
22023 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22027 /* Pad with "finish" opcodes. */
22029 data
= (data
<< 8) | 0xb0;
22036 /* We get two opcodes "free" in the first word. */
22037 size
= unwind
.opcode_count
- 2;
22041 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22042 if (unwind
.personality_index
!= -1)
22044 as_bad (_("attempt to recreate an unwind entry"));
22048 /* An extra byte is required for the opcode count. */
22049 size
= unwind
.opcode_count
+ 1;
22052 size
= (size
+ 3) >> 2;
22054 as_bad (_("too many unwind opcodes"));
22056 frag_align (2, 0, 0);
22057 record_alignment (now_seg
, 2);
22058 unwind
.table_entry
= expr_build_dot ();
22060 /* Allocate the table entry. */
22061 ptr
= frag_more ((size
<< 2) + 4);
22062 /* PR 13449: Zero the table entries in case some of them are not used. */
22063 memset (ptr
, 0, (size
<< 2) + 4);
22064 where
= frag_now_fix () - ((size
<< 2) + 4);
22066 switch (unwind
.personality_index
)
22069 /* ??? Should this be a PLT generating relocation? */
22070 /* Custom personality routine. */
22071 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22072 BFD_RELOC_ARM_PREL31
);
22077 /* Set the first byte to the number of additional words. */
22078 data
= size
> 0 ? size
- 1 : 0;
22082 /* ABI defined personality routines. */
22084 /* Three opcodes bytes are packed into the first word. */
22091 /* The size and first two opcode bytes go in the first word. */
22092 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22097 /* Should never happen. */
22101 /* Pack the opcodes into words (MSB first), reversing the list at the same
22103 while (unwind
.opcode_count
> 0)
22107 md_number_to_chars (ptr
, data
, 4);
22112 unwind
.opcode_count
--;
22114 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22117 /* Finish off the last word. */
22120 /* Pad with "finish" opcodes. */
22122 data
= (data
<< 8) | 0xb0;
22124 md_number_to_chars (ptr
, data
, 4);
22129 /* Add an empty descriptor if there is no user-specified data. */
22130 ptr
= frag_more (4);
22131 md_number_to_chars (ptr
, 0, 4);
22138 /* Initialize the DWARF-2 unwind information for this procedure. */
22141 tc_arm_frame_initial_instructions (void)
22143 cfi_add_CFA_def_cfa (REG_SP
, 0);
22145 #endif /* OBJ_ELF */
22147 /* Convert REGNAME to a DWARF-2 register number. */
22150 tc_arm_regname_to_dw2regnum (char *regname
)
22152 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22156 /* PR 16694: Allow VFP registers as well. */
22157 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22161 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22170 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22174 exp
.X_op
= O_secrel
;
22175 exp
.X_add_symbol
= symbol
;
22176 exp
.X_add_number
= 0;
22177 emit_expr (&exp
, size
);
22181 /* MD interface: Symbol and relocation handling. */
22183 /* Return the address within the segment that a PC-relative fixup is
22184 relative to. For ARM, PC-relative fixups applied to instructions
22185 are generally relative to the location of the fixup plus 8 bytes.
22186 Thumb branches are offset by 4, and Thumb loads relative to PC
22187 require special handling. */
22190 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22192 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22194 /* If this is pc-relative and we are going to emit a relocation
22195 then we just want to put out any pipeline compensation that the linker
22196 will need. Otherwise we want to use the calculated base.
22197 For WinCE we skip the bias for externals as well, since this
22198 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22200 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22201 || (arm_force_relocation (fixP
)
22203 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22209 switch (fixP
->fx_r_type
)
22211 /* PC relative addressing on the Thumb is slightly odd as the
22212 bottom two bits of the PC are forced to zero for the
22213 calculation. This happens *after* application of the
22214 pipeline offset. However, Thumb adrl already adjusts for
22215 this, so we need not do it again. */
22216 case BFD_RELOC_ARM_THUMB_ADD
:
22219 case BFD_RELOC_ARM_THUMB_OFFSET
:
22220 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22221 case BFD_RELOC_ARM_T32_ADD_PC12
:
22222 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22223 return (base
+ 4) & ~3;
22225 /* Thumb branches are simply offset by +4. */
22226 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22227 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22228 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22229 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22230 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22233 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22235 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22236 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22237 && ARM_IS_FUNC (fixP
->fx_addsy
)
22238 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22239 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22242 /* BLX is like branches above, but forces the low two bits of PC to
22244 case BFD_RELOC_THUMB_PCREL_BLX
:
22246 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22247 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22248 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22249 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22250 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22251 return (base
+ 4) & ~3;
22253 /* ARM mode branches are offset by +8. However, the Windows CE
22254 loader expects the relocation not to take this into account. */
22255 case BFD_RELOC_ARM_PCREL_BLX
:
22257 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22258 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22259 && ARM_IS_FUNC (fixP
->fx_addsy
)
22260 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22261 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22264 case BFD_RELOC_ARM_PCREL_CALL
:
22266 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22267 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22268 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22269 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22270 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22273 case BFD_RELOC_ARM_PCREL_BRANCH
:
22274 case BFD_RELOC_ARM_PCREL_JUMP
:
22275 case BFD_RELOC_ARM_PLT32
:
22277 /* When handling fixups immediately, because we have already
22278 discovered the value of a symbol, or the address of the frag involved
22279 we must account for the offset by +8, as the OS loader will never see the reloc.
22280 see fixup_segment() in write.c
22281 The S_IS_EXTERNAL test handles the case of global symbols.
22282 Those need the calculated base, not just the pipe compensation the linker will need. */
22284 && fixP
->fx_addsy
!= NULL
22285 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22286 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22294 /* ARM mode loads relative to PC are also offset by +8. Unlike
22295 branches, the Windows CE loader *does* expect the relocation
22296 to take this into account. */
22297 case BFD_RELOC_ARM_OFFSET_IMM
:
22298 case BFD_RELOC_ARM_OFFSET_IMM8
:
22299 case BFD_RELOC_ARM_HWLITERAL
:
22300 case BFD_RELOC_ARM_LITERAL
:
22301 case BFD_RELOC_ARM_CP_OFF_IMM
:
22305 /* Other PC-relative relocations are un-offset. */
22311 static bfd_boolean flag_warn_syms
= TRUE
;
22314 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22316 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22317 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22318 does mean that the resulting code might be very confusing to the reader.
22319 Also this warning can be triggered if the user omits an operand before
22320 an immediate address, eg:
22324 GAS treats this as an assignment of the value of the symbol foo to a
22325 symbol LDR, and so (without this code) it will not issue any kind of
22326 warning or error message.
22328 Note - ARM instructions are case-insensitive but the strings in the hash
22329 table are all stored in lower case, so we must first ensure that name is
22331 if (flag_warn_syms
&& arm_ops_hsh
)
22333 char * nbuf
= strdup (name
);
22336 for (p
= nbuf
; *p
; p
++)
22338 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22340 static struct hash_control
* already_warned
= NULL
;
22342 if (already_warned
== NULL
)
22343 already_warned
= hash_new ();
22344 /* Only warn about the symbol once. To keep the code
22345 simple we let hash_insert do the lookup for us. */
22346 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22347 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22356 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22357 Otherwise we have no need to default values of symbols. */
22360 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22363 if (name
[0] == '_' && name
[1] == 'G'
22364 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22368 if (symbol_find (name
))
22369 as_bad (_("GOT already in the symbol table"));
22371 GOT_symbol
= symbol_new (name
, undefined_section
,
22372 (valueT
) 0, & zero_address_frag
);
22382 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22383 computed as two separate immediate values, added together. We
22384 already know that this value cannot be computed by just one ARM
22387 static unsigned int
22388 validate_immediate_twopart (unsigned int val
,
22389 unsigned int * highpart
)
22394 for (i
= 0; i
< 32; i
+= 2)
22395 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22401 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22403 else if (a
& 0xff0000)
22405 if (a
& 0xff000000)
22407 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22411 gas_assert (a
& 0xff000000);
22412 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22415 return (a
& 0xff) | (i
<< 7);
22422 validate_offset_imm (unsigned int val
, int hwse
)
22424 if ((hwse
&& val
> 255) || val
> 4095)
22429 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22430 negative immediate constant by altering the instruction. A bit of
22435 by inverting the second operand, and
22438 by negating the second operand. */
22441 negate_data_op (unsigned long * instruction
,
22442 unsigned long value
)
22445 unsigned long negated
, inverted
;
22447 negated
= encode_arm_immediate (-value
);
22448 inverted
= encode_arm_immediate (~value
);
22450 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22453 /* First negates. */
22454 case OPCODE_SUB
: /* ADD <-> SUB */
22455 new_inst
= OPCODE_ADD
;
22460 new_inst
= OPCODE_SUB
;
22464 case OPCODE_CMP
: /* CMP <-> CMN */
22465 new_inst
= OPCODE_CMN
;
22470 new_inst
= OPCODE_CMP
;
22474 /* Now Inverted ops. */
22475 case OPCODE_MOV
: /* MOV <-> MVN */
22476 new_inst
= OPCODE_MVN
;
22481 new_inst
= OPCODE_MOV
;
22485 case OPCODE_AND
: /* AND <-> BIC */
22486 new_inst
= OPCODE_BIC
;
22491 new_inst
= OPCODE_AND
;
22495 case OPCODE_ADC
: /* ADC <-> SBC */
22496 new_inst
= OPCODE_SBC
;
22501 new_inst
= OPCODE_ADC
;
22505 /* We cannot do anything. */
22510 if (value
== (unsigned) FAIL
)
22513 *instruction
&= OPCODE_MASK
;
22514 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22518 /* Like negate_data_op, but for Thumb-2. */
22520 static unsigned int
22521 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22525 unsigned int negated
, inverted
;
22527 negated
= encode_thumb32_immediate (-value
);
22528 inverted
= encode_thumb32_immediate (~value
);
22530 rd
= (*instruction
>> 8) & 0xf;
22531 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22534 /* ADD <-> SUB. Includes CMP <-> CMN. */
22535 case T2_OPCODE_SUB
:
22536 new_inst
= T2_OPCODE_ADD
;
22540 case T2_OPCODE_ADD
:
22541 new_inst
= T2_OPCODE_SUB
;
22545 /* ORR <-> ORN. Includes MOV <-> MVN. */
22546 case T2_OPCODE_ORR
:
22547 new_inst
= T2_OPCODE_ORN
;
22551 case T2_OPCODE_ORN
:
22552 new_inst
= T2_OPCODE_ORR
;
22556 /* AND <-> BIC. TST has no inverted equivalent. */
22557 case T2_OPCODE_AND
:
22558 new_inst
= T2_OPCODE_BIC
;
22565 case T2_OPCODE_BIC
:
22566 new_inst
= T2_OPCODE_AND
;
22571 case T2_OPCODE_ADC
:
22572 new_inst
= T2_OPCODE_SBC
;
22576 case T2_OPCODE_SBC
:
22577 new_inst
= T2_OPCODE_ADC
;
22581 /* We cannot do anything. */
22586 if (value
== (unsigned int)FAIL
)
22589 *instruction
&= T2_OPCODE_MASK
;
22590 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22594 /* Read a 32-bit thumb instruction from buf. */
22595 static unsigned long
22596 get_thumb32_insn (char * buf
)
22598 unsigned long insn
;
22599 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22600 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22606 /* We usually want to set the low bit on the address of thumb function
22607 symbols. In particular .word foo - . should have the low bit set.
22608 Generic code tries to fold the difference of two symbols to
22609 a constant. Prevent this and force a relocation when the first symbols
22610 is a thumb function. */
22613 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22615 if (op
== O_subtract
22616 && l
->X_op
== O_symbol
22617 && r
->X_op
== O_symbol
22618 && THUMB_IS_FUNC (l
->X_add_symbol
))
22620 l
->X_op
= O_subtract
;
22621 l
->X_op_symbol
= r
->X_add_symbol
;
22622 l
->X_add_number
-= r
->X_add_number
;
22626 /* Process as normal. */
22630 /* Encode Thumb2 unconditional branches and calls. The encoding
22631 for the 2 are identical for the immediate values. */
22634 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22636 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22639 addressT S
, I1
, I2
, lo
, hi
;
22641 S
= (value
>> 24) & 0x01;
22642 I1
= (value
>> 23) & 0x01;
22643 I2
= (value
>> 22) & 0x01;
22644 hi
= (value
>> 12) & 0x3ff;
22645 lo
= (value
>> 1) & 0x7ff;
22646 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22647 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22648 newval
|= (S
<< 10) | hi
;
22649 newval2
&= ~T2I1I2MASK
;
22650 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22651 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22652 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22656 md_apply_fix (fixS
* fixP
,
22660 offsetT value
= * valP
;
22662 unsigned int newimm
;
22663 unsigned long temp
;
22665 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22667 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22669 /* Note whether this will delete the relocation. */
22671 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22674 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22675 consistency with the behaviour on 32-bit hosts. Remember value
22677 value
&= 0xffffffff;
22678 value
^= 0x80000000;
22679 value
-= 0x80000000;
22682 fixP
->fx_addnumber
= value
;
22684 /* Same treatment for fixP->fx_offset. */
22685 fixP
->fx_offset
&= 0xffffffff;
22686 fixP
->fx_offset
^= 0x80000000;
22687 fixP
->fx_offset
-= 0x80000000;
22689 switch (fixP
->fx_r_type
)
22691 case BFD_RELOC_NONE
:
22692 /* This will need to go in the object file. */
22696 case BFD_RELOC_ARM_IMMEDIATE
:
22697 /* We claim that this fixup has been processed here,
22698 even if in fact we generate an error because we do
22699 not have a reloc for it, so tc_gen_reloc will reject it. */
22702 if (fixP
->fx_addsy
)
22704 const char *msg
= 0;
22706 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22707 msg
= _("undefined symbol %s used as an immediate value");
22708 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22709 msg
= _("symbol %s is in a different section");
22710 else if (S_IS_WEAK (fixP
->fx_addsy
))
22711 msg
= _("symbol %s is weak and may be overridden later");
22715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22716 msg
, S_GET_NAME (fixP
->fx_addsy
));
22721 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22723 /* If the offset is negative, we should use encoding A2 for ADR. */
22724 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22725 newimm
= negate_data_op (&temp
, value
);
22728 newimm
= encode_arm_immediate (value
);
22730 /* If the instruction will fail, see if we can fix things up by
22731 changing the opcode. */
22732 if (newimm
== (unsigned int) FAIL
)
22733 newimm
= negate_data_op (&temp
, value
);
22736 if (newimm
== (unsigned int) FAIL
)
22738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22739 _("invalid constant (%lx) after fixup"),
22740 (unsigned long) value
);
22744 newimm
|= (temp
& 0xfffff000);
22745 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22748 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22750 unsigned int highpart
= 0;
22751 unsigned int newinsn
= 0xe1a00000; /* nop. */
22753 if (fixP
->fx_addsy
)
22755 const char *msg
= 0;
22757 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22758 msg
= _("undefined symbol %s used as an immediate value");
22759 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22760 msg
= _("symbol %s is in a different section");
22761 else if (S_IS_WEAK (fixP
->fx_addsy
))
22762 msg
= _("symbol %s is weak and may be overridden later");
22766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22767 msg
, S_GET_NAME (fixP
->fx_addsy
));
22772 newimm
= encode_arm_immediate (value
);
22773 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22775 /* If the instruction will fail, see if we can fix things up by
22776 changing the opcode. */
22777 if (newimm
== (unsigned int) FAIL
22778 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22780 /* No ? OK - try using two ADD instructions to generate
22782 newimm
= validate_immediate_twopart (value
, & highpart
);
22784 /* Yes - then make sure that the second instruction is
22786 if (newimm
!= (unsigned int) FAIL
)
22788 /* Still No ? Try using a negated value. */
22789 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22790 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22791 /* Otherwise - give up. */
22794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22795 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22800 /* Replace the first operand in the 2nd instruction (which
22801 is the PC) with the destination register. We have
22802 already added in the PC in the first instruction and we
22803 do not want to do it again. */
22804 newinsn
&= ~ 0xf0000;
22805 newinsn
|= ((newinsn
& 0x0f000) << 4);
22808 newimm
|= (temp
& 0xfffff000);
22809 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22811 highpart
|= (newinsn
& 0xfffff000);
22812 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22816 case BFD_RELOC_ARM_OFFSET_IMM
:
22817 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22820 case BFD_RELOC_ARM_LITERAL
:
22826 if (validate_offset_imm (value
, 0) == FAIL
)
22828 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22830 _("invalid literal constant: pool needs to be closer"));
22832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22833 _("bad immediate value for offset (%ld)"),
22838 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22840 newval
&= 0xfffff000;
22843 newval
&= 0xff7ff000;
22844 newval
|= value
| (sign
? INDEX_UP
: 0);
22846 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22849 case BFD_RELOC_ARM_OFFSET_IMM8
:
22850 case BFD_RELOC_ARM_HWLITERAL
:
22856 if (validate_offset_imm (value
, 1) == FAIL
)
22858 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22860 _("invalid literal constant: pool needs to be closer"));
22862 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22863 _("bad immediate value for 8-bit offset (%ld)"),
22868 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22870 newval
&= 0xfffff0f0;
22873 newval
&= 0xff7ff0f0;
22874 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22876 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22879 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22880 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22882 _("bad immediate value for offset (%ld)"), (long) value
);
22885 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22887 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22890 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22891 /* This is a complicated relocation used for all varieties of Thumb32
22892 load/store instruction with immediate offset:
22894 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22895 *4, optional writeback(W)
22896 (doubleword load/store)
22898 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22899 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22900 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22901 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22902 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22904 Uppercase letters indicate bits that are already encoded at
22905 this point. Lowercase letters are our problem. For the
22906 second block of instructions, the secondary opcode nybble
22907 (bits 8..11) is present, and bit 23 is zero, even if this is
22908 a PC-relative operation. */
22909 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22911 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22913 if ((newval
& 0xf0000000) == 0xe0000000)
22915 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22917 newval
|= (1 << 23);
22920 if (value
% 4 != 0)
22922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22923 _("offset not a multiple of 4"));
22929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22930 _("offset out of range"));
22935 else if ((newval
& 0x000f0000) == 0x000f0000)
22937 /* PC-relative, 12-bit offset. */
22939 newval
|= (1 << 23);
22944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22945 _("offset out of range"));
22950 else if ((newval
& 0x00000100) == 0x00000100)
22952 /* Writeback: 8-bit, +/- offset. */
22954 newval
|= (1 << 9);
22959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22960 _("offset out of range"));
22965 else if ((newval
& 0x00000f00) == 0x00000e00)
22967 /* T-instruction: positive 8-bit offset. */
22968 if (value
< 0 || value
> 0xff)
22970 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22971 _("offset out of range"));
22979 /* Positive 12-bit or negative 8-bit offset. */
22983 newval
|= (1 << 23);
22993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22994 _("offset out of range"));
23001 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23002 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23005 case BFD_RELOC_ARM_SHIFT_IMM
:
23006 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23007 if (((unsigned long) value
) > 32
23009 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23011 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23012 _("shift expression is too large"));
23017 /* Shifts of zero must be done as lsl. */
23019 else if (value
== 32)
23021 newval
&= 0xfffff07f;
23022 newval
|= (value
& 0x1f) << 7;
23023 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23026 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23027 case BFD_RELOC_ARM_T32_ADD_IMM
:
23028 case BFD_RELOC_ARM_T32_IMM12
:
23029 case BFD_RELOC_ARM_T32_ADD_PC12
:
23030 /* We claim that this fixup has been processed here,
23031 even if in fact we generate an error because we do
23032 not have a reloc for it, so tc_gen_reloc will reject it. */
23036 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23039 _("undefined symbol %s used as an immediate value"),
23040 S_GET_NAME (fixP
->fx_addsy
));
23044 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23046 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23049 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23050 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23052 newimm
= encode_thumb32_immediate (value
);
23053 if (newimm
== (unsigned int) FAIL
)
23054 newimm
= thumb32_negate_data_op (&newval
, value
);
23056 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
23057 && newimm
== (unsigned int) FAIL
)
23059 /* Turn add/sum into addw/subw. */
23060 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23061 newval
= (newval
& 0xfeffffff) | 0x02000000;
23062 /* No flat 12-bit imm encoding for addsw/subsw. */
23063 if ((newval
& 0x00100000) == 0)
23065 /* 12 bit immediate for addw/subw. */
23069 newval
^= 0x00a00000;
23072 newimm
= (unsigned int) FAIL
;
23078 if (newimm
== (unsigned int)FAIL
)
23080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23081 _("invalid constant (%lx) after fixup"),
23082 (unsigned long) value
);
23086 newval
|= (newimm
& 0x800) << 15;
23087 newval
|= (newimm
& 0x700) << 4;
23088 newval
|= (newimm
& 0x0ff);
23090 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23091 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23094 case BFD_RELOC_ARM_SMC
:
23095 if (((unsigned long) value
) > 0xffff)
23096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23097 _("invalid smc expression"));
23098 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23099 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23100 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23103 case BFD_RELOC_ARM_HVC
:
23104 if (((unsigned long) value
) > 0xffff)
23105 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23106 _("invalid hvc expression"));
23107 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23108 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23109 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23112 case BFD_RELOC_ARM_SWI
:
23113 if (fixP
->tc_fix_data
!= 0)
23115 if (((unsigned long) value
) > 0xff)
23116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23117 _("invalid swi expression"));
23118 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23120 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23124 if (((unsigned long) value
) > 0x00ffffff)
23125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23126 _("invalid swi expression"));
23127 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23129 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23133 case BFD_RELOC_ARM_MULTI
:
23134 if (((unsigned long) value
) > 0xffff)
23135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23136 _("invalid expression in load/store multiple"));
23137 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23138 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23142 case BFD_RELOC_ARM_PCREL_CALL
:
23144 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23146 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23147 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23148 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23149 /* Flip the bl to blx. This is a simple flip
23150 bit here because we generate PCREL_CALL for
23151 unconditional bls. */
23153 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23154 newval
= newval
| 0x10000000;
23155 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23161 goto arm_branch_common
;
23163 case BFD_RELOC_ARM_PCREL_JUMP
:
23164 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23166 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23167 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23168 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23170 /* This would map to a bl<cond>, b<cond>,
23171 b<always> to a Thumb function. We
23172 need to force a relocation for this particular
23174 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23178 case BFD_RELOC_ARM_PLT32
:
23180 case BFD_RELOC_ARM_PCREL_BRANCH
:
23182 goto arm_branch_common
;
23184 case BFD_RELOC_ARM_PCREL_BLX
:
23187 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23189 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23190 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23191 && ARM_IS_FUNC (fixP
->fx_addsy
))
23193 /* Flip the blx to a bl and warn. */
23194 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23195 newval
= 0xeb000000;
23196 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23197 _("blx to '%s' an ARM ISA state function changed to bl"),
23199 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23205 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23206 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23210 /* We are going to store value (shifted right by two) in the
23211 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23212 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23213 also be be clear. */
23215 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23216 _("misaligned branch destination"));
23217 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23218 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23219 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23221 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23223 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23224 newval
|= (value
>> 2) & 0x00ffffff;
23225 /* Set the H bit on BLX instructions. */
23229 newval
|= 0x01000000;
23231 newval
&= ~0x01000000;
23233 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23237 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23238 /* CBZ can only branch forward. */
23240 /* Attempts to use CBZ to branch to the next instruction
23241 (which, strictly speaking, are prohibited) will be turned into
23244 FIXME: It may be better to remove the instruction completely and
23245 perform relaxation. */
23248 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23249 newval
= 0xbf00; /* NOP encoding T1 */
23250 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23257 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23259 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23260 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23261 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23266 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23267 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23270 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23272 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23273 newval
|= (value
& 0x1ff) >> 1;
23274 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23278 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23279 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23280 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23282 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23284 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23285 newval
|= (value
& 0xfff) >> 1;
23286 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23290 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23292 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23293 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23294 && ARM_IS_FUNC (fixP
->fx_addsy
)
23295 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23297 /* Force a relocation for a branch 20 bits wide. */
23300 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23301 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23302 _("conditional branch out of range"));
23304 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23307 addressT S
, J1
, J2
, lo
, hi
;
23309 S
= (value
& 0x00100000) >> 20;
23310 J2
= (value
& 0x00080000) >> 19;
23311 J1
= (value
& 0x00040000) >> 18;
23312 hi
= (value
& 0x0003f000) >> 12;
23313 lo
= (value
& 0x00000ffe) >> 1;
23315 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23316 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23317 newval
|= (S
<< 10) | hi
;
23318 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23319 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23320 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23324 case BFD_RELOC_THUMB_PCREL_BLX
:
23325 /* If there is a blx from a thumb state function to
23326 another thumb function flip this to a bl and warn
23330 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23331 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23332 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23334 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23335 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23336 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23338 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23339 newval
= newval
| 0x1000;
23340 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23341 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23346 goto thumb_bl_common
;
23348 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23349 /* A bl from Thumb state ISA to an internal ARM state function
23350 is converted to a blx. */
23352 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23353 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23354 && ARM_IS_FUNC (fixP
->fx_addsy
)
23355 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23357 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23358 newval
= newval
& ~0x1000;
23359 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23360 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23366 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23367 /* For a BLX instruction, make sure that the relocation is rounded up
23368 to a word boundary. This follows the semantics of the instruction
23369 which specifies that bit 1 of the target address will come from bit
23370 1 of the base address. */
23371 value
= (value
+ 3) & ~ 3;
23374 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23375 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23376 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23379 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23381 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23382 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23383 else if ((value
& ~0x1ffffff)
23384 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23386 _("Thumb2 branch out of range"));
23389 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23390 encode_thumb2_b_bl_offset (buf
, value
);
23394 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23395 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23396 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23398 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23399 encode_thumb2_b_bl_offset (buf
, value
);
23404 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23409 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23410 md_number_to_chars (buf
, value
, 2);
23414 case BFD_RELOC_ARM_TLS_CALL
:
23415 case BFD_RELOC_ARM_THM_TLS_CALL
:
23416 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23417 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23418 case BFD_RELOC_ARM_TLS_GOTDESC
:
23419 case BFD_RELOC_ARM_TLS_GD32
:
23420 case BFD_RELOC_ARM_TLS_LE32
:
23421 case BFD_RELOC_ARM_TLS_IE32
:
23422 case BFD_RELOC_ARM_TLS_LDM32
:
23423 case BFD_RELOC_ARM_TLS_LDO32
:
23424 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23427 case BFD_RELOC_ARM_GOT32
:
23428 case BFD_RELOC_ARM_GOTOFF
:
23431 case BFD_RELOC_ARM_GOT_PREL
:
23432 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23433 md_number_to_chars (buf
, value
, 4);
23436 case BFD_RELOC_ARM_TARGET2
:
23437 /* TARGET2 is not partial-inplace, so we need to write the
23438 addend here for REL targets, because it won't be written out
23439 during reloc processing later. */
23440 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23441 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23445 case BFD_RELOC_RVA
:
23447 case BFD_RELOC_ARM_TARGET1
:
23448 case BFD_RELOC_ARM_ROSEGREL32
:
23449 case BFD_RELOC_ARM_SBREL32
:
23450 case BFD_RELOC_32_PCREL
:
23452 case BFD_RELOC_32_SECREL
:
23454 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23456 /* For WinCE we only do this for pcrel fixups. */
23457 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23459 md_number_to_chars (buf
, value
, 4);
23463 case BFD_RELOC_ARM_PREL31
:
23464 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23466 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23467 if ((value
^ (value
>> 1)) & 0x40000000)
23469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23470 _("rel31 relocation overflow"));
23472 newval
|= value
& 0x7fffffff;
23473 md_number_to_chars (buf
, newval
, 4);
23478 case BFD_RELOC_ARM_CP_OFF_IMM
:
23479 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23480 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23481 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23483 newval
= get_thumb32_insn (buf
);
23484 if ((newval
& 0x0f200f00) == 0x0d000900)
23486 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23487 has permitted values that are multiples of 2, in the range 0
23489 if (value
< -510 || value
> 510 || (value
& 1))
23490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23491 _("co-processor offset out of range"));
23493 else if (value
< -1023 || value
> 1023 || (value
& 3))
23494 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23495 _("co-processor offset out of range"));
23500 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23501 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23502 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23504 newval
= get_thumb32_insn (buf
);
23506 newval
&= 0xffffff00;
23509 newval
&= 0xff7fff00;
23510 if ((newval
& 0x0f200f00) == 0x0d000900)
23512 /* This is a fp16 vstr/vldr.
23514 It requires the immediate offset in the instruction is shifted
23515 left by 1 to be a half-word offset.
23517 Here, left shift by 1 first, and later right shift by 2
23518 should get the right offset. */
23521 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23523 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23524 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23525 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23527 put_thumb32_insn (buf
, newval
);
23530 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23531 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23532 if (value
< -255 || value
> 255)
23533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23534 _("co-processor offset out of range"));
23536 goto cp_off_common
;
23538 case BFD_RELOC_ARM_THUMB_OFFSET
:
23539 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23540 /* Exactly what ranges, and where the offset is inserted depends
23541 on the type of instruction, we can establish this from the
23543 switch (newval
>> 12)
23545 case 4: /* PC load. */
23546 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23547 forced to zero for these loads; md_pcrel_from has already
23548 compensated for this. */
23550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23551 _("invalid offset, target not word aligned (0x%08lX)"),
23552 (((unsigned long) fixP
->fx_frag
->fr_address
23553 + (unsigned long) fixP
->fx_where
) & ~3)
23554 + (unsigned long) value
);
23556 if (value
& ~0x3fc)
23557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23558 _("invalid offset, value too big (0x%08lX)"),
23561 newval
|= value
>> 2;
23564 case 9: /* SP load/store. */
23565 if (value
& ~0x3fc)
23566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23567 _("invalid offset, value too big (0x%08lX)"),
23569 newval
|= value
>> 2;
23572 case 6: /* Word load/store. */
23574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23575 _("invalid offset, value too big (0x%08lX)"),
23577 newval
|= value
<< 4; /* 6 - 2. */
23580 case 7: /* Byte load/store. */
23582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23583 _("invalid offset, value too big (0x%08lX)"),
23585 newval
|= value
<< 6;
23588 case 8: /* Halfword load/store. */
23590 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23591 _("invalid offset, value too big (0x%08lX)"),
23593 newval
|= value
<< 5; /* 6 - 1. */
23597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23598 "Unable to process relocation for thumb opcode: %lx",
23599 (unsigned long) newval
);
23602 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23605 case BFD_RELOC_ARM_THUMB_ADD
:
23606 /* This is a complicated relocation, since we use it for all of
23607 the following immediate relocations:
23611 9bit ADD/SUB SP word-aligned
23612 10bit ADD PC/SP word-aligned
23614 The type of instruction being processed is encoded in the
23621 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23623 int rd
= (newval
>> 4) & 0xf;
23624 int rs
= newval
& 0xf;
23625 int subtract
= !!(newval
& 0x8000);
23627 /* Check for HI regs, only very restricted cases allowed:
23628 Adjusting SP, and using PC or SP to get an address. */
23629 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23630 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23632 _("invalid Hi register with immediate"));
23634 /* If value is negative, choose the opposite instruction. */
23638 subtract
= !subtract
;
23640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23641 _("immediate value out of range"));
23646 if (value
& ~0x1fc)
23647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23648 _("invalid immediate for stack address calculation"));
23649 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23650 newval
|= value
>> 2;
23652 else if (rs
== REG_PC
|| rs
== REG_SP
)
23654 /* PR gas/18541. If the addition is for a defined symbol
23655 within range of an ADR instruction then accept it. */
23658 && fixP
->fx_addsy
!= NULL
)
23662 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23663 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23664 || S_IS_WEAK (fixP
->fx_addsy
))
23666 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23667 _("address calculation needs a strongly defined nearby symbol"));
23671 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23673 /* Round up to the next 4-byte boundary. */
23678 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23682 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23683 _("symbol too far away"));
23693 if (subtract
|| value
& ~0x3fc)
23694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23695 _("invalid immediate for address calculation (value = 0x%08lX)"),
23696 (unsigned long) (subtract
? - value
: value
));
23697 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23699 newval
|= value
>> 2;
23704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23705 _("immediate value out of range"));
23706 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23707 newval
|= (rd
<< 8) | value
;
23712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23713 _("immediate value out of range"));
23714 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23715 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23718 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23721 case BFD_RELOC_ARM_THUMB_IMM
:
23722 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23723 if (value
< 0 || value
> 255)
23724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23725 _("invalid immediate: %ld is out of range"),
23728 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23731 case BFD_RELOC_ARM_THUMB_SHIFT
:
23732 /* 5bit shift value (0..32). LSL cannot take 32. */
23733 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23734 temp
= newval
& 0xf800;
23735 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23736 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23737 _("invalid shift value: %ld"), (long) value
);
23738 /* Shifts of zero must be encoded as LSL. */
23740 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23741 /* Shifts of 32 are encoded as zero. */
23742 else if (value
== 32)
23744 newval
|= value
<< 6;
23745 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23748 case BFD_RELOC_VTABLE_INHERIT
:
23749 case BFD_RELOC_VTABLE_ENTRY
:
23753 case BFD_RELOC_ARM_MOVW
:
23754 case BFD_RELOC_ARM_MOVT
:
23755 case BFD_RELOC_ARM_THUMB_MOVW
:
23756 case BFD_RELOC_ARM_THUMB_MOVT
:
23757 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23759 /* REL format relocations are limited to a 16-bit addend. */
23760 if (!fixP
->fx_done
)
23762 if (value
< -0x8000 || value
> 0x7fff)
23763 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23764 _("offset out of range"));
23766 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23767 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23772 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23773 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23775 newval
= get_thumb32_insn (buf
);
23776 newval
&= 0xfbf08f00;
23777 newval
|= (value
& 0xf000) << 4;
23778 newval
|= (value
& 0x0800) << 15;
23779 newval
|= (value
& 0x0700) << 4;
23780 newval
|= (value
& 0x00ff);
23781 put_thumb32_insn (buf
, newval
);
23785 newval
= md_chars_to_number (buf
, 4);
23786 newval
&= 0xfff0f000;
23787 newval
|= value
& 0x0fff;
23788 newval
|= (value
& 0xf000) << 4;
23789 md_number_to_chars (buf
, newval
, 4);
23794 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23795 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23796 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23797 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23798 gas_assert (!fixP
->fx_done
);
23801 bfd_boolean is_mov
;
23802 bfd_vma encoded_addend
= value
;
23804 /* Check that addend can be encoded in instruction. */
23805 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23807 _("the offset 0x%08lX is not representable"),
23808 (unsigned long) encoded_addend
);
23810 /* Extract the instruction. */
23811 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23812 is_mov
= (insn
& 0xf800) == 0x2000;
23817 if (!seg
->use_rela_p
)
23818 insn
|= encoded_addend
;
23824 /* Extract the instruction. */
23825 /* Encoding is the following
23830 /* The following conditions must be true :
23835 rd
= (insn
>> 4) & 0xf;
23837 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23839 _("Unable to process relocation for thumb opcode: %lx"),
23840 (unsigned long) insn
);
23842 /* Encode as ADD immediate8 thumb 1 code. */
23843 insn
= 0x3000 | (rd
<< 8);
23845 /* Place the encoded addend into the first 8 bits of the
23847 if (!seg
->use_rela_p
)
23848 insn
|= encoded_addend
;
23851 /* Update the instruction. */
23852 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23856 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23857 case BFD_RELOC_ARM_ALU_PC_G0
:
23858 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23859 case BFD_RELOC_ARM_ALU_PC_G1
:
23860 case BFD_RELOC_ARM_ALU_PC_G2
:
23861 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23862 case BFD_RELOC_ARM_ALU_SB_G0
:
23863 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23864 case BFD_RELOC_ARM_ALU_SB_G1
:
23865 case BFD_RELOC_ARM_ALU_SB_G2
:
23866 gas_assert (!fixP
->fx_done
);
23867 if (!seg
->use_rela_p
)
23870 bfd_vma encoded_addend
;
23871 bfd_vma addend_abs
= abs (value
);
23873 /* Check that the absolute value of the addend can be
23874 expressed as an 8-bit constant plus a rotation. */
23875 encoded_addend
= encode_arm_immediate (addend_abs
);
23876 if (encoded_addend
== (unsigned int) FAIL
)
23877 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23878 _("the offset 0x%08lX is not representable"),
23879 (unsigned long) addend_abs
);
23881 /* Extract the instruction. */
23882 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23884 /* If the addend is positive, use an ADD instruction.
23885 Otherwise use a SUB. Take care not to destroy the S bit. */
23886 insn
&= 0xff1fffff;
23892 /* Place the encoded addend into the first 12 bits of the
23894 insn
&= 0xfffff000;
23895 insn
|= encoded_addend
;
23897 /* Update the instruction. */
23898 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23902 case BFD_RELOC_ARM_LDR_PC_G0
:
23903 case BFD_RELOC_ARM_LDR_PC_G1
:
23904 case BFD_RELOC_ARM_LDR_PC_G2
:
23905 case BFD_RELOC_ARM_LDR_SB_G0
:
23906 case BFD_RELOC_ARM_LDR_SB_G1
:
23907 case BFD_RELOC_ARM_LDR_SB_G2
:
23908 gas_assert (!fixP
->fx_done
);
23909 if (!seg
->use_rela_p
)
23912 bfd_vma addend_abs
= abs (value
);
23914 /* Check that the absolute value of the addend can be
23915 encoded in 12 bits. */
23916 if (addend_abs
>= 0x1000)
23917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23918 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23919 (unsigned long) addend_abs
);
23921 /* Extract the instruction. */
23922 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23924 /* If the addend is negative, clear bit 23 of the instruction.
23925 Otherwise set it. */
23927 insn
&= ~(1 << 23);
23931 /* Place the absolute value of the addend into the first 12 bits
23932 of the instruction. */
23933 insn
&= 0xfffff000;
23934 insn
|= addend_abs
;
23936 /* Update the instruction. */
23937 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23941 case BFD_RELOC_ARM_LDRS_PC_G0
:
23942 case BFD_RELOC_ARM_LDRS_PC_G1
:
23943 case BFD_RELOC_ARM_LDRS_PC_G2
:
23944 case BFD_RELOC_ARM_LDRS_SB_G0
:
23945 case BFD_RELOC_ARM_LDRS_SB_G1
:
23946 case BFD_RELOC_ARM_LDRS_SB_G2
:
23947 gas_assert (!fixP
->fx_done
);
23948 if (!seg
->use_rela_p
)
23951 bfd_vma addend_abs
= abs (value
);
23953 /* Check that the absolute value of the addend can be
23954 encoded in 8 bits. */
23955 if (addend_abs
>= 0x100)
23956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23957 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23958 (unsigned long) addend_abs
);
23960 /* Extract the instruction. */
23961 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23963 /* If the addend is negative, clear bit 23 of the instruction.
23964 Otherwise set it. */
23966 insn
&= ~(1 << 23);
23970 /* Place the first four bits of the absolute value of the addend
23971 into the first 4 bits of the instruction, and the remaining
23972 four into bits 8 .. 11. */
23973 insn
&= 0xfffff0f0;
23974 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23976 /* Update the instruction. */
23977 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23981 case BFD_RELOC_ARM_LDC_PC_G0
:
23982 case BFD_RELOC_ARM_LDC_PC_G1
:
23983 case BFD_RELOC_ARM_LDC_PC_G2
:
23984 case BFD_RELOC_ARM_LDC_SB_G0
:
23985 case BFD_RELOC_ARM_LDC_SB_G1
:
23986 case BFD_RELOC_ARM_LDC_SB_G2
:
23987 gas_assert (!fixP
->fx_done
);
23988 if (!seg
->use_rela_p
)
23991 bfd_vma addend_abs
= abs (value
);
23993 /* Check that the absolute value of the addend is a multiple of
23994 four and, when divided by four, fits in 8 bits. */
23995 if (addend_abs
& 0x3)
23996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23997 _("bad offset 0x%08lX (must be word-aligned)"),
23998 (unsigned long) addend_abs
);
24000 if ((addend_abs
>> 2) > 0xff)
24001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24002 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24003 (unsigned long) addend_abs
);
24005 /* Extract the instruction. */
24006 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24008 /* If the addend is negative, clear bit 23 of the instruction.
24009 Otherwise set it. */
24011 insn
&= ~(1 << 23);
24015 /* Place the addend (divided by four) into the first eight
24016 bits of the instruction. */
24017 insn
&= 0xfffffff0;
24018 insn
|= addend_abs
>> 2;
24020 /* Update the instruction. */
24021 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24025 case BFD_RELOC_ARM_V4BX
:
24026 /* This will need to go in the object file. */
24030 case BFD_RELOC_UNUSED
:
24032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24033 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24037 /* Translate internal representation of relocation info to BFD target
24041 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24044 bfd_reloc_code_real_type code
;
24046 reloc
= XNEW (arelent
);
24048 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24049 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24050 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24052 if (fixp
->fx_pcrel
)
24054 if (section
->use_rela_p
)
24055 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24057 fixp
->fx_offset
= reloc
->address
;
24059 reloc
->addend
= fixp
->fx_offset
;
24061 switch (fixp
->fx_r_type
)
24064 if (fixp
->fx_pcrel
)
24066 code
= BFD_RELOC_8_PCREL
;
24071 if (fixp
->fx_pcrel
)
24073 code
= BFD_RELOC_16_PCREL
;
24078 if (fixp
->fx_pcrel
)
24080 code
= BFD_RELOC_32_PCREL
;
24084 case BFD_RELOC_ARM_MOVW
:
24085 if (fixp
->fx_pcrel
)
24087 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24091 case BFD_RELOC_ARM_MOVT
:
24092 if (fixp
->fx_pcrel
)
24094 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24098 case BFD_RELOC_ARM_THUMB_MOVW
:
24099 if (fixp
->fx_pcrel
)
24101 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24105 case BFD_RELOC_ARM_THUMB_MOVT
:
24106 if (fixp
->fx_pcrel
)
24108 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24112 case BFD_RELOC_NONE
:
24113 case BFD_RELOC_ARM_PCREL_BRANCH
:
24114 case BFD_RELOC_ARM_PCREL_BLX
:
24115 case BFD_RELOC_RVA
:
24116 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24117 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24118 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24119 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24120 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24121 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24122 case BFD_RELOC_VTABLE_ENTRY
:
24123 case BFD_RELOC_VTABLE_INHERIT
:
24125 case BFD_RELOC_32_SECREL
:
24127 code
= fixp
->fx_r_type
;
24130 case BFD_RELOC_THUMB_PCREL_BLX
:
24132 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24133 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24136 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24139 case BFD_RELOC_ARM_LITERAL
:
24140 case BFD_RELOC_ARM_HWLITERAL
:
24141 /* If this is called then the a literal has
24142 been referenced across a section boundary. */
24143 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24144 _("literal referenced across section boundary"));
24148 case BFD_RELOC_ARM_TLS_CALL
:
24149 case BFD_RELOC_ARM_THM_TLS_CALL
:
24150 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24151 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24152 case BFD_RELOC_ARM_GOT32
:
24153 case BFD_RELOC_ARM_GOTOFF
:
24154 case BFD_RELOC_ARM_GOT_PREL
:
24155 case BFD_RELOC_ARM_PLT32
:
24156 case BFD_RELOC_ARM_TARGET1
:
24157 case BFD_RELOC_ARM_ROSEGREL32
:
24158 case BFD_RELOC_ARM_SBREL32
:
24159 case BFD_RELOC_ARM_PREL31
:
24160 case BFD_RELOC_ARM_TARGET2
:
24161 case BFD_RELOC_ARM_TLS_LDO32
:
24162 case BFD_RELOC_ARM_PCREL_CALL
:
24163 case BFD_RELOC_ARM_PCREL_JUMP
:
24164 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24165 case BFD_RELOC_ARM_ALU_PC_G0
:
24166 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24167 case BFD_RELOC_ARM_ALU_PC_G1
:
24168 case BFD_RELOC_ARM_ALU_PC_G2
:
24169 case BFD_RELOC_ARM_LDR_PC_G0
:
24170 case BFD_RELOC_ARM_LDR_PC_G1
:
24171 case BFD_RELOC_ARM_LDR_PC_G2
:
24172 case BFD_RELOC_ARM_LDRS_PC_G0
:
24173 case BFD_RELOC_ARM_LDRS_PC_G1
:
24174 case BFD_RELOC_ARM_LDRS_PC_G2
:
24175 case BFD_RELOC_ARM_LDC_PC_G0
:
24176 case BFD_RELOC_ARM_LDC_PC_G1
:
24177 case BFD_RELOC_ARM_LDC_PC_G2
:
24178 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24179 case BFD_RELOC_ARM_ALU_SB_G0
:
24180 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24181 case BFD_RELOC_ARM_ALU_SB_G1
:
24182 case BFD_RELOC_ARM_ALU_SB_G2
:
24183 case BFD_RELOC_ARM_LDR_SB_G0
:
24184 case BFD_RELOC_ARM_LDR_SB_G1
:
24185 case BFD_RELOC_ARM_LDR_SB_G2
:
24186 case BFD_RELOC_ARM_LDRS_SB_G0
:
24187 case BFD_RELOC_ARM_LDRS_SB_G1
:
24188 case BFD_RELOC_ARM_LDRS_SB_G2
:
24189 case BFD_RELOC_ARM_LDC_SB_G0
:
24190 case BFD_RELOC_ARM_LDC_SB_G1
:
24191 case BFD_RELOC_ARM_LDC_SB_G2
:
24192 case BFD_RELOC_ARM_V4BX
:
24193 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24194 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24195 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24196 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24197 code
= fixp
->fx_r_type
;
24200 case BFD_RELOC_ARM_TLS_GOTDESC
:
24201 case BFD_RELOC_ARM_TLS_GD32
:
24202 case BFD_RELOC_ARM_TLS_LE32
:
24203 case BFD_RELOC_ARM_TLS_IE32
:
24204 case BFD_RELOC_ARM_TLS_LDM32
:
24205 /* BFD will include the symbol's address in the addend.
24206 But we don't want that, so subtract it out again here. */
24207 if (!S_IS_COMMON (fixp
->fx_addsy
))
24208 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24209 code
= fixp
->fx_r_type
;
24213 case BFD_RELOC_ARM_IMMEDIATE
:
24214 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24215 _("internal relocation (type: IMMEDIATE) not fixed up"));
24218 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24219 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24220 _("ADRL used for a symbol not defined in the same file"));
24223 case BFD_RELOC_ARM_OFFSET_IMM
:
24224 if (section
->use_rela_p
)
24226 code
= fixp
->fx_r_type
;
24230 if (fixp
->fx_addsy
!= NULL
24231 && !S_IS_DEFINED (fixp
->fx_addsy
)
24232 && S_IS_LOCAL (fixp
->fx_addsy
))
24234 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24235 _("undefined local label `%s'"),
24236 S_GET_NAME (fixp
->fx_addsy
));
24240 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24241 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24248 switch (fixp
->fx_r_type
)
24250 case BFD_RELOC_NONE
: type
= "NONE"; break;
24251 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24252 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24253 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24254 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24255 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24256 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24257 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24258 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24259 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24260 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24261 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24262 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24263 default: type
= _("<unknown>"); break;
24265 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24266 _("cannot represent %s relocation in this object file format"),
24273 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24275 && fixp
->fx_addsy
== GOT_symbol
)
24277 code
= BFD_RELOC_ARM_GOTPC
;
24278 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24282 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24284 if (reloc
->howto
== NULL
)
24286 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24287 _("cannot represent %s relocation in this object file format"),
24288 bfd_get_reloc_code_name (code
));
24292 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24293 vtable entry to be used in the relocation's section offset. */
24294 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24295 reloc
->address
= fixp
->fx_offset
;
24300 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24303 cons_fix_new_arm (fragS
* frag
,
24307 bfd_reloc_code_real_type reloc
)
24312 FIXME: @@ Should look at CPU word size. */
24316 reloc
= BFD_RELOC_8
;
24319 reloc
= BFD_RELOC_16
;
24323 reloc
= BFD_RELOC_32
;
24326 reloc
= BFD_RELOC_64
;
24331 if (exp
->X_op
== O_secrel
)
24333 exp
->X_op
= O_symbol
;
24334 reloc
= BFD_RELOC_32_SECREL
;
24338 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24341 #if defined (OBJ_COFF)
24343 arm_validate_fix (fixS
* fixP
)
24345 /* If the destination of the branch is a defined symbol which does not have
24346 the THUMB_FUNC attribute, then we must be calling a function which has
24347 the (interfacearm) attribute. We look for the Thumb entry point to that
24348 function and change the branch to refer to that function instead. */
24349 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24350 && fixP
->fx_addsy
!= NULL
24351 && S_IS_DEFINED (fixP
->fx_addsy
)
24352 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24354 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24361 arm_force_relocation (struct fix
* fixp
)
24363 #if defined (OBJ_COFF) && defined (TE_PE)
24364 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24368 /* In case we have a call or a branch to a function in ARM ISA mode from
24369 a thumb function or vice-versa force the relocation. These relocations
24370 are cleared off for some cores that might have blx and simple transformations
24374 switch (fixp
->fx_r_type
)
24376 case BFD_RELOC_ARM_PCREL_JUMP
:
24377 case BFD_RELOC_ARM_PCREL_CALL
:
24378 case BFD_RELOC_THUMB_PCREL_BLX
:
24379 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24383 case BFD_RELOC_ARM_PCREL_BLX
:
24384 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24385 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24386 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24387 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24396 /* Resolve these relocations even if the symbol is extern or weak.
24397 Technically this is probably wrong due to symbol preemption.
24398 In practice these relocations do not have enough range to be useful
24399 at dynamic link time, and some code (e.g. in the Linux kernel)
24400 expects these references to be resolved. */
24401 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24402 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24403 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24404 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24405 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24406 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24407 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24408 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24409 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24410 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24411 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24412 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24413 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24414 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24417 /* Always leave these relocations for the linker. */
24418 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24419 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24420 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24423 /* Always generate relocations against function symbols. */
24424 if (fixp
->fx_r_type
== BFD_RELOC_32
24426 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24429 return generic_force_reloc (fixp
);
24432 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24433 /* Relocations against function names must be left unadjusted,
24434 so that the linker can use this information to generate interworking
24435 stubs. The MIPS version of this function
24436 also prevents relocations that are mips-16 specific, but I do not
24437 know why it does this.
24440 There is one other problem that ought to be addressed here, but
24441 which currently is not: Taking the address of a label (rather
24442 than a function) and then later jumping to that address. Such
24443 addresses also ought to have their bottom bit set (assuming that
24444 they reside in Thumb code), but at the moment they will not. */
24447 arm_fix_adjustable (fixS
* fixP
)
24449 if (fixP
->fx_addsy
== NULL
)
24452 /* Preserve relocations against symbols with function type. */
24453 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24456 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24457 && fixP
->fx_subsy
== NULL
)
24460 /* We need the symbol name for the VTABLE entries. */
24461 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24462 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24465 /* Don't allow symbols to be discarded on GOT related relocs. */
24466 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24467 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24468 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24469 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24470 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24471 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24472 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24473 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24474 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24475 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24476 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24477 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24478 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24479 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24482 /* Similarly for group relocations. */
24483 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24484 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24485 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24488 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24489 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24490 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24491 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24492 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24493 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24494 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24495 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24496 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24499 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24500 offsets, so keep these symbols. */
24501 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24502 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24507 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24511 elf32_arm_target_format (void)
24514 return (target_big_endian
24515 ? "elf32-bigarm-symbian"
24516 : "elf32-littlearm-symbian");
24517 #elif defined (TE_VXWORKS)
24518 return (target_big_endian
24519 ? "elf32-bigarm-vxworks"
24520 : "elf32-littlearm-vxworks");
24521 #elif defined (TE_NACL)
24522 return (target_big_endian
24523 ? "elf32-bigarm-nacl"
24524 : "elf32-littlearm-nacl");
24526 if (target_big_endian
)
24527 return "elf32-bigarm";
24529 return "elf32-littlearm";
24534 armelf_frob_symbol (symbolS
* symp
,
24537 elf_frob_symbol (symp
, puntp
);
24541 /* MD interface: Finalization. */
24546 literal_pool
* pool
;
24548 /* Ensure that all the IT blocks are properly closed. */
24549 check_it_blocks_finished ();
24551 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24553 /* Put it at the end of the relevant section. */
24554 subseg_set (pool
->section
, pool
->sub_section
);
24556 arm_elf_change_section ();
24563 /* Remove any excess mapping symbols generated for alignment frags in
24564 SEC. We may have created a mapping symbol before a zero byte
24565 alignment; remove it if there's a mapping symbol after the
24568 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24569 void *dummy ATTRIBUTE_UNUSED
)
24571 segment_info_type
*seginfo
= seg_info (sec
);
24574 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24577 for (fragp
= seginfo
->frchainP
->frch_root
;
24579 fragp
= fragp
->fr_next
)
24581 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24582 fragS
*next
= fragp
->fr_next
;
24584 /* Variable-sized frags have been converted to fixed size by
24585 this point. But if this was variable-sized to start with,
24586 there will be a fixed-size frag after it. So don't handle
24588 if (sym
== NULL
|| next
== NULL
)
24591 if (S_GET_VALUE (sym
) < next
->fr_address
)
24592 /* Not at the end of this frag. */
24594 know (S_GET_VALUE (sym
) == next
->fr_address
);
24598 if (next
->tc_frag_data
.first_map
!= NULL
)
24600 /* Next frag starts with a mapping symbol. Discard this
24602 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24606 if (next
->fr_next
== NULL
)
24608 /* This mapping symbol is at the end of the section. Discard
24610 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24611 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24615 /* As long as we have empty frags without any mapping symbols,
24617 /* If the next frag is non-empty and does not start with a
24618 mapping symbol, then this mapping symbol is required. */
24619 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24622 next
= next
->fr_next
;
24624 while (next
!= NULL
);
24629 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24633 arm_adjust_symtab (void)
24638 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24640 if (ARM_IS_THUMB (sym
))
24642 if (THUMB_IS_FUNC (sym
))
24644 /* Mark the symbol as a Thumb function. */
24645 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24646 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24647 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24649 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24650 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24652 as_bad (_("%s: unexpected function type: %d"),
24653 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24655 else switch (S_GET_STORAGE_CLASS (sym
))
24658 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24661 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24664 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24672 if (ARM_IS_INTERWORK (sym
))
24673 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24680 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24682 if (ARM_IS_THUMB (sym
))
24684 elf_symbol_type
* elf_sym
;
24686 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24687 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24689 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24690 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24692 /* If it's a .thumb_func, declare it as so,
24693 otherwise tag label as .code 16. */
24694 if (THUMB_IS_FUNC (sym
))
24695 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24696 ST_BRANCH_TO_THUMB
);
24697 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24698 elf_sym
->internal_elf_sym
.st_info
=
24699 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24704 /* Remove any overlapping mapping symbols generated by alignment frags. */
24705 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24706 /* Now do generic ELF adjustments. */
24707 elf_adjust_symtab ();
24711 /* MD interface: Initialization. */
24714 set_constant_flonums (void)
24718 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24719 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24723 /* Auto-select Thumb mode if it's the only available instruction set for the
24724 given architecture. */
24727 autoselect_thumb_from_cpu_variant (void)
24729 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24730 opcode_select (16);
24739 if ( (arm_ops_hsh
= hash_new ()) == NULL
24740 || (arm_cond_hsh
= hash_new ()) == NULL
24741 || (arm_shift_hsh
= hash_new ()) == NULL
24742 || (arm_psr_hsh
= hash_new ()) == NULL
24743 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24744 || (arm_reg_hsh
= hash_new ()) == NULL
24745 || (arm_reloc_hsh
= hash_new ()) == NULL
24746 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24747 as_fatal (_("virtual memory exhausted"));
24749 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24750 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24751 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24752 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24753 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24754 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24755 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24756 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24757 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24758 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24759 (void *) (v7m_psrs
+ i
));
24760 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24761 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24763 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24765 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24766 (void *) (barrier_opt_names
+ i
));
24768 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24770 struct reloc_entry
* entry
= reloc_names
+ i
;
24772 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24773 /* This makes encode_branch() use the EABI versions of this relocation. */
24774 entry
->reloc
= BFD_RELOC_UNUSED
;
24776 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24780 set_constant_flonums ();
24782 /* Set the cpu variant based on the command-line options. We prefer
24783 -mcpu= over -march= if both are set (as for GCC); and we prefer
24784 -mfpu= over any other way of setting the floating point unit.
24785 Use of legacy options with new options are faulted. */
24788 if (mcpu_cpu_opt
|| march_cpu_opt
)
24789 as_bad (_("use of old and new-style options to set CPU type"));
24791 mcpu_cpu_opt
= legacy_cpu
;
24793 else if (!mcpu_cpu_opt
)
24794 mcpu_cpu_opt
= march_cpu_opt
;
24799 as_bad (_("use of old and new-style options to set FPU type"));
24801 mfpu_opt
= legacy_fpu
;
24803 else if (!mfpu_opt
)
24805 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24806 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24807 /* Some environments specify a default FPU. If they don't, infer it
24808 from the processor. */
24810 mfpu_opt
= mcpu_fpu_opt
;
24812 mfpu_opt
= march_fpu_opt
;
24814 mfpu_opt
= &fpu_default
;
24820 if (mcpu_cpu_opt
!= NULL
)
24821 mfpu_opt
= &fpu_default
;
24822 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24823 mfpu_opt
= &fpu_arch_vfp_v2
;
24825 mfpu_opt
= &fpu_arch_fpa
;
24831 mcpu_cpu_opt
= &cpu_default
;
24832 selected_cpu
= cpu_default
;
24834 else if (no_cpu_selected ())
24835 selected_cpu
= cpu_default
;
24838 selected_cpu
= *mcpu_cpu_opt
;
24840 mcpu_cpu_opt
= &arm_arch_any
;
24843 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24845 autoselect_thumb_from_cpu_variant ();
24847 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24849 #if defined OBJ_COFF || defined OBJ_ELF
24851 unsigned int flags
= 0;
24853 #if defined OBJ_ELF
24854 flags
= meabi_flags
;
24856 switch (meabi_flags
)
24858 case EF_ARM_EABI_UNKNOWN
:
24860 /* Set the flags in the private structure. */
24861 if (uses_apcs_26
) flags
|= F_APCS26
;
24862 if (support_interwork
) flags
|= F_INTERWORK
;
24863 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24864 if (pic_code
) flags
|= F_PIC
;
24865 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24866 flags
|= F_SOFT_FLOAT
;
24868 switch (mfloat_abi_opt
)
24870 case ARM_FLOAT_ABI_SOFT
:
24871 case ARM_FLOAT_ABI_SOFTFP
:
24872 flags
|= F_SOFT_FLOAT
;
24875 case ARM_FLOAT_ABI_HARD
:
24876 if (flags
& F_SOFT_FLOAT
)
24877 as_bad (_("hard-float conflicts with specified fpu"));
24881 /* Using pure-endian doubles (even if soft-float). */
24882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24883 flags
|= F_VFP_FLOAT
;
24885 #if defined OBJ_ELF
24886 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24887 flags
|= EF_ARM_MAVERICK_FLOAT
;
24890 case EF_ARM_EABI_VER4
:
24891 case EF_ARM_EABI_VER5
:
24892 /* No additional flags to set. */
24899 bfd_set_private_flags (stdoutput
, flags
);
24901 /* We have run out flags in the COFF header to encode the
24902 status of ATPCS support, so instead we create a dummy,
24903 empty, debug section called .arm.atpcs. */
24908 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24912 bfd_set_section_flags
24913 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24914 bfd_set_section_size (stdoutput
, sec
, 0);
24915 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24921 /* Record the CPU type as well. */
24922 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24923 mach
= bfd_mach_arm_iWMMXt2
;
24924 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24925 mach
= bfd_mach_arm_iWMMXt
;
24926 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24927 mach
= bfd_mach_arm_XScale
;
24928 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24929 mach
= bfd_mach_arm_ep9312
;
24930 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24931 mach
= bfd_mach_arm_5TE
;
24932 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24934 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24935 mach
= bfd_mach_arm_5T
;
24937 mach
= bfd_mach_arm_5
;
24939 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24941 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24942 mach
= bfd_mach_arm_4T
;
24944 mach
= bfd_mach_arm_4
;
24946 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24947 mach
= bfd_mach_arm_3M
;
24948 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24949 mach
= bfd_mach_arm_3
;
24950 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24951 mach
= bfd_mach_arm_2a
;
24952 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24953 mach
= bfd_mach_arm_2
;
24955 mach
= bfd_mach_arm_unknown
;
24957 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24960 /* Command line processing. */
24963 Invocation line includes a switch not recognized by the base assembler.
24964 See if it's a processor-specific option.
24966 This routine is somewhat complicated by the need for backwards
24967 compatibility (since older releases of gcc can't be changed).
24968 The new options try to make the interface as compatible as
24971 New options (supported) are:
24973 -mcpu=<cpu name> Assemble for selected processor
24974 -march=<architecture name> Assemble for selected architecture
24975 -mfpu=<fpu architecture> Assemble for selected FPU.
24976 -EB/-mbig-endian Big-endian
24977 -EL/-mlittle-endian Little-endian
24978 -k Generate PIC code
24979 -mthumb Start in Thumb mode
24980 -mthumb-interwork Code supports ARM/Thumb interworking
24982 -m[no-]warn-deprecated Warn about deprecated features
24983 -m[no-]warn-syms Warn when symbols match instructions
24985 For now we will also provide support for:
24987 -mapcs-32 32-bit Program counter
24988 -mapcs-26 26-bit Program counter
24989 -macps-float Floats passed in FP registers
24990 -mapcs-reentrant Reentrant code
24992 (sometime these will probably be replaced with -mapcs=<list of options>
24993 and -matpcs=<list of options>)
24995 The remaining options are only supported for back-wards compatibility.
24996 Cpu variants, the arm part is optional:
24997 -m[arm]1 Currently not supported.
24998 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24999 -m[arm]3 Arm 3 processor
25000 -m[arm]6[xx], Arm 6 processors
25001 -m[arm]7[xx][t][[d]m] Arm 7 processors
25002 -m[arm]8[10] Arm 8 processors
25003 -m[arm]9[20][tdmi] Arm 9 processors
25004 -mstrongarm[110[0]] StrongARM processors
25005 -mxscale XScale processors
25006 -m[arm]v[2345[t[e]]] Arm architectures
25007 -mall All (except the ARM1)
25009 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25010 -mfpe-old (No float load/store multiples)
25011 -mvfpxd VFP Single precision
25013 -mno-fpu Disable all floating point instructions
25015 The following CPU names are recognized:
25016 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25017 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25018 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25019 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25020 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25021 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25022 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25026 const char * md_shortopts
= "m:k";
25028 #ifdef ARM_BI_ENDIAN
25029 #define OPTION_EB (OPTION_MD_BASE + 0)
25030 #define OPTION_EL (OPTION_MD_BASE + 1)
25032 #if TARGET_BYTES_BIG_ENDIAN
25033 #define OPTION_EB (OPTION_MD_BASE + 0)
25035 #define OPTION_EL (OPTION_MD_BASE + 1)
25038 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25040 struct option md_longopts
[] =
25043 {"EB", no_argument
, NULL
, OPTION_EB
},
25046 {"EL", no_argument
, NULL
, OPTION_EL
},
25048 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25049 {NULL
, no_argument
, NULL
, 0}
25053 size_t md_longopts_size
= sizeof (md_longopts
);
25055 struct arm_option_table
25057 const char *option
; /* Option name to match. */
25058 const char *help
; /* Help information. */
25059 int *var
; /* Variable to change. */
25060 int value
; /* What to change it to. */
25061 const char *deprecated
; /* If non-null, print this message. */
25064 struct arm_option_table arm_opts
[] =
25066 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25067 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25068 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25069 &support_interwork
, 1, NULL
},
25070 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25071 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25072 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25074 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25075 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25076 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25077 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25080 /* These are recognized by the assembler, but have no affect on code. */
25081 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25082 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25084 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25085 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25086 &warn_on_deprecated
, 0, NULL
},
25087 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25088 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25089 {NULL
, NULL
, NULL
, 0, NULL
}
25092 struct arm_legacy_option_table
25094 const char *option
; /* Option name to match. */
25095 const arm_feature_set
**var
; /* Variable to change. */
25096 const arm_feature_set value
; /* What to change it to. */
25097 const char *deprecated
; /* If non-null, print this message. */
25100 const struct arm_legacy_option_table arm_legacy_opts
[] =
25102 /* DON'T add any new processors to this list -- we want the whole list
25103 to go away... Add them to the processors table instead. */
25104 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25105 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25106 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25107 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25108 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25109 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25110 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25111 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25112 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25113 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25114 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25115 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25116 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25117 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25118 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25119 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25120 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25121 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25122 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25123 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25124 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25125 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25126 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25127 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25128 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25129 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25130 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25131 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25132 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25133 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25134 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25135 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25136 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25137 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25138 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25139 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25140 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25141 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25142 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25143 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25144 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25145 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25146 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25147 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25148 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25149 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25150 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25151 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25152 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25153 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25154 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25155 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25156 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25157 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25158 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25159 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25160 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25161 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25162 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25163 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25164 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25165 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25166 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25167 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25168 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25169 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25170 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25171 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25172 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25173 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25174 N_("use -mcpu=strongarm110")},
25175 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25176 N_("use -mcpu=strongarm1100")},
25177 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25178 N_("use -mcpu=strongarm1110")},
25179 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25180 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25181 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25183 /* Architecture variants -- don't add any more to this list either. */
25184 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25185 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25186 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25187 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25188 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25189 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25190 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25191 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25192 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25193 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25194 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25195 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25196 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25197 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25198 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25199 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25200 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25201 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25203 /* Floating point variants -- don't add any more to this list either. */
25204 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25205 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25206 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25207 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25208 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25210 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25213 struct arm_cpu_option_table
25217 const arm_feature_set value
;
25218 /* For some CPUs we assume an FPU unless the user explicitly sets
25220 const arm_feature_set default_fpu
;
25221 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25223 const char *canonical_name
;
25226 /* This list should, at a minimum, contain all the cpu names
25227 recognized by GCC. */
25228 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25229 static const struct arm_cpu_option_table arm_cpus
[] =
25231 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25232 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25233 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25234 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25235 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25236 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25237 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25238 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25239 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25240 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25241 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25242 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25243 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25244 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25245 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25246 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25247 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25248 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25249 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25250 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25251 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25252 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25253 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25254 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25255 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25256 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25257 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25258 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25259 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25260 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25261 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25262 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25263 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25264 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25265 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25266 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25267 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25268 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25269 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25270 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25271 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25272 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25273 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25274 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25275 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25276 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25277 /* For V5 or later processors we default to using VFP; but the user
25278 should really set the FPU type explicitly. */
25279 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25280 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25281 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25282 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25283 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25284 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25285 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25286 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25287 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25288 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25289 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25290 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25291 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25292 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25293 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25294 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25295 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25296 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25297 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25298 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25300 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25301 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25302 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25303 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25304 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25305 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25306 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25307 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25308 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25310 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25311 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25312 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25313 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25314 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25315 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25316 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25317 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25318 FPU_NONE
, "Cortex-A5"),
25319 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25321 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25322 ARM_FEATURE_COPROC (FPU_VFP_V3
25323 | FPU_NEON_EXT_V1
),
25325 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25326 ARM_FEATURE_COPROC (FPU_VFP_V3
25327 | FPU_NEON_EXT_V1
),
25329 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25331 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25333 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25335 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25337 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25339 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25341 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25343 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25345 ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25347 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25348 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25350 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25351 FPU_NONE
, "Cortex-R5"),
25352 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25353 FPU_ARCH_VFP_V3D16
,
25355 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25356 FPU_ARCH_VFP_V3D16
,
25358 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25359 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25360 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25361 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25362 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25363 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25364 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25367 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25371 /* ??? XSCALE is really an architecture. */
25372 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25373 /* ??? iwmmxt is not a processor. */
25374 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25375 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25376 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25378 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25379 FPU_ARCH_MAVERICK
, "ARM920T"),
25380 /* Marvell processors. */
25381 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25383 ARM_EXT2_V6T2_V8M
),
25384 FPU_ARCH_VFP_V3D16
, NULL
),
25385 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25387 ARM_EXT2_V6T2_V8M
),
25388 FPU_ARCH_NEON_VFP_V4
, NULL
),
25389 /* APM X-Gene family. */
25390 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25392 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25395 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25399 struct arm_arch_option_table
25403 const arm_feature_set value
;
25404 const arm_feature_set default_fpu
;
25407 /* This list should, at a minimum, contain all the architecture names
25408 recognized by GCC. */
25409 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25410 static const struct arm_arch_option_table arm_archs
[] =
25412 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25413 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25414 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25415 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25416 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25417 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25418 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25419 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25420 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25421 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25422 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25423 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25424 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25425 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25426 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25427 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25428 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25429 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25430 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25431 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25432 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25433 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25434 kept to preserve existing behaviour. */
25435 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25436 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25437 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25438 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25439 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25440 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25441 kept to preserve existing behaviour. */
25442 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25443 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25444 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25445 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25446 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25447 /* The official spelling of the ARMv7 profile variants is the dashed form.
25448 Accept the non-dashed form for compatibility with old toolchains. */
25449 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25450 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25451 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25452 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25453 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25454 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25455 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25456 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25457 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25458 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25459 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25460 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25461 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25462 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25463 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25464 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25465 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25467 #undef ARM_ARCH_OPT
25469 /* ISA extensions in the co-processor and main instruction set space. */
25470 struct arm_option_extension_value_table
25474 const arm_feature_set merge_value
;
25475 const arm_feature_set clear_value
;
25476 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25477 indicates that an extension is available for all architectures while
25478 ARM_ANY marks an empty entry. */
25479 const arm_feature_set allowed_archs
[2];
25482 /* The following table must be in alphabetical order with a NULL last entry.
25484 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25485 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25486 static const struct arm_option_extension_value_table arm_extensions
[] =
25488 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25489 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25490 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25491 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25492 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25493 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25494 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25495 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25496 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25497 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25498 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25499 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25501 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25502 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25503 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25504 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25505 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25506 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25507 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25508 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25509 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25510 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25511 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25512 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25513 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25514 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25515 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25516 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25517 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25518 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25519 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25520 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25521 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
25522 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
25523 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25524 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25525 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25526 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25527 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25528 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25529 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25530 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25531 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25532 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25533 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25534 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25536 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25537 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25538 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25539 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
25540 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
25544 /* ISA floating-point and Advanced SIMD extensions. */
25545 struct arm_option_fpu_value_table
25548 const arm_feature_set value
;
25551 /* This list should, at a minimum, contain all the fpu names
25552 recognized by GCC. */
25553 static const struct arm_option_fpu_value_table arm_fpus
[] =
25555 {"softfpa", FPU_NONE
},
25556 {"fpe", FPU_ARCH_FPE
},
25557 {"fpe2", FPU_ARCH_FPE
},
25558 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25559 {"fpa", FPU_ARCH_FPA
},
25560 {"fpa10", FPU_ARCH_FPA
},
25561 {"fpa11", FPU_ARCH_FPA
},
25562 {"arm7500fe", FPU_ARCH_FPA
},
25563 {"softvfp", FPU_ARCH_VFP
},
25564 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25565 {"vfp", FPU_ARCH_VFP_V2
},
25566 {"vfp9", FPU_ARCH_VFP_V2
},
25567 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25568 {"vfp10", FPU_ARCH_VFP_V2
},
25569 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25570 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25571 {"vfpv2", FPU_ARCH_VFP_V2
},
25572 {"vfpv3", FPU_ARCH_VFP_V3
},
25573 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25574 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25575 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25576 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25577 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25578 {"arm1020t", FPU_ARCH_VFP_V1
},
25579 {"arm1020e", FPU_ARCH_VFP_V2
},
25580 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25581 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25582 {"maverick", FPU_ARCH_MAVERICK
},
25583 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25584 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25585 {"vfpv4", FPU_ARCH_VFP_V4
},
25586 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25587 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25588 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25589 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25590 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25591 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25592 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25593 {"crypto-neon-fp-armv8",
25594 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25595 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25596 {"crypto-neon-fp-armv8.1",
25597 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25598 {NULL
, ARM_ARCH_NONE
}
25601 struct arm_option_value_table
25607 static const struct arm_option_value_table arm_float_abis
[] =
25609 {"hard", ARM_FLOAT_ABI_HARD
},
25610 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25611 {"soft", ARM_FLOAT_ABI_SOFT
},
25616 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25617 static const struct arm_option_value_table arm_eabis
[] =
25619 {"gnu", EF_ARM_EABI_UNKNOWN
},
25620 {"4", EF_ARM_EABI_VER4
},
25621 {"5", EF_ARM_EABI_VER5
},
25626 struct arm_long_option_table
25628 const char * option
; /* Substring to match. */
25629 const char * help
; /* Help information. */
25630 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25631 const char * deprecated
; /* If non-null, print this message. */
25635 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25637 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25639 /* We insist on extensions being specified in alphabetical order, and with
25640 extensions being added before being removed. We achieve this by having
25641 the global ARM_EXTENSIONS table in alphabetical order, and using the
25642 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25643 or removing it (0) and only allowing it to change in the order
25645 const struct arm_option_extension_value_table
* opt
= NULL
;
25646 const arm_feature_set arm_any
= ARM_ANY
;
25647 int adding_value
= -1;
25649 /* Copy the feature set, so that we can modify it. */
25650 *ext_set
= **opt_p
;
25653 while (str
!= NULL
&& *str
!= 0)
25660 as_bad (_("invalid architectural extension"));
25665 ext
= strchr (str
, '+');
25670 len
= strlen (str
);
25672 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25674 if (adding_value
!= 0)
25677 opt
= arm_extensions
;
25685 if (adding_value
== -1)
25688 opt
= arm_extensions
;
25690 else if (adding_value
!= 1)
25692 as_bad (_("must specify extensions to add before specifying "
25693 "those to remove"));
25700 as_bad (_("missing architectural extension"));
25704 gas_assert (adding_value
!= -1);
25705 gas_assert (opt
!= NULL
);
25707 /* Scan over the options table trying to find an exact match. */
25708 for (; opt
->name
!= NULL
; opt
++)
25709 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25711 int i
, nb_allowed_archs
=
25712 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
25713 /* Check we can apply the extension to this architecture. */
25714 for (i
= 0; i
< nb_allowed_archs
; i
++)
25717 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
25719 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *ext_set
))
25722 if (i
== nb_allowed_archs
)
25724 as_bad (_("extension does not apply to the base architecture"));
25728 /* Add or remove the extension. */
25730 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25732 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25737 if (opt
->name
== NULL
)
25739 /* Did we fail to find an extension because it wasn't specified in
25740 alphabetical order, or because it does not exist? */
25742 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25743 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25746 if (opt
->name
== NULL
)
25747 as_bad (_("unknown architectural extension `%s'"), str
);
25749 as_bad (_("architectural extensions must be specified in "
25750 "alphabetical order"));
25756 /* We should skip the extension we've just matched the next time
25768 arm_parse_cpu (const char *str
)
25770 const struct arm_cpu_option_table
*opt
;
25771 const char *ext
= strchr (str
, '+');
25777 len
= strlen (str
);
25781 as_bad (_("missing cpu name `%s'"), str
);
25785 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25786 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25788 mcpu_cpu_opt
= &opt
->value
;
25789 mcpu_fpu_opt
= &opt
->default_fpu
;
25790 if (opt
->canonical_name
)
25792 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25793 strcpy (selected_cpu_name
, opt
->canonical_name
);
25799 if (len
>= sizeof selected_cpu_name
)
25800 len
= (sizeof selected_cpu_name
) - 1;
25802 for (i
= 0; i
< len
; i
++)
25803 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25804 selected_cpu_name
[i
] = 0;
25808 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25813 as_bad (_("unknown cpu `%s'"), str
);
25818 arm_parse_arch (const char *str
)
25820 const struct arm_arch_option_table
*opt
;
25821 const char *ext
= strchr (str
, '+');
25827 len
= strlen (str
);
25831 as_bad (_("missing architecture name `%s'"), str
);
25835 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25836 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25838 march_cpu_opt
= &opt
->value
;
25839 march_fpu_opt
= &opt
->default_fpu
;
25840 strcpy (selected_cpu_name
, opt
->name
);
25843 return arm_parse_extension (ext
, &march_cpu_opt
);
25848 as_bad (_("unknown architecture `%s'\n"), str
);
25853 arm_parse_fpu (const char * str
)
25855 const struct arm_option_fpu_value_table
* opt
;
25857 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25858 if (streq (opt
->name
, str
))
25860 mfpu_opt
= &opt
->value
;
25864 as_bad (_("unknown floating point format `%s'\n"), str
);
25869 arm_parse_float_abi (const char * str
)
25871 const struct arm_option_value_table
* opt
;
25873 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25874 if (streq (opt
->name
, str
))
25876 mfloat_abi_opt
= opt
->value
;
25880 as_bad (_("unknown floating point abi `%s'\n"), str
);
25886 arm_parse_eabi (const char * str
)
25888 const struct arm_option_value_table
*opt
;
25890 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25891 if (streq (opt
->name
, str
))
25893 meabi_flags
= opt
->value
;
25896 as_bad (_("unknown EABI `%s'\n"), str
);
25902 arm_parse_it_mode (const char * str
)
25904 bfd_boolean ret
= TRUE
;
25906 if (streq ("arm", str
))
25907 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25908 else if (streq ("thumb", str
))
25909 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25910 else if (streq ("always", str
))
25911 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25912 else if (streq ("never", str
))
25913 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25916 as_bad (_("unknown implicit IT mode `%s', should be "\
25917 "arm, thumb, always, or never."), str
);
25925 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
25927 codecomposer_syntax
= TRUE
;
25928 arm_comment_chars
[0] = ';';
25929 arm_line_separator_chars
[0] = 0;
25933 struct arm_long_option_table arm_long_opts
[] =
25935 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25936 arm_parse_cpu
, NULL
},
25937 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25938 arm_parse_arch
, NULL
},
25939 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25940 arm_parse_fpu
, NULL
},
25941 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25942 arm_parse_float_abi
, NULL
},
25944 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25945 arm_parse_eabi
, NULL
},
25947 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25948 arm_parse_it_mode
, NULL
},
25949 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25950 arm_ccs_mode
, NULL
},
25951 {NULL
, NULL
, 0, NULL
}
25955 md_parse_option (int c
, const char * arg
)
25957 struct arm_option_table
*opt
;
25958 const struct arm_legacy_option_table
*fopt
;
25959 struct arm_long_option_table
*lopt
;
25965 target_big_endian
= 1;
25971 target_big_endian
= 0;
25975 case OPTION_FIX_V4BX
:
25980 /* Listing option. Just ignore these, we don't support additional
25985 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25987 if (c
== opt
->option
[0]
25988 && ((arg
== NULL
&& opt
->option
[1] == 0)
25989 || streq (arg
, opt
->option
+ 1)))
25991 /* If the option is deprecated, tell the user. */
25992 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25993 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25994 arg
? arg
: "", _(opt
->deprecated
));
25996 if (opt
->var
!= NULL
)
25997 *opt
->var
= opt
->value
;
26003 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26005 if (c
== fopt
->option
[0]
26006 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26007 || streq (arg
, fopt
->option
+ 1)))
26009 /* If the option is deprecated, tell the user. */
26010 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26011 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26012 arg
? arg
: "", _(fopt
->deprecated
));
26014 if (fopt
->var
!= NULL
)
26015 *fopt
->var
= &fopt
->value
;
26021 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26023 /* These options are expected to have an argument. */
26024 if (c
== lopt
->option
[0]
26026 && strncmp (arg
, lopt
->option
+ 1,
26027 strlen (lopt
->option
+ 1)) == 0)
26029 /* If the option is deprecated, tell the user. */
26030 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26031 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26032 _(lopt
->deprecated
));
26034 /* Call the sup-option parser. */
26035 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26046 md_show_usage (FILE * fp
)
26048 struct arm_option_table
*opt
;
26049 struct arm_long_option_table
*lopt
;
26051 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26053 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26054 if (opt
->help
!= NULL
)
26055 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26057 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26058 if (lopt
->help
!= NULL
)
26059 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26063 -EB assemble code for a big-endian cpu\n"));
26068 -EL assemble code for a little-endian cpu\n"));
26072 --fix-v4bx Allow BX in ARMv4 code\n"));
26080 arm_feature_set flags
;
26081 } cpu_arch_ver_table
;
26083 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26084 must be sorted least features first but some reordering is needed, eg. for
26085 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26086 static const cpu_arch_ver_table cpu_arch_ver
[] =
26092 {4, ARM_ARCH_V5TE
},
26093 {5, ARM_ARCH_V5TEJ
},
26097 {11, ARM_ARCH_V6M
},
26098 {12, ARM_ARCH_V6SM
},
26099 {8, ARM_ARCH_V6T2
},
26100 {10, ARM_ARCH_V7VE
},
26101 {10, ARM_ARCH_V7R
},
26102 {10, ARM_ARCH_V7M
},
26103 {14, ARM_ARCH_V8A
},
26104 {16, ARM_ARCH_V8M_BASE
},
26105 {17, ARM_ARCH_V8M_MAIN
},
26109 /* Set an attribute if it has not already been set by the user. */
26111 aeabi_set_attribute_int (int tag
, int value
)
26114 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26115 || !attributes_set_explicitly
[tag
])
26116 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26120 aeabi_set_attribute_string (int tag
, const char *value
)
26123 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26124 || !attributes_set_explicitly
[tag
])
26125 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26128 /* Set the public EABI object attributes. */
26130 aeabi_set_public_attributes (void)
26135 int fp16_optional
= 0;
26136 arm_feature_set arm_arch
= ARM_ARCH_NONE
;
26137 arm_feature_set flags
;
26138 arm_feature_set tmp
;
26139 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26140 const cpu_arch_ver_table
*p
;
26142 /* Choose the architecture based on the capabilities of the requested cpu
26143 (if any) and/or the instructions actually used. */
26144 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26145 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26146 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26148 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26149 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26151 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26152 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26154 selected_cpu
= flags
;
26156 /* Allow the user to override the reported architecture. */
26159 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26160 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26163 /* We need to make sure that the attributes do not identify us as v6S-M
26164 when the only v6S-M feature in use is the Operating System Extensions. */
26165 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26166 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26167 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26171 for (p
= cpu_arch_ver
; p
->val
; p
++)
26173 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26176 arm_arch
= p
->flags
;
26177 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26181 /* The table lookup above finds the last architecture to contribute
26182 a new feature. Unfortunately, Tag13 is a subset of the union of
26183 v6T2 and v7-M, so it is never seen as contributing a new feature.
26184 We can not search for the last entry which is entirely used,
26185 because if no CPU is specified we build up only those flags
26186 actually used. Perhaps we should separate out the specified
26187 and implicit cases. Avoid taking this path for -march=all by
26188 checking for contradictory v7-A / v7-M features. */
26189 if (arch
== TAG_CPU_ARCH_V7
26190 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26191 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26192 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26194 arch
= TAG_CPU_ARCH_V7E_M
;
26195 arm_arch
= (arm_feature_set
) ARM_ARCH_V7EM
;
26198 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26199 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26201 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26202 arm_arch
= (arm_feature_set
) ARM_ARCH_V8M_MAIN
;
26205 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26206 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26207 ARMv8-M, -march=all must be detected as ARMv8-A. */
26208 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26209 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26211 arch
= TAG_CPU_ARCH_V8
;
26212 arm_arch
= (arm_feature_set
) ARM_ARCH_V8A
;
26215 /* Tag_CPU_name. */
26216 if (selected_cpu_name
[0])
26220 q
= selected_cpu_name
;
26221 if (strncmp (q
, "armv", 4) == 0)
26226 for (i
= 0; q
[i
]; i
++)
26227 q
[i
] = TOUPPER (q
[i
]);
26229 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26232 /* Tag_CPU_arch. */
26233 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26235 /* Tag_CPU_arch_profile. */
26236 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26237 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26238 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26239 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
)))
26241 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26243 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26248 if (profile
!= '\0')
26249 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26251 /* Tag_DSP_extension. */
26252 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_dsp
))
26254 arm_feature_set ext
;
26256 /* DSP instructions not in architecture. */
26257 ARM_CLEAR_FEATURE (ext
, flags
, arm_arch
);
26258 if (ARM_CPU_HAS_FEATURE (ext
, arm_ext_dsp
))
26259 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26262 /* Tag_ARM_ISA_use. */
26263 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26265 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26267 /* Tag_THUMB_ISA_use. */
26268 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26273 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26274 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26276 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26280 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26283 /* Tag_VFP_arch. */
26284 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26285 aeabi_set_attribute_int (Tag_VFP_arch
,
26286 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26288 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26289 aeabi_set_attribute_int (Tag_VFP_arch
,
26290 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26292 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26295 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26297 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26299 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26302 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26303 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26304 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26305 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26306 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26308 /* Tag_ABI_HardFP_use. */
26309 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26310 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26311 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26313 /* Tag_WMMX_arch. */
26314 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26315 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26316 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26317 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26319 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26320 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26321 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26322 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26323 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26324 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26326 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26328 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26332 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26337 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26338 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26339 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26343 We set Tag_DIV_use to two when integer divide instructions have been used
26344 in ARM state, or when Thumb integer divide instructions have been used,
26345 but we have no architecture profile set, nor have we any ARM instructions.
26347 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26348 by the base architecture.
26350 For new architectures we will have to check these tests. */
26351 gas_assert (arch
<= TAG_CPU_ARCH_V8
26352 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26353 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26354 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26355 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26356 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26357 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26358 || (profile
== '\0'
26359 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26360 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26361 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26363 /* Tag_MP_extension_use. */
26364 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26365 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26367 /* Tag Virtualization_use. */
26368 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26370 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26373 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26376 /* Add the default contents for the .ARM.attributes section. */
26380 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26383 aeabi_set_public_attributes ();
26385 #endif /* OBJ_ELF */
26388 /* Parse a .cpu directive. */
26391 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26393 const struct arm_cpu_option_table
*opt
;
26397 name
= input_line_pointer
;
26398 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26399 input_line_pointer
++;
26400 saved_char
= *input_line_pointer
;
26401 *input_line_pointer
= 0;
26403 /* Skip the first "all" entry. */
26404 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26405 if (streq (opt
->name
, name
))
26407 mcpu_cpu_opt
= &opt
->value
;
26408 selected_cpu
= opt
->value
;
26409 if (opt
->canonical_name
)
26410 strcpy (selected_cpu_name
, opt
->canonical_name
);
26414 for (i
= 0; opt
->name
[i
]; i
++)
26415 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26417 selected_cpu_name
[i
] = 0;
26419 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26420 *input_line_pointer
= saved_char
;
26421 demand_empty_rest_of_line ();
26424 as_bad (_("unknown cpu `%s'"), name
);
26425 *input_line_pointer
= saved_char
;
26426 ignore_rest_of_line ();
26430 /* Parse a .arch directive. */
26433 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26435 const struct arm_arch_option_table
*opt
;
26439 name
= input_line_pointer
;
26440 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26441 input_line_pointer
++;
26442 saved_char
= *input_line_pointer
;
26443 *input_line_pointer
= 0;
26445 /* Skip the first "all" entry. */
26446 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26447 if (streq (opt
->name
, name
))
26449 mcpu_cpu_opt
= &opt
->value
;
26450 selected_cpu
= opt
->value
;
26451 strcpy (selected_cpu_name
, opt
->name
);
26452 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26453 *input_line_pointer
= saved_char
;
26454 demand_empty_rest_of_line ();
26458 as_bad (_("unknown architecture `%s'\n"), name
);
26459 *input_line_pointer
= saved_char
;
26460 ignore_rest_of_line ();
26464 /* Parse a .object_arch directive. */
26467 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26469 const struct arm_arch_option_table
*opt
;
26473 name
= input_line_pointer
;
26474 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26475 input_line_pointer
++;
26476 saved_char
= *input_line_pointer
;
26477 *input_line_pointer
= 0;
26479 /* Skip the first "all" entry. */
26480 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26481 if (streq (opt
->name
, name
))
26483 object_arch
= &opt
->value
;
26484 *input_line_pointer
= saved_char
;
26485 demand_empty_rest_of_line ();
26489 as_bad (_("unknown architecture `%s'\n"), name
);
26490 *input_line_pointer
= saved_char
;
26491 ignore_rest_of_line ();
26494 /* Parse a .arch_extension directive. */
26497 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26499 const struct arm_option_extension_value_table
*opt
;
26500 const arm_feature_set arm_any
= ARM_ANY
;
26503 int adding_value
= 1;
26505 name
= input_line_pointer
;
26506 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26507 input_line_pointer
++;
26508 saved_char
= *input_line_pointer
;
26509 *input_line_pointer
= 0;
26511 if (strlen (name
) >= 2
26512 && strncmp (name
, "no", 2) == 0)
26518 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26519 if (streq (opt
->name
, name
))
26521 int i
, nb_allowed_archs
=
26522 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
26523 for (i
= 0; i
< nb_allowed_archs
; i
++)
26526 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26528 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
26532 if (i
== nb_allowed_archs
)
26534 as_bad (_("architectural extension `%s' is not allowed for the "
26535 "current base architecture"), name
);
26540 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26543 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26545 mcpu_cpu_opt
= &selected_cpu
;
26546 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26547 *input_line_pointer
= saved_char
;
26548 demand_empty_rest_of_line ();
26552 if (opt
->name
== NULL
)
26553 as_bad (_("unknown architecture extension `%s'\n"), name
);
26555 *input_line_pointer
= saved_char
;
26556 ignore_rest_of_line ();
26559 /* Parse a .fpu directive. */
26562 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26564 const struct arm_option_fpu_value_table
*opt
;
26568 name
= input_line_pointer
;
26569 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26570 input_line_pointer
++;
26571 saved_char
= *input_line_pointer
;
26572 *input_line_pointer
= 0;
26574 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26575 if (streq (opt
->name
, name
))
26577 mfpu_opt
= &opt
->value
;
26578 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26579 *input_line_pointer
= saved_char
;
26580 demand_empty_rest_of_line ();
26584 as_bad (_("unknown floating point format `%s'\n"), name
);
26585 *input_line_pointer
= saved_char
;
26586 ignore_rest_of_line ();
26589 /* Copy symbol information. */
26592 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26594 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26598 /* Given a symbolic attribute NAME, return the proper integer value.
26599 Returns -1 if the attribute is not known. */
26602 arm_convert_symbolic_attribute (const char *name
)
26604 static const struct
26609 attribute_table
[] =
26611 /* When you modify this table you should
26612 also modify the list in doc/c-arm.texi. */
26613 #define T(tag) {#tag, tag}
26614 T (Tag_CPU_raw_name
),
26617 T (Tag_CPU_arch_profile
),
26618 T (Tag_ARM_ISA_use
),
26619 T (Tag_THUMB_ISA_use
),
26623 T (Tag_Advanced_SIMD_arch
),
26624 T (Tag_PCS_config
),
26625 T (Tag_ABI_PCS_R9_use
),
26626 T (Tag_ABI_PCS_RW_data
),
26627 T (Tag_ABI_PCS_RO_data
),
26628 T (Tag_ABI_PCS_GOT_use
),
26629 T (Tag_ABI_PCS_wchar_t
),
26630 T (Tag_ABI_FP_rounding
),
26631 T (Tag_ABI_FP_denormal
),
26632 T (Tag_ABI_FP_exceptions
),
26633 T (Tag_ABI_FP_user_exceptions
),
26634 T (Tag_ABI_FP_number_model
),
26635 T (Tag_ABI_align_needed
),
26636 T (Tag_ABI_align8_needed
),
26637 T (Tag_ABI_align_preserved
),
26638 T (Tag_ABI_align8_preserved
),
26639 T (Tag_ABI_enum_size
),
26640 T (Tag_ABI_HardFP_use
),
26641 T (Tag_ABI_VFP_args
),
26642 T (Tag_ABI_WMMX_args
),
26643 T (Tag_ABI_optimization_goals
),
26644 T (Tag_ABI_FP_optimization_goals
),
26645 T (Tag_compatibility
),
26646 T (Tag_CPU_unaligned_access
),
26647 T (Tag_FP_HP_extension
),
26648 T (Tag_VFP_HP_extension
),
26649 T (Tag_ABI_FP_16bit_format
),
26650 T (Tag_MPextension_use
),
26652 T (Tag_nodefaults
),
26653 T (Tag_also_compatible_with
),
26654 T (Tag_conformance
),
26656 T (Tag_Virtualization_use
),
26657 T (Tag_DSP_extension
),
26658 /* We deliberately do not include Tag_MPextension_use_legacy. */
26666 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26667 if (streq (name
, attribute_table
[i
].name
))
26668 return attribute_table
[i
].tag
;
26674 /* Apply sym value for relocations only in the case that they are for
26675 local symbols in the same segment as the fixup and you have the
26676 respective architectural feature for blx and simple switches. */
26678 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26681 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26682 /* PR 17444: If the local symbol is in a different section then a reloc
26683 will always be generated for it, so applying the symbol value now
26684 will result in a double offset being stored in the relocation. */
26685 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26686 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26688 switch (fixP
->fx_r_type
)
26690 case BFD_RELOC_ARM_PCREL_BLX
:
26691 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26692 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26696 case BFD_RELOC_ARM_PCREL_CALL
:
26697 case BFD_RELOC_THUMB_PCREL_BLX
:
26698 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26709 #endif /* OBJ_ELF */