1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
204 static const arm_feature_set arm_arch_any
= ARM_ANY
;
205 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
206 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
207 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
209 static const arm_feature_set arm_cext_iwmmxt2
=
210 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
211 static const arm_feature_set arm_cext_iwmmxt
=
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
213 static const arm_feature_set arm_cext_xscale
=
214 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
215 static const arm_feature_set arm_cext_maverick
=
216 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
217 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
218 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v1xd
=
220 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
221 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
222 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
223 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
224 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
225 static const arm_feature_set fpu_vfp_ext_d32
=
226 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
227 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
228 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
229 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
230 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
231 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
232 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
234 static int mfloat_abi_opt
= -1;
235 /* Record user cpu selection for object attributes. */
236 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
237 /* Must be long enough to hold any of the names in arm_cpus. */
238 static char selected_cpu_name
[16];
241 static int meabi_flags
= EABI_DEFAULT
;
243 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
246 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
251 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
256 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
257 symbolS
* GOT_symbol
;
260 /* 0: assemble for ARM,
261 1: assemble for Thumb,
262 2: assemble for Thumb even though target CPU does not support thumb
264 static int thumb_mode
= 0;
265 /* A value distinct from the possible values for thumb_mode that we
266 can use to record whether thumb_mode has been copied into the
267 tc_frag_data field of a frag. */
268 #define MODE_RECORDED (1 << 4)
270 /* Specifies the intrinsic IT insn behavior mode. */
271 enum implicit_it_mode
273 IMPLICIT_IT_MODE_NEVER
= 0x00,
274 IMPLICIT_IT_MODE_ARM
= 0x01,
275 IMPLICIT_IT_MODE_THUMB
= 0x02,
276 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
278 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
280 /* If unified_syntax is true, we are processing the new unified
281 ARM/Thumb syntax. Important differences from the old ARM mode:
283 - Immediate operands do not require a # prefix.
284 - Conditional affixes always appear at the end of the
285 instruction. (For backward compatibility, those instructions
286 that formerly had them in the middle, continue to accept them
288 - The IT instruction may appear, and if it does is validated
289 against subsequent conditional affixes. It does not generate
292 Important differences from the old Thumb mode:
294 - Immediate operands do not require a # prefix.
295 - Most of the V6T2 instructions are only available in unified mode.
296 - The .N and .W suffixes are recognized and honored (it is an error
297 if they cannot be honored).
298 - All instructions set the flags if and only if they have an 's' affix.
299 - Conditional affixes may be used. They are validated against
300 preceding IT instructions. Unlike ARM mode, you cannot use a
301 conditional affix except in the scope of an IT instruction. */
303 static bfd_boolean unified_syntax
= FALSE
;
318 enum neon_el_type type
;
322 #define NEON_MAX_TYPE_ELS 4
326 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
330 enum it_instruction_type
335 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
336 if inside, should be the last one. */
337 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
338 i.e. BKPT and NOP. */
339 IT_INSN
/* The IT insn has been parsed. */
345 unsigned long instruction
;
349 /* "uncond_value" is set to the value in place of the conditional field in
350 unconditional versions of the instruction, or -1 if nothing is
353 struct neon_type vectype
;
354 /* This does not indicate an actual NEON instruction, only that
355 the mnemonic accepts neon-style type suffixes. */
357 /* Set to the opcode if the instruction needs relaxation.
358 Zero if the instruction is not relaxed. */
362 bfd_reloc_code_real_type type
;
367 enum it_instruction_type it_insn_type
;
373 struct neon_type_el vectype
;
374 unsigned present
: 1; /* Operand present. */
375 unsigned isreg
: 1; /* Operand was a register. */
376 unsigned immisreg
: 1; /* .imm field is a second register. */
377 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
378 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
379 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
380 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
381 instructions. This allows us to disambiguate ARM <-> vector insns. */
382 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
383 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
384 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
385 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
386 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
387 unsigned writeback
: 1; /* Operand has trailing ! */
388 unsigned preind
: 1; /* Preindexed address. */
389 unsigned postind
: 1; /* Postindexed address. */
390 unsigned negative
: 1; /* Index register was negated. */
391 unsigned shifted
: 1; /* Shift applied to operation. */
392 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
396 static struct arm_it inst
;
398 #define NUM_FLOAT_VALS 8
400 const char * fp_const
[] =
402 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
405 /* Number of littlenums required to hold an extended precision number. */
406 #define MAX_LITTLENUMS 6
408 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
418 #define CP_T_X 0x00008000
419 #define CP_T_Y 0x00400000
421 #define CONDS_BIT 0x00100000
422 #define LOAD_BIT 0x00100000
424 #define DOUBLE_LOAD_FLAG 0x00000001
428 const char * template_name
;
432 #define COND_ALWAYS 0xE
436 const char * template_name
;
440 struct asm_barrier_opt
442 const char * template_name
;
446 /* The bit that distinguishes CPSR and SPSR. */
447 #define SPSR_BIT (1 << 22)
449 /* The individual PSR flag bits. */
450 #define PSR_c (1 << 16)
451 #define PSR_x (1 << 17)
452 #define PSR_s (1 << 18)
453 #define PSR_f (1 << 19)
458 bfd_reloc_code_real_type reloc
;
463 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
464 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
469 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
472 /* Bits for DEFINED field in neon_typed_alias. */
473 #define NTA_HASTYPE 1
474 #define NTA_HASINDEX 2
476 struct neon_typed_alias
478 unsigned char defined
;
480 struct neon_type_el eltype
;
483 /* ARM register categories. This includes coprocessor numbers and various
484 architecture extensions' registers. */
510 /* Structure for a hash table entry for a register.
511 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
512 information which states whether a vector type or index is specified (for a
513 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
517 unsigned char number
;
519 unsigned char builtin
;
520 struct neon_typed_alias
* neon
;
523 /* Diagnostics used when we don't get a register of the expected type. */
524 const char * const reg_expected_msgs
[] =
526 N_("ARM register expected"),
527 N_("bad or missing co-processor number"),
528 N_("co-processor register expected"),
529 N_("FPA register expected"),
530 N_("VFP single precision register expected"),
531 N_("VFP/Neon double precision register expected"),
532 N_("Neon quad precision register expected"),
533 N_("VFP single or double precision register expected"),
534 N_("Neon double or quad precision register expected"),
535 N_("VFP single, double or Neon quad precision register expected"),
536 N_("VFP system register expected"),
537 N_("Maverick MVF register expected"),
538 N_("Maverick MVD register expected"),
539 N_("Maverick MVFX register expected"),
540 N_("Maverick MVDX register expected"),
541 N_("Maverick MVAX register expected"),
542 N_("Maverick DSPSC register expected"),
543 N_("iWMMXt data register expected"),
544 N_("iWMMXt control register expected"),
545 N_("iWMMXt scalar register expected"),
546 N_("XScale accumulator register expected"),
549 /* Some well known registers that we refer to directly elsewhere. */
554 /* ARM instructions take 4bytes in the object file, Thumb instructions
560 /* Basic string to match. */
561 const char * template_name
;
563 /* Parameters to instruction. */
564 unsigned int operands
[8];
566 /* Conditional tag - see opcode_lookup. */
567 unsigned int tag
: 4;
569 /* Basic instruction code. */
570 unsigned int avalue
: 28;
572 /* Thumb-format instruction code. */
575 /* Which architecture variant provides this instruction. */
576 const arm_feature_set
* avariant
;
577 const arm_feature_set
* tvariant
;
579 /* Function to call to encode instruction in ARM format. */
580 void (* aencode
) (void);
582 /* Function to call to encode instruction in Thumb format. */
583 void (* tencode
) (void);
586 /* Defines for various bits that we will want to toggle. */
587 #define INST_IMMEDIATE 0x02000000
588 #define OFFSET_REG 0x02000000
589 #define HWOFFSET_IMM 0x00400000
590 #define SHIFT_BY_REG 0x00000010
591 #define PRE_INDEX 0x01000000
592 #define INDEX_UP 0x00800000
593 #define WRITE_BACK 0x00200000
594 #define LDM_TYPE_2_OR_3 0x00400000
595 #define CPSI_MMOD 0x00020000
597 #define LITERAL_MASK 0xf000f000
598 #define OPCODE_MASK 0xfe1fffff
599 #define V4_STR_BIT 0x00000020
601 #define T2_SUBS_PC_LR 0xf3de8f00
603 #define DATA_OP_SHIFT 21
605 #define T2_OPCODE_MASK 0xfe1fffff
606 #define T2_DATA_OP_SHIFT 21
608 /* Codes to distinguish the arithmetic instructions. */
619 #define OPCODE_CMP 10
620 #define OPCODE_CMN 11
621 #define OPCODE_ORR 12
622 #define OPCODE_MOV 13
623 #define OPCODE_BIC 14
624 #define OPCODE_MVN 15
626 #define T2_OPCODE_AND 0
627 #define T2_OPCODE_BIC 1
628 #define T2_OPCODE_ORR 2
629 #define T2_OPCODE_ORN 3
630 #define T2_OPCODE_EOR 4
631 #define T2_OPCODE_ADD 8
632 #define T2_OPCODE_ADC 10
633 #define T2_OPCODE_SBC 11
634 #define T2_OPCODE_SUB 13
635 #define T2_OPCODE_RSB 14
637 #define T_OPCODE_MUL 0x4340
638 #define T_OPCODE_TST 0x4200
639 #define T_OPCODE_CMN 0x42c0
640 #define T_OPCODE_NEG 0x4240
641 #define T_OPCODE_MVN 0x43c0
643 #define T_OPCODE_ADD_R3 0x1800
644 #define T_OPCODE_SUB_R3 0x1a00
645 #define T_OPCODE_ADD_HI 0x4400
646 #define T_OPCODE_ADD_ST 0xb000
647 #define T_OPCODE_SUB_ST 0xb080
648 #define T_OPCODE_ADD_SP 0xa800
649 #define T_OPCODE_ADD_PC 0xa000
650 #define T_OPCODE_ADD_I8 0x3000
651 #define T_OPCODE_SUB_I8 0x3800
652 #define T_OPCODE_ADD_I3 0x1c00
653 #define T_OPCODE_SUB_I3 0x1e00
655 #define T_OPCODE_ASR_R 0x4100
656 #define T_OPCODE_LSL_R 0x4080
657 #define T_OPCODE_LSR_R 0x40c0
658 #define T_OPCODE_ROR_R 0x41c0
659 #define T_OPCODE_ASR_I 0x1000
660 #define T_OPCODE_LSL_I 0x0000
661 #define T_OPCODE_LSR_I 0x0800
663 #define T_OPCODE_MOV_I8 0x2000
664 #define T_OPCODE_CMP_I8 0x2800
665 #define T_OPCODE_CMP_LR 0x4280
666 #define T_OPCODE_MOV_HR 0x4600
667 #define T_OPCODE_CMP_HR 0x4500
669 #define T_OPCODE_LDR_PC 0x4800
670 #define T_OPCODE_LDR_SP 0x9800
671 #define T_OPCODE_STR_SP 0x9000
672 #define T_OPCODE_LDR_IW 0x6800
673 #define T_OPCODE_STR_IW 0x6000
674 #define T_OPCODE_LDR_IH 0x8800
675 #define T_OPCODE_STR_IH 0x8000
676 #define T_OPCODE_LDR_IB 0x7800
677 #define T_OPCODE_STR_IB 0x7000
678 #define T_OPCODE_LDR_RW 0x5800
679 #define T_OPCODE_STR_RW 0x5000
680 #define T_OPCODE_LDR_RH 0x5a00
681 #define T_OPCODE_STR_RH 0x5200
682 #define T_OPCODE_LDR_RB 0x5c00
683 #define T_OPCODE_STR_RB 0x5400
685 #define T_OPCODE_PUSH 0xb400
686 #define T_OPCODE_POP 0xbc00
688 #define T_OPCODE_BRANCH 0xe000
690 #define THUMB_SIZE 2 /* Size of thumb instruction. */
691 #define THUMB_PP_PC_LR 0x0100
692 #define THUMB_LOAD_BIT 0x0800
693 #define THUMB2_LOAD_BIT 0x00100000
695 #define BAD_ARGS _("bad arguments to instruction")
696 #define BAD_SP _("r13 not allowed here")
697 #define BAD_PC _("r15 not allowed here")
698 #define BAD_COND _("instruction cannot be conditional")
699 #define BAD_OVERLAP _("registers may not be the same")
700 #define BAD_HIREG _("lo register required")
701 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
702 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
703 #define BAD_BRANCH _("branch must be last instruction in IT block")
704 #define BAD_NOT_IT _("instruction not allowed in IT block")
705 #define BAD_FPU _("selected FPU does not support instruction")
706 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
707 #define BAD_IT_COND _("incorrect condition in IT block")
708 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
709 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
710 #define BAD_PC_ADDRESSING \
711 _("cannot use register index with PC-relative addressing")
712 #define BAD_PC_WRITEBACK \
713 _("cannot use writeback with PC-relative addressing")
715 static struct hash_control
* arm_ops_hsh
;
716 static struct hash_control
* arm_cond_hsh
;
717 static struct hash_control
* arm_shift_hsh
;
718 static struct hash_control
* arm_psr_hsh
;
719 static struct hash_control
* arm_v7m_psr_hsh
;
720 static struct hash_control
* arm_reg_hsh
;
721 static struct hash_control
* arm_reloc_hsh
;
722 static struct hash_control
* arm_barrier_opt_hsh
;
724 /* Stuff needed to resolve the label ambiguity
733 symbolS
* last_label_seen
;
734 static int label_is_thumb_function_name
= FALSE
;
736 /* Literal pool structure. Held on a per-section
737 and per-sub-section basis. */
739 #define MAX_LITERAL_POOL_SIZE 1024
740 typedef struct literal_pool
742 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
743 unsigned int next_free_entry
;
748 struct literal_pool
* next
;
751 /* Pointer to a linked list of literal pools. */
752 literal_pool
* list_of_pools
= NULL
;
755 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
757 static struct current_it now_it
;
761 now_it_compatible (int cond
)
763 return (cond
& ~1) == (now_it
.cc
& ~1);
767 conditional_insn (void)
769 return inst
.cond
!= COND_ALWAYS
;
772 static int in_it_block (void);
774 static int handle_it_state (void);
776 static void force_automatic_it_block_close (void);
778 static void it_fsm_post_encode (void);
780 #define set_it_insn_type(type) \
783 inst.it_insn_type = type; \
784 if (handle_it_state () == FAIL) \
789 #define set_it_insn_type_nonvoid(type, failret) \
792 inst.it_insn_type = type; \
793 if (handle_it_state () == FAIL) \
798 #define set_it_insn_type_last() \
801 if (inst.cond == COND_ALWAYS) \
802 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
804 set_it_insn_type (INSIDE_IT_LAST_INSN); \
810 /* This array holds the chars that always start a comment. If the
811 pre-processor is disabled, these aren't very useful. */
812 const char comment_chars
[] = "@";
814 /* This array holds the chars that only start a comment at the beginning of
815 a line. If the line seems to have the form '# 123 filename'
816 .line and .file directives will appear in the pre-processed output. */
817 /* Note that input_file.c hand checks for '#' at the beginning of the
818 first line of the input file. This is because the compiler outputs
819 #NO_APP at the beginning of its output. */
820 /* Also note that comments like this one will always work. */
821 const char line_comment_chars
[] = "#";
823 const char line_separator_chars
[] = ";";
825 /* Chars that can be used to separate mant
826 from exp in floating point numbers. */
827 const char EXP_CHARS
[] = "eE";
829 /* Chars that mean this number is a floating point constant. */
833 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
835 /* Prefix characters that indicate the start of an immediate
837 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
839 /* Separator character handling. */
841 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
844 skip_past_char (char ** str
, char c
)
855 #define skip_past_comma(str) skip_past_char (str, ',')
857 /* Arithmetic expressions (possibly involving symbols). */
859 /* Return TRUE if anything in the expression is a bignum. */
862 walk_no_bignums (symbolS
* sp
)
864 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
867 if (symbol_get_value_expression (sp
)->X_add_symbol
)
869 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
870 || (symbol_get_value_expression (sp
)->X_op_symbol
871 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
877 static int in_my_get_expression
= 0;
879 /* Third argument to my_get_expression. */
880 #define GE_NO_PREFIX 0
881 #define GE_IMM_PREFIX 1
882 #define GE_OPT_PREFIX 2
883 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
884 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
885 #define GE_OPT_PREFIX_BIG 3
888 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
893 /* In unified syntax, all prefixes are optional. */
895 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
900 case GE_NO_PREFIX
: break;
902 if (!is_immediate_prefix (**str
))
904 inst
.error
= _("immediate expression requires a # prefix");
910 case GE_OPT_PREFIX_BIG
:
911 if (is_immediate_prefix (**str
))
917 memset (ep
, 0, sizeof (expressionS
));
919 save_in
= input_line_pointer
;
920 input_line_pointer
= *str
;
921 in_my_get_expression
= 1;
922 seg
= expression (ep
);
923 in_my_get_expression
= 0;
925 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
927 /* We found a bad or missing expression in md_operand(). */
928 *str
= input_line_pointer
;
929 input_line_pointer
= save_in
;
930 if (inst
.error
== NULL
)
931 inst
.error
= (ep
->X_op
== O_absent
932 ? _("missing expression") :_("bad expression"));
937 if (seg
!= absolute_section
938 && seg
!= text_section
939 && seg
!= data_section
940 && seg
!= bss_section
941 && seg
!= undefined_section
)
943 inst
.error
= _("bad segment");
944 *str
= input_line_pointer
;
945 input_line_pointer
= save_in
;
952 /* Get rid of any bignums now, so that we don't generate an error for which
953 we can't establish a line number later on. Big numbers are never valid
954 in instructions, which is where this routine is always called. */
955 if (prefix_mode
!= GE_OPT_PREFIX_BIG
956 && (ep
->X_op
== O_big
958 && (walk_no_bignums (ep
->X_add_symbol
)
960 && walk_no_bignums (ep
->X_op_symbol
))))))
962 inst
.error
= _("invalid constant");
963 *str
= input_line_pointer
;
964 input_line_pointer
= save_in
;
968 *str
= input_line_pointer
;
969 input_line_pointer
= save_in
;
973 /* Turn a string in input_line_pointer into a floating point constant
974 of type TYPE, and store the appropriate bytes in *LITP. The number
975 of LITTLENUMS emitted is stored in *SIZEP. An error message is
976 returned, or NULL on OK.
978 Note that fp constants aren't represent in the normal way on the ARM.
979 In big endian mode, things are as expected. However, in little endian
980 mode fp constants are big-endian word-wise, and little-endian byte-wise
981 within the words. For example, (double) 1.1 in big endian mode is
982 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
983 the byte sequence 99 99 f1 3f 9a 99 99 99.
985 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
988 md_atof (int type
, char * litP
, int * sizeP
)
991 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1023 return _("Unrecognized or unsupported floating point constant");
1026 t
= atof_ieee (input_line_pointer
, type
, words
);
1028 input_line_pointer
= t
;
1029 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1031 if (target_big_endian
)
1033 for (i
= 0; i
< prec
; i
++)
1035 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1036 litP
+= sizeof (LITTLENUM_TYPE
);
1041 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1042 for (i
= prec
- 1; i
>= 0; i
--)
1044 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1045 litP
+= sizeof (LITTLENUM_TYPE
);
1048 /* For a 4 byte float the order of elements in `words' is 1 0.
1049 For an 8 byte float the order is 1 0 3 2. */
1050 for (i
= 0; i
< prec
; i
+= 2)
1052 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1053 sizeof (LITTLENUM_TYPE
));
1054 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1055 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1056 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1063 /* We handle all bad expressions here, so that we can report the faulty
1064 instruction in the error message. */
1066 md_operand (expressionS
* exp
)
1068 if (in_my_get_expression
)
1069 exp
->X_op
= O_illegal
;
1072 /* Immediate values. */
1074 /* Generic immediate-value read function for use in directives.
1075 Accepts anything that 'expression' can fold to a constant.
1076 *val receives the number. */
1079 immediate_for_directive (int *val
)
1082 exp
.X_op
= O_illegal
;
1084 if (is_immediate_prefix (*input_line_pointer
))
1086 input_line_pointer
++;
1090 if (exp
.X_op
!= O_constant
)
1092 as_bad (_("expected #constant"));
1093 ignore_rest_of_line ();
1096 *val
= exp
.X_add_number
;
1101 /* Register parsing. */
1103 /* Generic register parser. CCP points to what should be the
1104 beginning of a register name. If it is indeed a valid register
1105 name, advance CCP over it and return the reg_entry structure;
1106 otherwise return NULL. Does not issue diagnostics. */
1108 static struct reg_entry
*
1109 arm_reg_parse_multi (char **ccp
)
1113 struct reg_entry
*reg
;
1115 #ifdef REGISTER_PREFIX
1116 if (*start
!= REGISTER_PREFIX
)
1120 #ifdef OPTIONAL_REGISTER_PREFIX
1121 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1126 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1131 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1133 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1143 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1144 enum arm_reg_type type
)
1146 /* Alternative syntaxes are accepted for a few register classes. */
1153 /* Generic coprocessor register names are allowed for these. */
1154 if (reg
&& reg
->type
== REG_TYPE_CN
)
1159 /* For backward compatibility, a bare number is valid here. */
1161 unsigned long processor
= strtoul (start
, ccp
, 10);
1162 if (*ccp
!= start
&& processor
<= 15)
1166 case REG_TYPE_MMXWC
:
1167 /* WC includes WCG. ??? I'm not sure this is true for all
1168 instructions that take WC registers. */
1169 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1180 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1181 return value is the register number or FAIL. */
1184 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1187 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1190 /* Do not allow a scalar (reg+index) to parse as a register. */
1191 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1194 if (reg
&& reg
->type
== type
)
1197 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1204 /* Parse a Neon type specifier. *STR should point at the leading '.'
1205 character. Does no verification at this stage that the type fits the opcode
1212 Can all be legally parsed by this function.
1214 Fills in neon_type struct pointer with parsed information, and updates STR
1215 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1216 type, FAIL if not. */
1219 parse_neon_type (struct neon_type
*type
, char **str
)
1226 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1228 enum neon_el_type thistype
= NT_untyped
;
1229 unsigned thissize
= -1u;
1236 /* Just a size without an explicit type. */
1240 switch (TOLOWER (*ptr
))
1242 case 'i': thistype
= NT_integer
; break;
1243 case 'f': thistype
= NT_float
; break;
1244 case 'p': thistype
= NT_poly
; break;
1245 case 's': thistype
= NT_signed
; break;
1246 case 'u': thistype
= NT_unsigned
; break;
1248 thistype
= NT_float
;
1253 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1259 /* .f is an abbreviation for .f32. */
1260 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1265 thissize
= strtoul (ptr
, &ptr
, 10);
1267 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1270 as_bad (_("bad size %d in type specifier"), thissize
);
1278 type
->el
[type
->elems
].type
= thistype
;
1279 type
->el
[type
->elems
].size
= thissize
;
1284 /* Empty/missing type is not a successful parse. */
1285 if (type
->elems
== 0)
1293 /* Errors may be set multiple times during parsing or bit encoding
1294 (particularly in the Neon bits), but usually the earliest error which is set
1295 will be the most meaningful. Avoid overwriting it with later (cascading)
1296 errors by calling this function. */
1299 first_error (const char *err
)
1305 /* Parse a single type, e.g. ".s32", leading period included. */
1307 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1310 struct neon_type optype
;
1314 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1316 if (optype
.elems
== 1)
1317 *vectype
= optype
.el
[0];
1320 first_error (_("only one type should be specified for operand"));
1326 first_error (_("vector type expected"));
1338 /* Special meanings for indices (which have a range of 0-7), which will fit into
1341 #define NEON_ALL_LANES 15
1342 #define NEON_INTERLEAVE_LANES 14
1344 /* Parse either a register or a scalar, with an optional type. Return the
1345 register number, and optionally fill in the actual type of the register
1346 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1347 type/index information in *TYPEINFO. */
1350 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1351 enum arm_reg_type
*rtype
,
1352 struct neon_typed_alias
*typeinfo
)
1355 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1356 struct neon_typed_alias atype
;
1357 struct neon_type_el parsetype
;
1361 atype
.eltype
.type
= NT_invtype
;
1362 atype
.eltype
.size
= -1;
1364 /* Try alternate syntax for some types of register. Note these are mutually
1365 exclusive with the Neon syntax extensions. */
1368 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1376 /* Undo polymorphism when a set of register types may be accepted. */
1377 if ((type
== REG_TYPE_NDQ
1378 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1379 || (type
== REG_TYPE_VFSD
1380 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1381 || (type
== REG_TYPE_NSDQ
1382 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1383 || reg
->type
== REG_TYPE_NQ
))
1384 || (type
== REG_TYPE_MMXWC
1385 && (reg
->type
== REG_TYPE_MMXWCG
)))
1386 type
= (enum arm_reg_type
) reg
->type
;
1388 if (type
!= reg
->type
)
1394 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1396 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1398 first_error (_("can't redefine type for operand"));
1401 atype
.defined
|= NTA_HASTYPE
;
1402 atype
.eltype
= parsetype
;
1405 if (skip_past_char (&str
, '[') == SUCCESS
)
1407 if (type
!= REG_TYPE_VFD
)
1409 first_error (_("only D registers may be indexed"));
1413 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1415 first_error (_("can't change index for operand"));
1419 atype
.defined
|= NTA_HASINDEX
;
1421 if (skip_past_char (&str
, ']') == SUCCESS
)
1422 atype
.index
= NEON_ALL_LANES
;
1427 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1429 if (exp
.X_op
!= O_constant
)
1431 first_error (_("constant expression required"));
1435 if (skip_past_char (&str
, ']') == FAIL
)
1438 atype
.index
= exp
.X_add_number
;
1453 /* Like arm_reg_parse, but allow allow the following extra features:
1454 - If RTYPE is non-zero, return the (possibly restricted) type of the
1455 register (e.g. Neon double or quad reg when either has been requested).
1456 - If this is a Neon vector type with additional type information, fill
1457 in the struct pointed to by VECTYPE (if non-NULL).
1458 This function will fault on encountering a scalar. */
1461 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1462 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1464 struct neon_typed_alias atype
;
1466 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1471 /* Do not allow a scalar (reg+index) to parse as a register. */
1472 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1474 first_error (_("register operand expected, but got scalar"));
1479 *vectype
= atype
.eltype
;
1486 #define NEON_SCALAR_REG(X) ((X) >> 4)
1487 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1489 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1490 have enough information to be able to do a good job bounds-checking. So, we
1491 just do easy checks here, and do further checks later. */
1494 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1498 struct neon_typed_alias atype
;
1500 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1502 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1505 if (atype
.index
== NEON_ALL_LANES
)
1507 first_error (_("scalar must have an index"));
1510 else if (atype
.index
>= 64 / elsize
)
1512 first_error (_("scalar index out of range"));
1517 *type
= atype
.eltype
;
1521 return reg
* 16 + atype
.index
;
1524 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1527 parse_reg_list (char ** strp
)
1529 char * str
= * strp
;
1533 /* We come back here if we get ranges concatenated by '+' or '|'. */
1548 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1550 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1560 first_error (_("bad range in register list"));
1564 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1566 if (range
& (1 << i
))
1568 (_("Warning: duplicated register (r%d) in register list"),
1576 if (range
& (1 << reg
))
1577 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1579 else if (reg
<= cur_reg
)
1580 as_tsktsk (_("Warning: register range not in ascending order"));
1585 while (skip_past_comma (&str
) != FAIL
1586 || (in_range
= 1, *str
++ == '-'));
1591 first_error (_("missing `}'"));
1599 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1602 if (exp
.X_op
== O_constant
)
1604 if (exp
.X_add_number
1605 != (exp
.X_add_number
& 0x0000ffff))
1607 inst
.error
= _("invalid register mask");
1611 if ((range
& exp
.X_add_number
) != 0)
1613 int regno
= range
& exp
.X_add_number
;
1616 regno
= (1 << regno
) - 1;
1618 (_("Warning: duplicated register (r%d) in register list"),
1622 range
|= exp
.X_add_number
;
1626 if (inst
.reloc
.type
!= 0)
1628 inst
.error
= _("expression too complex");
1632 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1633 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1634 inst
.reloc
.pc_rel
= 0;
1638 if (*str
== '|' || *str
== '+')
1644 while (another_range
);
1650 /* Types of registers in a list. */
1659 /* Parse a VFP register list. If the string is invalid return FAIL.
1660 Otherwise return the number of registers, and set PBASE to the first
1661 register. Parses registers of type ETYPE.
1662 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1663 - Q registers can be used to specify pairs of D registers
1664 - { } can be omitted from around a singleton register list
1665 FIXME: This is not implemented, as it would require backtracking in
1668 This could be done (the meaning isn't really ambiguous), but doesn't
1669 fit in well with the current parsing framework.
1670 - 32 D registers may be used (also true for VFPv3).
1671 FIXME: Types are ignored in these register lists, which is probably a
1675 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1680 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1684 unsigned long mask
= 0;
1689 inst
.error
= _("expecting {");
1698 regtype
= REG_TYPE_VFS
;
1703 regtype
= REG_TYPE_VFD
;
1706 case REGLIST_NEON_D
:
1707 regtype
= REG_TYPE_NDQ
;
1711 if (etype
!= REGLIST_VFP_S
)
1713 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1714 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1718 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1721 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1728 base_reg
= max_regs
;
1732 int setmask
= 1, addregs
= 1;
1734 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1736 if (new_base
== FAIL
)
1738 first_error (_(reg_expected_msgs
[regtype
]));
1742 if (new_base
>= max_regs
)
1744 first_error (_("register out of range in list"));
1748 /* Note: a value of 2 * n is returned for the register Q<n>. */
1749 if (regtype
== REG_TYPE_NQ
)
1755 if (new_base
< base_reg
)
1756 base_reg
= new_base
;
1758 if (mask
& (setmask
<< new_base
))
1760 first_error (_("invalid register list"));
1764 if ((mask
>> new_base
) != 0 && ! warned
)
1766 as_tsktsk (_("register list not in ascending order"));
1770 mask
|= setmask
<< new_base
;
1773 if (*str
== '-') /* We have the start of a range expression */
1779 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1782 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1786 if (high_range
>= max_regs
)
1788 first_error (_("register out of range in list"));
1792 if (regtype
== REG_TYPE_NQ
)
1793 high_range
= high_range
+ 1;
1795 if (high_range
<= new_base
)
1797 inst
.error
= _("register range not in ascending order");
1801 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1803 if (mask
& (setmask
<< new_base
))
1805 inst
.error
= _("invalid register list");
1809 mask
|= setmask
<< new_base
;
1814 while (skip_past_comma (&str
) != FAIL
);
1818 /* Sanity check -- should have raised a parse error above. */
1819 if (count
== 0 || count
> max_regs
)
1824 /* Final test -- the registers must be consecutive. */
1826 for (i
= 0; i
< count
; i
++)
1828 if ((mask
& (1u << i
)) == 0)
1830 inst
.error
= _("non-contiguous register range");
1840 /* True if two alias types are the same. */
1843 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1851 if (a
->defined
!= b
->defined
)
1854 if ((a
->defined
& NTA_HASTYPE
) != 0
1855 && (a
->eltype
.type
!= b
->eltype
.type
1856 || a
->eltype
.size
!= b
->eltype
.size
))
1859 if ((a
->defined
& NTA_HASINDEX
) != 0
1860 && (a
->index
!= b
->index
))
1866 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1867 The base register is put in *PBASE.
1868 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1870 The register stride (minus one) is put in bit 4 of the return value.
1871 Bits [6:5] encode the list length (minus one).
1872 The type of the list elements is put in *ELTYPE, if non-NULL. */
1874 #define NEON_LANE(X) ((X) & 0xf)
1875 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1876 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1879 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1880 struct neon_type_el
*eltype
)
1887 int leading_brace
= 0;
1888 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1889 const char *const incr_error
= _("register stride must be 1 or 2");
1890 const char *const type_error
= _("mismatched element/structure types in list");
1891 struct neon_typed_alias firsttype
;
1893 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1898 struct neon_typed_alias atype
;
1899 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1903 first_error (_(reg_expected_msgs
[rtype
]));
1910 if (rtype
== REG_TYPE_NQ
)
1916 else if (reg_incr
== -1)
1918 reg_incr
= getreg
- base_reg
;
1919 if (reg_incr
< 1 || reg_incr
> 2)
1921 first_error (_(incr_error
));
1925 else if (getreg
!= base_reg
+ reg_incr
* count
)
1927 first_error (_(incr_error
));
1931 if (! neon_alias_types_same (&atype
, &firsttype
))
1933 first_error (_(type_error
));
1937 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1941 struct neon_typed_alias htype
;
1942 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1944 lane
= NEON_INTERLEAVE_LANES
;
1945 else if (lane
!= NEON_INTERLEAVE_LANES
)
1947 first_error (_(type_error
));
1952 else if (reg_incr
!= 1)
1954 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1958 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1961 first_error (_(reg_expected_msgs
[rtype
]));
1964 if (! neon_alias_types_same (&htype
, &firsttype
))
1966 first_error (_(type_error
));
1969 count
+= hireg
+ dregs
- getreg
;
1973 /* If we're using Q registers, we can't use [] or [n] syntax. */
1974 if (rtype
== REG_TYPE_NQ
)
1980 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1984 else if (lane
!= atype
.index
)
1986 first_error (_(type_error
));
1990 else if (lane
== -1)
1991 lane
= NEON_INTERLEAVE_LANES
;
1992 else if (lane
!= NEON_INTERLEAVE_LANES
)
1994 first_error (_(type_error
));
1999 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2001 /* No lane set by [x]. We must be interleaving structures. */
2003 lane
= NEON_INTERLEAVE_LANES
;
2006 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2007 || (count
> 1 && reg_incr
== -1))
2009 first_error (_("error parsing element/structure list"));
2013 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2015 first_error (_("expected }"));
2023 *eltype
= firsttype
.eltype
;
2028 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2031 /* Parse an explicit relocation suffix on an expression. This is
2032 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2033 arm_reloc_hsh contains no entries, so this function can only
2034 succeed if there is no () after the word. Returns -1 on error,
2035 BFD_RELOC_UNUSED if there wasn't any suffix. */
2037 parse_reloc (char **str
)
2039 struct reloc_entry
*r
;
2043 return BFD_RELOC_UNUSED
;
2048 while (*q
&& *q
!= ')' && *q
!= ',')
2053 if ((r
= (struct reloc_entry
*)
2054 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2061 /* Directives: register aliases. */
2063 static struct reg_entry
*
2064 insert_reg_alias (char *str
, int number
, int type
)
2066 struct reg_entry
*new_reg
;
2069 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2071 if (new_reg
->builtin
)
2072 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2074 /* Only warn about a redefinition if it's not defined as the
2076 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2077 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2082 name
= xstrdup (str
);
2083 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2085 new_reg
->name
= name
;
2086 new_reg
->number
= number
;
2087 new_reg
->type
= type
;
2088 new_reg
->builtin
= FALSE
;
2089 new_reg
->neon
= NULL
;
2091 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2098 insert_neon_reg_alias (char *str
, int number
, int type
,
2099 struct neon_typed_alias
*atype
)
2101 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2105 first_error (_("attempt to redefine typed alias"));
2111 reg
->neon
= (struct neon_typed_alias
*)
2112 xmalloc (sizeof (struct neon_typed_alias
));
2113 *reg
->neon
= *atype
;
2117 /* Look for the .req directive. This is of the form:
2119 new_register_name .req existing_register_name
2121 If we find one, or if it looks sufficiently like one that we want to
2122 handle any error here, return TRUE. Otherwise return FALSE. */
2125 create_register_alias (char * newname
, char *p
)
2127 struct reg_entry
*old
;
2128 char *oldname
, *nbuf
;
2131 /* The input scrubber ensures that whitespace after the mnemonic is
2132 collapsed to single spaces. */
2134 if (strncmp (oldname
, " .req ", 6) != 0)
2138 if (*oldname
== '\0')
2141 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2144 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2148 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2149 the desired alias name, and p points to its end. If not, then
2150 the desired alias name is in the global original_case_string. */
2151 #ifdef TC_CASE_SENSITIVE
2154 newname
= original_case_string
;
2155 nlen
= strlen (newname
);
2158 nbuf
= (char *) alloca (nlen
+ 1);
2159 memcpy (nbuf
, newname
, nlen
);
2162 /* Create aliases under the new name as stated; an all-lowercase
2163 version of the new name; and an all-uppercase version of the new
2165 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2167 for (p
= nbuf
; *p
; p
++)
2170 if (strncmp (nbuf
, newname
, nlen
))
2172 /* If this attempt to create an additional alias fails, do not bother
2173 trying to create the all-lower case alias. We will fail and issue
2174 a second, duplicate error message. This situation arises when the
2175 programmer does something like:
2178 The second .req creates the "Foo" alias but then fails to create
2179 the artificial FOO alias because it has already been created by the
2181 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2185 for (p
= nbuf
; *p
; p
++)
2188 if (strncmp (nbuf
, newname
, nlen
))
2189 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2195 /* Create a Neon typed/indexed register alias using directives, e.g.:
2200 These typed registers can be used instead of the types specified after the
2201 Neon mnemonic, so long as all operands given have types. Types can also be
2202 specified directly, e.g.:
2203 vadd d0.s32, d1.s32, d2.s32 */
2206 create_neon_reg_alias (char *newname
, char *p
)
2208 enum arm_reg_type basetype
;
2209 struct reg_entry
*basereg
;
2210 struct reg_entry mybasereg
;
2211 struct neon_type ntype
;
2212 struct neon_typed_alias typeinfo
;
2213 char *namebuf
, *nameend
;
2216 typeinfo
.defined
= 0;
2217 typeinfo
.eltype
.type
= NT_invtype
;
2218 typeinfo
.eltype
.size
= -1;
2219 typeinfo
.index
= -1;
2223 if (strncmp (p
, " .dn ", 5) == 0)
2224 basetype
= REG_TYPE_VFD
;
2225 else if (strncmp (p
, " .qn ", 5) == 0)
2226 basetype
= REG_TYPE_NQ
;
2235 basereg
= arm_reg_parse_multi (&p
);
2237 if (basereg
&& basereg
->type
!= basetype
)
2239 as_bad (_("bad type for register"));
2243 if (basereg
== NULL
)
2246 /* Try parsing as an integer. */
2247 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2248 if (exp
.X_op
!= O_constant
)
2250 as_bad (_("expression must be constant"));
2253 basereg
= &mybasereg
;
2254 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2260 typeinfo
= *basereg
->neon
;
2262 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2264 /* We got a type. */
2265 if (typeinfo
.defined
& NTA_HASTYPE
)
2267 as_bad (_("can't redefine the type of a register alias"));
2271 typeinfo
.defined
|= NTA_HASTYPE
;
2272 if (ntype
.elems
!= 1)
2274 as_bad (_("you must specify a single type only"));
2277 typeinfo
.eltype
= ntype
.el
[0];
2280 if (skip_past_char (&p
, '[') == SUCCESS
)
2283 /* We got a scalar index. */
2285 if (typeinfo
.defined
& NTA_HASINDEX
)
2287 as_bad (_("can't redefine the index of a scalar alias"));
2291 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2293 if (exp
.X_op
!= O_constant
)
2295 as_bad (_("scalar index must be constant"));
2299 typeinfo
.defined
|= NTA_HASINDEX
;
2300 typeinfo
.index
= exp
.X_add_number
;
2302 if (skip_past_char (&p
, ']') == FAIL
)
2304 as_bad (_("expecting ]"));
2309 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2310 the desired alias name, and p points to its end. If not, then
2311 the desired alias name is in the global original_case_string. */
2312 #ifdef TC_CASE_SENSITIVE
2313 namelen
= nameend
- newname
;
2315 newname
= original_case_string
;
2316 namelen
= strlen (newname
);
2319 namebuf
= (char *) alloca (namelen
+ 1);
2320 strncpy (namebuf
, newname
, namelen
);
2321 namebuf
[namelen
] = '\0';
2323 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2324 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2326 /* Insert name in all uppercase. */
2327 for (p
= namebuf
; *p
; p
++)
2330 if (strncmp (namebuf
, newname
, namelen
))
2331 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2332 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2334 /* Insert name in all lowercase. */
2335 for (p
= namebuf
; *p
; p
++)
2338 if (strncmp (namebuf
, newname
, namelen
))
2339 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2340 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2345 /* Should never be called, as .req goes between the alias and the
2346 register name, not at the beginning of the line. */
2349 s_req (int a ATTRIBUTE_UNUSED
)
2351 as_bad (_("invalid syntax for .req directive"));
2355 s_dn (int a ATTRIBUTE_UNUSED
)
2357 as_bad (_("invalid syntax for .dn directive"));
2361 s_qn (int a ATTRIBUTE_UNUSED
)
2363 as_bad (_("invalid syntax for .qn directive"));
2366 /* The .unreq directive deletes an alias which was previously defined
2367 by .req. For example:
2373 s_unreq (int a ATTRIBUTE_UNUSED
)
2378 name
= input_line_pointer
;
2380 while (*input_line_pointer
!= 0
2381 && *input_line_pointer
!= ' '
2382 && *input_line_pointer
!= '\n')
2383 ++input_line_pointer
;
2385 saved_char
= *input_line_pointer
;
2386 *input_line_pointer
= 0;
2389 as_bad (_("invalid syntax for .unreq directive"));
2392 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2396 as_bad (_("unknown register alias '%s'"), name
);
2397 else if (reg
->builtin
)
2398 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2405 hash_delete (arm_reg_hsh
, name
, FALSE
);
2406 free ((char *) reg
->name
);
2411 /* Also locate the all upper case and all lower case versions.
2412 Do not complain if we cannot find one or the other as it
2413 was probably deleted above. */
2415 nbuf
= strdup (name
);
2416 for (p
= nbuf
; *p
; p
++)
2418 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2421 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2422 free ((char *) reg
->name
);
2428 for (p
= nbuf
; *p
; p
++)
2430 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2433 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2434 free ((char *) reg
->name
);
2444 *input_line_pointer
= saved_char
;
2445 demand_empty_rest_of_line ();
2448 /* Directives: Instruction set selection. */
2451 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2452 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2453 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2454 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2456 /* Create a new mapping symbol for the transition to STATE. */
2459 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2462 const char * symname
;
2469 type
= BSF_NO_FLAGS
;
2473 type
= BSF_NO_FLAGS
;
2477 type
= BSF_NO_FLAGS
;
2483 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2484 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2489 THUMB_SET_FUNC (symbolP
, 0);
2490 ARM_SET_THUMB (symbolP
, 0);
2491 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2495 THUMB_SET_FUNC (symbolP
, 1);
2496 ARM_SET_THUMB (symbolP
, 1);
2497 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2505 /* Save the mapping symbols for future reference. Also check that
2506 we do not place two mapping symbols at the same offset within a
2507 frag. We'll handle overlap between frags in
2508 check_mapping_symbols.
2510 If .fill or other data filling directive generates zero sized data,
2511 the mapping symbol for the following code will have the same value
2512 as the one generated for the data filling directive. In this case,
2513 we replace the old symbol with the new one at the same address. */
2516 if (frag
->tc_frag_data
.first_map
!= NULL
)
2518 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2519 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2521 frag
->tc_frag_data
.first_map
= symbolP
;
2523 if (frag
->tc_frag_data
.last_map
!= NULL
)
2525 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2526 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2527 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2529 frag
->tc_frag_data
.last_map
= symbolP
;
2532 /* We must sometimes convert a region marked as code to data during
2533 code alignment, if an odd number of bytes have to be padded. The
2534 code mapping symbol is pushed to an aligned address. */
2537 insert_data_mapping_symbol (enum mstate state
,
2538 valueT value
, fragS
*frag
, offsetT bytes
)
2540 /* If there was already a mapping symbol, remove it. */
2541 if (frag
->tc_frag_data
.last_map
!= NULL
2542 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2544 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2548 know (frag
->tc_frag_data
.first_map
== symp
);
2549 frag
->tc_frag_data
.first_map
= NULL
;
2551 frag
->tc_frag_data
.last_map
= NULL
;
2552 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2555 make_mapping_symbol (MAP_DATA
, value
, frag
);
2556 make_mapping_symbol (state
, value
+ bytes
, frag
);
2559 static void mapping_state_2 (enum mstate state
, int max_chars
);
2561 /* Set the mapping state to STATE. Only call this when about to
2562 emit some STATE bytes to the file. */
2565 mapping_state (enum mstate state
)
2567 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2569 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2571 if (mapstate
== state
)
2572 /* The mapping symbol has already been emitted.
2573 There is nothing else to do. */
2575 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2576 /* This case will be evaluated later in the next else. */
2578 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2579 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2581 /* Only add the symbol if the offset is > 0:
2582 if we're at the first frag, check it's size > 0;
2583 if we're not at the first frag, then for sure
2584 the offset is > 0. */
2585 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2586 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2589 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2592 mapping_state_2 (state
, 0);
2596 /* Same as mapping_state, but MAX_CHARS bytes have already been
2597 allocated. Put the mapping symbol that far back. */
2600 mapping_state_2 (enum mstate state
, int max_chars
)
2602 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2604 if (!SEG_NORMAL (now_seg
))
2607 if (mapstate
== state
)
2608 /* The mapping symbol has already been emitted.
2609 There is nothing else to do. */
2612 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2613 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2616 #define mapping_state(x) ((void)0)
2617 #define mapping_state_2(x, y) ((void)0)
2620 /* Find the real, Thumb encoded start of a Thumb function. */
2624 find_real_start (symbolS
* symbolP
)
2627 const char * name
= S_GET_NAME (symbolP
);
2628 symbolS
* new_target
;
2630 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2631 #define STUB_NAME ".real_start_of"
2636 /* The compiler may generate BL instructions to local labels because
2637 it needs to perform a branch to a far away location. These labels
2638 do not have a corresponding ".real_start_of" label. We check
2639 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2640 the ".real_start_of" convention for nonlocal branches. */
2641 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2644 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2645 new_target
= symbol_find (real_start
);
2647 if (new_target
== NULL
)
2649 as_warn (_("Failed to find real start of function: %s\n"), name
);
2650 new_target
= symbolP
;
2658 opcode_select (int width
)
2665 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2666 as_bad (_("selected processor does not support THUMB opcodes"));
2669 /* No need to force the alignment, since we will have been
2670 coming from ARM mode, which is word-aligned. */
2671 record_alignment (now_seg
, 1);
2678 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2679 as_bad (_("selected processor does not support ARM opcodes"));
2684 frag_align (2, 0, 0);
2686 record_alignment (now_seg
, 1);
2691 as_bad (_("invalid instruction size selected (%d)"), width
);
2696 s_arm (int ignore ATTRIBUTE_UNUSED
)
2699 demand_empty_rest_of_line ();
2703 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2706 demand_empty_rest_of_line ();
2710 s_code (int unused ATTRIBUTE_UNUSED
)
2714 temp
= get_absolute_expression ();
2719 opcode_select (temp
);
2723 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2728 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2730 /* If we are not already in thumb mode go into it, EVEN if
2731 the target processor does not support thumb instructions.
2732 This is used by gcc/config/arm/lib1funcs.asm for example
2733 to compile interworking support functions even if the
2734 target processor should not support interworking. */
2738 record_alignment (now_seg
, 1);
2741 demand_empty_rest_of_line ();
2745 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2749 /* The following label is the name/address of the start of a Thumb function.
2750 We need to know this for the interworking support. */
2751 label_is_thumb_function_name
= TRUE
;
2754 /* Perform a .set directive, but also mark the alias as
2755 being a thumb function. */
2758 s_thumb_set (int equiv
)
2760 /* XXX the following is a duplicate of the code for s_set() in read.c
2761 We cannot just call that code as we need to get at the symbol that
2768 /* Especial apologies for the random logic:
2769 This just grew, and could be parsed much more simply!
2771 name
= input_line_pointer
;
2772 delim
= get_symbol_end ();
2773 end_name
= input_line_pointer
;
2776 if (*input_line_pointer
!= ',')
2779 as_bad (_("expected comma after name \"%s\""), name
);
2781 ignore_rest_of_line ();
2785 input_line_pointer
++;
2788 if (name
[0] == '.' && name
[1] == '\0')
2790 /* XXX - this should not happen to .thumb_set. */
2794 if ((symbolP
= symbol_find (name
)) == NULL
2795 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2798 /* When doing symbol listings, play games with dummy fragments living
2799 outside the normal fragment chain to record the file and line info
2801 if (listing
& LISTING_SYMBOLS
)
2803 extern struct list_info_struct
* listing_tail
;
2804 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2806 memset (dummy_frag
, 0, sizeof (fragS
));
2807 dummy_frag
->fr_type
= rs_fill
;
2808 dummy_frag
->line
= listing_tail
;
2809 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2810 dummy_frag
->fr_symbol
= symbolP
;
2814 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2817 /* "set" symbols are local unless otherwise specified. */
2818 SF_SET_LOCAL (symbolP
);
2819 #endif /* OBJ_COFF */
2820 } /* Make a new symbol. */
2822 symbol_table_insert (symbolP
);
2827 && S_IS_DEFINED (symbolP
)
2828 && S_GET_SEGMENT (symbolP
) != reg_section
)
2829 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2831 pseudo_set (symbolP
);
2833 demand_empty_rest_of_line ();
2835 /* XXX Now we come to the Thumb specific bit of code. */
2837 THUMB_SET_FUNC (symbolP
, 1);
2838 ARM_SET_THUMB (symbolP
, 1);
2839 #if defined OBJ_ELF || defined OBJ_COFF
2840 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2844 /* Directives: Mode selection. */
2846 /* .syntax [unified|divided] - choose the new unified syntax
2847 (same for Arm and Thumb encoding, modulo slight differences in what
2848 can be represented) or the old divergent syntax for each mode. */
2850 s_syntax (int unused ATTRIBUTE_UNUSED
)
2854 name
= input_line_pointer
;
2855 delim
= get_symbol_end ();
2857 if (!strcasecmp (name
, "unified"))
2858 unified_syntax
= TRUE
;
2859 else if (!strcasecmp (name
, "divided"))
2860 unified_syntax
= FALSE
;
2863 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2866 *input_line_pointer
= delim
;
2867 demand_empty_rest_of_line ();
2870 /* Directives: sectioning and alignment. */
2872 /* Same as s_align_ptwo but align 0 => align 2. */
2875 s_align (int unused ATTRIBUTE_UNUSED
)
2880 long max_alignment
= 15;
2882 temp
= get_absolute_expression ();
2883 if (temp
> max_alignment
)
2884 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2887 as_bad (_("alignment negative. 0 assumed."));
2891 if (*input_line_pointer
== ',')
2893 input_line_pointer
++;
2894 temp_fill
= get_absolute_expression ();
2906 /* Only make a frag if we HAVE to. */
2907 if (temp
&& !need_pass_2
)
2909 if (!fill_p
&& subseg_text_p (now_seg
))
2910 frag_align_code (temp
, 0);
2912 frag_align (temp
, (int) temp_fill
, 0);
2914 demand_empty_rest_of_line ();
2916 record_alignment (now_seg
, temp
);
2920 s_bss (int ignore ATTRIBUTE_UNUSED
)
2922 /* We don't support putting frags in the BSS segment, we fake it by
2923 marking in_bss, then looking at s_skip for clues. */
2924 subseg_set (bss_section
, 0);
2925 demand_empty_rest_of_line ();
2927 #ifdef md_elf_section_change_hook
2928 md_elf_section_change_hook ();
2933 s_even (int ignore ATTRIBUTE_UNUSED
)
2935 /* Never make frag if expect extra pass. */
2937 frag_align (1, 0, 0);
2939 record_alignment (now_seg
, 1);
2941 demand_empty_rest_of_line ();
2944 /* Directives: Literal pools. */
2946 static literal_pool
*
2947 find_literal_pool (void)
2949 literal_pool
* pool
;
2951 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2953 if (pool
->section
== now_seg
2954 && pool
->sub_section
== now_subseg
)
2961 static literal_pool
*
2962 find_or_make_literal_pool (void)
2964 /* Next literal pool ID number. */
2965 static unsigned int latest_pool_num
= 1;
2966 literal_pool
* pool
;
2968 pool
= find_literal_pool ();
2972 /* Create a new pool. */
2973 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2977 pool
->next_free_entry
= 0;
2978 pool
->section
= now_seg
;
2979 pool
->sub_section
= now_subseg
;
2980 pool
->next
= list_of_pools
;
2981 pool
->symbol
= NULL
;
2983 /* Add it to the list. */
2984 list_of_pools
= pool
;
2987 /* New pools, and emptied pools, will have a NULL symbol. */
2988 if (pool
->symbol
== NULL
)
2990 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2991 (valueT
) 0, &zero_address_frag
);
2992 pool
->id
= latest_pool_num
++;
2999 /* Add the literal in the global 'inst'
3000 structure to the relevant literal pool. */
3003 add_to_lit_pool (void)
3005 literal_pool
* pool
;
3008 pool
= find_or_make_literal_pool ();
3010 /* Check if this literal value is already in the pool. */
3011 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3013 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3014 && (inst
.reloc
.exp
.X_op
== O_constant
)
3015 && (pool
->literals
[entry
].X_add_number
3016 == inst
.reloc
.exp
.X_add_number
)
3017 && (pool
->literals
[entry
].X_unsigned
3018 == inst
.reloc
.exp
.X_unsigned
))
3021 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3022 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3023 && (pool
->literals
[entry
].X_add_number
3024 == inst
.reloc
.exp
.X_add_number
)
3025 && (pool
->literals
[entry
].X_add_symbol
3026 == inst
.reloc
.exp
.X_add_symbol
)
3027 && (pool
->literals
[entry
].X_op_symbol
3028 == inst
.reloc
.exp
.X_op_symbol
))
3032 /* Do we need to create a new entry? */
3033 if (entry
== pool
->next_free_entry
)
3035 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3037 inst
.error
= _("literal pool overflow");
3041 pool
->literals
[entry
] = inst
.reloc
.exp
;
3042 pool
->next_free_entry
+= 1;
3045 inst
.reloc
.exp
.X_op
= O_symbol
;
3046 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3047 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3052 /* Can't use symbol_new here, so have to create a symbol and then at
3053 a later date assign it a value. Thats what these functions do. */
3056 symbol_locate (symbolS
* symbolP
,
3057 const char * name
, /* It is copied, the caller can modify. */
3058 segT segment
, /* Segment identifier (SEG_<something>). */
3059 valueT valu
, /* Symbol value. */
3060 fragS
* frag
) /* Associated fragment. */
3062 unsigned int name_length
;
3063 char * preserved_copy_of_name
;
3065 name_length
= strlen (name
) + 1; /* +1 for \0. */
3066 obstack_grow (¬es
, name
, name_length
);
3067 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3069 #ifdef tc_canonicalize_symbol_name
3070 preserved_copy_of_name
=
3071 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3074 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3076 S_SET_SEGMENT (symbolP
, segment
);
3077 S_SET_VALUE (symbolP
, valu
);
3078 symbol_clear_list_pointers (symbolP
);
3080 symbol_set_frag (symbolP
, frag
);
3082 /* Link to end of symbol chain. */
3084 extern int symbol_table_frozen
;
3086 if (symbol_table_frozen
)
3090 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3092 obj_symbol_new_hook (symbolP
);
3094 #ifdef tc_symbol_new_hook
3095 tc_symbol_new_hook (symbolP
);
3099 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3100 #endif /* DEBUG_SYMS */
3105 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3108 literal_pool
* pool
;
3111 pool
= find_literal_pool ();
3113 || pool
->symbol
== NULL
3114 || pool
->next_free_entry
== 0)
3117 mapping_state (MAP_DATA
);
3119 /* Align pool as you have word accesses.
3120 Only make a frag if we have to. */
3122 frag_align (2, 0, 0);
3124 record_alignment (now_seg
, 2);
3126 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3128 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3129 (valueT
) frag_now_fix (), frag_now
);
3130 symbol_table_insert (pool
->symbol
);
3132 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3134 #if defined OBJ_COFF || defined OBJ_ELF
3135 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3138 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3139 /* First output the expression in the instruction to the pool. */
3140 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3142 /* Mark the pool as empty. */
3143 pool
->next_free_entry
= 0;
3144 pool
->symbol
= NULL
;
3148 /* Forward declarations for functions below, in the MD interface
3150 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3151 static valueT
create_unwind_entry (int);
3152 static void start_unwind_section (const segT
, int);
3153 static void add_unwind_opcode (valueT
, int);
3154 static void flush_pending_unwind (void);
3156 /* Directives: Data. */
3159 s_arm_elf_cons (int nbytes
)
3163 #ifdef md_flush_pending_output
3164 md_flush_pending_output ();
3167 if (is_it_end_of_statement ())
3169 demand_empty_rest_of_line ();
3173 #ifdef md_cons_align
3174 md_cons_align (nbytes
);
3177 mapping_state (MAP_DATA
);
3181 char *base
= input_line_pointer
;
3185 if (exp
.X_op
!= O_symbol
)
3186 emit_expr (&exp
, (unsigned int) nbytes
);
3189 char *before_reloc
= input_line_pointer
;
3190 reloc
= parse_reloc (&input_line_pointer
);
3193 as_bad (_("unrecognized relocation suffix"));
3194 ignore_rest_of_line ();
3197 else if (reloc
== BFD_RELOC_UNUSED
)
3198 emit_expr (&exp
, (unsigned int) nbytes
);
3201 reloc_howto_type
*howto
= (reloc_howto_type
*)
3202 bfd_reloc_type_lookup (stdoutput
,
3203 (bfd_reloc_code_real_type
) reloc
);
3204 int size
= bfd_get_reloc_size (howto
);
3206 if (reloc
== BFD_RELOC_ARM_PLT32
)
3208 as_bad (_("(plt) is only valid on branch targets"));
3209 reloc
= BFD_RELOC_UNUSED
;
3214 as_bad (_("%s relocations do not fit in %d bytes"),
3215 howto
->name
, nbytes
);
3218 /* We've parsed an expression stopping at O_symbol.
3219 But there may be more expression left now that we
3220 have parsed the relocation marker. Parse it again.
3221 XXX Surely there is a cleaner way to do this. */
3222 char *p
= input_line_pointer
;
3224 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3225 memcpy (save_buf
, base
, input_line_pointer
- base
);
3226 memmove (base
+ (input_line_pointer
- before_reloc
),
3227 base
, before_reloc
- base
);
3229 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3231 memcpy (base
, save_buf
, p
- base
);
3233 offset
= nbytes
- size
;
3234 p
= frag_more ((int) nbytes
);
3235 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3236 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3241 while (*input_line_pointer
++ == ',');
3243 /* Put terminator back into stream. */
3244 input_line_pointer
--;
3245 demand_empty_rest_of_line ();
3248 /* Emit an expression containing a 32-bit thumb instruction.
3249 Implementation based on put_thumb32_insn. */
3252 emit_thumb32_expr (expressionS
* exp
)
3254 expressionS exp_high
= *exp
;
3256 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3257 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3258 exp
->X_add_number
&= 0xffff;
3259 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3262 /* Guess the instruction size based on the opcode. */
3265 thumb_insn_size (int opcode
)
3267 if ((unsigned int) opcode
< 0xe800u
)
3269 else if ((unsigned int) opcode
>= 0xe8000000u
)
3276 emit_insn (expressionS
*exp
, int nbytes
)
3280 if (exp
->X_op
== O_constant
)
3285 size
= thumb_insn_size (exp
->X_add_number
);
3289 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3291 as_bad (_(".inst.n operand too big. "\
3292 "Use .inst.w instead"));
3297 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3298 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3300 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3302 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3303 emit_thumb32_expr (exp
);
3305 emit_expr (exp
, (unsigned int) size
);
3307 it_fsm_post_encode ();
3311 as_bad (_("cannot determine Thumb instruction size. " \
3312 "Use .inst.n/.inst.w instead"));
3315 as_bad (_("constant expression required"));
3320 /* Like s_arm_elf_cons but do not use md_cons_align and
3321 set the mapping state to MAP_ARM/MAP_THUMB. */
3324 s_arm_elf_inst (int nbytes
)
3326 if (is_it_end_of_statement ())
3328 demand_empty_rest_of_line ();
3332 /* Calling mapping_state () here will not change ARM/THUMB,
3333 but will ensure not to be in DATA state. */
3336 mapping_state (MAP_THUMB
);
3341 as_bad (_("width suffixes are invalid in ARM mode"));
3342 ignore_rest_of_line ();
3348 mapping_state (MAP_ARM
);
3357 if (! emit_insn (& exp
, nbytes
))
3359 ignore_rest_of_line ();
3363 while (*input_line_pointer
++ == ',');
3365 /* Put terminator back into stream. */
3366 input_line_pointer
--;
3367 demand_empty_rest_of_line ();
3370 /* Parse a .rel31 directive. */
3373 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3380 if (*input_line_pointer
== '1')
3381 highbit
= 0x80000000;
3382 else if (*input_line_pointer
!= '0')
3383 as_bad (_("expected 0 or 1"));
3385 input_line_pointer
++;
3386 if (*input_line_pointer
!= ',')
3387 as_bad (_("missing comma"));
3388 input_line_pointer
++;
3390 #ifdef md_flush_pending_output
3391 md_flush_pending_output ();
3394 #ifdef md_cons_align
3398 mapping_state (MAP_DATA
);
3403 md_number_to_chars (p
, highbit
, 4);
3404 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3405 BFD_RELOC_ARM_PREL31
);
3407 demand_empty_rest_of_line ();
3410 /* Directives: AEABI stack-unwind tables. */
3412 /* Parse an unwind_fnstart directive. Simply records the current location. */
3415 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3417 demand_empty_rest_of_line ();
3418 if (unwind
.proc_start
)
3420 as_bad (_("duplicate .fnstart directive"));
3424 /* Mark the start of the function. */
3425 unwind
.proc_start
= expr_build_dot ();
3427 /* Reset the rest of the unwind info. */
3428 unwind
.opcode_count
= 0;
3429 unwind
.table_entry
= NULL
;
3430 unwind
.personality_routine
= NULL
;
3431 unwind
.personality_index
= -1;
3432 unwind
.frame_size
= 0;
3433 unwind
.fp_offset
= 0;
3434 unwind
.fp_reg
= REG_SP
;
3436 unwind
.sp_restored
= 0;
3440 /* Parse a handlerdata directive. Creates the exception handling table entry
3441 for the function. */
3444 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3446 demand_empty_rest_of_line ();
3447 if (!unwind
.proc_start
)
3448 as_bad (MISSING_FNSTART
);
3450 if (unwind
.table_entry
)
3451 as_bad (_("duplicate .handlerdata directive"));
3453 create_unwind_entry (1);
3456 /* Parse an unwind_fnend directive. Generates the index table entry. */
3459 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3464 unsigned int marked_pr_dependency
;
3466 demand_empty_rest_of_line ();
3468 if (!unwind
.proc_start
)
3470 as_bad (_(".fnend directive without .fnstart"));
3474 /* Add eh table entry. */
3475 if (unwind
.table_entry
== NULL
)
3476 val
= create_unwind_entry (0);
3480 /* Add index table entry. This is two words. */
3481 start_unwind_section (unwind
.saved_seg
, 1);
3482 frag_align (2, 0, 0);
3483 record_alignment (now_seg
, 2);
3485 ptr
= frag_more (8);
3486 where
= frag_now_fix () - 8;
3488 /* Self relative offset of the function start. */
3489 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3490 BFD_RELOC_ARM_PREL31
);
3492 /* Indicate dependency on EHABI-defined personality routines to the
3493 linker, if it hasn't been done already. */
3494 marked_pr_dependency
3495 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3496 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3497 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3499 static const char *const name
[] =
3501 "__aeabi_unwind_cpp_pr0",
3502 "__aeabi_unwind_cpp_pr1",
3503 "__aeabi_unwind_cpp_pr2"
3505 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3506 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3507 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3508 |= 1 << unwind
.personality_index
;
3512 /* Inline exception table entry. */
3513 md_number_to_chars (ptr
+ 4, val
, 4);
3515 /* Self relative offset of the table entry. */
3516 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3517 BFD_RELOC_ARM_PREL31
);
3519 /* Restore the original section. */
3520 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3522 unwind
.proc_start
= NULL
;
3526 /* Parse an unwind_cantunwind directive. */
3529 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3531 demand_empty_rest_of_line ();
3532 if (!unwind
.proc_start
)
3533 as_bad (MISSING_FNSTART
);
3535 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3536 as_bad (_("personality routine specified for cantunwind frame"));
3538 unwind
.personality_index
= -2;
3542 /* Parse a personalityindex directive. */
3545 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3549 if (!unwind
.proc_start
)
3550 as_bad (MISSING_FNSTART
);
3552 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3553 as_bad (_("duplicate .personalityindex directive"));
3557 if (exp
.X_op
!= O_constant
3558 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3560 as_bad (_("bad personality routine number"));
3561 ignore_rest_of_line ();
3565 unwind
.personality_index
= exp
.X_add_number
;
3567 demand_empty_rest_of_line ();
3571 /* Parse a personality directive. */
3574 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3578 if (!unwind
.proc_start
)
3579 as_bad (MISSING_FNSTART
);
3581 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3582 as_bad (_("duplicate .personality directive"));
3584 name
= input_line_pointer
;
3585 c
= get_symbol_end ();
3586 p
= input_line_pointer
;
3587 unwind
.personality_routine
= symbol_find_or_make (name
);
3589 demand_empty_rest_of_line ();
3593 /* Parse a directive saving core registers. */
3596 s_arm_unwind_save_core (void)
3602 range
= parse_reg_list (&input_line_pointer
);
3605 as_bad (_("expected register list"));
3606 ignore_rest_of_line ();
3610 demand_empty_rest_of_line ();
3612 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3613 into .unwind_save {..., sp...}. We aren't bothered about the value of
3614 ip because it is clobbered by calls. */
3615 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3616 && (range
& 0x3000) == 0x1000)
3618 unwind
.opcode_count
--;
3619 unwind
.sp_restored
= 0;
3620 range
= (range
| 0x2000) & ~0x1000;
3621 unwind
.pending_offset
= 0;
3627 /* See if we can use the short opcodes. These pop a block of up to 8
3628 registers starting with r4, plus maybe r14. */
3629 for (n
= 0; n
< 8; n
++)
3631 /* Break at the first non-saved register. */
3632 if ((range
& (1 << (n
+ 4))) == 0)
3635 /* See if there are any other bits set. */
3636 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3638 /* Use the long form. */
3639 op
= 0x8000 | ((range
>> 4) & 0xfff);
3640 add_unwind_opcode (op
, 2);
3644 /* Use the short form. */
3646 op
= 0xa8; /* Pop r14. */
3648 op
= 0xa0; /* Do not pop r14. */
3650 add_unwind_opcode (op
, 1);
3657 op
= 0xb100 | (range
& 0xf);
3658 add_unwind_opcode (op
, 2);
3661 /* Record the number of bytes pushed. */
3662 for (n
= 0; n
< 16; n
++)
3664 if (range
& (1 << n
))
3665 unwind
.frame_size
+= 4;
3670 /* Parse a directive saving FPA registers. */
3673 s_arm_unwind_save_fpa (int reg
)
3679 /* Get Number of registers to transfer. */
3680 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3683 exp
.X_op
= O_illegal
;
3685 if (exp
.X_op
!= O_constant
)
3687 as_bad (_("expected , <constant>"));
3688 ignore_rest_of_line ();
3692 num_regs
= exp
.X_add_number
;
3694 if (num_regs
< 1 || num_regs
> 4)
3696 as_bad (_("number of registers must be in the range [1:4]"));
3697 ignore_rest_of_line ();
3701 demand_empty_rest_of_line ();
3706 op
= 0xb4 | (num_regs
- 1);
3707 add_unwind_opcode (op
, 1);
3712 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3713 add_unwind_opcode (op
, 2);
3715 unwind
.frame_size
+= num_regs
* 12;
3719 /* Parse a directive saving VFP registers for ARMv6 and above. */
3722 s_arm_unwind_save_vfp_armv6 (void)
3727 int num_vfpv3_regs
= 0;
3728 int num_regs_below_16
;
3730 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3733 as_bad (_("expected register list"));
3734 ignore_rest_of_line ();
3738 demand_empty_rest_of_line ();
3740 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3741 than FSTMX/FLDMX-style ones). */
3743 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3745 num_vfpv3_regs
= count
;
3746 else if (start
+ count
> 16)
3747 num_vfpv3_regs
= start
+ count
- 16;
3749 if (num_vfpv3_regs
> 0)
3751 int start_offset
= start
> 16 ? start
- 16 : 0;
3752 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3753 add_unwind_opcode (op
, 2);
3756 /* Generate opcode for registers numbered in the range 0 .. 15. */
3757 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3758 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3759 if (num_regs_below_16
> 0)
3761 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3762 add_unwind_opcode (op
, 2);
3765 unwind
.frame_size
+= count
* 8;
3769 /* Parse a directive saving VFP registers for pre-ARMv6. */
3772 s_arm_unwind_save_vfp (void)
3778 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3781 as_bad (_("expected register list"));
3782 ignore_rest_of_line ();
3786 demand_empty_rest_of_line ();
3791 op
= 0xb8 | (count
- 1);
3792 add_unwind_opcode (op
, 1);
3797 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3798 add_unwind_opcode (op
, 2);
3800 unwind
.frame_size
+= count
* 8 + 4;
3804 /* Parse a directive saving iWMMXt data registers. */
3807 s_arm_unwind_save_mmxwr (void)
3815 if (*input_line_pointer
== '{')
3816 input_line_pointer
++;
3820 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3824 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3829 as_tsktsk (_("register list not in ascending order"));
3832 if (*input_line_pointer
== '-')
3834 input_line_pointer
++;
3835 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3838 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3841 else if (reg
>= hi_reg
)
3843 as_bad (_("bad register range"));
3846 for (; reg
< hi_reg
; reg
++)
3850 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3852 if (*input_line_pointer
== '}')
3853 input_line_pointer
++;
3855 demand_empty_rest_of_line ();
3857 /* Generate any deferred opcodes because we're going to be looking at
3859 flush_pending_unwind ();
3861 for (i
= 0; i
< 16; i
++)
3863 if (mask
& (1 << i
))
3864 unwind
.frame_size
+= 8;
3867 /* Attempt to combine with a previous opcode. We do this because gcc
3868 likes to output separate unwind directives for a single block of
3870 if (unwind
.opcode_count
> 0)
3872 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3873 if ((i
& 0xf8) == 0xc0)
3876 /* Only merge if the blocks are contiguous. */
3879 if ((mask
& 0xfe00) == (1 << 9))
3881 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3882 unwind
.opcode_count
--;
3885 else if (i
== 6 && unwind
.opcode_count
>= 2)
3887 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3891 op
= 0xffff << (reg
- 1);
3893 && ((mask
& op
) == (1u << (reg
- 1))))
3895 op
= (1 << (reg
+ i
+ 1)) - 1;
3896 op
&= ~((1 << reg
) - 1);
3898 unwind
.opcode_count
-= 2;
3905 /* We want to generate opcodes in the order the registers have been
3906 saved, ie. descending order. */
3907 for (reg
= 15; reg
>= -1; reg
--)
3909 /* Save registers in blocks. */
3911 || !(mask
& (1 << reg
)))
3913 /* We found an unsaved reg. Generate opcodes to save the
3920 op
= 0xc0 | (hi_reg
- 10);
3921 add_unwind_opcode (op
, 1);
3926 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3927 add_unwind_opcode (op
, 2);
3936 ignore_rest_of_line ();
3940 s_arm_unwind_save_mmxwcg (void)
3947 if (*input_line_pointer
== '{')
3948 input_line_pointer
++;
3952 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3956 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3962 as_tsktsk (_("register list not in ascending order"));
3965 if (*input_line_pointer
== '-')
3967 input_line_pointer
++;
3968 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3971 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3974 else if (reg
>= hi_reg
)
3976 as_bad (_("bad register range"));
3979 for (; reg
< hi_reg
; reg
++)
3983 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3985 if (*input_line_pointer
== '}')
3986 input_line_pointer
++;
3988 demand_empty_rest_of_line ();
3990 /* Generate any deferred opcodes because we're going to be looking at
3992 flush_pending_unwind ();
3994 for (reg
= 0; reg
< 16; reg
++)
3996 if (mask
& (1 << reg
))
3997 unwind
.frame_size
+= 4;
4000 add_unwind_opcode (op
, 2);
4003 ignore_rest_of_line ();
4007 /* Parse an unwind_save directive.
4008 If the argument is non-zero, this is a .vsave directive. */
4011 s_arm_unwind_save (int arch_v6
)
4014 struct reg_entry
*reg
;
4015 bfd_boolean had_brace
= FALSE
;
4017 if (!unwind
.proc_start
)
4018 as_bad (MISSING_FNSTART
);
4020 /* Figure out what sort of save we have. */
4021 peek
= input_line_pointer
;
4029 reg
= arm_reg_parse_multi (&peek
);
4033 as_bad (_("register expected"));
4034 ignore_rest_of_line ();
4043 as_bad (_("FPA .unwind_save does not take a register list"));
4044 ignore_rest_of_line ();
4047 input_line_pointer
= peek
;
4048 s_arm_unwind_save_fpa (reg
->number
);
4051 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4054 s_arm_unwind_save_vfp_armv6 ();
4056 s_arm_unwind_save_vfp ();
4058 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4059 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4062 as_bad (_(".unwind_save does not support this kind of register"));
4063 ignore_rest_of_line ();
4068 /* Parse an unwind_movsp directive. */
4071 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4077 if (!unwind
.proc_start
)
4078 as_bad (MISSING_FNSTART
);
4080 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4083 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4084 ignore_rest_of_line ();
4088 /* Optional constant. */
4089 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4091 if (immediate_for_directive (&offset
) == FAIL
)
4097 demand_empty_rest_of_line ();
4099 if (reg
== REG_SP
|| reg
== REG_PC
)
4101 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4105 if (unwind
.fp_reg
!= REG_SP
)
4106 as_bad (_("unexpected .unwind_movsp directive"));
4108 /* Generate opcode to restore the value. */
4110 add_unwind_opcode (op
, 1);
4112 /* Record the information for later. */
4113 unwind
.fp_reg
= reg
;
4114 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4115 unwind
.sp_restored
= 1;
4118 /* Parse an unwind_pad directive. */
4121 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4125 if (!unwind
.proc_start
)
4126 as_bad (MISSING_FNSTART
);
4128 if (immediate_for_directive (&offset
) == FAIL
)
4133 as_bad (_("stack increment must be multiple of 4"));
4134 ignore_rest_of_line ();
4138 /* Don't generate any opcodes, just record the details for later. */
4139 unwind
.frame_size
+= offset
;
4140 unwind
.pending_offset
+= offset
;
4142 demand_empty_rest_of_line ();
4145 /* Parse an unwind_setfp directive. */
4148 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4154 if (!unwind
.proc_start
)
4155 as_bad (MISSING_FNSTART
);
4157 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4158 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4161 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4163 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4165 as_bad (_("expected <reg>, <reg>"));
4166 ignore_rest_of_line ();
4170 /* Optional constant. */
4171 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4173 if (immediate_for_directive (&offset
) == FAIL
)
4179 demand_empty_rest_of_line ();
4181 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4183 as_bad (_("register must be either sp or set by a previous"
4184 "unwind_movsp directive"));
4188 /* Don't generate any opcodes, just record the information for later. */
4189 unwind
.fp_reg
= fp_reg
;
4191 if (sp_reg
== REG_SP
)
4192 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4194 unwind
.fp_offset
-= offset
;
4197 /* Parse an unwind_raw directive. */
4200 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4203 /* This is an arbitrary limit. */
4204 unsigned char op
[16];
4207 if (!unwind
.proc_start
)
4208 as_bad (MISSING_FNSTART
);
4211 if (exp
.X_op
== O_constant
4212 && skip_past_comma (&input_line_pointer
) != FAIL
)
4214 unwind
.frame_size
+= exp
.X_add_number
;
4218 exp
.X_op
= O_illegal
;
4220 if (exp
.X_op
!= O_constant
)
4222 as_bad (_("expected <offset>, <opcode>"));
4223 ignore_rest_of_line ();
4229 /* Parse the opcode. */
4234 as_bad (_("unwind opcode too long"));
4235 ignore_rest_of_line ();
4237 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4239 as_bad (_("invalid unwind opcode"));
4240 ignore_rest_of_line ();
4243 op
[count
++] = exp
.X_add_number
;
4245 /* Parse the next byte. */
4246 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4252 /* Add the opcode bytes in reverse order. */
4254 add_unwind_opcode (op
[count
], 1);
4256 demand_empty_rest_of_line ();
4260 /* Parse a .eabi_attribute directive. */
4263 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4265 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4267 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4268 attributes_set_explicitly
[tag
] = 1;
4270 #endif /* OBJ_ELF */
4272 static void s_arm_arch (int);
4273 static void s_arm_object_arch (int);
4274 static void s_arm_cpu (int);
4275 static void s_arm_fpu (int);
4276 static void s_arm_arch_extension (int);
4281 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4288 if (exp
.X_op
== O_symbol
)
4289 exp
.X_op
= O_secrel
;
4291 emit_expr (&exp
, 4);
4293 while (*input_line_pointer
++ == ',');
4295 input_line_pointer
--;
4296 demand_empty_rest_of_line ();
4300 /* This table describes all the machine specific pseudo-ops the assembler
4301 has to support. The fields are:
4302 pseudo-op name without dot
4303 function to call to execute this pseudo-op
4304 Integer arg to pass to the function. */
4306 const pseudo_typeS md_pseudo_table
[] =
4308 /* Never called because '.req' does not start a line. */
4309 { "req", s_req
, 0 },
4310 /* Following two are likewise never called. */
4313 { "unreq", s_unreq
, 0 },
4314 { "bss", s_bss
, 0 },
4315 { "align", s_align
, 0 },
4316 { "arm", s_arm
, 0 },
4317 { "thumb", s_thumb
, 0 },
4318 { "code", s_code
, 0 },
4319 { "force_thumb", s_force_thumb
, 0 },
4320 { "thumb_func", s_thumb_func
, 0 },
4321 { "thumb_set", s_thumb_set
, 0 },
4322 { "even", s_even
, 0 },
4323 { "ltorg", s_ltorg
, 0 },
4324 { "pool", s_ltorg
, 0 },
4325 { "syntax", s_syntax
, 0 },
4326 { "cpu", s_arm_cpu
, 0 },
4327 { "arch", s_arm_arch
, 0 },
4328 { "object_arch", s_arm_object_arch
, 0 },
4329 { "fpu", s_arm_fpu
, 0 },
4330 { "arch_extension", s_arm_arch_extension
, 0 },
4332 { "word", s_arm_elf_cons
, 4 },
4333 { "long", s_arm_elf_cons
, 4 },
4334 { "inst.n", s_arm_elf_inst
, 2 },
4335 { "inst.w", s_arm_elf_inst
, 4 },
4336 { "inst", s_arm_elf_inst
, 0 },
4337 { "rel31", s_arm_rel31
, 0 },
4338 { "fnstart", s_arm_unwind_fnstart
, 0 },
4339 { "fnend", s_arm_unwind_fnend
, 0 },
4340 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4341 { "personality", s_arm_unwind_personality
, 0 },
4342 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4343 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4344 { "save", s_arm_unwind_save
, 0 },
4345 { "vsave", s_arm_unwind_save
, 1 },
4346 { "movsp", s_arm_unwind_movsp
, 0 },
4347 { "pad", s_arm_unwind_pad
, 0 },
4348 { "setfp", s_arm_unwind_setfp
, 0 },
4349 { "unwind_raw", s_arm_unwind_raw
, 0 },
4350 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4354 /* These are used for dwarf. */
4358 /* These are used for dwarf2. */
4359 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4360 { "loc", dwarf2_directive_loc
, 0 },
4361 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4363 { "extend", float_cons
, 'x' },
4364 { "ldouble", float_cons
, 'x' },
4365 { "packed", float_cons
, 'p' },
4367 {"secrel32", pe_directive_secrel
, 0},
4372 /* Parser functions used exclusively in instruction operands. */
4374 /* Generic immediate-value read function for use in insn parsing.
4375 STR points to the beginning of the immediate (the leading #);
4376 VAL receives the value; if the value is outside [MIN, MAX]
4377 issue an error. PREFIX_OPT is true if the immediate prefix is
4381 parse_immediate (char **str
, int *val
, int min
, int max
,
4382 bfd_boolean prefix_opt
)
4385 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4386 if (exp
.X_op
!= O_constant
)
4388 inst
.error
= _("constant expression required");
4392 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4394 inst
.error
= _("immediate value out of range");
4398 *val
= exp
.X_add_number
;
4402 /* Less-generic immediate-value read function with the possibility of loading a
4403 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4404 instructions. Puts the result directly in inst.operands[i]. */
4407 parse_big_immediate (char **str
, int i
)
4412 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4414 if (exp
.X_op
== O_constant
)
4416 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4417 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4418 O_constant. We have to be careful not to break compilation for
4419 32-bit X_add_number, though. */
4420 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4422 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4423 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4424 inst
.operands
[i
].regisimm
= 1;
4427 else if (exp
.X_op
== O_big
4428 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4430 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4432 /* Bignums have their least significant bits in
4433 generic_bignum[0]. Make sure we put 32 bits in imm and
4434 32 bits in reg, in a (hopefully) portable way. */
4435 gas_assert (parts
!= 0);
4437 /* Make sure that the number is not too big.
4438 PR 11972: Bignums can now be sign-extended to the
4439 size of a .octa so check that the out of range bits
4440 are all zero or all one. */
4441 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4443 LITTLENUM_TYPE m
= -1;
4445 if (generic_bignum
[parts
* 2] != 0
4446 && generic_bignum
[parts
* 2] != m
)
4449 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4450 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4454 inst
.operands
[i
].imm
= 0;
4455 for (j
= 0; j
< parts
; j
++, idx
++)
4456 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4457 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4458 inst
.operands
[i
].reg
= 0;
4459 for (j
= 0; j
< parts
; j
++, idx
++)
4460 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4461 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4462 inst
.operands
[i
].regisimm
= 1;
4472 /* Returns the pseudo-register number of an FPA immediate constant,
4473 or FAIL if there isn't a valid constant here. */
4476 parse_fpa_immediate (char ** str
)
4478 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4484 /* First try and match exact strings, this is to guarantee
4485 that some formats will work even for cross assembly. */
4487 for (i
= 0; fp_const
[i
]; i
++)
4489 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4493 *str
+= strlen (fp_const
[i
]);
4494 if (is_end_of_line
[(unsigned char) **str
])
4500 /* Just because we didn't get a match doesn't mean that the constant
4501 isn't valid, just that it is in a format that we don't
4502 automatically recognize. Try parsing it with the standard
4503 expression routines. */
4505 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4507 /* Look for a raw floating point number. */
4508 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4509 && is_end_of_line
[(unsigned char) *save_in
])
4511 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4513 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4515 if (words
[j
] != fp_values
[i
][j
])
4519 if (j
== MAX_LITTLENUMS
)
4527 /* Try and parse a more complex expression, this will probably fail
4528 unless the code uses a floating point prefix (eg "0f"). */
4529 save_in
= input_line_pointer
;
4530 input_line_pointer
= *str
;
4531 if (expression (&exp
) == absolute_section
4532 && exp
.X_op
== O_big
4533 && exp
.X_add_number
< 0)
4535 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4537 if (gen_to_words (words
, 5, (long) 15) == 0)
4539 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4541 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4543 if (words
[j
] != fp_values
[i
][j
])
4547 if (j
== MAX_LITTLENUMS
)
4549 *str
= input_line_pointer
;
4550 input_line_pointer
= save_in
;
4557 *str
= input_line_pointer
;
4558 input_line_pointer
= save_in
;
4559 inst
.error
= _("invalid FPA immediate expression");
4563 /* Returns 1 if a number has "quarter-precision" float format
4564 0baBbbbbbc defgh000 00000000 00000000. */
4567 is_quarter_float (unsigned imm
)
4569 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4570 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4573 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4574 0baBbbbbbc defgh000 00000000 00000000.
4575 The zero and minus-zero cases need special handling, since they can't be
4576 encoded in the "quarter-precision" float format, but can nonetheless be
4577 loaded as integer constants. */
4580 parse_qfloat_immediate (char **ccp
, int *immed
)
4584 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4585 int found_fpchar
= 0;
4587 skip_past_char (&str
, '#');
4589 /* We must not accidentally parse an integer as a floating-point number. Make
4590 sure that the value we parse is not an integer by checking for special
4591 characters '.' or 'e'.
4592 FIXME: This is a horrible hack, but doing better is tricky because type
4593 information isn't in a very usable state at parse time. */
4595 skip_whitespace (fpnum
);
4597 if (strncmp (fpnum
, "0x", 2) == 0)
4601 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4602 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4612 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4614 unsigned fpword
= 0;
4617 /* Our FP word must be 32 bits (single-precision FP). */
4618 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4620 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4624 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4637 /* Shift operands. */
4640 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4643 struct asm_shift_name
4646 enum shift_kind kind
;
4649 /* Third argument to parse_shift. */
4650 enum parse_shift_mode
4652 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4653 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4654 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4655 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4656 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4659 /* Parse a <shift> specifier on an ARM data processing instruction.
4660 This has three forms:
4662 (LSL|LSR|ASL|ASR|ROR) Rs
4663 (LSL|LSR|ASL|ASR|ROR) #imm
4666 Note that ASL is assimilated to LSL in the instruction encoding, and
4667 RRX to ROR #0 (which cannot be written as such). */
4670 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4672 const struct asm_shift_name
*shift_name
;
4673 enum shift_kind shift
;
4678 for (p
= *str
; ISALPHA (*p
); p
++)
4683 inst
.error
= _("shift expression expected");
4687 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4690 if (shift_name
== NULL
)
4692 inst
.error
= _("shift expression expected");
4696 shift
= shift_name
->kind
;
4700 case NO_SHIFT_RESTRICT
:
4701 case SHIFT_IMMEDIATE
: break;
4703 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4704 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4706 inst
.error
= _("'LSL' or 'ASR' required");
4711 case SHIFT_LSL_IMMEDIATE
:
4712 if (shift
!= SHIFT_LSL
)
4714 inst
.error
= _("'LSL' required");
4719 case SHIFT_ASR_IMMEDIATE
:
4720 if (shift
!= SHIFT_ASR
)
4722 inst
.error
= _("'ASR' required");
4730 if (shift
!= SHIFT_RRX
)
4732 /* Whitespace can appear here if the next thing is a bare digit. */
4733 skip_whitespace (p
);
4735 if (mode
== NO_SHIFT_RESTRICT
4736 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4738 inst
.operands
[i
].imm
= reg
;
4739 inst
.operands
[i
].immisreg
= 1;
4741 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4744 inst
.operands
[i
].shift_kind
= shift
;
4745 inst
.operands
[i
].shifted
= 1;
4750 /* Parse a <shifter_operand> for an ARM data processing instruction:
4753 #<immediate>, <rotate>
4757 where <shift> is defined by parse_shift above, and <rotate> is a
4758 multiple of 2 between 0 and 30. Validation of immediate operands
4759 is deferred to md_apply_fix. */
4762 parse_shifter_operand (char **str
, int i
)
4767 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4769 inst
.operands
[i
].reg
= value
;
4770 inst
.operands
[i
].isreg
= 1;
4772 /* parse_shift will override this if appropriate */
4773 inst
.reloc
.exp
.X_op
= O_constant
;
4774 inst
.reloc
.exp
.X_add_number
= 0;
4776 if (skip_past_comma (str
) == FAIL
)
4779 /* Shift operation on register. */
4780 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4783 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4786 if (skip_past_comma (str
) == SUCCESS
)
4788 /* #x, y -- ie explicit rotation by Y. */
4789 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4792 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4794 inst
.error
= _("constant expression expected");
4798 value
= exp
.X_add_number
;
4799 if (value
< 0 || value
> 30 || value
% 2 != 0)
4801 inst
.error
= _("invalid rotation");
4804 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4806 inst
.error
= _("invalid constant");
4810 /* Convert to decoded value. md_apply_fix will put it back. */
4811 inst
.reloc
.exp
.X_add_number
4812 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4813 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4816 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4817 inst
.reloc
.pc_rel
= 0;
4821 /* Group relocation information. Each entry in the table contains the
4822 textual name of the relocation as may appear in assembler source
4823 and must end with a colon.
4824 Along with this textual name are the relocation codes to be used if
4825 the corresponding instruction is an ALU instruction (ADD or SUB only),
4826 an LDR, an LDRS, or an LDC. */
4828 struct group_reloc_table_entry
4839 /* Varieties of non-ALU group relocation. */
4846 static struct group_reloc_table_entry group_reloc_table
[] =
4847 { /* Program counter relative: */
4849 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4854 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4855 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4856 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4857 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4859 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4864 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4865 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4866 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4867 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4869 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4870 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4871 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4872 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4873 /* Section base relative */
4875 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4880 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4881 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4882 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4883 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4885 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4890 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4891 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4892 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4893 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4895 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4896 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4897 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4898 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4900 /* Given the address of a pointer pointing to the textual name of a group
4901 relocation as may appear in assembler source, attempt to find its details
4902 in group_reloc_table. The pointer will be updated to the character after
4903 the trailing colon. On failure, FAIL will be returned; SUCCESS
4904 otherwise. On success, *entry will be updated to point at the relevant
4905 group_reloc_table entry. */
4908 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4911 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4913 int length
= strlen (group_reloc_table
[i
].name
);
4915 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4916 && (*str
)[length
] == ':')
4918 *out
= &group_reloc_table
[i
];
4919 *str
+= (length
+ 1);
4927 /* Parse a <shifter_operand> for an ARM data processing instruction
4928 (as for parse_shifter_operand) where group relocations are allowed:
4931 #<immediate>, <rotate>
4932 #:<group_reloc>:<expression>
4936 where <group_reloc> is one of the strings defined in group_reloc_table.
4937 The hashes are optional.
4939 Everything else is as for parse_shifter_operand. */
4941 static parse_operand_result
4942 parse_shifter_operand_group_reloc (char **str
, int i
)
4944 /* Determine if we have the sequence of characters #: or just :
4945 coming next. If we do, then we check for a group relocation.
4946 If we don't, punt the whole lot to parse_shifter_operand. */
4948 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4949 || (*str
)[0] == ':')
4951 struct group_reloc_table_entry
*entry
;
4953 if ((*str
)[0] == '#')
4958 /* Try to parse a group relocation. Anything else is an error. */
4959 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4961 inst
.error
= _("unknown group relocation");
4962 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4965 /* We now have the group relocation table entry corresponding to
4966 the name in the assembler source. Next, we parse the expression. */
4967 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4968 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4970 /* Record the relocation type (always the ALU variant here). */
4971 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4972 gas_assert (inst
.reloc
.type
!= 0);
4974 return PARSE_OPERAND_SUCCESS
;
4977 return parse_shifter_operand (str
, i
) == SUCCESS
4978 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4980 /* Never reached. */
4983 /* Parse a Neon alignment expression. Information is written to
4984 inst.operands[i]. We assume the initial ':' has been skipped.
4986 align .imm = align << 8, .immisalign=1, .preind=0 */
4987 static parse_operand_result
4988 parse_neon_alignment (char **str
, int i
)
4993 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4995 if (exp
.X_op
!= O_constant
)
4997 inst
.error
= _("alignment must be constant");
4998 return PARSE_OPERAND_FAIL
;
5001 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5002 inst
.operands
[i
].immisalign
= 1;
5003 /* Alignments are not pre-indexes. */
5004 inst
.operands
[i
].preind
= 0;
5007 return PARSE_OPERAND_SUCCESS
;
5010 /* Parse all forms of an ARM address expression. Information is written
5011 to inst.operands[i] and/or inst.reloc.
5013 Preindexed addressing (.preind=1):
5015 [Rn, #offset] .reg=Rn .reloc.exp=offset
5016 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5017 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5018 .shift_kind=shift .reloc.exp=shift_imm
5020 These three may have a trailing ! which causes .writeback to be set also.
5022 Postindexed addressing (.postind=1, .writeback=1):
5024 [Rn], #offset .reg=Rn .reloc.exp=offset
5025 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5026 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5027 .shift_kind=shift .reloc.exp=shift_imm
5029 Unindexed addressing (.preind=0, .postind=0):
5031 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5035 [Rn]{!} shorthand for [Rn,#0]{!}
5036 =immediate .isreg=0 .reloc.exp=immediate
5037 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5039 It is the caller's responsibility to check for addressing modes not
5040 supported by the instruction, and to set inst.reloc.type. */
5042 static parse_operand_result
5043 parse_address_main (char **str
, int i
, int group_relocations
,
5044 group_reloc_type group_type
)
5049 if (skip_past_char (&p
, '[') == FAIL
)
5051 if (skip_past_char (&p
, '=') == FAIL
)
5053 /* Bare address - translate to PC-relative offset. */
5054 inst
.reloc
.pc_rel
= 1;
5055 inst
.operands
[i
].reg
= REG_PC
;
5056 inst
.operands
[i
].isreg
= 1;
5057 inst
.operands
[i
].preind
= 1;
5059 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5061 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5062 return PARSE_OPERAND_FAIL
;
5065 return PARSE_OPERAND_SUCCESS
;
5068 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5070 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5071 return PARSE_OPERAND_FAIL
;
5073 inst
.operands
[i
].reg
= reg
;
5074 inst
.operands
[i
].isreg
= 1;
5076 if (skip_past_comma (&p
) == SUCCESS
)
5078 inst
.operands
[i
].preind
= 1;
5081 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5083 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5085 inst
.operands
[i
].imm
= reg
;
5086 inst
.operands
[i
].immisreg
= 1;
5088 if (skip_past_comma (&p
) == SUCCESS
)
5089 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5090 return PARSE_OPERAND_FAIL
;
5092 else if (skip_past_char (&p
, ':') == SUCCESS
)
5094 /* FIXME: '@' should be used here, but it's filtered out by generic
5095 code before we get to see it here. This may be subject to
5097 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5099 if (result
!= PARSE_OPERAND_SUCCESS
)
5104 if (inst
.operands
[i
].negative
)
5106 inst
.operands
[i
].negative
= 0;
5110 if (group_relocations
5111 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5113 struct group_reloc_table_entry
*entry
;
5115 /* Skip over the #: or : sequence. */
5121 /* Try to parse a group relocation. Anything else is an
5123 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5125 inst
.error
= _("unknown group relocation");
5126 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5129 /* We now have the group relocation table entry corresponding to
5130 the name in the assembler source. Next, we parse the
5132 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5133 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5135 /* Record the relocation type. */
5139 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5143 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5147 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5154 if (inst
.reloc
.type
== 0)
5156 inst
.error
= _("this group relocation is not allowed on this instruction");
5157 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5161 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5162 return PARSE_OPERAND_FAIL
;
5165 else if (skip_past_char (&p
, ':') == SUCCESS
)
5167 /* FIXME: '@' should be used here, but it's filtered out by generic code
5168 before we get to see it here. This may be subject to change. */
5169 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5171 if (result
!= PARSE_OPERAND_SUCCESS
)
5175 if (skip_past_char (&p
, ']') == FAIL
)
5177 inst
.error
= _("']' expected");
5178 return PARSE_OPERAND_FAIL
;
5181 if (skip_past_char (&p
, '!') == SUCCESS
)
5182 inst
.operands
[i
].writeback
= 1;
5184 else if (skip_past_comma (&p
) == SUCCESS
)
5186 if (skip_past_char (&p
, '{') == SUCCESS
)
5188 /* [Rn], {expr} - unindexed, with option */
5189 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5190 0, 255, TRUE
) == FAIL
)
5191 return PARSE_OPERAND_FAIL
;
5193 if (skip_past_char (&p
, '}') == FAIL
)
5195 inst
.error
= _("'}' expected at end of 'option' field");
5196 return PARSE_OPERAND_FAIL
;
5198 if (inst
.operands
[i
].preind
)
5200 inst
.error
= _("cannot combine index with option");
5201 return PARSE_OPERAND_FAIL
;
5204 return PARSE_OPERAND_SUCCESS
;
5208 inst
.operands
[i
].postind
= 1;
5209 inst
.operands
[i
].writeback
= 1;
5211 if (inst
.operands
[i
].preind
)
5213 inst
.error
= _("cannot combine pre- and post-indexing");
5214 return PARSE_OPERAND_FAIL
;
5218 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5220 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5222 /* We might be using the immediate for alignment already. If we
5223 are, OR the register number into the low-order bits. */
5224 if (inst
.operands
[i
].immisalign
)
5225 inst
.operands
[i
].imm
|= reg
;
5227 inst
.operands
[i
].imm
= reg
;
5228 inst
.operands
[i
].immisreg
= 1;
5230 if (skip_past_comma (&p
) == SUCCESS
)
5231 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5232 return PARSE_OPERAND_FAIL
;
5236 if (inst
.operands
[i
].negative
)
5238 inst
.operands
[i
].negative
= 0;
5241 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5242 return PARSE_OPERAND_FAIL
;
5247 /* If at this point neither .preind nor .postind is set, we have a
5248 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5249 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5251 inst
.operands
[i
].preind
= 1;
5252 inst
.reloc
.exp
.X_op
= O_constant
;
5253 inst
.reloc
.exp
.X_add_number
= 0;
5256 return PARSE_OPERAND_SUCCESS
;
5260 parse_address (char **str
, int i
)
5262 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5266 static parse_operand_result
5267 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5269 return parse_address_main (str
, i
, 1, type
);
5272 /* Parse an operand for a MOVW or MOVT instruction. */
5274 parse_half (char **str
)
5279 skip_past_char (&p
, '#');
5280 if (strncasecmp (p
, ":lower16:", 9) == 0)
5281 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5282 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5283 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5285 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5288 skip_whitespace (p
);
5291 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5294 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5296 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5298 inst
.error
= _("constant expression expected");
5301 if (inst
.reloc
.exp
.X_add_number
< 0
5302 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5304 inst
.error
= _("immediate value out of range");
5312 /* Miscellaneous. */
5314 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5315 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5317 parse_psr (char **str
)
5320 unsigned long psr_field
;
5321 const struct asm_psr
*psr
;
5324 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5325 feature for ease of use and backwards compatibility. */
5327 if (strncasecmp (p
, "SPSR", 4) == 0)
5328 psr_field
= SPSR_BIT
;
5329 else if (strncasecmp (p
, "CPSR", 4) == 0
5330 || (strncasecmp (p
, "APSR", 4) == 0
5331 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
)))
5338 while (ISALNUM (*p
) || *p
== '_');
5340 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5352 /* A suffix follows. */
5358 while (ISALNUM (*p
) || *p
== '_');
5360 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5365 psr_field
|= psr
->field
;
5370 goto error
; /* Garbage after "[CS]PSR". */
5372 psr_field
|= (PSR_c
| PSR_f
);
5378 inst
.error
= _("flag for {c}psr instruction expected");
5382 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5383 value suitable for splatting into the AIF field of the instruction. */
5386 parse_cps_flags (char **str
)
5395 case '\0': case ',':
5398 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5399 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5400 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5403 inst
.error
= _("unrecognized CPS flag");
5408 if (saw_a_flag
== 0)
5410 inst
.error
= _("missing CPS flags");
5418 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5419 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5422 parse_endian_specifier (char **str
)
5427 if (strncasecmp (s
, "BE", 2))
5429 else if (strncasecmp (s
, "LE", 2))
5433 inst
.error
= _("valid endian specifiers are be or le");
5437 if (ISALNUM (s
[2]) || s
[2] == '_')
5439 inst
.error
= _("valid endian specifiers are be or le");
5444 return little_endian
;
5447 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5448 value suitable for poking into the rotate field of an sxt or sxta
5449 instruction, or FAIL on error. */
5452 parse_ror (char **str
)
5457 if (strncasecmp (s
, "ROR", 3) == 0)
5461 inst
.error
= _("missing rotation field after comma");
5465 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5470 case 0: *str
= s
; return 0x0;
5471 case 8: *str
= s
; return 0x1;
5472 case 16: *str
= s
; return 0x2;
5473 case 24: *str
= s
; return 0x3;
5476 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5481 /* Parse a conditional code (from conds[] below). The value returned is in the
5482 range 0 .. 14, or FAIL. */
5484 parse_cond (char **str
)
5487 const struct asm_cond
*c
;
5489 /* Condition codes are always 2 characters, so matching up to
5490 3 characters is sufficient. */
5495 while (ISALPHA (*q
) && n
< 3)
5497 cond
[n
] = TOLOWER (*q
);
5502 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5505 inst
.error
= _("condition required");
5513 /* Parse an option for a barrier instruction. Returns the encoding for the
5516 parse_barrier (char **str
)
5519 const struct asm_barrier_opt
*o
;
5522 while (ISALPHA (*q
))
5525 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5534 /* Parse the operands of a table branch instruction. Similar to a memory
5537 parse_tb (char **str
)
5542 if (skip_past_char (&p
, '[') == FAIL
)
5544 inst
.error
= _("'[' expected");
5548 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5550 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5553 inst
.operands
[0].reg
= reg
;
5555 if (skip_past_comma (&p
) == FAIL
)
5557 inst
.error
= _("',' expected");
5561 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5563 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5566 inst
.operands
[0].imm
= reg
;
5568 if (skip_past_comma (&p
) == SUCCESS
)
5570 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5572 if (inst
.reloc
.exp
.X_add_number
!= 1)
5574 inst
.error
= _("invalid shift");
5577 inst
.operands
[0].shifted
= 1;
5580 if (skip_past_char (&p
, ']') == FAIL
)
5582 inst
.error
= _("']' expected");
5589 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5590 information on the types the operands can take and how they are encoded.
5591 Up to four operands may be read; this function handles setting the
5592 ".present" field for each read operand itself.
5593 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5594 else returns FAIL. */
5597 parse_neon_mov (char **str
, int *which_operand
)
5599 int i
= *which_operand
, val
;
5600 enum arm_reg_type rtype
;
5602 struct neon_type_el optype
;
5604 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5606 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5607 inst
.operands
[i
].reg
= val
;
5608 inst
.operands
[i
].isscalar
= 1;
5609 inst
.operands
[i
].vectype
= optype
;
5610 inst
.operands
[i
++].present
= 1;
5612 if (skip_past_comma (&ptr
) == FAIL
)
5615 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5618 inst
.operands
[i
].reg
= val
;
5619 inst
.operands
[i
].isreg
= 1;
5620 inst
.operands
[i
].present
= 1;
5622 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5625 /* Cases 0, 1, 2, 3, 5 (D only). */
5626 if (skip_past_comma (&ptr
) == FAIL
)
5629 inst
.operands
[i
].reg
= val
;
5630 inst
.operands
[i
].isreg
= 1;
5631 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5632 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5633 inst
.operands
[i
].isvec
= 1;
5634 inst
.operands
[i
].vectype
= optype
;
5635 inst
.operands
[i
++].present
= 1;
5637 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5639 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5640 Case 13: VMOV <Sd>, <Rm> */
5641 inst
.operands
[i
].reg
= val
;
5642 inst
.operands
[i
].isreg
= 1;
5643 inst
.operands
[i
].present
= 1;
5645 if (rtype
== REG_TYPE_NQ
)
5647 first_error (_("can't use Neon quad register here"));
5650 else if (rtype
!= REG_TYPE_VFS
)
5653 if (skip_past_comma (&ptr
) == FAIL
)
5655 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5657 inst
.operands
[i
].reg
= val
;
5658 inst
.operands
[i
].isreg
= 1;
5659 inst
.operands
[i
].present
= 1;
5662 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5665 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5666 Case 1: VMOV<c><q> <Dd>, <Dm>
5667 Case 8: VMOV.F32 <Sd>, <Sm>
5668 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5670 inst
.operands
[i
].reg
= val
;
5671 inst
.operands
[i
].isreg
= 1;
5672 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5673 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5674 inst
.operands
[i
].isvec
= 1;
5675 inst
.operands
[i
].vectype
= optype
;
5676 inst
.operands
[i
].present
= 1;
5678 if (skip_past_comma (&ptr
) == SUCCESS
)
5683 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5686 inst
.operands
[i
].reg
= val
;
5687 inst
.operands
[i
].isreg
= 1;
5688 inst
.operands
[i
++].present
= 1;
5690 if (skip_past_comma (&ptr
) == FAIL
)
5693 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5696 inst
.operands
[i
].reg
= val
;
5697 inst
.operands
[i
].isreg
= 1;
5698 inst
.operands
[i
++].present
= 1;
5701 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5702 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5703 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5704 Case 10: VMOV.F32 <Sd>, #<imm>
5705 Case 11: VMOV.F64 <Dd>, #<imm> */
5706 inst
.operands
[i
].immisfloat
= 1;
5707 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5708 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5709 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5713 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5717 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5720 inst
.operands
[i
].reg
= val
;
5721 inst
.operands
[i
].isreg
= 1;
5722 inst
.operands
[i
++].present
= 1;
5724 if (skip_past_comma (&ptr
) == FAIL
)
5727 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5729 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5730 inst
.operands
[i
].reg
= val
;
5731 inst
.operands
[i
].isscalar
= 1;
5732 inst
.operands
[i
].present
= 1;
5733 inst
.operands
[i
].vectype
= optype
;
5735 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5737 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5738 inst
.operands
[i
].reg
= val
;
5739 inst
.operands
[i
].isreg
= 1;
5740 inst
.operands
[i
++].present
= 1;
5742 if (skip_past_comma (&ptr
) == FAIL
)
5745 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5748 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5752 inst
.operands
[i
].reg
= val
;
5753 inst
.operands
[i
].isreg
= 1;
5754 inst
.operands
[i
].isvec
= 1;
5755 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5756 inst
.operands
[i
].vectype
= optype
;
5757 inst
.operands
[i
].present
= 1;
5759 if (rtype
== REG_TYPE_VFS
)
5763 if (skip_past_comma (&ptr
) == FAIL
)
5765 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5768 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5771 inst
.operands
[i
].reg
= val
;
5772 inst
.operands
[i
].isreg
= 1;
5773 inst
.operands
[i
].isvec
= 1;
5774 inst
.operands
[i
].issingle
= 1;
5775 inst
.operands
[i
].vectype
= optype
;
5776 inst
.operands
[i
].present
= 1;
5779 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5783 inst
.operands
[i
].reg
= val
;
5784 inst
.operands
[i
].isreg
= 1;
5785 inst
.operands
[i
].isvec
= 1;
5786 inst
.operands
[i
].issingle
= 1;
5787 inst
.operands
[i
].vectype
= optype
;
5788 inst
.operands
[i
++].present
= 1;
5793 first_error (_("parse error"));
5797 /* Successfully parsed the operands. Update args. */
5803 first_error (_("expected comma"));
5807 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5811 /* Use this macro when the operand constraints are different
5812 for ARM and THUMB (e.g. ldrd). */
5813 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5814 ((arm_operand) | ((thumb_operand) << 16))
5816 /* Matcher codes for parse_operands. */
5817 enum operand_parse_code
5819 OP_stop
, /* end of line */
5821 OP_RR
, /* ARM register */
5822 OP_RRnpc
, /* ARM register, not r15 */
5823 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5824 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5825 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5826 optional trailing ! */
5827 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5828 OP_RCP
, /* Coprocessor number */
5829 OP_RCN
, /* Coprocessor register */
5830 OP_RF
, /* FPA register */
5831 OP_RVS
, /* VFP single precision register */
5832 OP_RVD
, /* VFP double precision register (0..15) */
5833 OP_RND
, /* Neon double precision register (0..31) */
5834 OP_RNQ
, /* Neon quad precision register */
5835 OP_RVSD
, /* VFP single or double precision register */
5836 OP_RNDQ
, /* Neon double or quad precision register */
5837 OP_RNSDQ
, /* Neon single, double or quad precision register */
5838 OP_RNSC
, /* Neon scalar D[X] */
5839 OP_RVC
, /* VFP control register */
5840 OP_RMF
, /* Maverick F register */
5841 OP_RMD
, /* Maverick D register */
5842 OP_RMFX
, /* Maverick FX register */
5843 OP_RMDX
, /* Maverick DX register */
5844 OP_RMAX
, /* Maverick AX register */
5845 OP_RMDS
, /* Maverick DSPSC register */
5846 OP_RIWR
, /* iWMMXt wR register */
5847 OP_RIWC
, /* iWMMXt wC register */
5848 OP_RIWG
, /* iWMMXt wCG register */
5849 OP_RXA
, /* XScale accumulator register */
5851 OP_REGLST
, /* ARM register list */
5852 OP_VRSLST
, /* VFP single-precision register list */
5853 OP_VRDLST
, /* VFP double-precision register list */
5854 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5855 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5856 OP_NSTRLST
, /* Neon element/structure list */
5858 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5859 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5860 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5861 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5862 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5863 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5864 OP_VMOV
, /* Neon VMOV operands. */
5865 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5866 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5867 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5869 OP_I0
, /* immediate zero */
5870 OP_I7
, /* immediate value 0 .. 7 */
5871 OP_I15
, /* 0 .. 15 */
5872 OP_I16
, /* 1 .. 16 */
5873 OP_I16z
, /* 0 .. 16 */
5874 OP_I31
, /* 0 .. 31 */
5875 OP_I31w
, /* 0 .. 31, optional trailing ! */
5876 OP_I32
, /* 1 .. 32 */
5877 OP_I32z
, /* 0 .. 32 */
5878 OP_I63
, /* 0 .. 63 */
5879 OP_I63s
, /* -64 .. 63 */
5880 OP_I64
, /* 1 .. 64 */
5881 OP_I64z
, /* 0 .. 64 */
5882 OP_I255
, /* 0 .. 255 */
5884 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5885 OP_I7b
, /* 0 .. 7 */
5886 OP_I15b
, /* 0 .. 15 */
5887 OP_I31b
, /* 0 .. 31 */
5889 OP_SH
, /* shifter operand */
5890 OP_SHG
, /* shifter operand with possible group relocation */
5891 OP_ADDR
, /* Memory address expression (any mode) */
5892 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5893 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5894 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5895 OP_EXP
, /* arbitrary expression */
5896 OP_EXPi
, /* same, with optional immediate prefix */
5897 OP_EXPr
, /* same, with optional relocation suffix */
5898 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5900 OP_CPSF
, /* CPS flags */
5901 OP_ENDI
, /* Endianness specifier */
5902 OP_PSR
, /* CPSR/SPSR mask for msr */
5903 OP_COND
, /* conditional code */
5904 OP_TB
, /* Table branch. */
5906 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5907 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5909 OP_RRnpc_I0
, /* ARM register or literal 0 */
5910 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5911 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5912 OP_RF_IF
, /* FPA register or immediate */
5913 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5914 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5916 /* Optional operands. */
5917 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5918 OP_oI31b
, /* 0 .. 31 */
5919 OP_oI32b
, /* 1 .. 32 */
5920 OP_oIffffb
, /* 0 .. 65535 */
5921 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5923 OP_oRR
, /* ARM register */
5924 OP_oRRnpc
, /* ARM register, not the PC */
5925 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5926 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5927 OP_oRND
, /* Optional Neon double precision register */
5928 OP_oRNQ
, /* Optional Neon quad precision register */
5929 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5930 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5931 OP_oSHll
, /* LSL immediate */
5932 OP_oSHar
, /* ASR immediate */
5933 OP_oSHllar
, /* LSL or ASR immediate */
5934 OP_oROR
, /* ROR 0/8/16/24 */
5935 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
5937 /* Some pre-defined mixed (ARM/THUMB) operands. */
5938 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5939 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5940 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5942 OP_FIRST_OPTIONAL
= OP_oI7b
5945 /* Generic instruction operand parser. This does no encoding and no
5946 semantic validation; it merely squirrels values away in the inst
5947 structure. Returns SUCCESS or FAIL depending on whether the
5948 specified grammar matched. */
5950 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5952 unsigned const int *upat
= pattern
;
5953 char *backtrack_pos
= 0;
5954 const char *backtrack_error
= 0;
5955 int i
, val
, backtrack_index
= 0;
5956 enum arm_reg_type rtype
;
5957 parse_operand_result result
;
5958 unsigned int op_parse_code
;
5960 #define po_char_or_fail(chr) \
5963 if (skip_past_char (&str, chr) == FAIL) \
5968 #define po_reg_or_fail(regtype) \
5971 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5972 & inst.operands[i].vectype); \
5975 first_error (_(reg_expected_msgs[regtype])); \
5978 inst.operands[i].reg = val; \
5979 inst.operands[i].isreg = 1; \
5980 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5981 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5982 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5983 || rtype == REG_TYPE_VFD \
5984 || rtype == REG_TYPE_NQ); \
5988 #define po_reg_or_goto(regtype, label) \
5991 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5992 & inst.operands[i].vectype); \
5996 inst.operands[i].reg = val; \
5997 inst.operands[i].isreg = 1; \
5998 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5999 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6000 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6001 || rtype == REG_TYPE_VFD \
6002 || rtype == REG_TYPE_NQ); \
6006 #define po_imm_or_fail(min, max, popt) \
6009 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6011 inst.operands[i].imm = val; \
6015 #define po_scalar_or_goto(elsz, label) \
6018 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6021 inst.operands[i].reg = val; \
6022 inst.operands[i].isscalar = 1; \
6026 #define po_misc_or_fail(expr) \
6034 #define po_misc_or_fail_no_backtrack(expr) \
6038 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6039 backtrack_pos = 0; \
6040 if (result != PARSE_OPERAND_SUCCESS) \
6045 #define po_barrier_or_imm(str) \
6048 val = parse_barrier (&str); \
6051 if (ISALPHA (*str)) \
6058 if ((inst.instruction & 0xf0) == 0x60 \
6061 /* ISB can only take SY as an option. */ \
6062 inst.error = _("invalid barrier type"); \
6069 skip_whitespace (str
);
6071 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6073 op_parse_code
= upat
[i
];
6074 if (op_parse_code
>= 1<<16)
6075 op_parse_code
= thumb
? (op_parse_code
>> 16)
6076 : (op_parse_code
& ((1<<16)-1));
6078 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6080 /* Remember where we are in case we need to backtrack. */
6081 gas_assert (!backtrack_pos
);
6082 backtrack_pos
= str
;
6083 backtrack_error
= inst
.error
;
6084 backtrack_index
= i
;
6087 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6088 po_char_or_fail (',');
6090 switch (op_parse_code
)
6098 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6099 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6100 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6101 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6102 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6103 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6105 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6107 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6109 /* Also accept generic coprocessor regs for unknown registers. */
6111 po_reg_or_fail (REG_TYPE_CN
);
6113 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6114 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6115 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6116 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6117 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6118 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6119 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6120 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6121 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6122 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6124 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6126 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6127 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6129 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6131 /* Neon scalar. Using an element size of 8 means that some invalid
6132 scalars are accepted here, so deal with those in later code. */
6133 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6137 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6140 po_imm_or_fail (0, 0, TRUE
);
6145 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6150 po_scalar_or_goto (8, try_rr
);
6153 po_reg_or_fail (REG_TYPE_RN
);
6159 po_scalar_or_goto (8, try_nsdq
);
6162 po_reg_or_fail (REG_TYPE_NSDQ
);
6168 po_scalar_or_goto (8, try_ndq
);
6171 po_reg_or_fail (REG_TYPE_NDQ
);
6177 po_scalar_or_goto (8, try_vfd
);
6180 po_reg_or_fail (REG_TYPE_VFD
);
6185 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6186 not careful then bad things might happen. */
6187 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6192 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6195 /* There's a possibility of getting a 64-bit immediate here, so
6196 we need special handling. */
6197 if (parse_big_immediate (&str
, i
) == FAIL
)
6199 inst
.error
= _("immediate value is out of range");
6207 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6210 po_imm_or_fail (0, 63, TRUE
);
6215 po_char_or_fail ('[');
6216 po_reg_or_fail (REG_TYPE_RN
);
6217 po_char_or_fail (']');
6223 po_reg_or_fail (REG_TYPE_RN
);
6224 if (skip_past_char (&str
, '!') == SUCCESS
)
6225 inst
.operands
[i
].writeback
= 1;
6229 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6230 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6231 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6232 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6233 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6234 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6235 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6236 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6237 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6238 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6239 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6240 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6242 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6244 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6245 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6247 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6248 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6249 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6251 /* Immediate variants */
6253 po_char_or_fail ('{');
6254 po_imm_or_fail (0, 255, TRUE
);
6255 po_char_or_fail ('}');
6259 /* The expression parser chokes on a trailing !, so we have
6260 to find it first and zap it. */
6263 while (*s
&& *s
!= ',')
6268 inst
.operands
[i
].writeback
= 1;
6270 po_imm_or_fail (0, 31, TRUE
);
6278 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6283 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6288 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6290 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6292 val
= parse_reloc (&str
);
6295 inst
.error
= _("unrecognized relocation suffix");
6298 else if (val
!= BFD_RELOC_UNUSED
)
6300 inst
.operands
[i
].imm
= val
;
6301 inst
.operands
[i
].hasreloc
= 1;
6306 /* Operand for MOVW or MOVT. */
6308 po_misc_or_fail (parse_half (&str
));
6311 /* Register or expression. */
6312 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6313 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6315 /* Register or immediate. */
6316 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6317 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6319 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6321 if (!is_immediate_prefix (*str
))
6324 val
= parse_fpa_immediate (&str
);
6327 /* FPA immediates are encoded as registers 8-15.
6328 parse_fpa_immediate has already applied the offset. */
6329 inst
.operands
[i
].reg
= val
;
6330 inst
.operands
[i
].isreg
= 1;
6333 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6334 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6336 /* Two kinds of register. */
6339 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6341 || (rege
->type
!= REG_TYPE_MMXWR
6342 && rege
->type
!= REG_TYPE_MMXWC
6343 && rege
->type
!= REG_TYPE_MMXWCG
))
6345 inst
.error
= _("iWMMXt data or control register expected");
6348 inst
.operands
[i
].reg
= rege
->number
;
6349 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6355 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6357 || (rege
->type
!= REG_TYPE_MMXWC
6358 && rege
->type
!= REG_TYPE_MMXWCG
))
6360 inst
.error
= _("iWMMXt control register expected");
6363 inst
.operands
[i
].reg
= rege
->number
;
6364 inst
.operands
[i
].isreg
= 1;
6369 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6370 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6371 case OP_oROR
: val
= parse_ror (&str
); break;
6372 case OP_PSR
: val
= parse_psr (&str
); break;
6373 case OP_COND
: val
= parse_cond (&str
); break;
6374 case OP_oBARRIER_I15
:
6375 po_barrier_or_imm (str
); break;
6377 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6382 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6383 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6386 val
= parse_psr (&str
);
6390 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6393 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6395 if (strncasecmp (str
, "APSR_", 5) == 0)
6402 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6403 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6404 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6405 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6406 default: found
= 16;
6410 inst
.operands
[i
].isvec
= 1;
6411 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6412 inst
.operands
[i
].reg
= REG_PC
;
6419 po_misc_or_fail (parse_tb (&str
));
6422 /* Register lists. */
6424 val
= parse_reg_list (&str
);
6427 inst
.operands
[1].writeback
= 1;
6433 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6437 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6441 /* Allow Q registers too. */
6442 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6447 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6449 inst
.operands
[i
].issingle
= 1;
6454 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6459 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6460 &inst
.operands
[i
].vectype
);
6463 /* Addressing modes */
6465 po_misc_or_fail (parse_address (&str
, i
));
6469 po_misc_or_fail_no_backtrack (
6470 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6474 po_misc_or_fail_no_backtrack (
6475 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6479 po_misc_or_fail_no_backtrack (
6480 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6484 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6488 po_misc_or_fail_no_backtrack (
6489 parse_shifter_operand_group_reloc (&str
, i
));
6493 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6497 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6501 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6505 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6508 /* Various value-based sanity checks and shared operations. We
6509 do not signal immediate failures for the register constraints;
6510 this allows a syntax error to take precedence. */
6511 switch (op_parse_code
)
6519 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6520 inst
.error
= BAD_PC
;
6525 if (inst
.operands
[i
].isreg
)
6527 if (inst
.operands
[i
].reg
== REG_PC
)
6528 inst
.error
= BAD_PC
;
6529 else if (inst
.operands
[i
].reg
== REG_SP
)
6530 inst
.error
= BAD_SP
;
6535 if (inst
.operands
[i
].isreg
6536 && inst
.operands
[i
].reg
== REG_PC
6537 && (inst
.operands
[i
].writeback
|| thumb
))
6538 inst
.error
= BAD_PC
;
6547 case OP_oBARRIER_I15
:
6556 inst
.operands
[i
].imm
= val
;
6563 /* If we get here, this operand was successfully parsed. */
6564 inst
.operands
[i
].present
= 1;
6568 inst
.error
= BAD_ARGS
;
6573 /* The parse routine should already have set inst.error, but set a
6574 default here just in case. */
6576 inst
.error
= _("syntax error");
6580 /* Do not backtrack over a trailing optional argument that
6581 absorbed some text. We will only fail again, with the
6582 'garbage following instruction' error message, which is
6583 probably less helpful than the current one. */
6584 if (backtrack_index
== i
&& backtrack_pos
!= str
6585 && upat
[i
+1] == OP_stop
)
6588 inst
.error
= _("syntax error");
6592 /* Try again, skipping the optional argument at backtrack_pos. */
6593 str
= backtrack_pos
;
6594 inst
.error
= backtrack_error
;
6595 inst
.operands
[backtrack_index
].present
= 0;
6596 i
= backtrack_index
;
6600 /* Check that we have parsed all the arguments. */
6601 if (*str
!= '\0' && !inst
.error
)
6602 inst
.error
= _("garbage following instruction");
6604 return inst
.error
? FAIL
: SUCCESS
;
6607 #undef po_char_or_fail
6608 #undef po_reg_or_fail
6609 #undef po_reg_or_goto
6610 #undef po_imm_or_fail
6611 #undef po_scalar_or_fail
6612 #undef po_barrier_or_imm
6614 /* Shorthand macro for instruction encoding functions issuing errors. */
6615 #define constraint(expr, err) \
6626 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6627 instructions are unpredictable if these registers are used. This
6628 is the BadReg predicate in ARM's Thumb-2 documentation. */
6629 #define reject_bad_reg(reg) \
6631 if (reg == REG_SP || reg == REG_PC) \
6633 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6638 /* If REG is R13 (the stack pointer), warn that its use is
6640 #define warn_deprecated_sp(reg) \
6642 if (warn_on_deprecated && reg == REG_SP) \
6643 as_warn (_("use of r13 is deprecated")); \
6646 /* Functions for operand encoding. ARM, then Thumb. */
6648 #define rotate_left(v, n) (v << n | v >> (32 - n))
6650 /* If VAL can be encoded in the immediate field of an ARM instruction,
6651 return the encoded form. Otherwise, return FAIL. */
6654 encode_arm_immediate (unsigned int val
)
6658 for (i
= 0; i
< 32; i
+= 2)
6659 if ((a
= rotate_left (val
, i
)) <= 0xff)
6660 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6665 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6666 return the encoded form. Otherwise, return FAIL. */
6668 encode_thumb32_immediate (unsigned int val
)
6675 for (i
= 1; i
<= 24; i
++)
6678 if ((val
& ~(0xff << i
)) == 0)
6679 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6683 if (val
== ((a
<< 16) | a
))
6685 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6689 if (val
== ((a
<< 16) | a
))
6690 return 0x200 | (a
>> 8);
6694 /* Encode a VFP SP or DP register number into inst.instruction. */
6697 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6699 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6702 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6705 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6708 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6713 first_error (_("D register out of range for selected VFP version"));
6721 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6725 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6729 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6733 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6737 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6741 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6749 /* Encode a <shift> in an ARM-format instruction. The immediate,
6750 if any, is handled by md_apply_fix. */
6752 encode_arm_shift (int i
)
6754 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6755 inst
.instruction
|= SHIFT_ROR
<< 5;
6758 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6759 if (inst
.operands
[i
].immisreg
)
6761 inst
.instruction
|= SHIFT_BY_REG
;
6762 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6765 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6770 encode_arm_shifter_operand (int i
)
6772 if (inst
.operands
[i
].isreg
)
6774 inst
.instruction
|= inst
.operands
[i
].reg
;
6775 encode_arm_shift (i
);
6778 inst
.instruction
|= INST_IMMEDIATE
;
6781 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6783 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6785 gas_assert (inst
.operands
[i
].isreg
);
6786 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6788 if (inst
.operands
[i
].preind
)
6792 inst
.error
= _("instruction does not accept preindexed addressing");
6795 inst
.instruction
|= PRE_INDEX
;
6796 if (inst
.operands
[i
].writeback
)
6797 inst
.instruction
|= WRITE_BACK
;
6800 else if (inst
.operands
[i
].postind
)
6802 gas_assert (inst
.operands
[i
].writeback
);
6804 inst
.instruction
|= WRITE_BACK
;
6806 else /* unindexed - only for coprocessor */
6808 inst
.error
= _("instruction does not accept unindexed addressing");
6812 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6813 && (((inst
.instruction
& 0x000f0000) >> 16)
6814 == ((inst
.instruction
& 0x0000f000) >> 12)))
6815 as_warn ((inst
.instruction
& LOAD_BIT
)
6816 ? _("destination register same as write-back base")
6817 : _("source register same as write-back base"));
6820 /* inst.operands[i] was set up by parse_address. Encode it into an
6821 ARM-format mode 2 load or store instruction. If is_t is true,
6822 reject forms that cannot be used with a T instruction (i.e. not
6825 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6827 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6829 encode_arm_addr_mode_common (i
, is_t
);
6831 if (inst
.operands
[i
].immisreg
)
6833 constraint ((inst
.operands
[i
].imm
== REG_PC
6834 || (is_pc
&& inst
.operands
[i
].writeback
)),
6836 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6837 inst
.instruction
|= inst
.operands
[i
].imm
;
6838 if (!inst
.operands
[i
].negative
)
6839 inst
.instruction
|= INDEX_UP
;
6840 if (inst
.operands
[i
].shifted
)
6842 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6843 inst
.instruction
|= SHIFT_ROR
<< 5;
6846 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6847 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6851 else /* immediate offset in inst.reloc */
6853 if (is_pc
&& !inst
.reloc
.pc_rel
)
6855 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6857 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
6858 cannot use PC in addressing.
6859 PC cannot be used in writeback addressing, either. */
6860 constraint ((is_t
|| inst
.operands
[i
].writeback
),
6863 /* Use of PC in str is deprecated for ARMv7. */
6864 if (warn_on_deprecated
6866 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
6867 as_warn (_("use of PC in this instruction is deprecated"));
6870 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6871 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6875 /* inst.operands[i] was set up by parse_address. Encode it into an
6876 ARM-format mode 3 load or store instruction. Reject forms that
6877 cannot be used with such instructions. If is_t is true, reject
6878 forms that cannot be used with a T instruction (i.e. not
6881 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6883 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6885 inst
.error
= _("instruction does not accept scaled register index");
6889 encode_arm_addr_mode_common (i
, is_t
);
6891 if (inst
.operands
[i
].immisreg
)
6893 constraint ((inst
.operands
[i
].imm
== REG_PC
6894 || inst
.operands
[i
].reg
== REG_PC
),
6896 inst
.instruction
|= inst
.operands
[i
].imm
;
6897 if (!inst
.operands
[i
].negative
)
6898 inst
.instruction
|= INDEX_UP
;
6900 else /* immediate offset in inst.reloc */
6902 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6903 && inst
.operands
[i
].writeback
),
6905 inst
.instruction
|= HWOFFSET_IMM
;
6906 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6907 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6911 /* inst.operands[i] was set up by parse_address. Encode it into an
6912 ARM-format instruction. Reject all forms which cannot be encoded
6913 into a coprocessor load/store instruction. If wb_ok is false,
6914 reject use of writeback; if unind_ok is false, reject use of
6915 unindexed addressing. If reloc_override is not 0, use it instead
6916 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6917 (in which case it is preserved). */
6920 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6922 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6924 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6926 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6928 gas_assert (!inst
.operands
[i
].writeback
);
6931 inst
.error
= _("instruction does not support unindexed addressing");
6934 inst
.instruction
|= inst
.operands
[i
].imm
;
6935 inst
.instruction
|= INDEX_UP
;
6939 if (inst
.operands
[i
].preind
)
6940 inst
.instruction
|= PRE_INDEX
;
6942 if (inst
.operands
[i
].writeback
)
6944 if (inst
.operands
[i
].reg
== REG_PC
)
6946 inst
.error
= _("pc may not be used with write-back");
6951 inst
.error
= _("instruction does not support writeback");
6954 inst
.instruction
|= WRITE_BACK
;
6958 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6959 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6960 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6961 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6964 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6966 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6972 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6973 Determine whether it can be performed with a move instruction; if
6974 it can, convert inst.instruction to that move instruction and
6975 return TRUE; if it can't, convert inst.instruction to a literal-pool
6976 load and return FALSE. If this is not a valid thing to do in the
6977 current context, set inst.error and return TRUE.
6979 inst.operands[i] describes the destination register. */
6982 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6987 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6991 if ((inst
.instruction
& tbit
) == 0)
6993 inst
.error
= _("invalid pseudo operation");
6996 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6998 inst
.error
= _("constant expression expected");
7001 if (inst
.reloc
.exp
.X_op
== O_constant
)
7005 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7007 /* This can be done with a mov(1) instruction. */
7008 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7009 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7015 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7018 /* This can be done with a mov instruction. */
7019 inst
.instruction
&= LITERAL_MASK
;
7020 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7021 inst
.instruction
|= value
& 0xfff;
7025 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7028 /* This can be done with a mvn instruction. */
7029 inst
.instruction
&= LITERAL_MASK
;
7030 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7031 inst
.instruction
|= value
& 0xfff;
7037 if (add_to_lit_pool () == FAIL
)
7039 inst
.error
= _("literal pool insertion failed");
7042 inst
.operands
[1].reg
= REG_PC
;
7043 inst
.operands
[1].isreg
= 1;
7044 inst
.operands
[1].preind
= 1;
7045 inst
.reloc
.pc_rel
= 1;
7046 inst
.reloc
.type
= (thumb_p
7047 ? BFD_RELOC_ARM_THUMB_OFFSET
7049 ? BFD_RELOC_ARM_HWLITERAL
7050 : BFD_RELOC_ARM_LITERAL
));
7054 /* Functions for instruction encoding, sorted by sub-architecture.
7055 First some generics; their names are taken from the conventional
7056 bit positions for register arguments in ARM format instructions. */
7066 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7072 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7073 inst
.instruction
|= inst
.operands
[1].reg
;
7079 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7080 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7086 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7087 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7093 unsigned Rn
= inst
.operands
[2].reg
;
7094 /* Enforce restrictions on SWP instruction. */
7095 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7097 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7098 _("Rn must not overlap other operands"));
7100 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7101 if (warn_on_deprecated
7102 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7103 as_warn (_("swp{b} use is deprecated for this architecture"));
7106 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7107 inst
.instruction
|= inst
.operands
[1].reg
;
7108 inst
.instruction
|= Rn
<< 16;
7114 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7115 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7116 inst
.instruction
|= inst
.operands
[2].reg
;
7122 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7123 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7124 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7125 || inst
.reloc
.exp
.X_add_number
!= 0),
7127 inst
.instruction
|= inst
.operands
[0].reg
;
7128 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7129 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7135 inst
.instruction
|= inst
.operands
[0].imm
;
7141 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7142 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7145 /* ARM instructions, in alphabetical order by function name (except
7146 that wrapper functions appear immediately after the function they
7149 /* This is a pseudo-op of the form "adr rd, label" to be converted
7150 into a relative address of the form "add rd, pc, #label-.-8". */
7155 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7157 /* Frag hacking will turn this into a sub instruction if the offset turns
7158 out to be negative. */
7159 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7160 inst
.reloc
.pc_rel
= 1;
7161 inst
.reloc
.exp
.X_add_number
-= 8;
7164 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7165 into a relative address of the form:
7166 add rd, pc, #low(label-.-8)"
7167 add rd, rd, #high(label-.-8)" */
7172 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7174 /* Frag hacking will turn this into a sub instruction if the offset turns
7175 out to be negative. */
7176 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7177 inst
.reloc
.pc_rel
= 1;
7178 inst
.size
= INSN_SIZE
* 2;
7179 inst
.reloc
.exp
.X_add_number
-= 8;
7185 if (!inst
.operands
[1].present
)
7186 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7187 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7188 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7189 encode_arm_shifter_operand (2);
7195 if (inst
.operands
[0].present
)
7197 constraint ((inst
.instruction
& 0xf0) != 0x40
7198 && inst
.operands
[0].imm
> 0xf
7199 && inst
.operands
[0].imm
< 0x0,
7200 _("bad barrier type"));
7201 inst
.instruction
|= inst
.operands
[0].imm
;
7204 inst
.instruction
|= 0xf;
7210 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7211 constraint (msb
> 32, _("bit-field extends past end of register"));
7212 /* The instruction encoding stores the LSB and MSB,
7213 not the LSB and width. */
7214 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7215 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7216 inst
.instruction
|= (msb
- 1) << 16;
7224 /* #0 in second position is alternative syntax for bfc, which is
7225 the same instruction but with REG_PC in the Rm field. */
7226 if (!inst
.operands
[1].isreg
)
7227 inst
.operands
[1].reg
= REG_PC
;
7229 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7230 constraint (msb
> 32, _("bit-field extends past end of register"));
7231 /* The instruction encoding stores the LSB and MSB,
7232 not the LSB and width. */
7233 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7234 inst
.instruction
|= inst
.operands
[1].reg
;
7235 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7236 inst
.instruction
|= (msb
- 1) << 16;
7242 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7243 _("bit-field extends past end of register"));
7244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7245 inst
.instruction
|= inst
.operands
[1].reg
;
7246 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7247 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7250 /* ARM V5 breakpoint instruction (argument parse)
7251 BKPT <16 bit unsigned immediate>
7252 Instruction is not conditional.
7253 The bit pattern given in insns[] has the COND_ALWAYS condition,
7254 and it is an error if the caller tried to override that. */
7259 /* Top 12 of 16 bits to bits 19:8. */
7260 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7262 /* Bottom 4 of 16 bits to bits 3:0. */
7263 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7267 encode_branch (int default_reloc
)
7269 if (inst
.operands
[0].hasreloc
)
7271 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7272 _("the only suffix valid here is '(plt)'"));
7273 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7277 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7279 inst
.reloc
.pc_rel
= 1;
7286 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7287 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7290 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7297 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7299 if (inst
.cond
== COND_ALWAYS
)
7300 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7302 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7306 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7309 /* ARM V5 branch-link-exchange instruction (argument parse)
7310 BLX <target_addr> ie BLX(1)
7311 BLX{<condition>} <Rm> ie BLX(2)
7312 Unfortunately, there are two different opcodes for this mnemonic.
7313 So, the insns[].value is not used, and the code here zaps values
7314 into inst.instruction.
7315 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7320 if (inst
.operands
[0].isreg
)
7322 /* Arg is a register; the opcode provided by insns[] is correct.
7323 It is not illegal to do "blx pc", just useless. */
7324 if (inst
.operands
[0].reg
== REG_PC
)
7325 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7327 inst
.instruction
|= inst
.operands
[0].reg
;
7331 /* Arg is an address; this instruction cannot be executed
7332 conditionally, and the opcode must be adjusted.
7333 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7334 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7335 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7336 inst
.instruction
= 0xfa000000;
7337 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7344 bfd_boolean want_reloc
;
7346 if (inst
.operands
[0].reg
== REG_PC
)
7347 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7349 inst
.instruction
|= inst
.operands
[0].reg
;
7350 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7351 it is for ARMv4t or earlier. */
7352 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7353 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7357 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7362 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7366 /* ARM v5TEJ. Jump to Jazelle code. */
7371 if (inst
.operands
[0].reg
== REG_PC
)
7372 as_tsktsk (_("use of r15 in bxj is not really useful"));
7374 inst
.instruction
|= inst
.operands
[0].reg
;
7377 /* Co-processor data operation:
7378 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7379 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7383 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7384 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7385 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7386 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7387 inst
.instruction
|= inst
.operands
[4].reg
;
7388 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7394 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7395 encode_arm_shifter_operand (1);
7398 /* Transfer between coprocessor and ARM registers.
7399 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7404 No special properties. */
7411 Rd
= inst
.operands
[2].reg
;
7414 if (inst
.instruction
== 0xee000010
7415 || inst
.instruction
== 0xfe000010)
7417 reject_bad_reg (Rd
);
7420 constraint (Rd
== REG_SP
, BAD_SP
);
7425 if (inst
.instruction
== 0xe000010)
7426 constraint (Rd
== REG_PC
, BAD_PC
);
7430 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7431 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7432 inst
.instruction
|= Rd
<< 12;
7433 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7434 inst
.instruction
|= inst
.operands
[4].reg
;
7435 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7438 /* Transfer between coprocessor register and pair of ARM registers.
7439 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7444 Two XScale instructions are special cases of these:
7446 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7447 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7449 Result unpredictable if Rd or Rn is R15. */
7456 Rd
= inst
.operands
[2].reg
;
7457 Rn
= inst
.operands
[3].reg
;
7461 reject_bad_reg (Rd
);
7462 reject_bad_reg (Rn
);
7466 constraint (Rd
== REG_PC
, BAD_PC
);
7467 constraint (Rn
== REG_PC
, BAD_PC
);
7470 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7471 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7472 inst
.instruction
|= Rd
<< 12;
7473 inst
.instruction
|= Rn
<< 16;
7474 inst
.instruction
|= inst
.operands
[4].reg
;
7480 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7481 if (inst
.operands
[1].present
)
7483 inst
.instruction
|= CPSI_MMOD
;
7484 inst
.instruction
|= inst
.operands
[1].imm
;
7491 inst
.instruction
|= inst
.operands
[0].imm
;
7497 /* There is no IT instruction in ARM mode. We
7498 process it to do the validation as if in
7499 thumb mode, just in case the code gets
7500 assembled for thumb using the unified syntax. */
7505 set_it_insn_type (IT_INSN
);
7506 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7507 now_it
.cc
= inst
.operands
[0].imm
;
7514 int base_reg
= inst
.operands
[0].reg
;
7515 int range
= inst
.operands
[1].imm
;
7517 inst
.instruction
|= base_reg
<< 16;
7518 inst
.instruction
|= range
;
7520 if (inst
.operands
[1].writeback
)
7521 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7523 if (inst
.operands
[0].writeback
)
7525 inst
.instruction
|= WRITE_BACK
;
7526 /* Check for unpredictable uses of writeback. */
7527 if (inst
.instruction
& LOAD_BIT
)
7529 /* Not allowed in LDM type 2. */
7530 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7531 && ((range
& (1 << REG_PC
)) == 0))
7532 as_warn (_("writeback of base register is UNPREDICTABLE"));
7533 /* Only allowed if base reg not in list for other types. */
7534 else if (range
& (1 << base_reg
))
7535 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7539 /* Not allowed for type 2. */
7540 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7541 as_warn (_("writeback of base register is UNPREDICTABLE"));
7542 /* Only allowed if base reg not in list, or first in list. */
7543 else if ((range
& (1 << base_reg
))
7544 && (range
& ((1 << base_reg
) - 1)))
7545 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7550 /* ARMv5TE load-consecutive (argument parse)
7559 constraint (inst
.operands
[0].reg
% 2 != 0,
7560 _("first destination register must be even"));
7561 constraint (inst
.operands
[1].present
7562 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7563 _("can only load two consecutive registers"));
7564 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7565 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7567 if (!inst
.operands
[1].present
)
7568 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7570 if (inst
.instruction
& LOAD_BIT
)
7572 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7573 register and the first register written; we have to diagnose
7574 overlap between the base and the second register written here. */
7576 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7577 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7578 as_warn (_("base register written back, and overlaps "
7579 "second destination register"));
7581 /* For an index-register load, the index register must not overlap the
7582 destination (even if not write-back). */
7583 else if (inst
.operands
[2].immisreg
7584 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7585 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7586 as_warn (_("index register overlaps destination register"));
7589 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7590 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7596 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7597 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7598 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7599 || inst
.operands
[1].negative
7600 /* This can arise if the programmer has written
7602 or if they have mistakenly used a register name as the last
7605 It is very difficult to distinguish between these two cases
7606 because "rX" might actually be a label. ie the register
7607 name has been occluded by a symbol of the same name. So we
7608 just generate a general 'bad addressing mode' type error
7609 message and leave it up to the programmer to discover the
7610 true cause and fix their mistake. */
7611 || (inst
.operands
[1].reg
== REG_PC
),
7614 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7615 || inst
.reloc
.exp
.X_add_number
!= 0,
7616 _("offset must be zero in ARM encoding"));
7618 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7620 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7621 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7622 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7628 constraint (inst
.operands
[0].reg
% 2 != 0,
7629 _("even register required"));
7630 constraint (inst
.operands
[1].present
7631 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7632 _("can only load two consecutive registers"));
7633 /* If op 1 were present and equal to PC, this function wouldn't
7634 have been called in the first place. */
7635 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7637 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7638 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7644 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7645 if (!inst
.operands
[1].isreg
)
7646 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7648 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7654 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7656 if (inst
.operands
[1].preind
)
7658 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7659 || inst
.reloc
.exp
.X_add_number
!= 0,
7660 _("this instruction requires a post-indexed address"));
7662 inst
.operands
[1].preind
= 0;
7663 inst
.operands
[1].postind
= 1;
7664 inst
.operands
[1].writeback
= 1;
7666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7667 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7670 /* Halfword and signed-byte load/store operations. */
7675 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7677 if (!inst
.operands
[1].isreg
)
7678 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7680 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7686 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7688 if (inst
.operands
[1].preind
)
7690 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7691 || inst
.reloc
.exp
.X_add_number
!= 0,
7692 _("this instruction requires a post-indexed address"));
7694 inst
.operands
[1].preind
= 0;
7695 inst
.operands
[1].postind
= 1;
7696 inst
.operands
[1].writeback
= 1;
7698 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7699 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7702 /* Co-processor register load/store.
7703 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7707 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7708 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7709 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7715 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7716 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7717 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7718 && !(inst
.instruction
& 0x00400000))
7719 as_tsktsk (_("Rd and Rm should be different in mla"));
7721 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7722 inst
.instruction
|= inst
.operands
[1].reg
;
7723 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7724 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7730 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7731 encode_arm_shifter_operand (1);
7734 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7741 top
= (inst
.instruction
& 0x00400000) != 0;
7742 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7743 _(":lower16: not allowed this instruction"));
7744 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7745 _(":upper16: not allowed instruction"));
7746 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7747 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7749 imm
= inst
.reloc
.exp
.X_add_number
;
7750 /* The value is in two pieces: 0:11, 16:19. */
7751 inst
.instruction
|= (imm
& 0x00000fff);
7752 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7756 static void do_vfp_nsyn_opcode (const char *);
7759 do_vfp_nsyn_mrs (void)
7761 if (inst
.operands
[0].isvec
)
7763 if (inst
.operands
[1].reg
!= 1)
7764 first_error (_("operand 1 must be FPSCR"));
7765 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7766 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7767 do_vfp_nsyn_opcode ("fmstat");
7769 else if (inst
.operands
[1].isvec
)
7770 do_vfp_nsyn_opcode ("fmrx");
7778 do_vfp_nsyn_msr (void)
7780 if (inst
.operands
[0].isvec
)
7781 do_vfp_nsyn_opcode ("fmxr");
7791 unsigned Rt
= inst
.operands
[0].reg
;
7793 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7795 inst
.error
= BAD_SP
;
7799 /* APSR_ sets isvec. All other refs to PC are illegal. */
7800 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7802 inst
.error
= BAD_PC
;
7806 if (inst
.operands
[1].reg
!= 1)
7807 first_error (_("operand 1 must be FPSCR"));
7809 inst
.instruction
|= (Rt
<< 12);
7815 unsigned Rt
= inst
.operands
[1].reg
;
7818 reject_bad_reg (Rt
);
7819 else if (Rt
== REG_PC
)
7821 inst
.error
= BAD_PC
;
7825 if (inst
.operands
[0].reg
!= 1)
7826 first_error (_("operand 0 must be FPSCR"));
7828 inst
.instruction
|= (Rt
<< 12);
7834 if (do_vfp_nsyn_mrs () == SUCCESS
)
7837 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7838 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7840 _("'CPSR' or 'SPSR' expected"));
7841 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7842 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7843 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7846 /* Two possible forms:
7847 "{C|S}PSR_<field>, Rm",
7848 "{C|S}PSR_f, #expression". */
7853 if (do_vfp_nsyn_msr () == SUCCESS
)
7856 inst
.instruction
|= inst
.operands
[0].imm
;
7857 if (inst
.operands
[1].isreg
)
7858 inst
.instruction
|= inst
.operands
[1].reg
;
7861 inst
.instruction
|= INST_IMMEDIATE
;
7862 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7863 inst
.reloc
.pc_rel
= 0;
7870 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7872 if (!inst
.operands
[2].present
)
7873 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7874 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7875 inst
.instruction
|= inst
.operands
[1].reg
;
7876 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7878 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7879 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7880 as_tsktsk (_("Rd and Rm should be different in mul"));
7883 /* Long Multiply Parser
7884 UMULL RdLo, RdHi, Rm, Rs
7885 SMULL RdLo, RdHi, Rm, Rs
7886 UMLAL RdLo, RdHi, Rm, Rs
7887 SMLAL RdLo, RdHi, Rm, Rs. */
7892 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7893 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7894 inst
.instruction
|= inst
.operands
[2].reg
;
7895 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7897 /* rdhi and rdlo must be different. */
7898 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7899 as_tsktsk (_("rdhi and rdlo must be different"));
7901 /* rdhi, rdlo and rm must all be different before armv6. */
7902 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7903 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7904 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7905 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7911 if (inst
.operands
[0].present
7912 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7914 /* Architectural NOP hints are CPSR sets with no bits selected. */
7915 inst
.instruction
&= 0xf0000000;
7916 inst
.instruction
|= 0x0320f000;
7917 if (inst
.operands
[0].present
)
7918 inst
.instruction
|= inst
.operands
[0].imm
;
7922 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7923 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7924 Condition defaults to COND_ALWAYS.
7925 Error if Rd, Rn or Rm are R15. */
7930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7931 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7932 inst
.instruction
|= inst
.operands
[2].reg
;
7933 if (inst
.operands
[3].present
)
7934 encode_arm_shift (3);
7937 /* ARM V6 PKHTB (Argument Parse). */
7942 if (!inst
.operands
[3].present
)
7944 /* If the shift specifier is omitted, turn the instruction
7945 into pkhbt rd, rm, rn. */
7946 inst
.instruction
&= 0xfff00010;
7947 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7948 inst
.instruction
|= inst
.operands
[1].reg
;
7949 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7953 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7954 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7955 inst
.instruction
|= inst
.operands
[2].reg
;
7956 encode_arm_shift (3);
7960 /* ARMv5TE: Preload-Cache
7961 MP Extensions: Preload for write
7965 Syntactically, like LDR with B=1, W=0, L=1. */
7970 constraint (!inst
.operands
[0].isreg
,
7971 _("'[' expected after PLD mnemonic"));
7972 constraint (inst
.operands
[0].postind
,
7973 _("post-indexed expression used in preload instruction"));
7974 constraint (inst
.operands
[0].writeback
,
7975 _("writeback used in preload instruction"));
7976 constraint (!inst
.operands
[0].preind
,
7977 _("unindexed addressing used in preload instruction"));
7978 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7981 /* ARMv7: PLI <addr_mode> */
7985 constraint (!inst
.operands
[0].isreg
,
7986 _("'[' expected after PLI mnemonic"));
7987 constraint (inst
.operands
[0].postind
,
7988 _("post-indexed expression used in preload instruction"));
7989 constraint (inst
.operands
[0].writeback
,
7990 _("writeback used in preload instruction"));
7991 constraint (!inst
.operands
[0].preind
,
7992 _("unindexed addressing used in preload instruction"));
7993 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7994 inst
.instruction
&= ~PRE_INDEX
;
8000 inst
.operands
[1] = inst
.operands
[0];
8001 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8002 inst
.operands
[0].isreg
= 1;
8003 inst
.operands
[0].writeback
= 1;
8004 inst
.operands
[0].reg
= REG_SP
;
8008 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8009 word at the specified address and the following word
8011 Unconditionally executed.
8012 Error if Rn is R15. */
8017 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8018 if (inst
.operands
[0].writeback
)
8019 inst
.instruction
|= WRITE_BACK
;
8022 /* ARM V6 ssat (argument parse). */
8027 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8028 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8029 inst
.instruction
|= inst
.operands
[2].reg
;
8031 if (inst
.operands
[3].present
)
8032 encode_arm_shift (3);
8035 /* ARM V6 usat (argument parse). */
8040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8041 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8042 inst
.instruction
|= inst
.operands
[2].reg
;
8044 if (inst
.operands
[3].present
)
8045 encode_arm_shift (3);
8048 /* ARM V6 ssat16 (argument parse). */
8053 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8054 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8055 inst
.instruction
|= inst
.operands
[2].reg
;
8061 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8062 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8063 inst
.instruction
|= inst
.operands
[2].reg
;
8066 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8067 preserving the other bits.
8069 setend <endian_specifier>, where <endian_specifier> is either
8075 if (inst
.operands
[0].imm
)
8076 inst
.instruction
|= 0x200;
8082 unsigned int Rm
= (inst
.operands
[1].present
8083 ? inst
.operands
[1].reg
8084 : inst
.operands
[0].reg
);
8086 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8087 inst
.instruction
|= Rm
;
8088 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8090 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8091 inst
.instruction
|= SHIFT_BY_REG
;
8094 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8100 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8101 inst
.reloc
.pc_rel
= 0;
8107 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8108 inst
.reloc
.pc_rel
= 0;
8111 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8112 SMLAxy{cond} Rd,Rm,Rs,Rn
8113 SMLAWy{cond} Rd,Rm,Rs,Rn
8114 Error if any register is R15. */
8119 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8120 inst
.instruction
|= inst
.operands
[1].reg
;
8121 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8122 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8125 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8126 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8127 Error if any register is R15.
8128 Warning if Rdlo == Rdhi. */
8133 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8134 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8135 inst
.instruction
|= inst
.operands
[2].reg
;
8136 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8138 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8139 as_tsktsk (_("rdhi and rdlo must be different"));
8142 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8143 SMULxy{cond} Rd,Rm,Rs
8144 Error if any register is R15. */
8149 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8150 inst
.instruction
|= inst
.operands
[1].reg
;
8151 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8154 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8155 the same for both ARM and Thumb-2. */
8162 if (inst
.operands
[0].present
)
8164 reg
= inst
.operands
[0].reg
;
8165 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8170 inst
.instruction
|= reg
<< 16;
8171 inst
.instruction
|= inst
.operands
[1].imm
;
8172 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8173 inst
.instruction
|= WRITE_BACK
;
8176 /* ARM V6 strex (argument parse). */
8181 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8182 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8183 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8184 || inst
.operands
[2].negative
8185 /* See comment in do_ldrex(). */
8186 || (inst
.operands
[2].reg
== REG_PC
),
8189 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8190 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8192 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8193 || inst
.reloc
.exp
.X_add_number
!= 0,
8194 _("offset must be zero in ARM encoding"));
8196 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8197 inst
.instruction
|= inst
.operands
[1].reg
;
8198 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8199 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8205 constraint (inst
.operands
[1].reg
% 2 != 0,
8206 _("even register required"));
8207 constraint (inst
.operands
[2].present
8208 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8209 _("can only store two consecutive registers"));
8210 /* If op 2 were present and equal to PC, this function wouldn't
8211 have been called in the first place. */
8212 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8214 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8215 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8216 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8220 inst
.instruction
|= inst
.operands
[1].reg
;
8221 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8224 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8225 extends it to 32-bits, and adds the result to a value in another
8226 register. You can specify a rotation by 0, 8, 16, or 24 bits
8227 before extracting the 16-bit value.
8228 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8229 Condition defaults to COND_ALWAYS.
8230 Error if any register uses R15. */
8235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8236 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8237 inst
.instruction
|= inst
.operands
[2].reg
;
8238 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8243 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8244 Condition defaults to COND_ALWAYS.
8245 Error if any register uses R15. */
8250 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8251 inst
.instruction
|= inst
.operands
[1].reg
;
8252 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8255 /* VFP instructions. In a logical order: SP variant first, monad
8256 before dyad, arithmetic then move then load/store. */
8259 do_vfp_sp_monadic (void)
8261 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8262 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8266 do_vfp_sp_dyadic (void)
8268 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8269 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8270 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8274 do_vfp_sp_compare_z (void)
8276 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8280 do_vfp_dp_sp_cvt (void)
8282 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8283 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8287 do_vfp_sp_dp_cvt (void)
8289 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8290 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8294 do_vfp_reg_from_sp (void)
8296 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8297 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8301 do_vfp_reg2_from_sp2 (void)
8303 constraint (inst
.operands
[2].imm
!= 2,
8304 _("only two consecutive VFP SP registers allowed here"));
8305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8306 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8307 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8311 do_vfp_sp_from_reg (void)
8313 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8314 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8318 do_vfp_sp2_from_reg2 (void)
8320 constraint (inst
.operands
[0].imm
!= 2,
8321 _("only two consecutive VFP SP registers allowed here"));
8322 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8323 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8324 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8328 do_vfp_sp_ldst (void)
8330 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8331 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8335 do_vfp_dp_ldst (void)
8337 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8338 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8343 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8345 if (inst
.operands
[0].writeback
)
8346 inst
.instruction
|= WRITE_BACK
;
8348 constraint (ldstm_type
!= VFP_LDSTMIA
,
8349 _("this addressing mode requires base-register writeback"));
8350 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8351 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8352 inst
.instruction
|= inst
.operands
[1].imm
;
8356 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8360 if (inst
.operands
[0].writeback
)
8361 inst
.instruction
|= WRITE_BACK
;
8363 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8364 _("this addressing mode requires base-register writeback"));
8366 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8367 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8369 count
= inst
.operands
[1].imm
<< 1;
8370 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8373 inst
.instruction
|= count
;
8377 do_vfp_sp_ldstmia (void)
8379 vfp_sp_ldstm (VFP_LDSTMIA
);
8383 do_vfp_sp_ldstmdb (void)
8385 vfp_sp_ldstm (VFP_LDSTMDB
);
8389 do_vfp_dp_ldstmia (void)
8391 vfp_dp_ldstm (VFP_LDSTMIA
);
8395 do_vfp_dp_ldstmdb (void)
8397 vfp_dp_ldstm (VFP_LDSTMDB
);
8401 do_vfp_xp_ldstmia (void)
8403 vfp_dp_ldstm (VFP_LDSTMIAX
);
8407 do_vfp_xp_ldstmdb (void)
8409 vfp_dp_ldstm (VFP_LDSTMDBX
);
8413 do_vfp_dp_rd_rm (void)
8415 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8416 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8420 do_vfp_dp_rn_rd (void)
8422 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8423 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8427 do_vfp_dp_rd_rn (void)
8429 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8430 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8434 do_vfp_dp_rd_rn_rm (void)
8436 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8437 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8438 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8444 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8448 do_vfp_dp_rm_rd_rn (void)
8450 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8451 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8452 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8455 /* VFPv3 instructions. */
8457 do_vfp_sp_const (void)
8459 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8460 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8461 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8465 do_vfp_dp_const (void)
8467 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8468 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8469 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8473 vfp_conv (int srcsize
)
8475 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8476 inst
.instruction
|= (immbits
& 1) << 5;
8477 inst
.instruction
|= (immbits
>> 1);
8481 do_vfp_sp_conv_16 (void)
8483 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8488 do_vfp_dp_conv_16 (void)
8490 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8495 do_vfp_sp_conv_32 (void)
8497 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8502 do_vfp_dp_conv_32 (void)
8504 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8508 /* FPA instructions. Also in a logical order. */
8513 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8514 inst
.instruction
|= inst
.operands
[1].reg
;
8518 do_fpa_ldmstm (void)
8520 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8521 switch (inst
.operands
[1].imm
)
8523 case 1: inst
.instruction
|= CP_T_X
; break;
8524 case 2: inst
.instruction
|= CP_T_Y
; break;
8525 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8530 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8532 /* The instruction specified "ea" or "fd", so we can only accept
8533 [Rn]{!}. The instruction does not really support stacking or
8534 unstacking, so we have to emulate these by setting appropriate
8535 bits and offsets. */
8536 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8537 || inst
.reloc
.exp
.X_add_number
!= 0,
8538 _("this instruction does not support indexing"));
8540 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8541 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8543 if (!(inst
.instruction
& INDEX_UP
))
8544 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8546 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8548 inst
.operands
[2].preind
= 0;
8549 inst
.operands
[2].postind
= 1;
8553 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8556 /* iWMMXt instructions: strictly in alphabetical order. */
8559 do_iwmmxt_tandorc (void)
8561 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8565 do_iwmmxt_textrc (void)
8567 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8568 inst
.instruction
|= inst
.operands
[1].imm
;
8572 do_iwmmxt_textrm (void)
8574 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8575 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8576 inst
.instruction
|= inst
.operands
[2].imm
;
8580 do_iwmmxt_tinsr (void)
8582 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8583 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8584 inst
.instruction
|= inst
.operands
[2].imm
;
8588 do_iwmmxt_tmia (void)
8590 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8591 inst
.instruction
|= inst
.operands
[1].reg
;
8592 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8596 do_iwmmxt_waligni (void)
8598 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8599 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8600 inst
.instruction
|= inst
.operands
[2].reg
;
8601 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8605 do_iwmmxt_wmerge (void)
8607 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8608 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8609 inst
.instruction
|= inst
.operands
[2].reg
;
8610 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8614 do_iwmmxt_wmov (void)
8616 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8617 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8618 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8619 inst
.instruction
|= inst
.operands
[1].reg
;
8623 do_iwmmxt_wldstbh (void)
8626 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8628 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8630 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8631 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8635 do_iwmmxt_wldstw (void)
8637 /* RIWR_RIWC clears .isreg for a control register. */
8638 if (!inst
.operands
[0].isreg
)
8640 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8641 inst
.instruction
|= 0xf0000000;
8644 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8645 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8649 do_iwmmxt_wldstd (void)
8651 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8652 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8653 && inst
.operands
[1].immisreg
)
8655 inst
.instruction
&= ~0x1a000ff;
8656 inst
.instruction
|= (0xf << 28);
8657 if (inst
.operands
[1].preind
)
8658 inst
.instruction
|= PRE_INDEX
;
8659 if (!inst
.operands
[1].negative
)
8660 inst
.instruction
|= INDEX_UP
;
8661 if (inst
.operands
[1].writeback
)
8662 inst
.instruction
|= WRITE_BACK
;
8663 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8664 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8665 inst
.instruction
|= inst
.operands
[1].imm
;
8668 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8672 do_iwmmxt_wshufh (void)
8674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8675 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8676 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8677 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8681 do_iwmmxt_wzero (void)
8683 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8684 inst
.instruction
|= inst
.operands
[0].reg
;
8685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8686 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8690 do_iwmmxt_wrwrwr_or_imm5 (void)
8692 if (inst
.operands
[2].isreg
)
8695 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8696 _("immediate operand requires iWMMXt2"));
8698 if (inst
.operands
[2].imm
== 0)
8700 switch ((inst
.instruction
>> 20) & 0xf)
8706 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8707 inst
.operands
[2].imm
= 16;
8708 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8714 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8715 inst
.operands
[2].imm
= 32;
8716 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8723 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8725 wrn
= (inst
.instruction
>> 16) & 0xf;
8726 inst
.instruction
&= 0xff0fff0f;
8727 inst
.instruction
|= wrn
;
8728 /* Bail out here; the instruction is now assembled. */
8733 /* Map 32 -> 0, etc. */
8734 inst
.operands
[2].imm
&= 0x1f;
8735 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8739 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8740 operations first, then control, shift, and load/store. */
8742 /* Insns like "foo X,Y,Z". */
8745 do_mav_triple (void)
8747 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8748 inst
.instruction
|= inst
.operands
[1].reg
;
8749 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8752 /* Insns like "foo W,X,Y,Z".
8753 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8758 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8759 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8760 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8761 inst
.instruction
|= inst
.operands
[3].reg
;
8764 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8768 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8771 /* Maverick shift immediate instructions.
8772 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8773 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8778 int imm
= inst
.operands
[2].imm
;
8780 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8781 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8783 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8784 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8785 Bit 4 should be 0. */
8786 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8788 inst
.instruction
|= imm
;
8791 /* XScale instructions. Also sorted arithmetic before move. */
8793 /* Xscale multiply-accumulate (argument parse)
8796 MIAxycc acc0,Rm,Rs. */
8801 inst
.instruction
|= inst
.operands
[1].reg
;
8802 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8805 /* Xscale move-accumulator-register (argument parse)
8807 MARcc acc0,RdLo,RdHi. */
8812 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8813 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8816 /* Xscale move-register-accumulator (argument parse)
8818 MRAcc RdLo,RdHi,acc0. */
8823 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8824 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8825 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8828 /* Encoding functions relevant only to Thumb. */
8830 /* inst.operands[i] is a shifted-register operand; encode
8831 it into inst.instruction in the format used by Thumb32. */
8834 encode_thumb32_shifted_operand (int i
)
8836 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8837 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8839 constraint (inst
.operands
[i
].immisreg
,
8840 _("shift by register not allowed in thumb mode"));
8841 inst
.instruction
|= inst
.operands
[i
].reg
;
8842 if (shift
== SHIFT_RRX
)
8843 inst
.instruction
|= SHIFT_ROR
<< 4;
8846 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8847 _("expression too complex"));
8849 constraint (value
> 32
8850 || (value
== 32 && (shift
== SHIFT_LSL
8851 || shift
== SHIFT_ROR
)),
8852 _("shift expression is too large"));
8856 else if (value
== 32)
8859 inst
.instruction
|= shift
<< 4;
8860 inst
.instruction
|= (value
& 0x1c) << 10;
8861 inst
.instruction
|= (value
& 0x03) << 6;
8866 /* inst.operands[i] was set up by parse_address. Encode it into a
8867 Thumb32 format load or store instruction. Reject forms that cannot
8868 be used with such instructions. If is_t is true, reject forms that
8869 cannot be used with a T instruction; if is_d is true, reject forms
8870 that cannot be used with a D instruction. If it is a store insn,
8874 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8876 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8878 constraint (!inst
.operands
[i
].isreg
,
8879 _("Instruction does not support =N addresses"));
8881 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8882 if (inst
.operands
[i
].immisreg
)
8884 constraint (is_pc
, BAD_PC_ADDRESSING
);
8885 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8886 constraint (inst
.operands
[i
].negative
,
8887 _("Thumb does not support negative register indexing"));
8888 constraint (inst
.operands
[i
].postind
,
8889 _("Thumb does not support register post-indexing"));
8890 constraint (inst
.operands
[i
].writeback
,
8891 _("Thumb does not support register indexing with writeback"));
8892 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8893 _("Thumb supports only LSL in shifted register indexing"));
8895 inst
.instruction
|= inst
.operands
[i
].imm
;
8896 if (inst
.operands
[i
].shifted
)
8898 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8899 _("expression too complex"));
8900 constraint (inst
.reloc
.exp
.X_add_number
< 0
8901 || inst
.reloc
.exp
.X_add_number
> 3,
8902 _("shift out of range"));
8903 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8905 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8907 else if (inst
.operands
[i
].preind
)
8909 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8910 constraint (is_t
&& inst
.operands
[i
].writeback
,
8911 _("cannot use writeback with this instruction"));
8912 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8913 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8917 inst
.instruction
|= 0x01000000;
8918 if (inst
.operands
[i
].writeback
)
8919 inst
.instruction
|= 0x00200000;
8923 inst
.instruction
|= 0x00000c00;
8924 if (inst
.operands
[i
].writeback
)
8925 inst
.instruction
|= 0x00000100;
8927 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8929 else if (inst
.operands
[i
].postind
)
8931 gas_assert (inst
.operands
[i
].writeback
);
8932 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8933 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8936 inst
.instruction
|= 0x00200000;
8938 inst
.instruction
|= 0x00000900;
8939 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8941 else /* unindexed - only for coprocessor */
8942 inst
.error
= _("instruction does not accept unindexed addressing");
8945 /* Table of Thumb instructions which exist in both 16- and 32-bit
8946 encodings (the latter only in post-V6T2 cores). The index is the
8947 value used in the insns table below. When there is more than one
8948 possible 16-bit encoding for the instruction, this table always
8950 Also contains several pseudo-instructions used during relaxation. */
8951 #define T16_32_TAB \
8952 X(_adc, 4140, eb400000), \
8953 X(_adcs, 4140, eb500000), \
8954 X(_add, 1c00, eb000000), \
8955 X(_adds, 1c00, eb100000), \
8956 X(_addi, 0000, f1000000), \
8957 X(_addis, 0000, f1100000), \
8958 X(_add_pc,000f, f20f0000), \
8959 X(_add_sp,000d, f10d0000), \
8960 X(_adr, 000f, f20f0000), \
8961 X(_and, 4000, ea000000), \
8962 X(_ands, 4000, ea100000), \
8963 X(_asr, 1000, fa40f000), \
8964 X(_asrs, 1000, fa50f000), \
8965 X(_b, e000, f000b000), \
8966 X(_bcond, d000, f0008000), \
8967 X(_bic, 4380, ea200000), \
8968 X(_bics, 4380, ea300000), \
8969 X(_cmn, 42c0, eb100f00), \
8970 X(_cmp, 2800, ebb00f00), \
8971 X(_cpsie, b660, f3af8400), \
8972 X(_cpsid, b670, f3af8600), \
8973 X(_cpy, 4600, ea4f0000), \
8974 X(_dec_sp,80dd, f1ad0d00), \
8975 X(_eor, 4040, ea800000), \
8976 X(_eors, 4040, ea900000), \
8977 X(_inc_sp,00dd, f10d0d00), \
8978 X(_ldmia, c800, e8900000), \
8979 X(_ldr, 6800, f8500000), \
8980 X(_ldrb, 7800, f8100000), \
8981 X(_ldrh, 8800, f8300000), \
8982 X(_ldrsb, 5600, f9100000), \
8983 X(_ldrsh, 5e00, f9300000), \
8984 X(_ldr_pc,4800, f85f0000), \
8985 X(_ldr_pc2,4800, f85f0000), \
8986 X(_ldr_sp,9800, f85d0000), \
8987 X(_lsl, 0000, fa00f000), \
8988 X(_lsls, 0000, fa10f000), \
8989 X(_lsr, 0800, fa20f000), \
8990 X(_lsrs, 0800, fa30f000), \
8991 X(_mov, 2000, ea4f0000), \
8992 X(_movs, 2000, ea5f0000), \
8993 X(_mul, 4340, fb00f000), \
8994 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8995 X(_mvn, 43c0, ea6f0000), \
8996 X(_mvns, 43c0, ea7f0000), \
8997 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8998 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8999 X(_orr, 4300, ea400000), \
9000 X(_orrs, 4300, ea500000), \
9001 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9002 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9003 X(_rev, ba00, fa90f080), \
9004 X(_rev16, ba40, fa90f090), \
9005 X(_revsh, bac0, fa90f0b0), \
9006 X(_ror, 41c0, fa60f000), \
9007 X(_rors, 41c0, fa70f000), \
9008 X(_sbc, 4180, eb600000), \
9009 X(_sbcs, 4180, eb700000), \
9010 X(_stmia, c000, e8800000), \
9011 X(_str, 6000, f8400000), \
9012 X(_strb, 7000, f8000000), \
9013 X(_strh, 8000, f8200000), \
9014 X(_str_sp,9000, f84d0000), \
9015 X(_sub, 1e00, eba00000), \
9016 X(_subs, 1e00, ebb00000), \
9017 X(_subi, 8000, f1a00000), \
9018 X(_subis, 8000, f1b00000), \
9019 X(_sxtb, b240, fa4ff080), \
9020 X(_sxth, b200, fa0ff080), \
9021 X(_tst, 4200, ea100f00), \
9022 X(_uxtb, b2c0, fa5ff080), \
9023 X(_uxth, b280, fa1ff080), \
9024 X(_nop, bf00, f3af8000), \
9025 X(_yield, bf10, f3af8001), \
9026 X(_wfe, bf20, f3af8002), \
9027 X(_wfi, bf30, f3af8003), \
9028 X(_sev, bf40, f3af8004),
9030 /* To catch errors in encoding functions, the codes are all offset by
9031 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9032 as 16-bit instructions. */
9033 #define X(a,b,c) T_MNEM##a
9034 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9037 #define X(a,b,c) 0x##b
9038 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9039 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9042 #define X(a,b,c) 0x##c
9043 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9044 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9045 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9049 /* Thumb instruction encoders, in alphabetical order. */
9054 do_t_add_sub_w (void)
9058 Rd
= inst
.operands
[0].reg
;
9059 Rn
= inst
.operands
[1].reg
;
9061 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9062 is the SP-{plus,minus}-immediate form of the instruction. */
9064 constraint (Rd
== REG_PC
, BAD_PC
);
9066 reject_bad_reg (Rd
);
9068 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9069 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9072 /* Parse an add or subtract instruction. We get here with inst.instruction
9073 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9080 Rd
= inst
.operands
[0].reg
;
9081 Rs
= (inst
.operands
[1].present
9082 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9083 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9086 set_it_insn_type_last ();
9094 flags
= (inst
.instruction
== T_MNEM_adds
9095 || inst
.instruction
== T_MNEM_subs
);
9097 narrow
= !in_it_block ();
9099 narrow
= in_it_block ();
9100 if (!inst
.operands
[2].isreg
)
9104 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9106 add
= (inst
.instruction
== T_MNEM_add
9107 || inst
.instruction
== T_MNEM_adds
);
9109 if (inst
.size_req
!= 4)
9111 /* Attempt to use a narrow opcode, with relaxation if
9113 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9114 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9115 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9116 opcode
= T_MNEM_add_sp
;
9117 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9118 opcode
= T_MNEM_add_pc
;
9119 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9122 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9124 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9128 inst
.instruction
= THUMB_OP16(opcode
);
9129 inst
.instruction
|= (Rd
<< 4) | Rs
;
9130 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9131 if (inst
.size_req
!= 2)
9132 inst
.relax
= opcode
;
9135 constraint (inst
.size_req
== 2, BAD_HIREG
);
9137 if (inst
.size_req
== 4
9138 || (inst
.size_req
!= 2 && !opcode
))
9142 constraint (add
, BAD_PC
);
9143 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9144 _("only SUBS PC, LR, #const allowed"));
9145 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9146 _("expression too complex"));
9147 constraint (inst
.reloc
.exp
.X_add_number
< 0
9148 || inst
.reloc
.exp
.X_add_number
> 0xff,
9149 _("immediate value out of range"));
9150 inst
.instruction
= T2_SUBS_PC_LR
9151 | inst
.reloc
.exp
.X_add_number
;
9152 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9155 else if (Rs
== REG_PC
)
9157 /* Always use addw/subw. */
9158 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9159 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9163 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9164 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9167 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9169 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9171 inst
.instruction
|= Rd
<< 8;
9172 inst
.instruction
|= Rs
<< 16;
9177 Rn
= inst
.operands
[2].reg
;
9178 /* See if we can do this with a 16-bit instruction. */
9179 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9181 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9186 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9187 || inst
.instruction
== T_MNEM_add
)
9190 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9194 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9196 /* Thumb-1 cores (except v6-M) require at least one high
9197 register in a narrow non flag setting add. */
9198 if (Rd
> 7 || Rn
> 7
9199 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9200 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9207 inst
.instruction
= T_OPCODE_ADD_HI
;
9208 inst
.instruction
|= (Rd
& 8) << 4;
9209 inst
.instruction
|= (Rd
& 7);
9210 inst
.instruction
|= Rn
<< 3;
9216 constraint (Rd
== REG_PC
, BAD_PC
);
9217 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9218 constraint (Rs
== REG_PC
, BAD_PC
);
9219 reject_bad_reg (Rn
);
9221 /* If we get here, it can't be done in 16 bits. */
9222 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9223 _("shift must be constant"));
9224 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9225 inst
.instruction
|= Rd
<< 8;
9226 inst
.instruction
|= Rs
<< 16;
9227 encode_thumb32_shifted_operand (2);
9232 constraint (inst
.instruction
== T_MNEM_adds
9233 || inst
.instruction
== T_MNEM_subs
,
9236 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9238 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9239 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9242 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9244 inst
.instruction
|= (Rd
<< 4) | Rs
;
9245 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9249 Rn
= inst
.operands
[2].reg
;
9250 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9252 /* We now have Rd, Rs, and Rn set to registers. */
9253 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9255 /* Can't do this for SUB. */
9256 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9257 inst
.instruction
= T_OPCODE_ADD_HI
;
9258 inst
.instruction
|= (Rd
& 8) << 4;
9259 inst
.instruction
|= (Rd
& 7);
9261 inst
.instruction
|= Rn
<< 3;
9263 inst
.instruction
|= Rs
<< 3;
9265 constraint (1, _("dest must overlap one source register"));
9269 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9270 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9271 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9281 Rd
= inst
.operands
[0].reg
;
9282 reject_bad_reg (Rd
);
9284 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9286 /* Defer to section relaxation. */
9287 inst
.relax
= inst
.instruction
;
9288 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9289 inst
.instruction
|= Rd
<< 4;
9291 else if (unified_syntax
&& inst
.size_req
!= 2)
9293 /* Generate a 32-bit opcode. */
9294 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9295 inst
.instruction
|= Rd
<< 8;
9296 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9297 inst
.reloc
.pc_rel
= 1;
9301 /* Generate a 16-bit opcode. */
9302 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9303 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9304 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9305 inst
.reloc
.pc_rel
= 1;
9307 inst
.instruction
|= Rd
<< 4;
9311 /* Arithmetic instructions for which there is just one 16-bit
9312 instruction encoding, and it allows only two low registers.
9313 For maximal compatibility with ARM syntax, we allow three register
9314 operands even when Thumb-32 instructions are not available, as long
9315 as the first two are identical. For instance, both "sbc r0,r1" and
9316 "sbc r0,r0,r1" are allowed. */
9322 Rd
= inst
.operands
[0].reg
;
9323 Rs
= (inst
.operands
[1].present
9324 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9325 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9326 Rn
= inst
.operands
[2].reg
;
9328 reject_bad_reg (Rd
);
9329 reject_bad_reg (Rs
);
9330 if (inst
.operands
[2].isreg
)
9331 reject_bad_reg (Rn
);
9335 if (!inst
.operands
[2].isreg
)
9337 /* For an immediate, we always generate a 32-bit opcode;
9338 section relaxation will shrink it later if possible. */
9339 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9340 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9341 inst
.instruction
|= Rd
<< 8;
9342 inst
.instruction
|= Rs
<< 16;
9343 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9349 /* See if we can do this with a 16-bit instruction. */
9350 if (THUMB_SETS_FLAGS (inst
.instruction
))
9351 narrow
= !in_it_block ();
9353 narrow
= in_it_block ();
9355 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9357 if (inst
.operands
[2].shifted
)
9359 if (inst
.size_req
== 4)
9365 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9366 inst
.instruction
|= Rd
;
9367 inst
.instruction
|= Rn
<< 3;
9371 /* If we get here, it can't be done in 16 bits. */
9372 constraint (inst
.operands
[2].shifted
9373 && inst
.operands
[2].immisreg
,
9374 _("shift must be constant"));
9375 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9376 inst
.instruction
|= Rd
<< 8;
9377 inst
.instruction
|= Rs
<< 16;
9378 encode_thumb32_shifted_operand (2);
9383 /* On its face this is a lie - the instruction does set the
9384 flags. However, the only supported mnemonic in this mode
9386 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9388 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9389 _("unshifted register required"));
9390 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9391 constraint (Rd
!= Rs
,
9392 _("dest and source1 must be the same register"));
9394 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9395 inst
.instruction
|= Rd
;
9396 inst
.instruction
|= Rn
<< 3;
9400 /* Similarly, but for instructions where the arithmetic operation is
9401 commutative, so we can allow either of them to be different from
9402 the destination operand in a 16-bit instruction. For instance, all
9403 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9410 Rd
= inst
.operands
[0].reg
;
9411 Rs
= (inst
.operands
[1].present
9412 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9413 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9414 Rn
= inst
.operands
[2].reg
;
9416 reject_bad_reg (Rd
);
9417 reject_bad_reg (Rs
);
9418 if (inst
.operands
[2].isreg
)
9419 reject_bad_reg (Rn
);
9423 if (!inst
.operands
[2].isreg
)
9425 /* For an immediate, we always generate a 32-bit opcode;
9426 section relaxation will shrink it later if possible. */
9427 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9428 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9429 inst
.instruction
|= Rd
<< 8;
9430 inst
.instruction
|= Rs
<< 16;
9431 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9437 /* See if we can do this with a 16-bit instruction. */
9438 if (THUMB_SETS_FLAGS (inst
.instruction
))
9439 narrow
= !in_it_block ();
9441 narrow
= in_it_block ();
9443 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9445 if (inst
.operands
[2].shifted
)
9447 if (inst
.size_req
== 4)
9454 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9455 inst
.instruction
|= Rd
;
9456 inst
.instruction
|= Rn
<< 3;
9461 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9462 inst
.instruction
|= Rd
;
9463 inst
.instruction
|= Rs
<< 3;
9468 /* If we get here, it can't be done in 16 bits. */
9469 constraint (inst
.operands
[2].shifted
9470 && inst
.operands
[2].immisreg
,
9471 _("shift must be constant"));
9472 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9473 inst
.instruction
|= Rd
<< 8;
9474 inst
.instruction
|= Rs
<< 16;
9475 encode_thumb32_shifted_operand (2);
9480 /* On its face this is a lie - the instruction does set the
9481 flags. However, the only supported mnemonic in this mode
9483 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9485 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9486 _("unshifted register required"));
9487 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9489 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9490 inst
.instruction
|= Rd
;
9493 inst
.instruction
|= Rn
<< 3;
9495 inst
.instruction
|= Rs
<< 3;
9497 constraint (1, _("dest must overlap one source register"));
9504 if (inst
.operands
[0].present
)
9506 constraint ((inst
.instruction
& 0xf0) != 0x40
9507 && inst
.operands
[0].imm
> 0xf
9508 && inst
.operands
[0].imm
< 0x0,
9509 _("bad barrier type"));
9510 inst
.instruction
|= inst
.operands
[0].imm
;
9513 inst
.instruction
|= 0xf;
9520 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9521 constraint (msb
> 32, _("bit-field extends past end of register"));
9522 /* The instruction encoding stores the LSB and MSB,
9523 not the LSB and width. */
9524 Rd
= inst
.operands
[0].reg
;
9525 reject_bad_reg (Rd
);
9526 inst
.instruction
|= Rd
<< 8;
9527 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9528 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9529 inst
.instruction
|= msb
- 1;
9538 Rd
= inst
.operands
[0].reg
;
9539 reject_bad_reg (Rd
);
9541 /* #0 in second position is alternative syntax for bfc, which is
9542 the same instruction but with REG_PC in the Rm field. */
9543 if (!inst
.operands
[1].isreg
)
9547 Rn
= inst
.operands
[1].reg
;
9548 reject_bad_reg (Rn
);
9551 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9552 constraint (msb
> 32, _("bit-field extends past end of register"));
9553 /* The instruction encoding stores the LSB and MSB,
9554 not the LSB and width. */
9555 inst
.instruction
|= Rd
<< 8;
9556 inst
.instruction
|= Rn
<< 16;
9557 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9558 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9559 inst
.instruction
|= msb
- 1;
9567 Rd
= inst
.operands
[0].reg
;
9568 Rn
= inst
.operands
[1].reg
;
9570 reject_bad_reg (Rd
);
9571 reject_bad_reg (Rn
);
9573 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9574 _("bit-field extends past end of register"));
9575 inst
.instruction
|= Rd
<< 8;
9576 inst
.instruction
|= Rn
<< 16;
9577 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9578 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9579 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9582 /* ARM V5 Thumb BLX (argument parse)
9583 BLX <target_addr> which is BLX(1)
9584 BLX <Rm> which is BLX(2)
9585 Unfortunately, there are two different opcodes for this mnemonic.
9586 So, the insns[].value is not used, and the code here zaps values
9587 into inst.instruction.
9589 ??? How to take advantage of the additional two bits of displacement
9590 available in Thumb32 mode? Need new relocation? */
9595 set_it_insn_type_last ();
9597 if (inst
.operands
[0].isreg
)
9599 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9600 /* We have a register, so this is BLX(2). */
9601 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9605 /* No register. This must be BLX(1). */
9606 inst
.instruction
= 0xf000e800;
9607 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9608 inst
.reloc
.pc_rel
= 1;
9619 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9623 /* Conditional branches inside IT blocks are encoded as unconditional
9630 if (cond
!= COND_ALWAYS
)
9631 opcode
= T_MNEM_bcond
;
9633 opcode
= inst
.instruction
;
9635 if (unified_syntax
&& inst
.size_req
== 4)
9637 inst
.instruction
= THUMB_OP32(opcode
);
9638 if (cond
== COND_ALWAYS
)
9639 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9642 gas_assert (cond
!= 0xF);
9643 inst
.instruction
|= cond
<< 22;
9644 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9649 inst
.instruction
= THUMB_OP16(opcode
);
9650 if (cond
== COND_ALWAYS
)
9651 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9654 inst
.instruction
|= cond
<< 8;
9655 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9657 /* Allow section relaxation. */
9658 if (unified_syntax
&& inst
.size_req
!= 2)
9659 inst
.relax
= opcode
;
9662 inst
.reloc
.pc_rel
= 1;
9668 constraint (inst
.cond
!= COND_ALWAYS
,
9669 _("instruction is always unconditional"));
9670 if (inst
.operands
[0].present
)
9672 constraint (inst
.operands
[0].imm
> 255,
9673 _("immediate value out of range"));
9674 inst
.instruction
|= inst
.operands
[0].imm
;
9675 set_it_insn_type (NEUTRAL_IT_INSN
);
9680 do_t_branch23 (void)
9682 set_it_insn_type_last ();
9683 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9684 inst
.reloc
.pc_rel
= 1;
9686 #if defined(OBJ_COFF)
9687 /* If the destination of the branch is a defined symbol which does not have
9688 the THUMB_FUNC attribute, then we must be calling a function which has
9689 the (interfacearm) attribute. We look for the Thumb entry point to that
9690 function and change the branch to refer to that function instead. */
9691 if ( inst
.reloc
.exp
.X_op
== O_symbol
9692 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9693 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9694 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9695 inst
.reloc
.exp
.X_add_symbol
=
9696 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9703 set_it_insn_type_last ();
9704 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9705 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9706 should cause the alignment to be checked once it is known. This is
9707 because BX PC only works if the instruction is word aligned. */
9715 set_it_insn_type_last ();
9716 Rm
= inst
.operands
[0].reg
;
9717 reject_bad_reg (Rm
);
9718 inst
.instruction
|= Rm
<< 16;
9727 Rd
= inst
.operands
[0].reg
;
9728 Rm
= inst
.operands
[1].reg
;
9730 reject_bad_reg (Rd
);
9731 reject_bad_reg (Rm
);
9733 inst
.instruction
|= Rd
<< 8;
9734 inst
.instruction
|= Rm
<< 16;
9735 inst
.instruction
|= Rm
;
9741 set_it_insn_type (OUTSIDE_IT_INSN
);
9742 inst
.instruction
|= inst
.operands
[0].imm
;
9748 set_it_insn_type (OUTSIDE_IT_INSN
);
9750 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9751 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9753 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9754 inst
.instruction
= 0xf3af8000;
9755 inst
.instruction
|= imod
<< 9;
9756 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9757 if (inst
.operands
[1].present
)
9758 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9762 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9763 && (inst
.operands
[0].imm
& 4),
9764 _("selected processor does not support 'A' form "
9765 "of this instruction"));
9766 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9767 _("Thumb does not support the 2-argument "
9768 "form of this instruction"));
9769 inst
.instruction
|= inst
.operands
[0].imm
;
9773 /* THUMB CPY instruction (argument parse). */
9778 if (inst
.size_req
== 4)
9780 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9781 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9782 inst
.instruction
|= inst
.operands
[1].reg
;
9786 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9787 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9788 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9795 set_it_insn_type (OUTSIDE_IT_INSN
);
9796 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9797 inst
.instruction
|= inst
.operands
[0].reg
;
9798 inst
.reloc
.pc_rel
= 1;
9799 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9805 inst
.instruction
|= inst
.operands
[0].imm
;
9811 unsigned Rd
, Rn
, Rm
;
9813 Rd
= inst
.operands
[0].reg
;
9814 Rn
= (inst
.operands
[1].present
9815 ? inst
.operands
[1].reg
: Rd
);
9816 Rm
= inst
.operands
[2].reg
;
9818 reject_bad_reg (Rd
);
9819 reject_bad_reg (Rn
);
9820 reject_bad_reg (Rm
);
9822 inst
.instruction
|= Rd
<< 8;
9823 inst
.instruction
|= Rn
<< 16;
9824 inst
.instruction
|= Rm
;
9830 if (unified_syntax
&& inst
.size_req
== 4)
9831 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9833 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9839 unsigned int cond
= inst
.operands
[0].imm
;
9841 set_it_insn_type (IT_INSN
);
9842 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9845 /* If the condition is a negative condition, invert the mask. */
9846 if ((cond
& 0x1) == 0x0)
9848 unsigned int mask
= inst
.instruction
& 0x000f;
9850 if ((mask
& 0x7) == 0)
9851 /* no conversion needed */;
9852 else if ((mask
& 0x3) == 0)
9854 else if ((mask
& 0x1) == 0)
9859 inst
.instruction
&= 0xfff0;
9860 inst
.instruction
|= mask
;
9863 inst
.instruction
|= cond
<< 4;
9866 /* Helper function used for both push/pop and ldm/stm. */
9868 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9872 load
= (inst
.instruction
& (1 << 20)) != 0;
9874 if (mask
& (1 << 13))
9875 inst
.error
= _("SP not allowed in register list");
9877 if ((mask
& (1 << base
)) != 0
9879 inst
.error
= _("having the base register in the register list when "
9880 "using write back is UNPREDICTABLE");
9884 if (mask
& (1 << 15))
9886 if (mask
& (1 << 14))
9887 inst
.error
= _("LR and PC should not both be in register list");
9889 set_it_insn_type_last ();
9894 if (mask
& (1 << 15))
9895 inst
.error
= _("PC not allowed in register list");
9898 if ((mask
& (mask
- 1)) == 0)
9900 /* Single register transfers implemented as str/ldr. */
9903 if (inst
.instruction
& (1 << 23))
9904 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9906 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9910 if (inst
.instruction
& (1 << 23))
9911 inst
.instruction
= 0x00800000; /* ia -> [base] */
9913 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9916 inst
.instruction
|= 0xf8400000;
9918 inst
.instruction
|= 0x00100000;
9920 mask
= ffs (mask
) - 1;
9924 inst
.instruction
|= WRITE_BACK
;
9926 inst
.instruction
|= mask
;
9927 inst
.instruction
|= base
<< 16;
9933 /* This really doesn't seem worth it. */
9934 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9935 _("expression too complex"));
9936 constraint (inst
.operands
[1].writeback
,
9937 _("Thumb load/store multiple does not support {reglist}^"));
9945 /* See if we can use a 16-bit instruction. */
9946 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9947 && inst
.size_req
!= 4
9948 && !(inst
.operands
[1].imm
& ~0xff))
9950 mask
= 1 << inst
.operands
[0].reg
;
9952 if (inst
.operands
[0].reg
<= 7)
9954 if (inst
.instruction
== T_MNEM_stmia
9955 ? inst
.operands
[0].writeback
9956 : (inst
.operands
[0].writeback
9957 == !(inst
.operands
[1].imm
& mask
)))
9959 if (inst
.instruction
== T_MNEM_stmia
9960 && (inst
.operands
[1].imm
& mask
)
9961 && (inst
.operands
[1].imm
& (mask
- 1)))
9962 as_warn (_("value stored for r%d is UNKNOWN"),
9963 inst
.operands
[0].reg
);
9965 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9966 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9967 inst
.instruction
|= inst
.operands
[1].imm
;
9970 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
9972 /* This means 1 register in reg list one of 3 situations:
9973 1. Instruction is stmia, but without writeback.
9974 2. lmdia without writeback, but with Rn not in
9976 3. ldmia with writeback, but with Rn in reglist.
9977 Case 3 is UNPREDICTABLE behaviour, so we handle
9978 case 1 and 2 which can be converted into a 16-bit
9979 str or ldr. The SP cases are handled below. */
9980 unsigned long opcode
;
9981 /* First, record an error for Case 3. */
9982 if (inst
.operands
[1].imm
& mask
9983 && inst
.operands
[0].writeback
)
9985 _("having the base register in the register list when "
9986 "using write back is UNPREDICTABLE");
9988 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
9990 inst
.instruction
= THUMB_OP16 (opcode
);
9991 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9992 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
9996 else if (inst
.operands
[0] .reg
== REG_SP
)
9998 if (inst
.operands
[0].writeback
)
10001 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10002 ? T_MNEM_push
: T_MNEM_pop
);
10003 inst
.instruction
|= inst
.operands
[1].imm
;
10006 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10009 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10010 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10011 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10019 if (inst
.instruction
< 0xffff)
10020 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10022 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10023 inst
.operands
[0].writeback
);
10028 constraint (inst
.operands
[0].reg
> 7
10029 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10030 constraint (inst
.instruction
!= T_MNEM_ldmia
10031 && inst
.instruction
!= T_MNEM_stmia
,
10032 _("Thumb-2 instruction only valid in unified syntax"));
10033 if (inst
.instruction
== T_MNEM_stmia
)
10035 if (!inst
.operands
[0].writeback
)
10036 as_warn (_("this instruction will write back the base register"));
10037 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10038 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10039 as_warn (_("value stored for r%d is UNKNOWN"),
10040 inst
.operands
[0].reg
);
10044 if (!inst
.operands
[0].writeback
10045 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10046 as_warn (_("this instruction will write back the base register"));
10047 else if (inst
.operands
[0].writeback
10048 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10049 as_warn (_("this instruction will not write back the base register"));
10052 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10053 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10054 inst
.instruction
|= inst
.operands
[1].imm
;
10061 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10062 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10063 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10064 || inst
.operands
[1].negative
,
10067 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10070 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10071 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10077 if (!inst
.operands
[1].present
)
10079 constraint (inst
.operands
[0].reg
== REG_LR
,
10080 _("r14 not allowed as first register "
10081 "when second register is omitted"));
10082 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10084 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10087 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10088 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10089 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10095 unsigned long opcode
;
10098 if (inst
.operands
[0].isreg
10099 && !inst
.operands
[0].preind
10100 && inst
.operands
[0].reg
== REG_PC
)
10101 set_it_insn_type_last ();
10103 opcode
= inst
.instruction
;
10104 if (unified_syntax
)
10106 if (!inst
.operands
[1].isreg
)
10108 if (opcode
<= 0xffff)
10109 inst
.instruction
= THUMB_OP32 (opcode
);
10110 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10113 if (inst
.operands
[1].isreg
10114 && !inst
.operands
[1].writeback
10115 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10116 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10117 && opcode
<= 0xffff
10118 && inst
.size_req
!= 4)
10120 /* Insn may have a 16-bit form. */
10121 Rn
= inst
.operands
[1].reg
;
10122 if (inst
.operands
[1].immisreg
)
10124 inst
.instruction
= THUMB_OP16 (opcode
);
10126 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10128 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10129 reject_bad_reg (inst
.operands
[1].imm
);
10131 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10132 && opcode
!= T_MNEM_ldrsb
)
10133 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10134 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10141 if (inst
.reloc
.pc_rel
)
10142 opcode
= T_MNEM_ldr_pc2
;
10144 opcode
= T_MNEM_ldr_pc
;
10148 if (opcode
== T_MNEM_ldr
)
10149 opcode
= T_MNEM_ldr_sp
;
10151 opcode
= T_MNEM_str_sp
;
10153 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10157 inst
.instruction
= inst
.operands
[0].reg
;
10158 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10160 inst
.instruction
|= THUMB_OP16 (opcode
);
10161 if (inst
.size_req
== 2)
10162 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10164 inst
.relax
= opcode
;
10168 /* Definitely a 32-bit variant. */
10170 /* Do some validations regarding addressing modes. */
10171 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10172 && opcode
!= T_MNEM_str
)
10173 reject_bad_reg (inst
.operands
[1].imm
);
10175 inst
.instruction
= THUMB_OP32 (opcode
);
10176 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10177 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10181 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10183 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10185 /* Only [Rn,Rm] is acceptable. */
10186 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10187 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10188 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10189 || inst
.operands
[1].negative
,
10190 _("Thumb does not support this addressing mode"));
10191 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10195 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10196 if (!inst
.operands
[1].isreg
)
10197 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10200 constraint (!inst
.operands
[1].preind
10201 || inst
.operands
[1].shifted
10202 || inst
.operands
[1].writeback
,
10203 _("Thumb does not support this addressing mode"));
10204 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10206 constraint (inst
.instruction
& 0x0600,
10207 _("byte or halfword not valid for base register"));
10208 constraint (inst
.operands
[1].reg
== REG_PC
10209 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10210 _("r15 based store not allowed"));
10211 constraint (inst
.operands
[1].immisreg
,
10212 _("invalid base register for register offset"));
10214 if (inst
.operands
[1].reg
== REG_PC
)
10215 inst
.instruction
= T_OPCODE_LDR_PC
;
10216 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10217 inst
.instruction
= T_OPCODE_LDR_SP
;
10219 inst
.instruction
= T_OPCODE_STR_SP
;
10221 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10222 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10226 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10227 if (!inst
.operands
[1].immisreg
)
10229 /* Immediate offset. */
10230 inst
.instruction
|= inst
.operands
[0].reg
;
10231 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10232 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10236 /* Register offset. */
10237 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10238 constraint (inst
.operands
[1].negative
,
10239 _("Thumb does not support this addressing mode"));
10242 switch (inst
.instruction
)
10244 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10245 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10246 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10247 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10248 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10249 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10250 case 0x5600 /* ldrsb */:
10251 case 0x5e00 /* ldrsh */: break;
10255 inst
.instruction
|= inst
.operands
[0].reg
;
10256 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10257 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10263 if (!inst
.operands
[1].present
)
10265 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10266 constraint (inst
.operands
[0].reg
== REG_LR
,
10267 _("r14 not allowed here"));
10269 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10270 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10271 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10277 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10278 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10284 unsigned Rd
, Rn
, Rm
, Ra
;
10286 Rd
= inst
.operands
[0].reg
;
10287 Rn
= inst
.operands
[1].reg
;
10288 Rm
= inst
.operands
[2].reg
;
10289 Ra
= inst
.operands
[3].reg
;
10291 reject_bad_reg (Rd
);
10292 reject_bad_reg (Rn
);
10293 reject_bad_reg (Rm
);
10294 reject_bad_reg (Ra
);
10296 inst
.instruction
|= Rd
<< 8;
10297 inst
.instruction
|= Rn
<< 16;
10298 inst
.instruction
|= Rm
;
10299 inst
.instruction
|= Ra
<< 12;
10305 unsigned RdLo
, RdHi
, Rn
, Rm
;
10307 RdLo
= inst
.operands
[0].reg
;
10308 RdHi
= inst
.operands
[1].reg
;
10309 Rn
= inst
.operands
[2].reg
;
10310 Rm
= inst
.operands
[3].reg
;
10312 reject_bad_reg (RdLo
);
10313 reject_bad_reg (RdHi
);
10314 reject_bad_reg (Rn
);
10315 reject_bad_reg (Rm
);
10317 inst
.instruction
|= RdLo
<< 12;
10318 inst
.instruction
|= RdHi
<< 8;
10319 inst
.instruction
|= Rn
<< 16;
10320 inst
.instruction
|= Rm
;
10324 do_t_mov_cmp (void)
10328 Rn
= inst
.operands
[0].reg
;
10329 Rm
= inst
.operands
[1].reg
;
10332 set_it_insn_type_last ();
10334 if (unified_syntax
)
10336 int r0off
= (inst
.instruction
== T_MNEM_mov
10337 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10338 unsigned long opcode
;
10339 bfd_boolean narrow
;
10340 bfd_boolean low_regs
;
10342 low_regs
= (Rn
<= 7 && Rm
<= 7);
10343 opcode
= inst
.instruction
;
10344 if (in_it_block ())
10345 narrow
= opcode
!= T_MNEM_movs
;
10347 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10348 if (inst
.size_req
== 4
10349 || inst
.operands
[1].shifted
)
10352 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10353 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10354 && !inst
.operands
[1].shifted
10358 inst
.instruction
= T2_SUBS_PC_LR
;
10362 if (opcode
== T_MNEM_cmp
)
10364 constraint (Rn
== REG_PC
, BAD_PC
);
10367 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10369 warn_deprecated_sp (Rm
);
10370 /* R15 was documented as a valid choice for Rm in ARMv6,
10371 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10372 tools reject R15, so we do too. */
10373 constraint (Rm
== REG_PC
, BAD_PC
);
10376 reject_bad_reg (Rm
);
10378 else if (opcode
== T_MNEM_mov
10379 || opcode
== T_MNEM_movs
)
10381 if (inst
.operands
[1].isreg
)
10383 if (opcode
== T_MNEM_movs
)
10385 reject_bad_reg (Rn
);
10386 reject_bad_reg (Rm
);
10390 /* This is mov.n. */
10391 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10392 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10394 as_warn (_("Use of r%u as a source register is "
10395 "deprecated when r%u is the destination "
10396 "register."), Rm
, Rn
);
10401 /* This is mov.w. */
10402 constraint (Rn
== REG_PC
, BAD_PC
);
10403 constraint (Rm
== REG_PC
, BAD_PC
);
10404 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10408 reject_bad_reg (Rn
);
10411 if (!inst
.operands
[1].isreg
)
10413 /* Immediate operand. */
10414 if (!in_it_block () && opcode
== T_MNEM_mov
)
10416 if (low_regs
&& narrow
)
10418 inst
.instruction
= THUMB_OP16 (opcode
);
10419 inst
.instruction
|= Rn
<< 8;
10420 if (inst
.size_req
== 2)
10421 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10423 inst
.relax
= opcode
;
10427 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10428 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10429 inst
.instruction
|= Rn
<< r0off
;
10430 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10433 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10434 && (inst
.instruction
== T_MNEM_mov
10435 || inst
.instruction
== T_MNEM_movs
))
10437 /* Register shifts are encoded as separate shift instructions. */
10438 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10440 if (in_it_block ())
10445 if (inst
.size_req
== 4)
10448 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10454 switch (inst
.operands
[1].shift_kind
)
10457 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10460 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10463 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10466 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10472 inst
.instruction
= opcode
;
10475 inst
.instruction
|= Rn
;
10476 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10481 inst
.instruction
|= CONDS_BIT
;
10483 inst
.instruction
|= Rn
<< 8;
10484 inst
.instruction
|= Rm
<< 16;
10485 inst
.instruction
|= inst
.operands
[1].imm
;
10490 /* Some mov with immediate shift have narrow variants.
10491 Register shifts are handled above. */
10492 if (low_regs
&& inst
.operands
[1].shifted
10493 && (inst
.instruction
== T_MNEM_mov
10494 || inst
.instruction
== T_MNEM_movs
))
10496 if (in_it_block ())
10497 narrow
= (inst
.instruction
== T_MNEM_mov
);
10499 narrow
= (inst
.instruction
== T_MNEM_movs
);
10504 switch (inst
.operands
[1].shift_kind
)
10506 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10507 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10508 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10509 default: narrow
= FALSE
; break;
10515 inst
.instruction
|= Rn
;
10516 inst
.instruction
|= Rm
<< 3;
10517 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10521 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10522 inst
.instruction
|= Rn
<< r0off
;
10523 encode_thumb32_shifted_operand (1);
10527 switch (inst
.instruction
)
10530 inst
.instruction
= T_OPCODE_MOV_HR
;
10531 inst
.instruction
|= (Rn
& 0x8) << 4;
10532 inst
.instruction
|= (Rn
& 0x7);
10533 inst
.instruction
|= Rm
<< 3;
10537 /* We know we have low registers at this point.
10538 Generate LSLS Rd, Rs, #0. */
10539 inst
.instruction
= T_OPCODE_LSL_I
;
10540 inst
.instruction
|= Rn
;
10541 inst
.instruction
|= Rm
<< 3;
10547 inst
.instruction
= T_OPCODE_CMP_LR
;
10548 inst
.instruction
|= Rn
;
10549 inst
.instruction
|= Rm
<< 3;
10553 inst
.instruction
= T_OPCODE_CMP_HR
;
10554 inst
.instruction
|= (Rn
& 0x8) << 4;
10555 inst
.instruction
|= (Rn
& 0x7);
10556 inst
.instruction
|= Rm
<< 3;
10563 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10565 /* PR 10443: Do not silently ignore shifted operands. */
10566 constraint (inst
.operands
[1].shifted
,
10567 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10569 if (inst
.operands
[1].isreg
)
10571 if (Rn
< 8 && Rm
< 8)
10573 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10574 since a MOV instruction produces unpredictable results. */
10575 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10576 inst
.instruction
= T_OPCODE_ADD_I3
;
10578 inst
.instruction
= T_OPCODE_CMP_LR
;
10580 inst
.instruction
|= Rn
;
10581 inst
.instruction
|= Rm
<< 3;
10585 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10586 inst
.instruction
= T_OPCODE_MOV_HR
;
10588 inst
.instruction
= T_OPCODE_CMP_HR
;
10594 constraint (Rn
> 7,
10595 _("only lo regs allowed with immediate"));
10596 inst
.instruction
|= Rn
<< 8;
10597 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10608 top
= (inst
.instruction
& 0x00800000) != 0;
10609 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10611 constraint (top
, _(":lower16: not allowed this instruction"));
10612 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10614 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10616 constraint (!top
, _(":upper16: not allowed this instruction"));
10617 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10620 Rd
= inst
.operands
[0].reg
;
10621 reject_bad_reg (Rd
);
10623 inst
.instruction
|= Rd
<< 8;
10624 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10626 imm
= inst
.reloc
.exp
.X_add_number
;
10627 inst
.instruction
|= (imm
& 0xf000) << 4;
10628 inst
.instruction
|= (imm
& 0x0800) << 15;
10629 inst
.instruction
|= (imm
& 0x0700) << 4;
10630 inst
.instruction
|= (imm
& 0x00ff);
10635 do_t_mvn_tst (void)
10639 Rn
= inst
.operands
[0].reg
;
10640 Rm
= inst
.operands
[1].reg
;
10642 if (inst
.instruction
== T_MNEM_cmp
10643 || inst
.instruction
== T_MNEM_cmn
)
10644 constraint (Rn
== REG_PC
, BAD_PC
);
10646 reject_bad_reg (Rn
);
10647 reject_bad_reg (Rm
);
10649 if (unified_syntax
)
10651 int r0off
= (inst
.instruction
== T_MNEM_mvn
10652 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10653 bfd_boolean narrow
;
10655 if (inst
.size_req
== 4
10656 || inst
.instruction
> 0xffff
10657 || inst
.operands
[1].shifted
10658 || Rn
> 7 || Rm
> 7)
10660 else if (inst
.instruction
== T_MNEM_cmn
)
10662 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10663 narrow
= !in_it_block ();
10665 narrow
= in_it_block ();
10667 if (!inst
.operands
[1].isreg
)
10669 /* For an immediate, we always generate a 32-bit opcode;
10670 section relaxation will shrink it later if possible. */
10671 if (inst
.instruction
< 0xffff)
10672 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10673 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10674 inst
.instruction
|= Rn
<< r0off
;
10675 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10679 /* See if we can do this with a 16-bit instruction. */
10682 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10683 inst
.instruction
|= Rn
;
10684 inst
.instruction
|= Rm
<< 3;
10688 constraint (inst
.operands
[1].shifted
10689 && inst
.operands
[1].immisreg
,
10690 _("shift must be constant"));
10691 if (inst
.instruction
< 0xffff)
10692 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10693 inst
.instruction
|= Rn
<< r0off
;
10694 encode_thumb32_shifted_operand (1);
10700 constraint (inst
.instruction
> 0xffff
10701 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10702 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10703 _("unshifted register required"));
10704 constraint (Rn
> 7 || Rm
> 7,
10707 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10708 inst
.instruction
|= Rn
;
10709 inst
.instruction
|= Rm
<< 3;
10719 if (do_vfp_nsyn_mrs () == SUCCESS
)
10722 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10725 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10726 _("selected processor does not support "
10727 "requested special purpose register"));
10731 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10732 _("selected processor does not support "
10733 "requested special purpose register"));
10734 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10735 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10736 _("'CPSR' or 'SPSR' expected"));
10739 Rd
= inst
.operands
[0].reg
;
10740 reject_bad_reg (Rd
);
10742 inst
.instruction
|= Rd
<< 8;
10743 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10744 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10753 if (do_vfp_nsyn_msr () == SUCCESS
)
10756 constraint (!inst
.operands
[1].isreg
,
10757 _("Thumb encoding does not support an immediate here"));
10758 flags
= inst
.operands
[0].imm
;
10761 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10762 _("selected processor does not support "
10763 "requested special purpose register"));
10767 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10768 _("selected processor does not support "
10769 "requested special purpose register"));
10773 Rn
= inst
.operands
[1].reg
;
10774 reject_bad_reg (Rn
);
10776 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10777 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10778 inst
.instruction
|= (flags
& 0xff);
10779 inst
.instruction
|= Rn
<< 16;
10785 bfd_boolean narrow
;
10786 unsigned Rd
, Rn
, Rm
;
10788 if (!inst
.operands
[2].present
)
10789 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10791 Rd
= inst
.operands
[0].reg
;
10792 Rn
= inst
.operands
[1].reg
;
10793 Rm
= inst
.operands
[2].reg
;
10795 if (unified_syntax
)
10797 if (inst
.size_req
== 4
10803 else if (inst
.instruction
== T_MNEM_muls
)
10804 narrow
= !in_it_block ();
10806 narrow
= in_it_block ();
10810 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10811 constraint (Rn
> 7 || Rm
> 7,
10818 /* 16-bit MULS/Conditional MUL. */
10819 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10820 inst
.instruction
|= Rd
;
10823 inst
.instruction
|= Rm
<< 3;
10825 inst
.instruction
|= Rn
<< 3;
10827 constraint (1, _("dest must overlap one source register"));
10831 constraint (inst
.instruction
!= T_MNEM_mul
,
10832 _("Thumb-2 MUL must not set flags"));
10834 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10835 inst
.instruction
|= Rd
<< 8;
10836 inst
.instruction
|= Rn
<< 16;
10837 inst
.instruction
|= Rm
<< 0;
10839 reject_bad_reg (Rd
);
10840 reject_bad_reg (Rn
);
10841 reject_bad_reg (Rm
);
10848 unsigned RdLo
, RdHi
, Rn
, Rm
;
10850 RdLo
= inst
.operands
[0].reg
;
10851 RdHi
= inst
.operands
[1].reg
;
10852 Rn
= inst
.operands
[2].reg
;
10853 Rm
= inst
.operands
[3].reg
;
10855 reject_bad_reg (RdLo
);
10856 reject_bad_reg (RdHi
);
10857 reject_bad_reg (Rn
);
10858 reject_bad_reg (Rm
);
10860 inst
.instruction
|= RdLo
<< 12;
10861 inst
.instruction
|= RdHi
<< 8;
10862 inst
.instruction
|= Rn
<< 16;
10863 inst
.instruction
|= Rm
;
10866 as_tsktsk (_("rdhi and rdlo must be different"));
10872 set_it_insn_type (NEUTRAL_IT_INSN
);
10874 if (unified_syntax
)
10876 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10878 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10879 inst
.instruction
|= inst
.operands
[0].imm
;
10883 /* PR9722: Check for Thumb2 availability before
10884 generating a thumb2 nop instruction. */
10885 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10887 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10888 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10891 inst
.instruction
= 0x46c0;
10896 constraint (inst
.operands
[0].present
,
10897 _("Thumb does not support NOP with hints"));
10898 inst
.instruction
= 0x46c0;
10905 if (unified_syntax
)
10907 bfd_boolean narrow
;
10909 if (THUMB_SETS_FLAGS (inst
.instruction
))
10910 narrow
= !in_it_block ();
10912 narrow
= in_it_block ();
10913 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10915 if (inst
.size_req
== 4)
10920 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10921 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10922 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10926 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10927 inst
.instruction
|= inst
.operands
[0].reg
;
10928 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10933 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10935 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10937 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10938 inst
.instruction
|= inst
.operands
[0].reg
;
10939 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10948 Rd
= inst
.operands
[0].reg
;
10949 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10951 reject_bad_reg (Rd
);
10952 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10953 reject_bad_reg (Rn
);
10955 inst
.instruction
|= Rd
<< 8;
10956 inst
.instruction
|= Rn
<< 16;
10958 if (!inst
.operands
[2].isreg
)
10960 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10961 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10967 Rm
= inst
.operands
[2].reg
;
10968 reject_bad_reg (Rm
);
10970 constraint (inst
.operands
[2].shifted
10971 && inst
.operands
[2].immisreg
,
10972 _("shift must be constant"));
10973 encode_thumb32_shifted_operand (2);
10980 unsigned Rd
, Rn
, Rm
;
10982 Rd
= inst
.operands
[0].reg
;
10983 Rn
= inst
.operands
[1].reg
;
10984 Rm
= inst
.operands
[2].reg
;
10986 reject_bad_reg (Rd
);
10987 reject_bad_reg (Rn
);
10988 reject_bad_reg (Rm
);
10990 inst
.instruction
|= Rd
<< 8;
10991 inst
.instruction
|= Rn
<< 16;
10992 inst
.instruction
|= Rm
;
10993 if (inst
.operands
[3].present
)
10995 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10996 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10997 _("expression too complex"));
10998 inst
.instruction
|= (val
& 0x1c) << 10;
10999 inst
.instruction
|= (val
& 0x03) << 6;
11006 if (!inst
.operands
[3].present
)
11010 inst
.instruction
&= ~0x00000020;
11012 /* PR 10168. Swap the Rm and Rn registers. */
11013 Rtmp
= inst
.operands
[1].reg
;
11014 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11015 inst
.operands
[2].reg
= Rtmp
;
11023 if (inst
.operands
[0].immisreg
)
11024 reject_bad_reg (inst
.operands
[0].imm
);
11026 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11030 do_t_push_pop (void)
11034 constraint (inst
.operands
[0].writeback
,
11035 _("push/pop do not support {reglist}^"));
11036 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11037 _("expression too complex"));
11039 mask
= inst
.operands
[0].imm
;
11040 if ((mask
& ~0xff) == 0)
11041 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11042 else if ((inst
.instruction
== T_MNEM_push
11043 && (mask
& ~0xff) == 1 << REG_LR
)
11044 || (inst
.instruction
== T_MNEM_pop
11045 && (mask
& ~0xff) == 1 << REG_PC
))
11047 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11048 inst
.instruction
|= THUMB_PP_PC_LR
;
11049 inst
.instruction
|= mask
& 0xff;
11051 else if (unified_syntax
)
11053 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11054 encode_thumb2_ldmstm (13, mask
, TRUE
);
11058 inst
.error
= _("invalid register list to push/pop instruction");
11068 Rd
= inst
.operands
[0].reg
;
11069 Rm
= inst
.operands
[1].reg
;
11071 reject_bad_reg (Rd
);
11072 reject_bad_reg (Rm
);
11074 inst
.instruction
|= Rd
<< 8;
11075 inst
.instruction
|= Rm
<< 16;
11076 inst
.instruction
|= Rm
;
11084 Rd
= inst
.operands
[0].reg
;
11085 Rm
= inst
.operands
[1].reg
;
11087 reject_bad_reg (Rd
);
11088 reject_bad_reg (Rm
);
11090 if (Rd
<= 7 && Rm
<= 7
11091 && inst
.size_req
!= 4)
11093 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11094 inst
.instruction
|= Rd
;
11095 inst
.instruction
|= Rm
<< 3;
11097 else if (unified_syntax
)
11099 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11100 inst
.instruction
|= Rd
<< 8;
11101 inst
.instruction
|= Rm
<< 16;
11102 inst
.instruction
|= Rm
;
11105 inst
.error
= BAD_HIREG
;
11113 Rd
= inst
.operands
[0].reg
;
11114 Rm
= inst
.operands
[1].reg
;
11116 reject_bad_reg (Rd
);
11117 reject_bad_reg (Rm
);
11119 inst
.instruction
|= Rd
<< 8;
11120 inst
.instruction
|= Rm
;
11128 Rd
= inst
.operands
[0].reg
;
11129 Rs
= (inst
.operands
[1].present
11130 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11131 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11133 reject_bad_reg (Rd
);
11134 reject_bad_reg (Rs
);
11135 if (inst
.operands
[2].isreg
)
11136 reject_bad_reg (inst
.operands
[2].reg
);
11138 inst
.instruction
|= Rd
<< 8;
11139 inst
.instruction
|= Rs
<< 16;
11140 if (!inst
.operands
[2].isreg
)
11142 bfd_boolean narrow
;
11144 if ((inst
.instruction
& 0x00100000) != 0)
11145 narrow
= !in_it_block ();
11147 narrow
= in_it_block ();
11149 if (Rd
> 7 || Rs
> 7)
11152 if (inst
.size_req
== 4 || !unified_syntax
)
11155 if (inst
.reloc
.exp
.X_op
!= O_constant
11156 || inst
.reloc
.exp
.X_add_number
!= 0)
11159 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11160 relaxation, but it doesn't seem worth the hassle. */
11163 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11164 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11165 inst
.instruction
|= Rs
<< 3;
11166 inst
.instruction
|= Rd
;
11170 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11171 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11175 encode_thumb32_shifted_operand (2);
11181 set_it_insn_type (OUTSIDE_IT_INSN
);
11182 if (inst
.operands
[0].imm
)
11183 inst
.instruction
|= 0x8;
11189 if (!inst
.operands
[1].present
)
11190 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11192 if (unified_syntax
)
11194 bfd_boolean narrow
;
11197 switch (inst
.instruction
)
11200 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11202 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11204 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11206 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11210 if (THUMB_SETS_FLAGS (inst
.instruction
))
11211 narrow
= !in_it_block ();
11213 narrow
= in_it_block ();
11214 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11216 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11218 if (inst
.operands
[2].isreg
11219 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11220 || inst
.operands
[2].reg
> 7))
11222 if (inst
.size_req
== 4)
11225 reject_bad_reg (inst
.operands
[0].reg
);
11226 reject_bad_reg (inst
.operands
[1].reg
);
11230 if (inst
.operands
[2].isreg
)
11232 reject_bad_reg (inst
.operands
[2].reg
);
11233 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11234 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11235 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11236 inst
.instruction
|= inst
.operands
[2].reg
;
11240 inst
.operands
[1].shifted
= 1;
11241 inst
.operands
[1].shift_kind
= shift_kind
;
11242 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11243 ? T_MNEM_movs
: T_MNEM_mov
);
11244 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11245 encode_thumb32_shifted_operand (1);
11246 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11247 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11252 if (inst
.operands
[2].isreg
)
11254 switch (shift_kind
)
11256 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11257 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11258 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11259 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11263 inst
.instruction
|= inst
.operands
[0].reg
;
11264 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11268 switch (shift_kind
)
11270 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11271 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11272 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11275 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11276 inst
.instruction
|= inst
.operands
[0].reg
;
11277 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11283 constraint (inst
.operands
[0].reg
> 7
11284 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11285 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11287 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11289 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11290 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11291 _("source1 and dest must be same register"));
11293 switch (inst
.instruction
)
11295 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11296 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11297 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11298 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11302 inst
.instruction
|= inst
.operands
[0].reg
;
11303 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11307 switch (inst
.instruction
)
11309 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11310 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11311 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11312 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11315 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11316 inst
.instruction
|= inst
.operands
[0].reg
;
11317 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11325 unsigned Rd
, Rn
, Rm
;
11327 Rd
= inst
.operands
[0].reg
;
11328 Rn
= inst
.operands
[1].reg
;
11329 Rm
= inst
.operands
[2].reg
;
11331 reject_bad_reg (Rd
);
11332 reject_bad_reg (Rn
);
11333 reject_bad_reg (Rm
);
11335 inst
.instruction
|= Rd
<< 8;
11336 inst
.instruction
|= Rn
<< 16;
11337 inst
.instruction
|= Rm
;
11343 unsigned Rd
, Rn
, Rm
;
11345 Rd
= inst
.operands
[0].reg
;
11346 Rm
= inst
.operands
[1].reg
;
11347 Rn
= inst
.operands
[2].reg
;
11349 reject_bad_reg (Rd
);
11350 reject_bad_reg (Rn
);
11351 reject_bad_reg (Rm
);
11353 inst
.instruction
|= Rd
<< 8;
11354 inst
.instruction
|= Rn
<< 16;
11355 inst
.instruction
|= Rm
;
11361 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11362 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11363 _("SMC is not permitted on this architecture"));
11364 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11365 _("expression too complex"));
11366 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11367 inst
.instruction
|= (value
& 0xf000) >> 12;
11368 inst
.instruction
|= (value
& 0x0ff0);
11369 inst
.instruction
|= (value
& 0x000f) << 16;
11373 do_t_ssat_usat (int bias
)
11377 Rd
= inst
.operands
[0].reg
;
11378 Rn
= inst
.operands
[2].reg
;
11380 reject_bad_reg (Rd
);
11381 reject_bad_reg (Rn
);
11383 inst
.instruction
|= Rd
<< 8;
11384 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11385 inst
.instruction
|= Rn
<< 16;
11387 if (inst
.operands
[3].present
)
11389 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11391 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11393 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11394 _("expression too complex"));
11396 if (shift_amount
!= 0)
11398 constraint (shift_amount
> 31,
11399 _("shift expression is too large"));
11401 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11402 inst
.instruction
|= 0x00200000; /* sh bit. */
11404 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11405 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11413 do_t_ssat_usat (1);
11421 Rd
= inst
.operands
[0].reg
;
11422 Rn
= inst
.operands
[2].reg
;
11424 reject_bad_reg (Rd
);
11425 reject_bad_reg (Rn
);
11427 inst
.instruction
|= Rd
<< 8;
11428 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11429 inst
.instruction
|= Rn
<< 16;
11435 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11436 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11437 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11438 || inst
.operands
[2].negative
,
11441 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11443 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11444 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11445 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11446 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11452 if (!inst
.operands
[2].present
)
11453 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11455 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11456 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11457 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11460 inst
.instruction
|= inst
.operands
[0].reg
;
11461 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11462 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11463 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11469 unsigned Rd
, Rn
, Rm
;
11471 Rd
= inst
.operands
[0].reg
;
11472 Rn
= inst
.operands
[1].reg
;
11473 Rm
= inst
.operands
[2].reg
;
11475 reject_bad_reg (Rd
);
11476 reject_bad_reg (Rn
);
11477 reject_bad_reg (Rm
);
11479 inst
.instruction
|= Rd
<< 8;
11480 inst
.instruction
|= Rn
<< 16;
11481 inst
.instruction
|= Rm
;
11482 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11490 Rd
= inst
.operands
[0].reg
;
11491 Rm
= inst
.operands
[1].reg
;
11493 reject_bad_reg (Rd
);
11494 reject_bad_reg (Rm
);
11496 if (inst
.instruction
<= 0xffff
11497 && inst
.size_req
!= 4
11498 && Rd
<= 7 && Rm
<= 7
11499 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11501 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11502 inst
.instruction
|= Rd
;
11503 inst
.instruction
|= Rm
<< 3;
11505 else if (unified_syntax
)
11507 if (inst
.instruction
<= 0xffff)
11508 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11509 inst
.instruction
|= Rd
<< 8;
11510 inst
.instruction
|= Rm
;
11511 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11515 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11516 _("Thumb encoding does not support rotation"));
11517 constraint (1, BAD_HIREG
);
11524 /* We have to do the following check manually as ARM_EXT_OS only applies
11526 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11528 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
))
11529 as_bad (_("SVC is not permitted on this architecture"));
11530 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11533 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11542 half
= (inst
.instruction
& 0x10) != 0;
11543 set_it_insn_type_last ();
11544 constraint (inst
.operands
[0].immisreg
,
11545 _("instruction requires register index"));
11547 Rn
= inst
.operands
[0].reg
;
11548 Rm
= inst
.operands
[0].imm
;
11550 constraint (Rn
== REG_SP
, BAD_SP
);
11551 reject_bad_reg (Rm
);
11553 constraint (!half
&& inst
.operands
[0].shifted
,
11554 _("instruction does not allow shifted index"));
11555 inst
.instruction
|= (Rn
<< 16) | Rm
;
11561 do_t_ssat_usat (0);
11569 Rd
= inst
.operands
[0].reg
;
11570 Rn
= inst
.operands
[2].reg
;
11572 reject_bad_reg (Rd
);
11573 reject_bad_reg (Rn
);
11575 inst
.instruction
|= Rd
<< 8;
11576 inst
.instruction
|= inst
.operands
[1].imm
;
11577 inst
.instruction
|= Rn
<< 16;
11580 /* Neon instruction encoder helpers. */
11582 /* Encodings for the different types for various Neon opcodes. */
11584 /* An "invalid" code for the following tables. */
11587 struct neon_tab_entry
11590 unsigned float_or_poly
;
11591 unsigned scalar_or_imm
;
11594 /* Map overloaded Neon opcodes to their respective encodings. */
11595 #define NEON_ENC_TAB \
11596 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11597 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11598 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11599 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11600 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11601 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11602 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11603 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11604 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11605 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11606 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11607 /* Register variants of the following two instructions are encoded as
11608 vcge / vcgt with the operands reversed. */ \
11609 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11610 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11611 X(vfma, N_INV, 0x0000c10, N_INV), \
11612 X(vfms, N_INV, 0x0200c10, N_INV), \
11613 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11614 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11615 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11616 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11617 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11618 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11619 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11620 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11621 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11622 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11623 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11624 X(vshl, 0x0000400, N_INV, 0x0800510), \
11625 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11626 X(vand, 0x0000110, N_INV, 0x0800030), \
11627 X(vbic, 0x0100110, N_INV, 0x0800030), \
11628 X(veor, 0x1000110, N_INV, N_INV), \
11629 X(vorn, 0x0300110, N_INV, 0x0800010), \
11630 X(vorr, 0x0200110, N_INV, 0x0800010), \
11631 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11632 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11633 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11634 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11635 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11636 X(vst1, 0x0000000, 0x0800000, N_INV), \
11637 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11638 X(vst2, 0x0000100, 0x0800100, N_INV), \
11639 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11640 X(vst3, 0x0000200, 0x0800200, N_INV), \
11641 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11642 X(vst4, 0x0000300, 0x0800300, N_INV), \
11643 X(vmovn, 0x1b20200, N_INV, N_INV), \
11644 X(vtrn, 0x1b20080, N_INV, N_INV), \
11645 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11646 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11647 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11648 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11649 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11650 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11651 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11652 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11653 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11654 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11655 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11659 #define X(OPC,I,F,S) N_MNEM_##OPC
11664 static const struct neon_tab_entry neon_enc_tab
[] =
11666 #define X(OPC,I,F,S) { (I), (F), (S) }
11671 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11672 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11673 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11674 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11675 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11676 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11677 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11678 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11679 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11680 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11681 #define NEON_ENC_SINGLE_(X) \
11682 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11683 #define NEON_ENC_DOUBLE_(X) \
11684 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11686 #define NEON_ENCODE(type, inst) \
11689 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11690 inst.is_neon = 1; \
11694 #define check_neon_suffixes \
11697 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11699 as_bad (_("invalid neon suffix for non neon instruction")); \
11705 /* Define shapes for instruction operands. The following mnemonic characters
11706 are used in this table:
11708 F - VFP S<n> register
11709 D - Neon D<n> register
11710 Q - Neon Q<n> register
11714 L - D<n> register list
11716 This table is used to generate various data:
11717 - enumerations of the form NS_DDR to be used as arguments to
11719 - a table classifying shapes into single, double, quad, mixed.
11720 - a table used to drive neon_select_shape. */
11722 #define NEON_SHAPE_DEF \
11723 X(3, (D, D, D), DOUBLE), \
11724 X(3, (Q, Q, Q), QUAD), \
11725 X(3, (D, D, I), DOUBLE), \
11726 X(3, (Q, Q, I), QUAD), \
11727 X(3, (D, D, S), DOUBLE), \
11728 X(3, (Q, Q, S), QUAD), \
11729 X(2, (D, D), DOUBLE), \
11730 X(2, (Q, Q), QUAD), \
11731 X(2, (D, S), DOUBLE), \
11732 X(2, (Q, S), QUAD), \
11733 X(2, (D, R), DOUBLE), \
11734 X(2, (Q, R), QUAD), \
11735 X(2, (D, I), DOUBLE), \
11736 X(2, (Q, I), QUAD), \
11737 X(3, (D, L, D), DOUBLE), \
11738 X(2, (D, Q), MIXED), \
11739 X(2, (Q, D), MIXED), \
11740 X(3, (D, Q, I), MIXED), \
11741 X(3, (Q, D, I), MIXED), \
11742 X(3, (Q, D, D), MIXED), \
11743 X(3, (D, Q, Q), MIXED), \
11744 X(3, (Q, Q, D), MIXED), \
11745 X(3, (Q, D, S), MIXED), \
11746 X(3, (D, Q, S), MIXED), \
11747 X(4, (D, D, D, I), DOUBLE), \
11748 X(4, (Q, Q, Q, I), QUAD), \
11749 X(2, (F, F), SINGLE), \
11750 X(3, (F, F, F), SINGLE), \
11751 X(2, (F, I), SINGLE), \
11752 X(2, (F, D), MIXED), \
11753 X(2, (D, F), MIXED), \
11754 X(3, (F, F, I), MIXED), \
11755 X(4, (R, R, F, F), SINGLE), \
11756 X(4, (F, F, R, R), SINGLE), \
11757 X(3, (D, R, R), DOUBLE), \
11758 X(3, (R, R, D), DOUBLE), \
11759 X(2, (S, R), SINGLE), \
11760 X(2, (R, S), SINGLE), \
11761 X(2, (F, R), SINGLE), \
11762 X(2, (R, F), SINGLE)
11764 #define S2(A,B) NS_##A##B
11765 #define S3(A,B,C) NS_##A##B##C
11766 #define S4(A,B,C,D) NS_##A##B##C##D
11768 #define X(N, L, C) S##N L
11781 enum neon_shape_class
11789 #define X(N, L, C) SC_##C
11791 static enum neon_shape_class neon_shape_class
[] =
11809 /* Register widths of above. */
11810 static unsigned neon_shape_el_size
[] =
11821 struct neon_shape_info
11824 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11827 #define S2(A,B) { SE_##A, SE_##B }
11828 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11829 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11831 #define X(N, L, C) { N, S##N L }
11833 static struct neon_shape_info neon_shape_tab
[] =
11843 /* Bit masks used in type checking given instructions.
11844 'N_EQK' means the type must be the same as (or based on in some way) the key
11845 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11846 set, various other bits can be set as well in order to modify the meaning of
11847 the type constraint. */
11849 enum neon_type_mask
11872 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11873 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11874 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11875 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11876 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11877 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11878 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11879 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11880 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11881 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11883 N_MAX_NONSPECIAL
= N_F64
11886 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11888 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11889 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11890 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11891 #define N_SUF_32 (N_SU_32 | N_F32)
11892 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11893 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11895 /* Pass this as the first type argument to neon_check_type to ignore types
11897 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11899 /* Select a "shape" for the current instruction (describing register types or
11900 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11901 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11902 function of operand parsing, so this function doesn't need to be called.
11903 Shapes should be listed in order of decreasing length. */
11905 static enum neon_shape
11906 neon_select_shape (enum neon_shape shape
, ...)
11909 enum neon_shape first_shape
= shape
;
11911 /* Fix missing optional operands. FIXME: we don't know at this point how
11912 many arguments we should have, so this makes the assumption that we have
11913 > 1. This is true of all current Neon opcodes, I think, but may not be
11914 true in the future. */
11915 if (!inst
.operands
[1].present
)
11916 inst
.operands
[1] = inst
.operands
[0];
11918 va_start (ap
, shape
);
11920 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11925 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11927 if (!inst
.operands
[j
].present
)
11933 switch (neon_shape_tab
[shape
].el
[j
])
11936 if (!(inst
.operands
[j
].isreg
11937 && inst
.operands
[j
].isvec
11938 && inst
.operands
[j
].issingle
11939 && !inst
.operands
[j
].isquad
))
11944 if (!(inst
.operands
[j
].isreg
11945 && inst
.operands
[j
].isvec
11946 && !inst
.operands
[j
].isquad
11947 && !inst
.operands
[j
].issingle
))
11952 if (!(inst
.operands
[j
].isreg
11953 && !inst
.operands
[j
].isvec
))
11958 if (!(inst
.operands
[j
].isreg
11959 && inst
.operands
[j
].isvec
11960 && inst
.operands
[j
].isquad
11961 && !inst
.operands
[j
].issingle
))
11966 if (!(!inst
.operands
[j
].isreg
11967 && !inst
.operands
[j
].isscalar
))
11972 if (!(!inst
.operands
[j
].isreg
11973 && inst
.operands
[j
].isscalar
))
11989 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11990 first_error (_("invalid instruction shape"));
11995 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11996 means the Q bit should be set). */
11999 neon_quad (enum neon_shape shape
)
12001 return neon_shape_class
[shape
] == SC_QUAD
;
12005 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12008 /* Allow modification to be made to types which are constrained to be
12009 based on the key element, based on bits set alongside N_EQK. */
12010 if ((typebits
& N_EQK
) != 0)
12012 if ((typebits
& N_HLF
) != 0)
12014 else if ((typebits
& N_DBL
) != 0)
12016 if ((typebits
& N_SGN
) != 0)
12017 *g_type
= NT_signed
;
12018 else if ((typebits
& N_UNS
) != 0)
12019 *g_type
= NT_unsigned
;
12020 else if ((typebits
& N_INT
) != 0)
12021 *g_type
= NT_integer
;
12022 else if ((typebits
& N_FLT
) != 0)
12023 *g_type
= NT_float
;
12024 else if ((typebits
& N_SIZ
) != 0)
12025 *g_type
= NT_untyped
;
12029 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12030 operand type, i.e. the single type specified in a Neon instruction when it
12031 is the only one given. */
12033 static struct neon_type_el
12034 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12036 struct neon_type_el dest
= *key
;
12038 gas_assert ((thisarg
& N_EQK
) != 0);
12040 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12045 /* Convert Neon type and size into compact bitmask representation. */
12047 static enum neon_type_mask
12048 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12055 case 8: return N_8
;
12056 case 16: return N_16
;
12057 case 32: return N_32
;
12058 case 64: return N_64
;
12066 case 8: return N_I8
;
12067 case 16: return N_I16
;
12068 case 32: return N_I32
;
12069 case 64: return N_I64
;
12077 case 16: return N_F16
;
12078 case 32: return N_F32
;
12079 case 64: return N_F64
;
12087 case 8: return N_P8
;
12088 case 16: return N_P16
;
12096 case 8: return N_S8
;
12097 case 16: return N_S16
;
12098 case 32: return N_S32
;
12099 case 64: return N_S64
;
12107 case 8: return N_U8
;
12108 case 16: return N_U16
;
12109 case 32: return N_U32
;
12110 case 64: return N_U64
;
12121 /* Convert compact Neon bitmask type representation to a type and size. Only
12122 handles the case where a single bit is set in the mask. */
12125 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12126 enum neon_type_mask mask
)
12128 if ((mask
& N_EQK
) != 0)
12131 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12133 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12135 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12137 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12142 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12144 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12145 *type
= NT_unsigned
;
12146 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12147 *type
= NT_integer
;
12148 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12149 *type
= NT_untyped
;
12150 else if ((mask
& (N_P8
| N_P16
)) != 0)
12152 else if ((mask
& (N_F32
| N_F64
)) != 0)
12160 /* Modify a bitmask of allowed types. This is only needed for type
12164 modify_types_allowed (unsigned allowed
, unsigned mods
)
12167 enum neon_el_type type
;
12173 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12175 if (el_type_of_type_chk (&type
, &size
,
12176 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12178 neon_modify_type_size (mods
, &type
, &size
);
12179 destmask
|= type_chk_of_el_type (type
, size
);
12186 /* Check type and return type classification.
12187 The manual states (paraphrase): If one datatype is given, it indicates the
12189 - the second operand, if there is one
12190 - the operand, if there is no second operand
12191 - the result, if there are no operands.
12192 This isn't quite good enough though, so we use a concept of a "key" datatype
12193 which is set on a per-instruction basis, which is the one which matters when
12194 only one data type is written.
12195 Note: this function has side-effects (e.g. filling in missing operands). All
12196 Neon instructions should call it before performing bit encoding. */
12198 static struct neon_type_el
12199 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12202 unsigned i
, pass
, key_el
= 0;
12203 unsigned types
[NEON_MAX_TYPE_ELS
];
12204 enum neon_el_type k_type
= NT_invtype
;
12205 unsigned k_size
= -1u;
12206 struct neon_type_el badtype
= {NT_invtype
, -1};
12207 unsigned key_allowed
= 0;
12209 /* Optional registers in Neon instructions are always (not) in operand 1.
12210 Fill in the missing operand here, if it was omitted. */
12211 if (els
> 1 && !inst
.operands
[1].present
)
12212 inst
.operands
[1] = inst
.operands
[0];
12214 /* Suck up all the varargs. */
12216 for (i
= 0; i
< els
; i
++)
12218 unsigned thisarg
= va_arg (ap
, unsigned);
12219 if (thisarg
== N_IGNORE_TYPE
)
12224 types
[i
] = thisarg
;
12225 if ((thisarg
& N_KEY
) != 0)
12230 if (inst
.vectype
.elems
> 0)
12231 for (i
= 0; i
< els
; i
++)
12232 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12234 first_error (_("types specified in both the mnemonic and operands"));
12238 /* Duplicate inst.vectype elements here as necessary.
12239 FIXME: No idea if this is exactly the same as the ARM assembler,
12240 particularly when an insn takes one register and one non-register
12242 if (inst
.vectype
.elems
== 1 && els
> 1)
12245 inst
.vectype
.elems
= els
;
12246 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12247 for (j
= 0; j
< els
; j
++)
12249 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12252 else if (inst
.vectype
.elems
== 0 && els
> 0)
12255 /* No types were given after the mnemonic, so look for types specified
12256 after each operand. We allow some flexibility here; as long as the
12257 "key" operand has a type, we can infer the others. */
12258 for (j
= 0; j
< els
; j
++)
12259 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12260 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12262 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12264 for (j
= 0; j
< els
; j
++)
12265 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12266 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12271 first_error (_("operand types can't be inferred"));
12275 else if (inst
.vectype
.elems
!= els
)
12277 first_error (_("type specifier has the wrong number of parts"));
12281 for (pass
= 0; pass
< 2; pass
++)
12283 for (i
= 0; i
< els
; i
++)
12285 unsigned thisarg
= types
[i
];
12286 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12287 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12288 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12289 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12291 /* Decay more-specific signed & unsigned types to sign-insensitive
12292 integer types if sign-specific variants are unavailable. */
12293 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12294 && (types_allowed
& N_SU_ALL
) == 0)
12295 g_type
= NT_integer
;
12297 /* If only untyped args are allowed, decay any more specific types to
12298 them. Some instructions only care about signs for some element
12299 sizes, so handle that properly. */
12300 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12301 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12302 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12303 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12304 g_type
= NT_untyped
;
12308 if ((thisarg
& N_KEY
) != 0)
12312 key_allowed
= thisarg
& ~N_KEY
;
12317 if ((thisarg
& N_VFP
) != 0)
12319 enum neon_shape_el regshape
;
12320 unsigned regwidth
, match
;
12322 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12325 first_error (_("invalid instruction shape"));
12328 regshape
= neon_shape_tab
[ns
].el
[i
];
12329 regwidth
= neon_shape_el_size
[regshape
];
12331 /* In VFP mode, operands must match register widths. If we
12332 have a key operand, use its width, else use the width of
12333 the current operand. */
12339 if (regwidth
!= match
)
12341 first_error (_("operand size must match register width"));
12346 if ((thisarg
& N_EQK
) == 0)
12348 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12350 if ((given_type
& types_allowed
) == 0)
12352 first_error (_("bad type in Neon instruction"));
12358 enum neon_el_type mod_k_type
= k_type
;
12359 unsigned mod_k_size
= k_size
;
12360 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12361 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12363 first_error (_("inconsistent types in Neon instruction"));
12371 return inst
.vectype
.el
[key_el
];
12374 /* Neon-style VFP instruction forwarding. */
12376 /* Thumb VFP instructions have 0xE in the condition field. */
12379 do_vfp_cond_or_thumb (void)
12384 inst
.instruction
|= 0xe0000000;
12386 inst
.instruction
|= inst
.cond
<< 28;
12389 /* Look up and encode a simple mnemonic, for use as a helper function for the
12390 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12391 etc. It is assumed that operand parsing has already been done, and that the
12392 operands are in the form expected by the given opcode (this isn't necessarily
12393 the same as the form in which they were parsed, hence some massaging must
12394 take place before this function is called).
12395 Checks current arch version against that in the looked-up opcode. */
12398 do_vfp_nsyn_opcode (const char *opname
)
12400 const struct asm_opcode
*opcode
;
12402 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12407 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12408 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12415 inst
.instruction
= opcode
->tvalue
;
12416 opcode
->tencode ();
12420 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12421 opcode
->aencode ();
12426 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12428 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12433 do_vfp_nsyn_opcode ("fadds");
12435 do_vfp_nsyn_opcode ("fsubs");
12440 do_vfp_nsyn_opcode ("faddd");
12442 do_vfp_nsyn_opcode ("fsubd");
12446 /* Check operand types to see if this is a VFP instruction, and if so call
12450 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12452 enum neon_shape rs
;
12453 struct neon_type_el et
;
12458 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12459 et
= neon_check_type (2, rs
,
12460 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12464 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12465 et
= neon_check_type (3, rs
,
12466 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12473 if (et
.type
!= NT_invtype
)
12484 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12486 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12491 do_vfp_nsyn_opcode ("fmacs");
12493 do_vfp_nsyn_opcode ("fnmacs");
12498 do_vfp_nsyn_opcode ("fmacd");
12500 do_vfp_nsyn_opcode ("fnmacd");
12505 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12507 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12512 do_vfp_nsyn_opcode ("ffmas");
12514 do_vfp_nsyn_opcode ("ffnmas");
12519 do_vfp_nsyn_opcode ("ffmad");
12521 do_vfp_nsyn_opcode ("ffnmad");
12526 do_vfp_nsyn_mul (enum neon_shape rs
)
12529 do_vfp_nsyn_opcode ("fmuls");
12531 do_vfp_nsyn_opcode ("fmuld");
12535 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12537 int is_neg
= (inst
.instruction
& 0x80) != 0;
12538 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12543 do_vfp_nsyn_opcode ("fnegs");
12545 do_vfp_nsyn_opcode ("fabss");
12550 do_vfp_nsyn_opcode ("fnegd");
12552 do_vfp_nsyn_opcode ("fabsd");
12556 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12557 insns belong to Neon, and are handled elsewhere. */
12560 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12562 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12566 do_vfp_nsyn_opcode ("fldmdbs");
12568 do_vfp_nsyn_opcode ("fldmias");
12573 do_vfp_nsyn_opcode ("fstmdbs");
12575 do_vfp_nsyn_opcode ("fstmias");
12580 do_vfp_nsyn_sqrt (void)
12582 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12583 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12586 do_vfp_nsyn_opcode ("fsqrts");
12588 do_vfp_nsyn_opcode ("fsqrtd");
12592 do_vfp_nsyn_div (void)
12594 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12595 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12596 N_F32
| N_F64
| N_KEY
| N_VFP
);
12599 do_vfp_nsyn_opcode ("fdivs");
12601 do_vfp_nsyn_opcode ("fdivd");
12605 do_vfp_nsyn_nmul (void)
12607 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12608 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12609 N_F32
| N_F64
| N_KEY
| N_VFP
);
12613 NEON_ENCODE (SINGLE
, inst
);
12614 do_vfp_sp_dyadic ();
12618 NEON_ENCODE (DOUBLE
, inst
);
12619 do_vfp_dp_rd_rn_rm ();
12621 do_vfp_cond_or_thumb ();
12625 do_vfp_nsyn_cmp (void)
12627 if (inst
.operands
[1].isreg
)
12629 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12630 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12634 NEON_ENCODE (SINGLE
, inst
);
12635 do_vfp_sp_monadic ();
12639 NEON_ENCODE (DOUBLE
, inst
);
12640 do_vfp_dp_rd_rm ();
12645 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12646 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12648 switch (inst
.instruction
& 0x0fffffff)
12651 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12654 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12662 NEON_ENCODE (SINGLE
, inst
);
12663 do_vfp_sp_compare_z ();
12667 NEON_ENCODE (DOUBLE
, inst
);
12671 do_vfp_cond_or_thumb ();
12675 nsyn_insert_sp (void)
12677 inst
.operands
[1] = inst
.operands
[0];
12678 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12679 inst
.operands
[0].reg
= REG_SP
;
12680 inst
.operands
[0].isreg
= 1;
12681 inst
.operands
[0].writeback
= 1;
12682 inst
.operands
[0].present
= 1;
12686 do_vfp_nsyn_push (void)
12689 if (inst
.operands
[1].issingle
)
12690 do_vfp_nsyn_opcode ("fstmdbs");
12692 do_vfp_nsyn_opcode ("fstmdbd");
12696 do_vfp_nsyn_pop (void)
12699 if (inst
.operands
[1].issingle
)
12700 do_vfp_nsyn_opcode ("fldmias");
12702 do_vfp_nsyn_opcode ("fldmiad");
12705 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12706 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12709 neon_dp_fixup (struct arm_it
* insn
)
12711 unsigned int i
= insn
->instruction
;
12716 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12727 insn
->instruction
= i
;
12730 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12734 neon_logbits (unsigned x
)
12736 return ffs (x
) - 4;
12739 #define LOW4(R) ((R) & 0xf)
12740 #define HI1(R) (((R) >> 4) & 1)
12742 /* Encode insns with bit pattern:
12744 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12745 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12747 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12748 different meaning for some instruction. */
12751 neon_three_same (int isquad
, int ubit
, int size
)
12753 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12754 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12755 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12756 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12757 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12758 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12759 inst
.instruction
|= (isquad
!= 0) << 6;
12760 inst
.instruction
|= (ubit
!= 0) << 24;
12762 inst
.instruction
|= neon_logbits (size
) << 20;
12764 neon_dp_fixup (&inst
);
12767 /* Encode instructions of the form:
12769 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12770 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12772 Don't write size if SIZE == -1. */
12775 neon_two_same (int qbit
, int ubit
, int size
)
12777 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12778 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12779 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12780 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12781 inst
.instruction
|= (qbit
!= 0) << 6;
12782 inst
.instruction
|= (ubit
!= 0) << 24;
12785 inst
.instruction
|= neon_logbits (size
) << 18;
12787 neon_dp_fixup (&inst
);
12790 /* Neon instruction encoders, in approximate order of appearance. */
12793 do_neon_dyadic_i_su (void)
12795 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12796 struct neon_type_el et
= neon_check_type (3, rs
,
12797 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12798 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12802 do_neon_dyadic_i64_su (void)
12804 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12805 struct neon_type_el et
= neon_check_type (3, rs
,
12806 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12807 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12811 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12814 unsigned size
= et
.size
>> 3;
12815 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12816 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12817 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12818 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12819 inst
.instruction
|= (isquad
!= 0) << 6;
12820 inst
.instruction
|= immbits
<< 16;
12821 inst
.instruction
|= (size
>> 3) << 7;
12822 inst
.instruction
|= (size
& 0x7) << 19;
12824 inst
.instruction
|= (uval
!= 0) << 24;
12826 neon_dp_fixup (&inst
);
12830 do_neon_shl_imm (void)
12832 if (!inst
.operands
[2].isreg
)
12834 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12835 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12836 NEON_ENCODE (IMMED
, inst
);
12837 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12841 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12842 struct neon_type_el et
= neon_check_type (3, rs
,
12843 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12846 /* VSHL/VQSHL 3-register variants have syntax such as:
12848 whereas other 3-register operations encoded by neon_three_same have
12851 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12853 tmp
= inst
.operands
[2].reg
;
12854 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12855 inst
.operands
[1].reg
= tmp
;
12856 NEON_ENCODE (INTEGER
, inst
);
12857 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12862 do_neon_qshl_imm (void)
12864 if (!inst
.operands
[2].isreg
)
12866 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12867 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12869 NEON_ENCODE (IMMED
, inst
);
12870 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12871 inst
.operands
[2].imm
);
12875 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12876 struct neon_type_el et
= neon_check_type (3, rs
,
12877 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12880 /* See note in do_neon_shl_imm. */
12881 tmp
= inst
.operands
[2].reg
;
12882 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12883 inst
.operands
[1].reg
= tmp
;
12884 NEON_ENCODE (INTEGER
, inst
);
12885 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12890 do_neon_rshl (void)
12892 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12893 struct neon_type_el et
= neon_check_type (3, rs
,
12894 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12897 tmp
= inst
.operands
[2].reg
;
12898 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12899 inst
.operands
[1].reg
= tmp
;
12900 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12904 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12906 /* Handle .I8 pseudo-instructions. */
12909 /* Unfortunately, this will make everything apart from zero out-of-range.
12910 FIXME is this the intended semantics? There doesn't seem much point in
12911 accepting .I8 if so. */
12912 immediate
|= immediate
<< 8;
12918 if (immediate
== (immediate
& 0x000000ff))
12920 *immbits
= immediate
;
12923 else if (immediate
== (immediate
& 0x0000ff00))
12925 *immbits
= immediate
>> 8;
12928 else if (immediate
== (immediate
& 0x00ff0000))
12930 *immbits
= immediate
>> 16;
12933 else if (immediate
== (immediate
& 0xff000000))
12935 *immbits
= immediate
>> 24;
12938 if ((immediate
& 0xffff) != (immediate
>> 16))
12939 goto bad_immediate
;
12940 immediate
&= 0xffff;
12943 if (immediate
== (immediate
& 0x000000ff))
12945 *immbits
= immediate
;
12948 else if (immediate
== (immediate
& 0x0000ff00))
12950 *immbits
= immediate
>> 8;
12955 first_error (_("immediate value out of range"));
12959 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12963 neon_bits_same_in_bytes (unsigned imm
)
12965 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12966 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12967 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12968 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12971 /* For immediate of above form, return 0bABCD. */
12974 neon_squash_bits (unsigned imm
)
12976 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12977 | ((imm
& 0x01000000) >> 21);
12980 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12983 neon_qfloat_bits (unsigned imm
)
12985 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12988 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12989 the instruction. *OP is passed as the initial value of the op field, and
12990 may be set to a different value depending on the constant (i.e.
12991 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12992 MVN). If the immediate looks like a repeated pattern then also
12993 try smaller element sizes. */
12996 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12997 unsigned *immbits
, int *op
, int size
,
12998 enum neon_el_type type
)
13000 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13002 if (type
== NT_float
&& !float_p
)
13005 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13007 if (size
!= 32 || *op
== 1)
13009 *immbits
= neon_qfloat_bits (immlo
);
13015 if (neon_bits_same_in_bytes (immhi
)
13016 && neon_bits_same_in_bytes (immlo
))
13020 *immbits
= (neon_squash_bits (immhi
) << 4)
13021 | neon_squash_bits (immlo
);
13026 if (immhi
!= immlo
)
13032 if (immlo
== (immlo
& 0x000000ff))
13037 else if (immlo
== (immlo
& 0x0000ff00))
13039 *immbits
= immlo
>> 8;
13042 else if (immlo
== (immlo
& 0x00ff0000))
13044 *immbits
= immlo
>> 16;
13047 else if (immlo
== (immlo
& 0xff000000))
13049 *immbits
= immlo
>> 24;
13052 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13054 *immbits
= (immlo
>> 8) & 0xff;
13057 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13059 *immbits
= (immlo
>> 16) & 0xff;
13063 if ((immlo
& 0xffff) != (immlo
>> 16))
13070 if (immlo
== (immlo
& 0x000000ff))
13075 else if (immlo
== (immlo
& 0x0000ff00))
13077 *immbits
= immlo
>> 8;
13081 if ((immlo
& 0xff) != (immlo
>> 8))
13086 if (immlo
== (immlo
& 0x000000ff))
13088 /* Don't allow MVN with 8-bit immediate. */
13098 /* Write immediate bits [7:0] to the following locations:
13100 |28/24|23 19|18 16|15 4|3 0|
13101 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13103 This function is used by VMOV/VMVN/VORR/VBIC. */
13106 neon_write_immbits (unsigned immbits
)
13108 inst
.instruction
|= immbits
& 0xf;
13109 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13110 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13113 /* Invert low-order SIZE bits of XHI:XLO. */
13116 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13118 unsigned immlo
= xlo
? *xlo
: 0;
13119 unsigned immhi
= xhi
? *xhi
: 0;
13124 immlo
= (~immlo
) & 0xff;
13128 immlo
= (~immlo
) & 0xffff;
13132 immhi
= (~immhi
) & 0xffffffff;
13133 /* fall through. */
13136 immlo
= (~immlo
) & 0xffffffff;
13151 do_neon_logic (void)
13153 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13155 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13156 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13157 /* U bit and size field were set as part of the bitmask. */
13158 NEON_ENCODE (INTEGER
, inst
);
13159 neon_three_same (neon_quad (rs
), 0, -1);
13163 const int three_ops_form
= (inst
.operands
[2].present
13164 && !inst
.operands
[2].isreg
);
13165 const int immoperand
= (three_ops_form
? 2 : 1);
13166 enum neon_shape rs
= (three_ops_form
13167 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13168 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13169 struct neon_type_el et
= neon_check_type (2, rs
,
13170 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13171 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13175 if (et
.type
== NT_invtype
)
13178 if (three_ops_form
)
13179 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13180 _("first and second operands shall be the same register"));
13182 NEON_ENCODE (IMMED
, inst
);
13184 immbits
= inst
.operands
[immoperand
].imm
;
13187 /* .i64 is a pseudo-op, so the immediate must be a repeating
13189 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13190 inst
.operands
[immoperand
].reg
: 0))
13192 /* Set immbits to an invalid constant. */
13193 immbits
= 0xdeadbeef;
13200 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13204 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13208 /* Pseudo-instruction for VBIC. */
13209 neon_invert_size (&immbits
, 0, et
.size
);
13210 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13214 /* Pseudo-instruction for VORR. */
13215 neon_invert_size (&immbits
, 0, et
.size
);
13216 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13226 inst
.instruction
|= neon_quad (rs
) << 6;
13227 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13228 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13229 inst
.instruction
|= cmode
<< 8;
13230 neon_write_immbits (immbits
);
13232 neon_dp_fixup (&inst
);
13237 do_neon_bitfield (void)
13239 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13240 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13241 neon_three_same (neon_quad (rs
), 0, -1);
13245 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13248 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13249 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13251 if (et
.type
== NT_float
)
13253 NEON_ENCODE (FLOAT
, inst
);
13254 neon_three_same (neon_quad (rs
), 0, -1);
13258 NEON_ENCODE (INTEGER
, inst
);
13259 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13264 do_neon_dyadic_if_su (void)
13266 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13270 do_neon_dyadic_if_su_d (void)
13272 /* This version only allow D registers, but that constraint is enforced during
13273 operand parsing so we don't need to do anything extra here. */
13274 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13278 do_neon_dyadic_if_i_d (void)
13280 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13281 affected if we specify unsigned args. */
13282 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13285 enum vfp_or_neon_is_neon_bits
13288 NEON_CHECK_ARCH
= 2
13291 /* Call this function if an instruction which may have belonged to the VFP or
13292 Neon instruction sets, but turned out to be a Neon instruction (due to the
13293 operand types involved, etc.). We have to check and/or fix-up a couple of
13296 - Make sure the user hasn't attempted to make a Neon instruction
13298 - Alter the value in the condition code field if necessary.
13299 - Make sure that the arch supports Neon instructions.
13301 Which of these operations take place depends on bits from enum
13302 vfp_or_neon_is_neon_bits.
13304 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13305 current instruction's condition is COND_ALWAYS, the condition field is
13306 changed to inst.uncond_value. This is necessary because instructions shared
13307 between VFP and Neon may be conditional for the VFP variants only, and the
13308 unconditional Neon version must have, e.g., 0xF in the condition field. */
13311 vfp_or_neon_is_neon (unsigned check
)
13313 /* Conditions are always legal in Thumb mode (IT blocks). */
13314 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13316 if (inst
.cond
!= COND_ALWAYS
)
13318 first_error (_(BAD_COND
));
13321 if (inst
.uncond_value
!= -1)
13322 inst
.instruction
|= inst
.uncond_value
<< 28;
13325 if ((check
& NEON_CHECK_ARCH
)
13326 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13328 first_error (_(BAD_FPU
));
13336 do_neon_addsub_if_i (void)
13338 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13341 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13344 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13345 affected if we specify unsigned args. */
13346 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13349 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13351 V<op> A,B (A is operand 0, B is operand 2)
13356 so handle that case specially. */
13359 neon_exchange_operands (void)
13361 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13362 if (inst
.operands
[1].present
)
13364 /* Swap operands[1] and operands[2]. */
13365 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13366 inst
.operands
[1] = inst
.operands
[2];
13367 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13371 inst
.operands
[1] = inst
.operands
[2];
13372 inst
.operands
[2] = inst
.operands
[0];
13377 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13379 if (inst
.operands
[2].isreg
)
13382 neon_exchange_operands ();
13383 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13387 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13388 struct neon_type_el et
= neon_check_type (2, rs
,
13389 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13391 NEON_ENCODE (IMMED
, inst
);
13392 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13393 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13394 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13395 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13396 inst
.instruction
|= neon_quad (rs
) << 6;
13397 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13398 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13400 neon_dp_fixup (&inst
);
13407 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13411 do_neon_cmp_inv (void)
13413 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13419 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13422 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13423 scalars, which are encoded in 5 bits, M : Rm.
13424 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13425 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13429 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13431 unsigned regno
= NEON_SCALAR_REG (scalar
);
13432 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13437 if (regno
> 7 || elno
> 3)
13439 return regno
| (elno
<< 3);
13442 if (regno
> 15 || elno
> 1)
13444 return regno
| (elno
<< 4);
13448 first_error (_("scalar out of range for multiply instruction"));
13454 /* Encode multiply / multiply-accumulate scalar instructions. */
13457 neon_mul_mac (struct neon_type_el et
, int ubit
)
13461 /* Give a more helpful error message if we have an invalid type. */
13462 if (et
.type
== NT_invtype
)
13465 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13466 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13467 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13468 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13469 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13470 inst
.instruction
|= LOW4 (scalar
);
13471 inst
.instruction
|= HI1 (scalar
) << 5;
13472 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13473 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13474 inst
.instruction
|= (ubit
!= 0) << 24;
13476 neon_dp_fixup (&inst
);
13480 do_neon_mac_maybe_scalar (void)
13482 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13485 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13488 if (inst
.operands
[2].isscalar
)
13490 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13491 struct neon_type_el et
= neon_check_type (3, rs
,
13492 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13493 NEON_ENCODE (SCALAR
, inst
);
13494 neon_mul_mac (et
, neon_quad (rs
));
13498 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13499 affected if we specify unsigned args. */
13500 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13505 do_neon_fmac (void)
13507 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13510 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13513 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13519 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13520 struct neon_type_el et
= neon_check_type (3, rs
,
13521 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13522 neon_three_same (neon_quad (rs
), 0, et
.size
);
13525 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13526 same types as the MAC equivalents. The polynomial type for this instruction
13527 is encoded the same as the integer type. */
13532 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13535 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13538 if (inst
.operands
[2].isscalar
)
13539 do_neon_mac_maybe_scalar ();
13541 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13545 do_neon_qdmulh (void)
13547 if (inst
.operands
[2].isscalar
)
13549 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13550 struct neon_type_el et
= neon_check_type (3, rs
,
13551 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13552 NEON_ENCODE (SCALAR
, inst
);
13553 neon_mul_mac (et
, neon_quad (rs
));
13557 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13558 struct neon_type_el et
= neon_check_type (3, rs
,
13559 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13560 NEON_ENCODE (INTEGER
, inst
);
13561 /* The U bit (rounding) comes from bit mask. */
13562 neon_three_same (neon_quad (rs
), 0, et
.size
);
13567 do_neon_fcmp_absolute (void)
13569 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13570 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13571 /* Size field comes from bit mask. */
13572 neon_three_same (neon_quad (rs
), 1, -1);
13576 do_neon_fcmp_absolute_inv (void)
13578 neon_exchange_operands ();
13579 do_neon_fcmp_absolute ();
13583 do_neon_step (void)
13585 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13586 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13587 neon_three_same (neon_quad (rs
), 0, -1);
13591 do_neon_abs_neg (void)
13593 enum neon_shape rs
;
13594 struct neon_type_el et
;
13596 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13599 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13602 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13603 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13607 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13608 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13609 inst
.instruction
|= neon_quad (rs
) << 6;
13610 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13611 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13613 neon_dp_fixup (&inst
);
13619 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13620 struct neon_type_el et
= neon_check_type (2, rs
,
13621 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13622 int imm
= inst
.operands
[2].imm
;
13623 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13624 _("immediate out of range for insert"));
13625 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13631 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13632 struct neon_type_el et
= neon_check_type (2, rs
,
13633 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13634 int imm
= inst
.operands
[2].imm
;
13635 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13636 _("immediate out of range for insert"));
13637 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13641 do_neon_qshlu_imm (void)
13643 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13644 struct neon_type_el et
= neon_check_type (2, rs
,
13645 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13646 int imm
= inst
.operands
[2].imm
;
13647 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13648 _("immediate out of range for shift"));
13649 /* Only encodes the 'U present' variant of the instruction.
13650 In this case, signed types have OP (bit 8) set to 0.
13651 Unsigned types have OP set to 1. */
13652 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13653 /* The rest of the bits are the same as other immediate shifts. */
13654 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13658 do_neon_qmovn (void)
13660 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13661 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13662 /* Saturating move where operands can be signed or unsigned, and the
13663 destination has the same signedness. */
13664 NEON_ENCODE (INTEGER
, inst
);
13665 if (et
.type
== NT_unsigned
)
13666 inst
.instruction
|= 0xc0;
13668 inst
.instruction
|= 0x80;
13669 neon_two_same (0, 1, et
.size
/ 2);
13673 do_neon_qmovun (void)
13675 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13676 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13677 /* Saturating move with unsigned results. Operands must be signed. */
13678 NEON_ENCODE (INTEGER
, inst
);
13679 neon_two_same (0, 1, et
.size
/ 2);
13683 do_neon_rshift_sat_narrow (void)
13685 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13686 or unsigned. If operands are unsigned, results must also be unsigned. */
13687 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13688 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13689 int imm
= inst
.operands
[2].imm
;
13690 /* This gets the bounds check, size encoding and immediate bits calculation
13694 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13695 VQMOVN.I<size> <Dd>, <Qm>. */
13698 inst
.operands
[2].present
= 0;
13699 inst
.instruction
= N_MNEM_vqmovn
;
13704 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13705 _("immediate out of range"));
13706 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13710 do_neon_rshift_sat_narrow_u (void)
13712 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13713 or unsigned. If operands are unsigned, results must also be unsigned. */
13714 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13715 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13716 int imm
= inst
.operands
[2].imm
;
13717 /* This gets the bounds check, size encoding and immediate bits calculation
13721 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13722 VQMOVUN.I<size> <Dd>, <Qm>. */
13725 inst
.operands
[2].present
= 0;
13726 inst
.instruction
= N_MNEM_vqmovun
;
13731 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13732 _("immediate out of range"));
13733 /* FIXME: The manual is kind of unclear about what value U should have in
13734 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13736 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13740 do_neon_movn (void)
13742 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13743 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13744 NEON_ENCODE (INTEGER
, inst
);
13745 neon_two_same (0, 1, et
.size
/ 2);
13749 do_neon_rshift_narrow (void)
13751 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13752 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13753 int imm
= inst
.operands
[2].imm
;
13754 /* This gets the bounds check, size encoding and immediate bits calculation
13758 /* If immediate is zero then we are a pseudo-instruction for
13759 VMOVN.I<size> <Dd>, <Qm> */
13762 inst
.operands
[2].present
= 0;
13763 inst
.instruction
= N_MNEM_vmovn
;
13768 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13769 _("immediate out of range for narrowing operation"));
13770 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13774 do_neon_shll (void)
13776 /* FIXME: Type checking when lengthening. */
13777 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13778 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13779 unsigned imm
= inst
.operands
[2].imm
;
13781 if (imm
== et
.size
)
13783 /* Maximum shift variant. */
13784 NEON_ENCODE (INTEGER
, inst
);
13785 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13786 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13787 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13788 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13789 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13791 neon_dp_fixup (&inst
);
13795 /* A more-specific type check for non-max versions. */
13796 et
= neon_check_type (2, NS_QDI
,
13797 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13798 NEON_ENCODE (IMMED
, inst
);
13799 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13803 /* Check the various types for the VCVT instruction, and return which version
13804 the current instruction is. */
13807 neon_cvt_flavour (enum neon_shape rs
)
13809 #define CVT_VAR(C,X,Y) \
13810 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13811 if (et.type != NT_invtype) \
13813 inst.error = NULL; \
13816 struct neon_type_el et
;
13817 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13818 || rs
== NS_FF
) ? N_VFP
: 0;
13819 /* The instruction versions which take an immediate take one register
13820 argument, which is extended to the width of the full register. Thus the
13821 "source" and "destination" registers must have the same width. Hack that
13822 here by making the size equal to the key (wider, in this case) operand. */
13823 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13825 CVT_VAR (0, N_S32
, N_F32
);
13826 CVT_VAR (1, N_U32
, N_F32
);
13827 CVT_VAR (2, N_F32
, N_S32
);
13828 CVT_VAR (3, N_F32
, N_U32
);
13829 /* Half-precision conversions. */
13830 CVT_VAR (4, N_F32
, N_F16
);
13831 CVT_VAR (5, N_F16
, N_F32
);
13835 /* VFP instructions. */
13836 CVT_VAR (6, N_F32
, N_F64
);
13837 CVT_VAR (7, N_F64
, N_F32
);
13838 CVT_VAR (8, N_S32
, N_F64
| key
);
13839 CVT_VAR (9, N_U32
, N_F64
| key
);
13840 CVT_VAR (10, N_F64
| key
, N_S32
);
13841 CVT_VAR (11, N_F64
| key
, N_U32
);
13842 /* VFP instructions with bitshift. */
13843 CVT_VAR (12, N_F32
| key
, N_S16
);
13844 CVT_VAR (13, N_F32
| key
, N_U16
);
13845 CVT_VAR (14, N_F64
| key
, N_S16
);
13846 CVT_VAR (15, N_F64
| key
, N_U16
);
13847 CVT_VAR (16, N_S16
, N_F32
| key
);
13848 CVT_VAR (17, N_U16
, N_F32
| key
);
13849 CVT_VAR (18, N_S16
, N_F64
| key
);
13850 CVT_VAR (19, N_U16
, N_F64
| key
);
13856 /* Neon-syntax VFP conversions. */
13859 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13861 const char *opname
= 0;
13863 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13865 /* Conversions with immediate bitshift. */
13866 const char *enc
[] =
13890 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13892 opname
= enc
[flavour
];
13893 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13894 _("operands 0 and 1 must be the same register"));
13895 inst
.operands
[1] = inst
.operands
[2];
13896 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13901 /* Conversions without bitshift. */
13902 const char *enc
[] =
13918 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13919 opname
= enc
[flavour
];
13923 do_vfp_nsyn_opcode (opname
);
13927 do_vfp_nsyn_cvtz (void)
13929 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13930 int flavour
= neon_cvt_flavour (rs
);
13931 const char *enc
[] =
13945 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13946 do_vfp_nsyn_opcode (enc
[flavour
]);
13950 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13952 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13953 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13954 int flavour
= neon_cvt_flavour (rs
);
13956 /* PR11109: Handle round-to-zero for VCVT conversions. */
13958 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13959 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13960 && (rs
== NS_FD
|| rs
== NS_FF
))
13962 do_vfp_nsyn_cvtz ();
13966 /* VFP rather than Neon conversions. */
13969 do_vfp_nsyn_cvt (rs
, flavour
);
13979 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13981 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13984 /* Fixed-point conversion with #0 immediate is encoded as an
13985 integer conversion. */
13986 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13988 immbits
= 32 - inst
.operands
[2].imm
;
13989 NEON_ENCODE (IMMED
, inst
);
13991 inst
.instruction
|= enctab
[flavour
];
13992 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13993 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13994 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13995 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13996 inst
.instruction
|= neon_quad (rs
) << 6;
13997 inst
.instruction
|= 1 << 21;
13998 inst
.instruction
|= immbits
<< 16;
14000 neon_dp_fixup (&inst
);
14008 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14010 NEON_ENCODE (INTEGER
, inst
);
14012 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14016 inst
.instruction
|= enctab
[flavour
];
14018 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14019 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14020 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14021 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14022 inst
.instruction
|= neon_quad (rs
) << 6;
14023 inst
.instruction
|= 2 << 18;
14025 neon_dp_fixup (&inst
);
14029 /* Half-precision conversions for Advanced SIMD -- neon. */
14034 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14036 as_bad (_("operand size must match register width"));
14041 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14043 as_bad (_("operand size must match register width"));
14048 inst
.instruction
= 0x3b60600;
14050 inst
.instruction
= 0x3b60700;
14052 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14053 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14054 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14055 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14056 neon_dp_fixup (&inst
);
14060 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14061 do_vfp_nsyn_cvt (rs
, flavour
);
14066 do_neon_cvtr (void)
14068 do_neon_cvt_1 (FALSE
);
14074 do_neon_cvt_1 (TRUE
);
14078 do_neon_cvtb (void)
14080 inst
.instruction
= 0xeb20a40;
14082 /* The sizes are attached to the mnemonic. */
14083 if (inst
.vectype
.el
[0].type
!= NT_invtype
14084 && inst
.vectype
.el
[0].size
== 16)
14085 inst
.instruction
|= 0x00010000;
14087 /* Programmer's syntax: the sizes are attached to the operands. */
14088 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14089 && inst
.operands
[0].vectype
.size
== 16)
14090 inst
.instruction
|= 0x00010000;
14092 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14093 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14094 do_vfp_cond_or_thumb ();
14099 do_neon_cvtt (void)
14102 inst
.instruction
|= 0x80;
14106 neon_move_immediate (void)
14108 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14109 struct neon_type_el et
= neon_check_type (2, rs
,
14110 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14111 unsigned immlo
, immhi
= 0, immbits
;
14112 int op
, cmode
, float_p
;
14114 constraint (et
.type
== NT_invtype
,
14115 _("operand size must be specified for immediate VMOV"));
14117 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14118 op
= (inst
.instruction
& (1 << 5)) != 0;
14120 immlo
= inst
.operands
[1].imm
;
14121 if (inst
.operands
[1].regisimm
)
14122 immhi
= inst
.operands
[1].reg
;
14124 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14125 _("immediate has bits set outside the operand size"));
14127 float_p
= inst
.operands
[1].immisfloat
;
14129 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14130 et
.size
, et
.type
)) == FAIL
)
14132 /* Invert relevant bits only. */
14133 neon_invert_size (&immlo
, &immhi
, et
.size
);
14134 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14135 with one or the other; those cases are caught by
14136 neon_cmode_for_move_imm. */
14138 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14139 &op
, et
.size
, et
.type
)) == FAIL
)
14141 first_error (_("immediate out of range"));
14146 inst
.instruction
&= ~(1 << 5);
14147 inst
.instruction
|= op
<< 5;
14149 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14150 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14151 inst
.instruction
|= neon_quad (rs
) << 6;
14152 inst
.instruction
|= cmode
<< 8;
14154 neon_write_immbits (immbits
);
14160 if (inst
.operands
[1].isreg
)
14162 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14164 NEON_ENCODE (INTEGER
, inst
);
14165 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14166 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14167 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14168 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14169 inst
.instruction
|= neon_quad (rs
) << 6;
14173 NEON_ENCODE (IMMED
, inst
);
14174 neon_move_immediate ();
14177 neon_dp_fixup (&inst
);
14180 /* Encode instructions of form:
14182 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14183 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14186 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14188 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14189 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14190 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14191 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14192 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14193 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14194 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14195 inst
.instruction
|= neon_logbits (size
) << 20;
14197 neon_dp_fixup (&inst
);
14201 do_neon_dyadic_long (void)
14203 /* FIXME: Type checking for lengthening op. */
14204 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14205 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14206 neon_mixed_length (et
, et
.size
);
14210 do_neon_abal (void)
14212 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14213 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14214 neon_mixed_length (et
, et
.size
);
14218 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14220 if (inst
.operands
[2].isscalar
)
14222 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14223 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14224 NEON_ENCODE (SCALAR
, inst
);
14225 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14229 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14230 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14231 NEON_ENCODE (INTEGER
, inst
);
14232 neon_mixed_length (et
, et
.size
);
14237 do_neon_mac_maybe_scalar_long (void)
14239 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14243 do_neon_dyadic_wide (void)
14245 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14246 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14247 neon_mixed_length (et
, et
.size
);
14251 do_neon_dyadic_narrow (void)
14253 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14254 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14255 /* Operand sign is unimportant, and the U bit is part of the opcode,
14256 so force the operand type to integer. */
14257 et
.type
= NT_integer
;
14258 neon_mixed_length (et
, et
.size
/ 2);
14262 do_neon_mul_sat_scalar_long (void)
14264 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14268 do_neon_vmull (void)
14270 if (inst
.operands
[2].isscalar
)
14271 do_neon_mac_maybe_scalar_long ();
14274 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14275 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14276 if (et
.type
== NT_poly
)
14277 NEON_ENCODE (POLY
, inst
);
14279 NEON_ENCODE (INTEGER
, inst
);
14280 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14281 zero. Should be OK as-is. */
14282 neon_mixed_length (et
, et
.size
);
14289 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14290 struct neon_type_el et
= neon_check_type (3, rs
,
14291 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14292 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14294 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14295 _("shift out of range"));
14296 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14297 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14298 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14299 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14300 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14301 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14302 inst
.instruction
|= neon_quad (rs
) << 6;
14303 inst
.instruction
|= imm
<< 8;
14305 neon_dp_fixup (&inst
);
14311 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14312 struct neon_type_el et
= neon_check_type (2, rs
,
14313 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14314 unsigned op
= (inst
.instruction
>> 7) & 3;
14315 /* N (width of reversed regions) is encoded as part of the bitmask. We
14316 extract it here to check the elements to be reversed are smaller.
14317 Otherwise we'd get a reserved instruction. */
14318 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14319 gas_assert (elsize
!= 0);
14320 constraint (et
.size
>= elsize
,
14321 _("elements must be smaller than reversal region"));
14322 neon_two_same (neon_quad (rs
), 1, et
.size
);
14328 if (inst
.operands
[1].isscalar
)
14330 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14331 struct neon_type_el et
= neon_check_type (2, rs
,
14332 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14333 unsigned sizebits
= et
.size
>> 3;
14334 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14335 int logsize
= neon_logbits (et
.size
);
14336 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14338 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14341 NEON_ENCODE (SCALAR
, inst
);
14342 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14343 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14344 inst
.instruction
|= LOW4 (dm
);
14345 inst
.instruction
|= HI1 (dm
) << 5;
14346 inst
.instruction
|= neon_quad (rs
) << 6;
14347 inst
.instruction
|= x
<< 17;
14348 inst
.instruction
|= sizebits
<< 16;
14350 neon_dp_fixup (&inst
);
14354 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14355 struct neon_type_el et
= neon_check_type (2, rs
,
14356 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14357 /* Duplicate ARM register to lanes of vector. */
14358 NEON_ENCODE (ARMREG
, inst
);
14361 case 8: inst
.instruction
|= 0x400000; break;
14362 case 16: inst
.instruction
|= 0x000020; break;
14363 case 32: inst
.instruction
|= 0x000000; break;
14366 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14367 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14368 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14369 inst
.instruction
|= neon_quad (rs
) << 21;
14370 /* The encoding for this instruction is identical for the ARM and Thumb
14371 variants, except for the condition field. */
14372 do_vfp_cond_or_thumb ();
14376 /* VMOV has particularly many variations. It can be one of:
14377 0. VMOV<c><q> <Qd>, <Qm>
14378 1. VMOV<c><q> <Dd>, <Dm>
14379 (Register operations, which are VORR with Rm = Rn.)
14380 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14381 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14383 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14384 (ARM register to scalar.)
14385 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14386 (Two ARM registers to vector.)
14387 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14388 (Scalar to ARM register.)
14389 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14390 (Vector to two ARM registers.)
14391 8. VMOV.F32 <Sd>, <Sm>
14392 9. VMOV.F64 <Dd>, <Dm>
14393 (VFP register moves.)
14394 10. VMOV.F32 <Sd>, #imm
14395 11. VMOV.F64 <Dd>, #imm
14396 (VFP float immediate load.)
14397 12. VMOV <Rd>, <Sm>
14398 (VFP single to ARM reg.)
14399 13. VMOV <Sd>, <Rm>
14400 (ARM reg to VFP single.)
14401 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14402 (Two ARM regs to two VFP singles.)
14403 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14404 (Two VFP singles to two ARM regs.)
14406 These cases can be disambiguated using neon_select_shape, except cases 1/9
14407 and 3/11 which depend on the operand type too.
14409 All the encoded bits are hardcoded by this function.
14411 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14412 Cases 5, 7 may be used with VFPv2 and above.
14414 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14415 can specify a type where it doesn't make sense to, and is ignored). */
14420 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14421 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14423 struct neon_type_el et
;
14424 const char *ldconst
= 0;
14428 case NS_DD
: /* case 1/9. */
14429 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14430 /* It is not an error here if no type is given. */
14432 if (et
.type
== NT_float
&& et
.size
== 64)
14434 do_vfp_nsyn_opcode ("fcpyd");
14437 /* fall through. */
14439 case NS_QQ
: /* case 0/1. */
14441 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14443 /* The architecture manual I have doesn't explicitly state which
14444 value the U bit should have for register->register moves, but
14445 the equivalent VORR instruction has U = 0, so do that. */
14446 inst
.instruction
= 0x0200110;
14447 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14448 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14449 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14450 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14451 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14452 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14453 inst
.instruction
|= neon_quad (rs
) << 6;
14455 neon_dp_fixup (&inst
);
14459 case NS_DI
: /* case 3/11. */
14460 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14462 if (et
.type
== NT_float
&& et
.size
== 64)
14464 /* case 11 (fconstd). */
14465 ldconst
= "fconstd";
14466 goto encode_fconstd
;
14468 /* fall through. */
14470 case NS_QI
: /* case 2/3. */
14471 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14473 inst
.instruction
= 0x0800010;
14474 neon_move_immediate ();
14475 neon_dp_fixup (&inst
);
14478 case NS_SR
: /* case 4. */
14480 unsigned bcdebits
= 0;
14482 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14483 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14485 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14486 logsize
= neon_logbits (et
.size
);
14488 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14490 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14491 && et
.size
!= 32, _(BAD_FPU
));
14492 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14493 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14497 case 8: bcdebits
= 0x8; break;
14498 case 16: bcdebits
= 0x1; break;
14499 case 32: bcdebits
= 0x0; break;
14503 bcdebits
|= x
<< logsize
;
14505 inst
.instruction
= 0xe000b10;
14506 do_vfp_cond_or_thumb ();
14507 inst
.instruction
|= LOW4 (dn
) << 16;
14508 inst
.instruction
|= HI1 (dn
) << 7;
14509 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14510 inst
.instruction
|= (bcdebits
& 3) << 5;
14511 inst
.instruction
|= (bcdebits
>> 2) << 21;
14515 case NS_DRR
: /* case 5 (fmdrr). */
14516 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14519 inst
.instruction
= 0xc400b10;
14520 do_vfp_cond_or_thumb ();
14521 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14522 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14523 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14524 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14527 case NS_RS
: /* case 6. */
14530 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14531 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14532 unsigned abcdebits
= 0;
14534 et
= neon_check_type (2, NS_NULL
,
14535 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14536 logsize
= neon_logbits (et
.size
);
14538 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14540 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14541 && et
.size
!= 32, _(BAD_FPU
));
14542 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14543 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14547 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14548 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14549 case 32: abcdebits
= 0x00; break;
14553 abcdebits
|= x
<< logsize
;
14554 inst
.instruction
= 0xe100b10;
14555 do_vfp_cond_or_thumb ();
14556 inst
.instruction
|= LOW4 (dn
) << 16;
14557 inst
.instruction
|= HI1 (dn
) << 7;
14558 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14559 inst
.instruction
|= (abcdebits
& 3) << 5;
14560 inst
.instruction
|= (abcdebits
>> 2) << 21;
14564 case NS_RRD
: /* case 7 (fmrrd). */
14565 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14568 inst
.instruction
= 0xc500b10;
14569 do_vfp_cond_or_thumb ();
14570 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14571 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14572 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14573 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14576 case NS_FF
: /* case 8 (fcpys). */
14577 do_vfp_nsyn_opcode ("fcpys");
14580 case NS_FI
: /* case 10 (fconsts). */
14581 ldconst
= "fconsts";
14583 if (is_quarter_float (inst
.operands
[1].imm
))
14585 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14586 do_vfp_nsyn_opcode (ldconst
);
14589 first_error (_("immediate out of range"));
14592 case NS_RF
: /* case 12 (fmrs). */
14593 do_vfp_nsyn_opcode ("fmrs");
14596 case NS_FR
: /* case 13 (fmsr). */
14597 do_vfp_nsyn_opcode ("fmsr");
14600 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14601 (one of which is a list), but we have parsed four. Do some fiddling to
14602 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14604 case NS_RRFF
: /* case 14 (fmrrs). */
14605 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14606 _("VFP registers must be adjacent"));
14607 inst
.operands
[2].imm
= 2;
14608 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14609 do_vfp_nsyn_opcode ("fmrrs");
14612 case NS_FFRR
: /* case 15 (fmsrr). */
14613 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14614 _("VFP registers must be adjacent"));
14615 inst
.operands
[1] = inst
.operands
[2];
14616 inst
.operands
[2] = inst
.operands
[3];
14617 inst
.operands
[0].imm
= 2;
14618 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14619 do_vfp_nsyn_opcode ("fmsrr");
14628 do_neon_rshift_round_imm (void)
14630 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14631 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14632 int imm
= inst
.operands
[2].imm
;
14634 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14637 inst
.operands
[2].present
= 0;
14642 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14643 _("immediate out of range for shift"));
14644 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14649 do_neon_movl (void)
14651 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14652 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14653 unsigned sizebits
= et
.size
>> 3;
14654 inst
.instruction
|= sizebits
<< 19;
14655 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14661 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14662 struct neon_type_el et
= neon_check_type (2, rs
,
14663 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14664 NEON_ENCODE (INTEGER
, inst
);
14665 neon_two_same (neon_quad (rs
), 1, et
.size
);
14669 do_neon_zip_uzp (void)
14671 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14672 struct neon_type_el et
= neon_check_type (2, rs
,
14673 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14674 if (rs
== NS_DD
&& et
.size
== 32)
14676 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14677 inst
.instruction
= N_MNEM_vtrn
;
14681 neon_two_same (neon_quad (rs
), 1, et
.size
);
14685 do_neon_sat_abs_neg (void)
14687 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14688 struct neon_type_el et
= neon_check_type (2, rs
,
14689 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14690 neon_two_same (neon_quad (rs
), 1, et
.size
);
14694 do_neon_pair_long (void)
14696 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14697 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14698 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14699 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14700 neon_two_same (neon_quad (rs
), 1, et
.size
);
14704 do_neon_recip_est (void)
14706 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14707 struct neon_type_el et
= neon_check_type (2, rs
,
14708 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14709 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14710 neon_two_same (neon_quad (rs
), 1, et
.size
);
14716 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14717 struct neon_type_el et
= neon_check_type (2, rs
,
14718 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14719 neon_two_same (neon_quad (rs
), 1, et
.size
);
14725 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14726 struct neon_type_el et
= neon_check_type (2, rs
,
14727 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14728 neon_two_same (neon_quad (rs
), 1, et
.size
);
14734 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14735 struct neon_type_el et
= neon_check_type (2, rs
,
14736 N_EQK
| N_INT
, N_8
| N_KEY
);
14737 neon_two_same (neon_quad (rs
), 1, et
.size
);
14743 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14744 neon_two_same (neon_quad (rs
), 1, -1);
14748 do_neon_tbl_tbx (void)
14750 unsigned listlenbits
;
14751 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14753 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14755 first_error (_("bad list length for table lookup"));
14759 listlenbits
= inst
.operands
[1].imm
- 1;
14760 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14761 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14762 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14763 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14764 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14765 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14766 inst
.instruction
|= listlenbits
<< 8;
14768 neon_dp_fixup (&inst
);
14772 do_neon_ldm_stm (void)
14774 /* P, U and L bits are part of bitmask. */
14775 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14776 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14778 if (inst
.operands
[1].issingle
)
14780 do_vfp_nsyn_ldm_stm (is_dbmode
);
14784 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14785 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14787 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14788 _("register list must contain at least 1 and at most 16 "
14791 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14792 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14793 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14794 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14796 inst
.instruction
|= offsetbits
;
14798 do_vfp_cond_or_thumb ();
14802 do_neon_ldr_str (void)
14804 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14806 if (inst
.operands
[0].issingle
)
14809 do_vfp_nsyn_opcode ("flds");
14811 do_vfp_nsyn_opcode ("fsts");
14816 do_vfp_nsyn_opcode ("fldd");
14818 do_vfp_nsyn_opcode ("fstd");
14822 /* "interleave" version also handles non-interleaving register VLD1/VST1
14826 do_neon_ld_st_interleave (void)
14828 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14829 N_8
| N_16
| N_32
| N_64
);
14830 unsigned alignbits
= 0;
14832 /* The bits in this table go:
14833 0: register stride of one (0) or two (1)
14834 1,2: register list length, minus one (1, 2, 3, 4).
14835 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14836 We use -1 for invalid entries. */
14837 const int typetable
[] =
14839 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14840 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14841 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14842 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14846 if (et
.type
== NT_invtype
)
14849 if (inst
.operands
[1].immisalign
)
14850 switch (inst
.operands
[1].imm
>> 8)
14852 case 64: alignbits
= 1; break;
14854 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14855 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14856 goto bad_alignment
;
14860 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14861 goto bad_alignment
;
14866 first_error (_("bad alignment"));
14870 inst
.instruction
|= alignbits
<< 4;
14871 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14873 /* Bits [4:6] of the immediate in a list specifier encode register stride
14874 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14875 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14876 up the right value for "type" in a table based on this value and the given
14877 list style, then stick it back. */
14878 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14879 | (((inst
.instruction
>> 8) & 3) << 3);
14881 typebits
= typetable
[idx
];
14883 constraint (typebits
== -1, _("bad list type for instruction"));
14885 inst
.instruction
&= ~0xf00;
14886 inst
.instruction
|= typebits
<< 8;
14889 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14890 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14891 otherwise. The variable arguments are a list of pairs of legal (size, align)
14892 values, terminated with -1. */
14895 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14898 int result
= FAIL
, thissize
, thisalign
;
14900 if (!inst
.operands
[1].immisalign
)
14906 va_start (ap
, do_align
);
14910 thissize
= va_arg (ap
, int);
14911 if (thissize
== -1)
14913 thisalign
= va_arg (ap
, int);
14915 if (size
== thissize
&& align
== thisalign
)
14918 while (result
!= SUCCESS
);
14922 if (result
== SUCCESS
)
14925 first_error (_("unsupported alignment for instruction"));
14931 do_neon_ld_st_lane (void)
14933 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14934 int align_good
, do_align
= 0;
14935 int logsize
= neon_logbits (et
.size
);
14936 int align
= inst
.operands
[1].imm
>> 8;
14937 int n
= (inst
.instruction
>> 8) & 3;
14938 int max_el
= 64 / et
.size
;
14940 if (et
.type
== NT_invtype
)
14943 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14944 _("bad list length"));
14945 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14946 _("scalar index out of range"));
14947 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14949 _("stride of 2 unavailable when element size is 8"));
14953 case 0: /* VLD1 / VST1. */
14954 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14956 if (align_good
== FAIL
)
14960 unsigned alignbits
= 0;
14963 case 16: alignbits
= 0x1; break;
14964 case 32: alignbits
= 0x3; break;
14967 inst
.instruction
|= alignbits
<< 4;
14971 case 1: /* VLD2 / VST2. */
14972 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14974 if (align_good
== FAIL
)
14977 inst
.instruction
|= 1 << 4;
14980 case 2: /* VLD3 / VST3. */
14981 constraint (inst
.operands
[1].immisalign
,
14982 _("can't use alignment with this instruction"));
14985 case 3: /* VLD4 / VST4. */
14986 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14987 16, 64, 32, 64, 32, 128, -1);
14988 if (align_good
== FAIL
)
14992 unsigned alignbits
= 0;
14995 case 8: alignbits
= 0x1; break;
14996 case 16: alignbits
= 0x1; break;
14997 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15000 inst
.instruction
|= alignbits
<< 4;
15007 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15008 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15009 inst
.instruction
|= 1 << (4 + logsize
);
15011 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15012 inst
.instruction
|= logsize
<< 10;
15015 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15018 do_neon_ld_dup (void)
15020 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15021 int align_good
, do_align
= 0;
15023 if (et
.type
== NT_invtype
)
15026 switch ((inst
.instruction
>> 8) & 3)
15028 case 0: /* VLD1. */
15029 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15030 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15031 &do_align
, 16, 16, 32, 32, -1);
15032 if (align_good
== FAIL
)
15034 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15037 case 2: inst
.instruction
|= 1 << 5; break;
15038 default: first_error (_("bad list length")); return;
15040 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15043 case 1: /* VLD2. */
15044 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15045 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15046 if (align_good
== FAIL
)
15048 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15049 _("bad list length"));
15050 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15051 inst
.instruction
|= 1 << 5;
15052 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15055 case 2: /* VLD3. */
15056 constraint (inst
.operands
[1].immisalign
,
15057 _("can't use alignment with this instruction"));
15058 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15059 _("bad list length"));
15060 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15061 inst
.instruction
|= 1 << 5;
15062 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15065 case 3: /* VLD4. */
15067 int align
= inst
.operands
[1].imm
>> 8;
15068 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15069 16, 64, 32, 64, 32, 128, -1);
15070 if (align_good
== FAIL
)
15072 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15073 _("bad list length"));
15074 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15075 inst
.instruction
|= 1 << 5;
15076 if (et
.size
== 32 && align
== 128)
15077 inst
.instruction
|= 0x3 << 6;
15079 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15086 inst
.instruction
|= do_align
<< 4;
15089 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15090 apart from bits [11:4]. */
15093 do_neon_ldx_stx (void)
15095 if (inst
.operands
[1].isreg
)
15096 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15098 switch (NEON_LANE (inst
.operands
[0].imm
))
15100 case NEON_INTERLEAVE_LANES
:
15101 NEON_ENCODE (INTERLV
, inst
);
15102 do_neon_ld_st_interleave ();
15105 case NEON_ALL_LANES
:
15106 NEON_ENCODE (DUP
, inst
);
15111 NEON_ENCODE (LANE
, inst
);
15112 do_neon_ld_st_lane ();
15115 /* L bit comes from bit mask. */
15116 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15117 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15118 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15120 if (inst
.operands
[1].postind
)
15122 int postreg
= inst
.operands
[1].imm
& 0xf;
15123 constraint (!inst
.operands
[1].immisreg
,
15124 _("post-index must be a register"));
15125 constraint (postreg
== 0xd || postreg
== 0xf,
15126 _("bad register for post-index"));
15127 inst
.instruction
|= postreg
;
15129 else if (inst
.operands
[1].writeback
)
15131 inst
.instruction
|= 0xd;
15134 inst
.instruction
|= 0xf;
15137 inst
.instruction
|= 0xf9000000;
15139 inst
.instruction
|= 0xf4000000;
15142 /* Overall per-instruction processing. */
15144 /* We need to be able to fix up arbitrary expressions in some statements.
15145 This is so that we can handle symbols that are an arbitrary distance from
15146 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15147 which returns part of an address in a form which will be valid for
15148 a data instruction. We do this by pushing the expression into a symbol
15149 in the expr_section, and creating a fix for that. */
15152 fix_new_arm (fragS
* frag
,
15167 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15168 (enum bfd_reloc_code_real
) reloc
);
15172 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15173 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15177 /* Mark whether the fix is to a THUMB instruction, or an ARM
15179 new_fix
->tc_fix_data
= thumb_mode
;
15182 /* Create a frg for an instruction requiring relaxation. */
15184 output_relax_insn (void)
15190 /* The size of the instruction is unknown, so tie the debug info to the
15191 start of the instruction. */
15192 dwarf2_emit_insn (0);
15194 switch (inst
.reloc
.exp
.X_op
)
15197 sym
= inst
.reloc
.exp
.X_add_symbol
;
15198 offset
= inst
.reloc
.exp
.X_add_number
;
15202 offset
= inst
.reloc
.exp
.X_add_number
;
15205 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15209 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15210 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15211 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15214 /* Write a 32-bit thumb instruction to buf. */
15216 put_thumb32_insn (char * buf
, unsigned long insn
)
15218 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15219 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15223 output_inst (const char * str
)
15229 as_bad ("%s -- `%s'", inst
.error
, str
);
15234 output_relax_insn ();
15237 if (inst
.size
== 0)
15240 to
= frag_more (inst
.size
);
15241 /* PR 9814: Record the thumb mode into the current frag so that we know
15242 what type of NOP padding to use, if necessary. We override any previous
15243 setting so that if the mode has changed then the NOPS that we use will
15244 match the encoding of the last instruction in the frag. */
15245 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15247 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15249 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15250 put_thumb32_insn (to
, inst
.instruction
);
15252 else if (inst
.size
> INSN_SIZE
)
15254 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15255 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15256 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15259 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15261 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15262 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15263 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15266 dwarf2_emit_insn (inst
.size
);
15270 output_it_inst (int cond
, int mask
, char * to
)
15272 unsigned long instruction
= 0xbf00;
15275 instruction
|= mask
;
15276 instruction
|= cond
<< 4;
15280 to
= frag_more (2);
15282 dwarf2_emit_insn (2);
15286 md_number_to_chars (to
, instruction
, 2);
15291 /* Tag values used in struct asm_opcode's tag field. */
15294 OT_unconditional
, /* Instruction cannot be conditionalized.
15295 The ARM condition field is still 0xE. */
15296 OT_unconditionalF
, /* Instruction cannot be conditionalized
15297 and carries 0xF in its ARM condition field. */
15298 OT_csuffix
, /* Instruction takes a conditional suffix. */
15299 OT_csuffixF
, /* Some forms of the instruction take a conditional
15300 suffix, others place 0xF where the condition field
15302 OT_cinfix3
, /* Instruction takes a conditional infix,
15303 beginning at character index 3. (In
15304 unified mode, it becomes a suffix.) */
15305 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15306 tsts, cmps, cmns, and teqs. */
15307 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15308 character index 3, even in unified mode. Used for
15309 legacy instructions where suffix and infix forms
15310 may be ambiguous. */
15311 OT_csuf_or_in3
, /* Instruction takes either a conditional
15312 suffix or an infix at character index 3. */
15313 OT_odd_infix_unc
, /* This is the unconditional variant of an
15314 instruction that takes a conditional infix
15315 at an unusual position. In unified mode,
15316 this variant will accept a suffix. */
15317 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15318 are the conditional variants of instructions that
15319 take conditional infixes in unusual positions.
15320 The infix appears at character index
15321 (tag - OT_odd_infix_0). These are not accepted
15322 in unified mode. */
15325 /* Subroutine of md_assemble, responsible for looking up the primary
15326 opcode from the mnemonic the user wrote. STR points to the
15327 beginning of the mnemonic.
15329 This is not simply a hash table lookup, because of conditional
15330 variants. Most instructions have conditional variants, which are
15331 expressed with a _conditional affix_ to the mnemonic. If we were
15332 to encode each conditional variant as a literal string in the opcode
15333 table, it would have approximately 20,000 entries.
15335 Most mnemonics take this affix as a suffix, and in unified syntax,
15336 'most' is upgraded to 'all'. However, in the divided syntax, some
15337 instructions take the affix as an infix, notably the s-variants of
15338 the arithmetic instructions. Of those instructions, all but six
15339 have the infix appear after the third character of the mnemonic.
15341 Accordingly, the algorithm for looking up primary opcodes given
15344 1. Look up the identifier in the opcode table.
15345 If we find a match, go to step U.
15347 2. Look up the last two characters of the identifier in the
15348 conditions table. If we find a match, look up the first N-2
15349 characters of the identifier in the opcode table. If we
15350 find a match, go to step CE.
15352 3. Look up the fourth and fifth characters of the identifier in
15353 the conditions table. If we find a match, extract those
15354 characters from the identifier, and look up the remaining
15355 characters in the opcode table. If we find a match, go
15360 U. Examine the tag field of the opcode structure, in case this is
15361 one of the six instructions with its conditional infix in an
15362 unusual place. If it is, the tag tells us where to find the
15363 infix; look it up in the conditions table and set inst.cond
15364 accordingly. Otherwise, this is an unconditional instruction.
15365 Again set inst.cond accordingly. Return the opcode structure.
15367 CE. Examine the tag field to make sure this is an instruction that
15368 should receive a conditional suffix. If it is not, fail.
15369 Otherwise, set inst.cond from the suffix we already looked up,
15370 and return the opcode structure.
15372 CM. Examine the tag field to make sure this is an instruction that
15373 should receive a conditional infix after the third character.
15374 If it is not, fail. Otherwise, undo the edits to the current
15375 line of input and proceed as for case CE. */
15377 static const struct asm_opcode
*
15378 opcode_lookup (char **str
)
15382 const struct asm_opcode
*opcode
;
15383 const struct asm_cond
*cond
;
15386 /* Scan up to the end of the mnemonic, which must end in white space,
15387 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15388 for (base
= end
= *str
; *end
!= '\0'; end
++)
15389 if (*end
== ' ' || *end
== '.')
15395 /* Handle a possible width suffix and/or Neon type suffix. */
15400 /* The .w and .n suffixes are only valid if the unified syntax is in
15402 if (unified_syntax
&& end
[1] == 'w')
15404 else if (unified_syntax
&& end
[1] == 'n')
15409 inst
.vectype
.elems
= 0;
15411 *str
= end
+ offset
;
15413 if (end
[offset
] == '.')
15415 /* See if we have a Neon type suffix (possible in either unified or
15416 non-unified ARM syntax mode). */
15417 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15420 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15426 /* Look for unaffixed or special-case affixed mnemonic. */
15427 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15432 if (opcode
->tag
< OT_odd_infix_0
)
15434 inst
.cond
= COND_ALWAYS
;
15438 if (warn_on_deprecated
&& unified_syntax
)
15439 as_warn (_("conditional infixes are deprecated in unified syntax"));
15440 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15441 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15444 inst
.cond
= cond
->value
;
15448 /* Cannot have a conditional suffix on a mnemonic of less than two
15450 if (end
- base
< 3)
15453 /* Look for suffixed mnemonic. */
15455 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15456 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15458 if (opcode
&& cond
)
15461 switch (opcode
->tag
)
15463 case OT_cinfix3_legacy
:
15464 /* Ignore conditional suffixes matched on infix only mnemonics. */
15468 case OT_cinfix3_deprecated
:
15469 case OT_odd_infix_unc
:
15470 if (!unified_syntax
)
15472 /* else fall through */
15476 case OT_csuf_or_in3
:
15477 inst
.cond
= cond
->value
;
15480 case OT_unconditional
:
15481 case OT_unconditionalF
:
15483 inst
.cond
= cond
->value
;
15486 /* Delayed diagnostic. */
15487 inst
.error
= BAD_COND
;
15488 inst
.cond
= COND_ALWAYS
;
15497 /* Cannot have a usual-position infix on a mnemonic of less than
15498 six characters (five would be a suffix). */
15499 if (end
- base
< 6)
15502 /* Look for infixed mnemonic in the usual position. */
15504 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15508 memcpy (save
, affix
, 2);
15509 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15510 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15512 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15513 memcpy (affix
, save
, 2);
15516 && (opcode
->tag
== OT_cinfix3
15517 || opcode
->tag
== OT_cinfix3_deprecated
15518 || opcode
->tag
== OT_csuf_or_in3
15519 || opcode
->tag
== OT_cinfix3_legacy
))
15522 if (warn_on_deprecated
&& unified_syntax
15523 && (opcode
->tag
== OT_cinfix3
15524 || opcode
->tag
== OT_cinfix3_deprecated
))
15525 as_warn (_("conditional infixes are deprecated in unified syntax"));
15527 inst
.cond
= cond
->value
;
15534 /* This function generates an initial IT instruction, leaving its block
15535 virtually open for the new instructions. Eventually,
15536 the mask will be updated by now_it_add_mask () each time
15537 a new instruction needs to be included in the IT block.
15538 Finally, the block is closed with close_automatic_it_block ().
15539 The block closure can be requested either from md_assemble (),
15540 a tencode (), or due to a label hook. */
15543 new_automatic_it_block (int cond
)
15545 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15546 now_it
.mask
= 0x18;
15548 now_it
.block_length
= 1;
15549 mapping_state (MAP_THUMB
);
15550 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15553 /* Close an automatic IT block.
15554 See comments in new_automatic_it_block (). */
15557 close_automatic_it_block (void)
15559 now_it
.mask
= 0x10;
15560 now_it
.block_length
= 0;
15563 /* Update the mask of the current automatically-generated IT
15564 instruction. See comments in new_automatic_it_block (). */
15567 now_it_add_mask (int cond
)
15569 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15570 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15571 | ((bitvalue) << (nbit)))
15572 const int resulting_bit
= (cond
& 1);
15574 now_it
.mask
&= 0xf;
15575 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15577 (5 - now_it
.block_length
));
15578 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15580 ((5 - now_it
.block_length
) - 1) );
15581 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15584 #undef SET_BIT_VALUE
15587 /* The IT blocks handling machinery is accessed through the these functions:
15588 it_fsm_pre_encode () from md_assemble ()
15589 set_it_insn_type () optional, from the tencode functions
15590 set_it_insn_type_last () ditto
15591 in_it_block () ditto
15592 it_fsm_post_encode () from md_assemble ()
15593 force_automatic_it_block_close () from label habdling functions
15596 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15597 initializing the IT insn type with a generic initial value depending
15598 on the inst.condition.
15599 2) During the tencode function, two things may happen:
15600 a) The tencode function overrides the IT insn type by
15601 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15602 b) The tencode function queries the IT block state by
15603 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15605 Both set_it_insn_type and in_it_block run the internal FSM state
15606 handling function (handle_it_state), because: a) setting the IT insn
15607 type may incur in an invalid state (exiting the function),
15608 and b) querying the state requires the FSM to be updated.
15609 Specifically we want to avoid creating an IT block for conditional
15610 branches, so it_fsm_pre_encode is actually a guess and we can't
15611 determine whether an IT block is required until the tencode () routine
15612 has decided what type of instruction this actually it.
15613 Because of this, if set_it_insn_type and in_it_block have to be used,
15614 set_it_insn_type has to be called first.
15616 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15617 determines the insn IT type depending on the inst.cond code.
15618 When a tencode () routine encodes an instruction that can be
15619 either outside an IT block, or, in the case of being inside, has to be
15620 the last one, set_it_insn_type_last () will determine the proper
15621 IT instruction type based on the inst.cond code. Otherwise,
15622 set_it_insn_type can be called for overriding that logic or
15623 for covering other cases.
15625 Calling handle_it_state () may not transition the IT block state to
15626 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15627 still queried. Instead, if the FSM determines that the state should
15628 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15629 after the tencode () function: that's what it_fsm_post_encode () does.
15631 Since in_it_block () calls the state handling function to get an
15632 updated state, an error may occur (due to invalid insns combination).
15633 In that case, inst.error is set.
15634 Therefore, inst.error has to be checked after the execution of
15635 the tencode () routine.
15637 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15638 any pending state change (if any) that didn't take place in
15639 handle_it_state () as explained above. */
15642 it_fsm_pre_encode (void)
15644 if (inst
.cond
!= COND_ALWAYS
)
15645 inst
.it_insn_type
= INSIDE_IT_INSN
;
15647 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15649 now_it
.state_handled
= 0;
15652 /* IT state FSM handling function. */
15655 handle_it_state (void)
15657 now_it
.state_handled
= 1;
15659 switch (now_it
.state
)
15661 case OUTSIDE_IT_BLOCK
:
15662 switch (inst
.it_insn_type
)
15664 case OUTSIDE_IT_INSN
:
15667 case INSIDE_IT_INSN
:
15668 case INSIDE_IT_LAST_INSN
:
15669 if (thumb_mode
== 0)
15672 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15673 as_tsktsk (_("Warning: conditional outside an IT block"\
15678 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15679 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15681 /* Automatically generate the IT instruction. */
15682 new_automatic_it_block (inst
.cond
);
15683 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15684 close_automatic_it_block ();
15688 inst
.error
= BAD_OUT_IT
;
15694 case IF_INSIDE_IT_LAST_INSN
:
15695 case NEUTRAL_IT_INSN
:
15699 now_it
.state
= MANUAL_IT_BLOCK
;
15700 now_it
.block_length
= 0;
15705 case AUTOMATIC_IT_BLOCK
:
15706 /* Three things may happen now:
15707 a) We should increment current it block size;
15708 b) We should close current it block (closing insn or 4 insns);
15709 c) We should close current it block and start a new one (due
15710 to incompatible conditions or
15711 4 insns-length block reached). */
15713 switch (inst
.it_insn_type
)
15715 case OUTSIDE_IT_INSN
:
15716 /* The closure of the block shall happen immediatelly,
15717 so any in_it_block () call reports the block as closed. */
15718 force_automatic_it_block_close ();
15721 case INSIDE_IT_INSN
:
15722 case INSIDE_IT_LAST_INSN
:
15723 case IF_INSIDE_IT_LAST_INSN
:
15724 now_it
.block_length
++;
15726 if (now_it
.block_length
> 4
15727 || !now_it_compatible (inst
.cond
))
15729 force_automatic_it_block_close ();
15730 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15731 new_automatic_it_block (inst
.cond
);
15735 now_it_add_mask (inst
.cond
);
15738 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15739 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15740 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15741 close_automatic_it_block ();
15744 case NEUTRAL_IT_INSN
:
15745 now_it
.block_length
++;
15747 if (now_it
.block_length
> 4)
15748 force_automatic_it_block_close ();
15750 now_it_add_mask (now_it
.cc
& 1);
15754 close_automatic_it_block ();
15755 now_it
.state
= MANUAL_IT_BLOCK
;
15760 case MANUAL_IT_BLOCK
:
15762 /* Check conditional suffixes. */
15763 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15766 now_it
.mask
&= 0x1f;
15767 is_last
= (now_it
.mask
== 0x10);
15769 switch (inst
.it_insn_type
)
15771 case OUTSIDE_IT_INSN
:
15772 inst
.error
= BAD_NOT_IT
;
15775 case INSIDE_IT_INSN
:
15776 if (cond
!= inst
.cond
)
15778 inst
.error
= BAD_IT_COND
;
15783 case INSIDE_IT_LAST_INSN
:
15784 case IF_INSIDE_IT_LAST_INSN
:
15785 if (cond
!= inst
.cond
)
15787 inst
.error
= BAD_IT_COND
;
15792 inst
.error
= BAD_BRANCH
;
15797 case NEUTRAL_IT_INSN
:
15798 /* The BKPT instruction is unconditional even in an IT block. */
15802 inst
.error
= BAD_IT_IT
;
15813 it_fsm_post_encode (void)
15817 if (!now_it
.state_handled
)
15818 handle_it_state ();
15820 is_last
= (now_it
.mask
== 0x10);
15823 now_it
.state
= OUTSIDE_IT_BLOCK
;
15829 force_automatic_it_block_close (void)
15831 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15833 close_automatic_it_block ();
15834 now_it
.state
= OUTSIDE_IT_BLOCK
;
15842 if (!now_it
.state_handled
)
15843 handle_it_state ();
15845 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15849 md_assemble (char *str
)
15852 const struct asm_opcode
* opcode
;
15854 /* Align the previous label if needed. */
15855 if (last_label_seen
!= NULL
)
15857 symbol_set_frag (last_label_seen
, frag_now
);
15858 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15859 S_SET_SEGMENT (last_label_seen
, now_seg
);
15862 memset (&inst
, '\0', sizeof (inst
));
15863 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15865 opcode
= opcode_lookup (&p
);
15868 /* It wasn't an instruction, but it might be a register alias of
15869 the form alias .req reg, or a Neon .dn/.qn directive. */
15870 if (! create_register_alias (str
, p
)
15871 && ! create_neon_reg_alias (str
, p
))
15872 as_bad (_("bad instruction `%s'"), str
);
15877 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15878 as_warn (_("s suffix on comparison instruction is deprecated"));
15880 /* The value which unconditional instructions should have in place of the
15881 condition field. */
15882 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15886 arm_feature_set variant
;
15888 variant
= cpu_variant
;
15889 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15890 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15891 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15892 /* Check that this instruction is supported for this CPU. */
15893 if (!opcode
->tvariant
15894 || (thumb_mode
== 1
15895 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15897 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15900 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15901 && opcode
->tencode
!= do_t_branch
)
15903 as_bad (_("Thumb does not support conditional execution"));
15907 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15909 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15910 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15911 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15913 /* Two things are addressed here.
15914 1) Implicit require narrow instructions on Thumb-1.
15915 This avoids relaxation accidentally introducing Thumb-2
15917 2) Reject wide instructions in non Thumb-2 cores. */
15918 if (inst
.size_req
== 0)
15920 else if (inst
.size_req
== 4)
15922 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
15928 inst
.instruction
= opcode
->tvalue
;
15930 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15932 /* Prepare the it_insn_type for those encodings that don't set
15934 it_fsm_pre_encode ();
15936 opcode
->tencode ();
15938 it_fsm_post_encode ();
15941 if (!(inst
.error
|| inst
.relax
))
15943 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15944 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15945 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15947 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15952 /* Something has gone badly wrong if we try to relax a fixed size
15954 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15956 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15957 *opcode
->tvariant
);
15958 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15959 set those bits when Thumb-2 32-bit instructions are seen. ie.
15960 anything other than bl/blx and v6-M instructions.
15961 This is overly pessimistic for relaxable instructions. */
15962 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15964 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15965 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15966 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15969 check_neon_suffixes
;
15973 mapping_state (MAP_THUMB
);
15976 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15980 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15981 is_bx
= (opcode
->aencode
== do_bx
);
15983 /* Check that this instruction is supported for this CPU. */
15984 if (!(is_bx
&& fix_v4bx
)
15985 && !(opcode
->avariant
&&
15986 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15988 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
15993 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15997 inst
.instruction
= opcode
->avalue
;
15998 if (opcode
->tag
== OT_unconditionalF
)
15999 inst
.instruction
|= 0xF << 28;
16001 inst
.instruction
|= inst
.cond
<< 28;
16002 inst
.size
= INSN_SIZE
;
16003 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16005 it_fsm_pre_encode ();
16006 opcode
->aencode ();
16007 it_fsm_post_encode ();
16009 /* Arm mode bx is marked as both v4T and v5 because it's still required
16010 on a hypothetical non-thumb v5 core. */
16012 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16014 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16015 *opcode
->avariant
);
16017 check_neon_suffixes
;
16021 mapping_state (MAP_ARM
);
16026 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16034 check_it_blocks_finished (void)
16039 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16040 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16041 == MANUAL_IT_BLOCK
)
16043 as_warn (_("section '%s' finished with an open IT block."),
16047 if (now_it
.state
== MANUAL_IT_BLOCK
)
16048 as_warn (_("file finished with an open IT block."));
16052 /* Various frobbings of labels and their addresses. */
16055 arm_start_line_hook (void)
16057 last_label_seen
= NULL
;
16061 arm_frob_label (symbolS
* sym
)
16063 last_label_seen
= sym
;
16065 ARM_SET_THUMB (sym
, thumb_mode
);
16067 #if defined OBJ_COFF || defined OBJ_ELF
16068 ARM_SET_INTERWORK (sym
, support_interwork
);
16071 force_automatic_it_block_close ();
16073 /* Note - do not allow local symbols (.Lxxx) to be labelled
16074 as Thumb functions. This is because these labels, whilst
16075 they exist inside Thumb code, are not the entry points for
16076 possible ARM->Thumb calls. Also, these labels can be used
16077 as part of a computed goto or switch statement. eg gcc
16078 can generate code that looks like this:
16080 ldr r2, [pc, .Laaa]
16090 The first instruction loads the address of the jump table.
16091 The second instruction converts a table index into a byte offset.
16092 The third instruction gets the jump address out of the table.
16093 The fourth instruction performs the jump.
16095 If the address stored at .Laaa is that of a symbol which has the
16096 Thumb_Func bit set, then the linker will arrange for this address
16097 to have the bottom bit set, which in turn would mean that the
16098 address computation performed by the third instruction would end
16099 up with the bottom bit set. Since the ARM is capable of unaligned
16100 word loads, the instruction would then load the incorrect address
16101 out of the jump table, and chaos would ensue. */
16102 if (label_is_thumb_function_name
16103 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16104 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16106 /* When the address of a Thumb function is taken the bottom
16107 bit of that address should be set. This will allow
16108 interworking between Arm and Thumb functions to work
16111 THUMB_SET_FUNC (sym
, 1);
16113 label_is_thumb_function_name
= FALSE
;
16116 dwarf2_emit_label (sym
);
16120 arm_data_in_code (void)
16122 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16124 *input_line_pointer
= '/';
16125 input_line_pointer
+= 5;
16126 *input_line_pointer
= 0;
16134 arm_canonicalize_symbol_name (char * name
)
16138 if (thumb_mode
&& (len
= strlen (name
)) > 5
16139 && streq (name
+ len
- 5, "/data"))
16140 *(name
+ len
- 5) = 0;
16145 /* Table of all register names defined by default. The user can
16146 define additional names with .req. Note that all register names
16147 should appear in both upper and lowercase variants. Some registers
16148 also have mixed-case names. */
16150 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16151 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16152 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16153 #define REGSET(p,t) \
16154 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16155 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16156 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16157 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16158 #define REGSETH(p,t) \
16159 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16160 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16161 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16162 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16163 #define REGSET2(p,t) \
16164 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16165 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16166 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16167 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16169 static const struct reg_entry reg_names
[] =
16171 /* ARM integer registers. */
16172 REGSET(r
, RN
), REGSET(R
, RN
),
16174 /* ATPCS synonyms. */
16175 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16176 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16177 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16179 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16180 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16181 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16183 /* Well-known aliases. */
16184 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16185 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16187 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16188 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16190 /* Coprocessor numbers. */
16191 REGSET(p
, CP
), REGSET(P
, CP
),
16193 /* Coprocessor register numbers. The "cr" variants are for backward
16195 REGSET(c
, CN
), REGSET(C
, CN
),
16196 REGSET(cr
, CN
), REGSET(CR
, CN
),
16198 /* FPA registers. */
16199 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16200 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16202 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16203 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16205 /* VFP SP registers. */
16206 REGSET(s
,VFS
), REGSET(S
,VFS
),
16207 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16209 /* VFP DP Registers. */
16210 REGSET(d
,VFD
), REGSET(D
,VFD
),
16211 /* Extra Neon DP registers. */
16212 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16214 /* Neon QP registers. */
16215 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16217 /* VFP control registers. */
16218 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16219 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16220 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16221 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16222 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16223 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16225 /* Maverick DSP coprocessor registers. */
16226 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16227 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16229 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16230 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16231 REGDEF(dspsc
,0,DSPSC
),
16233 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16234 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16235 REGDEF(DSPSC
,0,DSPSC
),
16237 /* iWMMXt data registers - p0, c0-15. */
16238 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16240 /* iWMMXt control registers - p1, c0-3. */
16241 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16242 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16243 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16244 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16246 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16247 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16248 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16249 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16250 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16252 /* XScale accumulator registers. */
16253 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16259 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16260 within psr_required_here. */
16261 static const struct asm_psr psrs
[] =
16263 /* Backward compatibility notation. Note that "all" is no longer
16264 truly all possible PSR bits. */
16265 {"all", PSR_c
| PSR_f
},
16269 /* Individual flags. */
16276 /* Combinations of flags. */
16277 {"fs", PSR_f
| PSR_s
},
16278 {"fx", PSR_f
| PSR_x
},
16279 {"fc", PSR_f
| PSR_c
},
16280 {"sf", PSR_s
| PSR_f
},
16281 {"sx", PSR_s
| PSR_x
},
16282 {"sc", PSR_s
| PSR_c
},
16283 {"xf", PSR_x
| PSR_f
},
16284 {"xs", PSR_x
| PSR_s
},
16285 {"xc", PSR_x
| PSR_c
},
16286 {"cf", PSR_c
| PSR_f
},
16287 {"cs", PSR_c
| PSR_s
},
16288 {"cx", PSR_c
| PSR_x
},
16289 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16290 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16291 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16292 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16293 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16294 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16295 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16296 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16297 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16298 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16299 {"scf", PSR_s
| PSR_c
| PSR_f
},
16300 {"scx", PSR_s
| PSR_c
| PSR_x
},
16301 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16302 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16303 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16304 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16305 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16306 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16307 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16308 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16309 {"csf", PSR_c
| PSR_s
| PSR_f
},
16310 {"csx", PSR_c
| PSR_s
| PSR_x
},
16311 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16312 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16313 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16314 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16315 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16316 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16317 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16318 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16319 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16320 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16321 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16322 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16323 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16324 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16325 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16326 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16327 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16328 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16329 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16330 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16331 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16332 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16333 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16334 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16335 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16336 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16340 {"nzcvqg", PSR_s
| PSR_f
}
16343 /* Table of V7M psr names. */
16344 static const struct asm_psr v7m_psrs
[] =
16346 {"apsr", 0 }, {"APSR", 0 },
16347 {"iapsr", 1 }, {"IAPSR", 1 },
16348 {"eapsr", 2 }, {"EAPSR", 2 },
16349 {"psr", 3 }, {"PSR", 3 },
16350 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16351 {"ipsr", 5 }, {"IPSR", 5 },
16352 {"epsr", 6 }, {"EPSR", 6 },
16353 {"iepsr", 7 }, {"IEPSR", 7 },
16354 {"msp", 8 }, {"MSP", 8 },
16355 {"psp", 9 }, {"PSP", 9 },
16356 {"primask", 16}, {"PRIMASK", 16},
16357 {"basepri", 17}, {"BASEPRI", 17},
16358 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16359 {"faultmask", 19}, {"FAULTMASK", 19},
16360 {"control", 20}, {"CONTROL", 20}
16363 /* Table of all shift-in-operand names. */
16364 static const struct asm_shift_name shift_names
[] =
16366 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16367 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16368 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16369 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16370 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16371 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16374 /* Table of all explicit relocation names. */
16376 static struct reloc_entry reloc_names
[] =
16378 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16379 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16380 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16381 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16382 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16383 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16384 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16385 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16386 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16387 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16388 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16389 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16393 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16394 static const struct asm_cond conds
[] =
16398 {"cs", 0x2}, {"hs", 0x2},
16399 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16413 static struct asm_barrier_opt barrier_opt_names
[] =
16415 { "sy", 0xf }, { "SY", 0xf },
16416 { "un", 0x7 }, { "UN", 0x7 },
16417 { "st", 0xe }, { "ST", 0xe },
16418 { "unst", 0x6 }, { "UNST", 0x6 },
16419 { "ish", 0xb }, { "ISH", 0xb },
16420 { "sh", 0xb }, { "SH", 0xb },
16421 { "ishst", 0xa }, { "ISHST", 0xa },
16422 { "shst", 0xa }, { "SHST", 0xa },
16423 { "nsh", 0x7 }, { "NSH", 0x7 },
16424 { "nshst", 0x6 }, { "NSHST", 0x6 },
16425 { "osh", 0x3 }, { "OSH", 0x3 },
16426 { "oshst", 0x2 }, { "OSHST", 0x2 }
16429 /* Table of ARM-format instructions. */
16431 /* Macros for gluing together operand strings. N.B. In all cases
16432 other than OPS0, the trailing OP_stop comes from default
16433 zero-initialization of the unspecified elements of the array. */
16434 #define OPS0() { OP_stop, }
16435 #define OPS1(a) { OP_##a, }
16436 #define OPS2(a,b) { OP_##a,OP_##b, }
16437 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16438 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16439 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16440 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16442 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16443 This is useful when mixing operands for ARM and THUMB, i.e. using the
16444 MIX_ARM_THUMB_OPERANDS macro.
16445 In order to use these macros, prefix the number of operands with _
16447 #define OPS_1(a) { a, }
16448 #define OPS_2(a,b) { a,b, }
16449 #define OPS_3(a,b,c) { a,b,c, }
16450 #define OPS_4(a,b,c,d) { a,b,c,d, }
16451 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16452 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16454 /* These macros abstract out the exact format of the mnemonic table and
16455 save some repeated characters. */
16457 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16458 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16459 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16460 THUMB_VARIANT, do_##ae, do_##te }
16462 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16463 a T_MNEM_xyz enumerator. */
16464 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16465 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16466 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16467 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16469 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16470 infix after the third character. */
16471 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16472 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16473 THUMB_VARIANT, do_##ae, do_##te }
16474 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16475 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16476 THUMB_VARIANT, do_##ae, do_##te }
16477 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16478 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16479 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16480 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16481 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16482 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16483 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16484 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16486 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16487 appear in the condition table. */
16488 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16489 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16490 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16492 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16493 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16494 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16495 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16496 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16497 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16498 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16499 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16500 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16501 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16502 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16503 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16504 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16505 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16506 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16507 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16508 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16509 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16510 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16511 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16513 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16514 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16515 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16516 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16518 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16519 field is still 0xE. Many of the Thumb variants can be executed
16520 conditionally, so this is checked separately. */
16521 #define TUE(mnem, op, top, nops, ops, ae, te) \
16522 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16523 THUMB_VARIANT, do_##ae, do_##te }
16525 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16526 condition code field. */
16527 #define TUF(mnem, op, top, nops, ops, ae, te) \
16528 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16529 THUMB_VARIANT, do_##ae, do_##te }
16531 /* ARM-only variants of all the above. */
16532 #define CE(mnem, op, nops, ops, ae) \
16533 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16535 #define C3(mnem, op, nops, ops, ae) \
16536 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16538 /* Legacy mnemonics that always have conditional infix after the third
16540 #define CL(mnem, op, nops, ops, ae) \
16541 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16542 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16544 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16545 #define cCE(mnem, op, nops, ops, ae) \
16546 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16548 /* Legacy coprocessor instructions where conditional infix and conditional
16549 suffix are ambiguous. For consistency this includes all FPA instructions,
16550 not just the potentially ambiguous ones. */
16551 #define cCL(mnem, op, nops, ops, ae) \
16552 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16553 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16555 /* Coprocessor, takes either a suffix or a position-3 infix
16556 (for an FPA corner case). */
16557 #define C3E(mnem, op, nops, ops, ae) \
16558 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16559 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16561 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16562 { m1 #m2 m3, OPS##nops ops, \
16563 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16564 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16566 #define CM(m1, m2, op, nops, ops, ae) \
16567 xCM_ (m1, , m2, op, nops, ops, ae), \
16568 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16569 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16570 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16571 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16572 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16573 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16574 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16575 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16576 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16577 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16578 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16579 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16580 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16581 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16582 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16583 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16584 xCM_ (m1, le, m2, op, nops, ops, ae), \
16585 xCM_ (m1, al, m2, op, nops, ops, ae)
16587 #define UE(mnem, op, nops, ops, ae) \
16588 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16590 #define UF(mnem, op, nops, ops, ae) \
16591 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16593 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16594 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16595 use the same encoding function for each. */
16596 #define NUF(mnem, op, nops, ops, enc) \
16597 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16598 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16600 /* Neon data processing, version which indirects through neon_enc_tab for
16601 the various overloaded versions of opcodes. */
16602 #define nUF(mnem, op, nops, ops, enc) \
16603 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16604 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16606 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16608 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16609 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16610 THUMB_VARIANT, do_##enc, do_##enc }
16612 #define NCE(mnem, op, nops, ops, enc) \
16613 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16615 #define NCEF(mnem, op, nops, ops, enc) \
16616 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16618 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16619 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16620 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16621 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16623 #define nCE(mnem, op, nops, ops, enc) \
16624 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16626 #define nCEF(mnem, op, nops, ops, enc) \
16627 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16631 static const struct asm_opcode insns
[] =
16633 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16634 #define THUMB_VARIANT &arm_ext_v4t
16635 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16636 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16637 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16638 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16639 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16640 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16641 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16642 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16643 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16644 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16645 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16646 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16647 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16648 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16649 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16650 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16652 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16653 for setting PSR flag bits. They are obsolete in V6 and do not
16654 have Thumb equivalents. */
16655 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16656 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16657 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16658 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16659 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16660 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16661 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16662 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16663 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16665 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16666 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16667 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16668 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16670 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16671 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16672 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16674 OP_ADDRGLDR
),ldst
, t_ldst
),
16675 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16677 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16678 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16679 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16680 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16681 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16682 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16684 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16685 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16686 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16687 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16690 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16691 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16692 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16694 /* Thumb-compatibility pseudo ops. */
16695 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16696 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16697 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16698 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16699 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16700 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16701 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16702 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16703 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16704 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16705 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16706 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16708 /* These may simplify to neg. */
16709 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16710 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16712 #undef THUMB_VARIANT
16713 #define THUMB_VARIANT & arm_ext_v6
16715 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16717 /* V1 instructions with no Thumb analogue prior to V6T2. */
16718 #undef THUMB_VARIANT
16719 #define THUMB_VARIANT & arm_ext_v6t2
16721 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16722 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16723 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16725 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16726 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16727 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16728 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16730 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16731 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16733 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16734 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16736 /* V1 instructions with no Thumb analogue at all. */
16737 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16738 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16740 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16741 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16742 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16743 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16744 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16745 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16746 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16747 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16750 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16751 #undef THUMB_VARIANT
16752 #define THUMB_VARIANT & arm_ext_v4t
16754 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16755 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16757 #undef THUMB_VARIANT
16758 #define THUMB_VARIANT & arm_ext_v6t2
16760 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16761 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16763 /* Generic coprocessor instructions. */
16764 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16765 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16766 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16767 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16768 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16769 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16770 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16773 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16775 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16776 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16779 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16780 #undef THUMB_VARIANT
16781 #define THUMB_VARIANT & arm_ext_msr
16783 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16784 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16787 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16788 #undef THUMB_VARIANT
16789 #define THUMB_VARIANT & arm_ext_v6t2
16791 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16792 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16793 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16794 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16795 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16796 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16797 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16798 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16801 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16802 #undef THUMB_VARIANT
16803 #define THUMB_VARIANT & arm_ext_v4t
16805 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16806 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16807 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16808 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16809 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16810 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16813 #define ARM_VARIANT & arm_ext_v4t_5
16815 /* ARM Architecture 4T. */
16816 /* Note: bx (and blx) are required on V5, even if the processor does
16817 not support Thumb. */
16818 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16821 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16822 #undef THUMB_VARIANT
16823 #define THUMB_VARIANT & arm_ext_v5t
16825 /* Note: blx has 2 variants; the .value coded here is for
16826 BLX(2). Only this variant has conditional execution. */
16827 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16828 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16830 #undef THUMB_VARIANT
16831 #define THUMB_VARIANT & arm_ext_v6t2
16833 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16834 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16835 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16836 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16837 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16838 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16839 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16840 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16843 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16844 #undef THUMB_VARIANT
16845 #define THUMB_VARIANT &arm_ext_v5exp
16847 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16848 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16849 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16850 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16852 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16853 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16855 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16856 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16857 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16858 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16860 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16861 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16862 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16863 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16865 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16866 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16868 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16869 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16870 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16871 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16874 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16875 #undef THUMB_VARIANT
16876 #define THUMB_VARIANT &arm_ext_v6t2
16878 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16879 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16881 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16882 ADDRGLDRS
), ldrd
, t_ldstd
),
16884 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16885 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16888 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16890 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16893 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16894 #undef THUMB_VARIANT
16895 #define THUMB_VARIANT & arm_ext_v6
16897 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16898 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16899 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16900 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16901 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16902 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16903 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16904 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16905 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16906 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16908 #undef THUMB_VARIANT
16909 #define THUMB_VARIANT & arm_ext_v6t2
16911 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16912 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16914 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16915 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16917 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16918 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16920 /* ARM V6 not included in V7M. */
16921 #undef THUMB_VARIANT
16922 #define THUMB_VARIANT & arm_ext_v6_notm
16923 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16924 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16925 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16926 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16927 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16928 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16929 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16930 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16931 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16932 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16933 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16934 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16936 /* ARM V6 not included in V7M (eg. integer SIMD). */
16937 #undef THUMB_VARIANT
16938 #define THUMB_VARIANT & arm_ext_v6_dsp
16939 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16940 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16941 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16942 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16943 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16944 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16945 /* Old name for QASX. */
16946 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16947 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16948 /* Old name for QSAX. */
16949 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16950 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16951 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16952 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16953 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16954 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16955 /* Old name for SASX. */
16956 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16957 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16958 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16959 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16960 /* Old name for SHASX. */
16961 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16962 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16963 /* Old name for SHSAX. */
16964 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16965 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16966 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16967 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16968 /* Old name for SSAX. */
16969 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16970 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16971 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16972 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16973 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16974 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16975 /* Old name for UASX. */
16976 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16977 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16978 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16979 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16980 /* Old name for UHASX. */
16981 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16982 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16983 /* Old name for UHSAX. */
16984 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16985 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16986 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16987 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16988 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16989 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16990 /* Old name for UQASX. */
16991 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16992 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16993 /* Old name for UQSAX. */
16994 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16995 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16996 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16997 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16998 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16999 /* Old name for USAX. */
17000 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17001 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17002 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17003 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17004 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17005 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17006 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17007 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17008 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17009 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17010 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17011 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17012 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17013 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17014 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17015 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17016 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17017 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17018 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17019 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17020 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17021 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17022 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17023 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17024 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17025 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17026 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17027 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17028 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17029 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17030 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17031 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17032 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17033 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17036 #define ARM_VARIANT & arm_ext_v6k
17037 #undef THUMB_VARIANT
17038 #define THUMB_VARIANT & arm_ext_v6k
17040 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17041 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17042 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17043 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17045 #undef THUMB_VARIANT
17046 #define THUMB_VARIANT & arm_ext_v6_notm
17047 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17049 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17050 RRnpcb
), strexd
, t_strexd
),
17052 #undef THUMB_VARIANT
17053 #define THUMB_VARIANT & arm_ext_v6t2
17054 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17056 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17058 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17060 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17062 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17065 #define ARM_VARIANT & arm_ext_sec
17066 #undef THUMB_VARIANT
17067 #define THUMB_VARIANT & arm_ext_sec
17069 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17072 #define ARM_VARIANT & arm_ext_v6t2
17073 #undef THUMB_VARIANT
17074 #define THUMB_VARIANT & arm_ext_v6t2
17076 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17077 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17078 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17079 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17081 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17082 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17083 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17084 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17086 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17087 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17088 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17089 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17091 /* Thumb-only instructions. */
17093 #define ARM_VARIANT NULL
17094 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17095 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17097 /* ARM does not really have an IT instruction, so always allow it.
17098 The opcode is copied from Thumb in order to allow warnings in
17099 -mimplicit-it=[never | arm] modes. */
17101 #define ARM_VARIANT & arm_ext_v1
17103 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17104 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17105 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17106 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17107 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17108 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17109 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17110 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17111 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17112 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17113 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17114 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17115 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17116 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17117 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17118 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17119 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17120 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17122 /* Thumb2 only instructions. */
17124 #define ARM_VARIANT NULL
17126 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17127 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17128 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17129 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17130 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17131 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17133 /* Thumb-2 hardware division instructions (R and M profiles only). */
17134 #undef THUMB_VARIANT
17135 #define THUMB_VARIANT & arm_ext_div
17137 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17138 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17140 /* ARM V6M/V7 instructions. */
17142 #define ARM_VARIANT & arm_ext_barrier
17143 #undef THUMB_VARIANT
17144 #define THUMB_VARIANT & arm_ext_barrier
17146 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17147 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17148 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17150 /* ARM V7 instructions. */
17152 #define ARM_VARIANT & arm_ext_v7
17153 #undef THUMB_VARIANT
17154 #define THUMB_VARIANT & arm_ext_v7
17156 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17157 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17160 #define ARM_VARIANT & arm_ext_mp
17161 #undef THUMB_VARIANT
17162 #define THUMB_VARIANT & arm_ext_mp
17164 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17167 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17169 cCE("wfs", e200110
, 1, (RR
), rd
),
17170 cCE("rfs", e300110
, 1, (RR
), rd
),
17171 cCE("wfc", e400110
, 1, (RR
), rd
),
17172 cCE("rfc", e500110
, 1, (RR
), rd
),
17174 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17175 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17176 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17177 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17179 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17180 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17181 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17182 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17184 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17185 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17186 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17187 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17188 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17189 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17190 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17191 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17192 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17193 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17194 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17195 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17197 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17198 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17199 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17200 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17201 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17202 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17203 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17204 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17205 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17206 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17207 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17208 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17210 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17211 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17212 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17213 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17214 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17215 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17216 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17217 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17218 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17219 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17220 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17221 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17223 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17224 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17225 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17226 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17227 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17228 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17229 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17230 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17231 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17232 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17233 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17234 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17236 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17237 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17238 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17239 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17240 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17241 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17242 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17243 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17244 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17245 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17246 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17247 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17249 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17250 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17251 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17252 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17253 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17254 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17255 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17256 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17257 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17258 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17259 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17260 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17262 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17263 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17264 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17265 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17266 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17267 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17268 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17269 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17270 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17271 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17272 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17273 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17275 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17276 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17277 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17278 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17279 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17280 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17281 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17282 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17283 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17284 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17285 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17286 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17288 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17289 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17290 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17291 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17292 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17293 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17294 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17295 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17296 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17297 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17298 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17299 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17301 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17302 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17303 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17304 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17305 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17306 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17307 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17308 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17309 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17310 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17311 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17312 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17314 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17315 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17316 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17317 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17318 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17319 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17320 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17321 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17322 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17323 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17324 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17325 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17327 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17328 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17329 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17330 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17331 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17332 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17333 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17334 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17335 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17336 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17337 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17338 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17340 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17341 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17342 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17343 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17344 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17345 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17346 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17347 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17348 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17349 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17350 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17351 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17353 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17354 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17355 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17356 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17357 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17358 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17359 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17360 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17361 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17362 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17363 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17364 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17366 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17367 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17368 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17369 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17370 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17371 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17372 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17373 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17374 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17375 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17376 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17377 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17379 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17380 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17381 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17382 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17383 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17384 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17385 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17386 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17387 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17388 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17389 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17390 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17392 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17393 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17394 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17395 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17396 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17397 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17398 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17399 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17400 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17401 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17402 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17403 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17405 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17406 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17407 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17408 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17409 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17410 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17411 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17412 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17413 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17414 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17415 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17416 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17418 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17419 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17420 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17421 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17422 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17423 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17424 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17425 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17426 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17427 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17428 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17429 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17431 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17432 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17433 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17434 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17435 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17436 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17437 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17438 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17439 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17440 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17441 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17442 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17444 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17445 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17446 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17447 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17448 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17449 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17450 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17451 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17452 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17453 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17454 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17455 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17457 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17458 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17459 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17460 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17461 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17462 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17463 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17464 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17465 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17466 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17467 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17468 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17470 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17471 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17472 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17473 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17474 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17475 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17476 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17477 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17478 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17479 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17480 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17481 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17483 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17484 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17485 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17486 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17487 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17488 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17489 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17490 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17491 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17492 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17493 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17494 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17496 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17497 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17498 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17499 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17500 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17501 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17502 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17503 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17504 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17505 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17506 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17507 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17509 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17510 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17511 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17512 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17513 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17514 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17515 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17516 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17517 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17518 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17519 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17520 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17522 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17523 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17524 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17525 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17526 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17527 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17528 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17529 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17530 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17531 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17532 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17533 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17535 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17536 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17537 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17538 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17539 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17540 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17541 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17542 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17543 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17544 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17545 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17546 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17548 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17549 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17550 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17551 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17552 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17553 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17554 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17555 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17556 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17557 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17558 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17559 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17561 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17562 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17563 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17564 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17566 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17567 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17568 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17569 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17570 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17571 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17572 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17573 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17574 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17575 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17576 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17577 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17579 /* The implementation of the FIX instruction is broken on some
17580 assemblers, in that it accepts a precision specifier as well as a
17581 rounding specifier, despite the fact that this is meaningless.
17582 To be more compatible, we accept it as well, though of course it
17583 does not set any bits. */
17584 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17585 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17586 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17587 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17588 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17589 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17590 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17591 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17592 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17593 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17594 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17595 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17596 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17598 /* Instructions that were new with the real FPA, call them V2. */
17600 #define ARM_VARIANT & fpu_fpa_ext_v2
17602 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17603 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17604 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17605 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17606 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17607 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17610 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17612 /* Moves and type conversions. */
17613 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17614 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17615 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17616 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17617 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17618 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17619 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17620 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17621 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17622 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17623 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17624 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17625 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17626 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17628 /* Memory operations. */
17629 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17630 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17631 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17632 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17633 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17634 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17635 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17636 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17637 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17638 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17639 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17640 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17641 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17642 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17643 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17644 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17645 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17646 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17648 /* Monadic operations. */
17649 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17650 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17651 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17653 /* Dyadic operations. */
17654 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17655 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17656 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17657 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17658 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17659 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17660 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17661 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17662 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17665 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17666 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17667 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17668 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17670 /* Double precision load/store are still present on single precision
17671 implementations. */
17672 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17673 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17674 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17675 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17676 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17677 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17678 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17679 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17680 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17681 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17684 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17686 /* Moves and type conversions. */
17687 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17688 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17689 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17690 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17691 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17692 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17693 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17694 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17695 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17696 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17697 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17698 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17699 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17701 /* Monadic operations. */
17702 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17703 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17704 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17706 /* Dyadic operations. */
17707 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17708 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17709 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17710 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17711 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17712 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17713 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17714 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17715 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17718 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17719 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17720 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17721 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17724 #define ARM_VARIANT & fpu_vfp_ext_v2
17726 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17727 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17728 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17729 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17731 /* Instructions which may belong to either the Neon or VFP instruction sets.
17732 Individual encoder functions perform additional architecture checks. */
17734 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17735 #undef THUMB_VARIANT
17736 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17738 /* These mnemonics are unique to VFP. */
17739 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17740 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17741 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17742 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17743 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17744 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17745 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17746 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17747 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17748 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17750 /* Mnemonics shared by Neon and VFP. */
17751 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17752 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17753 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17755 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17756 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17758 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17759 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17761 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17762 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17763 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17764 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17765 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17766 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17767 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17768 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17770 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17771 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17772 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17773 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17776 /* NOTE: All VMOV encoding is special-cased! */
17777 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17778 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17780 #undef THUMB_VARIANT
17781 #define THUMB_VARIANT & fpu_neon_ext_v1
17783 #define ARM_VARIANT & fpu_neon_ext_v1
17785 /* Data processing with three registers of the same length. */
17786 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17787 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17788 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17789 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17790 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17791 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17792 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17793 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17794 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17795 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17796 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17797 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17798 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17799 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17800 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17801 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17802 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17803 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17804 /* If not immediate, fall back to neon_dyadic_i64_su.
17805 shl_imm should accept I8 I16 I32 I64,
17806 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17807 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17808 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17809 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17810 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17811 /* Logic ops, types optional & ignored. */
17812 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17813 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17814 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17815 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17816 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17817 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17818 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17819 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17820 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17821 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17822 /* Bitfield ops, untyped. */
17823 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17824 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17825 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17826 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17827 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17828 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17829 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17830 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17831 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17832 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17833 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17834 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17835 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17836 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17837 back to neon_dyadic_if_su. */
17838 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17839 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17840 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17841 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17842 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17843 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17844 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17845 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17846 /* Comparison. Type I8 I16 I32 F32. */
17847 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17848 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17849 /* As above, D registers only. */
17850 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17851 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17852 /* Int and float variants, signedness unimportant. */
17853 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17854 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17855 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17856 /* Add/sub take types I8 I16 I32 I64 F32. */
17857 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17858 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17859 /* vtst takes sizes 8, 16, 32. */
17860 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17861 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17862 /* VMUL takes I8 I16 I32 F32 P8. */
17863 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17864 /* VQD{R}MULH takes S16 S32. */
17865 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17866 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17867 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17868 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17869 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17870 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17871 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17872 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17873 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17874 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17875 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17876 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17877 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17878 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17879 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17880 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17882 /* Two address, int/float. Types S8 S16 S32 F32. */
17883 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17884 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17886 /* Data processing with two registers and a shift amount. */
17887 /* Right shifts, and variants with rounding.
17888 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17889 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17890 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17891 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17892 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17893 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17894 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17895 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17896 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17897 /* Shift and insert. Sizes accepted 8 16 32 64. */
17898 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17899 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17900 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17901 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17902 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17903 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17904 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17905 /* Right shift immediate, saturating & narrowing, with rounding variants.
17906 Types accepted S16 S32 S64 U16 U32 U64. */
17907 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17908 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17909 /* As above, unsigned. Types accepted S16 S32 S64. */
17910 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17911 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17912 /* Right shift narrowing. Types accepted I16 I32 I64. */
17913 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17914 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17915 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17916 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17917 /* CVT with optional immediate for fixed-point variant. */
17918 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17920 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17921 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17923 /* Data processing, three registers of different lengths. */
17924 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17925 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17926 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17927 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17928 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17929 /* If not scalar, fall back to neon_dyadic_long.
17930 Vector types as above, scalar types S16 S32 U16 U32. */
17931 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17932 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17933 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17934 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17935 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17936 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17937 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17938 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17939 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17940 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17941 /* Saturating doubling multiplies. Types S16 S32. */
17942 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17943 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17944 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17945 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17946 S16 S32 U16 U32. */
17947 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17949 /* Extract. Size 8. */
17950 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17951 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17953 /* Two registers, miscellaneous. */
17954 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17955 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17956 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17957 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17958 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17959 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17960 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17961 /* Vector replicate. Sizes 8 16 32. */
17962 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17963 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17964 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17965 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17966 /* VMOVN. Types I16 I32 I64. */
17967 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17968 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17969 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17970 /* VQMOVUN. Types S16 S32 S64. */
17971 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17972 /* VZIP / VUZP. Sizes 8 16 32. */
17973 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17974 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17975 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17976 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17977 /* VQABS / VQNEG. Types S8 S16 S32. */
17978 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17979 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17980 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17981 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17982 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17983 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17984 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17985 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17986 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17987 /* Reciprocal estimates. Types U32 F32. */
17988 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17989 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17990 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17991 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17992 /* VCLS. Types S8 S16 S32. */
17993 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17994 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17995 /* VCLZ. Types I8 I16 I32. */
17996 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17997 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17998 /* VCNT. Size 8. */
17999 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18000 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18001 /* Two address, untyped. */
18002 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18003 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18004 /* VTRN. Sizes 8 16 32. */
18005 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18006 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18008 /* Table lookup. Size 8. */
18009 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18010 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18012 #undef THUMB_VARIANT
18013 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18015 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18017 /* Neon element/structure load/store. */
18018 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18019 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18020 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18021 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18022 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18023 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18024 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18025 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18027 #undef THUMB_VARIANT
18028 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18030 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18031 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18032 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18033 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18034 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18035 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18036 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18037 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18038 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18039 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18041 #undef THUMB_VARIANT
18042 #define THUMB_VARIANT & fpu_vfp_ext_v3
18044 #define ARM_VARIANT & fpu_vfp_ext_v3
18046 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18047 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18048 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18049 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18050 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18051 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18052 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18053 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18054 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18057 #define ARM_VARIANT &fpu_vfp_ext_fma
18058 #undef THUMB_VARIANT
18059 #define THUMB_VARIANT &fpu_vfp_ext_fma
18060 /* Mnemonics shared by Neon and VFP. These are included in the
18061 VFP FMA variant; NEON and VFP FMA always includes the NEON
18062 FMA instructions. */
18063 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18064 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18065 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18066 the v form should always be used. */
18067 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18068 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18069 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18070 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18071 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18072 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18074 #undef THUMB_VARIANT
18076 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18078 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18079 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18080 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18081 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18082 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18083 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18084 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18085 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18088 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18090 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18091 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18092 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18093 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18094 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18095 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18096 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18097 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18098 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18099 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18100 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18101 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18102 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18103 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18104 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18105 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18106 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18107 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18108 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18109 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18110 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18111 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18112 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18113 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18114 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18115 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18116 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18117 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18118 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18119 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18120 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18121 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18122 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18123 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18124 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18125 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18126 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18127 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18128 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18129 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18130 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18131 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18132 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18133 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18134 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18135 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18136 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18137 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18138 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18139 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18140 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18141 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18142 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18143 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18144 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18145 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18146 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18147 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18148 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18149 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18150 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18151 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18152 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18153 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18154 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18155 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18156 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18157 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18158 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18159 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18160 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18161 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18162 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18163 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18164 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18165 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18166 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18167 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18168 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18169 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18170 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18171 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18172 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18173 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18174 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18175 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18176 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18177 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18178 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18179 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18180 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18181 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18182 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18183 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18184 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18185 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18186 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18187 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18188 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18189 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18190 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18191 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18192 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18193 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18194 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18195 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18196 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18197 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18198 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18199 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18200 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18201 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18202 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18203 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18204 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18205 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18206 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18207 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18208 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18209 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18210 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18211 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18212 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18213 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18214 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18215 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18216 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18217 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18218 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18219 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18220 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18221 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18222 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18223 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18224 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18225 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18226 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18227 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18228 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18229 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18230 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18231 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18232 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18233 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18234 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18235 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18236 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18237 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18238 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18239 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18240 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18241 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18242 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18243 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18244 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18245 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18246 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18247 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18248 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18249 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18250 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18251 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18254 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18256 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18257 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18258 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18259 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18260 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18261 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18262 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18263 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18264 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18265 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18266 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18267 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18268 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18269 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18270 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18271 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18272 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18273 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18274 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18275 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18276 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18277 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18278 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18279 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18280 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18281 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18282 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18283 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18284 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18285 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18286 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18287 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18288 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18289 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18290 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18291 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18292 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18293 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18294 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18295 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18296 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18297 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18298 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18299 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18300 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18301 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18302 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18303 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18304 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18305 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18306 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18307 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18308 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18309 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18310 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18311 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18312 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18315 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18317 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18318 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18319 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18320 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18321 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18322 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18323 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18324 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18325 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18326 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18327 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18328 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18329 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18330 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18331 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18332 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18333 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18334 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18335 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18336 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18337 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18338 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18339 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18340 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18341 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18342 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18343 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18344 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18345 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18346 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18347 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18348 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18349 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18350 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18351 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18352 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18353 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18354 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18355 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18356 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18357 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18358 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18359 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18360 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18361 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18362 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18363 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18364 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18365 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18366 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18367 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18368 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18369 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18370 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18371 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18372 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18373 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18374 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18375 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18376 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18377 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18378 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18379 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18380 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18381 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18382 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18383 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18384 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18385 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18386 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18387 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18388 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18389 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18390 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18391 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18392 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18395 #undef THUMB_VARIANT
18422 /* MD interface: bits in the object file. */
18424 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18425 for use in the a.out file, and stores them in the array pointed to by buf.
18426 This knows about the endian-ness of the target machine and does
18427 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18428 2 (short) and 4 (long) Floating numbers are put out as a series of
18429 LITTLENUMS (shorts, here at least). */
18432 md_number_to_chars (char * buf
, valueT val
, int n
)
18434 if (target_big_endian
)
18435 number_to_chars_bigendian (buf
, val
, n
);
18437 number_to_chars_littleendian (buf
, val
, n
);
18441 md_chars_to_number (char * buf
, int n
)
18444 unsigned char * where
= (unsigned char *) buf
;
18446 if (target_big_endian
)
18451 result
|= (*where
++ & 255);
18459 result
|= (where
[n
] & 255);
18466 /* MD interface: Sections. */
18468 /* Estimate the size of a frag before relaxing. Assume everything fits in
18472 md_estimate_size_before_relax (fragS
* fragp
,
18473 segT segtype ATTRIBUTE_UNUSED
)
18479 /* Convert a machine dependent frag. */
18482 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18484 unsigned long insn
;
18485 unsigned long old_op
;
18493 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18495 old_op
= bfd_get_16(abfd
, buf
);
18496 if (fragp
->fr_symbol
)
18498 exp
.X_op
= O_symbol
;
18499 exp
.X_add_symbol
= fragp
->fr_symbol
;
18503 exp
.X_op
= O_constant
;
18505 exp
.X_add_number
= fragp
->fr_offset
;
18506 opcode
= fragp
->fr_subtype
;
18509 case T_MNEM_ldr_pc
:
18510 case T_MNEM_ldr_pc2
:
18511 case T_MNEM_ldr_sp
:
18512 case T_MNEM_str_sp
:
18519 if (fragp
->fr_var
== 4)
18521 insn
= THUMB_OP32 (opcode
);
18522 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18524 insn
|= (old_op
& 0x700) << 4;
18528 insn
|= (old_op
& 7) << 12;
18529 insn
|= (old_op
& 0x38) << 13;
18531 insn
|= 0x00000c00;
18532 put_thumb32_insn (buf
, insn
);
18533 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18537 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18539 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18542 if (fragp
->fr_var
== 4)
18544 insn
= THUMB_OP32 (opcode
);
18545 insn
|= (old_op
& 0xf0) << 4;
18546 put_thumb32_insn (buf
, insn
);
18547 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18551 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18552 exp
.X_add_number
-= 4;
18560 if (fragp
->fr_var
== 4)
18562 int r0off
= (opcode
== T_MNEM_mov
18563 || opcode
== T_MNEM_movs
) ? 0 : 8;
18564 insn
= THUMB_OP32 (opcode
);
18565 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18566 insn
|= (old_op
& 0x700) << r0off
;
18567 put_thumb32_insn (buf
, insn
);
18568 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18572 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18577 if (fragp
->fr_var
== 4)
18579 insn
= THUMB_OP32(opcode
);
18580 put_thumb32_insn (buf
, insn
);
18581 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18584 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18588 if (fragp
->fr_var
== 4)
18590 insn
= THUMB_OP32(opcode
);
18591 insn
|= (old_op
& 0xf00) << 14;
18592 put_thumb32_insn (buf
, insn
);
18593 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18596 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18599 case T_MNEM_add_sp
:
18600 case T_MNEM_add_pc
:
18601 case T_MNEM_inc_sp
:
18602 case T_MNEM_dec_sp
:
18603 if (fragp
->fr_var
== 4)
18605 /* ??? Choose between add and addw. */
18606 insn
= THUMB_OP32 (opcode
);
18607 insn
|= (old_op
& 0xf0) << 4;
18608 put_thumb32_insn (buf
, insn
);
18609 if (opcode
== T_MNEM_add_pc
)
18610 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18612 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18615 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18623 if (fragp
->fr_var
== 4)
18625 insn
= THUMB_OP32 (opcode
);
18626 insn
|= (old_op
& 0xf0) << 4;
18627 insn
|= (old_op
& 0xf) << 16;
18628 put_thumb32_insn (buf
, insn
);
18629 if (insn
& (1 << 20))
18630 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18632 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18635 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18641 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18642 (enum bfd_reloc_code_real
) reloc_type
);
18643 fixp
->fx_file
= fragp
->fr_file
;
18644 fixp
->fx_line
= fragp
->fr_line
;
18645 fragp
->fr_fix
+= fragp
->fr_var
;
18648 /* Return the size of a relaxable immediate operand instruction.
18649 SHIFT and SIZE specify the form of the allowable immediate. */
18651 relax_immediate (fragS
*fragp
, int size
, int shift
)
18657 /* ??? Should be able to do better than this. */
18658 if (fragp
->fr_symbol
)
18661 low
= (1 << shift
) - 1;
18662 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18663 offset
= fragp
->fr_offset
;
18664 /* Force misaligned offsets to 32-bit variant. */
18667 if (offset
& ~mask
)
18672 /* Get the address of a symbol during relaxation. */
18674 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18680 sym
= fragp
->fr_symbol
;
18681 sym_frag
= symbol_get_frag (sym
);
18682 know (S_GET_SEGMENT (sym
) != absolute_section
18683 || sym_frag
== &zero_address_frag
);
18684 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18686 /* If frag has yet to be reached on this pass, assume it will
18687 move by STRETCH just as we did. If this is not so, it will
18688 be because some frag between grows, and that will force
18692 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18696 /* Adjust stretch for any alignment frag. Note that if have
18697 been expanding the earlier code, the symbol may be
18698 defined in what appears to be an earlier frag. FIXME:
18699 This doesn't handle the fr_subtype field, which specifies
18700 a maximum number of bytes to skip when doing an
18702 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18704 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18707 stretch
= - ((- stretch
)
18708 & ~ ((1 << (int) f
->fr_offset
) - 1));
18710 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18722 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18725 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18730 /* Assume worst case for symbols not known to be in the same section. */
18731 if (fragp
->fr_symbol
== NULL
18732 || !S_IS_DEFINED (fragp
->fr_symbol
)
18733 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18734 || S_IS_WEAK (fragp
->fr_symbol
))
18737 val
= relaxed_symbol_addr (fragp
, stretch
);
18738 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18739 addr
= (addr
+ 4) & ~3;
18740 /* Force misaligned targets to 32-bit variant. */
18744 if (val
< 0 || val
> 1020)
18749 /* Return the size of a relaxable add/sub immediate instruction. */
18751 relax_addsub (fragS
*fragp
, asection
*sec
)
18756 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18757 op
= bfd_get_16(sec
->owner
, buf
);
18758 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18759 return relax_immediate (fragp
, 8, 0);
18761 return relax_immediate (fragp
, 3, 0);
18765 /* Return the size of a relaxable branch instruction. BITS is the
18766 size of the offset field in the narrow instruction. */
18769 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18775 /* Assume worst case for symbols not known to be in the same section. */
18776 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18777 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18778 || S_IS_WEAK (fragp
->fr_symbol
))
18782 if (S_IS_DEFINED (fragp
->fr_symbol
)
18783 && ARM_IS_FUNC (fragp
->fr_symbol
))
18787 val
= relaxed_symbol_addr (fragp
, stretch
);
18788 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18791 /* Offset is a signed value *2 */
18793 if (val
>= limit
|| val
< -limit
)
18799 /* Relax a machine dependent frag. This returns the amount by which
18800 the current size of the frag should change. */
18803 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18808 oldsize
= fragp
->fr_var
;
18809 switch (fragp
->fr_subtype
)
18811 case T_MNEM_ldr_pc2
:
18812 newsize
= relax_adr (fragp
, sec
, stretch
);
18814 case T_MNEM_ldr_pc
:
18815 case T_MNEM_ldr_sp
:
18816 case T_MNEM_str_sp
:
18817 newsize
= relax_immediate (fragp
, 8, 2);
18821 newsize
= relax_immediate (fragp
, 5, 2);
18825 newsize
= relax_immediate (fragp
, 5, 1);
18829 newsize
= relax_immediate (fragp
, 5, 0);
18832 newsize
= relax_adr (fragp
, sec
, stretch
);
18838 newsize
= relax_immediate (fragp
, 8, 0);
18841 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18844 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18846 case T_MNEM_add_sp
:
18847 case T_MNEM_add_pc
:
18848 newsize
= relax_immediate (fragp
, 8, 2);
18850 case T_MNEM_inc_sp
:
18851 case T_MNEM_dec_sp
:
18852 newsize
= relax_immediate (fragp
, 7, 2);
18858 newsize
= relax_addsub (fragp
, sec
);
18864 fragp
->fr_var
= newsize
;
18865 /* Freeze wide instructions that are at or before the same location as
18866 in the previous pass. This avoids infinite loops.
18867 Don't freeze them unconditionally because targets may be artificially
18868 misaligned by the expansion of preceding frags. */
18869 if (stretch
<= 0 && newsize
> 2)
18871 md_convert_frag (sec
->owner
, sec
, fragp
);
18875 return newsize
- oldsize
;
18878 /* Round up a section size to the appropriate boundary. */
18881 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18884 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18885 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18887 /* For a.out, force the section size to be aligned. If we don't do
18888 this, BFD will align it for us, but it will not write out the
18889 final bytes of the section. This may be a bug in BFD, but it is
18890 easier to fix it here since that is how the other a.out targets
18894 align
= bfd_get_section_alignment (stdoutput
, segment
);
18895 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18902 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18903 of an rs_align_code fragment. */
18906 arm_handle_align (fragS
* fragP
)
18908 static char const arm_noop
[2][2][4] =
18911 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18912 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18915 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18916 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18919 static char const thumb_noop
[2][2][2] =
18922 {0xc0, 0x46}, /* LE */
18923 {0x46, 0xc0}, /* BE */
18926 {0x00, 0xbf}, /* LE */
18927 {0xbf, 0x00} /* BE */
18930 static char const wide_thumb_noop
[2][4] =
18931 { /* Wide Thumb-2 */
18932 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18933 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18936 unsigned bytes
, fix
, noop_size
;
18939 const char *narrow_noop
= NULL
;
18944 if (fragP
->fr_type
!= rs_align_code
)
18947 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18948 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18951 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18952 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18954 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18956 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18958 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18960 narrow_noop
= thumb_noop
[1][target_big_endian
];
18961 noop
= wide_thumb_noop
[target_big_endian
];
18964 noop
= thumb_noop
[0][target_big_endian
];
18972 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18973 [target_big_endian
];
18980 fragP
->fr_var
= noop_size
;
18982 if (bytes
& (noop_size
- 1))
18984 fix
= bytes
& (noop_size
- 1);
18986 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18988 memset (p
, 0, fix
);
18995 if (bytes
& noop_size
)
18997 /* Insert a narrow noop. */
18998 memcpy (p
, narrow_noop
, noop_size
);
19000 bytes
-= noop_size
;
19004 /* Use wide noops for the remainder */
19008 while (bytes
>= noop_size
)
19010 memcpy (p
, noop
, noop_size
);
19012 bytes
-= noop_size
;
19016 fragP
->fr_fix
+= fix
;
19019 /* Called from md_do_align. Used to create an alignment
19020 frag in a code section. */
19023 arm_frag_align_code (int n
, int max
)
19027 /* We assume that there will never be a requirement
19028 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19029 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19034 _("alignments greater than %d bytes not supported in .text sections."),
19035 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19036 as_fatal ("%s", err_msg
);
19039 p
= frag_var (rs_align_code
,
19040 MAX_MEM_FOR_RS_ALIGN_CODE
,
19042 (relax_substateT
) max
,
19049 /* Perform target specific initialisation of a frag.
19050 Note - despite the name this initialisation is not done when the frag
19051 is created, but only when its type is assigned. A frag can be created
19052 and used a long time before its type is set, so beware of assuming that
19053 this initialisationis performed first. */
19057 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19059 /* Record whether this frag is in an ARM or a THUMB area. */
19060 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19063 #else /* OBJ_ELF is defined. */
19065 arm_init_frag (fragS
* fragP
, int max_chars
)
19067 /* If the current ARM vs THUMB mode has not already
19068 been recorded into this frag then do so now. */
19069 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19071 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19073 /* Record a mapping symbol for alignment frags. We will delete this
19074 later if the alignment ends up empty. */
19075 switch (fragP
->fr_type
)
19078 case rs_align_test
:
19080 mapping_state_2 (MAP_DATA
, max_chars
);
19082 case rs_align_code
:
19083 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19091 /* When we change sections we need to issue a new mapping symbol. */
19094 arm_elf_change_section (void)
19096 /* Link an unlinked unwind index table section to the .text section. */
19097 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19098 && elf_linked_to_section (now_seg
) == NULL
)
19099 elf_linked_to_section (now_seg
) = text_section
;
19103 arm_elf_section_type (const char * str
, size_t len
)
19105 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19106 return SHT_ARM_EXIDX
;
19111 /* Code to deal with unwinding tables. */
19113 static void add_unwind_adjustsp (offsetT
);
19115 /* Generate any deferred unwind frame offset. */
19118 flush_pending_unwind (void)
19122 offset
= unwind
.pending_offset
;
19123 unwind
.pending_offset
= 0;
19125 add_unwind_adjustsp (offset
);
19128 /* Add an opcode to this list for this function. Two-byte opcodes should
19129 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19133 add_unwind_opcode (valueT op
, int length
)
19135 /* Add any deferred stack adjustment. */
19136 if (unwind
.pending_offset
)
19137 flush_pending_unwind ();
19139 unwind
.sp_restored
= 0;
19141 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19143 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19144 if (unwind
.opcodes
)
19145 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19146 unwind
.opcode_alloc
);
19148 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19153 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19155 unwind
.opcode_count
++;
19159 /* Add unwind opcodes to adjust the stack pointer. */
19162 add_unwind_adjustsp (offsetT offset
)
19166 if (offset
> 0x200)
19168 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19173 /* Long form: 0xb2, uleb128. */
19174 /* This might not fit in a word so add the individual bytes,
19175 remembering the list is built in reverse order. */
19176 o
= (valueT
) ((offset
- 0x204) >> 2);
19178 add_unwind_opcode (0, 1);
19180 /* Calculate the uleb128 encoding of the offset. */
19184 bytes
[n
] = o
& 0x7f;
19190 /* Add the insn. */
19192 add_unwind_opcode (bytes
[n
- 1], 1);
19193 add_unwind_opcode (0xb2, 1);
19195 else if (offset
> 0x100)
19197 /* Two short opcodes. */
19198 add_unwind_opcode (0x3f, 1);
19199 op
= (offset
- 0x104) >> 2;
19200 add_unwind_opcode (op
, 1);
19202 else if (offset
> 0)
19204 /* Short opcode. */
19205 op
= (offset
- 4) >> 2;
19206 add_unwind_opcode (op
, 1);
19208 else if (offset
< 0)
19211 while (offset
> 0x100)
19213 add_unwind_opcode (0x7f, 1);
19216 op
= ((offset
- 4) >> 2) | 0x40;
19217 add_unwind_opcode (op
, 1);
19221 /* Finish the list of unwind opcodes for this function. */
19223 finish_unwind_opcodes (void)
19227 if (unwind
.fp_used
)
19229 /* Adjust sp as necessary. */
19230 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19231 flush_pending_unwind ();
19233 /* After restoring sp from the frame pointer. */
19234 op
= 0x90 | unwind
.fp_reg
;
19235 add_unwind_opcode (op
, 1);
19238 flush_pending_unwind ();
19242 /* Start an exception table entry. If idx is nonzero this is an index table
19246 start_unwind_section (const segT text_seg
, int idx
)
19248 const char * text_name
;
19249 const char * prefix
;
19250 const char * prefix_once
;
19251 const char * group_name
;
19255 size_t sec_name_len
;
19262 prefix
= ELF_STRING_ARM_unwind
;
19263 prefix_once
= ELF_STRING_ARM_unwind_once
;
19264 type
= SHT_ARM_EXIDX
;
19268 prefix
= ELF_STRING_ARM_unwind_info
;
19269 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19270 type
= SHT_PROGBITS
;
19273 text_name
= segment_name (text_seg
);
19274 if (streq (text_name
, ".text"))
19277 if (strncmp (text_name
, ".gnu.linkonce.t.",
19278 strlen (".gnu.linkonce.t.")) == 0)
19280 prefix
= prefix_once
;
19281 text_name
+= strlen (".gnu.linkonce.t.");
19284 prefix_len
= strlen (prefix
);
19285 text_len
= strlen (text_name
);
19286 sec_name_len
= prefix_len
+ text_len
;
19287 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19288 memcpy (sec_name
, prefix
, prefix_len
);
19289 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19290 sec_name
[prefix_len
+ text_len
] = '\0';
19296 /* Handle COMDAT group. */
19297 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19299 group_name
= elf_group_name (text_seg
);
19300 if (group_name
== NULL
)
19302 as_bad (_("Group section `%s' has no group signature"),
19303 segment_name (text_seg
));
19304 ignore_rest_of_line ();
19307 flags
|= SHF_GROUP
;
19311 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19313 /* Set the section link for index tables. */
19315 elf_linked_to_section (now_seg
) = text_seg
;
19319 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19320 personality routine data. Returns zero, or the index table value for
19321 and inline entry. */
19324 create_unwind_entry (int have_data
)
19329 /* The current word of data. */
19331 /* The number of bytes left in this word. */
19334 finish_unwind_opcodes ();
19336 /* Remember the current text section. */
19337 unwind
.saved_seg
= now_seg
;
19338 unwind
.saved_subseg
= now_subseg
;
19340 start_unwind_section (now_seg
, 0);
19342 if (unwind
.personality_routine
== NULL
)
19344 if (unwind
.personality_index
== -2)
19347 as_bad (_("handlerdata in cantunwind frame"));
19348 return 1; /* EXIDX_CANTUNWIND. */
19351 /* Use a default personality routine if none is specified. */
19352 if (unwind
.personality_index
== -1)
19354 if (unwind
.opcode_count
> 3)
19355 unwind
.personality_index
= 1;
19357 unwind
.personality_index
= 0;
19360 /* Space for the personality routine entry. */
19361 if (unwind
.personality_index
== 0)
19363 if (unwind
.opcode_count
> 3)
19364 as_bad (_("too many unwind opcodes for personality routine 0"));
19368 /* All the data is inline in the index table. */
19371 while (unwind
.opcode_count
> 0)
19373 unwind
.opcode_count
--;
19374 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19378 /* Pad with "finish" opcodes. */
19380 data
= (data
<< 8) | 0xb0;
19387 /* We get two opcodes "free" in the first word. */
19388 size
= unwind
.opcode_count
- 2;
19391 /* An extra byte is required for the opcode count. */
19392 size
= unwind
.opcode_count
+ 1;
19394 size
= (size
+ 3) >> 2;
19396 as_bad (_("too many unwind opcodes"));
19398 frag_align (2, 0, 0);
19399 record_alignment (now_seg
, 2);
19400 unwind
.table_entry
= expr_build_dot ();
19402 /* Allocate the table entry. */
19403 ptr
= frag_more ((size
<< 2) + 4);
19404 where
= frag_now_fix () - ((size
<< 2) + 4);
19406 switch (unwind
.personality_index
)
19409 /* ??? Should this be a PLT generating relocation? */
19410 /* Custom personality routine. */
19411 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19412 BFD_RELOC_ARM_PREL31
);
19417 /* Set the first byte to the number of additional words. */
19422 /* ABI defined personality routines. */
19424 /* Three opcodes bytes are packed into the first word. */
19431 /* The size and first two opcode bytes go in the first word. */
19432 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19437 /* Should never happen. */
19441 /* Pack the opcodes into words (MSB first), reversing the list at the same
19443 while (unwind
.opcode_count
> 0)
19447 md_number_to_chars (ptr
, data
, 4);
19452 unwind
.opcode_count
--;
19454 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19457 /* Finish off the last word. */
19460 /* Pad with "finish" opcodes. */
19462 data
= (data
<< 8) | 0xb0;
19464 md_number_to_chars (ptr
, data
, 4);
19469 /* Add an empty descriptor if there is no user-specified data. */
19470 ptr
= frag_more (4);
19471 md_number_to_chars (ptr
, 0, 4);
19478 /* Initialize the DWARF-2 unwind information for this procedure. */
19481 tc_arm_frame_initial_instructions (void)
19483 cfi_add_CFA_def_cfa (REG_SP
, 0);
19485 #endif /* OBJ_ELF */
19487 /* Convert REGNAME to a DWARF-2 register number. */
19490 tc_arm_regname_to_dw2regnum (char *regname
)
19492 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19502 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19506 exp
.X_op
= O_secrel
;
19507 exp
.X_add_symbol
= symbol
;
19508 exp
.X_add_number
= 0;
19509 emit_expr (&exp
, size
);
19513 /* MD interface: Symbol and relocation handling. */
19515 /* Return the address within the segment that a PC-relative fixup is
19516 relative to. For ARM, PC-relative fixups applied to instructions
19517 are generally relative to the location of the fixup plus 8 bytes.
19518 Thumb branches are offset by 4, and Thumb loads relative to PC
19519 require special handling. */
19522 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19524 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19526 /* If this is pc-relative and we are going to emit a relocation
19527 then we just want to put out any pipeline compensation that the linker
19528 will need. Otherwise we want to use the calculated base.
19529 For WinCE we skip the bias for externals as well, since this
19530 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19532 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19533 || (arm_force_relocation (fixP
)
19535 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19541 switch (fixP
->fx_r_type
)
19543 /* PC relative addressing on the Thumb is slightly odd as the
19544 bottom two bits of the PC are forced to zero for the
19545 calculation. This happens *after* application of the
19546 pipeline offset. However, Thumb adrl already adjusts for
19547 this, so we need not do it again. */
19548 case BFD_RELOC_ARM_THUMB_ADD
:
19551 case BFD_RELOC_ARM_THUMB_OFFSET
:
19552 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19553 case BFD_RELOC_ARM_T32_ADD_PC12
:
19554 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19555 return (base
+ 4) & ~3;
19557 /* Thumb branches are simply offset by +4. */
19558 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19559 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19560 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19561 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19562 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19565 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19567 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19568 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19569 && ARM_IS_FUNC (fixP
->fx_addsy
)
19570 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19571 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19574 /* BLX is like branches above, but forces the low two bits of PC to
19576 case BFD_RELOC_THUMB_PCREL_BLX
:
19578 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19579 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19580 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19581 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19582 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19583 return (base
+ 4) & ~3;
19585 /* ARM mode branches are offset by +8. However, the Windows CE
19586 loader expects the relocation not to take this into account. */
19587 case BFD_RELOC_ARM_PCREL_BLX
:
19589 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19590 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19591 && ARM_IS_FUNC (fixP
->fx_addsy
)
19592 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19593 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19596 case BFD_RELOC_ARM_PCREL_CALL
:
19598 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19599 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19600 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19601 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19602 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19605 case BFD_RELOC_ARM_PCREL_BRANCH
:
19606 case BFD_RELOC_ARM_PCREL_JUMP
:
19607 case BFD_RELOC_ARM_PLT32
:
19609 /* When handling fixups immediately, because we have already
19610 discovered the value of a symbol, or the address of the frag involved
19611 we must account for the offset by +8, as the OS loader will never see the reloc.
19612 see fixup_segment() in write.c
19613 The S_IS_EXTERNAL test handles the case of global symbols.
19614 Those need the calculated base, not just the pipe compensation the linker will need. */
19616 && fixP
->fx_addsy
!= NULL
19617 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19618 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19626 /* ARM mode loads relative to PC are also offset by +8. Unlike
19627 branches, the Windows CE loader *does* expect the relocation
19628 to take this into account. */
19629 case BFD_RELOC_ARM_OFFSET_IMM
:
19630 case BFD_RELOC_ARM_OFFSET_IMM8
:
19631 case BFD_RELOC_ARM_HWLITERAL
:
19632 case BFD_RELOC_ARM_LITERAL
:
19633 case BFD_RELOC_ARM_CP_OFF_IMM
:
19637 /* Other PC-relative relocations are un-offset. */
19643 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19644 Otherwise we have no need to default values of symbols. */
19647 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19650 if (name
[0] == '_' && name
[1] == 'G'
19651 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19655 if (symbol_find (name
))
19656 as_bad (_("GOT already in the symbol table"));
19658 GOT_symbol
= symbol_new (name
, undefined_section
,
19659 (valueT
) 0, & zero_address_frag
);
19669 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19670 computed as two separate immediate values, added together. We
19671 already know that this value cannot be computed by just one ARM
19674 static unsigned int
19675 validate_immediate_twopart (unsigned int val
,
19676 unsigned int * highpart
)
19681 for (i
= 0; i
< 32; i
+= 2)
19682 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19688 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19690 else if (a
& 0xff0000)
19692 if (a
& 0xff000000)
19694 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19698 gas_assert (a
& 0xff000000);
19699 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19702 return (a
& 0xff) | (i
<< 7);
19709 validate_offset_imm (unsigned int val
, int hwse
)
19711 if ((hwse
&& val
> 255) || val
> 4095)
19716 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19717 negative immediate constant by altering the instruction. A bit of
19722 by inverting the second operand, and
19725 by negating the second operand. */
19728 negate_data_op (unsigned long * instruction
,
19729 unsigned long value
)
19732 unsigned long negated
, inverted
;
19734 negated
= encode_arm_immediate (-value
);
19735 inverted
= encode_arm_immediate (~value
);
19737 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19740 /* First negates. */
19741 case OPCODE_SUB
: /* ADD <-> SUB */
19742 new_inst
= OPCODE_ADD
;
19747 new_inst
= OPCODE_SUB
;
19751 case OPCODE_CMP
: /* CMP <-> CMN */
19752 new_inst
= OPCODE_CMN
;
19757 new_inst
= OPCODE_CMP
;
19761 /* Now Inverted ops. */
19762 case OPCODE_MOV
: /* MOV <-> MVN */
19763 new_inst
= OPCODE_MVN
;
19768 new_inst
= OPCODE_MOV
;
19772 case OPCODE_AND
: /* AND <-> BIC */
19773 new_inst
= OPCODE_BIC
;
19778 new_inst
= OPCODE_AND
;
19782 case OPCODE_ADC
: /* ADC <-> SBC */
19783 new_inst
= OPCODE_SBC
;
19788 new_inst
= OPCODE_ADC
;
19792 /* We cannot do anything. */
19797 if (value
== (unsigned) FAIL
)
19800 *instruction
&= OPCODE_MASK
;
19801 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19805 /* Like negate_data_op, but for Thumb-2. */
19807 static unsigned int
19808 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19812 unsigned int negated
, inverted
;
19814 negated
= encode_thumb32_immediate (-value
);
19815 inverted
= encode_thumb32_immediate (~value
);
19817 rd
= (*instruction
>> 8) & 0xf;
19818 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19821 /* ADD <-> SUB. Includes CMP <-> CMN. */
19822 case T2_OPCODE_SUB
:
19823 new_inst
= T2_OPCODE_ADD
;
19827 case T2_OPCODE_ADD
:
19828 new_inst
= T2_OPCODE_SUB
;
19832 /* ORR <-> ORN. Includes MOV <-> MVN. */
19833 case T2_OPCODE_ORR
:
19834 new_inst
= T2_OPCODE_ORN
;
19838 case T2_OPCODE_ORN
:
19839 new_inst
= T2_OPCODE_ORR
;
19843 /* AND <-> BIC. TST has no inverted equivalent. */
19844 case T2_OPCODE_AND
:
19845 new_inst
= T2_OPCODE_BIC
;
19852 case T2_OPCODE_BIC
:
19853 new_inst
= T2_OPCODE_AND
;
19858 case T2_OPCODE_ADC
:
19859 new_inst
= T2_OPCODE_SBC
;
19863 case T2_OPCODE_SBC
:
19864 new_inst
= T2_OPCODE_ADC
;
19868 /* We cannot do anything. */
19873 if (value
== (unsigned int)FAIL
)
19876 *instruction
&= T2_OPCODE_MASK
;
19877 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19881 /* Read a 32-bit thumb instruction from buf. */
19882 static unsigned long
19883 get_thumb32_insn (char * buf
)
19885 unsigned long insn
;
19886 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19887 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19893 /* We usually want to set the low bit on the address of thumb function
19894 symbols. In particular .word foo - . should have the low bit set.
19895 Generic code tries to fold the difference of two symbols to
19896 a constant. Prevent this and force a relocation when the first symbols
19897 is a thumb function. */
19900 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19902 if (op
== O_subtract
19903 && l
->X_op
== O_symbol
19904 && r
->X_op
== O_symbol
19905 && THUMB_IS_FUNC (l
->X_add_symbol
))
19907 l
->X_op
= O_subtract
;
19908 l
->X_op_symbol
= r
->X_add_symbol
;
19909 l
->X_add_number
-= r
->X_add_number
;
19913 /* Process as normal. */
19917 /* Encode Thumb2 unconditional branches and calls. The encoding
19918 for the 2 are identical for the immediate values. */
19921 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19923 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19926 addressT S
, I1
, I2
, lo
, hi
;
19928 S
= (value
>> 24) & 0x01;
19929 I1
= (value
>> 23) & 0x01;
19930 I2
= (value
>> 22) & 0x01;
19931 hi
= (value
>> 12) & 0x3ff;
19932 lo
= (value
>> 1) & 0x7ff;
19933 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19934 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19935 newval
|= (S
<< 10) | hi
;
19936 newval2
&= ~T2I1I2MASK
;
19937 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19938 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19939 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19943 md_apply_fix (fixS
* fixP
,
19947 offsetT value
= * valP
;
19949 unsigned int newimm
;
19950 unsigned long temp
;
19952 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19954 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19956 /* Note whether this will delete the relocation. */
19958 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19961 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19962 consistency with the behaviour on 32-bit hosts. Remember value
19964 value
&= 0xffffffff;
19965 value
^= 0x80000000;
19966 value
-= 0x80000000;
19969 fixP
->fx_addnumber
= value
;
19971 /* Same treatment for fixP->fx_offset. */
19972 fixP
->fx_offset
&= 0xffffffff;
19973 fixP
->fx_offset
^= 0x80000000;
19974 fixP
->fx_offset
-= 0x80000000;
19976 switch (fixP
->fx_r_type
)
19978 case BFD_RELOC_NONE
:
19979 /* This will need to go in the object file. */
19983 case BFD_RELOC_ARM_IMMEDIATE
:
19984 /* We claim that this fixup has been processed here,
19985 even if in fact we generate an error because we do
19986 not have a reloc for it, so tc_gen_reloc will reject it. */
19989 if (fixP
->fx_addsy
)
19991 const char *msg
= 0;
19993 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19994 msg
= _("undefined symbol %s used as an immediate value");
19995 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19996 msg
= _("symbol %s is in a different section");
19997 else if (S_IS_WEAK (fixP
->fx_addsy
))
19998 msg
= _("symbol %s is weak and may be overridden later");
20002 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20003 msg
, S_GET_NAME (fixP
->fx_addsy
));
20008 newimm
= encode_arm_immediate (value
);
20009 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20011 /* If the instruction will fail, see if we can fix things up by
20012 changing the opcode. */
20013 if (newimm
== (unsigned int) FAIL
20014 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20016 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20017 _("invalid constant (%lx) after fixup"),
20018 (unsigned long) value
);
20022 newimm
|= (temp
& 0xfffff000);
20023 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20026 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20028 unsigned int highpart
= 0;
20029 unsigned int newinsn
= 0xe1a00000; /* nop. */
20031 if (fixP
->fx_addsy
)
20033 const char *msg
= 0;
20035 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20036 msg
= _("undefined symbol %s used as an immediate value");
20037 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20038 msg
= _("symbol %s is in a different section");
20039 else if (S_IS_WEAK (fixP
->fx_addsy
))
20040 msg
= _("symbol %s is weak and may be overridden later");
20044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20045 msg
, S_GET_NAME (fixP
->fx_addsy
));
20050 newimm
= encode_arm_immediate (value
);
20051 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20053 /* If the instruction will fail, see if we can fix things up by
20054 changing the opcode. */
20055 if (newimm
== (unsigned int) FAIL
20056 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20058 /* No ? OK - try using two ADD instructions to generate
20060 newimm
= validate_immediate_twopart (value
, & highpart
);
20062 /* Yes - then make sure that the second instruction is
20064 if (newimm
!= (unsigned int) FAIL
)
20066 /* Still No ? Try using a negated value. */
20067 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20068 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20069 /* Otherwise - give up. */
20072 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20073 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20078 /* Replace the first operand in the 2nd instruction (which
20079 is the PC) with the destination register. We have
20080 already added in the PC in the first instruction and we
20081 do not want to do it again. */
20082 newinsn
&= ~ 0xf0000;
20083 newinsn
|= ((newinsn
& 0x0f000) << 4);
20086 newimm
|= (temp
& 0xfffff000);
20087 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20089 highpart
|= (newinsn
& 0xfffff000);
20090 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20094 case BFD_RELOC_ARM_OFFSET_IMM
:
20095 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20098 case BFD_RELOC_ARM_LITERAL
:
20104 if (validate_offset_imm (value
, 0) == FAIL
)
20106 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20107 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20108 _("invalid literal constant: pool needs to be closer"));
20110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20111 _("bad immediate value for offset (%ld)"),
20116 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20117 newval
&= 0xff7ff000;
20118 newval
|= value
| (sign
? INDEX_UP
: 0);
20119 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20122 case BFD_RELOC_ARM_OFFSET_IMM8
:
20123 case BFD_RELOC_ARM_HWLITERAL
:
20129 if (validate_offset_imm (value
, 1) == FAIL
)
20131 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20133 _("invalid literal constant: pool needs to be closer"));
20135 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20140 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20141 newval
&= 0xff7ff0f0;
20142 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20143 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20146 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20147 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20148 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20149 _("bad immediate value for offset (%ld)"), (long) value
);
20152 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20154 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20157 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20158 /* This is a complicated relocation used for all varieties of Thumb32
20159 load/store instruction with immediate offset:
20161 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20162 *4, optional writeback(W)
20163 (doubleword load/store)
20165 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20166 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20167 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20168 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20169 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20171 Uppercase letters indicate bits that are already encoded at
20172 this point. Lowercase letters are our problem. For the
20173 second block of instructions, the secondary opcode nybble
20174 (bits 8..11) is present, and bit 23 is zero, even if this is
20175 a PC-relative operation. */
20176 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20178 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20180 if ((newval
& 0xf0000000) == 0xe0000000)
20182 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20184 newval
|= (1 << 23);
20187 if (value
% 4 != 0)
20189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20190 _("offset not a multiple of 4"));
20196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20197 _("offset out of range"));
20202 else if ((newval
& 0x000f0000) == 0x000f0000)
20204 /* PC-relative, 12-bit offset. */
20206 newval
|= (1 << 23);
20211 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20212 _("offset out of range"));
20217 else if ((newval
& 0x00000100) == 0x00000100)
20219 /* Writeback: 8-bit, +/- offset. */
20221 newval
|= (1 << 9);
20226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20227 _("offset out of range"));
20232 else if ((newval
& 0x00000f00) == 0x00000e00)
20234 /* T-instruction: positive 8-bit offset. */
20235 if (value
< 0 || value
> 0xff)
20237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20238 _("offset out of range"));
20246 /* Positive 12-bit or negative 8-bit offset. */
20250 newval
|= (1 << 23);
20260 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20261 _("offset out of range"));
20268 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20269 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20272 case BFD_RELOC_ARM_SHIFT_IMM
:
20273 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20274 if (((unsigned long) value
) > 32
20276 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20278 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20279 _("shift expression is too large"));
20284 /* Shifts of zero must be done as lsl. */
20286 else if (value
== 32)
20288 newval
&= 0xfffff07f;
20289 newval
|= (value
& 0x1f) << 7;
20290 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20293 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20294 case BFD_RELOC_ARM_T32_ADD_IMM
:
20295 case BFD_RELOC_ARM_T32_IMM12
:
20296 case BFD_RELOC_ARM_T32_ADD_PC12
:
20297 /* We claim that this fixup has been processed here,
20298 even if in fact we generate an error because we do
20299 not have a reloc for it, so tc_gen_reloc will reject it. */
20303 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20306 _("undefined symbol %s used as an immediate value"),
20307 S_GET_NAME (fixP
->fx_addsy
));
20311 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20313 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20316 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20317 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20319 newimm
= encode_thumb32_immediate (value
);
20320 if (newimm
== (unsigned int) FAIL
)
20321 newimm
= thumb32_negate_data_op (&newval
, value
);
20323 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20324 && newimm
== (unsigned int) FAIL
)
20326 /* Turn add/sum into addw/subw. */
20327 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20328 newval
= (newval
& 0xfeffffff) | 0x02000000;
20329 /* No flat 12-bit imm encoding for addsw/subsw. */
20330 if ((newval
& 0x00100000) == 0)
20332 /* 12 bit immediate for addw/subw. */
20336 newval
^= 0x00a00000;
20339 newimm
= (unsigned int) FAIL
;
20345 if (newimm
== (unsigned int)FAIL
)
20347 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20348 _("invalid constant (%lx) after fixup"),
20349 (unsigned long) value
);
20353 newval
|= (newimm
& 0x800) << 15;
20354 newval
|= (newimm
& 0x700) << 4;
20355 newval
|= (newimm
& 0x0ff);
20357 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20358 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20361 case BFD_RELOC_ARM_SMC
:
20362 if (((unsigned long) value
) > 0xffff)
20363 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20364 _("invalid smc expression"));
20365 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20366 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20367 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20370 case BFD_RELOC_ARM_SWI
:
20371 if (fixP
->tc_fix_data
!= 0)
20373 if (((unsigned long) value
) > 0xff)
20374 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20375 _("invalid swi expression"));
20376 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20378 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20382 if (((unsigned long) value
) > 0x00ffffff)
20383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20384 _("invalid swi expression"));
20385 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20387 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20391 case BFD_RELOC_ARM_MULTI
:
20392 if (((unsigned long) value
) > 0xffff)
20393 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20394 _("invalid expression in load/store multiple"));
20395 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20396 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20400 case BFD_RELOC_ARM_PCREL_CALL
:
20402 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20404 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20405 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20406 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20407 /* Flip the bl to blx. This is a simple flip
20408 bit here because we generate PCREL_CALL for
20409 unconditional bls. */
20411 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20412 newval
= newval
| 0x10000000;
20413 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20419 goto arm_branch_common
;
20421 case BFD_RELOC_ARM_PCREL_JUMP
:
20422 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20424 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20425 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20426 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20428 /* This would map to a bl<cond>, b<cond>,
20429 b<always> to a Thumb function. We
20430 need to force a relocation for this particular
20432 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20436 case BFD_RELOC_ARM_PLT32
:
20438 case BFD_RELOC_ARM_PCREL_BRANCH
:
20440 goto arm_branch_common
;
20442 case BFD_RELOC_ARM_PCREL_BLX
:
20445 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20447 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20448 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20449 && ARM_IS_FUNC (fixP
->fx_addsy
))
20451 /* Flip the blx to a bl and warn. */
20452 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20453 newval
= 0xeb000000;
20454 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20455 _("blx to '%s' an ARM ISA state function changed to bl"),
20457 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20463 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20464 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20468 /* We are going to store value (shifted right by two) in the
20469 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20470 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20471 also be be clear. */
20473 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20474 _("misaligned branch destination"));
20475 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20476 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20477 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20478 _("branch out of range"));
20480 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20482 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20483 newval
|= (value
>> 2) & 0x00ffffff;
20484 /* Set the H bit on BLX instructions. */
20488 newval
|= 0x01000000;
20490 newval
&= ~0x01000000;
20492 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20496 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20497 /* CBZ can only branch forward. */
20499 /* Attempts to use CBZ to branch to the next instruction
20500 (which, strictly speaking, are prohibited) will be turned into
20503 FIXME: It may be better to remove the instruction completely and
20504 perform relaxation. */
20507 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20508 newval
= 0xbf00; /* NOP encoding T1 */
20509 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20514 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20515 _("branch out of range"));
20517 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20519 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20520 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20521 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20526 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20527 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20528 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20529 _("branch out of range"));
20531 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20533 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20534 newval
|= (value
& 0x1ff) >> 1;
20535 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20539 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20540 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20542 _("branch out of range"));
20544 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20546 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20547 newval
|= (value
& 0xfff) >> 1;
20548 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20552 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20554 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20555 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20556 && S_IS_DEFINED (fixP
->fx_addsy
)
20557 && ARM_IS_FUNC (fixP
->fx_addsy
)
20558 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20560 /* Force a relocation for a branch 20 bits wide. */
20563 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20565 _("conditional branch out of range"));
20567 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20570 addressT S
, J1
, J2
, lo
, hi
;
20572 S
= (value
& 0x00100000) >> 20;
20573 J2
= (value
& 0x00080000) >> 19;
20574 J1
= (value
& 0x00040000) >> 18;
20575 hi
= (value
& 0x0003f000) >> 12;
20576 lo
= (value
& 0x00000ffe) >> 1;
20578 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20579 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20580 newval
|= (S
<< 10) | hi
;
20581 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20582 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20583 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20587 case BFD_RELOC_THUMB_PCREL_BLX
:
20589 /* If there is a blx from a thumb state function to
20590 another thumb function flip this to a bl and warn
20594 && S_IS_DEFINED (fixP
->fx_addsy
)
20595 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20596 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20597 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20599 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20600 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20601 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20603 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20604 newval
= newval
| 0x1000;
20605 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20606 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20611 goto thumb_bl_common
;
20613 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20615 /* A bl from Thumb state ISA to an internal ARM state function
20616 is converted to a blx. */
20618 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20619 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20620 && S_IS_DEFINED (fixP
->fx_addsy
)
20621 && ARM_IS_FUNC (fixP
->fx_addsy
)
20622 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20624 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20625 newval
= newval
& ~0x1000;
20626 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20627 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20634 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20635 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20636 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20639 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20640 /* For a BLX instruction, make sure that the relocation is rounded up
20641 to a word boundary. This follows the semantics of the instruction
20642 which specifies that bit 1 of the target address will come from bit
20643 1 of the base address. */
20644 value
= (value
+ 1) & ~ 1;
20647 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20649 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20651 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20652 _("branch out of range"));
20654 else if ((value
& ~0x1ffffff)
20655 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20658 _("Thumb2 branch out of range"));
20662 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20663 encode_thumb2_b_bl_offset (buf
, value
);
20667 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20668 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20670 _("branch out of range"));
20672 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20673 encode_thumb2_b_bl_offset (buf
, value
);
20678 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20679 md_number_to_chars (buf
, value
, 1);
20683 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20684 md_number_to_chars (buf
, value
, 2);
20688 case BFD_RELOC_ARM_TLS_GD32
:
20689 case BFD_RELOC_ARM_TLS_LE32
:
20690 case BFD_RELOC_ARM_TLS_IE32
:
20691 case BFD_RELOC_ARM_TLS_LDM32
:
20692 case BFD_RELOC_ARM_TLS_LDO32
:
20693 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20696 case BFD_RELOC_ARM_GOT32
:
20697 case BFD_RELOC_ARM_GOTOFF
:
20698 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20699 md_number_to_chars (buf
, 0, 4);
20702 case BFD_RELOC_ARM_GOT_PREL
:
20703 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20704 md_number_to_chars (buf
, value
, 4);
20707 case BFD_RELOC_ARM_TARGET2
:
20708 /* TARGET2 is not partial-inplace, so we need to write the
20709 addend here for REL targets, because it won't be written out
20710 during reloc processing later. */
20711 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20712 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20716 case BFD_RELOC_RVA
:
20718 case BFD_RELOC_ARM_TARGET1
:
20719 case BFD_RELOC_ARM_ROSEGREL32
:
20720 case BFD_RELOC_ARM_SBREL32
:
20721 case BFD_RELOC_32_PCREL
:
20723 case BFD_RELOC_32_SECREL
:
20725 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20727 /* For WinCE we only do this for pcrel fixups. */
20728 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20730 md_number_to_chars (buf
, value
, 4);
20734 case BFD_RELOC_ARM_PREL31
:
20735 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20737 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20738 if ((value
^ (value
>> 1)) & 0x40000000)
20740 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20741 _("rel31 relocation overflow"));
20743 newval
|= value
& 0x7fffffff;
20744 md_number_to_chars (buf
, newval
, 4);
20749 case BFD_RELOC_ARM_CP_OFF_IMM
:
20750 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20751 if (value
< -1023 || value
> 1023 || (value
& 3))
20752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20753 _("co-processor offset out of range"));
20758 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20759 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20760 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20762 newval
= get_thumb32_insn (buf
);
20763 newval
&= 0xff7fff00;
20764 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20765 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20766 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20767 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20769 put_thumb32_insn (buf
, newval
);
20772 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20773 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20774 if (value
< -255 || value
> 255)
20775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20776 _("co-processor offset out of range"));
20778 goto cp_off_common
;
20780 case BFD_RELOC_ARM_THUMB_OFFSET
:
20781 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20782 /* Exactly what ranges, and where the offset is inserted depends
20783 on the type of instruction, we can establish this from the
20785 switch (newval
>> 12)
20787 case 4: /* PC load. */
20788 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20789 forced to zero for these loads; md_pcrel_from has already
20790 compensated for this. */
20792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20793 _("invalid offset, target not word aligned (0x%08lX)"),
20794 (((unsigned long) fixP
->fx_frag
->fr_address
20795 + (unsigned long) fixP
->fx_where
) & ~3)
20796 + (unsigned long) value
);
20798 if (value
& ~0x3fc)
20799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20800 _("invalid offset, value too big (0x%08lX)"),
20803 newval
|= value
>> 2;
20806 case 9: /* SP load/store. */
20807 if (value
& ~0x3fc)
20808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20809 _("invalid offset, value too big (0x%08lX)"),
20811 newval
|= value
>> 2;
20814 case 6: /* Word load/store. */
20816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20817 _("invalid offset, value too big (0x%08lX)"),
20819 newval
|= value
<< 4; /* 6 - 2. */
20822 case 7: /* Byte load/store. */
20824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20825 _("invalid offset, value too big (0x%08lX)"),
20827 newval
|= value
<< 6;
20830 case 8: /* Halfword load/store. */
20832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20833 _("invalid offset, value too big (0x%08lX)"),
20835 newval
|= value
<< 5; /* 6 - 1. */
20839 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20840 "Unable to process relocation for thumb opcode: %lx",
20841 (unsigned long) newval
);
20844 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20847 case BFD_RELOC_ARM_THUMB_ADD
:
20848 /* This is a complicated relocation, since we use it for all of
20849 the following immediate relocations:
20853 9bit ADD/SUB SP word-aligned
20854 10bit ADD PC/SP word-aligned
20856 The type of instruction being processed is encoded in the
20863 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20865 int rd
= (newval
>> 4) & 0xf;
20866 int rs
= newval
& 0xf;
20867 int subtract
= !!(newval
& 0x8000);
20869 /* Check for HI regs, only very restricted cases allowed:
20870 Adjusting SP, and using PC or SP to get an address. */
20871 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20872 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20873 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20874 _("invalid Hi register with immediate"));
20876 /* If value is negative, choose the opposite instruction. */
20880 subtract
= !subtract
;
20882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20883 _("immediate value out of range"));
20888 if (value
& ~0x1fc)
20889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20890 _("invalid immediate for stack address calculation"));
20891 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20892 newval
|= value
>> 2;
20894 else if (rs
== REG_PC
|| rs
== REG_SP
)
20896 if (subtract
|| value
& ~0x3fc)
20897 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20898 _("invalid immediate for address calculation (value = 0x%08lX)"),
20899 (unsigned long) value
);
20900 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20902 newval
|= value
>> 2;
20907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20908 _("immediate value out of range"));
20909 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20910 newval
|= (rd
<< 8) | value
;
20915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20916 _("immediate value out of range"));
20917 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20918 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20921 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20924 case BFD_RELOC_ARM_THUMB_IMM
:
20925 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20926 if (value
< 0 || value
> 255)
20927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20928 _("invalid immediate: %ld is out of range"),
20931 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20934 case BFD_RELOC_ARM_THUMB_SHIFT
:
20935 /* 5bit shift value (0..32). LSL cannot take 32. */
20936 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20937 temp
= newval
& 0xf800;
20938 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20940 _("invalid shift value: %ld"), (long) value
);
20941 /* Shifts of zero must be encoded as LSL. */
20943 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20944 /* Shifts of 32 are encoded as zero. */
20945 else if (value
== 32)
20947 newval
|= value
<< 6;
20948 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20951 case BFD_RELOC_VTABLE_INHERIT
:
20952 case BFD_RELOC_VTABLE_ENTRY
:
20956 case BFD_RELOC_ARM_MOVW
:
20957 case BFD_RELOC_ARM_MOVT
:
20958 case BFD_RELOC_ARM_THUMB_MOVW
:
20959 case BFD_RELOC_ARM_THUMB_MOVT
:
20960 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20962 /* REL format relocations are limited to a 16-bit addend. */
20963 if (!fixP
->fx_done
)
20965 if (value
< -0x8000 || value
> 0x7fff)
20966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20967 _("offset out of range"));
20969 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20970 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20975 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20976 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20978 newval
= get_thumb32_insn (buf
);
20979 newval
&= 0xfbf08f00;
20980 newval
|= (value
& 0xf000) << 4;
20981 newval
|= (value
& 0x0800) << 15;
20982 newval
|= (value
& 0x0700) << 4;
20983 newval
|= (value
& 0x00ff);
20984 put_thumb32_insn (buf
, newval
);
20988 newval
= md_chars_to_number (buf
, 4);
20989 newval
&= 0xfff0f000;
20990 newval
|= value
& 0x0fff;
20991 newval
|= (value
& 0xf000) << 4;
20992 md_number_to_chars (buf
, newval
, 4);
20997 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20998 case BFD_RELOC_ARM_ALU_PC_G0
:
20999 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21000 case BFD_RELOC_ARM_ALU_PC_G1
:
21001 case BFD_RELOC_ARM_ALU_PC_G2
:
21002 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21003 case BFD_RELOC_ARM_ALU_SB_G0
:
21004 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21005 case BFD_RELOC_ARM_ALU_SB_G1
:
21006 case BFD_RELOC_ARM_ALU_SB_G2
:
21007 gas_assert (!fixP
->fx_done
);
21008 if (!seg
->use_rela_p
)
21011 bfd_vma encoded_addend
;
21012 bfd_vma addend_abs
= abs (value
);
21014 /* Check that the absolute value of the addend can be
21015 expressed as an 8-bit constant plus a rotation. */
21016 encoded_addend
= encode_arm_immediate (addend_abs
);
21017 if (encoded_addend
== (unsigned int) FAIL
)
21018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21019 _("the offset 0x%08lX is not representable"),
21020 (unsigned long) addend_abs
);
21022 /* Extract the instruction. */
21023 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21025 /* If the addend is positive, use an ADD instruction.
21026 Otherwise use a SUB. Take care not to destroy the S bit. */
21027 insn
&= 0xff1fffff;
21033 /* Place the encoded addend into the first 12 bits of the
21035 insn
&= 0xfffff000;
21036 insn
|= encoded_addend
;
21038 /* Update the instruction. */
21039 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21043 case BFD_RELOC_ARM_LDR_PC_G0
:
21044 case BFD_RELOC_ARM_LDR_PC_G1
:
21045 case BFD_RELOC_ARM_LDR_PC_G2
:
21046 case BFD_RELOC_ARM_LDR_SB_G0
:
21047 case BFD_RELOC_ARM_LDR_SB_G1
:
21048 case BFD_RELOC_ARM_LDR_SB_G2
:
21049 gas_assert (!fixP
->fx_done
);
21050 if (!seg
->use_rela_p
)
21053 bfd_vma addend_abs
= abs (value
);
21055 /* Check that the absolute value of the addend can be
21056 encoded in 12 bits. */
21057 if (addend_abs
>= 0x1000)
21058 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21059 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21060 (unsigned long) addend_abs
);
21062 /* Extract the instruction. */
21063 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21065 /* If the addend is negative, clear bit 23 of the instruction.
21066 Otherwise set it. */
21068 insn
&= ~(1 << 23);
21072 /* Place the absolute value of the addend into the first 12 bits
21073 of the instruction. */
21074 insn
&= 0xfffff000;
21075 insn
|= addend_abs
;
21077 /* Update the instruction. */
21078 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21082 case BFD_RELOC_ARM_LDRS_PC_G0
:
21083 case BFD_RELOC_ARM_LDRS_PC_G1
:
21084 case BFD_RELOC_ARM_LDRS_PC_G2
:
21085 case BFD_RELOC_ARM_LDRS_SB_G0
:
21086 case BFD_RELOC_ARM_LDRS_SB_G1
:
21087 case BFD_RELOC_ARM_LDRS_SB_G2
:
21088 gas_assert (!fixP
->fx_done
);
21089 if (!seg
->use_rela_p
)
21092 bfd_vma addend_abs
= abs (value
);
21094 /* Check that the absolute value of the addend can be
21095 encoded in 8 bits. */
21096 if (addend_abs
>= 0x100)
21097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21098 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21099 (unsigned long) addend_abs
);
21101 /* Extract the instruction. */
21102 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21104 /* If the addend is negative, clear bit 23 of the instruction.
21105 Otherwise set it. */
21107 insn
&= ~(1 << 23);
21111 /* Place the first four bits of the absolute value of the addend
21112 into the first 4 bits of the instruction, and the remaining
21113 four into bits 8 .. 11. */
21114 insn
&= 0xfffff0f0;
21115 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21117 /* Update the instruction. */
21118 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21122 case BFD_RELOC_ARM_LDC_PC_G0
:
21123 case BFD_RELOC_ARM_LDC_PC_G1
:
21124 case BFD_RELOC_ARM_LDC_PC_G2
:
21125 case BFD_RELOC_ARM_LDC_SB_G0
:
21126 case BFD_RELOC_ARM_LDC_SB_G1
:
21127 case BFD_RELOC_ARM_LDC_SB_G2
:
21128 gas_assert (!fixP
->fx_done
);
21129 if (!seg
->use_rela_p
)
21132 bfd_vma addend_abs
= abs (value
);
21134 /* Check that the absolute value of the addend is a multiple of
21135 four and, when divided by four, fits in 8 bits. */
21136 if (addend_abs
& 0x3)
21137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21138 _("bad offset 0x%08lX (must be word-aligned)"),
21139 (unsigned long) addend_abs
);
21141 if ((addend_abs
>> 2) > 0xff)
21142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21143 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21144 (unsigned long) addend_abs
);
21146 /* Extract the instruction. */
21147 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21149 /* If the addend is negative, clear bit 23 of the instruction.
21150 Otherwise set it. */
21152 insn
&= ~(1 << 23);
21156 /* Place the addend (divided by four) into the first eight
21157 bits of the instruction. */
21158 insn
&= 0xfffffff0;
21159 insn
|= addend_abs
>> 2;
21161 /* Update the instruction. */
21162 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21166 case BFD_RELOC_ARM_V4BX
:
21167 /* This will need to go in the object file. */
21171 case BFD_RELOC_UNUSED
:
21173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21174 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21178 /* Translate internal representation of relocation info to BFD target
21182 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21185 bfd_reloc_code_real_type code
;
21187 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21189 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21190 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21191 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21193 if (fixp
->fx_pcrel
)
21195 if (section
->use_rela_p
)
21196 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21198 fixp
->fx_offset
= reloc
->address
;
21200 reloc
->addend
= fixp
->fx_offset
;
21202 switch (fixp
->fx_r_type
)
21205 if (fixp
->fx_pcrel
)
21207 code
= BFD_RELOC_8_PCREL
;
21212 if (fixp
->fx_pcrel
)
21214 code
= BFD_RELOC_16_PCREL
;
21219 if (fixp
->fx_pcrel
)
21221 code
= BFD_RELOC_32_PCREL
;
21225 case BFD_RELOC_ARM_MOVW
:
21226 if (fixp
->fx_pcrel
)
21228 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21232 case BFD_RELOC_ARM_MOVT
:
21233 if (fixp
->fx_pcrel
)
21235 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21239 case BFD_RELOC_ARM_THUMB_MOVW
:
21240 if (fixp
->fx_pcrel
)
21242 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21246 case BFD_RELOC_ARM_THUMB_MOVT
:
21247 if (fixp
->fx_pcrel
)
21249 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21253 case BFD_RELOC_NONE
:
21254 case BFD_RELOC_ARM_PCREL_BRANCH
:
21255 case BFD_RELOC_ARM_PCREL_BLX
:
21256 case BFD_RELOC_RVA
:
21257 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21258 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21259 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21260 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21261 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21262 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21263 case BFD_RELOC_VTABLE_ENTRY
:
21264 case BFD_RELOC_VTABLE_INHERIT
:
21266 case BFD_RELOC_32_SECREL
:
21268 code
= fixp
->fx_r_type
;
21271 case BFD_RELOC_THUMB_PCREL_BLX
:
21273 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21274 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21277 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21280 case BFD_RELOC_ARM_LITERAL
:
21281 case BFD_RELOC_ARM_HWLITERAL
:
21282 /* If this is called then the a literal has
21283 been referenced across a section boundary. */
21284 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21285 _("literal referenced across section boundary"));
21289 case BFD_RELOC_ARM_GOT32
:
21290 case BFD_RELOC_ARM_GOTOFF
:
21291 case BFD_RELOC_ARM_GOT_PREL
:
21292 case BFD_RELOC_ARM_PLT32
:
21293 case BFD_RELOC_ARM_TARGET1
:
21294 case BFD_RELOC_ARM_ROSEGREL32
:
21295 case BFD_RELOC_ARM_SBREL32
:
21296 case BFD_RELOC_ARM_PREL31
:
21297 case BFD_RELOC_ARM_TARGET2
:
21298 case BFD_RELOC_ARM_TLS_LE32
:
21299 case BFD_RELOC_ARM_TLS_LDO32
:
21300 case BFD_RELOC_ARM_PCREL_CALL
:
21301 case BFD_RELOC_ARM_PCREL_JUMP
:
21302 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21303 case BFD_RELOC_ARM_ALU_PC_G0
:
21304 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21305 case BFD_RELOC_ARM_ALU_PC_G1
:
21306 case BFD_RELOC_ARM_ALU_PC_G2
:
21307 case BFD_RELOC_ARM_LDR_PC_G0
:
21308 case BFD_RELOC_ARM_LDR_PC_G1
:
21309 case BFD_RELOC_ARM_LDR_PC_G2
:
21310 case BFD_RELOC_ARM_LDRS_PC_G0
:
21311 case BFD_RELOC_ARM_LDRS_PC_G1
:
21312 case BFD_RELOC_ARM_LDRS_PC_G2
:
21313 case BFD_RELOC_ARM_LDC_PC_G0
:
21314 case BFD_RELOC_ARM_LDC_PC_G1
:
21315 case BFD_RELOC_ARM_LDC_PC_G2
:
21316 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21317 case BFD_RELOC_ARM_ALU_SB_G0
:
21318 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21319 case BFD_RELOC_ARM_ALU_SB_G1
:
21320 case BFD_RELOC_ARM_ALU_SB_G2
:
21321 case BFD_RELOC_ARM_LDR_SB_G0
:
21322 case BFD_RELOC_ARM_LDR_SB_G1
:
21323 case BFD_RELOC_ARM_LDR_SB_G2
:
21324 case BFD_RELOC_ARM_LDRS_SB_G0
:
21325 case BFD_RELOC_ARM_LDRS_SB_G1
:
21326 case BFD_RELOC_ARM_LDRS_SB_G2
:
21327 case BFD_RELOC_ARM_LDC_SB_G0
:
21328 case BFD_RELOC_ARM_LDC_SB_G1
:
21329 case BFD_RELOC_ARM_LDC_SB_G2
:
21330 case BFD_RELOC_ARM_V4BX
:
21331 code
= fixp
->fx_r_type
;
21334 case BFD_RELOC_ARM_TLS_GD32
:
21335 case BFD_RELOC_ARM_TLS_IE32
:
21336 case BFD_RELOC_ARM_TLS_LDM32
:
21337 /* BFD will include the symbol's address in the addend.
21338 But we don't want that, so subtract it out again here. */
21339 if (!S_IS_COMMON (fixp
->fx_addsy
))
21340 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21341 code
= fixp
->fx_r_type
;
21345 case BFD_RELOC_ARM_IMMEDIATE
:
21346 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21347 _("internal relocation (type: IMMEDIATE) not fixed up"));
21350 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21351 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21352 _("ADRL used for a symbol not defined in the same file"));
21355 case BFD_RELOC_ARM_OFFSET_IMM
:
21356 if (section
->use_rela_p
)
21358 code
= fixp
->fx_r_type
;
21362 if (fixp
->fx_addsy
!= NULL
21363 && !S_IS_DEFINED (fixp
->fx_addsy
)
21364 && S_IS_LOCAL (fixp
->fx_addsy
))
21366 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21367 _("undefined local label `%s'"),
21368 S_GET_NAME (fixp
->fx_addsy
));
21372 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21373 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21380 switch (fixp
->fx_r_type
)
21382 case BFD_RELOC_NONE
: type
= "NONE"; break;
21383 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21384 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21385 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21386 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21387 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21388 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21389 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21390 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21391 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21392 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21393 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21394 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21395 default: type
= _("<unknown>"); break;
21397 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21398 _("cannot represent %s relocation in this object file format"),
21405 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21407 && fixp
->fx_addsy
== GOT_symbol
)
21409 code
= BFD_RELOC_ARM_GOTPC
;
21410 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21414 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21416 if (reloc
->howto
== NULL
)
21418 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21419 _("cannot represent %s relocation in this object file format"),
21420 bfd_get_reloc_code_name (code
));
21424 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21425 vtable entry to be used in the relocation's section offset. */
21426 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21427 reloc
->address
= fixp
->fx_offset
;
21432 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21435 cons_fix_new_arm (fragS
* frag
,
21440 bfd_reloc_code_real_type type
;
21444 FIXME: @@ Should look at CPU word size. */
21448 type
= BFD_RELOC_8
;
21451 type
= BFD_RELOC_16
;
21455 type
= BFD_RELOC_32
;
21458 type
= BFD_RELOC_64
;
21463 if (exp
->X_op
== O_secrel
)
21465 exp
->X_op
= O_symbol
;
21466 type
= BFD_RELOC_32_SECREL
;
21470 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21473 #if defined (OBJ_COFF)
21475 arm_validate_fix (fixS
* fixP
)
21477 /* If the destination of the branch is a defined symbol which does not have
21478 the THUMB_FUNC attribute, then we must be calling a function which has
21479 the (interfacearm) attribute. We look for the Thumb entry point to that
21480 function and change the branch to refer to that function instead. */
21481 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21482 && fixP
->fx_addsy
!= NULL
21483 && S_IS_DEFINED (fixP
->fx_addsy
)
21484 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21486 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21493 arm_force_relocation (struct fix
* fixp
)
21495 #if defined (OBJ_COFF) && defined (TE_PE)
21496 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21500 /* In case we have a call or a branch to a function in ARM ISA mode from
21501 a thumb function or vice-versa force the relocation. These relocations
21502 are cleared off for some cores that might have blx and simple transformations
21506 switch (fixp
->fx_r_type
)
21508 case BFD_RELOC_ARM_PCREL_JUMP
:
21509 case BFD_RELOC_ARM_PCREL_CALL
:
21510 case BFD_RELOC_THUMB_PCREL_BLX
:
21511 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21515 case BFD_RELOC_ARM_PCREL_BLX
:
21516 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21517 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21518 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21519 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21528 /* Resolve these relocations even if the symbol is extern or weak. */
21529 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21530 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21531 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21532 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21533 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21534 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21535 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21538 /* Always leave these relocations for the linker. */
21539 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21540 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21541 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21544 /* Always generate relocations against function symbols. */
21545 if (fixp
->fx_r_type
== BFD_RELOC_32
21547 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21550 return generic_force_reloc (fixp
);
21553 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21554 /* Relocations against function names must be left unadjusted,
21555 so that the linker can use this information to generate interworking
21556 stubs. The MIPS version of this function
21557 also prevents relocations that are mips-16 specific, but I do not
21558 know why it does this.
21561 There is one other problem that ought to be addressed here, but
21562 which currently is not: Taking the address of a label (rather
21563 than a function) and then later jumping to that address. Such
21564 addresses also ought to have their bottom bit set (assuming that
21565 they reside in Thumb code), but at the moment they will not. */
21568 arm_fix_adjustable (fixS
* fixP
)
21570 if (fixP
->fx_addsy
== NULL
)
21573 /* Preserve relocations against symbols with function type. */
21574 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21577 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21578 && fixP
->fx_subsy
== NULL
)
21581 /* We need the symbol name for the VTABLE entries. */
21582 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21583 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21586 /* Don't allow symbols to be discarded on GOT related relocs. */
21587 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21588 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21589 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21590 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21591 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21592 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21593 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21594 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21595 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21598 /* Similarly for group relocations. */
21599 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21600 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21601 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21604 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21605 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21606 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21607 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21608 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21609 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21610 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21611 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21612 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21617 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21622 elf32_arm_target_format (void)
21625 return (target_big_endian
21626 ? "elf32-bigarm-symbian"
21627 : "elf32-littlearm-symbian");
21628 #elif defined (TE_VXWORKS)
21629 return (target_big_endian
21630 ? "elf32-bigarm-vxworks"
21631 : "elf32-littlearm-vxworks");
21633 if (target_big_endian
)
21634 return "elf32-bigarm";
21636 return "elf32-littlearm";
21641 armelf_frob_symbol (symbolS
* symp
,
21644 elf_frob_symbol (symp
, puntp
);
21648 /* MD interface: Finalization. */
21653 literal_pool
* pool
;
21655 /* Ensure that all the IT blocks are properly closed. */
21656 check_it_blocks_finished ();
21658 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21660 /* Put it at the end of the relevant section. */
21661 subseg_set (pool
->section
, pool
->sub_section
);
21663 arm_elf_change_section ();
21670 /* Remove any excess mapping symbols generated for alignment frags in
21671 SEC. We may have created a mapping symbol before a zero byte
21672 alignment; remove it if there's a mapping symbol after the
21675 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21676 void *dummy ATTRIBUTE_UNUSED
)
21678 segment_info_type
*seginfo
= seg_info (sec
);
21681 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21684 for (fragp
= seginfo
->frchainP
->frch_root
;
21686 fragp
= fragp
->fr_next
)
21688 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21689 fragS
*next
= fragp
->fr_next
;
21691 /* Variable-sized frags have been converted to fixed size by
21692 this point. But if this was variable-sized to start with,
21693 there will be a fixed-size frag after it. So don't handle
21695 if (sym
== NULL
|| next
== NULL
)
21698 if (S_GET_VALUE (sym
) < next
->fr_address
)
21699 /* Not at the end of this frag. */
21701 know (S_GET_VALUE (sym
) == next
->fr_address
);
21705 if (next
->tc_frag_data
.first_map
!= NULL
)
21707 /* Next frag starts with a mapping symbol. Discard this
21709 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21713 if (next
->fr_next
== NULL
)
21715 /* This mapping symbol is at the end of the section. Discard
21717 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21718 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21722 /* As long as we have empty frags without any mapping symbols,
21724 /* If the next frag is non-empty and does not start with a
21725 mapping symbol, then this mapping symbol is required. */
21726 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21729 next
= next
->fr_next
;
21731 while (next
!= NULL
);
21736 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21740 arm_adjust_symtab (void)
21745 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21747 if (ARM_IS_THUMB (sym
))
21749 if (THUMB_IS_FUNC (sym
))
21751 /* Mark the symbol as a Thumb function. */
21752 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21753 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21754 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21756 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21757 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21759 as_bad (_("%s: unexpected function type: %d"),
21760 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21762 else switch (S_GET_STORAGE_CLASS (sym
))
21765 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21768 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21771 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21779 if (ARM_IS_INTERWORK (sym
))
21780 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21787 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21789 if (ARM_IS_THUMB (sym
))
21791 elf_symbol_type
* elf_sym
;
21793 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21794 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21796 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21797 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21799 /* If it's a .thumb_func, declare it as so,
21800 otherwise tag label as .code 16. */
21801 if (THUMB_IS_FUNC (sym
))
21802 elf_sym
->internal_elf_sym
.st_info
=
21803 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21804 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21805 elf_sym
->internal_elf_sym
.st_info
=
21806 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21811 /* Remove any overlapping mapping symbols generated by alignment frags. */
21812 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21816 /* MD interface: Initialization. */
21819 set_constant_flonums (void)
21823 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21824 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21828 /* Auto-select Thumb mode if it's the only available instruction set for the
21829 given architecture. */
21832 autoselect_thumb_from_cpu_variant (void)
21834 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21835 opcode_select (16);
21844 if ( (arm_ops_hsh
= hash_new ()) == NULL
21845 || (arm_cond_hsh
= hash_new ()) == NULL
21846 || (arm_shift_hsh
= hash_new ()) == NULL
21847 || (arm_psr_hsh
= hash_new ()) == NULL
21848 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21849 || (arm_reg_hsh
= hash_new ()) == NULL
21850 || (arm_reloc_hsh
= hash_new ()) == NULL
21851 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21852 as_fatal (_("virtual memory exhausted"));
21854 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21855 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21856 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21857 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21858 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21859 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21860 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21861 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21862 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21863 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21864 (void *) (v7m_psrs
+ i
));
21865 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21866 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21868 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21870 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21871 (void *) (barrier_opt_names
+ i
));
21873 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21874 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21877 set_constant_flonums ();
21879 /* Set the cpu variant based on the command-line options. We prefer
21880 -mcpu= over -march= if both are set (as for GCC); and we prefer
21881 -mfpu= over any other way of setting the floating point unit.
21882 Use of legacy options with new options are faulted. */
21885 if (mcpu_cpu_opt
|| march_cpu_opt
)
21886 as_bad (_("use of old and new-style options to set CPU type"));
21888 mcpu_cpu_opt
= legacy_cpu
;
21890 else if (!mcpu_cpu_opt
)
21891 mcpu_cpu_opt
= march_cpu_opt
;
21896 as_bad (_("use of old and new-style options to set FPU type"));
21898 mfpu_opt
= legacy_fpu
;
21900 else if (!mfpu_opt
)
21902 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21903 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21904 /* Some environments specify a default FPU. If they don't, infer it
21905 from the processor. */
21907 mfpu_opt
= mcpu_fpu_opt
;
21909 mfpu_opt
= march_fpu_opt
;
21911 mfpu_opt
= &fpu_default
;
21917 if (mcpu_cpu_opt
!= NULL
)
21918 mfpu_opt
= &fpu_default
;
21919 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21920 mfpu_opt
= &fpu_arch_vfp_v2
;
21922 mfpu_opt
= &fpu_arch_fpa
;
21928 mcpu_cpu_opt
= &cpu_default
;
21929 selected_cpu
= cpu_default
;
21933 selected_cpu
= *mcpu_cpu_opt
;
21935 mcpu_cpu_opt
= &arm_arch_any
;
21938 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21940 autoselect_thumb_from_cpu_variant ();
21942 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21944 #if defined OBJ_COFF || defined OBJ_ELF
21946 unsigned int flags
= 0;
21948 #if defined OBJ_ELF
21949 flags
= meabi_flags
;
21951 switch (meabi_flags
)
21953 case EF_ARM_EABI_UNKNOWN
:
21955 /* Set the flags in the private structure. */
21956 if (uses_apcs_26
) flags
|= F_APCS26
;
21957 if (support_interwork
) flags
|= F_INTERWORK
;
21958 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21959 if (pic_code
) flags
|= F_PIC
;
21960 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21961 flags
|= F_SOFT_FLOAT
;
21963 switch (mfloat_abi_opt
)
21965 case ARM_FLOAT_ABI_SOFT
:
21966 case ARM_FLOAT_ABI_SOFTFP
:
21967 flags
|= F_SOFT_FLOAT
;
21970 case ARM_FLOAT_ABI_HARD
:
21971 if (flags
& F_SOFT_FLOAT
)
21972 as_bad (_("hard-float conflicts with specified fpu"));
21976 /* Using pure-endian doubles (even if soft-float). */
21977 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21978 flags
|= F_VFP_FLOAT
;
21980 #if defined OBJ_ELF
21981 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21982 flags
|= EF_ARM_MAVERICK_FLOAT
;
21985 case EF_ARM_EABI_VER4
:
21986 case EF_ARM_EABI_VER5
:
21987 /* No additional flags to set. */
21994 bfd_set_private_flags (stdoutput
, flags
);
21996 /* We have run out flags in the COFF header to encode the
21997 status of ATPCS support, so instead we create a dummy,
21998 empty, debug section called .arm.atpcs. */
22003 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22007 bfd_set_section_flags
22008 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22009 bfd_set_section_size (stdoutput
, sec
, 0);
22010 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22016 /* Record the CPU type as well. */
22017 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22018 mach
= bfd_mach_arm_iWMMXt2
;
22019 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22020 mach
= bfd_mach_arm_iWMMXt
;
22021 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22022 mach
= bfd_mach_arm_XScale
;
22023 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22024 mach
= bfd_mach_arm_ep9312
;
22025 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22026 mach
= bfd_mach_arm_5TE
;
22027 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22029 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22030 mach
= bfd_mach_arm_5T
;
22032 mach
= bfd_mach_arm_5
;
22034 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22036 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22037 mach
= bfd_mach_arm_4T
;
22039 mach
= bfd_mach_arm_4
;
22041 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22042 mach
= bfd_mach_arm_3M
;
22043 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22044 mach
= bfd_mach_arm_3
;
22045 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22046 mach
= bfd_mach_arm_2a
;
22047 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22048 mach
= bfd_mach_arm_2
;
22050 mach
= bfd_mach_arm_unknown
;
22052 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22055 /* Command line processing. */
22058 Invocation line includes a switch not recognized by the base assembler.
22059 See if it's a processor-specific option.
22061 This routine is somewhat complicated by the need for backwards
22062 compatibility (since older releases of gcc can't be changed).
22063 The new options try to make the interface as compatible as
22066 New options (supported) are:
22068 -mcpu=<cpu name> Assemble for selected processor
22069 -march=<architecture name> Assemble for selected architecture
22070 -mfpu=<fpu architecture> Assemble for selected FPU.
22071 -EB/-mbig-endian Big-endian
22072 -EL/-mlittle-endian Little-endian
22073 -k Generate PIC code
22074 -mthumb Start in Thumb mode
22075 -mthumb-interwork Code supports ARM/Thumb interworking
22077 -m[no-]warn-deprecated Warn about deprecated features
22079 For now we will also provide support for:
22081 -mapcs-32 32-bit Program counter
22082 -mapcs-26 26-bit Program counter
22083 -macps-float Floats passed in FP registers
22084 -mapcs-reentrant Reentrant code
22086 (sometime these will probably be replaced with -mapcs=<list of options>
22087 and -matpcs=<list of options>)
22089 The remaining options are only supported for back-wards compatibility.
22090 Cpu variants, the arm part is optional:
22091 -m[arm]1 Currently not supported.
22092 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22093 -m[arm]3 Arm 3 processor
22094 -m[arm]6[xx], Arm 6 processors
22095 -m[arm]7[xx][t][[d]m] Arm 7 processors
22096 -m[arm]8[10] Arm 8 processors
22097 -m[arm]9[20][tdmi] Arm 9 processors
22098 -mstrongarm[110[0]] StrongARM processors
22099 -mxscale XScale processors
22100 -m[arm]v[2345[t[e]]] Arm architectures
22101 -mall All (except the ARM1)
22103 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22104 -mfpe-old (No float load/store multiples)
22105 -mvfpxd VFP Single precision
22107 -mno-fpu Disable all floating point instructions
22109 The following CPU names are recognized:
22110 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22111 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22112 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22113 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22114 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22115 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22116 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22120 const char * md_shortopts
= "m:k";
22122 #ifdef ARM_BI_ENDIAN
22123 #define OPTION_EB (OPTION_MD_BASE + 0)
22124 #define OPTION_EL (OPTION_MD_BASE + 1)
22126 #if TARGET_BYTES_BIG_ENDIAN
22127 #define OPTION_EB (OPTION_MD_BASE + 0)
22129 #define OPTION_EL (OPTION_MD_BASE + 1)
22132 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22134 struct option md_longopts
[] =
22137 {"EB", no_argument
, NULL
, OPTION_EB
},
22140 {"EL", no_argument
, NULL
, OPTION_EL
},
22142 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22143 {NULL
, no_argument
, NULL
, 0}
22146 size_t md_longopts_size
= sizeof (md_longopts
);
22148 struct arm_option_table
22150 char *option
; /* Option name to match. */
22151 char *help
; /* Help information. */
22152 int *var
; /* Variable to change. */
22153 int value
; /* What to change it to. */
22154 char *deprecated
; /* If non-null, print this message. */
22157 struct arm_option_table arm_opts
[] =
22159 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22160 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22161 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22162 &support_interwork
, 1, NULL
},
22163 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22164 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22165 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22167 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22168 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22169 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22170 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22173 /* These are recognized by the assembler, but have no affect on code. */
22174 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22175 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22177 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22178 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22179 &warn_on_deprecated
, 0, NULL
},
22180 {NULL
, NULL
, NULL
, 0, NULL
}
22183 struct arm_legacy_option_table
22185 char *option
; /* Option name to match. */
22186 const arm_feature_set
**var
; /* Variable to change. */
22187 const arm_feature_set value
; /* What to change it to. */
22188 char *deprecated
; /* If non-null, print this message. */
22191 const struct arm_legacy_option_table arm_legacy_opts
[] =
22193 /* DON'T add any new processors to this list -- we want the whole list
22194 to go away... Add them to the processors table instead. */
22195 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22196 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22197 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22198 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22199 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22200 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22201 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22202 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22203 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22204 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22205 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22206 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22207 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22208 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22209 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22210 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22211 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22212 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22213 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22214 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22215 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22216 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22217 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22218 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22219 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22220 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22221 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22222 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22223 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22224 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22225 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22226 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22227 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22228 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22229 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22230 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22231 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22232 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22233 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22234 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22235 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22236 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22237 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22238 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22239 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22240 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22241 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22242 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22243 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22244 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22245 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22246 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22247 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22248 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22249 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22250 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22251 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22252 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22253 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22254 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22255 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22256 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22257 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22258 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22259 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22260 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22261 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22262 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22263 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22264 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22265 N_("use -mcpu=strongarm110")},
22266 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22267 N_("use -mcpu=strongarm1100")},
22268 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22269 N_("use -mcpu=strongarm1110")},
22270 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22271 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22272 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22274 /* Architecture variants -- don't add any more to this list either. */
22275 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22276 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22277 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22278 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22279 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22280 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22281 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22282 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22283 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22284 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22285 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22286 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22287 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22288 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22289 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22290 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22291 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22292 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22294 /* Floating point variants -- don't add any more to this list either. */
22295 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22296 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22297 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22298 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22299 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22301 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22304 struct arm_cpu_option_table
22307 const arm_feature_set value
;
22308 /* For some CPUs we assume an FPU unless the user explicitly sets
22310 const arm_feature_set default_fpu
;
22311 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22313 const char *canonical_name
;
22316 /* This list should, at a minimum, contain all the cpu names
22317 recognized by GCC. */
22318 static const struct arm_cpu_option_table arm_cpus
[] =
22320 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22321 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22322 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22323 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22324 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22325 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22326 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22327 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22328 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22329 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22330 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22331 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22332 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22333 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22334 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22335 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22336 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22337 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22338 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22339 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22340 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22341 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22342 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22343 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22344 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22345 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22346 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22347 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22348 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22349 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22350 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22351 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22352 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22353 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22354 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22355 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22356 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22357 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22358 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22359 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22360 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22361 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22362 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22363 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22364 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22365 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22366 /* For V5 or later processors we default to using VFP; but the user
22367 should really set the FPU type explicitly. */
22368 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22369 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22370 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22371 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22372 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22373 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22374 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22375 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22376 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22377 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22378 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22379 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22380 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22381 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22382 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22383 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22384 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22385 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22386 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22387 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22388 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22389 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22390 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22391 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22392 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22393 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22394 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22395 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22396 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22397 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22398 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22399 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22400 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22401 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22402 FPU_NONE
, "Cortex-A5"},
22403 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22404 ARM_FEATURE (0, FPU_VFP_V3
22405 | FPU_NEON_EXT_V1
),
22407 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22408 ARM_FEATURE (0, FPU_VFP_V3
22409 | FPU_NEON_EXT_V1
),
22411 {"cortex-a15", ARM_ARCH_V7A_MP_SEC
,
22412 FPU_ARCH_NEON_VFP_V4
,
22414 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22415 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22417 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22418 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22419 {"cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"},
22420 {"cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"},
22421 /* ??? XSCALE is really an architecture. */
22422 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22423 /* ??? iwmmxt is not a processor. */
22424 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22425 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22426 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22428 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22429 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22432 struct arm_arch_option_table
22435 const arm_feature_set value
;
22436 const arm_feature_set default_fpu
;
22439 /* This list should, at a minimum, contain all the architecture names
22440 recognized by GCC. */
22441 static const struct arm_arch_option_table arm_archs
[] =
22443 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22444 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22445 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22446 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22447 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22448 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22449 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22450 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22451 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22452 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22453 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22454 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22455 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22456 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22457 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22458 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22459 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22460 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22461 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22462 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22463 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22464 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22465 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22466 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22467 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22468 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22469 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22470 {"armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
},
22471 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22472 /* The official spelling of the ARMv7 profile variants is the dashed form.
22473 Accept the non-dashed form for compatibility with old toolchains. */
22474 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22475 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22476 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22477 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22478 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22479 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22480 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22481 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22482 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22483 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22484 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22487 /* ISA extensions in the co-processor and main instruction set space. */
22488 struct arm_option_extension_value_table
22491 const arm_feature_set value
;
22492 const arm_feature_set allowed_archs
;
22495 /* The following table must be in alphabetical order with a NULL last entry.
22497 static const struct arm_option_extension_value_table arm_extensions
[] =
22499 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
22500 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
22501 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
22502 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
22503 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22504 {"os", ARM_FEATURE (ARM_EXT_OS
, 0),
22505 ARM_FEATURE (ARM_EXT_V6M
, 0)},
22506 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
22507 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
22508 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
22509 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22512 /* ISA floating-point and Advanced SIMD extensions. */
22513 struct arm_option_fpu_value_table
22516 const arm_feature_set value
;
22519 /* This list should, at a minimum, contain all the fpu names
22520 recognized by GCC. */
22521 static const struct arm_option_fpu_value_table arm_fpus
[] =
22523 {"softfpa", FPU_NONE
},
22524 {"fpe", FPU_ARCH_FPE
},
22525 {"fpe2", FPU_ARCH_FPE
},
22526 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22527 {"fpa", FPU_ARCH_FPA
},
22528 {"fpa10", FPU_ARCH_FPA
},
22529 {"fpa11", FPU_ARCH_FPA
},
22530 {"arm7500fe", FPU_ARCH_FPA
},
22531 {"softvfp", FPU_ARCH_VFP
},
22532 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22533 {"vfp", FPU_ARCH_VFP_V2
},
22534 {"vfp9", FPU_ARCH_VFP_V2
},
22535 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22536 {"vfp10", FPU_ARCH_VFP_V2
},
22537 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22538 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22539 {"vfpv2", FPU_ARCH_VFP_V2
},
22540 {"vfpv3", FPU_ARCH_VFP_V3
},
22541 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22542 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22543 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22544 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22545 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22546 {"arm1020t", FPU_ARCH_VFP_V1
},
22547 {"arm1020e", FPU_ARCH_VFP_V2
},
22548 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22549 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22550 {"maverick", FPU_ARCH_MAVERICK
},
22551 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22552 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22553 {"vfpv4", FPU_ARCH_VFP_V4
},
22554 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22555 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22556 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22557 {NULL
, ARM_ARCH_NONE
}
22560 struct arm_option_value_table
22566 static const struct arm_option_value_table arm_float_abis
[] =
22568 {"hard", ARM_FLOAT_ABI_HARD
},
22569 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22570 {"soft", ARM_FLOAT_ABI_SOFT
},
22575 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22576 static const struct arm_option_value_table arm_eabis
[] =
22578 {"gnu", EF_ARM_EABI_UNKNOWN
},
22579 {"4", EF_ARM_EABI_VER4
},
22580 {"5", EF_ARM_EABI_VER5
},
22585 struct arm_long_option_table
22587 char * option
; /* Substring to match. */
22588 char * help
; /* Help information. */
22589 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22590 char * deprecated
; /* If non-null, print this message. */
22594 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22596 arm_feature_set
*ext_set
= (arm_feature_set
*)
22597 xmalloc (sizeof (arm_feature_set
));
22599 /* We insist on extensions being specified in alphabetical order, and with
22600 extensions being added before being removed. We achieve this by having
22601 the global ARM_EXTENSIONS table in alphabetical order, and using the
22602 ADDING_VALUE variable to indicate whether we are adding an extension (1)
22603 or removing it (0) and only allowing it to change in the order
22605 const struct arm_option_extension_value_table
* opt
= NULL
;
22606 int adding_value
= -1;
22608 /* Copy the feature set, so that we can modify it. */
22609 *ext_set
= **opt_p
;
22612 while (str
!= NULL
&& *str
!= 0)
22619 as_bad (_("invalid architectural extension"));
22624 ext
= strchr (str
, '+');
22627 optlen
= ext
- str
;
22629 optlen
= strlen (str
);
22632 && strncmp (str
, "no", 2) == 0)
22634 if (adding_value
!= 0)
22637 opt
= arm_extensions
;
22643 else if (optlen
> 0)
22645 if (adding_value
== -1)
22648 opt
= arm_extensions
;
22650 else if (adding_value
!= 1)
22652 as_bad (_("must specify extensions to add before specifying "
22653 "those to remove"));
22660 as_bad (_("missing architectural extension"));
22664 gas_assert (adding_value
!= -1);
22665 gas_assert (opt
!= NULL
);
22667 /* Scan over the options table trying to find an exact match. */
22668 for (; opt
->name
!= NULL
; opt
++)
22669 if (strncmp (opt
->name
, str
, optlen
) == 0
22670 && strlen (opt
->name
) == optlen
)
22672 /* Check we can apply the extension to this architecture. */
22673 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
22675 as_bad (_("extension does not apply to the base architecture"));
22679 /* Add or remove the extension. */
22681 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22683 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
22688 if (opt
->name
== NULL
)
22690 /* Did we fail to find an extension because it wasn't specified in
22691 alphabetical order, or because it does not exist? */
22693 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22694 if (strncmp (opt
->name
, str
, optlen
) == 0)
22697 if (opt
->name
== NULL
)
22698 as_bad (_("unknown architectural extension `%s'"), str
);
22700 as_bad (_("architectural extensions must be specified in "
22701 "alphabetical order"));
22707 /* We should skip the extension we've just matched the next time
22719 arm_parse_cpu (char * str
)
22721 const struct arm_cpu_option_table
* opt
;
22722 char * ext
= strchr (str
, '+');
22726 optlen
= ext
- str
;
22728 optlen
= strlen (str
);
22732 as_bad (_("missing cpu name `%s'"), str
);
22736 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22737 if (strncmp (opt
->name
, str
, optlen
) == 0)
22739 mcpu_cpu_opt
= &opt
->value
;
22740 mcpu_fpu_opt
= &opt
->default_fpu
;
22741 if (opt
->canonical_name
)
22742 strcpy (selected_cpu_name
, opt
->canonical_name
);
22747 for (i
= 0; i
< optlen
; i
++)
22748 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22749 selected_cpu_name
[i
] = 0;
22753 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22758 as_bad (_("unknown cpu `%s'"), str
);
22763 arm_parse_arch (char * str
)
22765 const struct arm_arch_option_table
*opt
;
22766 char *ext
= strchr (str
, '+');
22770 optlen
= ext
- str
;
22772 optlen
= strlen (str
);
22776 as_bad (_("missing architecture name `%s'"), str
);
22780 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22781 if (strncmp (opt
->name
, str
, optlen
) == 0)
22783 march_cpu_opt
= &opt
->value
;
22784 march_fpu_opt
= &opt
->default_fpu
;
22785 strcpy (selected_cpu_name
, opt
->name
);
22788 return arm_parse_extension (ext
, &march_cpu_opt
);
22793 as_bad (_("unknown architecture `%s'\n"), str
);
22798 arm_parse_fpu (char * str
)
22800 const struct arm_option_fpu_value_table
* opt
;
22802 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22803 if (streq (opt
->name
, str
))
22805 mfpu_opt
= &opt
->value
;
22809 as_bad (_("unknown floating point format `%s'\n"), str
);
22814 arm_parse_float_abi (char * str
)
22816 const struct arm_option_value_table
* opt
;
22818 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22819 if (streq (opt
->name
, str
))
22821 mfloat_abi_opt
= opt
->value
;
22825 as_bad (_("unknown floating point abi `%s'\n"), str
);
22831 arm_parse_eabi (char * str
)
22833 const struct arm_option_value_table
*opt
;
22835 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22836 if (streq (opt
->name
, str
))
22838 meabi_flags
= opt
->value
;
22841 as_bad (_("unknown EABI `%s'\n"), str
);
22847 arm_parse_it_mode (char * str
)
22849 bfd_boolean ret
= TRUE
;
22851 if (streq ("arm", str
))
22852 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22853 else if (streq ("thumb", str
))
22854 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22855 else if (streq ("always", str
))
22856 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22857 else if (streq ("never", str
))
22858 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22861 as_bad (_("unknown implicit IT mode `%s', should be "\
22862 "arm, thumb, always, or never."), str
);
22869 struct arm_long_option_table arm_long_opts
[] =
22871 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22872 arm_parse_cpu
, NULL
},
22873 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22874 arm_parse_arch
, NULL
},
22875 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22876 arm_parse_fpu
, NULL
},
22877 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22878 arm_parse_float_abi
, NULL
},
22880 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22881 arm_parse_eabi
, NULL
},
22883 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22884 arm_parse_it_mode
, NULL
},
22885 {NULL
, NULL
, 0, NULL
}
22889 md_parse_option (int c
, char * arg
)
22891 struct arm_option_table
*opt
;
22892 const struct arm_legacy_option_table
*fopt
;
22893 struct arm_long_option_table
*lopt
;
22899 target_big_endian
= 1;
22905 target_big_endian
= 0;
22909 case OPTION_FIX_V4BX
:
22914 /* Listing option. Just ignore these, we don't support additional
22919 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22921 if (c
== opt
->option
[0]
22922 && ((arg
== NULL
&& opt
->option
[1] == 0)
22923 || streq (arg
, opt
->option
+ 1)))
22925 /* If the option is deprecated, tell the user. */
22926 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22927 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22928 arg
? arg
: "", _(opt
->deprecated
));
22930 if (opt
->var
!= NULL
)
22931 *opt
->var
= opt
->value
;
22937 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22939 if (c
== fopt
->option
[0]
22940 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22941 || streq (arg
, fopt
->option
+ 1)))
22943 /* If the option is deprecated, tell the user. */
22944 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22945 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22946 arg
? arg
: "", _(fopt
->deprecated
));
22948 if (fopt
->var
!= NULL
)
22949 *fopt
->var
= &fopt
->value
;
22955 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22957 /* These options are expected to have an argument. */
22958 if (c
== lopt
->option
[0]
22960 && strncmp (arg
, lopt
->option
+ 1,
22961 strlen (lopt
->option
+ 1)) == 0)
22963 /* If the option is deprecated, tell the user. */
22964 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22965 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22966 _(lopt
->deprecated
));
22968 /* Call the sup-option parser. */
22969 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22980 md_show_usage (FILE * fp
)
22982 struct arm_option_table
*opt
;
22983 struct arm_long_option_table
*lopt
;
22985 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22987 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22988 if (opt
->help
!= NULL
)
22989 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22991 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22992 if (lopt
->help
!= NULL
)
22993 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22997 -EB assemble code for a big-endian cpu\n"));
23002 -EL assemble code for a little-endian cpu\n"));
23006 --fix-v4bx Allow BX in ARMv4 code\n"));
23014 arm_feature_set flags
;
23015 } cpu_arch_ver_table
;
23017 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23018 least features first. */
23019 static const cpu_arch_ver_table cpu_arch_ver
[] =
23025 {4, ARM_ARCH_V5TE
},
23026 {5, ARM_ARCH_V5TEJ
},
23030 {11, ARM_ARCH_V6M
},
23031 {12, ARM_ARCH_V6SM
},
23032 {8, ARM_ARCH_V6T2
},
23033 {10, ARM_ARCH_V7A
},
23034 {10, ARM_ARCH_V7R
},
23035 {10, ARM_ARCH_V7M
},
23039 /* Set an attribute if it has not already been set by the user. */
23041 aeabi_set_attribute_int (int tag
, int value
)
23044 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23045 || !attributes_set_explicitly
[tag
])
23046 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23050 aeabi_set_attribute_string (int tag
, const char *value
)
23053 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23054 || !attributes_set_explicitly
[tag
])
23055 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23058 /* Set the public EABI object attributes. */
23060 aeabi_set_public_attributes (void)
23063 arm_feature_set flags
;
23064 arm_feature_set tmp
;
23065 const cpu_arch_ver_table
*p
;
23067 /* Choose the architecture based on the capabilities of the requested cpu
23068 (if any) and/or the instructions actually used. */
23069 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23070 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23071 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23072 /*Allow the user to override the reported architecture. */
23075 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23076 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23081 for (p
= cpu_arch_ver
; p
->val
; p
++)
23083 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23086 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23090 /* The table lookup above finds the last architecture to contribute
23091 a new feature. Unfortunately, Tag13 is a subset of the union of
23092 v6T2 and v7-M, so it is never seen as contributing a new feature.
23093 We can not search for the last entry which is entirely used,
23094 because if no CPU is specified we build up only those flags
23095 actually used. Perhaps we should separate out the specified
23096 and implicit cases. Avoid taking this path for -march=all by
23097 checking for contradictory v7-A / v7-M features. */
23099 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23100 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23101 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23104 /* Tag_CPU_name. */
23105 if (selected_cpu_name
[0])
23109 q
= selected_cpu_name
;
23110 if (strncmp (q
, "armv", 4) == 0)
23115 for (i
= 0; q
[i
]; i
++)
23116 q
[i
] = TOUPPER (q
[i
]);
23118 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23121 /* Tag_CPU_arch. */
23122 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23124 /* Tag_CPU_arch_profile. */
23125 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23126 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23127 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23128 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23129 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23130 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23132 /* Tag_ARM_ISA_use. */
23133 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23135 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23137 /* Tag_THUMB_ISA_use. */
23138 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23140 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23141 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23143 /* Tag_VFP_arch. */
23144 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23145 aeabi_set_attribute_int (Tag_VFP_arch
,
23146 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23148 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23149 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23150 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23151 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23152 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23153 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23154 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23155 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23156 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23158 /* Tag_ABI_HardFP_use. */
23159 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23160 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23161 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23163 /* Tag_WMMX_arch. */
23164 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23165 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23166 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23167 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23169 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23170 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23171 aeabi_set_attribute_int
23172 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23175 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23176 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23177 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23180 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23181 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23182 /* Fill this in when gas supports v7a sdiv/udiv.
23183 else if (... v7a with div extension used ...)
23184 aeabi_set_attribute_int (Tag_DIV_use, 2); */
23186 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23188 /* Tag_MP_extension_use. */
23189 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23190 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23192 /* Tag Virtualization_use. */
23193 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23194 aeabi_set_attribute_int (Tag_Virtualization_use
, 1);
23197 /* Add the default contents for the .ARM.attributes section. */
23201 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23204 aeabi_set_public_attributes ();
23206 #endif /* OBJ_ELF */
23209 /* Parse a .cpu directive. */
23212 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23214 const struct arm_cpu_option_table
*opt
;
23218 name
= input_line_pointer
;
23219 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23220 input_line_pointer
++;
23221 saved_char
= *input_line_pointer
;
23222 *input_line_pointer
= 0;
23224 /* Skip the first "all" entry. */
23225 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23226 if (streq (opt
->name
, name
))
23228 mcpu_cpu_opt
= &opt
->value
;
23229 selected_cpu
= opt
->value
;
23230 if (opt
->canonical_name
)
23231 strcpy (selected_cpu_name
, opt
->canonical_name
);
23235 for (i
= 0; opt
->name
[i
]; i
++)
23236 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23237 selected_cpu_name
[i
] = 0;
23239 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23240 *input_line_pointer
= saved_char
;
23241 demand_empty_rest_of_line ();
23244 as_bad (_("unknown cpu `%s'"), name
);
23245 *input_line_pointer
= saved_char
;
23246 ignore_rest_of_line ();
23250 /* Parse a .arch directive. */
23253 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23255 const struct arm_arch_option_table
*opt
;
23259 name
= input_line_pointer
;
23260 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23261 input_line_pointer
++;
23262 saved_char
= *input_line_pointer
;
23263 *input_line_pointer
= 0;
23265 /* Skip the first "all" entry. */
23266 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23267 if (streq (opt
->name
, name
))
23269 mcpu_cpu_opt
= &opt
->value
;
23270 selected_cpu
= opt
->value
;
23271 strcpy (selected_cpu_name
, opt
->name
);
23272 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23273 *input_line_pointer
= saved_char
;
23274 demand_empty_rest_of_line ();
23278 as_bad (_("unknown architecture `%s'\n"), name
);
23279 *input_line_pointer
= saved_char
;
23280 ignore_rest_of_line ();
23284 /* Parse a .object_arch directive. */
23287 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23289 const struct arm_arch_option_table
*opt
;
23293 name
= input_line_pointer
;
23294 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23295 input_line_pointer
++;
23296 saved_char
= *input_line_pointer
;
23297 *input_line_pointer
= 0;
23299 /* Skip the first "all" entry. */
23300 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23301 if (streq (opt
->name
, name
))
23303 object_arch
= &opt
->value
;
23304 *input_line_pointer
= saved_char
;
23305 demand_empty_rest_of_line ();
23309 as_bad (_("unknown architecture `%s'\n"), name
);
23310 *input_line_pointer
= saved_char
;
23311 ignore_rest_of_line ();
23314 /* Parse a .arch_extension directive. */
23317 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23319 const struct arm_option_extension_value_table
*opt
;
23322 int adding_value
= 1;
23324 name
= input_line_pointer
;
23325 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23326 input_line_pointer
++;
23327 saved_char
= *input_line_pointer
;
23328 *input_line_pointer
= 0;
23330 if (strlen (name
) >= 2
23331 && strncmp (name
, "no", 2) == 0)
23337 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23338 if (streq (opt
->name
, name
))
23340 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23342 as_bad (_("architectural extension `%s' is not allowed for the "
23343 "current base architecture"), name
);
23348 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23350 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23352 mcpu_cpu_opt
= &selected_cpu
;
23353 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23354 *input_line_pointer
= saved_char
;
23355 demand_empty_rest_of_line ();
23359 if (opt
->name
== NULL
)
23360 as_bad (_("unknown architecture `%s'\n"), name
);
23362 *input_line_pointer
= saved_char
;
23363 ignore_rest_of_line ();
23366 /* Parse a .fpu directive. */
23369 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23371 const struct arm_option_fpu_value_table
*opt
;
23375 name
= input_line_pointer
;
23376 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23377 input_line_pointer
++;
23378 saved_char
= *input_line_pointer
;
23379 *input_line_pointer
= 0;
23381 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23382 if (streq (opt
->name
, name
))
23384 mfpu_opt
= &opt
->value
;
23385 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23386 *input_line_pointer
= saved_char
;
23387 demand_empty_rest_of_line ();
23391 as_bad (_("unknown floating point format `%s'\n"), name
);
23392 *input_line_pointer
= saved_char
;
23393 ignore_rest_of_line ();
23396 /* Copy symbol information. */
23399 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23401 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23405 /* Given a symbolic attribute NAME, return the proper integer value.
23406 Returns -1 if the attribute is not known. */
23409 arm_convert_symbolic_attribute (const char *name
)
23411 static const struct
23416 attribute_table
[] =
23418 /* When you modify this table you should
23419 also modify the list in doc/c-arm.texi. */
23420 #define T(tag) {#tag, tag}
23421 T (Tag_CPU_raw_name
),
23424 T (Tag_CPU_arch_profile
),
23425 T (Tag_ARM_ISA_use
),
23426 T (Tag_THUMB_ISA_use
),
23430 T (Tag_Advanced_SIMD_arch
),
23431 T (Tag_PCS_config
),
23432 T (Tag_ABI_PCS_R9_use
),
23433 T (Tag_ABI_PCS_RW_data
),
23434 T (Tag_ABI_PCS_RO_data
),
23435 T (Tag_ABI_PCS_GOT_use
),
23436 T (Tag_ABI_PCS_wchar_t
),
23437 T (Tag_ABI_FP_rounding
),
23438 T (Tag_ABI_FP_denormal
),
23439 T (Tag_ABI_FP_exceptions
),
23440 T (Tag_ABI_FP_user_exceptions
),
23441 T (Tag_ABI_FP_number_model
),
23442 T (Tag_ABI_align_needed
),
23443 T (Tag_ABI_align8_needed
),
23444 T (Tag_ABI_align_preserved
),
23445 T (Tag_ABI_align8_preserved
),
23446 T (Tag_ABI_enum_size
),
23447 T (Tag_ABI_HardFP_use
),
23448 T (Tag_ABI_VFP_args
),
23449 T (Tag_ABI_WMMX_args
),
23450 T (Tag_ABI_optimization_goals
),
23451 T (Tag_ABI_FP_optimization_goals
),
23452 T (Tag_compatibility
),
23453 T (Tag_CPU_unaligned_access
),
23454 T (Tag_FP_HP_extension
),
23455 T (Tag_VFP_HP_extension
),
23456 T (Tag_ABI_FP_16bit_format
),
23457 T (Tag_MPextension_use
),
23459 T (Tag_nodefaults
),
23460 T (Tag_also_compatible_with
),
23461 T (Tag_conformance
),
23463 T (Tag_Virtualization_use
),
23464 /* We deliberately do not include Tag_MPextension_use_legacy. */
23472 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23473 if (streq (name
, attribute_table
[i
].name
))
23474 return attribute_table
[i
].tag
;
23480 /* Apply sym value for relocations only in the case that
23481 they are for local symbols and you have the respective
23482 architectural feature for blx and simple switches. */
23484 arm_apply_sym_value (struct fix
* fixP
)
23487 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23488 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23490 switch (fixP
->fx_r_type
)
23492 case BFD_RELOC_ARM_PCREL_BLX
:
23493 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23494 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23498 case BFD_RELOC_ARM_PCREL_CALL
:
23499 case BFD_RELOC_THUMB_PCREL_BLX
:
23500 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23511 #endif /* OBJ_ELF */