1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
40 #include "opcode/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
60 symbolS
* table_entry
;
61 symbolS
* personality_routine
;
62 int personality_index
;
63 /* The segment containing the function. */
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes
;
70 /* The number of bytes pushed to the stack. */
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset
;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
80 /* Nonzero if an unwind_setfp directive has been seen. */
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored
:1;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency
= 0;
100 /* Types of processor to assemble for. */
102 #if defined __XSCALE__
103 #define CPU_DEFAULT ARM_ARCH_XSCALE
105 #if defined __thumb__
106 #define CPU_DEFAULT ARM_ARCH_V5T
113 # define FPU_DEFAULT FPU_ARCH_FPA
114 # elif defined (TE_NetBSD)
116 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
118 /* Legacy a.out format. */
119 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
121 # elif defined (TE_VXWORKS)
122 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
124 /* For backwards compatibility, default to FPA. */
125 # define FPU_DEFAULT FPU_ARCH_FPA
127 #endif /* ifndef FPU_DEFAULT */
129 #define streq(a, b) (strcmp (a, b) == 0)
131 static arm_feature_set cpu_variant
;
132 static arm_feature_set arm_arch_used
;
133 static arm_feature_set thumb_arch_used
;
135 /* Flags stored in private area of BFD structure. */
136 static int uses_apcs_26
= FALSE
;
137 static int atpcs
= FALSE
;
138 static int support_interwork
= FALSE
;
139 static int uses_apcs_float
= FALSE
;
140 static int pic_code
= FALSE
;
142 /* Variables that we set while parsing command-line options. Once all
143 options have been read we re-process these values to set the real
145 static const arm_feature_set
*legacy_cpu
= NULL
;
146 static const arm_feature_set
*legacy_fpu
= NULL
;
148 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
149 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
150 static const arm_feature_set
*march_cpu_opt
= NULL
;
151 static const arm_feature_set
*march_fpu_opt
= NULL
;
152 static const arm_feature_set
*mfpu_opt
= NULL
;
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
156 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
157 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
158 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
159 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
160 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
161 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
164 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
167 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
168 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
169 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
170 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
171 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
172 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
173 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
174 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
175 static const arm_feature_set arm_ext_v4t_5
=
176 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
177 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
178 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
179 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
180 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
181 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
182 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
183 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
184 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
185 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
186 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
187 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
188 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
189 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
190 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
192 static const arm_feature_set arm_arch_any
= ARM_ANY
;
193 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
194 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
195 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
197 static const arm_feature_set arm_cext_iwmmxt
=
198 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
199 static const arm_feature_set arm_cext_xscale
=
200 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
201 static const arm_feature_set arm_cext_maverick
=
202 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
203 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
204 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
205 static const arm_feature_set fpu_vfp_ext_v1xd
=
206 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
207 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
208 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
210 static int mfloat_abi_opt
= -1;
211 /* Record user cpu selection for object attributes. */
212 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
213 /* Must be long enough to hold any of the names in arm_cpus. */
214 static char selected_cpu_name
[16];
217 static int meabi_flags
= EABI_DEFAULT
;
219 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
224 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
225 symbolS
* GOT_symbol
;
228 /* 0: assemble for ARM,
229 1: assemble for Thumb,
230 2: assemble for Thumb even though target CPU does not support thumb
232 static int thumb_mode
= 0;
234 /* If unified_syntax is true, we are processing the new unified
235 ARM/Thumb syntax. Important differences from the old ARM mode:
237 - Immediate operands do not require a # prefix.
238 - Conditional affixes always appear at the end of the
239 instruction. (For backward compatibility, those instructions
240 that formerly had them in the middle, continue to accept them
242 - The IT instruction may appear, and if it does is validated
243 against subsequent conditional affixes. It does not generate
246 Important differences from the old Thumb mode:
248 - Immediate operands do not require a # prefix.
249 - Most of the V6T2 instructions are only available in unified mode.
250 - The .N and .W suffixes are recognized and honored (it is an error
251 if they cannot be honored).
252 - All instructions set the flags if and only if they have an 's' affix.
253 - Conditional affixes may be used. They are validated against
254 preceding IT instructions. Unlike ARM mode, you cannot use a
255 conditional affix except in the scope of an IT instruction. */
257 static bfd_boolean unified_syntax
= FALSE
;
262 unsigned long instruction
;
266 /* Set to the opcode if the instruction needs relaxation.
267 Zero if the instruction is not relaxed. */
271 bfd_reloc_code_real_type type
;
280 unsigned present
: 1; /* Operand present. */
281 unsigned isreg
: 1; /* Operand was a register. */
282 unsigned immisreg
: 1; /* .imm field is a second register. */
283 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
284 unsigned writeback
: 1; /* Operand has trailing ! */
285 unsigned preind
: 1; /* Preindexed address. */
286 unsigned postind
: 1; /* Postindexed address. */
287 unsigned negative
: 1; /* Index register was negated. */
288 unsigned shifted
: 1; /* Shift applied to operation. */
289 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
293 static struct arm_it inst
;
295 #define NUM_FLOAT_VALS 8
297 const char * fp_const
[] =
299 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
302 /* Number of littlenums required to hold an extended precision number. */
303 #define MAX_LITTLENUMS 6
305 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
315 #define CP_T_X 0x00008000
316 #define CP_T_Y 0x00400000
318 #define CONDS_BIT 0x00100000
319 #define LOAD_BIT 0x00100000
321 #define DOUBLE_LOAD_FLAG 0x00000001
325 const char * template;
329 #define COND_ALWAYS 0xE
333 const char *template;
337 struct asm_barrier_opt
339 const char *template;
343 /* The bit that distinguishes CPSR and SPSR. */
344 #define SPSR_BIT (1 << 22)
346 /* The individual PSR flag bits. */
347 #define PSR_c (1 << 16)
348 #define PSR_x (1 << 17)
349 #define PSR_s (1 << 18)
350 #define PSR_f (1 << 19)
355 bfd_reloc_code_real_type reloc
;
360 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
365 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
368 /* ARM register categories. This includes coprocessor numbers and various
369 architecture extensions' registers. */
391 /* Structure for a hash table entry for a register. */
395 unsigned char number
;
397 unsigned char builtin
;
400 /* Diagnostics used when we don't get a register of the expected type. */
401 const char *const reg_expected_msgs
[] =
403 N_("ARM register expected"),
404 N_("bad or missing co-processor number"),
405 N_("co-processor register expected"),
406 N_("FPA register expected"),
407 N_("VFP single precision register expected"),
408 N_("VFP double precision register expected"),
409 N_("VFP system register expected"),
410 N_("Maverick MVF register expected"),
411 N_("Maverick MVD register expected"),
412 N_("Maverick MVFX register expected"),
413 N_("Maverick MVDX register expected"),
414 N_("Maverick MVAX register expected"),
415 N_("Maverick DSPSC register expected"),
416 N_("iWMMXt data register expected"),
417 N_("iWMMXt control register expected"),
418 N_("iWMMXt scalar register expected"),
419 N_("XScale accumulator register expected"),
422 /* Some well known registers that we refer to directly elsewhere. */
427 /* ARM instructions take 4bytes in the object file, Thumb instructions
433 /* Basic string to match. */
434 const char *template;
436 /* Parameters to instruction. */
437 unsigned char operands
[8];
439 /* Conditional tag - see opcode_lookup. */
440 unsigned int tag
: 4;
442 /* Basic instruction code. */
443 unsigned int avalue
: 28;
445 /* Thumb-format instruction code. */
448 /* Which architecture variant provides this instruction. */
449 const arm_feature_set
*avariant
;
450 const arm_feature_set
*tvariant
;
452 /* Function to call to encode instruction in ARM format. */
453 void (* aencode
) (void);
455 /* Function to call to encode instruction in Thumb format. */
456 void (* tencode
) (void);
459 /* Defines for various bits that we will want to toggle. */
460 #define INST_IMMEDIATE 0x02000000
461 #define OFFSET_REG 0x02000000
462 #define HWOFFSET_IMM 0x00400000
463 #define SHIFT_BY_REG 0x00000010
464 #define PRE_INDEX 0x01000000
465 #define INDEX_UP 0x00800000
466 #define WRITE_BACK 0x00200000
467 #define LDM_TYPE_2_OR_3 0x00400000
469 #define LITERAL_MASK 0xf000f000
470 #define OPCODE_MASK 0xfe1fffff
471 #define V4_STR_BIT 0x00000020
473 #define DATA_OP_SHIFT 21
475 #define T2_OPCODE_MASK 0xfe1fffff
476 #define T2_DATA_OP_SHIFT 21
478 /* Codes to distinguish the arithmetic instructions. */
489 #define OPCODE_CMP 10
490 #define OPCODE_CMN 11
491 #define OPCODE_ORR 12
492 #define OPCODE_MOV 13
493 #define OPCODE_BIC 14
494 #define OPCODE_MVN 15
496 #define T2_OPCODE_AND 0
497 #define T2_OPCODE_BIC 1
498 #define T2_OPCODE_ORR 2
499 #define T2_OPCODE_ORN 3
500 #define T2_OPCODE_EOR 4
501 #define T2_OPCODE_ADD 8
502 #define T2_OPCODE_ADC 10
503 #define T2_OPCODE_SBC 11
504 #define T2_OPCODE_SUB 13
505 #define T2_OPCODE_RSB 14
507 #define T_OPCODE_MUL 0x4340
508 #define T_OPCODE_TST 0x4200
509 #define T_OPCODE_CMN 0x42c0
510 #define T_OPCODE_NEG 0x4240
511 #define T_OPCODE_MVN 0x43c0
513 #define T_OPCODE_ADD_R3 0x1800
514 #define T_OPCODE_SUB_R3 0x1a00
515 #define T_OPCODE_ADD_HI 0x4400
516 #define T_OPCODE_ADD_ST 0xb000
517 #define T_OPCODE_SUB_ST 0xb080
518 #define T_OPCODE_ADD_SP 0xa800
519 #define T_OPCODE_ADD_PC 0xa000
520 #define T_OPCODE_ADD_I8 0x3000
521 #define T_OPCODE_SUB_I8 0x3800
522 #define T_OPCODE_ADD_I3 0x1c00
523 #define T_OPCODE_SUB_I3 0x1e00
525 #define T_OPCODE_ASR_R 0x4100
526 #define T_OPCODE_LSL_R 0x4080
527 #define T_OPCODE_LSR_R 0x40c0
528 #define T_OPCODE_ROR_R 0x41c0
529 #define T_OPCODE_ASR_I 0x1000
530 #define T_OPCODE_LSL_I 0x0000
531 #define T_OPCODE_LSR_I 0x0800
533 #define T_OPCODE_MOV_I8 0x2000
534 #define T_OPCODE_CMP_I8 0x2800
535 #define T_OPCODE_CMP_LR 0x4280
536 #define T_OPCODE_MOV_HR 0x4600
537 #define T_OPCODE_CMP_HR 0x4500
539 #define T_OPCODE_LDR_PC 0x4800
540 #define T_OPCODE_LDR_SP 0x9800
541 #define T_OPCODE_STR_SP 0x9000
542 #define T_OPCODE_LDR_IW 0x6800
543 #define T_OPCODE_STR_IW 0x6000
544 #define T_OPCODE_LDR_IH 0x8800
545 #define T_OPCODE_STR_IH 0x8000
546 #define T_OPCODE_LDR_IB 0x7800
547 #define T_OPCODE_STR_IB 0x7000
548 #define T_OPCODE_LDR_RW 0x5800
549 #define T_OPCODE_STR_RW 0x5000
550 #define T_OPCODE_LDR_RH 0x5a00
551 #define T_OPCODE_STR_RH 0x5200
552 #define T_OPCODE_LDR_RB 0x5c00
553 #define T_OPCODE_STR_RB 0x5400
555 #define T_OPCODE_PUSH 0xb400
556 #define T_OPCODE_POP 0xbc00
558 #define T_OPCODE_BRANCH 0xe000
560 #define THUMB_SIZE 2 /* Size of thumb instruction. */
561 #define THUMB_PP_PC_LR 0x0100
562 #define THUMB_LOAD_BIT 0x0800
564 #define BAD_ARGS _("bad arguments to instruction")
565 #define BAD_PC _("r15 not allowed here")
566 #define BAD_COND _("instruction cannot be conditional")
567 #define BAD_OVERLAP _("registers may not be the same")
568 #define BAD_HIREG _("lo register required")
569 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
570 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
571 #define BAD_BRANCH _("branch must be last instruction in IT block")
572 #define BAD_NOT_IT _("instruction not allowed in IT block")
574 static struct hash_control
*arm_ops_hsh
;
575 static struct hash_control
*arm_cond_hsh
;
576 static struct hash_control
*arm_shift_hsh
;
577 static struct hash_control
*arm_psr_hsh
;
578 static struct hash_control
*arm_v7m_psr_hsh
;
579 static struct hash_control
*arm_reg_hsh
;
580 static struct hash_control
*arm_reloc_hsh
;
581 static struct hash_control
*arm_barrier_opt_hsh
;
583 /* Stuff needed to resolve the label ambiguity
593 symbolS
* last_label_seen
;
594 static int label_is_thumb_function_name
= FALSE
;
596 /* Literal pool structure. Held on a per-section
597 and per-sub-section basis. */
599 #define MAX_LITERAL_POOL_SIZE 1024
600 typedef struct literal_pool
602 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
603 unsigned int next_free_entry
;
608 struct literal_pool
* next
;
611 /* Pointer to a linked list of literal pools. */
612 literal_pool
* list_of_pools
= NULL
;
614 /* State variables for IT block handling. */
615 static bfd_boolean current_it_mask
= 0;
616 static int current_cc
;
621 /* This array holds the chars that always start a comment. If the
622 pre-processor is disabled, these aren't very useful. */
623 const char comment_chars
[] = "@";
625 /* This array holds the chars that only start a comment at the beginning of
626 a line. If the line seems to have the form '# 123 filename'
627 .line and .file directives will appear in the pre-processed output. */
628 /* Note that input_file.c hand checks for '#' at the beginning of the
629 first line of the input file. This is because the compiler outputs
630 #NO_APP at the beginning of its output. */
631 /* Also note that comments like this one will always work. */
632 const char line_comment_chars
[] = "#";
634 const char line_separator_chars
[] = ";";
636 /* Chars that can be used to separate mant
637 from exp in floating point numbers. */
638 const char EXP_CHARS
[] = "eE";
640 /* Chars that mean this number is a floating point constant. */
644 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
646 /* Prefix characters that indicate the start of an immediate
648 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
650 /* Separator character handling. */
652 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
655 skip_past_char (char ** str
, char c
)
665 #define skip_past_comma(str) skip_past_char (str, ',')
667 /* Arithmetic expressions (possibly involving symbols). */
669 /* Return TRUE if anything in the expression is a bignum. */
672 walk_no_bignums (symbolS
* sp
)
674 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
677 if (symbol_get_value_expression (sp
)->X_add_symbol
)
679 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
680 || (symbol_get_value_expression (sp
)->X_op_symbol
681 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
687 static int in_my_get_expression
= 0;
689 /* Third argument to my_get_expression. */
690 #define GE_NO_PREFIX 0
691 #define GE_IMM_PREFIX 1
692 #define GE_OPT_PREFIX 2
695 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
700 /* In unified syntax, all prefixes are optional. */
702 prefix_mode
= GE_OPT_PREFIX
;
706 case GE_NO_PREFIX
: break;
708 if (!is_immediate_prefix (**str
))
710 inst
.error
= _("immediate expression requires a # prefix");
716 if (is_immediate_prefix (**str
))
722 memset (ep
, 0, sizeof (expressionS
));
724 save_in
= input_line_pointer
;
725 input_line_pointer
= *str
;
726 in_my_get_expression
= 1;
727 seg
= expression (ep
);
728 in_my_get_expression
= 0;
730 if (ep
->X_op
== O_illegal
)
732 /* We found a bad expression in md_operand(). */
733 *str
= input_line_pointer
;
734 input_line_pointer
= save_in
;
735 if (inst
.error
== NULL
)
736 inst
.error
= _("bad expression");
741 if (seg
!= absolute_section
742 && seg
!= text_section
743 && seg
!= data_section
744 && seg
!= bss_section
745 && seg
!= undefined_section
)
747 inst
.error
= _("bad segment");
748 *str
= input_line_pointer
;
749 input_line_pointer
= save_in
;
754 /* Get rid of any bignums now, so that we don't generate an error for which
755 we can't establish a line number later on. Big numbers are never valid
756 in instructions, which is where this routine is always called. */
757 if (ep
->X_op
== O_big
759 && (walk_no_bignums (ep
->X_add_symbol
)
761 && walk_no_bignums (ep
->X_op_symbol
)))))
763 inst
.error
= _("invalid constant");
764 *str
= input_line_pointer
;
765 input_line_pointer
= save_in
;
769 *str
= input_line_pointer
;
770 input_line_pointer
= save_in
;
774 /* Turn a string in input_line_pointer into a floating point constant
775 of type TYPE, and store the appropriate bytes in *LITP. The number
776 of LITTLENUMS emitted is stored in *SIZEP. An error message is
777 returned, or NULL on OK.
779 Note that fp constants aren't represent in the normal way on the ARM.
780 In big endian mode, things are as expected. However, in little endian
781 mode fp constants are big-endian word-wise, and little-endian byte-wise
782 within the words. For example, (double) 1.1 in big endian mode is
783 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
784 the byte sequence 99 99 f1 3f 9a 99 99 99.
786 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
789 md_atof (int type
, char * litP
, int * sizeP
)
792 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
824 return _("bad call to MD_ATOF()");
827 t
= atof_ieee (input_line_pointer
, type
, words
);
829 input_line_pointer
= t
;
832 if (target_big_endian
)
834 for (i
= 0; i
< prec
; i
++)
836 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
842 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
843 for (i
= prec
- 1; i
>= 0; i
--)
845 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
849 /* For a 4 byte float the order of elements in `words' is 1 0.
850 For an 8 byte float the order is 1 0 3 2. */
851 for (i
= 0; i
< prec
; i
+= 2)
853 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
854 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
862 /* We handle all bad expressions here, so that we can report the faulty
863 instruction in the error message. */
865 md_operand (expressionS
* expr
)
867 if (in_my_get_expression
)
868 expr
->X_op
= O_illegal
;
871 /* Immediate values. */
873 /* Generic immediate-value read function for use in directives.
874 Accepts anything that 'expression' can fold to a constant.
875 *val receives the number. */
878 immediate_for_directive (int *val
)
881 exp
.X_op
= O_illegal
;
883 if (is_immediate_prefix (*input_line_pointer
))
885 input_line_pointer
++;
889 if (exp
.X_op
!= O_constant
)
891 as_bad (_("expected #constant"));
892 ignore_rest_of_line ();
895 *val
= exp
.X_add_number
;
900 /* Register parsing. */
902 /* Generic register parser. CCP points to what should be the
903 beginning of a register name. If it is indeed a valid register
904 name, advance CCP over it and return the reg_entry structure;
905 otherwise return NULL. Does not issue diagnostics. */
907 static struct reg_entry
*
908 arm_reg_parse_multi (char **ccp
)
912 struct reg_entry
*reg
;
914 #ifdef REGISTER_PREFIX
915 if (*start
!= REGISTER_PREFIX
)
919 #ifdef OPTIONAL_REGISTER_PREFIX
920 if (*start
== OPTIONAL_REGISTER_PREFIX
)
925 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
930 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
932 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
941 /* As above, but the register must be of type TYPE, and the return
942 value is the register number or FAIL. */
945 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
948 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
950 if (reg
&& reg
->type
== type
)
953 /* Alternative syntaxes are accepted for a few register classes. */
960 /* Generic coprocessor register names are allowed for these. */
961 if (reg
&& reg
->type
== REG_TYPE_CN
)
966 /* For backward compatibility, a bare number is valid here. */
968 unsigned long processor
= strtoul (start
, ccp
, 10);
969 if (*ccp
!= start
&& processor
<= 15)
974 /* WC includes WCG. ??? I'm not sure this is true for all
975 instructions that take WC registers. */
976 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
988 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
990 parse_reg_list (char ** strp
)
996 /* We come back here if we get ranges concatenated by '+' or '|'. */
1011 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1013 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
1023 inst
.error
= _("bad range in register list");
1027 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1029 if (range
& (1 << i
))
1031 (_("Warning: duplicated register (r%d) in register list"),
1039 if (range
& (1 << reg
))
1040 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1042 else if (reg
<= cur_reg
)
1043 as_tsktsk (_("Warning: register range not in ascending order"));
1048 while (skip_past_comma (&str
) != FAIL
1049 || (in_range
= 1, *str
++ == '-'));
1054 inst
.error
= _("missing `}'");
1062 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1065 if (expr
.X_op
== O_constant
)
1067 if (expr
.X_add_number
1068 != (expr
.X_add_number
& 0x0000ffff))
1070 inst
.error
= _("invalid register mask");
1074 if ((range
& expr
.X_add_number
) != 0)
1076 int regno
= range
& expr
.X_add_number
;
1079 regno
= (1 << regno
) - 1;
1081 (_("Warning: duplicated register (r%d) in register list"),
1085 range
|= expr
.X_add_number
;
1089 if (inst
.reloc
.type
!= 0)
1091 inst
.error
= _("expression too complex");
1095 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1096 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1097 inst
.reloc
.pc_rel
= 0;
1101 if (*str
== '|' || *str
== '+')
1107 while (another_range
);
1113 /* Parse a VFP register list. If the string is invalid return FAIL.
1114 Otherwise return the number of registers, and set PBASE to the first
1115 register. Double precision registers are matched if DP is nonzero. */
1118 parse_vfp_reg_list (char **str
, unsigned int *pbase
, int dp
)
1126 unsigned long mask
= 0;
1136 regtype
= REG_TYPE_VFD
;
1141 regtype
= REG_TYPE_VFS
;
1145 base_reg
= max_regs
;
1149 new_base
= arm_reg_parse (str
, regtype
);
1150 if (new_base
== FAIL
)
1152 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1156 if (new_base
< base_reg
)
1157 base_reg
= new_base
;
1159 if (mask
& (1 << new_base
))
1161 inst
.error
= _("invalid register list");
1165 if ((mask
>> new_base
) != 0 && ! warned
)
1167 as_tsktsk (_("register list not in ascending order"));
1171 mask
|= 1 << new_base
;
1174 if (**str
== '-') /* We have the start of a range expression */
1180 if ((high_range
= arm_reg_parse (str
, regtype
)) == FAIL
)
1182 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1186 if (high_range
<= new_base
)
1188 inst
.error
= _("register range not in ascending order");
1192 for (new_base
++; new_base
<= high_range
; new_base
++)
1194 if (mask
& (1 << new_base
))
1196 inst
.error
= _("invalid register list");
1200 mask
|= 1 << new_base
;
1205 while (skip_past_comma (str
) != FAIL
);
1209 /* Sanity check -- should have raised a parse error above. */
1210 if (count
== 0 || count
> max_regs
)
1215 /* Final test -- the registers must be consecutive. */
1217 for (i
= 0; i
< count
; i
++)
1219 if ((mask
& (1u << i
)) == 0)
1221 inst
.error
= _("non-contiguous register range");
1229 /* Parse an explicit relocation suffix on an expression. This is
1230 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1231 arm_reloc_hsh contains no entries, so this function can only
1232 succeed if there is no () after the word. Returns -1 on error,
1233 BFD_RELOC_UNUSED if there wasn't any suffix. */
1235 parse_reloc (char **str
)
1237 struct reloc_entry
*r
;
1241 return BFD_RELOC_UNUSED
;
1246 while (*q
&& *q
!= ')' && *q
!= ',')
1251 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1258 /* Directives: register aliases. */
1261 insert_reg_alias (char *str
, int number
, int type
)
1263 struct reg_entry
*new;
1266 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1269 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1271 /* Only warn about a redefinition if it's not defined as the
1273 else if (new->number
!= number
|| new->type
!= type
)
1274 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1279 name
= xstrdup (str
);
1280 new = xmalloc (sizeof (struct reg_entry
));
1283 new->number
= number
;
1285 new->builtin
= FALSE
;
1287 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1291 /* Look for the .req directive. This is of the form:
1293 new_register_name .req existing_register_name
1295 If we find one, or if it looks sufficiently like one that we want to
1296 handle any error here, return non-zero. Otherwise return zero. */
1299 create_register_alias (char * newname
, char *p
)
1301 struct reg_entry
*old
;
1302 char *oldname
, *nbuf
;
1305 /* The input scrubber ensures that whitespace after the mnemonic is
1306 collapsed to single spaces. */
1308 if (strncmp (oldname
, " .req ", 6) != 0)
1312 if (*oldname
== '\0')
1315 old
= hash_find (arm_reg_hsh
, oldname
);
1318 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1322 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1323 the desired alias name, and p points to its end. If not, then
1324 the desired alias name is in the global original_case_string. */
1325 #ifdef TC_CASE_SENSITIVE
1328 newname
= original_case_string
;
1329 nlen
= strlen (newname
);
1332 nbuf
= alloca (nlen
+ 1);
1333 memcpy (nbuf
, newname
, nlen
);
1336 /* Create aliases under the new name as stated; an all-lowercase
1337 version of the new name; and an all-uppercase version of the new
1339 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1341 for (p
= nbuf
; *p
; p
++)
1344 if (strncmp (nbuf
, newname
, nlen
))
1345 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1347 for (p
= nbuf
; *p
; p
++)
1350 if (strncmp (nbuf
, newname
, nlen
))
1351 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1356 /* Should never be called, as .req goes between the alias and the
1357 register name, not at the beginning of the line. */
1359 s_req (int a ATTRIBUTE_UNUSED
)
1361 as_bad (_("invalid syntax for .req directive"));
1364 /* The .unreq directive deletes an alias which was previously defined
1365 by .req. For example:
1371 s_unreq (int a ATTRIBUTE_UNUSED
)
1376 name
= input_line_pointer
;
1378 while (*input_line_pointer
!= 0
1379 && *input_line_pointer
!= ' '
1380 && *input_line_pointer
!= '\n')
1381 ++input_line_pointer
;
1383 saved_char
= *input_line_pointer
;
1384 *input_line_pointer
= 0;
1387 as_bad (_("invalid syntax for .unreq directive"));
1390 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
1393 as_bad (_("unknown register alias '%s'"), name
);
1394 else if (reg
->builtin
)
1395 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1399 hash_delete (arm_reg_hsh
, name
);
1400 free ((char *) reg
->name
);
1405 *input_line_pointer
= saved_char
;
1406 demand_empty_rest_of_line ();
1409 /* Directives: Instruction set selection. */
1412 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1413 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1414 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1415 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1417 static enum mstate mapstate
= MAP_UNDEFINED
;
1420 mapping_state (enum mstate state
)
1423 const char * symname
;
1426 if (mapstate
== state
)
1427 /* The mapping symbol has already been emitted.
1428 There is nothing else to do. */
1437 type
= BSF_NO_FLAGS
;
1441 type
= BSF_NO_FLAGS
;
1445 type
= BSF_NO_FLAGS
;
1453 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1455 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
1456 symbol_table_insert (symbolP
);
1457 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1462 THUMB_SET_FUNC (symbolP
, 0);
1463 ARM_SET_THUMB (symbolP
, 0);
1464 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1468 THUMB_SET_FUNC (symbolP
, 1);
1469 ARM_SET_THUMB (symbolP
, 1);
1470 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1479 #define mapping_state(x) /* nothing */
1482 /* Find the real, Thumb encoded start of a Thumb function. */
1485 find_real_start (symbolS
* symbolP
)
1488 const char * name
= S_GET_NAME (symbolP
);
1489 symbolS
* new_target
;
1491 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1492 #define STUB_NAME ".real_start_of"
1497 /* The compiler may generate BL instructions to local labels because
1498 it needs to perform a branch to a far away location. These labels
1499 do not have a corresponding ".real_start_of" label. We check
1500 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1501 the ".real_start_of" convention for nonlocal branches. */
1502 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
1505 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
1506 new_target
= symbol_find (real_start
);
1508 if (new_target
== NULL
)
1510 as_warn ("Failed to find real start of function: %s\n", name
);
1511 new_target
= symbolP
;
1518 opcode_select (int width
)
1525 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
1526 as_bad (_("selected processor does not support THUMB opcodes"));
1529 /* No need to force the alignment, since we will have been
1530 coming from ARM mode, which is word-aligned. */
1531 record_alignment (now_seg
, 1);
1533 mapping_state (MAP_THUMB
);
1539 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
1540 as_bad (_("selected processor does not support ARM opcodes"));
1545 frag_align (2, 0, 0);
1547 record_alignment (now_seg
, 1);
1549 mapping_state (MAP_ARM
);
1553 as_bad (_("invalid instruction size selected (%d)"), width
);
1558 s_arm (int ignore ATTRIBUTE_UNUSED
)
1561 demand_empty_rest_of_line ();
1565 s_thumb (int ignore ATTRIBUTE_UNUSED
)
1568 demand_empty_rest_of_line ();
1572 s_code (int unused ATTRIBUTE_UNUSED
)
1576 temp
= get_absolute_expression ();
1581 opcode_select (temp
);
1585 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
1590 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
1592 /* If we are not already in thumb mode go into it, EVEN if
1593 the target processor does not support thumb instructions.
1594 This is used by gcc/config/arm/lib1funcs.asm for example
1595 to compile interworking support functions even if the
1596 target processor should not support interworking. */
1600 record_alignment (now_seg
, 1);
1603 demand_empty_rest_of_line ();
1607 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
1611 /* The following label is the name/address of the start of a Thumb function.
1612 We need to know this for the interworking support. */
1613 label_is_thumb_function_name
= TRUE
;
1616 /* Perform a .set directive, but also mark the alias as
1617 being a thumb function. */
1620 s_thumb_set (int equiv
)
1622 /* XXX the following is a duplicate of the code for s_set() in read.c
1623 We cannot just call that code as we need to get at the symbol that
1630 /* Especial apologies for the random logic:
1631 This just grew, and could be parsed much more simply!
1633 name
= input_line_pointer
;
1634 delim
= get_symbol_end ();
1635 end_name
= input_line_pointer
;
1638 if (*input_line_pointer
!= ',')
1641 as_bad (_("expected comma after name \"%s\""), name
);
1643 ignore_rest_of_line ();
1647 input_line_pointer
++;
1650 if (name
[0] == '.' && name
[1] == '\0')
1652 /* XXX - this should not happen to .thumb_set. */
1656 if ((symbolP
= symbol_find (name
)) == NULL
1657 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
1660 /* When doing symbol listings, play games with dummy fragments living
1661 outside the normal fragment chain to record the file and line info
1663 if (listing
& LISTING_SYMBOLS
)
1665 extern struct list_info_struct
* listing_tail
;
1666 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
1668 memset (dummy_frag
, 0, sizeof (fragS
));
1669 dummy_frag
->fr_type
= rs_fill
;
1670 dummy_frag
->line
= listing_tail
;
1671 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
1672 dummy_frag
->fr_symbol
= symbolP
;
1676 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
1679 /* "set" symbols are local unless otherwise specified. */
1680 SF_SET_LOCAL (symbolP
);
1681 #endif /* OBJ_COFF */
1682 } /* Make a new symbol. */
1684 symbol_table_insert (symbolP
);
1689 && S_IS_DEFINED (symbolP
)
1690 && S_GET_SEGMENT (symbolP
) != reg_section
)
1691 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
1693 pseudo_set (symbolP
);
1695 demand_empty_rest_of_line ();
1697 /* XXX Now we come to the Thumb specific bit of code. */
1699 THUMB_SET_FUNC (symbolP
, 1);
1700 ARM_SET_THUMB (symbolP
, 1);
1701 #if defined OBJ_ELF || defined OBJ_COFF
1702 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1706 /* Directives: Mode selection. */
1708 /* .syntax [unified|divided] - choose the new unified syntax
1709 (same for Arm and Thumb encoding, modulo slight differences in what
1710 can be represented) or the old divergent syntax for each mode. */
1712 s_syntax (int unused ATTRIBUTE_UNUSED
)
1716 name
= input_line_pointer
;
1717 delim
= get_symbol_end ();
1719 if (!strcasecmp (name
, "unified"))
1720 unified_syntax
= TRUE
;
1721 else if (!strcasecmp (name
, "divided"))
1722 unified_syntax
= FALSE
;
1725 as_bad (_("unrecognized syntax mode \"%s\""), name
);
1728 *input_line_pointer
= delim
;
1729 demand_empty_rest_of_line ();
1732 /* Directives: sectioning and alignment. */
1734 /* Same as s_align_ptwo but align 0 => align 2. */
1737 s_align (int unused ATTRIBUTE_UNUSED
)
1741 long max_alignment
= 15;
1743 temp
= get_absolute_expression ();
1744 if (temp
> max_alignment
)
1745 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
1748 as_bad (_("alignment negative. 0 assumed."));
1752 if (*input_line_pointer
== ',')
1754 input_line_pointer
++;
1755 temp_fill
= get_absolute_expression ();
1763 /* Only make a frag if we HAVE to. */
1764 if (temp
&& !need_pass_2
)
1765 frag_align (temp
, (int) temp_fill
, 0);
1766 demand_empty_rest_of_line ();
1768 record_alignment (now_seg
, temp
);
1772 s_bss (int ignore ATTRIBUTE_UNUSED
)
1774 /* We don't support putting frags in the BSS segment, we fake it by
1775 marking in_bss, then looking at s_skip for clues. */
1776 subseg_set (bss_section
, 0);
1777 demand_empty_rest_of_line ();
1778 mapping_state (MAP_DATA
);
1782 s_even (int ignore ATTRIBUTE_UNUSED
)
1784 /* Never make frag if expect extra pass. */
1786 frag_align (1, 0, 0);
1788 record_alignment (now_seg
, 1);
1790 demand_empty_rest_of_line ();
1793 /* Directives: Literal pools. */
1795 static literal_pool
*
1796 find_literal_pool (void)
1798 literal_pool
* pool
;
1800 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1802 if (pool
->section
== now_seg
1803 && pool
->sub_section
== now_subseg
)
1810 static literal_pool
*
1811 find_or_make_literal_pool (void)
1813 /* Next literal pool ID number. */
1814 static unsigned int latest_pool_num
= 1;
1815 literal_pool
* pool
;
1817 pool
= find_literal_pool ();
1821 /* Create a new pool. */
1822 pool
= xmalloc (sizeof (* pool
));
1826 pool
->next_free_entry
= 0;
1827 pool
->section
= now_seg
;
1828 pool
->sub_section
= now_subseg
;
1829 pool
->next
= list_of_pools
;
1830 pool
->symbol
= NULL
;
1832 /* Add it to the list. */
1833 list_of_pools
= pool
;
1836 /* New pools, and emptied pools, will have a NULL symbol. */
1837 if (pool
->symbol
== NULL
)
1839 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1840 (valueT
) 0, &zero_address_frag
);
1841 pool
->id
= latest_pool_num
++;
1848 /* Add the literal in the global 'inst'
1849 structure to the relevent literal pool. */
1852 add_to_lit_pool (void)
1854 literal_pool
* pool
;
1857 pool
= find_or_make_literal_pool ();
1859 /* Check if this literal value is already in the pool. */
1860 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1862 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
1863 && (inst
.reloc
.exp
.X_op
== O_constant
)
1864 && (pool
->literals
[entry
].X_add_number
1865 == inst
.reloc
.exp
.X_add_number
)
1866 && (pool
->literals
[entry
].X_unsigned
1867 == inst
.reloc
.exp
.X_unsigned
))
1870 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
1871 && (inst
.reloc
.exp
.X_op
== O_symbol
)
1872 && (pool
->literals
[entry
].X_add_number
1873 == inst
.reloc
.exp
.X_add_number
)
1874 && (pool
->literals
[entry
].X_add_symbol
1875 == inst
.reloc
.exp
.X_add_symbol
)
1876 && (pool
->literals
[entry
].X_op_symbol
1877 == inst
.reloc
.exp
.X_op_symbol
))
1881 /* Do we need to create a new entry? */
1882 if (entry
== pool
->next_free_entry
)
1884 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1886 inst
.error
= _("literal pool overflow");
1890 pool
->literals
[entry
] = inst
.reloc
.exp
;
1891 pool
->next_free_entry
+= 1;
1894 inst
.reloc
.exp
.X_op
= O_symbol
;
1895 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
1896 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
1901 /* Can't use symbol_new here, so have to create a symbol and then at
1902 a later date assign it a value. Thats what these functions do. */
1905 symbol_locate (symbolS
* symbolP
,
1906 const char * name
, /* It is copied, the caller can modify. */
1907 segT segment
, /* Segment identifier (SEG_<something>). */
1908 valueT valu
, /* Symbol value. */
1909 fragS
* frag
) /* Associated fragment. */
1911 unsigned int name_length
;
1912 char * preserved_copy_of_name
;
1914 name_length
= strlen (name
) + 1; /* +1 for \0. */
1915 obstack_grow (¬es
, name
, name_length
);
1916 preserved_copy_of_name
= obstack_finish (¬es
);
1918 #ifdef tc_canonicalize_symbol_name
1919 preserved_copy_of_name
=
1920 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1923 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1925 S_SET_SEGMENT (symbolP
, segment
);
1926 S_SET_VALUE (symbolP
, valu
);
1927 symbol_clear_list_pointers (symbolP
);
1929 symbol_set_frag (symbolP
, frag
);
1931 /* Link to end of symbol chain. */
1933 extern int symbol_table_frozen
;
1935 if (symbol_table_frozen
)
1939 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
1941 obj_symbol_new_hook (symbolP
);
1943 #ifdef tc_symbol_new_hook
1944 tc_symbol_new_hook (symbolP
);
1948 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1949 #endif /* DEBUG_SYMS */
1954 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1957 literal_pool
* pool
;
1960 pool
= find_literal_pool ();
1962 || pool
->symbol
== NULL
1963 || pool
->next_free_entry
== 0)
1966 mapping_state (MAP_DATA
);
1968 /* Align pool as you have word accesses.
1969 Only make a frag if we have to. */
1971 frag_align (2, 0, 0);
1973 record_alignment (now_seg
, 2);
1975 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1977 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1978 (valueT
) frag_now_fix (), frag_now
);
1979 symbol_table_insert (pool
->symbol
);
1981 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
1983 #if defined OBJ_COFF || defined OBJ_ELF
1984 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
1987 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1988 /* First output the expression in the instruction to the pool. */
1989 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
1991 /* Mark the pool as empty. */
1992 pool
->next_free_entry
= 0;
1993 pool
->symbol
= NULL
;
1997 /* Forward declarations for functions below, in the MD interface
1999 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2000 static valueT
create_unwind_entry (int);
2001 static void start_unwind_section (const segT
, int);
2002 static void add_unwind_opcode (valueT
, int);
2003 static void flush_pending_unwind (void);
2005 /* Directives: Data. */
2008 s_arm_elf_cons (int nbytes
)
2012 #ifdef md_flush_pending_output
2013 md_flush_pending_output ();
2016 if (is_it_end_of_statement ())
2018 demand_empty_rest_of_line ();
2022 #ifdef md_cons_align
2023 md_cons_align (nbytes
);
2026 mapping_state (MAP_DATA
);
2030 char *base
= input_line_pointer
;
2034 if (exp
.X_op
!= O_symbol
)
2035 emit_expr (&exp
, (unsigned int) nbytes
);
2038 char *before_reloc
= input_line_pointer
;
2039 reloc
= parse_reloc (&input_line_pointer
);
2042 as_bad (_("unrecognized relocation suffix"));
2043 ignore_rest_of_line ();
2046 else if (reloc
== BFD_RELOC_UNUSED
)
2047 emit_expr (&exp
, (unsigned int) nbytes
);
2050 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2051 int size
= bfd_get_reloc_size (howto
);
2053 if (reloc
== BFD_RELOC_ARM_PLT32
)
2055 as_bad (_("(plt) is only valid on branch targets"));
2056 reloc
= BFD_RELOC_UNUSED
;
2061 as_bad (_("%s relocations do not fit in %d bytes"),
2062 howto
->name
, nbytes
);
2065 /* We've parsed an expression stopping at O_symbol.
2066 But there may be more expression left now that we
2067 have parsed the relocation marker. Parse it again.
2068 XXX Surely there is a cleaner way to do this. */
2069 char *p
= input_line_pointer
;
2071 char *save_buf
= alloca (input_line_pointer
- base
);
2072 memcpy (save_buf
, base
, input_line_pointer
- base
);
2073 memmove (base
+ (input_line_pointer
- before_reloc
),
2074 base
, before_reloc
- base
);
2076 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2078 memcpy (base
, save_buf
, p
- base
);
2080 offset
= nbytes
- size
;
2081 p
= frag_more ((int) nbytes
);
2082 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2083 size
, &exp
, 0, reloc
);
2088 while (*input_line_pointer
++ == ',');
2090 /* Put terminator back into stream. */
2091 input_line_pointer
--;
2092 demand_empty_rest_of_line ();
2096 /* Parse a .rel31 directive. */
2099 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2106 if (*input_line_pointer
== '1')
2107 highbit
= 0x80000000;
2108 else if (*input_line_pointer
!= '0')
2109 as_bad (_("expected 0 or 1"));
2111 input_line_pointer
++;
2112 if (*input_line_pointer
!= ',')
2113 as_bad (_("missing comma"));
2114 input_line_pointer
++;
2116 #ifdef md_flush_pending_output
2117 md_flush_pending_output ();
2120 #ifdef md_cons_align
2124 mapping_state (MAP_DATA
);
2129 md_number_to_chars (p
, highbit
, 4);
2130 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2131 BFD_RELOC_ARM_PREL31
);
2133 demand_empty_rest_of_line ();
2136 /* Directives: AEABI stack-unwind tables. */
2138 /* Parse an unwind_fnstart directive. Simply records the current location. */
2141 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
2143 demand_empty_rest_of_line ();
2144 /* Mark the start of the function. */
2145 unwind
.proc_start
= expr_build_dot ();
2147 /* Reset the rest of the unwind info. */
2148 unwind
.opcode_count
= 0;
2149 unwind
.table_entry
= NULL
;
2150 unwind
.personality_routine
= NULL
;
2151 unwind
.personality_index
= -1;
2152 unwind
.frame_size
= 0;
2153 unwind
.fp_offset
= 0;
2156 unwind
.sp_restored
= 0;
2160 /* Parse a handlerdata directive. Creates the exception handling table entry
2161 for the function. */
2164 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
2166 demand_empty_rest_of_line ();
2167 if (unwind
.table_entry
)
2168 as_bad (_("dupicate .handlerdata directive"));
2170 create_unwind_entry (1);
2173 /* Parse an unwind_fnend directive. Generates the index table entry. */
2176 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
2182 demand_empty_rest_of_line ();
2184 /* Add eh table entry. */
2185 if (unwind
.table_entry
== NULL
)
2186 val
= create_unwind_entry (0);
2190 /* Add index table entry. This is two words. */
2191 start_unwind_section (unwind
.saved_seg
, 1);
2192 frag_align (2, 0, 0);
2193 record_alignment (now_seg
, 2);
2195 ptr
= frag_more (8);
2196 where
= frag_now_fix () - 8;
2198 /* Self relative offset of the function start. */
2199 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
2200 BFD_RELOC_ARM_PREL31
);
2202 /* Indicate dependency on EHABI-defined personality routines to the
2203 linker, if it hasn't been done already. */
2204 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
2205 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
2207 static const char *const name
[] = {
2208 "__aeabi_unwind_cpp_pr0",
2209 "__aeabi_unwind_cpp_pr1",
2210 "__aeabi_unwind_cpp_pr2"
2212 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
2213 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
2214 marked_pr_dependency
|= 1 << unwind
.personality_index
;
2215 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
2216 = marked_pr_dependency
;
2220 /* Inline exception table entry. */
2221 md_number_to_chars (ptr
+ 4, val
, 4);
2223 /* Self relative offset of the table entry. */
2224 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
2225 BFD_RELOC_ARM_PREL31
);
2227 /* Restore the original section. */
2228 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
2232 /* Parse an unwind_cantunwind directive. */
2235 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
2237 demand_empty_rest_of_line ();
2238 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2239 as_bad (_("personality routine specified for cantunwind frame"));
2241 unwind
.personality_index
= -2;
2245 /* Parse a personalityindex directive. */
2248 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
2252 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2253 as_bad (_("duplicate .personalityindex directive"));
2257 if (exp
.X_op
!= O_constant
2258 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
2260 as_bad (_("bad personality routine number"));
2261 ignore_rest_of_line ();
2265 unwind
.personality_index
= exp
.X_add_number
;
2267 demand_empty_rest_of_line ();
2271 /* Parse a personality directive. */
2274 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
2278 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2279 as_bad (_("duplicate .personality directive"));
2281 name
= input_line_pointer
;
2282 c
= get_symbol_end ();
2283 p
= input_line_pointer
;
2284 unwind
.personality_routine
= symbol_find_or_make (name
);
2286 demand_empty_rest_of_line ();
2290 /* Parse a directive saving core registers. */
2293 s_arm_unwind_save_core (void)
2299 range
= parse_reg_list (&input_line_pointer
);
2302 as_bad (_("expected register list"));
2303 ignore_rest_of_line ();
2307 demand_empty_rest_of_line ();
2309 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2310 into .unwind_save {..., sp...}. We aren't bothered about the value of
2311 ip because it is clobbered by calls. */
2312 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
2313 && (range
& 0x3000) == 0x1000)
2315 unwind
.opcode_count
--;
2316 unwind
.sp_restored
= 0;
2317 range
= (range
| 0x2000) & ~0x1000;
2318 unwind
.pending_offset
= 0;
2324 /* See if we can use the short opcodes. These pop a block of up to 8
2325 registers starting with r4, plus maybe r14. */
2326 for (n
= 0; n
< 8; n
++)
2328 /* Break at the first non-saved register. */
2329 if ((range
& (1 << (n
+ 4))) == 0)
2332 /* See if there are any other bits set. */
2333 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
2335 /* Use the long form. */
2336 op
= 0x8000 | ((range
>> 4) & 0xfff);
2337 add_unwind_opcode (op
, 2);
2341 /* Use the short form. */
2343 op
= 0xa8; /* Pop r14. */
2345 op
= 0xa0; /* Do not pop r14. */
2347 add_unwind_opcode (op
, 1);
2354 op
= 0xb100 | (range
& 0xf);
2355 add_unwind_opcode (op
, 2);
2358 /* Record the number of bytes pushed. */
2359 for (n
= 0; n
< 16; n
++)
2361 if (range
& (1 << n
))
2362 unwind
.frame_size
+= 4;
2367 /* Parse a directive saving FPA registers. */
2370 s_arm_unwind_save_fpa (int reg
)
2376 /* Get Number of registers to transfer. */
2377 if (skip_past_comma (&input_line_pointer
) != FAIL
)
2380 exp
.X_op
= O_illegal
;
2382 if (exp
.X_op
!= O_constant
)
2384 as_bad (_("expected , <constant>"));
2385 ignore_rest_of_line ();
2389 num_regs
= exp
.X_add_number
;
2391 if (num_regs
< 1 || num_regs
> 4)
2393 as_bad (_("number of registers must be in the range [1:4]"));
2394 ignore_rest_of_line ();
2398 demand_empty_rest_of_line ();
2403 op
= 0xb4 | (num_regs
- 1);
2404 add_unwind_opcode (op
, 1);
2409 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
2410 add_unwind_opcode (op
, 2);
2412 unwind
.frame_size
+= num_regs
* 12;
2416 /* Parse a directive saving VFP registers. */
2419 s_arm_unwind_save_vfp (void)
2425 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, 1);
2428 as_bad (_("expected register list"));
2429 ignore_rest_of_line ();
2433 demand_empty_rest_of_line ();
2438 op
= 0xb8 | (count
- 1);
2439 add_unwind_opcode (op
, 1);
2444 op
= 0xb300 | (reg
<< 4) | (count
- 1);
2445 add_unwind_opcode (op
, 2);
2447 unwind
.frame_size
+= count
* 8 + 4;
2451 /* Parse a directive saving iWMMXt data registers. */
2454 s_arm_unwind_save_mmxwr (void)
2462 if (*input_line_pointer
== '{')
2463 input_line_pointer
++;
2467 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
2471 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
2476 as_tsktsk (_("register list not in ascending order"));
2479 if (*input_line_pointer
== '-')
2481 input_line_pointer
++;
2482 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
2485 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
2488 else if (reg
>= hi_reg
)
2490 as_bad (_("bad register range"));
2493 for (; reg
< hi_reg
; reg
++)
2497 while (skip_past_comma (&input_line_pointer
) != FAIL
);
2499 if (*input_line_pointer
== '}')
2500 input_line_pointer
++;
2502 demand_empty_rest_of_line ();
2504 /* Generate any deferred opcodes becuuse we're going to be looking at
2506 flush_pending_unwind ();
2508 for (i
= 0; i
< 16; i
++)
2510 if (mask
& (1 << i
))
2511 unwind
.frame_size
+= 8;
2514 /* Attempt to combine with a previous opcode. We do this because gcc
2515 likes to output separate unwind directives for a single block of
2517 if (unwind
.opcode_count
> 0)
2519 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
2520 if ((i
& 0xf8) == 0xc0)
2523 /* Only merge if the blocks are contiguous. */
2526 if ((mask
& 0xfe00) == (1 << 9))
2528 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
2529 unwind
.opcode_count
--;
2532 else if (i
== 6 && unwind
.opcode_count
>= 2)
2534 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
2538 op
= 0xffff << (reg
- 1);
2540 || ((mask
& op
) == (1u << (reg
- 1))))
2542 op
= (1 << (reg
+ i
+ 1)) - 1;
2543 op
&= ~((1 << reg
) - 1);
2545 unwind
.opcode_count
-= 2;
2552 /* We want to generate opcodes in the order the registers have been
2553 saved, ie. descending order. */
2554 for (reg
= 15; reg
>= -1; reg
--)
2556 /* Save registers in blocks. */
2558 || !(mask
& (1 << reg
)))
2560 /* We found an unsaved reg. Generate opcodes to save the
2561 preceeding block. */
2567 op
= 0xc0 | (hi_reg
- 10);
2568 add_unwind_opcode (op
, 1);
2573 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
2574 add_unwind_opcode (op
, 2);
2583 ignore_rest_of_line ();
2587 s_arm_unwind_save_mmxwcg (void)
2594 if (*input_line_pointer
== '{')
2595 input_line_pointer
++;
2599 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
2603 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
2609 as_tsktsk (_("register list not in ascending order"));
2612 if (*input_line_pointer
== '-')
2614 input_line_pointer
++;
2615 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
2618 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
2621 else if (reg
>= hi_reg
)
2623 as_bad (_("bad register range"));
2626 for (; reg
< hi_reg
; reg
++)
2630 while (skip_past_comma (&input_line_pointer
) != FAIL
);
2632 if (*input_line_pointer
== '}')
2633 input_line_pointer
++;
2635 demand_empty_rest_of_line ();
2637 /* Generate any deferred opcodes becuuse we're going to be looking at
2639 flush_pending_unwind ();
2641 for (reg
= 0; reg
< 16; reg
++)
2643 if (mask
& (1 << reg
))
2644 unwind
.frame_size
+= 4;
2647 add_unwind_opcode (op
, 2);
2650 ignore_rest_of_line ();
2654 /* Parse an unwind_save directive. */
2657 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED
)
2660 struct reg_entry
*reg
;
2661 bfd_boolean had_brace
= FALSE
;
2663 /* Figure out what sort of save we have. */
2664 peek
= input_line_pointer
;
2672 reg
= arm_reg_parse_multi (&peek
);
2676 as_bad (_("register expected"));
2677 ignore_rest_of_line ();
2686 as_bad (_("FPA .unwind_save does not take a register list"));
2687 ignore_rest_of_line ();
2690 s_arm_unwind_save_fpa (reg
->number
);
2693 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
2694 case REG_TYPE_VFD
: s_arm_unwind_save_vfp (); return;
2695 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
2696 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
2699 as_bad (_(".unwind_save does not support this kind of register"));
2700 ignore_rest_of_line ();
2705 /* Parse an unwind_movsp directive. */
2708 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
2713 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2716 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
2717 ignore_rest_of_line ();
2720 demand_empty_rest_of_line ();
2722 if (reg
== REG_SP
|| reg
== REG_PC
)
2724 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2728 if (unwind
.fp_reg
!= REG_SP
)
2729 as_bad (_("unexpected .unwind_movsp directive"));
2731 /* Generate opcode to restore the value. */
2733 add_unwind_opcode (op
, 1);
2735 /* Record the information for later. */
2736 unwind
.fp_reg
= reg
;
2737 unwind
.fp_offset
= unwind
.frame_size
;
2738 unwind
.sp_restored
= 1;
2741 /* Parse an unwind_pad directive. */
2744 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
2748 if (immediate_for_directive (&offset
) == FAIL
)
2753 as_bad (_("stack increment must be multiple of 4"));
2754 ignore_rest_of_line ();
2758 /* Don't generate any opcodes, just record the details for later. */
2759 unwind
.frame_size
+= offset
;
2760 unwind
.pending_offset
+= offset
;
2762 demand_empty_rest_of_line ();
2765 /* Parse an unwind_setfp directive. */
2768 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
2774 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2775 if (skip_past_comma (&input_line_pointer
) == FAIL
)
2778 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2780 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
2782 as_bad (_("expected <reg>, <reg>"));
2783 ignore_rest_of_line ();
2787 /* Optional constant. */
2788 if (skip_past_comma (&input_line_pointer
) != FAIL
)
2790 if (immediate_for_directive (&offset
) == FAIL
)
2796 demand_empty_rest_of_line ();
2798 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
2800 as_bad (_("register must be either sp or set by a previous"
2801 "unwind_movsp directive"));
2805 /* Don't generate any opcodes, just record the information for later. */
2806 unwind
.fp_reg
= fp_reg
;
2809 unwind
.fp_offset
= unwind
.frame_size
- offset
;
2811 unwind
.fp_offset
-= offset
;
2814 /* Parse an unwind_raw directive. */
2817 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
2820 /* This is an arbitary limit. */
2821 unsigned char op
[16];
2825 if (exp
.X_op
== O_constant
2826 && skip_past_comma (&input_line_pointer
) != FAIL
)
2828 unwind
.frame_size
+= exp
.X_add_number
;
2832 exp
.X_op
= O_illegal
;
2834 if (exp
.X_op
!= O_constant
)
2836 as_bad (_("expected <offset>, <opcode>"));
2837 ignore_rest_of_line ();
2843 /* Parse the opcode. */
2848 as_bad (_("unwind opcode too long"));
2849 ignore_rest_of_line ();
2851 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
2853 as_bad (_("invalid unwind opcode"));
2854 ignore_rest_of_line ();
2857 op
[count
++] = exp
.X_add_number
;
2859 /* Parse the next byte. */
2860 if (skip_past_comma (&input_line_pointer
) == FAIL
)
2866 /* Add the opcode bytes in reverse order. */
2868 add_unwind_opcode (op
[count
], 1);
2870 demand_empty_rest_of_line ();
2874 /* Parse a .eabi_attribute directive. */
2877 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
2880 bfd_boolean is_string
;
2887 if (exp
.X_op
!= O_constant
)
2890 tag
= exp
.X_add_number
;
2891 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
2896 if (skip_past_comma (&input_line_pointer
) == FAIL
)
2898 if (tag
== 32 || !is_string
)
2901 if (exp
.X_op
!= O_constant
)
2903 as_bad (_("expected numeric constant"));
2904 ignore_rest_of_line ();
2907 i
= exp
.X_add_number
;
2909 if (tag
== Tag_compatibility
2910 && skip_past_comma (&input_line_pointer
) == FAIL
)
2912 as_bad (_("expected comma"));
2913 ignore_rest_of_line ();
2918 skip_whitespace(input_line_pointer
);
2919 if (*input_line_pointer
!= '"')
2921 input_line_pointer
++;
2922 s
= input_line_pointer
;
2923 while (*input_line_pointer
&& *input_line_pointer
!= '"')
2924 input_line_pointer
++;
2925 if (*input_line_pointer
!= '"')
2927 saved_char
= *input_line_pointer
;
2928 *input_line_pointer
= 0;
2936 if (tag
== Tag_compatibility
)
2937 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
2939 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
2941 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
2945 *input_line_pointer
= saved_char
;
2946 input_line_pointer
++;
2948 demand_empty_rest_of_line ();
2951 as_bad (_("bad string constant"));
2952 ignore_rest_of_line ();
2955 as_bad (_("expected <tag> , <value>"));
2956 ignore_rest_of_line ();
2959 static void s_arm_arch (int);
2960 static void s_arm_cpu (int);
2961 static void s_arm_fpu (int);
2962 #endif /* OBJ_ELF */
2964 /* This table describes all the machine specific pseudo-ops the assembler
2965 has to support. The fields are:
2966 pseudo-op name without dot
2967 function to call to execute this pseudo-op
2968 Integer arg to pass to the function. */
2970 const pseudo_typeS md_pseudo_table
[] =
2972 /* Never called because '.req' does not start a line. */
2973 { "req", s_req
, 0 },
2974 { "unreq", s_unreq
, 0 },
2975 { "bss", s_bss
, 0 },
2976 { "align", s_align
, 0 },
2977 { "arm", s_arm
, 0 },
2978 { "thumb", s_thumb
, 0 },
2979 { "code", s_code
, 0 },
2980 { "force_thumb", s_force_thumb
, 0 },
2981 { "thumb_func", s_thumb_func
, 0 },
2982 { "thumb_set", s_thumb_set
, 0 },
2983 { "even", s_even
, 0 },
2984 { "ltorg", s_ltorg
, 0 },
2985 { "pool", s_ltorg
, 0 },
2986 { "syntax", s_syntax
, 0 },
2988 { "word", s_arm_elf_cons
, 4 },
2989 { "long", s_arm_elf_cons
, 4 },
2990 { "rel31", s_arm_rel31
, 0 },
2991 { "fnstart", s_arm_unwind_fnstart
, 0 },
2992 { "fnend", s_arm_unwind_fnend
, 0 },
2993 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
2994 { "personality", s_arm_unwind_personality
, 0 },
2995 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
2996 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
2997 { "save", s_arm_unwind_save
, 0 },
2998 { "movsp", s_arm_unwind_movsp
, 0 },
2999 { "pad", s_arm_unwind_pad
, 0 },
3000 { "setfp", s_arm_unwind_setfp
, 0 },
3001 { "unwind_raw", s_arm_unwind_raw
, 0 },
3002 { "cpu", s_arm_cpu
, 0 },
3003 { "arch", s_arm_arch
, 0 },
3004 { "fpu", s_arm_fpu
, 0 },
3005 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3009 { "extend", float_cons
, 'x' },
3010 { "ldouble", float_cons
, 'x' },
3011 { "packed", float_cons
, 'p' },
3015 /* Parser functions used exclusively in instruction operands. */
3017 /* Generic immediate-value read function for use in insn parsing.
3018 STR points to the beginning of the immediate (the leading #);
3019 VAL receives the value; if the value is outside [MIN, MAX]
3020 issue an error. PREFIX_OPT is true if the immediate prefix is
3024 parse_immediate (char **str
, int *val
, int min
, int max
,
3025 bfd_boolean prefix_opt
)
3028 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3029 if (exp
.X_op
!= O_constant
)
3031 inst
.error
= _("constant expression required");
3035 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
3037 inst
.error
= _("immediate value out of range");
3041 *val
= exp
.X_add_number
;
3045 /* Returns the pseudo-register number of an FPA immediate constant,
3046 or FAIL if there isn't a valid constant here. */
3049 parse_fpa_immediate (char ** str
)
3051 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3057 /* First try and match exact strings, this is to guarantee
3058 that some formats will work even for cross assembly. */
3060 for (i
= 0; fp_const
[i
]; i
++)
3062 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
3066 *str
+= strlen (fp_const
[i
]);
3067 if (is_end_of_line
[(unsigned char) **str
])
3073 /* Just because we didn't get a match doesn't mean that the constant
3074 isn't valid, just that it is in a format that we don't
3075 automatically recognize. Try parsing it with the standard
3076 expression routines. */
3078 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
3080 /* Look for a raw floating point number. */
3081 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
3082 && is_end_of_line
[(unsigned char) *save_in
])
3084 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
3086 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
3088 if (words
[j
] != fp_values
[i
][j
])
3092 if (j
== MAX_LITTLENUMS
)
3100 /* Try and parse a more complex expression, this will probably fail
3101 unless the code uses a floating point prefix (eg "0f"). */
3102 save_in
= input_line_pointer
;
3103 input_line_pointer
= *str
;
3104 if (expression (&exp
) == absolute_section
3105 && exp
.X_op
== O_big
3106 && exp
.X_add_number
< 0)
3108 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3110 if (gen_to_words (words
, 5, (long) 15) == 0)
3112 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
3114 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
3116 if (words
[j
] != fp_values
[i
][j
])
3120 if (j
== MAX_LITTLENUMS
)
3122 *str
= input_line_pointer
;
3123 input_line_pointer
= save_in
;
3130 *str
= input_line_pointer
;
3131 input_line_pointer
= save_in
;
3132 inst
.error
= _("invalid FPA immediate expression");
3136 /* Shift operands. */
3139 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
3142 struct asm_shift_name
3145 enum shift_kind kind
;
3148 /* Third argument to parse_shift. */
3149 enum parse_shift_mode
3151 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
3152 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
3153 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
3154 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
3155 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
3158 /* Parse a <shift> specifier on an ARM data processing instruction.
3159 This has three forms:
3161 (LSL|LSR|ASL|ASR|ROR) Rs
3162 (LSL|LSR|ASL|ASR|ROR) #imm
3165 Note that ASL is assimilated to LSL in the instruction encoding, and
3166 RRX to ROR #0 (which cannot be written as such). */
3169 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
3171 const struct asm_shift_name
*shift_name
;
3172 enum shift_kind shift
;
3177 for (p
= *str
; ISALPHA (*p
); p
++)
3182 inst
.error
= _("shift expression expected");
3186 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
3188 if (shift_name
== NULL
)
3190 inst
.error
= _("shift expression expected");
3194 shift
= shift_name
->kind
;
3198 case NO_SHIFT_RESTRICT
:
3199 case SHIFT_IMMEDIATE
: break;
3201 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
3202 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
3204 inst
.error
= _("'LSL' or 'ASR' required");
3209 case SHIFT_LSL_IMMEDIATE
:
3210 if (shift
!= SHIFT_LSL
)
3212 inst
.error
= _("'LSL' required");
3217 case SHIFT_ASR_IMMEDIATE
:
3218 if (shift
!= SHIFT_ASR
)
3220 inst
.error
= _("'ASR' required");
3228 if (shift
!= SHIFT_RRX
)
3230 /* Whitespace can appear here if the next thing is a bare digit. */
3231 skip_whitespace (p
);
3233 if (mode
== NO_SHIFT_RESTRICT
3234 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3236 inst
.operands
[i
].imm
= reg
;
3237 inst
.operands
[i
].immisreg
= 1;
3239 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3242 inst
.operands
[i
].shift_kind
= shift
;
3243 inst
.operands
[i
].shifted
= 1;
3248 /* Parse a <shifter_operand> for an ARM data processing instruction:
3251 #<immediate>, <rotate>
3255 where <shift> is defined by parse_shift above, and <rotate> is a
3256 multiple of 2 between 0 and 30. Validation of immediate operands
3257 is deferred to md_apply_fix. */
3260 parse_shifter_operand (char **str
, int i
)
3265 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
3267 inst
.operands
[i
].reg
= value
;
3268 inst
.operands
[i
].isreg
= 1;
3270 /* parse_shift will override this if appropriate */
3271 inst
.reloc
.exp
.X_op
= O_constant
;
3272 inst
.reloc
.exp
.X_add_number
= 0;
3274 if (skip_past_comma (str
) == FAIL
)
3277 /* Shift operation on register. */
3278 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
3281 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
3284 if (skip_past_comma (str
) == SUCCESS
)
3286 /* #x, y -- ie explicit rotation by Y. */
3287 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
3290 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
3292 inst
.error
= _("constant expression expected");
3296 value
= expr
.X_add_number
;
3297 if (value
< 0 || value
> 30 || value
% 2 != 0)
3299 inst
.error
= _("invalid rotation");
3302 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
3304 inst
.error
= _("invalid constant");
3308 /* Convert to decoded value. md_apply_fix will put it back. */
3309 inst
.reloc
.exp
.X_add_number
3310 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
3311 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
3314 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
3315 inst
.reloc
.pc_rel
= 0;
3319 /* Parse all forms of an ARM address expression. Information is written
3320 to inst.operands[i] and/or inst.reloc.
3322 Preindexed addressing (.preind=1):
3324 [Rn, #offset] .reg=Rn .reloc.exp=offset
3325 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3326 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3327 .shift_kind=shift .reloc.exp=shift_imm
3329 These three may have a trailing ! which causes .writeback to be set also.
3331 Postindexed addressing (.postind=1, .writeback=1):
3333 [Rn], #offset .reg=Rn .reloc.exp=offset
3334 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3335 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3336 .shift_kind=shift .reloc.exp=shift_imm
3338 Unindexed addressing (.preind=0, .postind=0):
3340 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3344 [Rn]{!} shorthand for [Rn,#0]{!}
3345 =immediate .isreg=0 .reloc.exp=immediate
3346 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3348 It is the caller's responsibility to check for addressing modes not
3349 supported by the instruction, and to set inst.reloc.type. */
3352 parse_address (char **str
, int i
)
3357 if (skip_past_char (&p
, '[') == FAIL
)
3359 if (skip_past_char (&p
, '=') == FAIL
)
3361 /* bare address - translate to PC-relative offset */
3362 inst
.reloc
.pc_rel
= 1;
3363 inst
.operands
[i
].reg
= REG_PC
;
3364 inst
.operands
[i
].isreg
= 1;
3365 inst
.operands
[i
].preind
= 1;
3367 /* else a load-constant pseudo op, no special treatment needed here */
3369 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
3376 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
3378 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
3381 inst
.operands
[i
].reg
= reg
;
3382 inst
.operands
[i
].isreg
= 1;
3384 if (skip_past_comma (&p
) == SUCCESS
)
3386 inst
.operands
[i
].preind
= 1;
3389 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
3391 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3393 inst
.operands
[i
].imm
= reg
;
3394 inst
.operands
[i
].immisreg
= 1;
3396 if (skip_past_comma (&p
) == SUCCESS
)
3397 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
3402 if (inst
.operands
[i
].negative
)
3404 inst
.operands
[i
].negative
= 0;
3407 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3412 if (skip_past_char (&p
, ']') == FAIL
)
3414 inst
.error
= _("']' expected");
3418 if (skip_past_char (&p
, '!') == SUCCESS
)
3419 inst
.operands
[i
].writeback
= 1;
3421 else if (skip_past_comma (&p
) == SUCCESS
)
3423 if (skip_past_char (&p
, '{') == SUCCESS
)
3425 /* [Rn], {expr} - unindexed, with option */
3426 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
3427 0, 255, TRUE
) == FAIL
)
3430 if (skip_past_char (&p
, '}') == FAIL
)
3432 inst
.error
= _("'}' expected at end of 'option' field");
3435 if (inst
.operands
[i
].preind
)
3437 inst
.error
= _("cannot combine index with option");
3445 inst
.operands
[i
].postind
= 1;
3446 inst
.operands
[i
].writeback
= 1;
3448 if (inst
.operands
[i
].preind
)
3450 inst
.error
= _("cannot combine pre- and post-indexing");
3455 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
3457 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3459 inst
.operands
[i
].imm
= reg
;
3460 inst
.operands
[i
].immisreg
= 1;
3462 if (skip_past_comma (&p
) == SUCCESS
)
3463 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
3468 if (inst
.operands
[i
].negative
)
3470 inst
.operands
[i
].negative
= 0;
3473 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3479 /* If at this point neither .preind nor .postind is set, we have a
3480 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3481 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
3483 inst
.operands
[i
].preind
= 1;
3484 inst
.reloc
.exp
.X_op
= O_constant
;
3485 inst
.reloc
.exp
.X_add_number
= 0;
3491 /* Miscellaneous. */
3493 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3494 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3496 parse_psr (char **str
)
3499 unsigned long psr_field
;
3500 const struct asm_psr
*psr
;
3503 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3504 feature for ease of use and backwards compatibility. */
3506 if (strncasecmp (p
, "SPSR", 4) == 0)
3507 psr_field
= SPSR_BIT
;
3508 else if (strncasecmp (p
, "CPSR", 4) == 0)
3515 while (ISALNUM (*p
) || *p
== '_');
3517 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
3528 /* A suffix follows. */
3534 while (ISALNUM (*p
) || *p
== '_');
3536 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
3540 psr_field
|= psr
->field
;
3545 goto error
; /* Garbage after "[CS]PSR". */
3547 psr_field
|= (PSR_c
| PSR_f
);
3553 inst
.error
= _("flag for {c}psr instruction expected");
3557 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3558 value suitable for splatting into the AIF field of the instruction. */
3561 parse_cps_flags (char **str
)
3570 case '\0': case ',':
3573 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
3574 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
3575 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
3578 inst
.error
= _("unrecognized CPS flag");
3583 if (saw_a_flag
== 0)
3585 inst
.error
= _("missing CPS flags");
3593 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3594 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3597 parse_endian_specifier (char **str
)
3602 if (strncasecmp (s
, "BE", 2))
3604 else if (strncasecmp (s
, "LE", 2))
3608 inst
.error
= _("valid endian specifiers are be or le");
3612 if (ISALNUM (s
[2]) || s
[2] == '_')
3614 inst
.error
= _("valid endian specifiers are be or le");
3619 return little_endian
;
3622 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3623 value suitable for poking into the rotate field of an sxt or sxta
3624 instruction, or FAIL on error. */
3627 parse_ror (char **str
)
3632 if (strncasecmp (s
, "ROR", 3) == 0)
3636 inst
.error
= _("missing rotation field after comma");
3640 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
3645 case 0: *str
= s
; return 0x0;
3646 case 8: *str
= s
; return 0x1;
3647 case 16: *str
= s
; return 0x2;
3648 case 24: *str
= s
; return 0x3;
3651 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
3656 /* Parse a conditional code (from conds[] below). The value returned is in the
3657 range 0 .. 14, or FAIL. */
3659 parse_cond (char **str
)
3662 const struct asm_cond
*c
;
3665 while (ISALPHA (*q
))
3668 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
3671 inst
.error
= _("condition required");
3679 /* Parse an option for a barrier instruction. Returns the encoding for the
3682 parse_barrier (char **str
)
3685 const struct asm_barrier_opt
*o
;
3688 while (ISALPHA (*q
))
3691 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
3699 /* Parse the operands of a table branch instruction. Similar to a memory
3702 parse_tb (char **str
)
3707 if (skip_past_char (&p
, '[') == FAIL
)
3710 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
3712 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
3715 inst
.operands
[0].reg
= reg
;
3717 if (skip_past_comma (&p
) == FAIL
)
3720 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
3722 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
3725 inst
.operands
[0].imm
= reg
;
3727 if (skip_past_comma (&p
) == SUCCESS
)
3729 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
3731 if (inst
.reloc
.exp
.X_add_number
!= 1)
3733 inst
.error
= _("invalid shift");
3736 inst
.operands
[0].shifted
= 1;
3739 if (skip_past_char (&p
, ']') == FAIL
)
3741 inst
.error
= _("']' expected");
3748 /* Matcher codes for parse_operands. */
3749 enum operand_parse_code
3751 OP_stop
, /* end of line */
3753 OP_RR
, /* ARM register */
3754 OP_RRnpc
, /* ARM register, not r15 */
3755 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
3756 OP_RRw
, /* ARM register, not r15, optional trailing ! */
3757 OP_RCP
, /* Coprocessor number */
3758 OP_RCN
, /* Coprocessor register */
3759 OP_RF
, /* FPA register */
3760 OP_RVS
, /* VFP single precision register */
3761 OP_RVD
, /* VFP double precision register */
3762 OP_RVC
, /* VFP control register */
3763 OP_RMF
, /* Maverick F register */
3764 OP_RMD
, /* Maverick D register */
3765 OP_RMFX
, /* Maverick FX register */
3766 OP_RMDX
, /* Maverick DX register */
3767 OP_RMAX
, /* Maverick AX register */
3768 OP_RMDS
, /* Maverick DSPSC register */
3769 OP_RIWR
, /* iWMMXt wR register */
3770 OP_RIWC
, /* iWMMXt wC register */
3771 OP_RIWG
, /* iWMMXt wCG register */
3772 OP_RXA
, /* XScale accumulator register */
3774 OP_REGLST
, /* ARM register list */
3775 OP_VRSLST
, /* VFP single-precision register list */
3776 OP_VRDLST
, /* VFP double-precision register list */
3778 OP_I7
, /* immediate value 0 .. 7 */
3779 OP_I15
, /* 0 .. 15 */
3780 OP_I16
, /* 1 .. 16 */
3781 OP_I31
, /* 0 .. 31 */
3782 OP_I31w
, /* 0 .. 31, optional trailing ! */
3783 OP_I32
, /* 1 .. 32 */
3784 OP_I63s
, /* -64 .. 63 */
3785 OP_I255
, /* 0 .. 255 */
3786 OP_Iffff
, /* 0 .. 65535 */
3788 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
3789 OP_I7b
, /* 0 .. 7 */
3790 OP_I15b
, /* 0 .. 15 */
3791 OP_I31b
, /* 0 .. 31 */
3793 OP_SH
, /* shifter operand */
3794 OP_ADDR
, /* Memory address expression (any mode) */
3795 OP_EXP
, /* arbitrary expression */
3796 OP_EXPi
, /* same, with optional immediate prefix */
3797 OP_EXPr
, /* same, with optional relocation suffix */
3799 OP_CPSF
, /* CPS flags */
3800 OP_ENDI
, /* Endianness specifier */
3801 OP_PSR
, /* CPSR/SPSR mask for msr */
3802 OP_COND
, /* conditional code */
3803 OP_TB
, /* Table branch. */
3805 OP_RRnpc_I0
, /* ARM register or literal 0 */
3806 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
3807 OP_RR_EXi
, /* ARM register or expression with imm prefix */
3808 OP_RF_IF
, /* FPA register or immediate */
3809 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
3811 /* Optional operands. */
3812 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
3813 OP_oI31b
, /* 0 .. 31 */
3814 OP_oIffffb
, /* 0 .. 65535 */
3815 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
3817 OP_oRR
, /* ARM register */
3818 OP_oRRnpc
, /* ARM register, not the PC */
3819 OP_oSHll
, /* LSL immediate */
3820 OP_oSHar
, /* ASR immediate */
3821 OP_oSHllar
, /* LSL or ASR immediate */
3822 OP_oROR
, /* ROR 0/8/16/24 */
3823 OP_oBARRIER
, /* Option argument for a barrier instruction. */
3825 OP_FIRST_OPTIONAL
= OP_oI7b
3828 /* Generic instruction operand parser. This does no encoding and no
3829 semantic validation; it merely squirrels values away in the inst
3830 structure. Returns SUCCESS or FAIL depending on whether the
3831 specified grammar matched. */
3833 parse_operands (char *str
, const unsigned char *pattern
)
3835 unsigned const char *upat
= pattern
;
3836 char *backtrack_pos
= 0;
3837 const char *backtrack_error
= 0;
3838 int i
, val
, backtrack_index
= 0;
3840 #define po_char_or_fail(chr) do { \
3841 if (skip_past_char (&str, chr) == FAIL) \
3845 #define po_reg_or_fail(regtype) do { \
3846 val = arm_reg_parse (&str, regtype); \
3849 inst.error = _(reg_expected_msgs[regtype]); \
3852 inst.operands[i].reg = val; \
3853 inst.operands[i].isreg = 1; \
3856 #define po_reg_or_goto(regtype, label) do { \
3857 val = arm_reg_parse (&str, regtype); \
3861 inst.operands[i].reg = val; \
3862 inst.operands[i].isreg = 1; \
3865 #define po_imm_or_fail(min, max, popt) do { \
3866 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3868 inst.operands[i].imm = val; \
3871 #define po_misc_or_fail(expr) do { \
3876 skip_whitespace (str
);
3878 for (i
= 0; upat
[i
] != OP_stop
; i
++)
3880 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
3882 /* Remember where we are in case we need to backtrack. */
3883 assert (!backtrack_pos
);
3884 backtrack_pos
= str
;
3885 backtrack_error
= inst
.error
;
3886 backtrack_index
= i
;
3890 po_char_or_fail (',');
3898 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
3899 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
3900 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
3901 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
3902 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
3903 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
3904 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
3905 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
3906 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
3907 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
3908 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
3909 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
3910 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
3911 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
3912 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
3913 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
3914 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
3917 po_char_or_fail ('[');
3918 po_reg_or_fail (REG_TYPE_RN
);
3919 po_char_or_fail (']');
3923 po_reg_or_fail (REG_TYPE_RN
);
3924 if (skip_past_char (&str
, '!') == SUCCESS
)
3925 inst
.operands
[i
].writeback
= 1;
3929 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
3930 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
3931 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
3932 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
3933 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
3934 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
3935 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
3936 case OP_Iffff
: po_imm_or_fail ( 0, 0xffff, FALSE
); break;
3938 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
3940 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
3941 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
3943 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
3944 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
3946 /* Immediate variants */
3948 po_char_or_fail ('{');
3949 po_imm_or_fail (0, 255, TRUE
);
3950 po_char_or_fail ('}');
3954 /* The expression parser chokes on a trailing !, so we have
3955 to find it first and zap it. */
3958 while (*s
&& *s
!= ',')
3963 inst
.operands
[i
].writeback
= 1;
3965 po_imm_or_fail (0, 31, TRUE
);
3973 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3978 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3983 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3985 if (inst
.reloc
.exp
.X_op
== O_symbol
)
3987 val
= parse_reloc (&str
);
3990 inst
.error
= _("unrecognized relocation suffix");
3993 else if (val
!= BFD_RELOC_UNUSED
)
3995 inst
.operands
[i
].imm
= val
;
3996 inst
.operands
[i
].hasreloc
= 1;
4001 /* Register or expression */
4002 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
4003 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
4005 /* Register or immediate */
4006 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
4007 I0
: po_imm_or_fail (0, 0, FALSE
); break;
4009 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
4011 if (!is_immediate_prefix (*str
))
4014 val
= parse_fpa_immediate (&str
);
4017 /* FPA immediates are encoded as registers 8-15.
4018 parse_fpa_immediate has already applied the offset. */
4019 inst
.operands
[i
].reg
= val
;
4020 inst
.operands
[i
].isreg
= 1;
4023 /* Two kinds of register */
4026 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
4027 if (rege
->type
!= REG_TYPE_MMXWR
4028 && rege
->type
!= REG_TYPE_MMXWC
4029 && rege
->type
!= REG_TYPE_MMXWCG
)
4031 inst
.error
= _("iWMMXt data or control register expected");
4034 inst
.operands
[i
].reg
= rege
->number
;
4035 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
4040 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
4041 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
4042 case OP_oROR
: val
= parse_ror (&str
); break;
4043 case OP_PSR
: val
= parse_psr (&str
); break;
4044 case OP_COND
: val
= parse_cond (&str
); break;
4045 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
4048 po_misc_or_fail (parse_tb (&str
));
4051 /* Register lists */
4053 val
= parse_reg_list (&str
);
4056 inst
.operands
[1].writeback
= 1;
4062 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, 0);
4066 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, 1);
4069 /* Addressing modes */
4071 po_misc_or_fail (parse_address (&str
, i
));
4075 po_misc_or_fail (parse_shifter_operand (&str
, i
));
4079 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
4083 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
4087 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
4091 as_fatal ("unhandled operand code %d", upat
[i
]);
4094 /* Various value-based sanity checks and shared operations. We
4095 do not signal immediate failures for the register constraints;
4096 this allows a syntax error to take precedence. */
4104 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
4105 inst
.error
= BAD_PC
;
4119 inst
.operands
[i
].imm
= val
;
4126 /* If we get here, this operand was successfully parsed. */
4127 inst
.operands
[i
].present
= 1;
4131 inst
.error
= BAD_ARGS
;
4137 /* Do not backtrack over a trailing optional argument that
4138 absorbed some text. We will only fail again, with the
4139 'garbage following instruction' error message, which is
4140 probably less helpful than the current one. */
4141 if (backtrack_index
== i
&& backtrack_pos
!= str
4142 && upat
[i
+1] == OP_stop
)
4145 /* Try again, skipping the optional argument at backtrack_pos. */
4146 str
= backtrack_pos
;
4147 inst
.error
= backtrack_error
;
4148 inst
.operands
[backtrack_index
].present
= 0;
4149 i
= backtrack_index
;
4153 /* Check that we have parsed all the arguments. */
4154 if (*str
!= '\0' && !inst
.error
)
4155 inst
.error
= _("garbage following instruction");
4157 return inst
.error
? FAIL
: SUCCESS
;
4160 #undef po_char_or_fail
4161 #undef po_reg_or_fail
4162 #undef po_reg_or_goto
4163 #undef po_imm_or_fail
4165 /* Shorthand macro for instruction encoding functions issuing errors. */
4166 #define constraint(expr, err) do { \
4174 /* Functions for operand encoding. ARM, then Thumb. */
4176 #define rotate_left(v, n) (v << n | v >> (32 - n))
4178 /* If VAL can be encoded in the immediate field of an ARM instruction,
4179 return the encoded form. Otherwise, return FAIL. */
4182 encode_arm_immediate (unsigned int val
)
4186 for (i
= 0; i
< 32; i
+= 2)
4187 if ((a
= rotate_left (val
, i
)) <= 0xff)
4188 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
4193 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
4194 return the encoded form. Otherwise, return FAIL. */
4196 encode_thumb32_immediate (unsigned int val
)
4203 for (i
= 1; i
<= 24; i
++)
4206 if ((val
& ~(0xff << i
)) == 0)
4207 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
4211 if (val
== ((a
<< 16) | a
))
4213 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
4217 if (val
== ((a
<< 16) | a
))
4218 return 0x200 | (a
>> 8);
4222 /* Encode a VFP SP register number into inst.instruction. */
4225 encode_arm_vfp_sp_reg (int reg
, enum vfp_sp_reg_pos pos
)
4230 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
4234 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
4238 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
4246 /* Encode a <shift> in an ARM-format instruction. The immediate,
4247 if any, is handled by md_apply_fix. */
4249 encode_arm_shift (int i
)
4251 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
4252 inst
.instruction
|= SHIFT_ROR
<< 5;
4255 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
4256 if (inst
.operands
[i
].immisreg
)
4258 inst
.instruction
|= SHIFT_BY_REG
;
4259 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
4262 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
4267 encode_arm_shifter_operand (int i
)
4269 if (inst
.operands
[i
].isreg
)
4271 inst
.instruction
|= inst
.operands
[i
].reg
;
4272 encode_arm_shift (i
);
4275 inst
.instruction
|= INST_IMMEDIATE
;
4278 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4280 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
4282 assert (inst
.operands
[i
].isreg
);
4283 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
4285 if (inst
.operands
[i
].preind
)
4289 inst
.error
= _("instruction does not accept preindexed addressing");
4292 inst
.instruction
|= PRE_INDEX
;
4293 if (inst
.operands
[i
].writeback
)
4294 inst
.instruction
|= WRITE_BACK
;
4297 else if (inst
.operands
[i
].postind
)
4299 assert (inst
.operands
[i
].writeback
);
4301 inst
.instruction
|= WRITE_BACK
;
4303 else /* unindexed - only for coprocessor */
4305 inst
.error
= _("instruction does not accept unindexed addressing");
4309 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
4310 && (((inst
.instruction
& 0x000f0000) >> 16)
4311 == ((inst
.instruction
& 0x0000f000) >> 12)))
4312 as_warn ((inst
.instruction
& LOAD_BIT
)
4313 ? _("destination register same as write-back base")
4314 : _("source register same as write-back base"));
4317 /* inst.operands[i] was set up by parse_address. Encode it into an
4318 ARM-format mode 2 load or store instruction. If is_t is true,
4319 reject forms that cannot be used with a T instruction (i.e. not
4322 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
4324 encode_arm_addr_mode_common (i
, is_t
);
4326 if (inst
.operands
[i
].immisreg
)
4328 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
4329 inst
.instruction
|= inst
.operands
[i
].imm
;
4330 if (!inst
.operands
[i
].negative
)
4331 inst
.instruction
|= INDEX_UP
;
4332 if (inst
.operands
[i
].shifted
)
4334 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
4335 inst
.instruction
|= SHIFT_ROR
<< 5;
4338 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
4339 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
4343 else /* immediate offset in inst.reloc */
4345 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4346 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
4350 /* inst.operands[i] was set up by parse_address. Encode it into an
4351 ARM-format mode 3 load or store instruction. Reject forms that
4352 cannot be used with such instructions. If is_t is true, reject
4353 forms that cannot be used with a T instruction (i.e. not
4356 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
4358 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
4360 inst
.error
= _("instruction does not accept scaled register index");
4364 encode_arm_addr_mode_common (i
, is_t
);
4366 if (inst
.operands
[i
].immisreg
)
4368 inst
.instruction
|= inst
.operands
[i
].imm
;
4369 if (!inst
.operands
[i
].negative
)
4370 inst
.instruction
|= INDEX_UP
;
4372 else /* immediate offset in inst.reloc */
4374 inst
.instruction
|= HWOFFSET_IMM
;
4375 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4376 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
4380 /* inst.operands[i] was set up by parse_address. Encode it into an
4381 ARM-format instruction. Reject all forms which cannot be encoded
4382 into a coprocessor load/store instruction. If wb_ok is false,
4383 reject use of writeback; if unind_ok is false, reject use of
4384 unindexed addressing. If reloc_override is not 0, use it instead
4385 of BFD_ARM_CP_OFF_IMM. */
4388 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
4390 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
4392 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
4394 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
4396 assert (!inst
.operands
[i
].writeback
);
4399 inst
.error
= _("instruction does not support unindexed addressing");
4402 inst
.instruction
|= inst
.operands
[i
].imm
;
4403 inst
.instruction
|= INDEX_UP
;
4407 if (inst
.operands
[i
].preind
)
4408 inst
.instruction
|= PRE_INDEX
;
4410 if (inst
.operands
[i
].writeback
)
4412 if (inst
.operands
[i
].reg
== REG_PC
)
4414 inst
.error
= _("pc may not be used with write-back");
4419 inst
.error
= _("instruction does not support writeback");
4422 inst
.instruction
|= WRITE_BACK
;
4426 inst
.reloc
.type
= reloc_override
;
4427 else if (thumb_mode
)
4428 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
4430 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
4434 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4435 Determine whether it can be performed with a move instruction; if
4436 it can, convert inst.instruction to that move instruction and
4437 return 1; if it can't, convert inst.instruction to a literal-pool
4438 load and return 0. If this is not a valid thing to do in the
4439 current context, set inst.error and return 1.
4441 inst.operands[i] describes the destination register. */
4444 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
4446 if ((inst
.instruction
& (thumb_p
? THUMB_LOAD_BIT
: LOAD_BIT
)) == 0)
4448 inst
.error
= _("invalid pseudo operation");
4451 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
4453 inst
.error
= _("constant expression expected");
4456 if (inst
.reloc
.exp
.X_op
== O_constant
)
4460 if ((inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
4462 /* This can be done with a mov(1) instruction. */
4463 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
4464 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
4470 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
4473 /* This can be done with a mov instruction. */
4474 inst
.instruction
&= LITERAL_MASK
;
4475 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
4476 inst
.instruction
|= value
& 0xfff;
4480 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
4483 /* This can be done with a mvn instruction. */
4484 inst
.instruction
&= LITERAL_MASK
;
4485 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
4486 inst
.instruction
|= value
& 0xfff;
4492 if (add_to_lit_pool () == FAIL
)
4494 inst
.error
= _("literal pool insertion failed");
4497 inst
.operands
[1].reg
= REG_PC
;
4498 inst
.operands
[1].isreg
= 1;
4499 inst
.operands
[1].preind
= 1;
4500 inst
.reloc
.pc_rel
= 1;
4501 inst
.reloc
.type
= (thumb_p
4502 ? BFD_RELOC_ARM_THUMB_OFFSET
4504 ? BFD_RELOC_ARM_HWLITERAL
4505 : BFD_RELOC_ARM_LITERAL
));
4509 /* Functions for instruction encoding, sorted by subarchitecture.
4510 First some generics; their names are taken from the conventional
4511 bit positions for register arguments in ARM format instructions. */
4521 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4528 inst
.instruction
|= inst
.operands
[1].reg
;
4534 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4535 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4541 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4542 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
4548 unsigned Rn
= inst
.operands
[2].reg
;
4549 /* Enforce resutrictions on SWP instruction. */
4550 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
4551 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
4552 _("Rn must not overlap other operands"));
4553 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4554 inst
.instruction
|= inst
.operands
[1].reg
;
4555 inst
.instruction
|= Rn
<< 16;
4561 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4562 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4563 inst
.instruction
|= inst
.operands
[2].reg
;
4569 inst
.instruction
|= inst
.operands
[0].reg
;
4570 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
4571 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4577 inst
.instruction
|= inst
.operands
[0].imm
;
4583 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4584 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
4587 /* ARM instructions, in alphabetical order by function name (except
4588 that wrapper functions appear immediately after the function they
4591 /* This is a pseudo-op of the form "adr rd, label" to be converted
4592 into a relative address of the form "add rd, pc, #label-.-8". */
4597 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
4599 /* Frag hacking will turn this into a sub instruction if the offset turns
4600 out to be negative. */
4601 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4602 inst
.reloc
.pc_rel
= 1;
4603 inst
.reloc
.exp
.X_add_number
-= 8;
4606 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4607 into a relative address of the form:
4608 add rd, pc, #low(label-.-8)"
4609 add rd, rd, #high(label-.-8)" */
4614 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
4616 /* Frag hacking will turn this into a sub instruction if the offset turns
4617 out to be negative. */
4618 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
4619 inst
.reloc
.pc_rel
= 1;
4620 inst
.size
= INSN_SIZE
* 2;
4621 inst
.reloc
.exp
.X_add_number
-= 8;
4627 if (!inst
.operands
[1].present
)
4628 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
4629 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4630 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4631 encode_arm_shifter_operand (2);
4637 if (inst
.operands
[0].present
)
4639 constraint ((inst
.instruction
& 0xf0) != 0x40
4640 && inst
.operands
[0].imm
!= 0xf,
4641 "bad barrier type");
4642 inst
.instruction
|= inst
.operands
[0].imm
;
4645 inst
.instruction
|= 0xf;
4651 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
4652 constraint (msb
> 32, _("bit-field extends past end of register"));
4653 /* The instruction encoding stores the LSB and MSB,
4654 not the LSB and width. */
4655 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4656 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
4657 inst
.instruction
|= (msb
- 1) << 16;
4665 /* #0 in second position is alternative syntax for bfc, which is
4666 the same instruction but with REG_PC in the Rm field. */
4667 if (!inst
.operands
[1].isreg
)
4668 inst
.operands
[1].reg
= REG_PC
;
4670 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
4671 constraint (msb
> 32, _("bit-field extends past end of register"));
4672 /* The instruction encoding stores the LSB and MSB,
4673 not the LSB and width. */
4674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4675 inst
.instruction
|= inst
.operands
[1].reg
;
4676 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
4677 inst
.instruction
|= (msb
- 1) << 16;
4683 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
4684 _("bit-field extends past end of register"));
4685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4686 inst
.instruction
|= inst
.operands
[1].reg
;
4687 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
4688 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
4691 /* ARM V5 breakpoint instruction (argument parse)
4692 BKPT <16 bit unsigned immediate>
4693 Instruction is not conditional.
4694 The bit pattern given in insns[] has the COND_ALWAYS condition,
4695 and it is an error if the caller tried to override that. */
4700 /* Top 12 of 16 bits to bits 19:8. */
4701 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
4703 /* Bottom 4 of 16 bits to bits 3:0. */
4704 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
4708 encode_branch (int default_reloc
)
4710 if (inst
.operands
[0].hasreloc
)
4712 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
4713 _("the only suffix valid here is '(plt)'"));
4714 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
4718 inst
.reloc
.type
= default_reloc
;
4720 inst
.reloc
.pc_rel
= 1;
4727 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
4728 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
4731 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
4738 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
4740 if (inst
.cond
== COND_ALWAYS
)
4741 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
4743 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
4747 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
4750 /* ARM V5 branch-link-exchange instruction (argument parse)
4751 BLX <target_addr> ie BLX(1)
4752 BLX{<condition>} <Rm> ie BLX(2)
4753 Unfortunately, there are two different opcodes for this mnemonic.
4754 So, the insns[].value is not used, and the code here zaps values
4755 into inst.instruction.
4756 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4761 if (inst
.operands
[0].isreg
)
4763 /* Arg is a register; the opcode provided by insns[] is correct.
4764 It is not illegal to do "blx pc", just useless. */
4765 if (inst
.operands
[0].reg
== REG_PC
)
4766 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4768 inst
.instruction
|= inst
.operands
[0].reg
;
4772 /* Arg is an address; this instruction cannot be executed
4773 conditionally, and the opcode must be adjusted. */
4774 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
4775 inst
.instruction
= 0xfa000000;
4777 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
4778 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
4781 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
4788 if (inst
.operands
[0].reg
== REG_PC
)
4789 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4791 inst
.instruction
|= inst
.operands
[0].reg
;
4795 /* ARM v5TEJ. Jump to Jazelle code. */
4800 if (inst
.operands
[0].reg
== REG_PC
)
4801 as_tsktsk (_("use of r15 in bxj is not really useful"));
4803 inst
.instruction
|= inst
.operands
[0].reg
;
4806 /* Co-processor data operation:
4807 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4808 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4812 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4813 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
4814 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4815 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4816 inst
.instruction
|= inst
.operands
[4].reg
;
4817 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
4823 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4824 encode_arm_shifter_operand (1);
4827 /* Transfer between coprocessor and ARM registers.
4828 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4833 No special properties. */
4838 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4839 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
4840 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4841 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4842 inst
.instruction
|= inst
.operands
[4].reg
;
4843 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
4846 /* Transfer between coprocessor register and pair of ARM registers.
4847 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4852 Two XScale instructions are special cases of these:
4854 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4855 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4857 Result unpredicatable if Rd or Rn is R15. */
4862 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4863 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
4864 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4865 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4866 inst
.instruction
|= inst
.operands
[4].reg
;
4872 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
4873 inst
.instruction
|= inst
.operands
[1].imm
;
4879 inst
.instruction
|= inst
.operands
[0].imm
;
4885 /* There is no IT instruction in ARM mode. We
4886 process it but do not generate code for it. */
4893 int base_reg
= inst
.operands
[0].reg
;
4894 int range
= inst
.operands
[1].imm
;
4896 inst
.instruction
|= base_reg
<< 16;
4897 inst
.instruction
|= range
;
4899 if (inst
.operands
[1].writeback
)
4900 inst
.instruction
|= LDM_TYPE_2_OR_3
;
4902 if (inst
.operands
[0].writeback
)
4904 inst
.instruction
|= WRITE_BACK
;
4905 /* Check for unpredictable uses of writeback. */
4906 if (inst
.instruction
& LOAD_BIT
)
4908 /* Not allowed in LDM type 2. */
4909 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
4910 && ((range
& (1 << REG_PC
)) == 0))
4911 as_warn (_("writeback of base register is UNPREDICTABLE"));
4912 /* Only allowed if base reg not in list for other types. */
4913 else if (range
& (1 << base_reg
))
4914 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4918 /* Not allowed for type 2. */
4919 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
4920 as_warn (_("writeback of base register is UNPREDICTABLE"));
4921 /* Only allowed if base reg not in list, or first in list. */
4922 else if ((range
& (1 << base_reg
))
4923 && (range
& ((1 << base_reg
) - 1)))
4924 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4929 /* ARMv5TE load-consecutive (argument parse)
4938 constraint (inst
.operands
[0].reg
% 2 != 0,
4939 _("first destination register must be even"));
4940 constraint (inst
.operands
[1].present
4941 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
4942 _("can only load two consecutive registers"));
4943 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
4944 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
4946 if (!inst
.operands
[1].present
)
4947 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
4949 if (inst
.instruction
& LOAD_BIT
)
4951 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4952 register and the first register written; we have to diagnose
4953 overlap between the base and the second register written here. */
4955 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
4956 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
4957 as_warn (_("base register written back, and overlaps "
4958 "second destination register"));
4960 /* For an index-register load, the index register must not overlap the
4961 destination (even if not write-back). */
4962 else if (inst
.operands
[2].immisreg
4963 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
4964 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
4965 as_warn (_("index register overlaps destination register"));
4968 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4969 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
4975 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
4976 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
4977 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
4978 || inst
.operands
[1].negative
4979 /* This can arise if the programmer has written
4981 or if they have mistakenly used a register name as the last
4984 It is very difficult to distinguish between these two cases
4985 because "rX" might actually be a label. ie the register
4986 name has been occluded by a symbol of the same name. So we
4987 just generate a general 'bad addressing mode' type error
4988 message and leave it up to the programmer to discover the
4989 true cause and fix their mistake. */
4990 || (inst
.operands
[1].reg
== REG_PC
),
4993 constraint (inst
.reloc
.exp
.X_op
!= O_constant
4994 || inst
.reloc
.exp
.X_add_number
!= 0,
4995 _("offset must be zero in ARM encoding"));
4997 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4998 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4999 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5005 constraint (inst
.operands
[0].reg
% 2 != 0,
5006 _("even register required"));
5007 constraint (inst
.operands
[1].present
5008 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
5009 _("can only load two consecutive registers"));
5010 /* If op 1 were present and equal to PC, this function wouldn't
5011 have been called in the first place. */
5012 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
5014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5015 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5022 if (!inst
.operands
[1].isreg
)
5023 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
5025 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
5031 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
5033 if (inst
.operands
[1].preind
)
5035 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
5036 inst
.reloc
.exp
.X_add_number
!= 0,
5037 _("this instruction requires a post-indexed address"));
5039 inst
.operands
[1].preind
= 0;
5040 inst
.operands
[1].postind
= 1;
5041 inst
.operands
[1].writeback
= 1;
5043 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5044 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
5047 /* Halfword and signed-byte load/store operations. */
5052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5053 if (!inst
.operands
[1].isreg
)
5054 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
5056 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
5062 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
5064 if (inst
.operands
[1].preind
)
5066 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
5067 inst
.reloc
.exp
.X_add_number
!= 0,
5068 _("this instruction requires a post-indexed address"));
5070 inst
.operands
[1].preind
= 0;
5071 inst
.operands
[1].postind
= 1;
5072 inst
.operands
[1].writeback
= 1;
5074 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5075 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
5078 /* Co-processor register load/store.
5079 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
5083 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
5084 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5085 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
5091 /* This restriction does not apply to mls (nor to mla in v6, but
5092 that's hard to detect at present). */
5093 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
5094 && !(inst
.instruction
& 0x00400000))
5095 as_tsktsk (_("rd and rm should be different in mla"));
5097 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5098 inst
.instruction
|= inst
.operands
[1].reg
;
5099 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5100 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
5107 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5108 encode_arm_shifter_operand (1);
5111 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
5115 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5116 /* The value is in two pieces: 0:11, 16:19. */
5117 inst
.instruction
|= (inst
.operands
[1].imm
& 0x00000fff);
5118 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0000f000) << 4;
5124 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
5125 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
5127 _("'CPSR' or 'SPSR' expected"));
5128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5129 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
5132 /* Two possible forms:
5133 "{C|S}PSR_<field>, Rm",
5134 "{C|S}PSR_f, #expression". */
5139 inst
.instruction
|= inst
.operands
[0].imm
;
5140 if (inst
.operands
[1].isreg
)
5141 inst
.instruction
|= inst
.operands
[1].reg
;
5144 inst
.instruction
|= INST_IMMEDIATE
;
5145 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5146 inst
.reloc
.pc_rel
= 0;
5153 if (!inst
.operands
[2].present
)
5154 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
5155 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5156 inst
.instruction
|= inst
.operands
[1].reg
;
5157 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5159 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
5160 as_tsktsk (_("rd and rm should be different in mul"));
5163 /* Long Multiply Parser
5164 UMULL RdLo, RdHi, Rm, Rs
5165 SMULL RdLo, RdHi, Rm, Rs
5166 UMLAL RdLo, RdHi, Rm, Rs
5167 SMLAL RdLo, RdHi, Rm, Rs. */
5172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5173 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5174 inst
.instruction
|= inst
.operands
[2].reg
;
5175 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
5177 /* rdhi, rdlo and rm must all be different. */
5178 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
5179 || inst
.operands
[0].reg
== inst
.operands
[2].reg
5180 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
5181 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
5187 if (inst
.operands
[0].present
)
5189 /* Architectural NOP hints are CPSR sets with no bits selected. */
5190 inst
.instruction
&= 0xf0000000;
5191 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
5195 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
5196 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
5197 Condition defaults to COND_ALWAYS.
5198 Error if Rd, Rn or Rm are R15. */
5203 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5204 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5205 inst
.instruction
|= inst
.operands
[2].reg
;
5206 if (inst
.operands
[3].present
)
5207 encode_arm_shift (3);
5210 /* ARM V6 PKHTB (Argument Parse). */
5215 if (!inst
.operands
[3].present
)
5217 /* If the shift specifier is omitted, turn the instruction
5218 into pkhbt rd, rm, rn. */
5219 inst
.instruction
&= 0xfff00010;
5220 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5221 inst
.instruction
|= inst
.operands
[1].reg
;
5222 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5226 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5227 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5228 inst
.instruction
|= inst
.operands
[2].reg
;
5229 encode_arm_shift (3);
5233 /* ARMv5TE: Preload-Cache
5237 Syntactically, like LDR with B=1, W=0, L=1. */
5242 constraint (!inst
.operands
[0].isreg
,
5243 _("'[' expected after PLD mnemonic"));
5244 constraint (inst
.operands
[0].postind
,
5245 _("post-indexed expression used in preload instruction"));
5246 constraint (inst
.operands
[0].writeback
,
5247 _("writeback used in preload instruction"));
5248 constraint (!inst
.operands
[0].preind
,
5249 _("unindexed addressing used in preload instruction"));
5250 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
5253 /* ARMv7: PLI <addr_mode> */
5257 constraint (!inst
.operands
[0].isreg
,
5258 _("'[' expected after PLI mnemonic"));
5259 constraint (inst
.operands
[0].postind
,
5260 _("post-indexed expression used in preload instruction"));
5261 constraint (inst
.operands
[0].writeback
,
5262 _("writeback used in preload instruction"));
5263 constraint (!inst
.operands
[0].preind
,
5264 _("unindexed addressing used in preload instruction"));
5265 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
5266 inst
.instruction
&= ~PRE_INDEX
;
5272 inst
.operands
[1] = inst
.operands
[0];
5273 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
5274 inst
.operands
[0].isreg
= 1;
5275 inst
.operands
[0].writeback
= 1;
5276 inst
.operands
[0].reg
= REG_SP
;
5280 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
5281 word at the specified address and the following word
5283 Unconditionally executed.
5284 Error if Rn is R15. */
5289 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5290 if (inst
.operands
[0].writeback
)
5291 inst
.instruction
|= WRITE_BACK
;
5294 /* ARM V6 ssat (argument parse). */
5299 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5300 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
5301 inst
.instruction
|= inst
.operands
[2].reg
;
5303 if (inst
.operands
[3].present
)
5304 encode_arm_shift (3);
5307 /* ARM V6 usat (argument parse). */
5312 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5313 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
5314 inst
.instruction
|= inst
.operands
[2].reg
;
5316 if (inst
.operands
[3].present
)
5317 encode_arm_shift (3);
5320 /* ARM V6 ssat16 (argument parse). */
5325 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5326 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
5327 inst
.instruction
|= inst
.operands
[2].reg
;
5333 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5334 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
5335 inst
.instruction
|= inst
.operands
[2].reg
;
5338 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5339 preserving the other bits.
5341 setend <endian_specifier>, where <endian_specifier> is either
5347 if (inst
.operands
[0].imm
)
5348 inst
.instruction
|= 0x200;
5354 unsigned int Rm
= (inst
.operands
[1].present
5355 ? inst
.operands
[1].reg
5356 : inst
.operands
[0].reg
);
5358 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5359 inst
.instruction
|= Rm
;
5360 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
5362 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5363 inst
.instruction
|= SHIFT_BY_REG
;
5366 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
5372 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
5373 inst
.reloc
.pc_rel
= 0;
5379 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
5380 inst
.reloc
.pc_rel
= 0;
5383 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5384 SMLAxy{cond} Rd,Rm,Rs,Rn
5385 SMLAWy{cond} Rd,Rm,Rs,Rn
5386 Error if any register is R15. */
5391 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5392 inst
.instruction
|= inst
.operands
[1].reg
;
5393 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5394 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
5397 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5398 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5399 Error if any register is R15.
5400 Warning if Rdlo == Rdhi. */
5405 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5406 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5407 inst
.instruction
|= inst
.operands
[2].reg
;
5408 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
5410 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
5411 as_tsktsk (_("rdhi and rdlo must be different"));
5414 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5415 SMULxy{cond} Rd,Rm,Rs
5416 Error if any register is R15. */
5421 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5422 inst
.instruction
|= inst
.operands
[1].reg
;
5423 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5426 /* ARM V6 srs (argument parse). */
5431 inst
.instruction
|= inst
.operands
[0].imm
;
5432 if (inst
.operands
[0].writeback
)
5433 inst
.instruction
|= WRITE_BACK
;
5436 /* ARM V6 strex (argument parse). */
5441 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
5442 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
5443 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
5444 || inst
.operands
[2].negative
5445 /* See comment in do_ldrex(). */
5446 || (inst
.operands
[2].reg
== REG_PC
),
5449 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
5450 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
5452 constraint (inst
.reloc
.exp
.X_op
!= O_constant
5453 || inst
.reloc
.exp
.X_add_number
!= 0,
5454 _("offset must be zero in ARM encoding"));
5456 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5457 inst
.instruction
|= inst
.operands
[1].reg
;
5458 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5459 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5465 constraint (inst
.operands
[1].reg
% 2 != 0,
5466 _("even register required"));
5467 constraint (inst
.operands
[2].present
5468 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
5469 _("can only store two consecutive registers"));
5470 /* If op 2 were present and equal to PC, this function wouldn't
5471 have been called in the first place. */
5472 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
5474 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
5475 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
5476 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
5479 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5480 inst
.instruction
|= inst
.operands
[1].reg
;
5481 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
5484 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5485 extends it to 32-bits, and adds the result to a value in another
5486 register. You can specify a rotation by 0, 8, 16, or 24 bits
5487 before extracting the 16-bit value.
5488 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5489 Condition defaults to COND_ALWAYS.
5490 Error if any register uses R15. */
5495 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5496 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5497 inst
.instruction
|= inst
.operands
[2].reg
;
5498 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
5503 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5504 Condition defaults to COND_ALWAYS.
5505 Error if any register uses R15. */
5510 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5511 inst
.instruction
|= inst
.operands
[1].reg
;
5512 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
5515 /* VFP instructions. In a logical order: SP variant first, monad
5516 before dyad, arithmetic then move then load/store. */
5519 do_vfp_sp_monadic (void)
5521 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5522 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
5526 do_vfp_sp_dyadic (void)
5528 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5529 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
5530 encode_arm_vfp_sp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
5534 do_vfp_sp_compare_z (void)
5536 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5540 do_vfp_dp_sp_cvt (void)
5542 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5543 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
5547 do_vfp_sp_dp_cvt (void)
5549 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5550 inst
.instruction
|= inst
.operands
[1].reg
;
5554 do_vfp_reg_from_sp (void)
5556 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5557 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
5561 do_vfp_reg2_from_sp2 (void)
5563 constraint (inst
.operands
[2].imm
!= 2,
5564 _("only two consecutive VFP SP registers allowed here"));
5565 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5566 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5567 encode_arm_vfp_sp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
5571 do_vfp_sp_from_reg (void)
5573 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
5574 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5578 do_vfp_sp2_from_reg2 (void)
5580 constraint (inst
.operands
[0].imm
!= 2,
5581 _("only two consecutive VFP SP registers allowed here"));
5582 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
5583 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5584 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5588 do_vfp_sp_ldst (void)
5590 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5591 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
5595 do_vfp_dp_ldst (void)
5597 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5598 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
5603 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
5605 if (inst
.operands
[0].writeback
)
5606 inst
.instruction
|= WRITE_BACK
;
5608 constraint (ldstm_type
!= VFP_LDSTMIA
,
5609 _("this addressing mode requires base-register writeback"));
5610 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5611 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
5612 inst
.instruction
|= inst
.operands
[1].imm
;
5616 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
5620 if (inst
.operands
[0].writeback
)
5621 inst
.instruction
|= WRITE_BACK
;
5623 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
5624 _("this addressing mode requires base-register writeback"));
5626 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5627 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5629 count
= inst
.operands
[1].imm
<< 1;
5630 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
5633 inst
.instruction
|= count
;
5637 do_vfp_sp_ldstmia (void)
5639 vfp_sp_ldstm (VFP_LDSTMIA
);
5643 do_vfp_sp_ldstmdb (void)
5645 vfp_sp_ldstm (VFP_LDSTMDB
);
5649 do_vfp_dp_ldstmia (void)
5651 vfp_dp_ldstm (VFP_LDSTMIA
);
5655 do_vfp_dp_ldstmdb (void)
5657 vfp_dp_ldstm (VFP_LDSTMDB
);
5661 do_vfp_xp_ldstmia (void)
5663 vfp_dp_ldstm (VFP_LDSTMIAX
);
5667 do_vfp_xp_ldstmdb (void)
5669 vfp_dp_ldstm (VFP_LDSTMDBX
);
5672 /* FPA instructions. Also in a logical order. */
5677 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5678 inst
.instruction
|= inst
.operands
[1].reg
;
5682 do_fpa_ldmstm (void)
5684 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5685 switch (inst
.operands
[1].imm
)
5687 case 1: inst
.instruction
|= CP_T_X
; break;
5688 case 2: inst
.instruction
|= CP_T_Y
; break;
5689 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
5694 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
5696 /* The instruction specified "ea" or "fd", so we can only accept
5697 [Rn]{!}. The instruction does not really support stacking or
5698 unstacking, so we have to emulate these by setting appropriate
5699 bits and offsets. */
5700 constraint (inst
.reloc
.exp
.X_op
!= O_constant
5701 || inst
.reloc
.exp
.X_add_number
!= 0,
5702 _("this instruction does not support indexing"));
5704 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
5705 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
5707 if (!(inst
.instruction
& INDEX_UP
))
5708 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
5710 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
5712 inst
.operands
[2].preind
= 0;
5713 inst
.operands
[2].postind
= 1;
5717 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
5720 /* iWMMXt instructions: strictly in alphabetical order. */
5723 do_iwmmxt_tandorc (void)
5725 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
5729 do_iwmmxt_textrc (void)
5731 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5732 inst
.instruction
|= inst
.operands
[1].imm
;
5736 do_iwmmxt_textrm (void)
5738 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5739 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5740 inst
.instruction
|= inst
.operands
[2].imm
;
5744 do_iwmmxt_tinsr (void)
5746 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5747 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5748 inst
.instruction
|= inst
.operands
[2].imm
;
5752 do_iwmmxt_tmia (void)
5754 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
5755 inst
.instruction
|= inst
.operands
[1].reg
;
5756 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5760 do_iwmmxt_waligni (void)
5762 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5763 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5764 inst
.instruction
|= inst
.operands
[2].reg
;
5765 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
5769 do_iwmmxt_wmov (void)
5771 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5772 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5773 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5774 inst
.instruction
|= inst
.operands
[1].reg
;
5778 do_iwmmxt_wldstbh (void)
5781 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5782 inst
.reloc
.exp
.X_add_number
*= 4;
5784 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
5786 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
5787 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
5791 do_iwmmxt_wldstw (void)
5793 /* RIWR_RIWC clears .isreg for a control register. */
5794 if (!inst
.operands
[0].isreg
)
5796 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
5797 inst
.instruction
|= 0xf0000000;
5800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5801 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
5805 do_iwmmxt_wldstd (void)
5807 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5808 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
5812 do_iwmmxt_wshufh (void)
5814 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5815 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5816 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
5817 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
5821 do_iwmmxt_wzero (void)
5823 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5824 inst
.instruction
|= inst
.operands
[0].reg
;
5825 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5826 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5829 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5830 operations first, then control, shift, and load/store. */
5832 /* Insns like "foo X,Y,Z". */
5835 do_mav_triple (void)
5837 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5838 inst
.instruction
|= inst
.operands
[1].reg
;
5839 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5842 /* Insns like "foo W,X,Y,Z".
5843 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5848 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
5849 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5850 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5851 inst
.instruction
|= inst
.operands
[3].reg
;
5854 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5858 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5861 /* Maverick shift immediate instructions.
5862 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5863 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5868 int imm
= inst
.operands
[2].imm
;
5870 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5871 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5873 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5874 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5875 Bit 4 should be 0. */
5876 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
5878 inst
.instruction
|= imm
;
5881 /* XScale instructions. Also sorted arithmetic before move. */
5883 /* Xscale multiply-accumulate (argument parse)
5886 MIAxycc acc0,Rm,Rs. */
5891 inst
.instruction
|= inst
.operands
[1].reg
;
5892 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5895 /* Xscale move-accumulator-register (argument parse)
5897 MARcc acc0,RdLo,RdHi. */
5902 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5903 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5906 /* Xscale move-register-accumulator (argument parse)
5908 MRAcc RdLo,RdHi,acc0. */
5913 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
5914 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5915 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5918 /* Encoding functions relevant only to Thumb. */
5920 /* inst.operands[i] is a shifted-register operand; encode
5921 it into inst.instruction in the format used by Thumb32. */
5924 encode_thumb32_shifted_operand (int i
)
5926 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
5927 unsigned int shift
= inst
.operands
[i
].shift_kind
;
5929 constraint (inst
.operands
[i
].immisreg
,
5930 _("shift by register not allowed in thumb mode"));
5931 inst
.instruction
|= inst
.operands
[i
].reg
;
5932 if (shift
== SHIFT_RRX
)
5933 inst
.instruction
|= SHIFT_ROR
<< 4;
5936 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
5937 _("expression too complex"));
5939 constraint (value
> 32
5940 || (value
== 32 && (shift
== SHIFT_LSL
5941 || shift
== SHIFT_ROR
)),
5942 _("shift expression is too large"));
5946 else if (value
== 32)
5949 inst
.instruction
|= shift
<< 4;
5950 inst
.instruction
|= (value
& 0x1c) << 10;
5951 inst
.instruction
|= (value
& 0x03) << 6;
5956 /* inst.operands[i] was set up by parse_address. Encode it into a
5957 Thumb32 format load or store instruction. Reject forms that cannot
5958 be used with such instructions. If is_t is true, reject forms that
5959 cannot be used with a T instruction; if is_d is true, reject forms
5960 that cannot be used with a D instruction. */
5963 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
5965 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
5967 constraint (!inst
.operands
[i
].isreg
,
5968 _("Thumb does not support the ldr =N pseudo-operation"));
5970 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
5971 if (inst
.operands
[i
].immisreg
)
5973 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
5974 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
5975 constraint (inst
.operands
[i
].negative
,
5976 _("Thumb does not support negative register indexing"));
5977 constraint (inst
.operands
[i
].postind
,
5978 _("Thumb does not support register post-indexing"));
5979 constraint (inst
.operands
[i
].writeback
,
5980 _("Thumb does not support register indexing with writeback"));
5981 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
5982 _("Thumb supports only LSL in shifted register indexing"));
5984 inst
.instruction
|= inst
.operands
[i
].imm
;
5985 if (inst
.operands
[i
].shifted
)
5987 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
5988 _("expression too complex"));
5989 constraint (inst
.reloc
.exp
.X_add_number
< 0
5990 || inst
.reloc
.exp
.X_add_number
> 3,
5991 _("shift out of range"));
5992 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
5994 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5996 else if (inst
.operands
[i
].preind
)
5998 constraint (is_pc
&& inst
.operands
[i
].writeback
,
5999 _("cannot use writeback with PC-relative addressing"));
6000 constraint (is_t
&& inst
.operands
[i
].writeback
,
6001 _("cannot use writeback with this instruction"));
6005 inst
.instruction
|= 0x01000000;
6006 if (inst
.operands
[i
].writeback
)
6007 inst
.instruction
|= 0x00200000;
6011 inst
.instruction
|= 0x00000c00;
6012 if (inst
.operands
[i
].writeback
)
6013 inst
.instruction
|= 0x00000100;
6015 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
6017 else if (inst
.operands
[i
].postind
)
6019 assert (inst
.operands
[i
].writeback
);
6020 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
6021 constraint (is_t
, _("cannot use post-indexing with this instruction"));
6024 inst
.instruction
|= 0x00200000;
6026 inst
.instruction
|= 0x00000900;
6027 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
6029 else /* unindexed - only for coprocessor */
6030 inst
.error
= _("instruction does not accept unindexed addressing");
6033 /* Table of Thumb instructions which exist in both 16- and 32-bit
6034 encodings (the latter only in post-V6T2 cores). The index is the
6035 value used in the insns table below. When there is more than one
6036 possible 16-bit encoding for the instruction, this table always
6038 Also contains several pseudo-instructions used during relaxation. */
6039 #define T16_32_TAB \
6040 X(adc, 4140, eb400000), \
6041 X(adcs, 4140, eb500000), \
6042 X(add, 1c00, eb000000), \
6043 X(adds, 1c00, eb100000), \
6044 X(addi, 0000, f1000000), \
6045 X(addis, 0000, f1100000), \
6046 X(add_pc,000f, f20f0000), \
6047 X(add_sp,000d, f10d0000), \
6048 X(adr, 000f, f20f0000), \
6049 X(and, 4000, ea000000), \
6050 X(ands, 4000, ea100000), \
6051 X(asr, 1000, fa40f000), \
6052 X(asrs, 1000, fa50f000), \
6053 X(b, e000, f000b000), \
6054 X(bcond, d000, f0008000), \
6055 X(bic, 4380, ea200000), \
6056 X(bics, 4380, ea300000), \
6057 X(cmn, 42c0, eb100f00), \
6058 X(cmp, 2800, ebb00f00), \
6059 X(cpsie, b660, f3af8400), \
6060 X(cpsid, b670, f3af8600), \
6061 X(cpy, 4600, ea4f0000), \
6062 X(dec_sp,80dd, f1bd0d00), \
6063 X(eor, 4040, ea800000), \
6064 X(eors, 4040, ea900000), \
6065 X(inc_sp,00dd, f10d0d00), \
6066 X(ldmia, c800, e8900000), \
6067 X(ldr, 6800, f8500000), \
6068 X(ldrb, 7800, f8100000), \
6069 X(ldrh, 8800, f8300000), \
6070 X(ldrsb, 5600, f9100000), \
6071 X(ldrsh, 5e00, f9300000), \
6072 X(ldr_pc,4800, f85f0000), \
6073 X(ldr_pc2,4800, f85f0000), \
6074 X(ldr_sp,9800, f85d0000), \
6075 X(lsl, 0000, fa00f000), \
6076 X(lsls, 0000, fa10f000), \
6077 X(lsr, 0800, fa20f000), \
6078 X(lsrs, 0800, fa30f000), \
6079 X(mov, 2000, ea4f0000), \
6080 X(movs, 2000, ea5f0000), \
6081 X(mul, 4340, fb00f000), \
6082 X(muls, 4340, ffffffff), /* no 32b muls */ \
6083 X(mvn, 43c0, ea6f0000), \
6084 X(mvns, 43c0, ea7f0000), \
6085 X(neg, 4240, f1c00000), /* rsb #0 */ \
6086 X(negs, 4240, f1d00000), /* rsbs #0 */ \
6087 X(orr, 4300, ea400000), \
6088 X(orrs, 4300, ea500000), \
6089 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
6090 X(push, b400, e92d0000), /* stmdb sp!,... */ \
6091 X(rev, ba00, fa90f080), \
6092 X(rev16, ba40, fa90f090), \
6093 X(revsh, bac0, fa90f0b0), \
6094 X(ror, 41c0, fa60f000), \
6095 X(rors, 41c0, fa70f000), \
6096 X(sbc, 4180, eb600000), \
6097 X(sbcs, 4180, eb700000), \
6098 X(stmia, c000, e8800000), \
6099 X(str, 6000, f8400000), \
6100 X(strb, 7000, f8000000), \
6101 X(strh, 8000, f8200000), \
6102 X(str_sp,9000, f84d0000), \
6103 X(sub, 1e00, eba00000), \
6104 X(subs, 1e00, ebb00000), \
6105 X(subi, 8000, f1a00000), \
6106 X(subis, 8000, f1b00000), \
6107 X(sxtb, b240, fa4ff080), \
6108 X(sxth, b200, fa0ff080), \
6109 X(tst, 4200, ea100f00), \
6110 X(uxtb, b2c0, fa5ff080), \
6111 X(uxth, b280, fa1ff080), \
6112 X(nop, bf00, f3af8000), \
6113 X(yield, bf10, f3af8001), \
6114 X(wfe, bf20, f3af8002), \
6115 X(wfi, bf30, f3af8003), \
6116 X(sev, bf40, f3af9004), /* typo, 8004? */
6118 /* To catch errors in encoding functions, the codes are all offset by
6119 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
6120 as 16-bit instructions. */
6121 #define X(a,b,c) T_MNEM_##a
6122 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
6125 #define X(a,b,c) 0x##b
6126 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
6127 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
6130 #define X(a,b,c) 0x##c
6131 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
6132 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
6133 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
6137 /* Thumb instruction encoders, in alphabetical order. */
6141 do_t_add_sub_w (void)
6145 Rd
= inst
.operands
[0].reg
;
6146 Rn
= inst
.operands
[1].reg
;
6148 constraint (Rd
== 15, _("PC not allowed as destination"));
6149 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
6150 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
6153 /* Parse an add or subtract instruction. We get here with inst.instruction
6154 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
6161 Rd
= inst
.operands
[0].reg
;
6162 Rs
= (inst
.operands
[1].present
6163 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
6164 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
6172 flags
= (inst
.instruction
== T_MNEM_adds
6173 || inst
.instruction
== T_MNEM_subs
);
6175 narrow
= (current_it_mask
== 0);
6177 narrow
= (current_it_mask
!= 0);
6178 if (!inst
.operands
[2].isreg
)
6181 if (inst
.size_req
!= 4)
6185 add
= (inst
.instruction
== T_MNEM_add
6186 || inst
.instruction
== T_MNEM_adds
);
6187 /* Attempt to use a narrow opcode, with relaxation if
6189 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
6190 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
6191 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
6192 opcode
= T_MNEM_add_sp
;
6193 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
6194 opcode
= T_MNEM_add_pc
;
6195 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
6198 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
6200 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
6204 inst
.instruction
= THUMB_OP16(opcode
);
6205 inst
.instruction
|= (Rd
<< 4) | Rs
;
6206 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
6207 if (inst
.size_req
!= 2)
6208 inst
.relax
= opcode
;
6211 constraint (inst
.size_req
== 2, BAD_HIREG
);
6213 if (inst
.size_req
== 4
6214 || (inst
.size_req
!= 2 && !opcode
))
6216 /* ??? Convert large immediates to addw/subw. */
6217 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6218 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6219 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6220 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6221 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6226 Rn
= inst
.operands
[2].reg
;
6227 /* See if we can do this with a 16-bit instruction. */
6228 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
6230 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
6235 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
6236 || inst
.instruction
== T_MNEM_add
)
6239 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
6243 if (inst
.instruction
== T_MNEM_add
)
6247 inst
.instruction
= T_OPCODE_ADD_HI
;
6248 inst
.instruction
|= (Rd
& 8) << 4;
6249 inst
.instruction
|= (Rd
& 7);
6250 inst
.instruction
|= Rn
<< 3;
6253 /* ... because addition is commutative! */
6256 inst
.instruction
= T_OPCODE_ADD_HI
;
6257 inst
.instruction
|= (Rd
& 8) << 4;
6258 inst
.instruction
|= (Rd
& 7);
6259 inst
.instruction
|= Rs
<< 3;
6264 /* If we get here, it can't be done in 16 bits. */
6265 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
6266 _("shift must be constant"));
6267 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6268 inst
.instruction
|= Rd
<< 8;
6269 inst
.instruction
|= Rs
<< 16;
6270 encode_thumb32_shifted_operand (2);
6275 constraint (inst
.instruction
== T_MNEM_adds
6276 || inst
.instruction
== T_MNEM_subs
,
6279 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
6281 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
6282 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
6285 inst
.instruction
= (inst
.instruction
== T_MNEM_add
6287 inst
.instruction
|= (Rd
<< 4) | Rs
;
6288 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
6292 Rn
= inst
.operands
[2].reg
;
6293 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
6295 /* We now have Rd, Rs, and Rn set to registers. */
6296 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
6298 /* Can't do this for SUB. */
6299 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
6300 inst
.instruction
= T_OPCODE_ADD_HI
;
6301 inst
.instruction
|= (Rd
& 8) << 4;
6302 inst
.instruction
|= (Rd
& 7);
6304 inst
.instruction
|= Rn
<< 3;
6306 inst
.instruction
|= Rs
<< 3;
6308 constraint (1, _("dest must overlap one source register"));
6312 inst
.instruction
= (inst
.instruction
== T_MNEM_add
6313 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
6314 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
6322 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
6324 /* Defer to section relaxation. */
6325 inst
.relax
= inst
.instruction
;
6326 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6327 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
6329 else if (unified_syntax
&& inst
.size_req
!= 2)
6331 /* Generate a 32-bit opcode. */
6332 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6333 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6334 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
6335 inst
.reloc
.pc_rel
= 1;
6339 /* Generate a 16-bit opcode. */
6340 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6341 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
6342 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
6343 inst
.reloc
.pc_rel
= 1;
6345 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
6349 /* Arithmetic instructions for which there is just one 16-bit
6350 instruction encoding, and it allows only two low registers.
6351 For maximal compatibility with ARM syntax, we allow three register
6352 operands even when Thumb-32 instructions are not available, as long
6353 as the first two are identical. For instance, both "sbc r0,r1" and
6354 "sbc r0,r0,r1" are allowed. */
6360 Rd
= inst
.operands
[0].reg
;
6361 Rs
= (inst
.operands
[1].present
6362 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
6363 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
6364 Rn
= inst
.operands
[2].reg
;
6368 if (!inst
.operands
[2].isreg
)
6370 /* For an immediate, we always generate a 32-bit opcode;
6371 section relaxation will shrink it later if possible. */
6372 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6373 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6374 inst
.instruction
|= Rd
<< 8;
6375 inst
.instruction
|= Rs
<< 16;
6376 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6382 /* See if we can do this with a 16-bit instruction. */
6383 if (THUMB_SETS_FLAGS (inst
.instruction
))
6384 narrow
= current_it_mask
== 0;
6386 narrow
= current_it_mask
!= 0;
6388 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
6390 if (inst
.operands
[2].shifted
)
6392 if (inst
.size_req
== 4)
6398 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6399 inst
.instruction
|= Rd
;
6400 inst
.instruction
|= Rn
<< 3;
6404 /* If we get here, it can't be done in 16 bits. */
6405 constraint (inst
.operands
[2].shifted
6406 && inst
.operands
[2].immisreg
,
6407 _("shift must be constant"));
6408 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6409 inst
.instruction
|= Rd
<< 8;
6410 inst
.instruction
|= Rs
<< 16;
6411 encode_thumb32_shifted_operand (2);
6416 /* On its face this is a lie - the instruction does set the
6417 flags. However, the only supported mnemonic in this mode
6419 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
6421 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
6422 _("unshifted register required"));
6423 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
6424 constraint (Rd
!= Rs
,
6425 _("dest and source1 must be the same register"));
6427 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6428 inst
.instruction
|= Rd
;
6429 inst
.instruction
|= Rn
<< 3;
6433 /* Similarly, but for instructions where the arithmetic operation is
6434 commutative, so we can allow either of them to be different from
6435 the destination operand in a 16-bit instruction. For instance, all
6436 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6443 Rd
= inst
.operands
[0].reg
;
6444 Rs
= (inst
.operands
[1].present
6445 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
6446 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
6447 Rn
= inst
.operands
[2].reg
;
6451 if (!inst
.operands
[2].isreg
)
6453 /* For an immediate, we always generate a 32-bit opcode;
6454 section relaxation will shrink it later if possible. */
6455 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6456 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6457 inst
.instruction
|= Rd
<< 8;
6458 inst
.instruction
|= Rs
<< 16;
6459 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6465 /* See if we can do this with a 16-bit instruction. */
6466 if (THUMB_SETS_FLAGS (inst
.instruction
))
6467 narrow
= current_it_mask
== 0;
6469 narrow
= current_it_mask
!= 0;
6471 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
6473 if (inst
.operands
[2].shifted
)
6475 if (inst
.size_req
== 4)
6482 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6483 inst
.instruction
|= Rd
;
6484 inst
.instruction
|= Rn
<< 3;
6489 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6490 inst
.instruction
|= Rd
;
6491 inst
.instruction
|= Rs
<< 3;
6496 /* If we get here, it can't be done in 16 bits. */
6497 constraint (inst
.operands
[2].shifted
6498 && inst
.operands
[2].immisreg
,
6499 _("shift must be constant"));
6500 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6501 inst
.instruction
|= Rd
<< 8;
6502 inst
.instruction
|= Rs
<< 16;
6503 encode_thumb32_shifted_operand (2);
6508 /* On its face this is a lie - the instruction does set the
6509 flags. However, the only supported mnemonic in this mode
6511 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
6513 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
6514 _("unshifted register required"));
6515 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
6517 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6518 inst
.instruction
|= Rd
;
6521 inst
.instruction
|= Rn
<< 3;
6523 inst
.instruction
|= Rs
<< 3;
6525 constraint (1, _("dest must overlap one source register"));
6532 if (inst
.operands
[0].present
)
6534 constraint ((inst
.instruction
& 0xf0) != 0x40
6535 && inst
.operands
[0].imm
!= 0xf,
6536 "bad barrier type");
6537 inst
.instruction
|= inst
.operands
[0].imm
;
6540 inst
.instruction
|= 0xf;
6546 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6547 constraint (msb
> 32, _("bit-field extends past end of register"));
6548 /* The instruction encoding stores the LSB and MSB,
6549 not the LSB and width. */
6550 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6551 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
6552 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
6553 inst
.instruction
|= msb
- 1;
6561 /* #0 in second position is alternative syntax for bfc, which is
6562 the same instruction but with REG_PC in the Rm field. */
6563 if (!inst
.operands
[1].isreg
)
6564 inst
.operands
[1].reg
= REG_PC
;
6566 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6567 constraint (msb
> 32, _("bit-field extends past end of register"));
6568 /* The instruction encoding stores the LSB and MSB,
6569 not the LSB and width. */
6570 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6571 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6572 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
6573 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
6574 inst
.instruction
|= msb
- 1;
6580 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6581 _("bit-field extends past end of register"));
6582 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6583 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6584 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
6585 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
6586 inst
.instruction
|= inst
.operands
[3].imm
- 1;
6589 /* ARM V5 Thumb BLX (argument parse)
6590 BLX <target_addr> which is BLX(1)
6591 BLX <Rm> which is BLX(2)
6592 Unfortunately, there are two different opcodes for this mnemonic.
6593 So, the insns[].value is not used, and the code here zaps values
6594 into inst.instruction.
6596 ??? How to take advantage of the additional two bits of displacement
6597 available in Thumb32 mode? Need new relocation? */
6602 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
6603 if (inst
.operands
[0].isreg
)
6604 /* We have a register, so this is BLX(2). */
6605 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
6608 /* No register. This must be BLX(1). */
6609 inst
.instruction
= 0xf000e800;
6611 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6612 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
6615 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
6616 inst
.reloc
.pc_rel
= 1;
6626 if (current_it_mask
)
6628 /* Conditional branches inside IT blocks are encoded as unconditional
6631 /* A branch must be the last instruction in an IT block. */
6632 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
6637 if (cond
!= COND_ALWAYS
)
6638 opcode
= T_MNEM_bcond
;
6640 opcode
= inst
.instruction
;
6642 if (unified_syntax
&& inst
.size_req
== 4)
6644 inst
.instruction
= THUMB_OP32(opcode
);
6645 if (cond
== COND_ALWAYS
)
6646 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
6649 assert (cond
!= 0xF);
6650 inst
.instruction
|= cond
<< 22;
6651 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
6656 inst
.instruction
= THUMB_OP16(opcode
);
6657 if (cond
== COND_ALWAYS
)
6658 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
6661 inst
.instruction
|= cond
<< 8;
6662 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
6664 /* Allow section relaxation. */
6665 if (unified_syntax
&& inst
.size_req
!= 2)
6666 inst
.relax
= opcode
;
6669 inst
.reloc
.pc_rel
= 1;
6675 constraint (inst
.cond
!= COND_ALWAYS
,
6676 _("instruction is always unconditional"));
6677 if (inst
.operands
[0].present
)
6679 constraint (inst
.operands
[0].imm
> 255,
6680 _("immediate value out of range"));
6681 inst
.instruction
|= inst
.operands
[0].imm
;
6686 do_t_branch23 (void)
6688 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
6689 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
6690 inst
.reloc
.pc_rel
= 1;
6692 /* If the destination of the branch is a defined symbol which does not have
6693 the THUMB_FUNC attribute, then we must be calling a function which has
6694 the (interfacearm) attribute. We look for the Thumb entry point to that
6695 function and change the branch to refer to that function instead. */
6696 if ( inst
.reloc
.exp
.X_op
== O_symbol
6697 && inst
.reloc
.exp
.X_add_symbol
!= NULL
6698 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
6699 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
6700 inst
.reloc
.exp
.X_add_symbol
=
6701 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
6707 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
6708 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
6709 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6710 should cause the alignment to be checked once it is known. This is
6711 because BX PC only works if the instruction is word aligned. */
6717 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
6718 if (inst
.operands
[0].reg
== REG_PC
)
6719 as_tsktsk (_("use of r15 in bxj is not really useful"));
6721 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6727 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6728 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6729 inst
.instruction
|= inst
.operands
[1].reg
;
6735 constraint (current_it_mask
, BAD_NOT_IT
);
6736 inst
.instruction
|= inst
.operands
[0].imm
;
6742 constraint (current_it_mask
, BAD_NOT_IT
);
6744 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
6745 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
6747 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
6748 inst
.instruction
= 0xf3af8000;
6749 inst
.instruction
|= imod
<< 9;
6750 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
6751 if (inst
.operands
[1].present
)
6752 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
6756 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
6757 && (inst
.operands
[0].imm
& 4),
6758 _("selected processor does not support 'A' form "
6759 "of this instruction"));
6760 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
6761 _("Thumb does not support the 2-argument "
6762 "form of this instruction"));
6763 inst
.instruction
|= inst
.operands
[0].imm
;
6767 /* THUMB CPY instruction (argument parse). */
6772 if (inst
.size_req
== 4)
6774 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
6775 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6776 inst
.instruction
|= inst
.operands
[1].reg
;
6780 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
6781 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
6782 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6789 constraint (current_it_mask
, BAD_NOT_IT
);
6790 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
6791 inst
.instruction
|= inst
.operands
[0].reg
;
6792 inst
.reloc
.pc_rel
= 1;
6793 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
6799 inst
.instruction
|= inst
.operands
[0].imm
;
6805 if (!inst
.operands
[1].present
)
6806 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6807 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6808 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6809 inst
.instruction
|= inst
.operands
[2].reg
;
6815 if (unified_syntax
&& inst
.size_req
== 4)
6816 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6818 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6824 unsigned int cond
= inst
.operands
[0].imm
;
6826 constraint (current_it_mask
, BAD_NOT_IT
);
6827 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
6830 /* If the condition is a negative condition, invert the mask. */
6831 if ((cond
& 0x1) == 0x0)
6833 unsigned int mask
= inst
.instruction
& 0x000f;
6835 if ((mask
& 0x7) == 0)
6836 /* no conversion needed */;
6837 else if ((mask
& 0x3) == 0)
6839 else if ((mask
& 0x1) == 0)
6844 inst
.instruction
&= 0xfff0;
6845 inst
.instruction
|= mask
;
6848 inst
.instruction
|= cond
<< 4;
6854 /* This really doesn't seem worth it. */
6855 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
6856 _("expression too complex"));
6857 constraint (inst
.operands
[1].writeback
,
6858 _("Thumb load/store multiple does not support {reglist}^"));
6862 /* See if we can use a 16-bit instruction. */
6863 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
6864 && inst
.size_req
!= 4
6865 && inst
.operands
[0].reg
<= 7
6866 && !(inst
.operands
[1].imm
& ~0xff)
6867 && (inst
.instruction
== T_MNEM_stmia
6868 ? inst
.operands
[0].writeback
6869 : (inst
.operands
[0].writeback
6870 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
6872 if (inst
.instruction
== T_MNEM_stmia
6873 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6874 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
6875 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6876 inst
.operands
[0].reg
);
6878 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6879 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6880 inst
.instruction
|= inst
.operands
[1].imm
;
6884 if (inst
.operands
[1].imm
& (1 << 13))
6885 as_warn (_("SP should not be in register list"));
6886 if (inst
.instruction
== T_MNEM_stmia
)
6888 if (inst
.operands
[1].imm
& (1 << 15))
6889 as_warn (_("PC should not be in register list"));
6890 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6891 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6892 inst
.operands
[0].reg
);
6896 if (inst
.operands
[1].imm
& (1 << 14)
6897 && inst
.operands
[1].imm
& (1 << 15))
6898 as_warn (_("LR and PC should not both be in register list"));
6899 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6900 && inst
.operands
[0].writeback
)
6901 as_warn (_("base register should not be in register list "
6902 "when written back"));
6904 if (inst
.instruction
< 0xffff)
6905 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6906 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6907 inst
.instruction
|= inst
.operands
[1].imm
;
6908 if (inst
.operands
[0].writeback
)
6909 inst
.instruction
|= WRITE_BACK
;
6914 constraint (inst
.operands
[0].reg
> 7
6915 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
6916 if (inst
.instruction
== T_MNEM_stmia
)
6918 if (!inst
.operands
[0].writeback
)
6919 as_warn (_("this instruction will write back the base register"));
6920 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6921 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
6922 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6923 inst
.operands
[0].reg
);
6927 if (!inst
.operands
[0].writeback
6928 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
6929 as_warn (_("this instruction will write back the base register"));
6930 else if (inst
.operands
[0].writeback
6931 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
6932 as_warn (_("this instruction will not write back the base register"));
6935 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6936 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6937 inst
.instruction
|= inst
.operands
[1].imm
;
6944 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6945 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6946 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6947 || inst
.operands
[1].negative
,
6950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6951 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6952 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
6958 if (!inst
.operands
[1].present
)
6960 constraint (inst
.operands
[0].reg
== REG_LR
,
6961 _("r14 not allowed as first register "
6962 "when second register is omitted"));
6963 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6965 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
6968 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6969 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6970 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6976 unsigned long opcode
;
6979 opcode
= inst
.instruction
;
6982 if (inst
.operands
[1].isreg
6983 && !inst
.operands
[1].writeback
6984 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
6985 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
6987 && inst
.size_req
!= 4)
6989 /* Insn may have a 16-bit form. */
6990 Rn
= inst
.operands
[1].reg
;
6991 if (inst
.operands
[1].immisreg
)
6993 inst
.instruction
= THUMB_OP16 (opcode
);
6995 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
6998 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
6999 && opcode
!= T_MNEM_ldrsb
)
7000 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
7001 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
7008 if (inst
.reloc
.pc_rel
)
7009 opcode
= T_MNEM_ldr_pc2
;
7011 opcode
= T_MNEM_ldr_pc
;
7015 if (opcode
== T_MNEM_ldr
)
7016 opcode
= T_MNEM_ldr_sp
;
7018 opcode
= T_MNEM_str_sp
;
7020 inst
.instruction
= inst
.operands
[0].reg
<< 8;
7024 inst
.instruction
= inst
.operands
[0].reg
;
7025 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7027 inst
.instruction
|= THUMB_OP16 (opcode
);
7028 if (inst
.size_req
== 2)
7029 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
7031 inst
.relax
= opcode
;
7035 /* Definitely a 32-bit variant. */
7036 inst
.instruction
= THUMB_OP32 (opcode
);
7037 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7038 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
7042 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
7044 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
7046 /* Only [Rn,Rm] is acceptable. */
7047 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
7048 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
7049 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
7050 || inst
.operands
[1].negative
,
7051 _("Thumb does not support this addressing mode"));
7052 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7056 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7057 if (!inst
.operands
[1].isreg
)
7058 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
7061 constraint (!inst
.operands
[1].preind
7062 || inst
.operands
[1].shifted
7063 || inst
.operands
[1].writeback
,
7064 _("Thumb does not support this addressing mode"));
7065 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
7067 constraint (inst
.instruction
& 0x0600,
7068 _("byte or halfword not valid for base register"));
7069 constraint (inst
.operands
[1].reg
== REG_PC
7070 && !(inst
.instruction
& THUMB_LOAD_BIT
),
7071 _("r15 based store not allowed"));
7072 constraint (inst
.operands
[1].immisreg
,
7073 _("invalid base register for register offset"));
7075 if (inst
.operands
[1].reg
== REG_PC
)
7076 inst
.instruction
= T_OPCODE_LDR_PC
;
7077 else if (inst
.instruction
& THUMB_LOAD_BIT
)
7078 inst
.instruction
= T_OPCODE_LDR_SP
;
7080 inst
.instruction
= T_OPCODE_STR_SP
;
7082 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7083 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
7087 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
7088 if (!inst
.operands
[1].immisreg
)
7090 /* Immediate offset. */
7091 inst
.instruction
|= inst
.operands
[0].reg
;
7092 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7093 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
7097 /* Register offset. */
7098 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
7099 constraint (inst
.operands
[1].negative
,
7100 _("Thumb does not support this addressing mode"));
7103 switch (inst
.instruction
)
7105 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
7106 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
7107 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
7108 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
7109 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
7110 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
7111 case 0x5600 /* ldrsb */:
7112 case 0x5e00 /* ldrsh */: break;
7116 inst
.instruction
|= inst
.operands
[0].reg
;
7117 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7118 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
7124 if (!inst
.operands
[1].present
)
7126 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7127 constraint (inst
.operands
[0].reg
== REG_LR
,
7128 _("r14 not allowed here"));
7130 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7131 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
7132 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
7139 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7140 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
7146 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7147 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7148 inst
.instruction
|= inst
.operands
[2].reg
;
7149 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7155 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7156 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
7157 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7158 inst
.instruction
|= inst
.operands
[3].reg
;
7166 int r0off
= (inst
.instruction
== T_MNEM_mov
7167 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
7168 unsigned long opcode
;
7170 bfd_boolean low_regs
;
7172 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
7173 opcode
= inst
.instruction
;
7174 if (current_it_mask
)
7175 narrow
= opcode
!= T_MNEM_movs
;
7177 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
7178 if (inst
.size_req
== 4
7179 || inst
.operands
[1].shifted
)
7182 if (!inst
.operands
[1].isreg
)
7184 /* Immediate operand. */
7185 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
7187 if (low_regs
&& narrow
)
7189 inst
.instruction
= THUMB_OP16 (opcode
);
7190 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7191 if (inst
.size_req
== 2)
7192 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
7194 inst
.relax
= opcode
;
7198 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7199 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
7200 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
7201 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
7206 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7207 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
7208 encode_thumb32_shifted_operand (1);
7211 switch (inst
.instruction
)
7214 inst
.instruction
= T_OPCODE_MOV_HR
;
7215 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
7216 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
7217 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7221 /* We know we have low registers at this point.
7222 Generate ADD Rd, Rs, #0. */
7223 inst
.instruction
= T_OPCODE_ADD_I3
;
7224 inst
.instruction
|= inst
.operands
[0].reg
;
7225 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7231 inst
.instruction
= T_OPCODE_CMP_LR
;
7232 inst
.instruction
|= inst
.operands
[0].reg
;
7233 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7237 inst
.instruction
= T_OPCODE_CMP_HR
;
7238 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
7239 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
7240 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7247 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7248 if (inst
.operands
[1].isreg
)
7250 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
7252 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
7253 since a MOV instruction produces unpredictable results. */
7254 if (inst
.instruction
== T_OPCODE_MOV_I8
)
7255 inst
.instruction
= T_OPCODE_ADD_I3
;
7257 inst
.instruction
= T_OPCODE_CMP_LR
;
7259 inst
.instruction
|= inst
.operands
[0].reg
;
7260 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7264 if (inst
.instruction
== T_OPCODE_MOV_I8
)
7265 inst
.instruction
= T_OPCODE_MOV_HR
;
7267 inst
.instruction
= T_OPCODE_CMP_HR
;
7273 constraint (inst
.operands
[0].reg
> 7,
7274 _("only lo regs allowed with immediate"));
7275 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7276 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
7283 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7284 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf000) << 4;
7285 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0800) << 15;
7286 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0700) << 4;
7287 inst
.instruction
|= (inst
.operands
[1].imm
& 0x00ff);
7295 int r0off
= (inst
.instruction
== T_MNEM_mvn
7296 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
7299 if (inst
.size_req
== 4
7300 || inst
.instruction
> 0xffff
7301 || inst
.operands
[1].shifted
7302 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
7304 else if (inst
.instruction
== T_MNEM_cmn
)
7306 else if (THUMB_SETS_FLAGS (inst
.instruction
))
7307 narrow
= (current_it_mask
== 0);
7309 narrow
= (current_it_mask
!= 0);
7311 if (!inst
.operands
[1].isreg
)
7313 /* For an immediate, we always generate a 32-bit opcode;
7314 section relaxation will shrink it later if possible. */
7315 if (inst
.instruction
< 0xffff)
7316 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7317 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
7318 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
7319 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
7323 /* See if we can do this with a 16-bit instruction. */
7326 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7327 inst
.instruction
|= inst
.operands
[0].reg
;
7328 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7332 constraint (inst
.operands
[1].shifted
7333 && inst
.operands
[1].immisreg
,
7334 _("shift must be constant"));
7335 if (inst
.instruction
< 0xffff)
7336 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7337 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
7338 encode_thumb32_shifted_operand (1);
7344 constraint (inst
.instruction
> 0xffff
7345 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
7346 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
7347 _("unshifted register required"));
7348 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
7351 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7352 inst
.instruction
|= inst
.operands
[0].reg
;
7353 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7361 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
7364 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
7365 _("selected processor does not support "
7366 "requested special purpose register"));
7370 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
7371 _("selected processor does not support "
7372 "requested special purpose register %x"));
7373 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7374 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
7375 _("'CPSR' or 'SPSR' expected"));
7378 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7379 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
7380 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
7388 constraint (!inst
.operands
[1].isreg
,
7389 _("Thumb encoding does not support an immediate here"));
7390 flags
= inst
.operands
[0].imm
;
7393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
7394 _("selected processor does not support "
7395 "requested special purpose register"));
7399 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
7400 _("selected processor does not support "
7401 "requested special purpose register"));
7404 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
7405 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
7406 inst
.instruction
|= (flags
& 0xff);
7407 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7413 if (!inst
.operands
[2].present
)
7414 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7416 /* There is no 32-bit MULS and no 16-bit MUL. */
7417 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
7419 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7420 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7421 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7422 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
7426 constraint (!unified_syntax
7427 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
7428 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
7431 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7432 inst
.instruction
|= inst
.operands
[0].reg
;
7434 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7435 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
7436 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
7437 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7439 constraint (1, _("dest must overlap one source register"));
7446 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7447 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
7448 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7449 inst
.instruction
|= inst
.operands
[3].reg
;
7451 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7452 as_tsktsk (_("rdhi and rdlo must be different"));
7460 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
7462 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7463 inst
.instruction
|= inst
.operands
[0].imm
;
7467 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7468 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
7473 constraint (inst
.operands
[0].present
,
7474 _("Thumb does not support NOP with hints"));
7475 inst
.instruction
= 0x46c0;
7486 if (THUMB_SETS_FLAGS (inst
.instruction
))
7487 narrow
= (current_it_mask
== 0);
7489 narrow
= (current_it_mask
!= 0);
7490 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
7492 if (inst
.size_req
== 4)
7497 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7498 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7499 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7503 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7504 inst
.instruction
|= inst
.operands
[0].reg
;
7505 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7510 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
7512 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
7514 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7515 inst
.instruction
|= inst
.operands
[0].reg
;
7516 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7523 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7524 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7525 inst
.instruction
|= inst
.operands
[2].reg
;
7526 if (inst
.operands
[3].present
)
7528 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
7529 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7530 _("expression too complex"));
7531 inst
.instruction
|= (val
& 0x1c) << 10;
7532 inst
.instruction
|= (val
& 0x03) << 6;
7539 if (!inst
.operands
[3].present
)
7540 inst
.instruction
&= ~0x00000020;
7547 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
7551 do_t_push_pop (void)
7555 constraint (inst
.operands
[0].writeback
,
7556 _("push/pop do not support {reglist}^"));
7557 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
7558 _("expression too complex"));
7560 mask
= inst
.operands
[0].imm
;
7561 if ((mask
& ~0xff) == 0)
7562 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7563 else if ((inst
.instruction
== T_MNEM_push
7564 && (mask
& ~0xff) == 1 << REG_LR
)
7565 || (inst
.instruction
== T_MNEM_pop
7566 && (mask
& ~0xff) == 1 << REG_PC
))
7568 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7569 inst
.instruction
|= THUMB_PP_PC_LR
;
7572 else if (unified_syntax
)
7574 if (mask
& (1 << 13))
7575 inst
.error
= _("SP not allowed in register list");
7576 if (inst
.instruction
== T_MNEM_push
)
7578 if (mask
& (1 << 15))
7579 inst
.error
= _("PC not allowed in register list");
7583 if (mask
& (1 << 14)
7584 && mask
& (1 << 15))
7585 inst
.error
= _("LR and PC should not both be in register list");
7587 if ((mask
& (mask
- 1)) == 0)
7589 /* Single register push/pop implemented as str/ldr. */
7590 if (inst
.instruction
== T_MNEM_push
)
7591 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
7593 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
7594 mask
= ffs(mask
) - 1;
7598 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7602 inst
.error
= _("invalid register list to push/pop instruction");
7606 inst
.instruction
|= mask
;
7612 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7613 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7619 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
7620 && inst
.size_req
!= 4)
7622 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7623 inst
.instruction
|= inst
.operands
[0].reg
;
7624 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7626 else if (unified_syntax
)
7628 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7629 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7630 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7631 inst
.instruction
|= inst
.operands
[1].reg
;
7634 inst
.error
= BAD_HIREG
;
7642 Rd
= inst
.operands
[0].reg
;
7643 Rs
= (inst
.operands
[1].present
7644 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
7645 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
7647 inst
.instruction
|= Rd
<< 8;
7648 inst
.instruction
|= Rs
<< 16;
7649 if (!inst
.operands
[2].isreg
)
7651 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
7652 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
7655 encode_thumb32_shifted_operand (2);
7661 constraint (current_it_mask
, BAD_NOT_IT
);
7662 if (inst
.operands
[0].imm
)
7663 inst
.instruction
|= 0x8;
7669 if (!inst
.operands
[1].present
)
7670 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7677 switch (inst
.instruction
)
7680 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
7682 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
7684 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
7686 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
7690 if (THUMB_SETS_FLAGS (inst
.instruction
))
7691 narrow
= (current_it_mask
== 0);
7693 narrow
= (current_it_mask
!= 0);
7694 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
7696 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
7698 if (inst
.operands
[2].isreg
7699 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
7700 || inst
.operands
[2].reg
> 7))
7702 if (inst
.size_req
== 4)
7707 if (inst
.operands
[2].isreg
)
7709 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7710 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7711 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7712 inst
.instruction
|= inst
.operands
[2].reg
;
7716 inst
.operands
[1].shifted
= 1;
7717 inst
.operands
[1].shift_kind
= shift_kind
;
7718 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
7719 ? T_MNEM_movs
: T_MNEM_mov
);
7720 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7721 encode_thumb32_shifted_operand (1);
7722 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7723 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7728 if (inst
.operands
[2].isreg
)
7732 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
7733 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
7734 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
7735 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
7739 inst
.instruction
|= inst
.operands
[0].reg
;
7740 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
7746 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
7747 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
7748 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
7751 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
7752 inst
.instruction
|= inst
.operands
[0].reg
;
7753 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7759 constraint (inst
.operands
[0].reg
> 7
7760 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
7761 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
7763 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
7765 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
7766 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
7767 _("source1 and dest must be same register"));
7769 switch (inst
.instruction
)
7771 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
7772 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
7773 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
7774 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
7778 inst
.instruction
|= inst
.operands
[0].reg
;
7779 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
7783 switch (inst
.instruction
)
7785 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
7786 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
7787 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
7788 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
7791 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
7792 inst
.instruction
|= inst
.operands
[0].reg
;
7793 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7801 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7802 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7803 inst
.instruction
|= inst
.operands
[2].reg
;
7809 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
7810 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7811 _("expression too complex"));
7812 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7813 inst
.instruction
|= (value
& 0xf000) >> 12;
7814 inst
.instruction
|= (value
& 0x0ff0);
7815 inst
.instruction
|= (value
& 0x000f) << 16;
7821 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7822 inst
.instruction
|= inst
.operands
[1].imm
- 1;
7823 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7825 if (inst
.operands
[3].present
)
7827 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7828 _("expression too complex"));
7830 if (inst
.reloc
.exp
.X_add_number
!= 0)
7832 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
7833 inst
.instruction
|= 0x00200000; /* sh bit */
7834 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
7835 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
7837 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7844 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7845 inst
.instruction
|= inst
.operands
[1].imm
- 1;
7846 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7852 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7853 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7854 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7855 || inst
.operands
[2].negative
,
7858 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7859 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7860 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7861 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
7867 if (!inst
.operands
[2].present
)
7868 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
7870 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7871 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7872 || inst
.operands
[0].reg
== inst
.operands
[3].reg
7873 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
7876 inst
.instruction
|= inst
.operands
[0].reg
;
7877 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7878 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7879 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7885 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7886 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7887 inst
.instruction
|= inst
.operands
[2].reg
;
7888 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
7894 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
7895 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
7896 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
7898 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7899 inst
.instruction
|= inst
.operands
[0].reg
;
7900 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7902 else if (unified_syntax
)
7904 if (inst
.instruction
<= 0xffff)
7905 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7906 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7907 inst
.instruction
|= inst
.operands
[1].reg
;
7908 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
7912 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
7913 _("Thumb encoding does not support rotation"));
7914 constraint (1, BAD_HIREG
);
7921 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7929 half
= (inst
.instruction
& 0x10) != 0;
7930 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
7931 constraint (inst
.operands
[0].immisreg
,
7932 _("instruction requires register index"));
7933 constraint (inst
.operands
[0].imm
== 15,
7934 _("PC is not a valid index register"));
7935 constraint (!half
&& inst
.operands
[0].shifted
,
7936 _("instruction does not allow shifted index"));
7937 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
7943 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7944 inst
.instruction
|= inst
.operands
[1].imm
;
7945 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7947 if (inst
.operands
[3].present
)
7949 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7950 _("expression too complex"));
7951 if (inst
.reloc
.exp
.X_add_number
!= 0)
7953 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
7954 inst
.instruction
|= 0x00200000; /* sh bit */
7956 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
7957 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
7959 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7966 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7967 inst
.instruction
|= inst
.operands
[1].imm
;
7968 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7971 /* Overall per-instruction processing. */
7973 /* We need to be able to fix up arbitrary expressions in some statements.
7974 This is so that we can handle symbols that are an arbitrary distance from
7975 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7976 which returns part of an address in a form which will be valid for
7977 a data instruction. We do this by pushing the expression into a symbol
7978 in the expr_section, and creating a fix for that. */
7981 fix_new_arm (fragS
* frag
,
7996 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
8000 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
8005 /* Mark whether the fix is to a THUMB instruction, or an ARM
8007 new_fix
->tc_fix_data
= thumb_mode
;
8010 /* Create a frg for an instruction requiring relaxation. */
8012 output_relax_insn (void)
8019 /* The size of the instruction is unknown, so tie the debug info to the
8020 start of the instruction. */
8021 dwarf2_emit_insn (0);
8024 switch (inst
.reloc
.exp
.X_op
)
8027 sym
= inst
.reloc
.exp
.X_add_symbol
;
8028 offset
= inst
.reloc
.exp
.X_add_number
;
8032 offset
= inst
.reloc
.exp
.X_add_number
;
8035 sym
= make_expr_symbol (&inst
.reloc
.exp
);
8039 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
8040 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
8041 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
8044 /* Write a 32-bit thumb instruction to buf. */
8046 put_thumb32_insn (char * buf
, unsigned long insn
)
8048 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
8049 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
8053 output_inst (const char * str
)
8059 as_bad ("%s -- `%s'", inst
.error
, str
);
8063 output_relax_insn();
8069 to
= frag_more (inst
.size
);
8071 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
8073 assert (inst
.size
== (2 * THUMB_SIZE
));
8074 put_thumb32_insn (to
, inst
.instruction
);
8076 else if (inst
.size
> INSN_SIZE
)
8078 assert (inst
.size
== (2 * INSN_SIZE
));
8079 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
8080 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
8083 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
8085 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
8086 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
8087 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
8091 dwarf2_emit_insn (inst
.size
);
8095 /* Tag values used in struct asm_opcode's tag field. */
8098 OT_unconditional
, /* Instruction cannot be conditionalized.
8099 The ARM condition field is still 0xE. */
8100 OT_unconditionalF
, /* Instruction cannot be conditionalized
8101 and carries 0xF in its ARM condition field. */
8102 OT_csuffix
, /* Instruction takes a conditional suffix. */
8103 OT_cinfix3
, /* Instruction takes a conditional infix,
8104 beginning at character index 3. (In
8105 unified mode, it becomes a suffix.) */
8106 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
8107 character index 3, even in unified mode. Used for
8108 legacy instructions where suffix and infix forms
8109 may be ambiguous. */
8110 OT_csuf_or_in3
, /* Instruction takes either a conditional
8111 suffix or an infix at character index 3. */
8112 OT_odd_infix_unc
, /* This is the unconditional variant of an
8113 instruction that takes a conditional infix
8114 at an unusual position. In unified mode,
8115 this variant will accept a suffix. */
8116 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
8117 are the conditional variants of instructions that
8118 take conditional infixes in unusual positions.
8119 The infix appears at character index
8120 (tag - OT_odd_infix_0). These are not accepted
8124 /* Subroutine of md_assemble, responsible for looking up the primary
8125 opcode from the mnemonic the user wrote. STR points to the
8126 beginning of the mnemonic.
8128 This is not simply a hash table lookup, because of conditional
8129 variants. Most instructions have conditional variants, which are
8130 expressed with a _conditional affix_ to the mnemonic. If we were
8131 to encode each conditional variant as a literal string in the opcode
8132 table, it would have approximately 20,000 entries.
8134 Most mnemonics take this affix as a suffix, and in unified syntax,
8135 'most' is upgraded to 'all'. However, in the divided syntax, some
8136 instructions take the affix as an infix, notably the s-variants of
8137 the arithmetic instructions. Of those instructions, all but six
8138 have the infix appear after the third character of the mnemonic.
8140 Accordingly, the algorithm for looking up primary opcodes given
8143 1. Look up the identifier in the opcode table.
8144 If we find a match, go to step U.
8146 2. Look up the last two characters of the identifier in the
8147 conditions table. If we find a match, look up the first N-2
8148 characters of the identifier in the opcode table. If we
8149 find a match, go to step CE.
8151 3. Look up the fourth and fifth characters of the identifier in
8152 the conditions table. If we find a match, extract those
8153 characters from the identifier, and look up the remaining
8154 characters in the opcode table. If we find a match, go
8159 U. Examine the tag field of the opcode structure, in case this is
8160 one of the six instructions with its conditional infix in an
8161 unusual place. If it is, the tag tells us where to find the
8162 infix; look it up in the conditions table and set inst.cond
8163 accordingly. Otherwise, this is an unconditional instruction.
8164 Again set inst.cond accordingly. Return the opcode structure.
8166 CE. Examine the tag field to make sure this is an instruction that
8167 should receive a conditional suffix. If it is not, fail.
8168 Otherwise, set inst.cond from the suffix we already looked up,
8169 and return the opcode structure.
8171 CM. Examine the tag field to make sure this is an instruction that
8172 should receive a conditional infix after the third character.
8173 If it is not, fail. Otherwise, undo the edits to the current
8174 line of input and proceed as for case CE. */
8176 static const struct asm_opcode
*
8177 opcode_lookup (char **str
)
8181 const struct asm_opcode
*opcode
;
8182 const struct asm_cond
*cond
;
8185 /* Scan up to the end of the mnemonic, which must end in white space,
8186 '.' (in unified mode only), or end of string. */
8187 for (base
= end
= *str
; *end
!= '\0'; end
++)
8188 if (*end
== ' ' || (unified_syntax
&& *end
== '.'))
8194 /* Handle a possible width suffix. */
8197 if (end
[1] == 'w' && (end
[2] == ' ' || end
[2] == '\0'))
8199 else if (end
[1] == 'n' && (end
[2] == ' ' || end
[2] == '\0'))
8209 /* Look for unaffixed or special-case affixed mnemonic. */
8210 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
8214 if (opcode
->tag
< OT_odd_infix_0
)
8216 inst
.cond
= COND_ALWAYS
;
8221 as_warn (_("conditional infixes are deprecated in unified syntax"));
8222 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
8223 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
8226 inst
.cond
= cond
->value
;
8230 /* Cannot have a conditional suffix on a mnemonic of less than two
8235 /* Look for suffixed mnemonic. */
8237 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
8238 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
8242 switch (opcode
->tag
)
8244 case OT_cinfix3_legacy
:
8245 /* Ignore conditional suffixes matched on infix only mnemonics. */
8249 case OT_odd_infix_unc
:
8250 if (!unified_syntax
)
8252 /* else fall through */
8255 case OT_csuf_or_in3
:
8256 inst
.cond
= cond
->value
;
8259 case OT_unconditional
:
8260 case OT_unconditionalF
:
8263 inst
.cond
= cond
->value
;
8267 /* delayed diagnostic */
8268 inst
.error
= BAD_COND
;
8269 inst
.cond
= COND_ALWAYS
;
8278 /* Cannot have a usual-position infix on a mnemonic of less than
8279 six characters (five would be a suffix). */
8283 /* Look for infixed mnemonic in the usual position. */
8285 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
8289 memcpy (save
, affix
, 2);
8290 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
8291 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
8292 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
8293 memcpy (affix
, save
, 2);
8295 if (opcode
&& (opcode
->tag
== OT_cinfix3
|| opcode
->tag
== OT_csuf_or_in3
8296 || opcode
->tag
== OT_cinfix3_legacy
))
8299 if (unified_syntax
&& opcode
->tag
== OT_cinfix3
)
8300 as_warn (_("conditional infixes are deprecated in unified syntax"));
8302 inst
.cond
= cond
->value
;
8310 md_assemble (char *str
)
8313 const struct asm_opcode
* opcode
;
8315 /* Align the previous label if needed. */
8316 if (last_label_seen
!= NULL
)
8318 symbol_set_frag (last_label_seen
, frag_now
);
8319 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
8320 S_SET_SEGMENT (last_label_seen
, now_seg
);
8323 memset (&inst
, '\0', sizeof (inst
));
8324 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8326 opcode
= opcode_lookup (&p
);
8329 /* It wasn't an instruction, but it might be a register alias of
8330 the form alias .req reg. */
8331 if (!create_register_alias (str
, p
))
8332 as_bad (_("bad instruction `%s'"), str
);
8339 arm_feature_set variant
;
8341 variant
= cpu_variant
;
8342 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
8343 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
8344 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
8345 /* Check that this instruction is supported for this CPU. */
8346 if (!opcode
->tvariant
8348 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
8350 as_bad (_("selected processor does not support `%s'"), str
);
8353 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
8354 && opcode
->tencode
!= do_t_branch
)
8356 as_bad (_("Thumb does not support conditional execution"));
8360 /* Check conditional suffixes. */
8361 if (current_it_mask
)
8364 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
8365 current_it_mask
<<= 1;
8366 current_it_mask
&= 0x1f;
8367 /* The BKPT instruction is unconditional even in an IT block. */
8369 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
8371 as_bad (_("incorrect condition in IT block"));
8375 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
8377 as_bad (_("thumb conditional instrunction not in IT block"));
8381 mapping_state (MAP_THUMB
);
8382 inst
.instruction
= opcode
->tvalue
;
8384 if (!parse_operands (p
, opcode
->operands
))
8387 /* Clear current_it_mask at the end of an IT block. */
8388 if (current_it_mask
== 0x10)
8389 current_it_mask
= 0;
8391 if (!(inst
.error
|| inst
.relax
))
8393 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
8394 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
8395 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
8397 as_bad (_("cannot honor width suffix -- `%s'"), str
);
8401 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8403 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
8404 set those bits when Thumb-2 32-bit instuctions are seen. ie.
8405 anything other than bl/blx.
8406 This is overly pessimistic for relaxable instructions. */
8407 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
8409 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8414 /* Check that this instruction is supported for this CPU. */
8415 if (!opcode
->avariant
||
8416 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
8418 as_bad (_("selected processor does not support `%s'"), str
);
8423 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
8427 mapping_state (MAP_ARM
);
8428 inst
.instruction
= opcode
->avalue
;
8429 if (opcode
->tag
== OT_unconditionalF
)
8430 inst
.instruction
|= 0xF << 28;
8432 inst
.instruction
|= inst
.cond
<< 28;
8433 inst
.size
= INSN_SIZE
;
8434 if (!parse_operands (p
, opcode
->operands
))
8436 /* Arm mode bx is marked as both v4T and v5 because it's still required
8437 on a hypothetical non-thumb v5 core. */
8438 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
8439 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
8440 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
8442 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8448 /* Various frobbings of labels and their addresses. */
8451 arm_start_line_hook (void)
8453 last_label_seen
= NULL
;
8457 arm_frob_label (symbolS
* sym
)
8459 last_label_seen
= sym
;
8461 ARM_SET_THUMB (sym
, thumb_mode
);
8463 #if defined OBJ_COFF || defined OBJ_ELF
8464 ARM_SET_INTERWORK (sym
, support_interwork
);
8467 /* Note - do not allow local symbols (.Lxxx) to be labeled
8468 as Thumb functions. This is because these labels, whilst
8469 they exist inside Thumb code, are not the entry points for
8470 possible ARM->Thumb calls. Also, these labels can be used
8471 as part of a computed goto or switch statement. eg gcc
8472 can generate code that looks like this:
8484 The first instruction loads the address of the jump table.
8485 The second instruction converts a table index into a byte offset.
8486 The third instruction gets the jump address out of the table.
8487 The fourth instruction performs the jump.
8489 If the address stored at .Laaa is that of a symbol which has the
8490 Thumb_Func bit set, then the linker will arrange for this address
8491 to have the bottom bit set, which in turn would mean that the
8492 address computation performed by the third instruction would end
8493 up with the bottom bit set. Since the ARM is capable of unaligned
8494 word loads, the instruction would then load the incorrect address
8495 out of the jump table, and chaos would ensue. */
8496 if (label_is_thumb_function_name
8497 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
8498 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
8500 /* When the address of a Thumb function is taken the bottom
8501 bit of that address should be set. This will allow
8502 interworking between Arm and Thumb functions to work
8505 THUMB_SET_FUNC (sym
, 1);
8507 label_is_thumb_function_name
= FALSE
;
8511 dwarf2_emit_label (sym
);
8516 arm_data_in_code (void)
8518 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
8520 *input_line_pointer
= '/';
8521 input_line_pointer
+= 5;
8522 *input_line_pointer
= 0;
8530 arm_canonicalize_symbol_name (char * name
)
8534 if (thumb_mode
&& (len
= strlen (name
)) > 5
8535 && streq (name
+ len
- 5, "/data"))
8536 *(name
+ len
- 5) = 0;
8541 /* Table of all register names defined by default. The user can
8542 define additional names with .req. Note that all register names
8543 should appear in both upper and lowercase variants. Some registers
8544 also have mixed-case names. */
8546 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
8547 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8548 #define REGSET(p,t) \
8549 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8550 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8551 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8552 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8554 static const struct reg_entry reg_names
[] =
8556 /* ARM integer registers. */
8557 REGSET(r
, RN
), REGSET(R
, RN
),
8559 /* ATPCS synonyms. */
8560 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
8561 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
8562 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
8564 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
8565 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
8566 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
8568 /* Well-known aliases. */
8569 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
8570 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
8572 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
8573 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
8575 /* Coprocessor numbers. */
8576 REGSET(p
, CP
), REGSET(P
, CP
),
8578 /* Coprocessor register numbers. The "cr" variants are for backward
8580 REGSET(c
, CN
), REGSET(C
, CN
),
8581 REGSET(cr
, CN
), REGSET(CR
, CN
),
8583 /* FPA registers. */
8584 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
8585 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
8587 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
8588 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
8590 /* VFP SP registers. */
8592 REGNUM(s
,16,VFS
), REGNUM(s
,17,VFS
), REGNUM(s
,18,VFS
), REGNUM(s
,19,VFS
),
8593 REGNUM(s
,20,VFS
), REGNUM(s
,21,VFS
), REGNUM(s
,22,VFS
), REGNUM(s
,23,VFS
),
8594 REGNUM(s
,24,VFS
), REGNUM(s
,25,VFS
), REGNUM(s
,26,VFS
), REGNUM(s
,27,VFS
),
8595 REGNUM(s
,28,VFS
), REGNUM(s
,29,VFS
), REGNUM(s
,30,VFS
), REGNUM(s
,31,VFS
),
8598 REGNUM(S
,16,VFS
), REGNUM(S
,17,VFS
), REGNUM(S
,18,VFS
), REGNUM(S
,19,VFS
),
8599 REGNUM(S
,20,VFS
), REGNUM(S
,21,VFS
), REGNUM(S
,22,VFS
), REGNUM(S
,23,VFS
),
8600 REGNUM(S
,24,VFS
), REGNUM(S
,25,VFS
), REGNUM(S
,26,VFS
), REGNUM(S
,27,VFS
),
8601 REGNUM(S
,28,VFS
), REGNUM(S
,29,VFS
), REGNUM(S
,30,VFS
), REGNUM(S
,31,VFS
),
8603 /* VFP DP Registers. */
8604 REGSET(d
,VFD
), REGSET(D
,VFS
),
8606 /* VFP control registers. */
8607 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
8608 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
8610 /* Maverick DSP coprocessor registers. */
8611 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
8612 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
8614 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
8615 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
8616 REGDEF(dspsc
,0,DSPSC
),
8618 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
8619 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
8620 REGDEF(DSPSC
,0,DSPSC
),
8622 /* iWMMXt data registers - p0, c0-15. */
8623 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
8625 /* iWMMXt control registers - p1, c0-3. */
8626 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
8627 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
8628 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
8629 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
8631 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
8632 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
8633 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
8634 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
8635 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
8637 /* XScale accumulator registers. */
8638 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
8644 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
8645 within psr_required_here. */
8646 static const struct asm_psr psrs
[] =
8648 /* Backward compatibility notation. Note that "all" is no longer
8649 truly all possible PSR bits. */
8650 {"all", PSR_c
| PSR_f
},
8654 /* Individual flags. */
8659 /* Combinations of flags. */
8660 {"fs", PSR_f
| PSR_s
},
8661 {"fx", PSR_f
| PSR_x
},
8662 {"fc", PSR_f
| PSR_c
},
8663 {"sf", PSR_s
| PSR_f
},
8664 {"sx", PSR_s
| PSR_x
},
8665 {"sc", PSR_s
| PSR_c
},
8666 {"xf", PSR_x
| PSR_f
},
8667 {"xs", PSR_x
| PSR_s
},
8668 {"xc", PSR_x
| PSR_c
},
8669 {"cf", PSR_c
| PSR_f
},
8670 {"cs", PSR_c
| PSR_s
},
8671 {"cx", PSR_c
| PSR_x
},
8672 {"fsx", PSR_f
| PSR_s
| PSR_x
},
8673 {"fsc", PSR_f
| PSR_s
| PSR_c
},
8674 {"fxs", PSR_f
| PSR_x
| PSR_s
},
8675 {"fxc", PSR_f
| PSR_x
| PSR_c
},
8676 {"fcs", PSR_f
| PSR_c
| PSR_s
},
8677 {"fcx", PSR_f
| PSR_c
| PSR_x
},
8678 {"sfx", PSR_s
| PSR_f
| PSR_x
},
8679 {"sfc", PSR_s
| PSR_f
| PSR_c
},
8680 {"sxf", PSR_s
| PSR_x
| PSR_f
},
8681 {"sxc", PSR_s
| PSR_x
| PSR_c
},
8682 {"scf", PSR_s
| PSR_c
| PSR_f
},
8683 {"scx", PSR_s
| PSR_c
| PSR_x
},
8684 {"xfs", PSR_x
| PSR_f
| PSR_s
},
8685 {"xfc", PSR_x
| PSR_f
| PSR_c
},
8686 {"xsf", PSR_x
| PSR_s
| PSR_f
},
8687 {"xsc", PSR_x
| PSR_s
| PSR_c
},
8688 {"xcf", PSR_x
| PSR_c
| PSR_f
},
8689 {"xcs", PSR_x
| PSR_c
| PSR_s
},
8690 {"cfs", PSR_c
| PSR_f
| PSR_s
},
8691 {"cfx", PSR_c
| PSR_f
| PSR_x
},
8692 {"csf", PSR_c
| PSR_s
| PSR_f
},
8693 {"csx", PSR_c
| PSR_s
| PSR_x
},
8694 {"cxf", PSR_c
| PSR_x
| PSR_f
},
8695 {"cxs", PSR_c
| PSR_x
| PSR_s
},
8696 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
8697 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
8698 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
8699 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
8700 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
8701 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
8702 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
8703 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
8704 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
8705 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
8706 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
8707 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
8708 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
8709 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
8710 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
8711 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
8712 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
8713 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
8714 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
8715 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
8716 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
8717 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
8718 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
8719 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
8722 /* Table of V7M psr names. */
8723 static const struct asm_psr v7m_psrs
[] =
8736 {"basepri_max", 18},
8741 /* Table of all shift-in-operand names. */
8742 static const struct asm_shift_name shift_names
[] =
8744 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
8745 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
8746 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
8747 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
8748 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
8749 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
8752 /* Table of all explicit relocation names. */
8754 static struct reloc_entry reloc_names
[] =
8756 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
8757 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
8758 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
8759 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
8760 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
8761 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
8762 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
8763 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
8764 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
8765 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
8766 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
8770 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
8771 static const struct asm_cond conds
[] =
8775 {"cs", 0x2}, {"hs", 0x2},
8776 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8790 static struct asm_barrier_opt barrier_opt_names
[] =
8798 /* Table of ARM-format instructions. */
8800 /* Macros for gluing together operand strings. N.B. In all cases
8801 other than OPS0, the trailing OP_stop comes from default
8802 zero-initialization of the unspecified elements of the array. */
8803 #define OPS0() { OP_stop, }
8804 #define OPS1(a) { OP_##a, }
8805 #define OPS2(a,b) { OP_##a,OP_##b, }
8806 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8807 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8808 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8809 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8811 /* These macros abstract out the exact format of the mnemonic table and
8812 save some repeated characters. */
8814 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8815 #define TxCE(mnem, op, top, nops, ops, ae, te) \
8816 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
8817 THUMB_VARIANT, do_##ae, do_##te }
8819 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8820 a T_MNEM_xyz enumerator. */
8821 #define TCE(mnem, aop, top, nops, ops, ae, te) \
8822 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8823 #define tCE(mnem, aop, top, nops, ops, ae, te) \
8824 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8826 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8827 infix after the third character. */
8828 #define TxC3(mnem, op, top, nops, ops, ae, te) \
8829 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
8830 THUMB_VARIANT, do_##ae, do_##te }
8831 #define TC3(mnem, aop, top, nops, ops, ae, te) \
8832 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8833 #define tC3(mnem, aop, top, nops, ops, ae, te) \
8834 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8836 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8837 appear in the condition table. */
8838 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8839 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8840 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
8842 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8843 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8844 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8845 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8846 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8847 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8848 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8849 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8850 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8851 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8852 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8853 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8854 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8855 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8856 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8857 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8858 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8859 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8860 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8861 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8863 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8864 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8865 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8866 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8868 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8869 field is still 0xE. Many of the Thumb variants can be executed
8870 conditionally, so this is checked separately. */
8871 #define TUE(mnem, op, top, nops, ops, ae, te) \
8872 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8873 THUMB_VARIANT, do_##ae, do_##te }
8875 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8876 condition code field. */
8877 #define TUF(mnem, op, top, nops, ops, ae, te) \
8878 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8879 THUMB_VARIANT, do_##ae, do_##te }
8881 /* ARM-only variants of all the above. */
8882 #define CE(mnem, op, nops, ops, ae) \
8883 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8885 #define C3(mnem, op, nops, ops, ae) \
8886 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8888 /* Legacy mnemonics that always have conditional infix after the third
8890 #define CL(mnem, op, nops, ops, ae) \
8891 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8892 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8894 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
8895 #define cCE(mnem, op, nops, ops, ae) \
8896 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8898 /* Legacy coprocessor instructions where conditional infix and conditional
8899 suffix are ambiguous. For consistency this includes all FPA instructions,
8900 not just the potentially ambiguous ones. */
8901 #define cCL(mnem, op, nops, ops, ae) \
8902 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8903 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8905 /* Coprocessor, takes either a suffix or a position-3 infix
8906 (for an FPA corner case). */
8907 #define C3E(mnem, op, nops, ops, ae) \
8908 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
8909 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8911 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8912 { #m1 #m2 #m3, OPS##nops ops, \
8913 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8914 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8916 #define CM(m1, m2, op, nops, ops, ae) \
8917 xCM_(m1, , m2, op, nops, ops, ae), \
8918 xCM_(m1, eq, m2, op, nops, ops, ae), \
8919 xCM_(m1, ne, m2, op, nops, ops, ae), \
8920 xCM_(m1, cs, m2, op, nops, ops, ae), \
8921 xCM_(m1, hs, m2, op, nops, ops, ae), \
8922 xCM_(m1, cc, m2, op, nops, ops, ae), \
8923 xCM_(m1, ul, m2, op, nops, ops, ae), \
8924 xCM_(m1, lo, m2, op, nops, ops, ae), \
8925 xCM_(m1, mi, m2, op, nops, ops, ae), \
8926 xCM_(m1, pl, m2, op, nops, ops, ae), \
8927 xCM_(m1, vs, m2, op, nops, ops, ae), \
8928 xCM_(m1, vc, m2, op, nops, ops, ae), \
8929 xCM_(m1, hi, m2, op, nops, ops, ae), \
8930 xCM_(m1, ls, m2, op, nops, ops, ae), \
8931 xCM_(m1, ge, m2, op, nops, ops, ae), \
8932 xCM_(m1, lt, m2, op, nops, ops, ae), \
8933 xCM_(m1, gt, m2, op, nops, ops, ae), \
8934 xCM_(m1, le, m2, op, nops, ops, ae), \
8935 xCM_(m1, al, m2, op, nops, ops, ae)
8937 #define UE(mnem, op, nops, ops, ae) \
8938 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8940 #define UF(mnem, op, nops, ops, ae) \
8941 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8945 /* Thumb-only, unconditional. */
8946 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8948 static const struct asm_opcode insns
[] =
8950 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
8951 #define THUMB_VARIANT &arm_ext_v4t
8952 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8953 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8954 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8955 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8956 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8957 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8958 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8959 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8960 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8961 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8962 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8963 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8964 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8965 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8966 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8967 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8969 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8970 for setting PSR flag bits. They are obsolete in V6 and do not
8971 have Thumb equivalents. */
8972 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8973 tC3(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8974 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
8975 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
8976 tC3(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
8977 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
8978 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8979 tC3(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8980 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
8982 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
8983 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
8984 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
8985 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
8987 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8988 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8989 tCE(str
, 4000000, str
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8990 tC3(strb
, 4400000, strb
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8992 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8993 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8994 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8995 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8996 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8997 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8999 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
9000 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
9001 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
9002 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
9005 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
9006 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
9007 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
9009 /* Thumb-compatibility pseudo ops. */
9010 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
9011 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
9012 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
9013 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
9014 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
9015 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
9016 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
9017 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
9018 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
9019 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
9020 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
9021 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
9023 #undef THUMB_VARIANT
9024 #define THUMB_VARIANT &arm_ext_v6
9025 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
9027 /* V1 instructions with no Thumb analogue prior to V6T2. */
9028 #undef THUMB_VARIANT
9029 #define THUMB_VARIANT &arm_ext_v6t2
9030 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
9031 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
9032 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
9033 TC3(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
9034 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
9036 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
9037 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
9038 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
9039 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
9041 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
9042 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
9044 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
9045 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
9047 /* V1 instructions with no Thumb analogue at all. */
9048 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
9049 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
9051 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
9052 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
9053 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
9054 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
9055 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
9056 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
9057 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
9058 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
9061 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
9062 #undef THUMB_VARIANT
9063 #define THUMB_VARIANT &arm_ext_v4t
9064 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
9065 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
9067 #undef THUMB_VARIANT
9068 #define THUMB_VARIANT &arm_ext_v6t2
9069 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
9070 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
9072 /* Generic coprocessor instructions. */
9073 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
9074 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
9075 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
9076 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
9077 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
9078 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
9079 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
9082 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
9083 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
9084 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
9087 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
9088 TCE(mrs
, 10f0000
, f3ef8000
, 2, (RR
, PSR
), mrs
, t_mrs
),
9089 TCE(msr
, 120f000
, f3808000
, 2, (PSR
, RR_EXi
), msr
, t_msr
),
9092 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
9093 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
9094 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
9095 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
9096 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
9097 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
9098 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
9099 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
9100 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
9103 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
9104 #undef THUMB_VARIANT
9105 #define THUMB_VARIANT &arm_ext_v4t
9106 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
9107 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
9108 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
9109 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
9110 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
9111 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
9114 #define ARM_VARIANT &arm_ext_v4t_5
9115 /* ARM Architecture 4T. */
9116 /* Note: bx (and blx) are required on V5, even if the processor does
9117 not support Thumb. */
9118 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
9121 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
9122 #undef THUMB_VARIANT
9123 #define THUMB_VARIANT &arm_ext_v5t
9124 /* Note: blx has 2 variants; the .value coded here is for
9125 BLX(2). Only this variant has conditional execution. */
9126 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
9127 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
9129 #undef THUMB_VARIANT
9130 #define THUMB_VARIANT &arm_ext_v6t2
9131 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
9132 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
9133 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
9134 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
9135 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
9136 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
9137 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
9138 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
9141 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
9142 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
9143 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
9144 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
9145 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
9147 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
9148 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
9150 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
9151 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
9152 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
9153 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
9155 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9156 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9157 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9158 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9160 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9161 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9163 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
9164 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
9165 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
9166 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
9169 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
9170 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
9171 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDR
), ldrd
, t_ldstd
),
9172 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDR
), ldrd
, t_ldstd
),
9174 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
9175 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
9178 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
9179 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
9182 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
9183 #undef THUMB_VARIANT
9184 #define THUMB_VARIANT &arm_ext_v6
9185 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
9186 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
9187 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
9188 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
9189 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
9190 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
9191 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
9192 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
9193 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
9194 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
9196 #undef THUMB_VARIANT
9197 #define THUMB_VARIANT &arm_ext_v6t2
9198 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
9199 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
9200 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
9202 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
9203 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
9205 /* ARM V6 not included in V7M (eg. integer SIMD). */
9206 #undef THUMB_VARIANT
9207 #define THUMB_VARIANT &arm_ext_v6_notm
9208 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
9209 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
9210 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
9211 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9212 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9213 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9214 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9215 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9216 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9217 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9218 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9219 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9220 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9221 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9222 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9223 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9224 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9225 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9226 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9227 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9228 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9229 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9230 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9231 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9232 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9233 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9234 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9235 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9236 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9237 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9238 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9239 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9240 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9241 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9242 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9243 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9244 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9245 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9246 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9247 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
9248 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
9249 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
9250 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
9251 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
9252 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
9253 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
9254 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
9255 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9256 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9257 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9258 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
9259 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9260 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9261 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9262 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
9263 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9264 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9265 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9266 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
9267 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
9268 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9269 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9270 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
9271 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
9272 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9273 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9274 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9275 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9276 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9277 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9278 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9279 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9280 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9281 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9282 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
9283 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
9284 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
9285 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
9286 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
9287 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
9288 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
9289 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9290 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9291 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
9294 #define ARM_VARIANT &arm_ext_v6k
9295 #undef THUMB_VARIANT
9296 #define THUMB_VARIANT &arm_ext_v6k
9297 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
9298 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
9299 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
9300 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
9302 #undef THUMB_VARIANT
9303 #define THUMB_VARIANT &arm_ext_v6_notm
9304 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
9305 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
9307 #undef THUMB_VARIANT
9308 #define THUMB_VARIANT &arm_ext_v6t2
9309 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
9310 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
9311 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
9312 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
9313 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
9316 #define ARM_VARIANT &arm_ext_v6z
9317 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
9320 #define ARM_VARIANT &arm_ext_v6t2
9321 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
9322 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
9323 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
9324 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
9326 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
9327 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, Iffff
), mov16
, t_mov16
),
9328 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, Iffff
), mov16
, t_mov16
),
9329 TCE(rbit
, 3ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
9331 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
9332 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
9333 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
9334 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
9336 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
9337 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
9338 /* ARM does not really have an IT instruction. */
9339 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
9340 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
9341 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
9342 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
9343 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
9344 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
9345 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
9346 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
9347 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
9348 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
9349 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
9350 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
9351 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
9352 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
9353 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
9355 /* Thumb2 only instructions. */
9357 #define ARM_VARIANT NULL
9359 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
9360 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
9361 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
9362 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
9364 /* Thumb-2 hardware division instructions (R and M profiles only). */
9365 #undef THUMB_VARIANT
9366 #define THUMB_VARIANT &arm_ext_div
9367 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
9368 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
9370 /* ARM V7 instructions. */
9372 #define ARM_VARIANT &arm_ext_v7
9373 #undef THUMB_VARIANT
9374 #define THUMB_VARIANT &arm_ext_v7
9375 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
9376 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
9377 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
9378 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
9379 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
9382 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
9383 cCE(wfs
, e200110
, 1, (RR
), rd
),
9384 cCE(rfs
, e300110
, 1, (RR
), rd
),
9385 cCE(wfc
, e400110
, 1, (RR
), rd
),
9386 cCE(rfc
, e500110
, 1, (RR
), rd
),
9388 cCL(ldfs
, c100100
, 2, (RF
, ADDR
), rd_cpaddr
),
9389 cCL(ldfd
, c108100
, 2, (RF
, ADDR
), rd_cpaddr
),
9390 cCL(ldfe
, c500100
, 2, (RF
, ADDR
), rd_cpaddr
),
9391 cCL(ldfp
, c508100
, 2, (RF
, ADDR
), rd_cpaddr
),
9393 cCL(stfs
, c000100
, 2, (RF
, ADDR
), rd_cpaddr
),
9394 cCL(stfd
, c008100
, 2, (RF
, ADDR
), rd_cpaddr
),
9395 cCL(stfe
, c400100
, 2, (RF
, ADDR
), rd_cpaddr
),
9396 cCL(stfp
, c408100
, 2, (RF
, ADDR
), rd_cpaddr
),
9398 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
9399 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
9400 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
9401 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
9402 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
9403 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
9404 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
9405 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
9406 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
9407 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
9408 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
9409 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
9411 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
9412 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
9413 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
9414 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
9415 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
9416 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
9417 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
9418 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
9419 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
9420 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
9421 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
9422 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
9424 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
9425 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
9426 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
9427 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
9428 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
9429 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
9430 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
9431 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
9432 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
9433 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
9434 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
9435 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
9437 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
9438 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
9439 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
9440 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
9441 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
9442 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
9443 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
9444 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
9445 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
9446 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
9447 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
9448 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
9450 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
9451 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
9452 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
9453 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
9454 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
9455 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
9456 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
9457 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
9458 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
9459 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
9460 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
9461 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
9463 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
9464 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
9465 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
9466 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
9467 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
9468 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
9469 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
9470 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
9471 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
9472 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
9473 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
9474 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
9476 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
9477 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
9478 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
9479 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
9480 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
9481 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
9482 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
9483 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
9484 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
9485 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
9486 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
9487 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
9489 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
9490 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
9491 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
9492 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
9493 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
9494 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
9495 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
9496 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
9497 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
9498 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
9499 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
9500 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
9502 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
9503 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
9504 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
9505 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
9506 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
9507 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
9508 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
9509 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
9510 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
9511 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
9512 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
9513 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
9515 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
9516 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
9517 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
9518 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
9519 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
9520 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
9521 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
9522 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
9523 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
9524 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
9525 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
9526 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
9528 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
9529 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
9530 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
9531 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
9532 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
9533 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
9534 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
9535 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
9536 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
9537 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
9538 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
9539 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
9541 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
9542 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
9543 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
9544 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
9545 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
9546 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
9547 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
9548 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
9549 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
9550 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
9551 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
9552 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
9554 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
9555 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
9556 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
9557 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
9558 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
9559 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
9560 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
9561 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
9562 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
9563 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
9564 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
9565 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
9567 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
9568 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
9569 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
9570 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
9571 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
9572 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
9573 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
9574 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
9575 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
9576 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
9577 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
9578 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
9580 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
9581 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
9582 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
9583 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
9584 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
9585 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
9586 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
9587 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
9588 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
9589 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
9590 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
9591 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
9593 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
9594 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
9595 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
9596 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
9597 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
9598 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
9599 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
9600 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
9601 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
9602 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
9603 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
9604 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
9606 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9607 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9608 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9609 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9610 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9611 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9612 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9613 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9614 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9615 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9616 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9617 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9619 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9620 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9621 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9622 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9623 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9624 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9625 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9626 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9627 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9628 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9629 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9630 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9632 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9633 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9634 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9635 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9636 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9637 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9638 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9639 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9640 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9641 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9642 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9643 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9645 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9646 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9647 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9648 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9649 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9650 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9651 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9652 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9653 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9654 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9655 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9656 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9658 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9659 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9660 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9661 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9662 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9663 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9664 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9665 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9666 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9667 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9668 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9669 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9671 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9672 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9673 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9674 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9675 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9676 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9677 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9678 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9679 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9680 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9681 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9682 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9684 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9685 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9686 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9687 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9688 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9689 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9690 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9691 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9692 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9693 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9694 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9695 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9697 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9698 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9699 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9700 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9701 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9702 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9703 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9704 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9705 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9706 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9707 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9708 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9710 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9711 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9712 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9713 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9714 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9715 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9716 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9717 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9718 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9719 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9720 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9721 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9723 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9724 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9725 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9726 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9727 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9728 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9729 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9730 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9731 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9732 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9733 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9734 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9736 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9737 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9738 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9739 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9740 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9741 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9742 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9743 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9744 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9745 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9746 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9747 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9749 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9750 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9751 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9752 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9753 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9754 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9755 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9756 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9757 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9758 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9759 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9760 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9762 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9763 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9764 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9765 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9766 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9767 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9768 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9769 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9770 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9771 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9772 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9773 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9775 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9776 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9777 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9778 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9780 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
9781 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
9782 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
9783 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
9784 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
9785 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
9786 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
9787 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
9788 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
9789 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
9790 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
9791 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
9793 /* The implementation of the FIX instruction is broken on some
9794 assemblers, in that it accepts a precision specifier as well as a
9795 rounding specifier, despite the fact that this is meaningless.
9796 To be more compatible, we accept it as well, though of course it
9797 does not set any bits. */
9798 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
9799 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
9800 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
9801 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
9802 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
9803 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
9804 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
9805 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
9806 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
9807 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
9808 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
9809 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
9810 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
9812 /* Instructions that were new with the real FPA, call them V2. */
9814 #define ARM_VARIANT &fpu_fpa_ext_v2
9815 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9816 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9817 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9818 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9819 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9820 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9823 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
9824 /* Moves and type conversions. */
9825 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9826 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
9827 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
9828 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
9829 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9830 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9831 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9832 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9833 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9834 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9835 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
9836 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
9838 /* Memory operations. */
9839 cCE(flds
, d100a00
, 2, (RVS
, ADDR
), vfp_sp_ldst
),
9840 cCE(fsts
, d000a00
, 2, (RVS
, ADDR
), vfp_sp_ldst
),
9841 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9842 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9843 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9844 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9845 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9846 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9847 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9848 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9849 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9850 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9851 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9852 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9853 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9854 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9855 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9856 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9858 /* Monadic operations. */
9859 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9860 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9861 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9863 /* Dyadic operations. */
9864 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9865 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9866 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9867 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9868 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9869 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9870 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9871 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9872 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9875 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9876 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
9877 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9878 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
9881 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
9882 /* Moves and type conversions. */
9883 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), rd_rm
),
9884 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
9885 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9886 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), rn_rd
),
9887 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), rn_rd
),
9888 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), rd_rn
),
9889 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), rd_rn
),
9890 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
9891 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
9892 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9893 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9894 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9895 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9897 /* Memory operations. */
9898 cCE(fldd
, d100b00
, 2, (RVD
, ADDR
), vfp_dp_ldst
),
9899 cCE(fstd
, d000b00
, 2, (RVD
, ADDR
), vfp_dp_ldst
),
9900 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9901 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9902 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9903 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9904 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9905 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9906 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9907 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9909 /* Monadic operations. */
9910 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), rd_rm
),
9911 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), rd_rm
),
9912 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), rd_rm
),
9914 /* Dyadic operations. */
9915 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9916 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9917 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9918 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9919 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9920 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9921 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9922 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9923 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9926 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), rd_rm
),
9927 cCE(fcmpzd
, eb50b40
, 1, (RVD
), rd
),
9928 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), rd_rm
),
9929 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), rd
),
9932 #define ARM_VARIANT &fpu_vfp_ext_v2
9933 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
9934 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
9935 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), rm_rd_rn
),
9936 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), rd_rn_rm
),
9939 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
9940 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9941 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9942 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9943 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9944 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9945 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9946 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
9947 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
9950 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
9951 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
9952 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
9953 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
9954 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
9955 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
9956 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
9957 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
9958 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
9959 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
9960 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9961 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9962 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9963 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9964 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9965 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9966 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9967 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9968 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9969 cCE(tmcr
, e000110
, 2, (RIWC
, RR
), rn_rd
),
9970 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
9971 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9972 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9973 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9974 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9975 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9976 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9977 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
9978 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
9979 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
9980 cCE(tmrc
, e100110
, 2, (RR
, RIWC
), rd_rn
),
9981 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
9982 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
9983 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
9984 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
9985 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9986 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9987 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9988 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9989 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9990 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9991 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9992 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9993 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9994 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9995 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9996 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9997 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
9998 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9999 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10000 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10001 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10002 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10003 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10004 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10005 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10006 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10007 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10008 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10009 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10010 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10011 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10012 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10013 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10014 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10015 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10016 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10017 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
10018 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
10019 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
10020 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
10021 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10022 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10023 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10024 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10025 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10026 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10027 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10028 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10029 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10030 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10031 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10032 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10033 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10034 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10035 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10036 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10037 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10038 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10039 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
10040 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10041 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10042 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10043 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10044 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10045 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10046 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10047 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10048 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10049 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10050 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10051 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10052 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10053 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10054 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10055 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10056 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10057 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10058 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10059 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10060 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10061 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
10062 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10063 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10064 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10065 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10066 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10067 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10068 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10069 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10070 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10071 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10072 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10073 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10074 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10075 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10076 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10077 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10078 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10079 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
10080 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
10081 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
10082 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
10083 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
10084 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10085 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10086 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10087 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10088 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10089 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10090 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10091 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10092 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10093 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
10094 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
10095 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
10096 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
10097 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
10098 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
10099 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10100 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10101 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10102 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
10103 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
10104 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
10105 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
10106 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
10107 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
10108 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10109 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10110 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10111 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
10112 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
10115 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
10116 cCE(cfldrs
, c100400
, 2, (RMF
, ADDR
), rd_cpaddr
),
10117 cCE(cfldrd
, c500400
, 2, (RMD
, ADDR
), rd_cpaddr
),
10118 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDR
), rd_cpaddr
),
10119 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDR
), rd_cpaddr
),
10120 cCE(cfstrs
, c000400
, 2, (RMF
, ADDR
), rd_cpaddr
),
10121 cCE(cfstrd
, c400400
, 2, (RMD
, ADDR
), rd_cpaddr
),
10122 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDR
), rd_cpaddr
),
10123 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDR
), rd_cpaddr
),
10124 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
10125 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
10126 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
10127 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
10128 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
10129 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
10130 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
10131 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
10132 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
10133 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
10134 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
10135 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
10136 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
10137 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
10138 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
10139 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
10140 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
10141 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
10142 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
10143 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
10144 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
10145 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
10146 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
10147 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
10148 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
10149 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
10150 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
10151 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
10152 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
10153 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
10154 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
10155 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
10156 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
10157 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
10158 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
10159 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
10160 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
10161 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
10162 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
10163 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
10164 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
10165 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
10166 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
10167 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
10168 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
10169 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
10170 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
10171 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
10172 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
10173 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
10174 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
10175 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
10176 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
10177 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
10178 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
10179 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
10180 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
10181 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
10182 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
10183 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
10184 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
10185 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
10186 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
10187 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
10188 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
10189 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
10190 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
10191 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
10194 #undef THUMB_VARIANT
10217 /* MD interface: bits in the object file. */
10219 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
10220 for use in the a.out file, and stores them in the array pointed to by buf.
10221 This knows about the endian-ness of the target machine and does
10222 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
10223 2 (short) and 4 (long) Floating numbers are put out as a series of
10224 LITTLENUMS (shorts, here at least). */
10227 md_number_to_chars (char * buf
, valueT val
, int n
)
10229 if (target_big_endian
)
10230 number_to_chars_bigendian (buf
, val
, n
);
10232 number_to_chars_littleendian (buf
, val
, n
);
10236 md_chars_to_number (char * buf
, int n
)
10239 unsigned char * where
= (unsigned char *) buf
;
10241 if (target_big_endian
)
10246 result
|= (*where
++ & 255);
10254 result
|= (where
[n
] & 255);
10261 /* MD interface: Sections. */
10263 /* Estimate the size of a frag before relaxing. Assume everything fits in
10267 md_estimate_size_before_relax (fragS
* fragp
,
10268 segT segtype ATTRIBUTE_UNUSED
)
10274 /* Convert a machine dependent frag. */
10277 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
10279 unsigned long insn
;
10280 unsigned long old_op
;
10288 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10290 old_op
= bfd_get_16(abfd
, buf
);
10291 if (fragp
->fr_symbol
) {
10292 exp
.X_op
= O_symbol
;
10293 exp
.X_add_symbol
= fragp
->fr_symbol
;
10295 exp
.X_op
= O_constant
;
10297 exp
.X_add_number
= fragp
->fr_offset
;
10298 opcode
= fragp
->fr_subtype
;
10301 case T_MNEM_ldr_pc
:
10302 case T_MNEM_ldr_pc2
:
10303 case T_MNEM_ldr_sp
:
10304 case T_MNEM_str_sp
:
10311 if (fragp
->fr_var
== 4)
10313 insn
= THUMB_OP32(opcode
);
10314 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
10316 insn
|= (old_op
& 0x700) << 4;
10320 insn
|= (old_op
& 7) << 12;
10321 insn
|= (old_op
& 0x38) << 13;
10323 insn
|= 0x00000c00;
10324 put_thumb32_insn (buf
, insn
);
10325 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10329 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10331 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
10334 if (fragp
->fr_var
== 4)
10336 insn
= THUMB_OP32 (opcode
);
10337 insn
|= (old_op
& 0xf0) << 4;
10338 put_thumb32_insn (buf
, insn
);
10339 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10343 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
10344 exp
.X_add_number
-= 4;
10352 if (fragp
->fr_var
== 4)
10354 int r0off
= (opcode
== T_MNEM_mov
10355 || opcode
== T_MNEM_movs
) ? 0 : 8;
10356 insn
= THUMB_OP32 (opcode
);
10357 insn
= (insn
& 0xe1ffffff) | 0x10000000;
10358 insn
|= (old_op
& 0x700) << r0off
;
10359 put_thumb32_insn (buf
, insn
);
10360 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10364 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
10369 if (fragp
->fr_var
== 4)
10371 insn
= THUMB_OP32(opcode
);
10372 put_thumb32_insn (buf
, insn
);
10373 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10376 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10380 if (fragp
->fr_var
== 4)
10382 insn
= THUMB_OP32(opcode
);
10383 insn
|= (old_op
& 0xf00) << 14;
10384 put_thumb32_insn (buf
, insn
);
10385 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10388 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10391 case T_MNEM_add_sp
:
10392 case T_MNEM_add_pc
:
10393 case T_MNEM_inc_sp
:
10394 case T_MNEM_dec_sp
:
10395 if (fragp
->fr_var
== 4)
10397 /* ??? Choose between add and addw. */
10398 insn
= THUMB_OP32 (opcode
);
10399 insn
|= (old_op
& 0xf0) << 4;
10400 put_thumb32_insn (buf
, insn
);
10401 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10404 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
10412 if (fragp
->fr_var
== 4)
10414 insn
= THUMB_OP32 (opcode
);
10415 insn
|= (old_op
& 0xf0) << 4;
10416 insn
|= (old_op
& 0xf) << 16;
10417 put_thumb32_insn (buf
, insn
);
10418 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10421 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
10427 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
10429 fixp
->fx_file
= fragp
->fr_file
;
10430 fixp
->fx_line
= fragp
->fr_line
;
10431 fragp
->fr_fix
+= fragp
->fr_var
;
10434 /* Return the size of a relaxable immediate operand instruction.
10435 SHIFT and SIZE specify the form of the allowable immediate. */
10437 relax_immediate (fragS
*fragp
, int size
, int shift
)
10443 /* ??? Should be able to do better than this. */
10444 if (fragp
->fr_symbol
)
10447 low
= (1 << shift
) - 1;
10448 mask
= (1 << (shift
+ size
)) - (1 << shift
);
10449 offset
= fragp
->fr_offset
;
10450 /* Force misaligned offsets to 32-bit variant. */
10453 if (offset
& ~mask
)
10458 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
10461 relax_adr (fragS
*fragp
, asection
*sec
)
10466 /* Assume worst case for symbols not known to be in the same section. */
10467 if (!S_IS_DEFINED(fragp
->fr_symbol
)
10468 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
10471 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
10472 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10473 addr
= (addr
+ 4) & ~3;
10474 /* Fix the insn as the 4-byte version if the target address is not
10475 sufficiently aligned. This is prevents an infinite loop when two
10476 instructions have contradictory range/alignment requirements. */
10480 if (val
< 0 || val
> 1020)
10485 /* Return the size of a relaxable add/sub immediate instruction. */
10487 relax_addsub (fragS
*fragp
, asection
*sec
)
10492 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10493 op
= bfd_get_16(sec
->owner
, buf
);
10494 if ((op
& 0xf) == ((op
>> 4) & 0xf))
10495 return relax_immediate (fragp
, 8, 0);
10497 return relax_immediate (fragp
, 3, 0);
10501 /* Return the size of a relaxable branch instruction. BITS is the
10502 size of the offset field in the narrow instruction. */
10505 relax_branch (fragS
*fragp
, asection
*sec
, int bits
)
10511 /* Assume worst case for symbols not known to be in the same section. */
10512 if (!S_IS_DEFINED(fragp
->fr_symbol
)
10513 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
10516 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
10517 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
10520 /* Offset is a signed value *2 */
10522 if (val
>= limit
|| val
< -limit
)
10528 /* Relax a machine dependent frag. This returns the amount by which
10529 the current size of the frag should change. */
10532 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
10537 oldsize
= fragp
->fr_var
;
10538 switch (fragp
->fr_subtype
)
10540 case T_MNEM_ldr_pc2
:
10541 newsize
= relax_adr(fragp
, sec
);
10543 case T_MNEM_ldr_pc
:
10544 case T_MNEM_ldr_sp
:
10545 case T_MNEM_str_sp
:
10546 newsize
= relax_immediate(fragp
, 8, 2);
10550 newsize
= relax_immediate(fragp
, 5, 2);
10554 newsize
= relax_immediate(fragp
, 5, 1);
10558 newsize
= relax_immediate(fragp
, 5, 0);
10561 newsize
= relax_adr(fragp
, sec
);
10567 newsize
= relax_immediate(fragp
, 8, 0);
10570 newsize
= relax_branch(fragp
, sec
, 11);
10573 newsize
= relax_branch(fragp
, sec
, 8);
10575 case T_MNEM_add_sp
:
10576 case T_MNEM_add_pc
:
10577 newsize
= relax_immediate (fragp
, 8, 2);
10579 case T_MNEM_inc_sp
:
10580 case T_MNEM_dec_sp
:
10581 newsize
= relax_immediate (fragp
, 7, 2);
10587 newsize
= relax_addsub (fragp
, sec
);
10594 fragp
->fr_var
= -newsize
;
10595 md_convert_frag (sec
->owner
, sec
, fragp
);
10597 return -(newsize
+ oldsize
);
10599 fragp
->fr_var
= newsize
;
10600 return newsize
- oldsize
;
10603 /* Round up a section size to the appropriate boundary. */
10606 md_section_align (segT segment ATTRIBUTE_UNUSED
,
10612 /* Round all sects to multiple of 4. */
10613 return (size
+ 3) & ~3;
10617 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10618 of an rs_align_code fragment. */
10621 arm_handle_align (fragS
* fragP
)
10623 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
10624 static char const thumb_noop
[2] = { 0xc0, 0x46 };
10625 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
10626 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
10628 int bytes
, fix
, noop_size
;
10632 if (fragP
->fr_type
!= rs_align_code
)
10635 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
10636 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
10639 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
10640 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
10642 if (fragP
->tc_frag_data
)
10644 if (target_big_endian
)
10645 noop
= thumb_bigend_noop
;
10648 noop_size
= sizeof (thumb_noop
);
10652 if (target_big_endian
)
10653 noop
= arm_bigend_noop
;
10656 noop_size
= sizeof (arm_noop
);
10659 if (bytes
& (noop_size
- 1))
10661 fix
= bytes
& (noop_size
- 1);
10662 memset (p
, 0, fix
);
10667 while (bytes
>= noop_size
)
10669 memcpy (p
, noop
, noop_size
);
10671 bytes
-= noop_size
;
10675 fragP
->fr_fix
+= fix
;
10676 fragP
->fr_var
= noop_size
;
10679 /* Called from md_do_align. Used to create an alignment
10680 frag in a code section. */
10683 arm_frag_align_code (int n
, int max
)
10687 /* We assume that there will never be a requirement
10688 to support alignments greater than 32 bytes. */
10689 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
10690 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
10692 p
= frag_var (rs_align_code
,
10693 MAX_MEM_FOR_RS_ALIGN_CODE
,
10695 (relax_substateT
) max
,
10702 /* Perform target specific initialisation of a frag. */
10705 arm_init_frag (fragS
* fragP
)
10707 /* Record whether this frag is in an ARM or a THUMB area. */
10708 fragP
->tc_frag_data
= thumb_mode
;
10712 /* When we change sections we need to issue a new mapping symbol. */
10715 arm_elf_change_section (void)
10718 segment_info_type
*seginfo
;
10720 /* Link an unlinked unwind index table section to the .text section. */
10721 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
10722 && elf_linked_to_section (now_seg
) == NULL
)
10723 elf_linked_to_section (now_seg
) = text_section
;
10725 if (!SEG_NORMAL (now_seg
))
10728 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
10730 /* We can ignore sections that only contain debug info. */
10731 if ((flags
& SEC_ALLOC
) == 0)
10734 seginfo
= seg_info (now_seg
);
10735 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
10736 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
10740 arm_elf_section_type (const char * str
, size_t len
)
10742 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
10743 return SHT_ARM_EXIDX
;
10748 /* Code to deal with unwinding tables. */
10750 static void add_unwind_adjustsp (offsetT
);
10752 /* Cenerate and deferred unwind frame offset. */
10755 flush_pending_unwind (void)
10759 offset
= unwind
.pending_offset
;
10760 unwind
.pending_offset
= 0;
10762 add_unwind_adjustsp (offset
);
10765 /* Add an opcode to this list for this function. Two-byte opcodes should
10766 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
10770 add_unwind_opcode (valueT op
, int length
)
10772 /* Add any deferred stack adjustment. */
10773 if (unwind
.pending_offset
)
10774 flush_pending_unwind ();
10776 unwind
.sp_restored
= 0;
10778 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
10780 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
10781 if (unwind
.opcodes
)
10782 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
10783 unwind
.opcode_alloc
);
10785 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
10790 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
10792 unwind
.opcode_count
++;
10796 /* Add unwind opcodes to adjust the stack pointer. */
10799 add_unwind_adjustsp (offsetT offset
)
10803 if (offset
> 0x200)
10805 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
10810 /* Long form: 0xb2, uleb128. */
10811 /* This might not fit in a word so add the individual bytes,
10812 remembering the list is built in reverse order. */
10813 o
= (valueT
) ((offset
- 0x204) >> 2);
10815 add_unwind_opcode (0, 1);
10817 /* Calculate the uleb128 encoding of the offset. */
10821 bytes
[n
] = o
& 0x7f;
10827 /* Add the insn. */
10829 add_unwind_opcode (bytes
[n
- 1], 1);
10830 add_unwind_opcode (0xb2, 1);
10832 else if (offset
> 0x100)
10834 /* Two short opcodes. */
10835 add_unwind_opcode (0x3f, 1);
10836 op
= (offset
- 0x104) >> 2;
10837 add_unwind_opcode (op
, 1);
10839 else if (offset
> 0)
10841 /* Short opcode. */
10842 op
= (offset
- 4) >> 2;
10843 add_unwind_opcode (op
, 1);
10845 else if (offset
< 0)
10848 while (offset
> 0x100)
10850 add_unwind_opcode (0x7f, 1);
10853 op
= ((offset
- 4) >> 2) | 0x40;
10854 add_unwind_opcode (op
, 1);
10858 /* Finish the list of unwind opcodes for this function. */
10860 finish_unwind_opcodes (void)
10864 if (unwind
.fp_used
)
10866 /* Adjust sp as neccessary. */
10867 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
10868 flush_pending_unwind ();
10870 /* After restoring sp from the frame pointer. */
10871 op
= 0x90 | unwind
.fp_reg
;
10872 add_unwind_opcode (op
, 1);
10875 flush_pending_unwind ();
10879 /* Start an exception table entry. If idx is nonzero this is an index table
10883 start_unwind_section (const segT text_seg
, int idx
)
10885 const char * text_name
;
10886 const char * prefix
;
10887 const char * prefix_once
;
10888 const char * group_name
;
10892 size_t sec_name_len
;
10899 prefix
= ELF_STRING_ARM_unwind
;
10900 prefix_once
= ELF_STRING_ARM_unwind_once
;
10901 type
= SHT_ARM_EXIDX
;
10905 prefix
= ELF_STRING_ARM_unwind_info
;
10906 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
10907 type
= SHT_PROGBITS
;
10910 text_name
= segment_name (text_seg
);
10911 if (streq (text_name
, ".text"))
10914 if (strncmp (text_name
, ".gnu.linkonce.t.",
10915 strlen (".gnu.linkonce.t.")) == 0)
10917 prefix
= prefix_once
;
10918 text_name
+= strlen (".gnu.linkonce.t.");
10921 prefix_len
= strlen (prefix
);
10922 text_len
= strlen (text_name
);
10923 sec_name_len
= prefix_len
+ text_len
;
10924 sec_name
= xmalloc (sec_name_len
+ 1);
10925 memcpy (sec_name
, prefix
, prefix_len
);
10926 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
10927 sec_name
[prefix_len
+ text_len
] = '\0';
10933 /* Handle COMDAT group. */
10934 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
10936 group_name
= elf_group_name (text_seg
);
10937 if (group_name
== NULL
)
10939 as_bad ("Group section `%s' has no group signature",
10940 segment_name (text_seg
));
10941 ignore_rest_of_line ();
10944 flags
|= SHF_GROUP
;
10948 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
10950 /* Set the setion link for index tables. */
10952 elf_linked_to_section (now_seg
) = text_seg
;
10956 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
10957 personality routine data. Returns zero, or the index table value for
10958 and inline entry. */
10961 create_unwind_entry (int have_data
)
10966 /* The current word of data. */
10968 /* The number of bytes left in this word. */
10971 finish_unwind_opcodes ();
10973 /* Remember the current text section. */
10974 unwind
.saved_seg
= now_seg
;
10975 unwind
.saved_subseg
= now_subseg
;
10977 start_unwind_section (now_seg
, 0);
10979 if (unwind
.personality_routine
== NULL
)
10981 if (unwind
.personality_index
== -2)
10984 as_bad (_("handerdata in cantunwind frame"));
10985 return 1; /* EXIDX_CANTUNWIND. */
10988 /* Use a default personality routine if none is specified. */
10989 if (unwind
.personality_index
== -1)
10991 if (unwind
.opcode_count
> 3)
10992 unwind
.personality_index
= 1;
10994 unwind
.personality_index
= 0;
10997 /* Space for the personality routine entry. */
10998 if (unwind
.personality_index
== 0)
11000 if (unwind
.opcode_count
> 3)
11001 as_bad (_("too many unwind opcodes for personality routine 0"));
11005 /* All the data is inline in the index table. */
11008 while (unwind
.opcode_count
> 0)
11010 unwind
.opcode_count
--;
11011 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
11015 /* Pad with "finish" opcodes. */
11017 data
= (data
<< 8) | 0xb0;
11024 /* We get two opcodes "free" in the first word. */
11025 size
= unwind
.opcode_count
- 2;
11028 /* An extra byte is required for the opcode count. */
11029 size
= unwind
.opcode_count
+ 1;
11031 size
= (size
+ 3) >> 2;
11033 as_bad (_("too many unwind opcodes"));
11035 frag_align (2, 0, 0);
11036 record_alignment (now_seg
, 2);
11037 unwind
.table_entry
= expr_build_dot ();
11039 /* Allocate the table entry. */
11040 ptr
= frag_more ((size
<< 2) + 4);
11041 where
= frag_now_fix () - ((size
<< 2) + 4);
11043 switch (unwind
.personality_index
)
11046 /* ??? Should this be a PLT generating relocation? */
11047 /* Custom personality routine. */
11048 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
11049 BFD_RELOC_ARM_PREL31
);
11054 /* Set the first byte to the number of additional words. */
11059 /* ABI defined personality routines. */
11061 /* Three opcodes bytes are packed into the first word. */
11068 /* The size and first two opcode bytes go in the first word. */
11069 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
11074 /* Should never happen. */
11078 /* Pack the opcodes into words (MSB first), reversing the list at the same
11080 while (unwind
.opcode_count
> 0)
11084 md_number_to_chars (ptr
, data
, 4);
11089 unwind
.opcode_count
--;
11091 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
11094 /* Finish off the last word. */
11097 /* Pad with "finish" opcodes. */
11099 data
= (data
<< 8) | 0xb0;
11101 md_number_to_chars (ptr
, data
, 4);
11106 /* Add an empty descriptor if there is no user-specified data. */
11107 ptr
= frag_more (4);
11108 md_number_to_chars (ptr
, 0, 4);
11114 /* Convert REGNAME to a DWARF-2 register number. */
11117 tc_arm_regname_to_dw2regnum (const char *regname
)
11119 int reg
= arm_reg_parse ((char **) ®name
, REG_TYPE_RN
);
11127 /* Initialize the DWARF-2 unwind information for this procedure. */
11130 tc_arm_frame_initial_instructions (void)
11132 cfi_add_CFA_def_cfa (REG_SP
, 0);
11134 #endif /* OBJ_ELF */
11137 /* MD interface: Symbol and relocation handling. */
11139 /* Return the address within the segment that a PC-relative fixup is
11140 relative to. For ARM, PC-relative fixups applied to instructions
11141 are generally relative to the location of the fixup plus 8 bytes.
11142 Thumb branches are offset by 4, and Thumb loads relative to PC
11143 require special handling. */
11146 md_pcrel_from_section (fixS
* fixP
, segT seg
)
11148 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11150 /* If this is pc-relative and we are going to emit a relocation
11151 then we just want to put out any pipeline compensation that the linker
11152 will need. Otherwise we want to use the calculated base. */
11154 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11155 || arm_force_relocation (fixP
)))
11158 switch (fixP
->fx_r_type
)
11160 /* PC relative addressing on the Thumb is slightly odd as the
11161 bottom two bits of the PC are forced to zero for the
11162 calculation. This happens *after* application of the
11163 pipeline offset. However, Thumb adrl already adjusts for
11164 this, so we need not do it again. */
11165 case BFD_RELOC_ARM_THUMB_ADD
:
11168 case BFD_RELOC_ARM_THUMB_OFFSET
:
11169 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
11170 case BFD_RELOC_ARM_T32_ADD_PC12
:
11171 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
11172 return (base
+ 4) & ~3;
11174 /* Thumb branches are simply offset by +4. */
11175 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
11176 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
11177 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
11178 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
11179 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
11180 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
11181 case BFD_RELOC_THUMB_PCREL_BLX
:
11184 /* ARM mode branches are offset by +8. However, the Windows CE
11185 loader expects the relocation not to take this into account. */
11186 case BFD_RELOC_ARM_PCREL_BRANCH
:
11187 case BFD_RELOC_ARM_PCREL_CALL
:
11188 case BFD_RELOC_ARM_PCREL_JUMP
:
11189 case BFD_RELOC_ARM_PCREL_BLX
:
11190 case BFD_RELOC_ARM_PLT32
:
11197 /* ARM mode loads relative to PC are also offset by +8. Unlike
11198 branches, the Windows CE loader *does* expect the relocation
11199 to take this into account. */
11200 case BFD_RELOC_ARM_OFFSET_IMM
:
11201 case BFD_RELOC_ARM_OFFSET_IMM8
:
11202 case BFD_RELOC_ARM_HWLITERAL
:
11203 case BFD_RELOC_ARM_LITERAL
:
11204 case BFD_RELOC_ARM_CP_OFF_IMM
:
11208 /* Other PC-relative relocations are un-offset. */
11214 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
11215 Otherwise we have no need to default values of symbols. */
11218 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
11221 if (name
[0] == '_' && name
[1] == 'G'
11222 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
11226 if (symbol_find (name
))
11227 as_bad ("GOT already in the symbol table");
11229 GOT_symbol
= symbol_new (name
, undefined_section
,
11230 (valueT
) 0, & zero_address_frag
);
11240 /* Subroutine of md_apply_fix. Check to see if an immediate can be
11241 computed as two separate immediate values, added together. We
11242 already know that this value cannot be computed by just one ARM
11245 static unsigned int
11246 validate_immediate_twopart (unsigned int val
,
11247 unsigned int * highpart
)
11252 for (i
= 0; i
< 32; i
+= 2)
11253 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
11259 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
11261 else if (a
& 0xff0000)
11263 if (a
& 0xff000000)
11265 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
11269 assert (a
& 0xff000000);
11270 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
11273 return (a
& 0xff) | (i
<< 7);
11280 validate_offset_imm (unsigned int val
, int hwse
)
11282 if ((hwse
&& val
> 255) || val
> 4095)
11287 /* Subroutine of md_apply_fix. Do those data_ops which can take a
11288 negative immediate constant by altering the instruction. A bit of
11293 by inverting the second operand, and
11296 by negating the second operand. */
11299 negate_data_op (unsigned long * instruction
,
11300 unsigned long value
)
11303 unsigned long negated
, inverted
;
11305 negated
= encode_arm_immediate (-value
);
11306 inverted
= encode_arm_immediate (~value
);
11308 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
11311 /* First negates. */
11312 case OPCODE_SUB
: /* ADD <-> SUB */
11313 new_inst
= OPCODE_ADD
;
11318 new_inst
= OPCODE_SUB
;
11322 case OPCODE_CMP
: /* CMP <-> CMN */
11323 new_inst
= OPCODE_CMN
;
11328 new_inst
= OPCODE_CMP
;
11332 /* Now Inverted ops. */
11333 case OPCODE_MOV
: /* MOV <-> MVN */
11334 new_inst
= OPCODE_MVN
;
11339 new_inst
= OPCODE_MOV
;
11343 case OPCODE_AND
: /* AND <-> BIC */
11344 new_inst
= OPCODE_BIC
;
11349 new_inst
= OPCODE_AND
;
11353 case OPCODE_ADC
: /* ADC <-> SBC */
11354 new_inst
= OPCODE_SBC
;
11359 new_inst
= OPCODE_ADC
;
11363 /* We cannot do anything. */
11368 if (value
== (unsigned) FAIL
)
11371 *instruction
&= OPCODE_MASK
;
11372 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
11376 /* Like negate_data_op, but for Thumb-2. */
11378 static unsigned int
11379 thumb32_negate_data_op (offsetT
*instruction
, offsetT value
)
11383 offsetT negated
, inverted
;
11385 negated
= encode_thumb32_immediate (-value
);
11386 inverted
= encode_thumb32_immediate (~value
);
11388 rd
= (*instruction
>> 8) & 0xf;
11389 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
11392 /* ADD <-> SUB. Includes CMP <-> CMN. */
11393 case T2_OPCODE_SUB
:
11394 new_inst
= T2_OPCODE_ADD
;
11398 case T2_OPCODE_ADD
:
11399 new_inst
= T2_OPCODE_SUB
;
11403 /* ORR <-> ORN. Includes MOV <-> MVN. */
11404 case T2_OPCODE_ORR
:
11405 new_inst
= T2_OPCODE_ORN
;
11409 case T2_OPCODE_ORN
:
11410 new_inst
= T2_OPCODE_ORR
;
11414 /* AND <-> BIC. TST has no inverted equivalent. */
11415 case T2_OPCODE_AND
:
11416 new_inst
= T2_OPCODE_BIC
;
11423 case T2_OPCODE_BIC
:
11424 new_inst
= T2_OPCODE_AND
;
11429 case T2_OPCODE_ADC
:
11430 new_inst
= T2_OPCODE_SBC
;
11434 case T2_OPCODE_SBC
:
11435 new_inst
= T2_OPCODE_ADC
;
11439 /* We cannot do anything. */
11447 *instruction
&= T2_OPCODE_MASK
;
11448 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
11452 /* Read a 32-bit thumb instruction from buf. */
11453 static unsigned long
11454 get_thumb32_insn (char * buf
)
11456 unsigned long insn
;
11457 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
11458 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
11464 md_apply_fix (fixS
* fixP
,
11468 offsetT value
= * valP
;
11470 unsigned int newimm
;
11471 unsigned long temp
;
11473 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11475 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
11477 /* Note whether this will delete the relocation. */
11478 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
11481 /* On a 64-bit host, silently truncate 'value' to 32 bits for
11482 consistency with the behavior on 32-bit hosts. Remember value
11484 value
&= 0xffffffff;
11485 value
^= 0x80000000;
11486 value
-= 0x80000000;
11489 fixP
->fx_addnumber
= value
;
11491 /* Same treatment for fixP->fx_offset. */
11492 fixP
->fx_offset
&= 0xffffffff;
11493 fixP
->fx_offset
^= 0x80000000;
11494 fixP
->fx_offset
-= 0x80000000;
11496 switch (fixP
->fx_r_type
)
11498 case BFD_RELOC_NONE
:
11499 /* This will need to go in the object file. */
11503 case BFD_RELOC_ARM_IMMEDIATE
:
11504 /* We claim that this fixup has been processed here,
11505 even if in fact we generate an error because we do
11506 not have a reloc for it, so tc_gen_reloc will reject it. */
11510 && ! S_IS_DEFINED (fixP
->fx_addsy
))
11512 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11513 _("undefined symbol %s used as an immediate value"),
11514 S_GET_NAME (fixP
->fx_addsy
));
11518 newimm
= encode_arm_immediate (value
);
11519 temp
= md_chars_to_number (buf
, INSN_SIZE
);
11521 /* If the instruction will fail, see if we can fix things up by
11522 changing the opcode. */
11523 if (newimm
== (unsigned int) FAIL
11524 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
11526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11527 _("invalid constant (%lx) after fixup"),
11528 (unsigned long) value
);
11532 newimm
|= (temp
& 0xfffff000);
11533 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
11536 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
11538 unsigned int highpart
= 0;
11539 unsigned int newinsn
= 0xe1a00000; /* nop. */
11541 newimm
= encode_arm_immediate (value
);
11542 temp
= md_chars_to_number (buf
, INSN_SIZE
);
11544 /* If the instruction will fail, see if we can fix things up by
11545 changing the opcode. */
11546 if (newimm
== (unsigned int) FAIL
11547 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
11549 /* No ? OK - try using two ADD instructions to generate
11551 newimm
= validate_immediate_twopart (value
, & highpart
);
11553 /* Yes - then make sure that the second instruction is
11555 if (newimm
!= (unsigned int) FAIL
)
11557 /* Still No ? Try using a negated value. */
11558 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
11559 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
11560 /* Otherwise - give up. */
11563 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11564 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
11569 /* Replace the first operand in the 2nd instruction (which
11570 is the PC) with the destination register. We have
11571 already added in the PC in the first instruction and we
11572 do not want to do it again. */
11573 newinsn
&= ~ 0xf0000;
11574 newinsn
|= ((newinsn
& 0x0f000) << 4);
11577 newimm
|= (temp
& 0xfffff000);
11578 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
11580 highpart
|= (newinsn
& 0xfffff000);
11581 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
11585 case BFD_RELOC_ARM_OFFSET_IMM
:
11586 if (!fixP
->fx_done
&& seg
->use_rela_p
)
11589 case BFD_RELOC_ARM_LITERAL
:
11595 if (validate_offset_imm (value
, 0) == FAIL
)
11597 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
11598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11599 _("invalid literal constant: pool needs to be closer"));
11601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11602 _("bad immediate value for offset (%ld)"),
11607 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11608 newval
&= 0xff7ff000;
11609 newval
|= value
| (sign
? INDEX_UP
: 0);
11610 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11613 case BFD_RELOC_ARM_OFFSET_IMM8
:
11614 case BFD_RELOC_ARM_HWLITERAL
:
11620 if (validate_offset_imm (value
, 1) == FAIL
)
11622 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
11623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11624 _("invalid literal constant: pool needs to be closer"));
11626 as_bad (_("bad immediate value for half-word offset (%ld)"),
11631 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11632 newval
&= 0xff7ff0f0;
11633 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
11634 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11637 case BFD_RELOC_ARM_T32_OFFSET_U8
:
11638 if (value
< 0 || value
> 1020 || value
% 4 != 0)
11639 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11640 _("bad immediate value for offset (%ld)"), (long) value
);
11643 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
11645 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
11648 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
11649 /* This is a complicated relocation used for all varieties of Thumb32
11650 load/store instruction with immediate offset:
11652 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
11653 *4, optional writeback(W)
11654 (doubleword load/store)
11656 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
11657 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
11658 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
11659 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
11660 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
11662 Uppercase letters indicate bits that are already encoded at
11663 this point. Lowercase letters are our problem. For the
11664 second block of instructions, the secondary opcode nybble
11665 (bits 8..11) is present, and bit 23 is zero, even if this is
11666 a PC-relative operation. */
11667 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11669 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
11671 if ((newval
& 0xf0000000) == 0xe0000000)
11673 /* Doubleword load/store: 8-bit offset, scaled by 4. */
11675 newval
|= (1 << 23);
11678 if (value
% 4 != 0)
11680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11681 _("offset not a multiple of 4"));
11687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11688 _("offset out of range"));
11693 else if ((newval
& 0x000f0000) == 0x000f0000)
11695 /* PC-relative, 12-bit offset. */
11697 newval
|= (1 << 23);
11702 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11703 _("offset out of range"));
11708 else if ((newval
& 0x00000100) == 0x00000100)
11710 /* Writeback: 8-bit, +/- offset. */
11712 newval
|= (1 << 9);
11717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11718 _("offset out of range"));
11723 else if ((newval
& 0x00000f00) == 0x00000e00)
11725 /* T-instruction: positive 8-bit offset. */
11726 if (value
< 0 || value
> 0xff)
11728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11729 _("offset out of range"));
11737 /* Positive 12-bit or negative 8-bit offset. */
11741 newval
|= (1 << 23);
11751 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11752 _("offset out of range"));
11759 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
11760 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
11763 case BFD_RELOC_ARM_SHIFT_IMM
:
11764 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11765 if (((unsigned long) value
) > 32
11767 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
11769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11770 _("shift expression is too large"));
11775 /* Shifts of zero must be done as lsl. */
11777 else if (value
== 32)
11779 newval
&= 0xfffff07f;
11780 newval
|= (value
& 0x1f) << 7;
11781 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11784 case BFD_RELOC_ARM_T32_IMMEDIATE
:
11785 case BFD_RELOC_ARM_T32_IMM12
:
11786 case BFD_RELOC_ARM_T32_ADD_PC12
:
11787 /* We claim that this fixup has been processed here,
11788 even if in fact we generate an error because we do
11789 not have a reloc for it, so tc_gen_reloc will reject it. */
11793 && ! S_IS_DEFINED (fixP
->fx_addsy
))
11795 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11796 _("undefined symbol %s used as an immediate value"),
11797 S_GET_NAME (fixP
->fx_addsy
));
11801 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11803 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
11805 /* FUTURE: Implement analogue of negate_data_op for T32. */
11806 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
)
11808 newimm
= encode_thumb32_immediate (value
);
11809 if (newimm
== (unsigned int) FAIL
)
11810 newimm
= thumb32_negate_data_op (&newval
, value
);
11814 /* 12 bit immediate for addw/subw. */
11818 newval
^= 0x00a00000;
11821 newimm
= (unsigned int) FAIL
;
11826 if (newimm
== (unsigned int)FAIL
)
11828 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11829 _("invalid constant (%lx) after fixup"),
11830 (unsigned long) value
);
11834 newval
|= (newimm
& 0x800) << 15;
11835 newval
|= (newimm
& 0x700) << 4;
11836 newval
|= (newimm
& 0x0ff);
11838 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
11839 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
11842 case BFD_RELOC_ARM_SMC
:
11843 if (((unsigned long) value
) > 0xffff)
11844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11845 _("invalid smc expression"));
11846 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11847 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
11848 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11851 case BFD_RELOC_ARM_SWI
:
11852 if (fixP
->tc_fix_data
!= 0)
11854 if (((unsigned long) value
) > 0xff)
11855 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11856 _("invalid swi expression"));
11857 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11859 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11863 if (((unsigned long) value
) > 0x00ffffff)
11864 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11865 _("invalid swi expression"));
11866 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11868 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11872 case BFD_RELOC_ARM_MULTI
:
11873 if (((unsigned long) value
) > 0xffff)
11874 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11875 _("invalid expression in load/store multiple"));
11876 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
11877 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11881 case BFD_RELOC_ARM_PCREL_CALL
:
11882 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11883 if ((newval
& 0xf0000000) == 0xf0000000)
11887 goto arm_branch_common
;
11889 case BFD_RELOC_ARM_PCREL_JUMP
:
11890 case BFD_RELOC_ARM_PLT32
:
11892 case BFD_RELOC_ARM_PCREL_BRANCH
:
11894 goto arm_branch_common
;
11896 case BFD_RELOC_ARM_PCREL_BLX
:
11899 /* We are going to store value (shifted right by two) in the
11900 instruction, in a 24 bit, signed field. Bits 26 through 32 either
11901 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
11902 also be be clear. */
11904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11905 _("misaligned branch destination"));
11906 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
11907 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
11908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11909 _("branch out of range"));
11911 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11913 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11914 newval
|= (value
>> 2) & 0x00ffffff;
11915 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11919 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
11920 /* CZB can only branch forward. */
11922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11923 _("branch out of range"));
11925 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11927 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11928 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
11929 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11933 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
11934 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
11935 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11936 _("branch out of range"));
11938 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11940 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11941 newval
|= (value
& 0x1ff) >> 1;
11942 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11946 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
11947 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
11948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11949 _("branch out of range"));
11951 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11953 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11954 newval
|= (value
& 0xfff) >> 1;
11955 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11959 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
11960 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
11961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11962 _("conditional branch out of range"));
11964 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11967 addressT S
, J1
, J2
, lo
, hi
;
11969 S
= (value
& 0x00100000) >> 20;
11970 J2
= (value
& 0x00080000) >> 19;
11971 J1
= (value
& 0x00040000) >> 18;
11972 hi
= (value
& 0x0003f000) >> 12;
11973 lo
= (value
& 0x00000ffe) >> 1;
11975 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11976 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
11977 newval
|= (S
<< 10) | hi
;
11978 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
11979 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11980 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
11984 case BFD_RELOC_THUMB_PCREL_BLX
:
11985 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
11986 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
11987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11988 _("branch out of range"));
11990 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
11991 /* For a BLX instruction, make sure that the relocation is rounded up
11992 to a word boundary. This follows the semantics of the instruction
11993 which specifies that bit 1 of the target address will come from bit
11994 1 of the base address. */
11995 value
= (value
+ 1) & ~ 1;
11997 if (fixP
->fx_done
|| !seg
->use_rela_p
)
12001 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
12002 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
12003 newval
|= (value
& 0x7fffff) >> 12;
12004 newval2
|= (value
& 0xfff) >> 1;
12005 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
12006 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
12010 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
12011 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
12012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12013 _("branch out of range"));
12015 if (fixP
->fx_done
|| !seg
->use_rela_p
)
12018 addressT S
, I1
, I2
, lo
, hi
;
12020 S
= (value
& 0x01000000) >> 24;
12021 I1
= (value
& 0x00800000) >> 23;
12022 I2
= (value
& 0x00400000) >> 22;
12023 hi
= (value
& 0x003ff000) >> 12;
12024 lo
= (value
& 0x00000ffe) >> 1;
12029 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
12030 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
12031 newval
|= (S
<< 10) | hi
;
12032 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
12033 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
12034 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
12039 if (fixP
->fx_done
|| !seg
->use_rela_p
)
12040 md_number_to_chars (buf
, value
, 1);
12044 if (fixP
->fx_done
|| !seg
->use_rela_p
)
12045 md_number_to_chars (buf
, value
, 2);
12049 case BFD_RELOC_ARM_TLS_GD32
:
12050 case BFD_RELOC_ARM_TLS_LE32
:
12051 case BFD_RELOC_ARM_TLS_IE32
:
12052 case BFD_RELOC_ARM_TLS_LDM32
:
12053 case BFD_RELOC_ARM_TLS_LDO32
:
12054 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12057 case BFD_RELOC_ARM_GOT32
:
12058 case BFD_RELOC_ARM_GOTOFF
:
12059 case BFD_RELOC_ARM_TARGET2
:
12060 if (fixP
->fx_done
|| !seg
->use_rela_p
)
12061 md_number_to_chars (buf
, 0, 4);
12065 case BFD_RELOC_RVA
:
12067 case BFD_RELOC_ARM_TARGET1
:
12068 case BFD_RELOC_ARM_ROSEGREL32
:
12069 case BFD_RELOC_ARM_SBREL32
:
12070 case BFD_RELOC_32_PCREL
:
12071 if (fixP
->fx_done
|| !seg
->use_rela_p
)
12072 md_number_to_chars (buf
, value
, 4);
12076 case BFD_RELOC_ARM_PREL31
:
12077 if (fixP
->fx_done
|| !seg
->use_rela_p
)
12079 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
12080 if ((value
^ (value
>> 1)) & 0x40000000)
12082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12083 _("rel31 relocation overflow"));
12085 newval
|= value
& 0x7fffffff;
12086 md_number_to_chars (buf
, newval
, 4);
12091 case BFD_RELOC_ARM_CP_OFF_IMM
:
12092 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
12093 if (value
< -1023 || value
> 1023 || (value
& 3))
12094 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12095 _("co-processor offset out of range"));
12100 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
12101 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
12102 newval
= md_chars_to_number (buf
, INSN_SIZE
);
12104 newval
= get_thumb32_insn (buf
);
12105 newval
&= 0xff7fff00;
12106 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
12108 newval
&= ~WRITE_BACK
;
12109 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
12110 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
12111 md_number_to_chars (buf
, newval
, INSN_SIZE
);
12113 put_thumb32_insn (buf
, newval
);
12116 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
12117 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
12118 if (value
< -255 || value
> 255)
12119 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12120 _("co-processor offset out of range"));
12121 goto cp_off_common
;
12123 case BFD_RELOC_ARM_THUMB_OFFSET
:
12124 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
12125 /* Exactly what ranges, and where the offset is inserted depends
12126 on the type of instruction, we can establish this from the
12128 switch (newval
>> 12)
12130 case 4: /* PC load. */
12131 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
12132 forced to zero for these loads; md_pcrel_from has already
12133 compensated for this. */
12135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12136 _("invalid offset, target not word aligned (0x%08lX)"),
12137 (((unsigned long) fixP
->fx_frag
->fr_address
12138 + (unsigned long) fixP
->fx_where
) & ~3)
12139 + (unsigned long) value
);
12141 if (value
& ~0x3fc)
12142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12143 _("invalid offset, value too big (0x%08lX)"),
12146 newval
|= value
>> 2;
12149 case 9: /* SP load/store. */
12150 if (value
& ~0x3fc)
12151 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12152 _("invalid offset, value too big (0x%08lX)"),
12154 newval
|= value
>> 2;
12157 case 6: /* Word load/store. */
12159 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12160 _("invalid offset, value too big (0x%08lX)"),
12162 newval
|= value
<< 4; /* 6 - 2. */
12165 case 7: /* Byte load/store. */
12167 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12168 _("invalid offset, value too big (0x%08lX)"),
12170 newval
|= value
<< 6;
12173 case 8: /* Halfword load/store. */
12175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12176 _("invalid offset, value too big (0x%08lX)"),
12178 newval
|= value
<< 5; /* 6 - 1. */
12182 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12183 "Unable to process relocation for thumb opcode: %lx",
12184 (unsigned long) newval
);
12187 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
12190 case BFD_RELOC_ARM_THUMB_ADD
:
12191 /* This is a complicated relocation, since we use it for all of
12192 the following immediate relocations:
12196 9bit ADD/SUB SP word-aligned
12197 10bit ADD PC/SP word-aligned
12199 The type of instruction being processed is encoded in the
12206 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
12208 int rd
= (newval
>> 4) & 0xf;
12209 int rs
= newval
& 0xf;
12210 int subtract
= !!(newval
& 0x8000);
12212 /* Check for HI regs, only very restricted cases allowed:
12213 Adjusting SP, and using PC or SP to get an address. */
12214 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
12215 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
12216 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12217 _("invalid Hi register with immediate"));
12219 /* If value is negative, choose the opposite instruction. */
12223 subtract
= !subtract
;
12225 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12226 _("immediate value out of range"));
12231 if (value
& ~0x1fc)
12232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12233 _("invalid immediate for stack address calculation"));
12234 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
12235 newval
|= value
>> 2;
12237 else if (rs
== REG_PC
|| rs
== REG_SP
)
12239 if (subtract
|| value
& ~0x3fc)
12240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12241 _("invalid immediate for address calculation (value = 0x%08lX)"),
12242 (unsigned long) value
);
12243 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
12245 newval
|= value
>> 2;
12250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12251 _("immediate value out of range"));
12252 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
12253 newval
|= (rd
<< 8) | value
;
12258 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12259 _("immediate value out of range"));
12260 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
12261 newval
|= rd
| (rs
<< 3) | (value
<< 6);
12264 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
12267 case BFD_RELOC_ARM_THUMB_IMM
:
12268 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
12269 if (value
< 0 || value
> 255)
12270 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12271 _("invalid immediate: %ld is too large"),
12274 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
12277 case BFD_RELOC_ARM_THUMB_SHIFT
:
12278 /* 5bit shift value (0..32). LSL cannot take 32. */
12279 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
12280 temp
= newval
& 0xf800;
12281 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
12282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12283 _("invalid shift value: %ld"), (long) value
);
12284 /* Shifts of zero must be encoded as LSL. */
12286 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
12287 /* Shifts of 32 are encoded as zero. */
12288 else if (value
== 32)
12290 newval
|= value
<< 6;
12291 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
12294 case BFD_RELOC_VTABLE_INHERIT
:
12295 case BFD_RELOC_VTABLE_ENTRY
:
12299 case BFD_RELOC_UNUSED
:
12301 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12302 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
12306 /* Translate internal representation of relocation info to BFD target
12310 tc_gen_reloc (asection
*section
, fixS
*fixp
)
12313 bfd_reloc_code_real_type code
;
12315 reloc
= xmalloc (sizeof (arelent
));
12317 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
12318 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12319 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12321 if (fixp
->fx_pcrel
)
12323 if (section
->use_rela_p
)
12324 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
12326 fixp
->fx_offset
= reloc
->address
;
12328 reloc
->addend
= fixp
->fx_offset
;
12330 switch (fixp
->fx_r_type
)
12333 if (fixp
->fx_pcrel
)
12335 code
= BFD_RELOC_8_PCREL
;
12340 if (fixp
->fx_pcrel
)
12342 code
= BFD_RELOC_16_PCREL
;
12347 if (fixp
->fx_pcrel
)
12349 code
= BFD_RELOC_32_PCREL
;
12353 case BFD_RELOC_NONE
:
12354 case BFD_RELOC_ARM_PCREL_BRANCH
:
12355 case BFD_RELOC_ARM_PCREL_BLX
:
12356 case BFD_RELOC_RVA
:
12357 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
12358 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
12359 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
12360 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
12361 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
12362 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
12363 case BFD_RELOC_THUMB_PCREL_BLX
:
12364 case BFD_RELOC_VTABLE_ENTRY
:
12365 case BFD_RELOC_VTABLE_INHERIT
:
12366 code
= fixp
->fx_r_type
;
12369 case BFD_RELOC_ARM_LITERAL
:
12370 case BFD_RELOC_ARM_HWLITERAL
:
12371 /* If this is called then the a literal has
12372 been referenced across a section boundary. */
12373 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12374 _("literal referenced across section boundary"));
12378 case BFD_RELOC_ARM_GOT32
:
12379 case BFD_RELOC_ARM_GOTOFF
:
12380 case BFD_RELOC_ARM_PLT32
:
12381 case BFD_RELOC_ARM_TARGET1
:
12382 case BFD_RELOC_ARM_ROSEGREL32
:
12383 case BFD_RELOC_ARM_SBREL32
:
12384 case BFD_RELOC_ARM_PREL31
:
12385 case BFD_RELOC_ARM_TARGET2
:
12386 case BFD_RELOC_ARM_TLS_LE32
:
12387 case BFD_RELOC_ARM_TLS_LDO32
:
12388 case BFD_RELOC_ARM_PCREL_CALL
:
12389 case BFD_RELOC_ARM_PCREL_JUMP
:
12390 code
= fixp
->fx_r_type
;
12393 case BFD_RELOC_ARM_TLS_GD32
:
12394 case BFD_RELOC_ARM_TLS_IE32
:
12395 case BFD_RELOC_ARM_TLS_LDM32
:
12396 /* BFD will include the symbol's address in the addend.
12397 But we don't want that, so subtract it out again here. */
12398 if (!S_IS_COMMON (fixp
->fx_addsy
))
12399 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
12400 code
= fixp
->fx_r_type
;
12404 case BFD_RELOC_ARM_IMMEDIATE
:
12405 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12406 _("internal relocation (type: IMMEDIATE) not fixed up"));
12409 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
12410 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12411 _("ADRL used for a symbol not defined in the same file"));
12414 case BFD_RELOC_ARM_OFFSET_IMM
:
12415 if (section
->use_rela_p
)
12417 code
= fixp
->fx_r_type
;
12421 if (fixp
->fx_addsy
!= NULL
12422 && !S_IS_DEFINED (fixp
->fx_addsy
)
12423 && S_IS_LOCAL (fixp
->fx_addsy
))
12425 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12426 _("undefined local label `%s'"),
12427 S_GET_NAME (fixp
->fx_addsy
));
12431 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12432 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
12439 switch (fixp
->fx_r_type
)
12441 case BFD_RELOC_NONE
: type
= "NONE"; break;
12442 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
12443 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
12444 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
12445 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
12446 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
12447 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
12448 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
12449 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
12450 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
12451 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
12452 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
12453 default: type
= _("<unknown>"); break;
12455 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12456 _("cannot represent %s relocation in this object file format"),
12463 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
12465 && fixp
->fx_addsy
== GOT_symbol
)
12467 code
= BFD_RELOC_ARM_GOTPC
;
12468 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
12472 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12474 if (reloc
->howto
== NULL
)
12476 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12477 _("cannot represent %s relocation in this object file format"),
12478 bfd_get_reloc_code_name (code
));
12482 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
12483 vtable entry to be used in the relocation's section offset. */
12484 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12485 reloc
->address
= fixp
->fx_offset
;
12490 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
12493 cons_fix_new_arm (fragS
* frag
,
12498 bfd_reloc_code_real_type type
;
12502 FIXME: @@ Should look at CPU word size. */
12506 type
= BFD_RELOC_8
;
12509 type
= BFD_RELOC_16
;
12513 type
= BFD_RELOC_32
;
12516 type
= BFD_RELOC_64
;
12520 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
12523 #if defined OBJ_COFF || defined OBJ_ELF
12525 arm_validate_fix (fixS
* fixP
)
12527 /* If the destination of the branch is a defined symbol which does not have
12528 the THUMB_FUNC attribute, then we must be calling a function which has
12529 the (interfacearm) attribute. We look for the Thumb entry point to that
12530 function and change the branch to refer to that function instead. */
12531 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
12532 && fixP
->fx_addsy
!= NULL
12533 && S_IS_DEFINED (fixP
->fx_addsy
)
12534 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
12536 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
12542 arm_force_relocation (struct fix
* fixp
)
12544 #if defined (OBJ_COFF) && defined (TE_PE)
12545 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
12549 /* Resolve these relocations even if the symbol is extern or weak. */
12550 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
12551 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
12552 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
12553 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
12554 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
12555 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
12558 return generic_force_reloc (fixp
);
12562 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
12563 local labels from being added to the output symbol table when they
12564 are used with the ADRL pseudo op. The ADRL relocation should always
12565 be resolved before the binbary is emitted, so it is safe to say that
12566 it is adjustable. */
12569 arm_fix_adjustable (fixS
* fixP
)
12571 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
12578 /* Relocations against Thumb function names must be left unadjusted,
12579 so that the linker can use this information to correctly set the
12580 bottom bit of their addresses. The MIPS version of this function
12581 also prevents relocations that are mips-16 specific, but I do not
12582 know why it does this.
12585 There is one other problem that ought to be addressed here, but
12586 which currently is not: Taking the address of a label (rather
12587 than a function) and then later jumping to that address. Such
12588 addresses also ought to have their bottom bit set (assuming that
12589 they reside in Thumb code), but at the moment they will not. */
12592 arm_fix_adjustable (fixS
* fixP
)
12594 if (fixP
->fx_addsy
== NULL
)
12597 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
12598 && fixP
->fx_subsy
== NULL
)
12601 /* We need the symbol name for the VTABLE entries. */
12602 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12603 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12606 /* Don't allow symbols to be discarded on GOT related relocs. */
12607 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
12608 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
12609 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
12610 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
12611 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
12612 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
12613 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
12614 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
12615 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
12622 elf32_arm_target_format (void)
12625 return (target_big_endian
12626 ? "elf32-bigarm-symbian"
12627 : "elf32-littlearm-symbian");
12628 #elif defined (TE_VXWORKS)
12629 return (target_big_endian
12630 ? "elf32-bigarm-vxworks"
12631 : "elf32-littlearm-vxworks");
12633 if (target_big_endian
)
12634 return "elf32-bigarm";
12636 return "elf32-littlearm";
12641 armelf_frob_symbol (symbolS
* symp
,
12644 elf_frob_symbol (symp
, puntp
);
12648 /* MD interface: Finalization. */
12650 /* A good place to do this, although this was probably not intended
12651 for this kind of use. We need to dump the literal pool before
12652 references are made to a null symbol pointer. */
12657 literal_pool
* pool
;
12659 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
12661 /* Put it at the end of the relevent section. */
12662 subseg_set (pool
->section
, pool
->sub_section
);
12664 arm_elf_change_section ();
12670 /* Adjust the symbol table. This marks Thumb symbols as distinct from
12674 arm_adjust_symtab (void)
12679 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
12681 if (ARM_IS_THUMB (sym
))
12683 if (THUMB_IS_FUNC (sym
))
12685 /* Mark the symbol as a Thumb function. */
12686 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
12687 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
12688 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
12690 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
12691 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
12693 as_bad (_("%s: unexpected function type: %d"),
12694 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
12696 else switch (S_GET_STORAGE_CLASS (sym
))
12699 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
12702 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
12705 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
12713 if (ARM_IS_INTERWORK (sym
))
12714 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
12721 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
12723 if (ARM_IS_THUMB (sym
))
12725 elf_symbol_type
* elf_sym
;
12727 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
12728 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
12730 if (! bfd_is_arm_mapping_symbol_name (elf_sym
->symbol
.name
))
12732 /* If it's a .thumb_func, declare it as so,
12733 otherwise tag label as .code 16. */
12734 if (THUMB_IS_FUNC (sym
))
12735 elf_sym
->internal_elf_sym
.st_info
=
12736 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
12738 elf_sym
->internal_elf_sym
.st_info
=
12739 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
12746 /* MD interface: Initialization. */
12749 set_constant_flonums (void)
12753 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
12754 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
12764 if ( (arm_ops_hsh
= hash_new ()) == NULL
12765 || (arm_cond_hsh
= hash_new ()) == NULL
12766 || (arm_shift_hsh
= hash_new ()) == NULL
12767 || (arm_psr_hsh
= hash_new ()) == NULL
12768 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
12769 || (arm_reg_hsh
= hash_new ()) == NULL
12770 || (arm_reloc_hsh
= hash_new ()) == NULL
12771 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
12772 as_fatal (_("virtual memory exhausted"));
12774 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
12775 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
12776 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
12777 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
12778 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
12779 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
12780 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
12781 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
12782 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
12783 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
12784 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
12785 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
12787 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
12789 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
12790 (PTR
) (barrier_opt_names
+ i
));
12792 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
12793 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
12796 set_constant_flonums ();
12798 /* Set the cpu variant based on the command-line options. We prefer
12799 -mcpu= over -march= if both are set (as for GCC); and we prefer
12800 -mfpu= over any other way of setting the floating point unit.
12801 Use of legacy options with new options are faulted. */
12804 if (mcpu_cpu_opt
|| march_cpu_opt
)
12805 as_bad (_("use of old and new-style options to set CPU type"));
12807 mcpu_cpu_opt
= legacy_cpu
;
12809 else if (!mcpu_cpu_opt
)
12810 mcpu_cpu_opt
= march_cpu_opt
;
12815 as_bad (_("use of old and new-style options to set FPU type"));
12817 mfpu_opt
= legacy_fpu
;
12819 else if (!mfpu_opt
)
12821 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
12822 /* Some environments specify a default FPU. If they don't, infer it
12823 from the processor. */
12825 mfpu_opt
= mcpu_fpu_opt
;
12827 mfpu_opt
= march_fpu_opt
;
12829 mfpu_opt
= &fpu_default
;
12836 mfpu_opt
= &fpu_default
;
12837 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
12838 mfpu_opt
= &fpu_arch_vfp_v2
;
12840 mfpu_opt
= &fpu_arch_fpa
;
12846 mcpu_cpu_opt
= &cpu_default
;
12847 selected_cpu
= cpu_default
;
12851 selected_cpu
= *mcpu_cpu_opt
;
12853 mcpu_cpu_opt
= &arm_arch_any
;
12856 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
12858 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
12860 #if defined OBJ_COFF || defined OBJ_ELF
12862 unsigned int flags
= 0;
12864 #if defined OBJ_ELF
12865 flags
= meabi_flags
;
12867 switch (meabi_flags
)
12869 case EF_ARM_EABI_UNKNOWN
:
12871 /* Set the flags in the private structure. */
12872 if (uses_apcs_26
) flags
|= F_APCS26
;
12873 if (support_interwork
) flags
|= F_INTERWORK
;
12874 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
12875 if (pic_code
) flags
|= F_PIC
;
12876 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
12877 flags
|= F_SOFT_FLOAT
;
12879 switch (mfloat_abi_opt
)
12881 case ARM_FLOAT_ABI_SOFT
:
12882 case ARM_FLOAT_ABI_SOFTFP
:
12883 flags
|= F_SOFT_FLOAT
;
12886 case ARM_FLOAT_ABI_HARD
:
12887 if (flags
& F_SOFT_FLOAT
)
12888 as_bad (_("hard-float conflicts with specified fpu"));
12892 /* Using pure-endian doubles (even if soft-float). */
12893 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
12894 flags
|= F_VFP_FLOAT
;
12896 #if defined OBJ_ELF
12897 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
12898 flags
|= EF_ARM_MAVERICK_FLOAT
;
12901 case EF_ARM_EABI_VER4
:
12902 case EF_ARM_EABI_VER5
:
12903 /* No additional flags to set. */
12910 bfd_set_private_flags (stdoutput
, flags
);
12912 /* We have run out flags in the COFF header to encode the
12913 status of ATPCS support, so instead we create a dummy,
12914 empty, debug section called .arm.atpcs. */
12919 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
12923 bfd_set_section_flags
12924 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
12925 bfd_set_section_size (stdoutput
, sec
, 0);
12926 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
12932 /* Record the CPU type as well. */
12933 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
12934 mach
= bfd_mach_arm_iWMMXt
;
12935 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
12936 mach
= bfd_mach_arm_XScale
;
12937 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
12938 mach
= bfd_mach_arm_ep9312
;
12939 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
12940 mach
= bfd_mach_arm_5TE
;
12941 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
12943 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
12944 mach
= bfd_mach_arm_5T
;
12946 mach
= bfd_mach_arm_5
;
12948 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
12950 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
12951 mach
= bfd_mach_arm_4T
;
12953 mach
= bfd_mach_arm_4
;
12955 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
12956 mach
= bfd_mach_arm_3M
;
12957 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
12958 mach
= bfd_mach_arm_3
;
12959 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
12960 mach
= bfd_mach_arm_2a
;
12961 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
12962 mach
= bfd_mach_arm_2
;
12964 mach
= bfd_mach_arm_unknown
;
12966 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
12969 /* Command line processing. */
12972 Invocation line includes a switch not recognized by the base assembler.
12973 See if it's a processor-specific option.
12975 This routine is somewhat complicated by the need for backwards
12976 compatibility (since older releases of gcc can't be changed).
12977 The new options try to make the interface as compatible as
12980 New options (supported) are:
12982 -mcpu=<cpu name> Assemble for selected processor
12983 -march=<architecture name> Assemble for selected architecture
12984 -mfpu=<fpu architecture> Assemble for selected FPU.
12985 -EB/-mbig-endian Big-endian
12986 -EL/-mlittle-endian Little-endian
12987 -k Generate PIC code
12988 -mthumb Start in Thumb mode
12989 -mthumb-interwork Code supports ARM/Thumb interworking
12991 For now we will also provide support for:
12993 -mapcs-32 32-bit Program counter
12994 -mapcs-26 26-bit Program counter
12995 -macps-float Floats passed in FP registers
12996 -mapcs-reentrant Reentrant code
12998 (sometime these will probably be replaced with -mapcs=<list of options>
12999 and -matpcs=<list of options>)
13001 The remaining options are only supported for back-wards compatibility.
13002 Cpu variants, the arm part is optional:
13003 -m[arm]1 Currently not supported.
13004 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
13005 -m[arm]3 Arm 3 processor
13006 -m[arm]6[xx], Arm 6 processors
13007 -m[arm]7[xx][t][[d]m] Arm 7 processors
13008 -m[arm]8[10] Arm 8 processors
13009 -m[arm]9[20][tdmi] Arm 9 processors
13010 -mstrongarm[110[0]] StrongARM processors
13011 -mxscale XScale processors
13012 -m[arm]v[2345[t[e]]] Arm architectures
13013 -mall All (except the ARM1)
13015 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
13016 -mfpe-old (No float load/store multiples)
13017 -mvfpxd VFP Single precision
13019 -mno-fpu Disable all floating point instructions
13021 The following CPU names are recognized:
13022 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
13023 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
13024 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
13025 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
13026 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
13027 arm10t arm10e, arm1020t, arm1020e, arm10200e,
13028 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
13032 const char * md_shortopts
= "m:k";
13034 #ifdef ARM_BI_ENDIAN
13035 #define OPTION_EB (OPTION_MD_BASE + 0)
13036 #define OPTION_EL (OPTION_MD_BASE + 1)
13038 #if TARGET_BYTES_BIG_ENDIAN
13039 #define OPTION_EB (OPTION_MD_BASE + 0)
13041 #define OPTION_EL (OPTION_MD_BASE + 1)
13045 struct option md_longopts
[] =
13048 {"EB", no_argument
, NULL
, OPTION_EB
},
13051 {"EL", no_argument
, NULL
, OPTION_EL
},
13053 {NULL
, no_argument
, NULL
, 0}
13056 size_t md_longopts_size
= sizeof (md_longopts
);
13058 struct arm_option_table
13060 char *option
; /* Option name to match. */
13061 char *help
; /* Help information. */
13062 int *var
; /* Variable to change. */
13063 int value
; /* What to change it to. */
13064 char *deprecated
; /* If non-null, print this message. */
13067 struct arm_option_table arm_opts
[] =
13069 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
13070 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
13071 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
13072 &support_interwork
, 1, NULL
},
13073 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
13074 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
13075 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
13077 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
13078 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
13079 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
13080 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
13083 /* These are recognized by the assembler, but have no affect on code. */
13084 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
13085 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
13086 {NULL
, NULL
, NULL
, 0, NULL
}
13089 struct arm_legacy_option_table
13091 char *option
; /* Option name to match. */
13092 const arm_feature_set
**var
; /* Variable to change. */
13093 const arm_feature_set value
; /* What to change it to. */
13094 char *deprecated
; /* If non-null, print this message. */
13097 const struct arm_legacy_option_table arm_legacy_opts
[] =
13099 /* DON'T add any new processors to this list -- we want the whole list
13100 to go away... Add them to the processors table instead. */
13101 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
13102 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
13103 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
13104 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
13105 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
13106 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
13107 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
13108 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
13109 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
13110 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
13111 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
13112 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
13113 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
13114 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
13115 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
13116 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
13117 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
13118 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
13119 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
13120 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
13121 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
13122 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
13123 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
13124 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
13125 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
13126 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
13127 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
13128 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
13129 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
13130 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
13131 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
13132 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
13133 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
13134 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
13135 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
13136 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
13137 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
13138 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
13139 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
13140 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
13141 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
13142 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
13143 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
13144 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
13145 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
13146 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
13147 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
13148 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
13149 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
13150 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
13151 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
13152 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
13153 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
13154 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
13155 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
13156 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
13157 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
13158 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
13159 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
13160 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
13161 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
13162 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
13163 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
13164 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
13165 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
13166 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
13167 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
13168 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
13169 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
13170 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
13171 N_("use -mcpu=strongarm110")},
13172 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
13173 N_("use -mcpu=strongarm1100")},
13174 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
13175 N_("use -mcpu=strongarm1110")},
13176 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
13177 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
13178 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
13180 /* Architecture variants -- don't add any more to this list either. */
13181 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
13182 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
13183 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
13184 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
13185 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
13186 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
13187 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
13188 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
13189 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
13190 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
13191 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
13192 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
13193 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
13194 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
13195 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
13196 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
13197 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
13198 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
13200 /* Floating point variants -- don't add any more to this list either. */
13201 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
13202 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
13203 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
13204 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
13205 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
13207 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
13210 struct arm_cpu_option_table
13213 const arm_feature_set value
;
13214 /* For some CPUs we assume an FPU unless the user explicitly sets
13216 const arm_feature_set default_fpu
;
13217 /* The canonical name of the CPU, or NULL to use NAME converted to upper
13219 const char *canonical_name
;
13222 /* This list should, at a minimum, contain all the cpu names
13223 recognized by GCC. */
13224 static const struct arm_cpu_option_table arm_cpus
[] =
13226 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
13227 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
13228 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
13229 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
13230 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
13231 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13232 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13233 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13234 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13235 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13236 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13237 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
13238 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13239 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
13240 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13241 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
13242 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13243 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13244 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13245 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13246 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13247 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13248 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13249 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13250 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13251 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13252 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13253 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
13254 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13255 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13256 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13257 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
13258 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
13259 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
13260 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
13261 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
13262 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
13263 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
13264 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13265 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
13266 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13267 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13268 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13269 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
13270 /* For V5 or later processors we default to using VFP; but the user
13271 should really set the FPU type explicitly. */
13272 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
13273 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
13274 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
13275 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
13276 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
13277 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
13278 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
13279 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
13280 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
13281 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
13282 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
13283 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
13284 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
13285 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
13286 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
13287 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
13288 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
13289 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
13290 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
13291 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
13292 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
13293 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
13294 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
13295 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
13296 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
13297 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
13298 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
13299 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
13300 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
13301 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
13302 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
13303 {"cortex-a8", ARM_ARCH_V7A
, FPU_ARCH_VFP_V2
, NULL
},
13304 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
13305 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
13306 /* ??? XSCALE is really an architecture. */
13307 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
13308 /* ??? iwmmxt is not a processor. */
13309 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
13310 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
13312 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
13313 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
13316 struct arm_arch_option_table
13319 const arm_feature_set value
;
13320 const arm_feature_set default_fpu
;
13323 /* This list should, at a minimum, contain all the architecture names
13324 recognized by GCC. */
13325 static const struct arm_arch_option_table arm_archs
[] =
13327 {"all", ARM_ANY
, FPU_ARCH_FPA
},
13328 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
13329 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
13330 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
13331 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
13332 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
13333 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
13334 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
13335 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
13336 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
13337 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
13338 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
13339 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
13340 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
13341 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
13342 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
13343 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
13344 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
13345 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
13346 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
13347 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
13348 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
13349 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
13350 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
13351 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
13352 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
13353 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
13354 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
13355 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
13356 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
13357 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
13358 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
13359 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
13362 /* ISA extensions in the co-processor space. */
13363 struct arm_option_cpu_value_table
13366 const arm_feature_set value
;
13369 static const struct arm_option_cpu_value_table arm_extensions
[] =
13371 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
13372 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
13373 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
13374 {NULL
, ARM_ARCH_NONE
}
13377 /* This list should, at a minimum, contain all the fpu names
13378 recognized by GCC. */
13379 static const struct arm_option_cpu_value_table arm_fpus
[] =
13381 {"softfpa", FPU_NONE
},
13382 {"fpe", FPU_ARCH_FPE
},
13383 {"fpe2", FPU_ARCH_FPE
},
13384 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
13385 {"fpa", FPU_ARCH_FPA
},
13386 {"fpa10", FPU_ARCH_FPA
},
13387 {"fpa11", FPU_ARCH_FPA
},
13388 {"arm7500fe", FPU_ARCH_FPA
},
13389 {"softvfp", FPU_ARCH_VFP
},
13390 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
13391 {"vfp", FPU_ARCH_VFP_V2
},
13392 {"vfp9", FPU_ARCH_VFP_V2
},
13393 {"vfp10", FPU_ARCH_VFP_V2
},
13394 {"vfp10-r0", FPU_ARCH_VFP_V1
},
13395 {"vfpxd", FPU_ARCH_VFP_V1xD
},
13396 {"arm1020t", FPU_ARCH_VFP_V1
},
13397 {"arm1020e", FPU_ARCH_VFP_V2
},
13398 {"arm1136jfs", FPU_ARCH_VFP_V2
},
13399 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
13400 {"maverick", FPU_ARCH_MAVERICK
},
13401 {NULL
, ARM_ARCH_NONE
}
13404 struct arm_option_value_table
13410 static const struct arm_option_value_table arm_float_abis
[] =
13412 {"hard", ARM_FLOAT_ABI_HARD
},
13413 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
13414 {"soft", ARM_FLOAT_ABI_SOFT
},
13419 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
13420 static const struct arm_option_value_table arm_eabis
[] =
13422 {"gnu", EF_ARM_EABI_UNKNOWN
},
13423 {"4", EF_ARM_EABI_VER4
},
13424 {"5", EF_ARM_EABI_VER5
},
13429 struct arm_long_option_table
13431 char * option
; /* Substring to match. */
13432 char * help
; /* Help information. */
13433 int (* func
) (char * subopt
); /* Function to decode sub-option. */
13434 char * deprecated
; /* If non-null, print this message. */
13438 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
13440 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
13442 /* Copy the feature set, so that we can modify it. */
13443 *ext_set
= **opt_p
;
13446 while (str
!= NULL
&& *str
!= 0)
13448 const struct arm_option_cpu_value_table
* opt
;
13454 as_bad (_("invalid architectural extension"));
13459 ext
= strchr (str
, '+');
13462 optlen
= ext
- str
;
13464 optlen
= strlen (str
);
13468 as_bad (_("missing architectural extension"));
13472 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
13473 if (strncmp (opt
->name
, str
, optlen
) == 0)
13475 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
13479 if (opt
->name
== NULL
)
13481 as_bad (_("unknown architectural extnsion `%s'"), str
);
13492 arm_parse_cpu (char * str
)
13494 const struct arm_cpu_option_table
* opt
;
13495 char * ext
= strchr (str
, '+');
13499 optlen
= ext
- str
;
13501 optlen
= strlen (str
);
13505 as_bad (_("missing cpu name `%s'"), str
);
13509 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
13510 if (strncmp (opt
->name
, str
, optlen
) == 0)
13512 mcpu_cpu_opt
= &opt
->value
;
13513 mcpu_fpu_opt
= &opt
->default_fpu
;
13514 if (opt
->canonical_name
)
13515 strcpy(selected_cpu_name
, opt
->canonical_name
);
13519 for (i
= 0; i
< optlen
; i
++)
13520 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
13521 selected_cpu_name
[i
] = 0;
13525 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
13530 as_bad (_("unknown cpu `%s'"), str
);
13535 arm_parse_arch (char * str
)
13537 const struct arm_arch_option_table
*opt
;
13538 char *ext
= strchr (str
, '+');
13542 optlen
= ext
- str
;
13544 optlen
= strlen (str
);
13548 as_bad (_("missing architecture name `%s'"), str
);
13552 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
13553 if (streq (opt
->name
, str
))
13555 march_cpu_opt
= &opt
->value
;
13556 march_fpu_opt
= &opt
->default_fpu
;
13557 strcpy(selected_cpu_name
, opt
->name
);
13560 return arm_parse_extension (ext
, &march_cpu_opt
);
13565 as_bad (_("unknown architecture `%s'\n"), str
);
13570 arm_parse_fpu (char * str
)
13572 const struct arm_option_cpu_value_table
* opt
;
13574 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
13575 if (streq (opt
->name
, str
))
13577 mfpu_opt
= &opt
->value
;
13581 as_bad (_("unknown floating point format `%s'\n"), str
);
13586 arm_parse_float_abi (char * str
)
13588 const struct arm_option_value_table
* opt
;
13590 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
13591 if (streq (opt
->name
, str
))
13593 mfloat_abi_opt
= opt
->value
;
13597 as_bad (_("unknown floating point abi `%s'\n"), str
);
13603 arm_parse_eabi (char * str
)
13605 const struct arm_option_value_table
*opt
;
13607 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
13608 if (streq (opt
->name
, str
))
13610 meabi_flags
= opt
->value
;
13613 as_bad (_("unknown EABI `%s'\n"), str
);
13618 struct arm_long_option_table arm_long_opts
[] =
13620 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
13621 arm_parse_cpu
, NULL
},
13622 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
13623 arm_parse_arch
, NULL
},
13624 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
13625 arm_parse_fpu
, NULL
},
13626 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
13627 arm_parse_float_abi
, NULL
},
13629 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
13630 arm_parse_eabi
, NULL
},
13632 {NULL
, NULL
, 0, NULL
}
13636 md_parse_option (int c
, char * arg
)
13638 struct arm_option_table
*opt
;
13639 const struct arm_legacy_option_table
*fopt
;
13640 struct arm_long_option_table
*lopt
;
13646 target_big_endian
= 1;
13652 target_big_endian
= 0;
13657 /* Listing option. Just ignore these, we don't support additional
13662 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
13664 if (c
== opt
->option
[0]
13665 && ((arg
== NULL
&& opt
->option
[1] == 0)
13666 || streq (arg
, opt
->option
+ 1)))
13668 #if WARN_DEPRECATED
13669 /* If the option is deprecated, tell the user. */
13670 if (opt
->deprecated
!= NULL
)
13671 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
13672 arg
? arg
: "", _(opt
->deprecated
));
13675 if (opt
->var
!= NULL
)
13676 *opt
->var
= opt
->value
;
13682 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
13684 if (c
== fopt
->option
[0]
13685 && ((arg
== NULL
&& fopt
->option
[1] == 0)
13686 || streq (arg
, fopt
->option
+ 1)))
13688 #if WARN_DEPRECATED
13689 /* If the option is deprecated, tell the user. */
13690 if (fopt
->deprecated
!= NULL
)
13691 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
13692 arg
? arg
: "", _(fopt
->deprecated
));
13695 if (fopt
->var
!= NULL
)
13696 *fopt
->var
= &fopt
->value
;
13702 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
13704 /* These options are expected to have an argument. */
13705 if (c
== lopt
->option
[0]
13707 && strncmp (arg
, lopt
->option
+ 1,
13708 strlen (lopt
->option
+ 1)) == 0)
13710 #if WARN_DEPRECATED
13711 /* If the option is deprecated, tell the user. */
13712 if (lopt
->deprecated
!= NULL
)
13713 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
13714 _(lopt
->deprecated
));
13717 /* Call the sup-option parser. */
13718 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
13729 md_show_usage (FILE * fp
)
13731 struct arm_option_table
*opt
;
13732 struct arm_long_option_table
*lopt
;
13734 fprintf (fp
, _(" ARM-specific assembler options:\n"));
13736 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
13737 if (opt
->help
!= NULL
)
13738 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
13740 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
13741 if (lopt
->help
!= NULL
)
13742 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
13746 -EB assemble code for a big-endian cpu\n"));
13751 -EL assemble code for a little-endian cpu\n"));
13760 arm_feature_set flags
;
13761 } cpu_arch_ver_table
;
13763 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
13764 least features first. */
13765 static const cpu_arch_ver_table cpu_arch_ver
[] =
13770 {4, ARM_ARCH_V5TE
},
13771 {5, ARM_ARCH_V5TEJ
},
13775 {9, ARM_ARCH_V6T2
},
13776 {10, ARM_ARCH_V7A
},
13777 {10, ARM_ARCH_V7R
},
13778 {10, ARM_ARCH_V7M
},
13782 /* Set the public EABI object attributes. */
13784 aeabi_set_public_attributes (void)
13787 arm_feature_set flags
;
13788 arm_feature_set tmp
;
13789 const cpu_arch_ver_table
*p
;
13791 /* Choose the architecture based on the capabilities of the requested cpu
13792 (if any) and/or the instructions actually used. */
13793 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
13794 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
13795 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
13799 for (p
= cpu_arch_ver
; p
->val
; p
++)
13801 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
13804 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
13808 /* Tag_CPU_name. */
13809 if (selected_cpu_name
[0])
13813 p
= selected_cpu_name
;
13814 if (strncmp(p
, "armv", 4) == 0)
13819 for (i
= 0; p
[i
]; i
++)
13820 p
[i
] = TOUPPER (p
[i
]);
13822 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
13824 /* Tag_CPU_arch. */
13825 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
13826 /* Tag_CPU_arch_profile. */
13827 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
13828 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
13829 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
13830 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
13831 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
13832 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
13833 /* Tag_ARM_ISA_use. */
13834 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
13835 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
13836 /* Tag_THUMB_ISA_use. */
13837 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
13838 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
13839 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
13840 /* Tag_VFP_arch. */
13841 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_arch_vfp_v2
)
13842 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_arch_vfp_v2
))
13843 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
13844 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_arch_vfp_v1
)
13845 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_arch_vfp_v1
))
13846 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
13847 /* Tag_WMMX_arch. */
13848 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
13849 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
13850 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
13853 /* Add the .ARM.attributes section. */
13862 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
13865 aeabi_set_public_attributes ();
13866 size
= elf32_arm_eabi_attr_size (stdoutput
);
13867 s
= subseg_new (".ARM.attributes", 0);
13868 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
13869 addr
= frag_now_fix ();
13870 p
= frag_more (size
);
13871 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
13875 /* Parse a .cpu directive. */
13878 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
13880 const struct arm_cpu_option_table
*opt
;
13884 name
= input_line_pointer
;
13885 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
13886 input_line_pointer
++;
13887 saved_char
= *input_line_pointer
;
13888 *input_line_pointer
= 0;
13890 /* Skip the first "all" entry. */
13891 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
13892 if (streq (opt
->name
, name
))
13894 mcpu_cpu_opt
= &opt
->value
;
13895 selected_cpu
= opt
->value
;
13896 if (opt
->canonical_name
)
13897 strcpy(selected_cpu_name
, opt
->canonical_name
);
13901 for (i
= 0; opt
->name
[i
]; i
++)
13902 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
13903 selected_cpu_name
[i
] = 0;
13905 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
13906 *input_line_pointer
= saved_char
;
13907 demand_empty_rest_of_line ();
13910 as_bad (_("unknown cpu `%s'"), name
);
13911 *input_line_pointer
= saved_char
;
13912 ignore_rest_of_line ();
13916 /* Parse a .arch directive. */
13919 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
13921 const struct arm_arch_option_table
*opt
;
13925 name
= input_line_pointer
;
13926 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
13927 input_line_pointer
++;
13928 saved_char
= *input_line_pointer
;
13929 *input_line_pointer
= 0;
13931 /* Skip the first "all" entry. */
13932 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
13933 if (streq (opt
->name
, name
))
13935 mcpu_cpu_opt
= &opt
->value
;
13936 selected_cpu
= opt
->value
;
13937 strcpy(selected_cpu_name
, opt
->name
);
13938 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
13939 *input_line_pointer
= saved_char
;
13940 demand_empty_rest_of_line ();
13944 as_bad (_("unknown architecture `%s'\n"), name
);
13945 *input_line_pointer
= saved_char
;
13946 ignore_rest_of_line ();
13950 /* Parse a .fpu directive. */
13953 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
13955 const struct arm_option_cpu_value_table
*opt
;
13959 name
= input_line_pointer
;
13960 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
13961 input_line_pointer
++;
13962 saved_char
= *input_line_pointer
;
13963 *input_line_pointer
= 0;
13965 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
13966 if (streq (opt
->name
, name
))
13968 mfpu_opt
= &opt
->value
;
13969 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
13970 *input_line_pointer
= saved_char
;
13971 demand_empty_rest_of_line ();
13975 as_bad (_("unknown floating point format `%s'\n"), name
);
13976 *input_line_pointer
= saved_char
;
13977 ignore_rest_of_line ();
13979 #endif /* OBJ_ELF */