1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
158 /* Understand CodeComposer Studio assembly syntax. */
159 bfd_boolean codecomposer_syntax
= FALSE
;
161 /* Variables that we set while parsing command-line options. Once all
162 options have been read we re-process these values to set the real
165 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
166 instead of -mcpu=arm1). */
167 static const arm_feature_set
*legacy_cpu
= NULL
;
168 static const arm_feature_set
*legacy_fpu
= NULL
;
170 /* CPU, extension and FPU feature bits selected by -mcpu. */
171 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
172 static arm_feature_set
*mcpu_ext_opt
= NULL
;
173 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
175 /* CPU, extension and FPU feature bits selected by -march. */
176 static const arm_feature_set
*march_cpu_opt
= NULL
;
177 static arm_feature_set
*march_ext_opt
= NULL
;
178 static const arm_feature_set
*march_fpu_opt
= NULL
;
180 /* Feature bits selected by -mfpu. */
181 static const arm_feature_set
*mfpu_opt
= NULL
;
183 /* Constants for known architecture features. */
184 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
185 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
186 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
187 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
188 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
189 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
190 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
192 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
194 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
197 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
200 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
201 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
202 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
203 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
204 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
205 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
206 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
207 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
208 static const arm_feature_set arm_ext_v4t_5
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
210 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
211 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
212 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
213 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
214 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
215 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
216 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
217 /* Only for compatability of hint instructions. */
218 static const arm_feature_set arm_ext_v6k_v6t2
=
219 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
220 static const arm_feature_set arm_ext_v6_notm
=
221 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
222 static const arm_feature_set arm_ext_v6_dsp
=
223 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
224 static const arm_feature_set arm_ext_barrier
=
225 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
226 static const arm_feature_set arm_ext_msr
=
227 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
228 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
229 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
230 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
231 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
233 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
235 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
236 static const arm_feature_set arm_ext_m
=
237 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
238 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
239 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
240 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
241 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
242 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
243 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
244 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
245 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
246 static const arm_feature_set arm_ext_v8m_main
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
248 static const arm_feature_set arm_ext_v8_1m_main
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
250 /* Instructions in ARMv8-M only found in M profile architectures. */
251 static const arm_feature_set arm_ext_v8m_m_only
=
252 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
253 static const arm_feature_set arm_ext_v6t2_v8m
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
255 /* Instructions shared between ARMv8-A and ARMv8-M. */
256 static const arm_feature_set arm_ext_atomics
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
259 /* DSP instructions Tag_DSP_extension refers to. */
260 static const arm_feature_set arm_ext_dsp
=
261 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
263 static const arm_feature_set arm_ext_ras
=
264 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
265 /* FP16 instructions. */
266 static const arm_feature_set arm_ext_fp16
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
268 static const arm_feature_set arm_ext_fp16_fml
=
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
270 static const arm_feature_set arm_ext_v8_2
=
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
272 static const arm_feature_set arm_ext_v8_3
=
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
274 static const arm_feature_set arm_ext_sb
=
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
276 static const arm_feature_set arm_ext_predres
=
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
278 static const arm_feature_set arm_ext_bf16
=
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
281 static const arm_feature_set arm_arch_any
= ARM_ANY
;
283 static const arm_feature_set fpu_any
= FPU_ANY
;
285 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
286 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
287 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
289 static const arm_feature_set arm_cext_iwmmxt2
=
290 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
291 static const arm_feature_set arm_cext_iwmmxt
=
292 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
293 static const arm_feature_set arm_cext_xscale
=
294 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
295 static const arm_feature_set arm_cext_maverick
=
296 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
297 static const arm_feature_set fpu_fpa_ext_v1
=
298 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
299 static const arm_feature_set fpu_fpa_ext_v2
=
300 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
301 static const arm_feature_set fpu_vfp_ext_v1xd
=
302 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
303 static const arm_feature_set fpu_vfp_ext_v1
=
304 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
305 static const arm_feature_set fpu_vfp_ext_v2
=
306 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
307 static const arm_feature_set fpu_vfp_ext_v3xd
=
308 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
309 static const arm_feature_set fpu_vfp_ext_v3
=
310 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
311 static const arm_feature_set fpu_vfp_ext_d32
=
312 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
313 static const arm_feature_set fpu_neon_ext_v1
=
314 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
315 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
316 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
317 static const arm_feature_set mve_ext
=
318 ARM_FEATURE_COPROC (FPU_MVE
);
319 static const arm_feature_set mve_fp_ext
=
320 ARM_FEATURE_COPROC (FPU_MVE_FP
);
322 static const arm_feature_set fpu_vfp_fp16
=
323 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
324 static const arm_feature_set fpu_neon_ext_fma
=
325 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
327 static const arm_feature_set fpu_vfp_ext_fma
=
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
329 static const arm_feature_set fpu_vfp_ext_armv8
=
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
331 static const arm_feature_set fpu_vfp_ext_armv8xd
=
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
333 static const arm_feature_set fpu_neon_ext_armv8
=
334 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
335 static const arm_feature_set fpu_crypto_ext_armv8
=
336 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
337 static const arm_feature_set crc_ext_armv8
=
338 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
339 static const arm_feature_set fpu_neon_ext_v8_1
=
340 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
341 static const arm_feature_set fpu_neon_ext_dotprod
=
342 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
344 static int mfloat_abi_opt
= -1;
345 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
347 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
348 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
350 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
351 /* Feature bits selected by the last -mcpu/-march or by the combination of the
352 last .cpu/.arch directive .arch_extension directives since that
354 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
355 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
356 static arm_feature_set selected_fpu
= FPU_NONE
;
357 /* Feature bits selected by the last .object_arch directive. */
358 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
359 /* Must be long enough to hold any of the names in arm_cpus. */
360 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
361 static char selected_cpu_name
[20];
363 extern FLONUM_TYPE generic_floating_point_number
;
365 /* Return if no cpu was selected on command-line. */
367 no_cpu_selected (void)
369 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
374 static int meabi_flags
= EABI_DEFAULT
;
376 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
379 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
384 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
389 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
390 symbolS
* GOT_symbol
;
393 /* 0: assemble for ARM,
394 1: assemble for Thumb,
395 2: assemble for Thumb even though target CPU does not support thumb
397 static int thumb_mode
= 0;
398 /* A value distinct from the possible values for thumb_mode that we
399 can use to record whether thumb_mode has been copied into the
400 tc_frag_data field of a frag. */
401 #define MODE_RECORDED (1 << 4)
403 /* Specifies the intrinsic IT insn behavior mode. */
404 enum implicit_it_mode
406 IMPLICIT_IT_MODE_NEVER
= 0x00,
407 IMPLICIT_IT_MODE_ARM
= 0x01,
408 IMPLICIT_IT_MODE_THUMB
= 0x02,
409 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
411 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
413 /* If unified_syntax is true, we are processing the new unified
414 ARM/Thumb syntax. Important differences from the old ARM mode:
416 - Immediate operands do not require a # prefix.
417 - Conditional affixes always appear at the end of the
418 instruction. (For backward compatibility, those instructions
419 that formerly had them in the middle, continue to accept them
421 - The IT instruction may appear, and if it does is validated
422 against subsequent conditional affixes. It does not generate
425 Important differences from the old Thumb mode:
427 - Immediate operands do not require a # prefix.
428 - Most of the V6T2 instructions are only available in unified mode.
429 - The .N and .W suffixes are recognized and honored (it is an error
430 if they cannot be honored).
431 - All instructions set the flags if and only if they have an 's' affix.
432 - Conditional affixes may be used. They are validated against
433 preceding IT instructions. Unlike ARM mode, you cannot use a
434 conditional affix except in the scope of an IT instruction. */
436 static bfd_boolean unified_syntax
= FALSE
;
438 /* An immediate operand can start with #, and ld*, st*, pld operands
439 can contain [ and ]. We need to tell APP not to elide whitespace
440 before a [, which can appear as the first operand for pld.
441 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
442 const char arm_symbol_chars
[] = "#[]{}";
458 enum neon_el_type type
;
462 #define NEON_MAX_TYPE_ELS 4
466 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
470 enum pred_instruction_type
476 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
477 if inside, should be the last one. */
478 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
479 i.e. BKPT and NOP. */
480 IT_INSN
, /* The IT insn has been parsed. */
481 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
482 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
483 a predication code. */
484 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
487 /* The maximum number of operands we need. */
488 #define ARM_IT_MAX_OPERANDS 6
489 #define ARM_IT_MAX_RELOCS 3
494 unsigned long instruction
;
498 /* "uncond_value" is set to the value in place of the conditional field in
499 unconditional versions of the instruction, or -1 if nothing is
502 struct neon_type vectype
;
503 /* This does not indicate an actual NEON instruction, only that
504 the mnemonic accepts neon-style type suffixes. */
506 /* Set to the opcode if the instruction needs relaxation.
507 Zero if the instruction is not relaxed. */
511 bfd_reloc_code_real_type type
;
514 } relocs
[ARM_IT_MAX_RELOCS
];
516 enum pred_instruction_type pred_insn_type
;
522 struct neon_type_el vectype
;
523 unsigned present
: 1; /* Operand present. */
524 unsigned isreg
: 1; /* Operand was a register. */
525 unsigned immisreg
: 2; /* .imm field is a second register.
526 0: imm, 1: gpr, 2: MVE Q-register. */
527 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
531 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
532 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
533 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
534 instructions. This allows us to disambiguate ARM <-> vector insns. */
535 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
536 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
537 unsigned isquad
: 1; /* Operand is SIMD quad register. */
538 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
539 unsigned iszr
: 1; /* Operand is ZR register. */
540 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
541 unsigned writeback
: 1; /* Operand has trailing ! */
542 unsigned preind
: 1; /* Preindexed address. */
543 unsigned postind
: 1; /* Postindexed address. */
544 unsigned negative
: 1; /* Index register was negated. */
545 unsigned shifted
: 1; /* Shift applied to operation. */
546 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
547 } operands
[ARM_IT_MAX_OPERANDS
];
550 static struct arm_it inst
;
552 #define NUM_FLOAT_VALS 8
554 const char * fp_const
[] =
556 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
559 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
569 #define CP_T_X 0x00008000
570 #define CP_T_Y 0x00400000
572 #define CONDS_BIT 0x00100000
573 #define LOAD_BIT 0x00100000
575 #define DOUBLE_LOAD_FLAG 0x00000001
579 const char * template_name
;
583 #define COND_ALWAYS 0xE
587 const char * template_name
;
591 struct asm_barrier_opt
593 const char * template_name
;
595 const arm_feature_set arch
;
598 /* The bit that distinguishes CPSR and SPSR. */
599 #define SPSR_BIT (1 << 22)
601 /* The individual PSR flag bits. */
602 #define PSR_c (1 << 16)
603 #define PSR_x (1 << 17)
604 #define PSR_s (1 << 18)
605 #define PSR_f (1 << 19)
610 bfd_reloc_code_real_type reloc
;
615 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
616 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
621 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
624 /* Bits for DEFINED field in neon_typed_alias. */
625 #define NTA_HASTYPE 1
626 #define NTA_HASINDEX 2
628 struct neon_typed_alias
630 unsigned char defined
;
632 struct neon_type_el eltype
;
635 /* ARM register categories. This includes coprocessor numbers and various
636 architecture extensions' registers. Each entry should have an error message
637 in reg_expected_msgs below. */
667 /* Structure for a hash table entry for a register.
668 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
669 information which states whether a vector type or index is specified (for a
670 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
676 unsigned char builtin
;
677 struct neon_typed_alias
* neon
;
680 /* Diagnostics used when we don't get a register of the expected type. */
681 const char * const reg_expected_msgs
[] =
683 [REG_TYPE_RN
] = N_("ARM register expected"),
684 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
685 [REG_TYPE_CN
] = N_("co-processor register expected"),
686 [REG_TYPE_FN
] = N_("FPA register expected"),
687 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
688 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
689 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
690 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
691 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
692 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
693 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
695 [REG_TYPE_VFC
] = N_("VFP system register expected"),
696 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
697 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
698 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
699 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
700 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
701 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
702 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
703 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
704 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
705 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
706 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
707 [REG_TYPE_RNB
] = N_("")
710 /* Some well known registers that we refer to directly elsewhere. */
716 /* ARM instructions take 4bytes in the object file, Thumb instructions
722 /* Basic string to match. */
723 const char * template_name
;
725 /* Parameters to instruction. */
726 unsigned int operands
[8];
728 /* Conditional tag - see opcode_lookup. */
729 unsigned int tag
: 4;
731 /* Basic instruction code. */
734 /* Thumb-format instruction code. */
737 /* Which architecture variant provides this instruction. */
738 const arm_feature_set
* avariant
;
739 const arm_feature_set
* tvariant
;
741 /* Function to call to encode instruction in ARM format. */
742 void (* aencode
) (void);
744 /* Function to call to encode instruction in Thumb format. */
745 void (* tencode
) (void);
747 /* Indicates whether this instruction may be vector predicated. */
748 unsigned int mayBeVecPred
: 1;
751 /* Defines for various bits that we will want to toggle. */
752 #define INST_IMMEDIATE 0x02000000
753 #define OFFSET_REG 0x02000000
754 #define HWOFFSET_IMM 0x00400000
755 #define SHIFT_BY_REG 0x00000010
756 #define PRE_INDEX 0x01000000
757 #define INDEX_UP 0x00800000
758 #define WRITE_BACK 0x00200000
759 #define LDM_TYPE_2_OR_3 0x00400000
760 #define CPSI_MMOD 0x00020000
762 #define LITERAL_MASK 0xf000f000
763 #define OPCODE_MASK 0xfe1fffff
764 #define V4_STR_BIT 0x00000020
765 #define VLDR_VMOV_SAME 0x0040f000
767 #define T2_SUBS_PC_LR 0xf3de8f00
769 #define DATA_OP_SHIFT 21
770 #define SBIT_SHIFT 20
772 #define T2_OPCODE_MASK 0xfe1fffff
773 #define T2_DATA_OP_SHIFT 21
774 #define T2_SBIT_SHIFT 20
776 #define A_COND_MASK 0xf0000000
777 #define A_PUSH_POP_OP_MASK 0x0fff0000
779 /* Opcodes for pushing/poping registers to/from the stack. */
780 #define A1_OPCODE_PUSH 0x092d0000
781 #define A2_OPCODE_PUSH 0x052d0004
782 #define A2_OPCODE_POP 0x049d0004
784 /* Codes to distinguish the arithmetic instructions. */
795 #define OPCODE_CMP 10
796 #define OPCODE_CMN 11
797 #define OPCODE_ORR 12
798 #define OPCODE_MOV 13
799 #define OPCODE_BIC 14
800 #define OPCODE_MVN 15
802 #define T2_OPCODE_AND 0
803 #define T2_OPCODE_BIC 1
804 #define T2_OPCODE_ORR 2
805 #define T2_OPCODE_ORN 3
806 #define T2_OPCODE_EOR 4
807 #define T2_OPCODE_ADD 8
808 #define T2_OPCODE_ADC 10
809 #define T2_OPCODE_SBC 11
810 #define T2_OPCODE_SUB 13
811 #define T2_OPCODE_RSB 14
813 #define T_OPCODE_MUL 0x4340
814 #define T_OPCODE_TST 0x4200
815 #define T_OPCODE_CMN 0x42c0
816 #define T_OPCODE_NEG 0x4240
817 #define T_OPCODE_MVN 0x43c0
819 #define T_OPCODE_ADD_R3 0x1800
820 #define T_OPCODE_SUB_R3 0x1a00
821 #define T_OPCODE_ADD_HI 0x4400
822 #define T_OPCODE_ADD_ST 0xb000
823 #define T_OPCODE_SUB_ST 0xb080
824 #define T_OPCODE_ADD_SP 0xa800
825 #define T_OPCODE_ADD_PC 0xa000
826 #define T_OPCODE_ADD_I8 0x3000
827 #define T_OPCODE_SUB_I8 0x3800
828 #define T_OPCODE_ADD_I3 0x1c00
829 #define T_OPCODE_SUB_I3 0x1e00
831 #define T_OPCODE_ASR_R 0x4100
832 #define T_OPCODE_LSL_R 0x4080
833 #define T_OPCODE_LSR_R 0x40c0
834 #define T_OPCODE_ROR_R 0x41c0
835 #define T_OPCODE_ASR_I 0x1000
836 #define T_OPCODE_LSL_I 0x0000
837 #define T_OPCODE_LSR_I 0x0800
839 #define T_OPCODE_MOV_I8 0x2000
840 #define T_OPCODE_CMP_I8 0x2800
841 #define T_OPCODE_CMP_LR 0x4280
842 #define T_OPCODE_MOV_HR 0x4600
843 #define T_OPCODE_CMP_HR 0x4500
845 #define T_OPCODE_LDR_PC 0x4800
846 #define T_OPCODE_LDR_SP 0x9800
847 #define T_OPCODE_STR_SP 0x9000
848 #define T_OPCODE_LDR_IW 0x6800
849 #define T_OPCODE_STR_IW 0x6000
850 #define T_OPCODE_LDR_IH 0x8800
851 #define T_OPCODE_STR_IH 0x8000
852 #define T_OPCODE_LDR_IB 0x7800
853 #define T_OPCODE_STR_IB 0x7000
854 #define T_OPCODE_LDR_RW 0x5800
855 #define T_OPCODE_STR_RW 0x5000
856 #define T_OPCODE_LDR_RH 0x5a00
857 #define T_OPCODE_STR_RH 0x5200
858 #define T_OPCODE_LDR_RB 0x5c00
859 #define T_OPCODE_STR_RB 0x5400
861 #define T_OPCODE_PUSH 0xb400
862 #define T_OPCODE_POP 0xbc00
864 #define T_OPCODE_BRANCH 0xe000
866 #define THUMB_SIZE 2 /* Size of thumb instruction. */
867 #define THUMB_PP_PC_LR 0x0100
868 #define THUMB_LOAD_BIT 0x0800
869 #define THUMB2_LOAD_BIT 0x00100000
871 #define BAD_SYNTAX _("syntax error")
872 #define BAD_ARGS _("bad arguments to instruction")
873 #define BAD_SP _("r13 not allowed here")
874 #define BAD_PC _("r15 not allowed here")
875 #define BAD_ODD _("Odd register not allowed here")
876 #define BAD_EVEN _("Even register not allowed here")
877 #define BAD_COND _("instruction cannot be conditional")
878 #define BAD_OVERLAP _("registers may not be the same")
879 #define BAD_HIREG _("lo register required")
880 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
881 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
882 #define BAD_BRANCH _("branch must be last instruction in IT block")
883 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
884 #define BAD_NOT_IT _("instruction not allowed in IT block")
885 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
886 #define BAD_FPU _("selected FPU does not support instruction")
887 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
888 #define BAD_OUT_VPT \
889 _("vector predicated instruction should be in VPT/VPST block")
890 #define BAD_IT_COND _("incorrect condition in IT block")
891 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
892 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
893 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
894 #define BAD_PC_ADDRESSING \
895 _("cannot use register index with PC-relative addressing")
896 #define BAD_PC_WRITEBACK \
897 _("cannot use writeback with PC-relative addressing")
898 #define BAD_RANGE _("branch out of range")
899 #define BAD_FP16 _("selected processor does not support fp16 instruction")
900 #define BAD_BF16 _("selected processor does not support bf16 instruction")
901 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
902 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
903 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
905 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
907 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
909 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
911 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
912 #define BAD_MVE_AUTO \
913 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
914 " use a valid -march or -mcpu option.")
915 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
916 "and source operands makes instruction UNPREDICTABLE")
917 #define BAD_EL_TYPE _("bad element type for instruction")
918 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
920 static struct hash_control
* arm_ops_hsh
;
921 static struct hash_control
* arm_cond_hsh
;
922 static struct hash_control
* arm_vcond_hsh
;
923 static struct hash_control
* arm_shift_hsh
;
924 static struct hash_control
* arm_psr_hsh
;
925 static struct hash_control
* arm_v7m_psr_hsh
;
926 static struct hash_control
* arm_reg_hsh
;
927 static struct hash_control
* arm_reloc_hsh
;
928 static struct hash_control
* arm_barrier_opt_hsh
;
930 /* Stuff needed to resolve the label ambiguity
939 symbolS
* last_label_seen
;
940 static int label_is_thumb_function_name
= FALSE
;
942 /* Literal pool structure. Held on a per-section
943 and per-sub-section basis. */
945 #define MAX_LITERAL_POOL_SIZE 1024
946 typedef struct literal_pool
948 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
949 unsigned int next_free_entry
;
955 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
957 struct literal_pool
* next
;
958 unsigned int alignment
;
961 /* Pointer to a linked list of literal pools. */
962 literal_pool
* list_of_pools
= NULL
;
964 typedef enum asmfunc_states
967 WAITING_ASMFUNC_NAME
,
971 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
974 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
976 static struct current_pred now_pred
;
980 now_pred_compatible (int cond
)
982 return (cond
& ~1) == (now_pred
.cc
& ~1);
986 conditional_insn (void)
988 return inst
.cond
!= COND_ALWAYS
;
991 static int in_pred_block (void);
993 static int handle_pred_state (void);
995 static void force_automatic_it_block_close (void);
997 static void it_fsm_post_encode (void);
999 #define set_pred_insn_type(type) \
1002 inst.pred_insn_type = type; \
1003 if (handle_pred_state () == FAIL) \
1008 #define set_pred_insn_type_nonvoid(type, failret) \
1011 inst.pred_insn_type = type; \
1012 if (handle_pred_state () == FAIL) \
1017 #define set_pred_insn_type_last() \
1020 if (inst.cond == COND_ALWAYS) \
1021 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1023 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1027 /* Toggle value[pos]. */
1028 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1032 /* This array holds the chars that always start a comment. If the
1033 pre-processor is disabled, these aren't very useful. */
1034 char arm_comment_chars
[] = "@";
1036 /* This array holds the chars that only start a comment at the beginning of
1037 a line. If the line seems to have the form '# 123 filename'
1038 .line and .file directives will appear in the pre-processed output. */
1039 /* Note that input_file.c hand checks for '#' at the beginning of the
1040 first line of the input file. This is because the compiler outputs
1041 #NO_APP at the beginning of its output. */
1042 /* Also note that comments like this one will always work. */
1043 const char line_comment_chars
[] = "#";
1045 char arm_line_separator_chars
[] = ";";
1047 /* Chars that can be used to separate mant
1048 from exp in floating point numbers. */
1049 const char EXP_CHARS
[] = "eE";
1051 /* Chars that mean this number is a floating point constant. */
1052 /* As in 0f12.456 */
1053 /* or 0d1.2345e12 */
1055 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1057 /* Prefix characters that indicate the start of an immediate
1059 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1061 /* Separator character handling. */
1063 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1065 enum fp_16bit_format
1067 ARM_FP16_FORMAT_IEEE
= 0x1,
1068 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1069 ARM_FP16_FORMAT_DEFAULT
= 0x3
1072 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1076 skip_past_char (char ** str
, char c
)
1078 /* PR gas/14987: Allow for whitespace before the expected character. */
1079 skip_whitespace (*str
);
1090 #define skip_past_comma(str) skip_past_char (str, ',')
1092 /* Arithmetic expressions (possibly involving symbols). */
1094 /* Return TRUE if anything in the expression is a bignum. */
1097 walk_no_bignums (symbolS
* sp
)
1099 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1102 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1104 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1105 || (symbol_get_value_expression (sp
)->X_op_symbol
1106 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1112 static bfd_boolean in_my_get_expression
= FALSE
;
1114 /* Third argument to my_get_expression. */
1115 #define GE_NO_PREFIX 0
1116 #define GE_IMM_PREFIX 1
1117 #define GE_OPT_PREFIX 2
1118 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1119 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1120 #define GE_OPT_PREFIX_BIG 3
1123 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1127 /* In unified syntax, all prefixes are optional. */
1129 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1132 switch (prefix_mode
)
1134 case GE_NO_PREFIX
: break;
1136 if (!is_immediate_prefix (**str
))
1138 inst
.error
= _("immediate expression requires a # prefix");
1144 case GE_OPT_PREFIX_BIG
:
1145 if (is_immediate_prefix (**str
))
1152 memset (ep
, 0, sizeof (expressionS
));
1154 save_in
= input_line_pointer
;
1155 input_line_pointer
= *str
;
1156 in_my_get_expression
= TRUE
;
1158 in_my_get_expression
= FALSE
;
1160 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1162 /* We found a bad or missing expression in md_operand(). */
1163 *str
= input_line_pointer
;
1164 input_line_pointer
= save_in
;
1165 if (inst
.error
== NULL
)
1166 inst
.error
= (ep
->X_op
== O_absent
1167 ? _("missing expression") :_("bad expression"));
1171 /* Get rid of any bignums now, so that we don't generate an error for which
1172 we can't establish a line number later on. Big numbers are never valid
1173 in instructions, which is where this routine is always called. */
1174 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1175 && (ep
->X_op
== O_big
1176 || (ep
->X_add_symbol
1177 && (walk_no_bignums (ep
->X_add_symbol
)
1179 && walk_no_bignums (ep
->X_op_symbol
))))))
1181 inst
.error
= _("invalid constant");
1182 *str
= input_line_pointer
;
1183 input_line_pointer
= save_in
;
1187 *str
= input_line_pointer
;
1188 input_line_pointer
= save_in
;
1192 /* Turn a string in input_line_pointer into a floating point constant
1193 of type TYPE, and store the appropriate bytes in *LITP. The number
1194 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1195 returned, or NULL on OK.
1197 Note that fp constants aren't represent in the normal way on the ARM.
1198 In big endian mode, things are as expected. However, in little endian
1199 mode fp constants are big-endian word-wise, and little-endian byte-wise
1200 within the words. For example, (double) 1.1 in big endian mode is
1201 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1202 the byte sequence 99 99 f1 3f 9a 99 99 99.
1204 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1207 md_atof (int type
, char * litP
, int * sizeP
)
1210 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1247 return _("Unrecognized or unsupported floating point constant");
1250 t
= atof_ieee (input_line_pointer
, type
, words
);
1252 input_line_pointer
= t
;
1253 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1255 if (target_big_endian
|| prec
== 1)
1256 for (i
= 0; i
< prec
; i
++)
1258 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1259 litP
+= sizeof (LITTLENUM_TYPE
);
1261 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1262 for (i
= prec
- 1; i
>= 0; i
--)
1264 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1265 litP
+= sizeof (LITTLENUM_TYPE
);
1268 /* For a 4 byte float the order of elements in `words' is 1 0.
1269 For an 8 byte float the order is 1 0 3 2. */
1270 for (i
= 0; i
< prec
; i
+= 2)
1272 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1273 sizeof (LITTLENUM_TYPE
));
1274 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1275 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1276 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1282 /* We handle all bad expressions here, so that we can report the faulty
1283 instruction in the error message. */
1286 md_operand (expressionS
* exp
)
1288 if (in_my_get_expression
)
1289 exp
->X_op
= O_illegal
;
1292 /* Immediate values. */
1295 /* Generic immediate-value read function for use in directives.
1296 Accepts anything that 'expression' can fold to a constant.
1297 *val receives the number. */
1300 immediate_for_directive (int *val
)
1303 exp
.X_op
= O_illegal
;
1305 if (is_immediate_prefix (*input_line_pointer
))
1307 input_line_pointer
++;
1311 if (exp
.X_op
!= O_constant
)
1313 as_bad (_("expected #constant"));
1314 ignore_rest_of_line ();
1317 *val
= exp
.X_add_number
;
1322 /* Register parsing. */
1324 /* Generic register parser. CCP points to what should be the
1325 beginning of a register name. If it is indeed a valid register
1326 name, advance CCP over it and return the reg_entry structure;
1327 otherwise return NULL. Does not issue diagnostics. */
1329 static struct reg_entry
*
1330 arm_reg_parse_multi (char **ccp
)
1334 struct reg_entry
*reg
;
1336 skip_whitespace (start
);
1338 #ifdef REGISTER_PREFIX
1339 if (*start
!= REGISTER_PREFIX
)
1343 #ifdef OPTIONAL_REGISTER_PREFIX
1344 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1349 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1354 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1356 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1366 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1367 enum arm_reg_type type
)
1369 /* Alternative syntaxes are accepted for a few register classes. */
1376 /* Generic coprocessor register names are allowed for these. */
1377 if (reg
&& reg
->type
== REG_TYPE_CN
)
1382 /* For backward compatibility, a bare number is valid here. */
1384 unsigned long processor
= strtoul (start
, ccp
, 10);
1385 if (*ccp
!= start
&& processor
<= 15)
1390 case REG_TYPE_MMXWC
:
1391 /* WC includes WCG. ??? I'm not sure this is true for all
1392 instructions that take WC registers. */
1393 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1404 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1405 return value is the register number or FAIL. */
1408 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1411 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1414 /* Do not allow a scalar (reg+index) to parse as a register. */
1415 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1418 if (reg
&& reg
->type
== type
)
1421 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1428 /* Parse a Neon type specifier. *STR should point at the leading '.'
1429 character. Does no verification at this stage that the type fits the opcode
1436 Can all be legally parsed by this function.
1438 Fills in neon_type struct pointer with parsed information, and updates STR
1439 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1440 type, FAIL if not. */
1443 parse_neon_type (struct neon_type
*type
, char **str
)
1450 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1452 enum neon_el_type thistype
= NT_untyped
;
1453 unsigned thissize
= -1u;
1460 /* Just a size without an explicit type. */
1464 switch (TOLOWER (*ptr
))
1466 case 'i': thistype
= NT_integer
; break;
1467 case 'f': thistype
= NT_float
; break;
1468 case 'p': thistype
= NT_poly
; break;
1469 case 's': thistype
= NT_signed
; break;
1470 case 'u': thistype
= NT_unsigned
; break;
1472 thistype
= NT_float
;
1477 thistype
= NT_bfloat
;
1478 switch (TOLOWER (*(++ptr
)))
1482 thissize
= strtoul (ptr
, &ptr
, 10);
1485 as_bad (_("bad size %d in type specifier"), thissize
);
1489 case '0': case '1': case '2': case '3': case '4':
1490 case '5': case '6': case '7': case '8': case '9':
1492 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1499 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1505 /* .f is an abbreviation for .f32. */
1506 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1511 thissize
= strtoul (ptr
, &ptr
, 10);
1513 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1516 as_bad (_("bad size %d in type specifier"), thissize
);
1524 type
->el
[type
->elems
].type
= thistype
;
1525 type
->el
[type
->elems
].size
= thissize
;
1530 /* Empty/missing type is not a successful parse. */
1531 if (type
->elems
== 0)
1539 /* Errors may be set multiple times during parsing or bit encoding
1540 (particularly in the Neon bits), but usually the earliest error which is set
1541 will be the most meaningful. Avoid overwriting it with later (cascading)
1542 errors by calling this function. */
1545 first_error (const char *err
)
1551 /* Parse a single type, e.g. ".s32", leading period included. */
1553 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1556 struct neon_type optype
;
1560 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1562 if (optype
.elems
== 1)
1563 *vectype
= optype
.el
[0];
1566 first_error (_("only one type should be specified for operand"));
1572 first_error (_("vector type expected"));
1584 /* Special meanings for indices (which have a range of 0-7), which will fit into
1587 #define NEON_ALL_LANES 15
1588 #define NEON_INTERLEAVE_LANES 14
1590 /* Record a use of the given feature. */
1592 record_feature_use (const arm_feature_set
*feature
)
1595 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1597 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1600 /* If the given feature available in the selected CPU, mark it as used.
1601 Returns TRUE iff feature is available. */
1603 mark_feature_used (const arm_feature_set
*feature
)
1606 /* Do not support the use of MVE only instructions when in auto-detection or
1608 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1609 && ARM_CPU_IS_ANY (cpu_variant
))
1611 first_error (BAD_MVE_AUTO
);
1614 /* Ensure the option is valid on the current architecture. */
1615 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1618 /* Add the appropriate architecture feature for the barrier option used.
1620 record_feature_use (feature
);
1625 /* Parse either a register or a scalar, with an optional type. Return the
1626 register number, and optionally fill in the actual type of the register
1627 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1628 type/index information in *TYPEINFO. */
1631 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1632 enum arm_reg_type
*rtype
,
1633 struct neon_typed_alias
*typeinfo
)
1636 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1637 struct neon_typed_alias atype
;
1638 struct neon_type_el parsetype
;
1642 atype
.eltype
.type
= NT_invtype
;
1643 atype
.eltype
.size
= -1;
1645 /* Try alternate syntax for some types of register. Note these are mutually
1646 exclusive with the Neon syntax extensions. */
1649 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1657 /* Undo polymorphism when a set of register types may be accepted. */
1658 if ((type
== REG_TYPE_NDQ
1659 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1660 || (type
== REG_TYPE_VFSD
1661 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1662 || (type
== REG_TYPE_NSDQ
1663 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1664 || reg
->type
== REG_TYPE_NQ
))
1665 || (type
== REG_TYPE_NSD
1666 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1667 || (type
== REG_TYPE_MMXWC
1668 && (reg
->type
== REG_TYPE_MMXWCG
)))
1669 type
= (enum arm_reg_type
) reg
->type
;
1671 if (type
== REG_TYPE_MQ
)
1673 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1676 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1679 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1681 first_error (_("expected MVE register [q0..q7]"));
1686 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1687 && (type
== REG_TYPE_NQ
))
1691 if (type
!= reg
->type
)
1697 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1699 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1701 first_error (_("can't redefine type for operand"));
1704 atype
.defined
|= NTA_HASTYPE
;
1705 atype
.eltype
= parsetype
;
1708 if (skip_past_char (&str
, '[') == SUCCESS
)
1710 if (type
!= REG_TYPE_VFD
1711 && !(type
== REG_TYPE_VFS
1712 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1713 && !(type
== REG_TYPE_NQ
1714 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1716 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1717 first_error (_("only D and Q registers may be indexed"));
1719 first_error (_("only D registers may be indexed"));
1723 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1725 first_error (_("can't change index for operand"));
1729 atype
.defined
|= NTA_HASINDEX
;
1731 if (skip_past_char (&str
, ']') == SUCCESS
)
1732 atype
.index
= NEON_ALL_LANES
;
1737 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1739 if (exp
.X_op
!= O_constant
)
1741 first_error (_("constant expression required"));
1745 if (skip_past_char (&str
, ']') == FAIL
)
1748 atype
.index
= exp
.X_add_number
;
1763 /* Like arm_reg_parse, but also allow the following extra features:
1764 - If RTYPE is non-zero, return the (possibly restricted) type of the
1765 register (e.g. Neon double or quad reg when either has been requested).
1766 - If this is a Neon vector type with additional type information, fill
1767 in the struct pointed to by VECTYPE (if non-NULL).
1768 This function will fault on encountering a scalar. */
1771 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1772 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1774 struct neon_typed_alias atype
;
1776 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1781 /* Do not allow regname(... to parse as a register. */
1785 /* Do not allow a scalar (reg+index) to parse as a register. */
1786 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1788 first_error (_("register operand expected, but got scalar"));
1793 *vectype
= atype
.eltype
;
1800 #define NEON_SCALAR_REG(X) ((X) >> 4)
1801 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1803 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1804 have enough information to be able to do a good job bounds-checking. So, we
1805 just do easy checks here, and do further checks later. */
1808 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1809 arm_reg_type reg_type
)
1813 struct neon_typed_alias atype
;
1816 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1834 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1837 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1839 first_error (_("scalar must have an index"));
1842 else if (atype
.index
>= reg_size
/ elsize
)
1844 first_error (_("scalar index out of range"));
1849 *type
= atype
.eltype
;
1853 return reg
* 16 + atype
.index
;
1856 /* Types of registers in a list. */
1869 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1872 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1878 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1880 /* We come back here if we get ranges concatenated by '+' or '|'. */
1883 skip_whitespace (str
);
1896 const char apsr_str
[] = "apsr";
1897 int apsr_str_len
= strlen (apsr_str
);
1899 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1900 if (etype
== REGLIST_CLRM
)
1902 if (reg
== REG_SP
|| reg
== REG_PC
)
1904 else if (reg
== FAIL
1905 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1906 && !ISALPHA (*(str
+ apsr_str_len
)))
1909 str
+= apsr_str_len
;
1914 first_error (_("r0-r12, lr or APSR expected"));
1918 else /* etype == REGLIST_RN. */
1922 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1933 first_error (_("bad range in register list"));
1937 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1939 if (range
& (1 << i
))
1941 (_("Warning: duplicated register (r%d) in register list"),
1949 if (range
& (1 << reg
))
1950 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1952 else if (reg
<= cur_reg
)
1953 as_tsktsk (_("Warning: register range not in ascending order"));
1958 while (skip_past_comma (&str
) != FAIL
1959 || (in_range
= 1, *str
++ == '-'));
1962 if (skip_past_char (&str
, '}') == FAIL
)
1964 first_error (_("missing `}'"));
1968 else if (etype
== REGLIST_RN
)
1972 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1975 if (exp
.X_op
== O_constant
)
1977 if (exp
.X_add_number
1978 != (exp
.X_add_number
& 0x0000ffff))
1980 inst
.error
= _("invalid register mask");
1984 if ((range
& exp
.X_add_number
) != 0)
1986 int regno
= range
& exp
.X_add_number
;
1989 regno
= (1 << regno
) - 1;
1991 (_("Warning: duplicated register (r%d) in register list"),
1995 range
|= exp
.X_add_number
;
1999 if (inst
.relocs
[0].type
!= 0)
2001 inst
.error
= _("expression too complex");
2005 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2006 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2007 inst
.relocs
[0].pc_rel
= 0;
2011 if (*str
== '|' || *str
== '+')
2017 while (another_range
);
2023 /* Parse a VFP register list. If the string is invalid return FAIL.
2024 Otherwise return the number of registers, and set PBASE to the first
2025 register. Parses registers of type ETYPE.
2026 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2027 - Q registers can be used to specify pairs of D registers
2028 - { } can be omitted from around a singleton register list
2029 FIXME: This is not implemented, as it would require backtracking in
2032 This could be done (the meaning isn't really ambiguous), but doesn't
2033 fit in well with the current parsing framework.
2034 - 32 D registers may be used (also true for VFPv3).
2035 FIXME: Types are ignored in these register lists, which is probably a
2039 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2040 bfd_boolean
*partial_match
)
2045 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2049 unsigned long mask
= 0;
2051 bfd_boolean vpr_seen
= FALSE
;
2052 bfd_boolean expect_vpr
=
2053 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2055 if (skip_past_char (&str
, '{') == FAIL
)
2057 inst
.error
= _("expecting {");
2064 case REGLIST_VFP_S_VPR
:
2065 regtype
= REG_TYPE_VFS
;
2070 case REGLIST_VFP_D_VPR
:
2071 regtype
= REG_TYPE_VFD
;
2074 case REGLIST_NEON_D
:
2075 regtype
= REG_TYPE_NDQ
;
2082 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2084 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2085 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2089 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2092 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2099 base_reg
= max_regs
;
2100 *partial_match
= FALSE
;
2104 int setmask
= 1, addregs
= 1;
2105 const char vpr_str
[] = "vpr";
2106 int vpr_str_len
= strlen (vpr_str
);
2108 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2112 if (new_base
== FAIL
2113 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2114 && !ISALPHA (*(str
+ vpr_str_len
))
2120 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2124 first_error (_("VPR expected last"));
2127 else if (new_base
== FAIL
)
2129 if (regtype
== REG_TYPE_VFS
)
2130 first_error (_("VFP single precision register or VPR "
2132 else /* regtype == REG_TYPE_VFD. */
2133 first_error (_("VFP/Neon double precision register or VPR "
2138 else if (new_base
== FAIL
)
2140 first_error (_(reg_expected_msgs
[regtype
]));
2144 *partial_match
= TRUE
;
2148 if (new_base
>= max_regs
)
2150 first_error (_("register out of range in list"));
2154 /* Note: a value of 2 * n is returned for the register Q<n>. */
2155 if (regtype
== REG_TYPE_NQ
)
2161 if (new_base
< base_reg
)
2162 base_reg
= new_base
;
2164 if (mask
& (setmask
<< new_base
))
2166 first_error (_("invalid register list"));
2170 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2172 as_tsktsk (_("register list not in ascending order"));
2176 mask
|= setmask
<< new_base
;
2179 if (*str
== '-') /* We have the start of a range expression */
2185 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2188 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2192 if (high_range
>= max_regs
)
2194 first_error (_("register out of range in list"));
2198 if (regtype
== REG_TYPE_NQ
)
2199 high_range
= high_range
+ 1;
2201 if (high_range
<= new_base
)
2203 inst
.error
= _("register range not in ascending order");
2207 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2209 if (mask
& (setmask
<< new_base
))
2211 inst
.error
= _("invalid register list");
2215 mask
|= setmask
<< new_base
;
2220 while (skip_past_comma (&str
) != FAIL
);
2224 /* Sanity check -- should have raised a parse error above. */
2225 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2230 if (expect_vpr
&& !vpr_seen
)
2232 first_error (_("VPR expected last"));
2236 /* Final test -- the registers must be consecutive. */
2238 for (i
= 0; i
< count
; i
++)
2240 if ((mask
& (1u << i
)) == 0)
2242 inst
.error
= _("non-contiguous register range");
2252 /* True if two alias types are the same. */
2255 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2263 if (a
->defined
!= b
->defined
)
2266 if ((a
->defined
& NTA_HASTYPE
) != 0
2267 && (a
->eltype
.type
!= b
->eltype
.type
2268 || a
->eltype
.size
!= b
->eltype
.size
))
2271 if ((a
->defined
& NTA_HASINDEX
) != 0
2272 && (a
->index
!= b
->index
))
2278 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2279 The base register is put in *PBASE.
2280 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2282 The register stride (minus one) is put in bit 4 of the return value.
2283 Bits [6:5] encode the list length (minus one).
2284 The type of the list elements is put in *ELTYPE, if non-NULL. */
2286 #define NEON_LANE(X) ((X) & 0xf)
2287 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2288 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2291 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2293 struct neon_type_el
*eltype
)
2300 int leading_brace
= 0;
2301 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2302 const char *const incr_error
= mve
? _("register stride must be 1") :
2303 _("register stride must be 1 or 2");
2304 const char *const type_error
= _("mismatched element/structure types in list");
2305 struct neon_typed_alias firsttype
;
2306 firsttype
.defined
= 0;
2307 firsttype
.eltype
.type
= NT_invtype
;
2308 firsttype
.eltype
.size
= -1;
2309 firsttype
.index
= -1;
2311 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2316 struct neon_typed_alias atype
;
2318 rtype
= REG_TYPE_MQ
;
2319 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2323 first_error (_(reg_expected_msgs
[rtype
]));
2330 if (rtype
== REG_TYPE_NQ
)
2336 else if (reg_incr
== -1)
2338 reg_incr
= getreg
- base_reg
;
2339 if (reg_incr
< 1 || reg_incr
> 2)
2341 first_error (_(incr_error
));
2345 else if (getreg
!= base_reg
+ reg_incr
* count
)
2347 first_error (_(incr_error
));
2351 if (! neon_alias_types_same (&atype
, &firsttype
))
2353 first_error (_(type_error
));
2357 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2361 struct neon_typed_alias htype
;
2362 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2364 lane
= NEON_INTERLEAVE_LANES
;
2365 else if (lane
!= NEON_INTERLEAVE_LANES
)
2367 first_error (_(type_error
));
2372 else if (reg_incr
!= 1)
2374 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2378 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2381 first_error (_(reg_expected_msgs
[rtype
]));
2384 if (! neon_alias_types_same (&htype
, &firsttype
))
2386 first_error (_(type_error
));
2389 count
+= hireg
+ dregs
- getreg
;
2393 /* If we're using Q registers, we can't use [] or [n] syntax. */
2394 if (rtype
== REG_TYPE_NQ
)
2400 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2404 else if (lane
!= atype
.index
)
2406 first_error (_(type_error
));
2410 else if (lane
== -1)
2411 lane
= NEON_INTERLEAVE_LANES
;
2412 else if (lane
!= NEON_INTERLEAVE_LANES
)
2414 first_error (_(type_error
));
2419 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2421 /* No lane set by [x]. We must be interleaving structures. */
2423 lane
= NEON_INTERLEAVE_LANES
;
2426 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2427 || (count
> 1 && reg_incr
== -1))
2429 first_error (_("error parsing element/structure list"));
2433 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2435 first_error (_("expected }"));
2443 *eltype
= firsttype
.eltype
;
2448 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2451 /* Parse an explicit relocation suffix on an expression. This is
2452 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2453 arm_reloc_hsh contains no entries, so this function can only
2454 succeed if there is no () after the word. Returns -1 on error,
2455 BFD_RELOC_UNUSED if there wasn't any suffix. */
2458 parse_reloc (char **str
)
2460 struct reloc_entry
*r
;
2464 return BFD_RELOC_UNUSED
;
2469 while (*q
&& *q
!= ')' && *q
!= ',')
2474 if ((r
= (struct reloc_entry
*)
2475 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2482 /* Directives: register aliases. */
2484 static struct reg_entry
*
2485 insert_reg_alias (char *str
, unsigned number
, int type
)
2487 struct reg_entry
*new_reg
;
2490 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2492 if (new_reg
->builtin
)
2493 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2495 /* Only warn about a redefinition if it's not defined as the
2497 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2498 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2503 name
= xstrdup (str
);
2504 new_reg
= XNEW (struct reg_entry
);
2506 new_reg
->name
= name
;
2507 new_reg
->number
= number
;
2508 new_reg
->type
= type
;
2509 new_reg
->builtin
= FALSE
;
2510 new_reg
->neon
= NULL
;
2512 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2519 insert_neon_reg_alias (char *str
, int number
, int type
,
2520 struct neon_typed_alias
*atype
)
2522 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2526 first_error (_("attempt to redefine typed alias"));
2532 reg
->neon
= XNEW (struct neon_typed_alias
);
2533 *reg
->neon
= *atype
;
2537 /* Look for the .req directive. This is of the form:
2539 new_register_name .req existing_register_name
2541 If we find one, or if it looks sufficiently like one that we want to
2542 handle any error here, return TRUE. Otherwise return FALSE. */
2545 create_register_alias (char * newname
, char *p
)
2547 struct reg_entry
*old
;
2548 char *oldname
, *nbuf
;
2551 /* The input scrubber ensures that whitespace after the mnemonic is
2552 collapsed to single spaces. */
2554 if (strncmp (oldname
, " .req ", 6) != 0)
2558 if (*oldname
== '\0')
2561 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2564 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2568 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2569 the desired alias name, and p points to its end. If not, then
2570 the desired alias name is in the global original_case_string. */
2571 #ifdef TC_CASE_SENSITIVE
2574 newname
= original_case_string
;
2575 nlen
= strlen (newname
);
2578 nbuf
= xmemdup0 (newname
, nlen
);
2580 /* Create aliases under the new name as stated; an all-lowercase
2581 version of the new name; and an all-uppercase version of the new
2583 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2585 for (p
= nbuf
; *p
; p
++)
2588 if (strncmp (nbuf
, newname
, nlen
))
2590 /* If this attempt to create an additional alias fails, do not bother
2591 trying to create the all-lower case alias. We will fail and issue
2592 a second, duplicate error message. This situation arises when the
2593 programmer does something like:
2596 The second .req creates the "Foo" alias but then fails to create
2597 the artificial FOO alias because it has already been created by the
2599 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2606 for (p
= nbuf
; *p
; p
++)
2609 if (strncmp (nbuf
, newname
, nlen
))
2610 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2617 /* Create a Neon typed/indexed register alias using directives, e.g.:
2622 These typed registers can be used instead of the types specified after the
2623 Neon mnemonic, so long as all operands given have types. Types can also be
2624 specified directly, e.g.:
2625 vadd d0.s32, d1.s32, d2.s32 */
2628 create_neon_reg_alias (char *newname
, char *p
)
2630 enum arm_reg_type basetype
;
2631 struct reg_entry
*basereg
;
2632 struct reg_entry mybasereg
;
2633 struct neon_type ntype
;
2634 struct neon_typed_alias typeinfo
;
2635 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2638 typeinfo
.defined
= 0;
2639 typeinfo
.eltype
.type
= NT_invtype
;
2640 typeinfo
.eltype
.size
= -1;
2641 typeinfo
.index
= -1;
2645 if (strncmp (p
, " .dn ", 5) == 0)
2646 basetype
= REG_TYPE_VFD
;
2647 else if (strncmp (p
, " .qn ", 5) == 0)
2648 basetype
= REG_TYPE_NQ
;
2657 basereg
= arm_reg_parse_multi (&p
);
2659 if (basereg
&& basereg
->type
!= basetype
)
2661 as_bad (_("bad type for register"));
2665 if (basereg
== NULL
)
2668 /* Try parsing as an integer. */
2669 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2670 if (exp
.X_op
!= O_constant
)
2672 as_bad (_("expression must be constant"));
2675 basereg
= &mybasereg
;
2676 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2682 typeinfo
= *basereg
->neon
;
2684 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2686 /* We got a type. */
2687 if (typeinfo
.defined
& NTA_HASTYPE
)
2689 as_bad (_("can't redefine the type of a register alias"));
2693 typeinfo
.defined
|= NTA_HASTYPE
;
2694 if (ntype
.elems
!= 1)
2696 as_bad (_("you must specify a single type only"));
2699 typeinfo
.eltype
= ntype
.el
[0];
2702 if (skip_past_char (&p
, '[') == SUCCESS
)
2705 /* We got a scalar index. */
2707 if (typeinfo
.defined
& NTA_HASINDEX
)
2709 as_bad (_("can't redefine the index of a scalar alias"));
2713 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2715 if (exp
.X_op
!= O_constant
)
2717 as_bad (_("scalar index must be constant"));
2721 typeinfo
.defined
|= NTA_HASINDEX
;
2722 typeinfo
.index
= exp
.X_add_number
;
2724 if (skip_past_char (&p
, ']') == FAIL
)
2726 as_bad (_("expecting ]"));
2731 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2732 the desired alias name, and p points to its end. If not, then
2733 the desired alias name is in the global original_case_string. */
2734 #ifdef TC_CASE_SENSITIVE
2735 namelen
= nameend
- newname
;
2737 newname
= original_case_string
;
2738 namelen
= strlen (newname
);
2741 namebuf
= xmemdup0 (newname
, namelen
);
2743 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2744 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2746 /* Insert name in all uppercase. */
2747 for (p
= namebuf
; *p
; p
++)
2750 if (strncmp (namebuf
, newname
, namelen
))
2751 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2752 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2754 /* Insert name in all lowercase. */
2755 for (p
= namebuf
; *p
; p
++)
2758 if (strncmp (namebuf
, newname
, namelen
))
2759 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2760 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2766 /* Should never be called, as .req goes between the alias and the
2767 register name, not at the beginning of the line. */
2770 s_req (int a ATTRIBUTE_UNUSED
)
2772 as_bad (_("invalid syntax for .req directive"));
2776 s_dn (int a ATTRIBUTE_UNUSED
)
2778 as_bad (_("invalid syntax for .dn directive"));
2782 s_qn (int a ATTRIBUTE_UNUSED
)
2784 as_bad (_("invalid syntax for .qn directive"));
2787 /* The .unreq directive deletes an alias which was previously defined
2788 by .req. For example:
2794 s_unreq (int a ATTRIBUTE_UNUSED
)
2799 name
= input_line_pointer
;
2801 while (*input_line_pointer
!= 0
2802 && *input_line_pointer
!= ' '
2803 && *input_line_pointer
!= '\n')
2804 ++input_line_pointer
;
2806 saved_char
= *input_line_pointer
;
2807 *input_line_pointer
= 0;
2810 as_bad (_("invalid syntax for .unreq directive"));
2813 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2817 as_bad (_("unknown register alias '%s'"), name
);
2818 else if (reg
->builtin
)
2819 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2826 hash_delete (arm_reg_hsh
, name
, FALSE
);
2827 free ((char *) reg
->name
);
2832 /* Also locate the all upper case and all lower case versions.
2833 Do not complain if we cannot find one or the other as it
2834 was probably deleted above. */
2836 nbuf
= strdup (name
);
2837 for (p
= nbuf
; *p
; p
++)
2839 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2842 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2843 free ((char *) reg
->name
);
2849 for (p
= nbuf
; *p
; p
++)
2851 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2854 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2855 free ((char *) reg
->name
);
2865 *input_line_pointer
= saved_char
;
2866 demand_empty_rest_of_line ();
2869 /* Directives: Instruction set selection. */
2872 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2873 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2874 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2875 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2877 /* Create a new mapping symbol for the transition to STATE. */
2880 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2883 const char * symname
;
2890 type
= BSF_NO_FLAGS
;
2894 type
= BSF_NO_FLAGS
;
2898 type
= BSF_NO_FLAGS
;
2904 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2905 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2910 THUMB_SET_FUNC (symbolP
, 0);
2911 ARM_SET_THUMB (symbolP
, 0);
2912 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2916 THUMB_SET_FUNC (symbolP
, 1);
2917 ARM_SET_THUMB (symbolP
, 1);
2918 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2926 /* Save the mapping symbols for future reference. Also check that
2927 we do not place two mapping symbols at the same offset within a
2928 frag. We'll handle overlap between frags in
2929 check_mapping_symbols.
2931 If .fill or other data filling directive generates zero sized data,
2932 the mapping symbol for the following code will have the same value
2933 as the one generated for the data filling directive. In this case,
2934 we replace the old symbol with the new one at the same address. */
2937 if (frag
->tc_frag_data
.first_map
!= NULL
)
2939 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2940 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2942 frag
->tc_frag_data
.first_map
= symbolP
;
2944 if (frag
->tc_frag_data
.last_map
!= NULL
)
2946 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2947 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2948 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2950 frag
->tc_frag_data
.last_map
= symbolP
;
2953 /* We must sometimes convert a region marked as code to data during
2954 code alignment, if an odd number of bytes have to be padded. The
2955 code mapping symbol is pushed to an aligned address. */
2958 insert_data_mapping_symbol (enum mstate state
,
2959 valueT value
, fragS
*frag
, offsetT bytes
)
2961 /* If there was already a mapping symbol, remove it. */
2962 if (frag
->tc_frag_data
.last_map
!= NULL
2963 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2965 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2969 know (frag
->tc_frag_data
.first_map
== symp
);
2970 frag
->tc_frag_data
.first_map
= NULL
;
2972 frag
->tc_frag_data
.last_map
= NULL
;
2973 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2976 make_mapping_symbol (MAP_DATA
, value
, frag
);
2977 make_mapping_symbol (state
, value
+ bytes
, frag
);
2980 static void mapping_state_2 (enum mstate state
, int max_chars
);
2982 /* Set the mapping state to STATE. Only call this when about to
2983 emit some STATE bytes to the file. */
2985 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2987 mapping_state (enum mstate state
)
2989 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2991 if (mapstate
== state
)
2992 /* The mapping symbol has already been emitted.
2993 There is nothing else to do. */
2996 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2998 All ARM instructions require 4-byte alignment.
2999 (Almost) all Thumb instructions require 2-byte alignment.
3001 When emitting instructions into any section, mark the section
3004 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3005 but themselves require 2-byte alignment; this applies to some
3006 PC- relative forms. However, these cases will involve implicit
3007 literal pool generation or an explicit .align >=2, both of
3008 which will cause the section to me marked with sufficient
3009 alignment. Thus, we don't handle those cases here. */
3010 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3012 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3013 /* This case will be evaluated later. */
3016 mapping_state_2 (state
, 0);
3019 /* Same as mapping_state, but MAX_CHARS bytes have already been
3020 allocated. Put the mapping symbol that far back. */
3023 mapping_state_2 (enum mstate state
, int max_chars
)
3025 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3027 if (!SEG_NORMAL (now_seg
))
3030 if (mapstate
== state
)
3031 /* The mapping symbol has already been emitted.
3032 There is nothing else to do. */
3035 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3036 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3038 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3039 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3042 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3045 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3046 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3050 #define mapping_state(x) ((void)0)
3051 #define mapping_state_2(x, y) ((void)0)
3054 /* Find the real, Thumb encoded start of a Thumb function. */
3058 find_real_start (symbolS
* symbolP
)
3061 const char * name
= S_GET_NAME (symbolP
);
3062 symbolS
* new_target
;
3064 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3065 #define STUB_NAME ".real_start_of"
3070 /* The compiler may generate BL instructions to local labels because
3071 it needs to perform a branch to a far away location. These labels
3072 do not have a corresponding ".real_start_of" label. We check
3073 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3074 the ".real_start_of" convention for nonlocal branches. */
3075 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3078 real_start
= concat (STUB_NAME
, name
, NULL
);
3079 new_target
= symbol_find (real_start
);
3082 if (new_target
== NULL
)
3084 as_warn (_("Failed to find real start of function: %s\n"), name
);
3085 new_target
= symbolP
;
3093 opcode_select (int width
)
3100 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3101 as_bad (_("selected processor does not support THUMB opcodes"));
3104 /* No need to force the alignment, since we will have been
3105 coming from ARM mode, which is word-aligned. */
3106 record_alignment (now_seg
, 1);
3113 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3114 as_bad (_("selected processor does not support ARM opcodes"));
3119 frag_align (2, 0, 0);
3121 record_alignment (now_seg
, 1);
3126 as_bad (_("invalid instruction size selected (%d)"), width
);
3131 s_arm (int ignore ATTRIBUTE_UNUSED
)
3134 demand_empty_rest_of_line ();
3138 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3141 demand_empty_rest_of_line ();
3145 s_code (int unused ATTRIBUTE_UNUSED
)
3149 temp
= get_absolute_expression ();
3154 opcode_select (temp
);
3158 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3163 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3165 /* If we are not already in thumb mode go into it, EVEN if
3166 the target processor does not support thumb instructions.
3167 This is used by gcc/config/arm/lib1funcs.asm for example
3168 to compile interworking support functions even if the
3169 target processor should not support interworking. */
3173 record_alignment (now_seg
, 1);
3176 demand_empty_rest_of_line ();
3180 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3184 /* The following label is the name/address of the start of a Thumb function.
3185 We need to know this for the interworking support. */
3186 label_is_thumb_function_name
= TRUE
;
3189 /* Perform a .set directive, but also mark the alias as
3190 being a thumb function. */
3193 s_thumb_set (int equiv
)
3195 /* XXX the following is a duplicate of the code for s_set() in read.c
3196 We cannot just call that code as we need to get at the symbol that
3203 /* Especial apologies for the random logic:
3204 This just grew, and could be parsed much more simply!
3206 delim
= get_symbol_name (& name
);
3207 end_name
= input_line_pointer
;
3208 (void) restore_line_pointer (delim
);
3210 if (*input_line_pointer
!= ',')
3213 as_bad (_("expected comma after name \"%s\""), name
);
3215 ignore_rest_of_line ();
3219 input_line_pointer
++;
3222 if (name
[0] == '.' && name
[1] == '\0')
3224 /* XXX - this should not happen to .thumb_set. */
3228 if ((symbolP
= symbol_find (name
)) == NULL
3229 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3232 /* When doing symbol listings, play games with dummy fragments living
3233 outside the normal fragment chain to record the file and line info
3235 if (listing
& LISTING_SYMBOLS
)
3237 extern struct list_info_struct
* listing_tail
;
3238 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3240 memset (dummy_frag
, 0, sizeof (fragS
));
3241 dummy_frag
->fr_type
= rs_fill
;
3242 dummy_frag
->line
= listing_tail
;
3243 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3244 dummy_frag
->fr_symbol
= symbolP
;
3248 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3251 /* "set" symbols are local unless otherwise specified. */
3252 SF_SET_LOCAL (symbolP
);
3253 #endif /* OBJ_COFF */
3254 } /* Make a new symbol. */
3256 symbol_table_insert (symbolP
);
3261 && S_IS_DEFINED (symbolP
)
3262 && S_GET_SEGMENT (symbolP
) != reg_section
)
3263 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3265 pseudo_set (symbolP
);
3267 demand_empty_rest_of_line ();
3269 /* XXX Now we come to the Thumb specific bit of code. */
3271 THUMB_SET_FUNC (symbolP
, 1);
3272 ARM_SET_THUMB (symbolP
, 1);
3273 #if defined OBJ_ELF || defined OBJ_COFF
3274 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3278 /* Directives: Mode selection. */
3280 /* .syntax [unified|divided] - choose the new unified syntax
3281 (same for Arm and Thumb encoding, modulo slight differences in what
3282 can be represented) or the old divergent syntax for each mode. */
3284 s_syntax (int unused ATTRIBUTE_UNUSED
)
3288 delim
= get_symbol_name (& name
);
3290 if (!strcasecmp (name
, "unified"))
3291 unified_syntax
= TRUE
;
3292 else if (!strcasecmp (name
, "divided"))
3293 unified_syntax
= FALSE
;
3296 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3299 (void) restore_line_pointer (delim
);
3300 demand_empty_rest_of_line ();
3303 /* Directives: sectioning and alignment. */
3306 s_bss (int ignore ATTRIBUTE_UNUSED
)
3308 /* We don't support putting frags in the BSS segment, we fake it by
3309 marking in_bss, then looking at s_skip for clues. */
3310 subseg_set (bss_section
, 0);
3311 demand_empty_rest_of_line ();
3313 #ifdef md_elf_section_change_hook
3314 md_elf_section_change_hook ();
3319 s_even (int ignore ATTRIBUTE_UNUSED
)
3321 /* Never make frag if expect extra pass. */
3323 frag_align (1, 0, 0);
3325 record_alignment (now_seg
, 1);
3327 demand_empty_rest_of_line ();
3330 /* Directives: CodeComposer Studio. */
3332 /* .ref (for CodeComposer Studio syntax only). */
3334 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3336 if (codecomposer_syntax
)
3337 ignore_rest_of_line ();
3339 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3342 /* If name is not NULL, then it is used for marking the beginning of a
3343 function, whereas if it is NULL then it means the function end. */
3345 asmfunc_debug (const char * name
)
3347 static const char * last_name
= NULL
;
3351 gas_assert (last_name
== NULL
);
3354 if (debug_type
== DEBUG_STABS
)
3355 stabs_generate_asm_func (name
, name
);
3359 gas_assert (last_name
!= NULL
);
3361 if (debug_type
== DEBUG_STABS
)
3362 stabs_generate_asm_endfunc (last_name
, last_name
);
3369 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3371 if (codecomposer_syntax
)
3373 switch (asmfunc_state
)
3375 case OUTSIDE_ASMFUNC
:
3376 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3379 case WAITING_ASMFUNC_NAME
:
3380 as_bad (_(".asmfunc repeated."));
3383 case WAITING_ENDASMFUNC
:
3384 as_bad (_(".asmfunc without function."));
3387 demand_empty_rest_of_line ();
3390 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3394 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3396 if (codecomposer_syntax
)
3398 switch (asmfunc_state
)
3400 case OUTSIDE_ASMFUNC
:
3401 as_bad (_(".endasmfunc without a .asmfunc."));
3404 case WAITING_ASMFUNC_NAME
:
3405 as_bad (_(".endasmfunc without function."));
3408 case WAITING_ENDASMFUNC
:
3409 asmfunc_state
= OUTSIDE_ASMFUNC
;
3410 asmfunc_debug (NULL
);
3413 demand_empty_rest_of_line ();
3416 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3420 s_ccs_def (int name
)
3422 if (codecomposer_syntax
)
3425 as_bad (_(".def pseudo-op only available with -mccs flag."));
3428 /* Directives: Literal pools. */
3430 static literal_pool
*
3431 find_literal_pool (void)
3433 literal_pool
* pool
;
3435 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3437 if (pool
->section
== now_seg
3438 && pool
->sub_section
== now_subseg
)
3445 static literal_pool
*
3446 find_or_make_literal_pool (void)
3448 /* Next literal pool ID number. */
3449 static unsigned int latest_pool_num
= 1;
3450 literal_pool
* pool
;
3452 pool
= find_literal_pool ();
3456 /* Create a new pool. */
3457 pool
= XNEW (literal_pool
);
3461 pool
->next_free_entry
= 0;
3462 pool
->section
= now_seg
;
3463 pool
->sub_section
= now_subseg
;
3464 pool
->next
= list_of_pools
;
3465 pool
->symbol
= NULL
;
3466 pool
->alignment
= 2;
3468 /* Add it to the list. */
3469 list_of_pools
= pool
;
3472 /* New pools, and emptied pools, will have a NULL symbol. */
3473 if (pool
->symbol
== NULL
)
3475 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3476 (valueT
) 0, &zero_address_frag
);
3477 pool
->id
= latest_pool_num
++;
3484 /* Add the literal in the global 'inst'
3485 structure to the relevant literal pool. */
3488 add_to_lit_pool (unsigned int nbytes
)
3490 #define PADDING_SLOT 0x1
3491 #define LIT_ENTRY_SIZE_MASK 0xFF
3492 literal_pool
* pool
;
3493 unsigned int entry
, pool_size
= 0;
3494 bfd_boolean padding_slot_p
= FALSE
;
3500 imm1
= inst
.operands
[1].imm
;
3501 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3502 : inst
.relocs
[0].exp
.X_unsigned
? 0
3503 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3504 if (target_big_endian
)
3507 imm2
= inst
.operands
[1].imm
;
3511 pool
= find_or_make_literal_pool ();
3513 /* Check if this literal value is already in the pool. */
3514 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3518 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3519 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3520 && (pool
->literals
[entry
].X_add_number
3521 == inst
.relocs
[0].exp
.X_add_number
)
3522 && (pool
->literals
[entry
].X_md
== nbytes
)
3523 && (pool
->literals
[entry
].X_unsigned
3524 == inst
.relocs
[0].exp
.X_unsigned
))
3527 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3528 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3529 && (pool
->literals
[entry
].X_add_number
3530 == inst
.relocs
[0].exp
.X_add_number
)
3531 && (pool
->literals
[entry
].X_add_symbol
3532 == inst
.relocs
[0].exp
.X_add_symbol
)
3533 && (pool
->literals
[entry
].X_op_symbol
3534 == inst
.relocs
[0].exp
.X_op_symbol
)
3535 && (pool
->literals
[entry
].X_md
== nbytes
))
3538 else if ((nbytes
== 8)
3539 && !(pool_size
& 0x7)
3540 && ((entry
+ 1) != pool
->next_free_entry
)
3541 && (pool
->literals
[entry
].X_op
== O_constant
)
3542 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3543 && (pool
->literals
[entry
].X_unsigned
3544 == inst
.relocs
[0].exp
.X_unsigned
)
3545 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3546 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3547 && (pool
->literals
[entry
+ 1].X_unsigned
3548 == inst
.relocs
[0].exp
.X_unsigned
))
3551 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3552 if (padding_slot_p
&& (nbytes
== 4))
3558 /* Do we need to create a new entry? */
3559 if (entry
== pool
->next_free_entry
)
3561 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3563 inst
.error
= _("literal pool overflow");
3569 /* For 8-byte entries, we align to an 8-byte boundary,
3570 and split it into two 4-byte entries, because on 32-bit
3571 host, 8-byte constants are treated as big num, thus
3572 saved in "generic_bignum" which will be overwritten
3573 by later assignments.
3575 We also need to make sure there is enough space for
3578 We also check to make sure the literal operand is a
3580 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3581 || inst
.relocs
[0].exp
.X_op
== O_big
))
3583 inst
.error
= _("invalid type for literal pool");
3586 else if (pool_size
& 0x7)
3588 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3590 inst
.error
= _("literal pool overflow");
3594 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3595 pool
->literals
[entry
].X_op
= O_constant
;
3596 pool
->literals
[entry
].X_add_number
= 0;
3597 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3598 pool
->next_free_entry
+= 1;
3601 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3603 inst
.error
= _("literal pool overflow");
3607 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3608 pool
->literals
[entry
].X_op
= O_constant
;
3609 pool
->literals
[entry
].X_add_number
= imm1
;
3610 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3611 pool
->literals
[entry
++].X_md
= 4;
3612 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3613 pool
->literals
[entry
].X_op
= O_constant
;
3614 pool
->literals
[entry
].X_add_number
= imm2
;
3615 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3616 pool
->literals
[entry
].X_md
= 4;
3617 pool
->alignment
= 3;
3618 pool
->next_free_entry
+= 1;
3622 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3623 pool
->literals
[entry
].X_md
= 4;
3627 /* PR ld/12974: Record the location of the first source line to reference
3628 this entry in the literal pool. If it turns out during linking that the
3629 symbol does not exist we will be able to give an accurate line number for
3630 the (first use of the) missing reference. */
3631 if (debug_type
== DEBUG_DWARF2
)
3632 dwarf2_where (pool
->locs
+ entry
);
3634 pool
->next_free_entry
+= 1;
3636 else if (padding_slot_p
)
3638 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3639 pool
->literals
[entry
].X_md
= nbytes
;
3642 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3643 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3644 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3650 tc_start_label_without_colon (void)
3652 bfd_boolean ret
= TRUE
;
3654 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3656 const char *label
= input_line_pointer
;
3658 while (!is_end_of_line
[(int) label
[-1]])
3663 as_bad (_("Invalid label '%s'"), label
);
3667 asmfunc_debug (label
);
3669 asmfunc_state
= WAITING_ENDASMFUNC
;
3675 /* Can't use symbol_new here, so have to create a symbol and then at
3676 a later date assign it a value. That's what these functions do. */
3679 symbol_locate (symbolS
* symbolP
,
3680 const char * name
, /* It is copied, the caller can modify. */
3681 segT segment
, /* Segment identifier (SEG_<something>). */
3682 valueT valu
, /* Symbol value. */
3683 fragS
* frag
) /* Associated fragment. */
3686 char * preserved_copy_of_name
;
3688 name_length
= strlen (name
) + 1; /* +1 for \0. */
3689 obstack_grow (¬es
, name
, name_length
);
3690 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3692 #ifdef tc_canonicalize_symbol_name
3693 preserved_copy_of_name
=
3694 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3697 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3699 S_SET_SEGMENT (symbolP
, segment
);
3700 S_SET_VALUE (symbolP
, valu
);
3701 symbol_clear_list_pointers (symbolP
);
3703 symbol_set_frag (symbolP
, frag
);
3705 /* Link to end of symbol chain. */
3707 extern int symbol_table_frozen
;
3709 if (symbol_table_frozen
)
3713 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3715 obj_symbol_new_hook (symbolP
);
3717 #ifdef tc_symbol_new_hook
3718 tc_symbol_new_hook (symbolP
);
3722 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3723 #endif /* DEBUG_SYMS */
3727 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3730 literal_pool
* pool
;
3733 pool
= find_literal_pool ();
3735 || pool
->symbol
== NULL
3736 || pool
->next_free_entry
== 0)
3739 /* Align pool as you have word accesses.
3740 Only make a frag if we have to. */
3742 frag_align (pool
->alignment
, 0, 0);
3744 record_alignment (now_seg
, 2);
3747 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3748 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3750 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3752 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3753 (valueT
) frag_now_fix (), frag_now
);
3754 symbol_table_insert (pool
->symbol
);
3756 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3758 #if defined OBJ_COFF || defined OBJ_ELF
3759 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3762 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3765 if (debug_type
== DEBUG_DWARF2
)
3766 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3768 /* First output the expression in the instruction to the pool. */
3769 emit_expr (&(pool
->literals
[entry
]),
3770 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3773 /* Mark the pool as empty. */
3774 pool
->next_free_entry
= 0;
3775 pool
->symbol
= NULL
;
3779 /* Forward declarations for functions below, in the MD interface
3781 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3782 static valueT
create_unwind_entry (int);
3783 static void start_unwind_section (const segT
, int);
3784 static void add_unwind_opcode (valueT
, int);
3785 static void flush_pending_unwind (void);
3787 /* Directives: Data. */
3790 s_arm_elf_cons (int nbytes
)
3794 #ifdef md_flush_pending_output
3795 md_flush_pending_output ();
3798 if (is_it_end_of_statement ())
3800 demand_empty_rest_of_line ();
3804 #ifdef md_cons_align
3805 md_cons_align (nbytes
);
3808 mapping_state (MAP_DATA
);
3812 char *base
= input_line_pointer
;
3816 if (exp
.X_op
!= O_symbol
)
3817 emit_expr (&exp
, (unsigned int) nbytes
);
3820 char *before_reloc
= input_line_pointer
;
3821 reloc
= parse_reloc (&input_line_pointer
);
3824 as_bad (_("unrecognized relocation suffix"));
3825 ignore_rest_of_line ();
3828 else if (reloc
== BFD_RELOC_UNUSED
)
3829 emit_expr (&exp
, (unsigned int) nbytes
);
3832 reloc_howto_type
*howto
= (reloc_howto_type
*)
3833 bfd_reloc_type_lookup (stdoutput
,
3834 (bfd_reloc_code_real_type
) reloc
);
3835 int size
= bfd_get_reloc_size (howto
);
3837 if (reloc
== BFD_RELOC_ARM_PLT32
)
3839 as_bad (_("(plt) is only valid on branch targets"));
3840 reloc
= BFD_RELOC_UNUSED
;
3845 as_bad (ngettext ("%s relocations do not fit in %d byte",
3846 "%s relocations do not fit in %d bytes",
3848 howto
->name
, nbytes
);
3851 /* We've parsed an expression stopping at O_symbol.
3852 But there may be more expression left now that we
3853 have parsed the relocation marker. Parse it again.
3854 XXX Surely there is a cleaner way to do this. */
3855 char *p
= input_line_pointer
;
3857 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3859 memcpy (save_buf
, base
, input_line_pointer
- base
);
3860 memmove (base
+ (input_line_pointer
- before_reloc
),
3861 base
, before_reloc
- base
);
3863 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3865 memcpy (base
, save_buf
, p
- base
);
3867 offset
= nbytes
- size
;
3868 p
= frag_more (nbytes
);
3869 memset (p
, 0, nbytes
);
3870 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3871 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3877 while (*input_line_pointer
++ == ',');
3879 /* Put terminator back into stream. */
3880 input_line_pointer
--;
3881 demand_empty_rest_of_line ();
3884 /* Emit an expression containing a 32-bit thumb instruction.
3885 Implementation based on put_thumb32_insn. */
3888 emit_thumb32_expr (expressionS
* exp
)
3890 expressionS exp_high
= *exp
;
3892 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3893 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3894 exp
->X_add_number
&= 0xffff;
3895 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3898 /* Guess the instruction size based on the opcode. */
3901 thumb_insn_size (int opcode
)
3903 if ((unsigned int) opcode
< 0xe800u
)
3905 else if ((unsigned int) opcode
>= 0xe8000000u
)
3912 emit_insn (expressionS
*exp
, int nbytes
)
3916 if (exp
->X_op
== O_constant
)
3921 size
= thumb_insn_size (exp
->X_add_number
);
3925 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3927 as_bad (_(".inst.n operand too big. "\
3928 "Use .inst.w instead"));
3933 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3934 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3936 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3938 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3939 emit_thumb32_expr (exp
);
3941 emit_expr (exp
, (unsigned int) size
);
3943 it_fsm_post_encode ();
3947 as_bad (_("cannot determine Thumb instruction size. " \
3948 "Use .inst.n/.inst.w instead"));
3951 as_bad (_("constant expression required"));
3956 /* Like s_arm_elf_cons but do not use md_cons_align and
3957 set the mapping state to MAP_ARM/MAP_THUMB. */
3960 s_arm_elf_inst (int nbytes
)
3962 if (is_it_end_of_statement ())
3964 demand_empty_rest_of_line ();
3968 /* Calling mapping_state () here will not change ARM/THUMB,
3969 but will ensure not to be in DATA state. */
3972 mapping_state (MAP_THUMB
);
3977 as_bad (_("width suffixes are invalid in ARM mode"));
3978 ignore_rest_of_line ();
3984 mapping_state (MAP_ARM
);
3993 if (! emit_insn (& exp
, nbytes
))
3995 ignore_rest_of_line ();
3999 while (*input_line_pointer
++ == ',');
4001 /* Put terminator back into stream. */
4002 input_line_pointer
--;
4003 demand_empty_rest_of_line ();
4006 /* Parse a .rel31 directive. */
4009 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4016 if (*input_line_pointer
== '1')
4017 highbit
= 0x80000000;
4018 else if (*input_line_pointer
!= '0')
4019 as_bad (_("expected 0 or 1"));
4021 input_line_pointer
++;
4022 if (*input_line_pointer
!= ',')
4023 as_bad (_("missing comma"));
4024 input_line_pointer
++;
4026 #ifdef md_flush_pending_output
4027 md_flush_pending_output ();
4030 #ifdef md_cons_align
4034 mapping_state (MAP_DATA
);
4039 md_number_to_chars (p
, highbit
, 4);
4040 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4041 BFD_RELOC_ARM_PREL31
);
4043 demand_empty_rest_of_line ();
4046 /* Directives: AEABI stack-unwind tables. */
4048 /* Parse an unwind_fnstart directive. Simply records the current location. */
4051 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4053 demand_empty_rest_of_line ();
4054 if (unwind
.proc_start
)
4056 as_bad (_("duplicate .fnstart directive"));
4060 /* Mark the start of the function. */
4061 unwind
.proc_start
= expr_build_dot ();
4063 /* Reset the rest of the unwind info. */
4064 unwind
.opcode_count
= 0;
4065 unwind
.table_entry
= NULL
;
4066 unwind
.personality_routine
= NULL
;
4067 unwind
.personality_index
= -1;
4068 unwind
.frame_size
= 0;
4069 unwind
.fp_offset
= 0;
4070 unwind
.fp_reg
= REG_SP
;
4072 unwind
.sp_restored
= 0;
4076 /* Parse a handlerdata directive. Creates the exception handling table entry
4077 for the function. */
4080 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4082 demand_empty_rest_of_line ();
4083 if (!unwind
.proc_start
)
4084 as_bad (MISSING_FNSTART
);
4086 if (unwind
.table_entry
)
4087 as_bad (_("duplicate .handlerdata directive"));
4089 create_unwind_entry (1);
4092 /* Parse an unwind_fnend directive. Generates the index table entry. */
4095 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4100 unsigned int marked_pr_dependency
;
4102 demand_empty_rest_of_line ();
4104 if (!unwind
.proc_start
)
4106 as_bad (_(".fnend directive without .fnstart"));
4110 /* Add eh table entry. */
4111 if (unwind
.table_entry
== NULL
)
4112 val
= create_unwind_entry (0);
4116 /* Add index table entry. This is two words. */
4117 start_unwind_section (unwind
.saved_seg
, 1);
4118 frag_align (2, 0, 0);
4119 record_alignment (now_seg
, 2);
4121 ptr
= frag_more (8);
4123 where
= frag_now_fix () - 8;
4125 /* Self relative offset of the function start. */
4126 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4127 BFD_RELOC_ARM_PREL31
);
4129 /* Indicate dependency on EHABI-defined personality routines to the
4130 linker, if it hasn't been done already. */
4131 marked_pr_dependency
4132 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4133 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4134 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4136 static const char *const name
[] =
4138 "__aeabi_unwind_cpp_pr0",
4139 "__aeabi_unwind_cpp_pr1",
4140 "__aeabi_unwind_cpp_pr2"
4142 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4143 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4144 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4145 |= 1 << unwind
.personality_index
;
4149 /* Inline exception table entry. */
4150 md_number_to_chars (ptr
+ 4, val
, 4);
4152 /* Self relative offset of the table entry. */
4153 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4154 BFD_RELOC_ARM_PREL31
);
4156 /* Restore the original section. */
4157 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4159 unwind
.proc_start
= NULL
;
4163 /* Parse an unwind_cantunwind directive. */
4166 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4168 demand_empty_rest_of_line ();
4169 if (!unwind
.proc_start
)
4170 as_bad (MISSING_FNSTART
);
4172 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4173 as_bad (_("personality routine specified for cantunwind frame"));
4175 unwind
.personality_index
= -2;
4179 /* Parse a personalityindex directive. */
4182 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4186 if (!unwind
.proc_start
)
4187 as_bad (MISSING_FNSTART
);
4189 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4190 as_bad (_("duplicate .personalityindex directive"));
4194 if (exp
.X_op
!= O_constant
4195 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4197 as_bad (_("bad personality routine number"));
4198 ignore_rest_of_line ();
4202 unwind
.personality_index
= exp
.X_add_number
;
4204 demand_empty_rest_of_line ();
4208 /* Parse a personality directive. */
4211 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4215 if (!unwind
.proc_start
)
4216 as_bad (MISSING_FNSTART
);
4218 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4219 as_bad (_("duplicate .personality directive"));
4221 c
= get_symbol_name (& name
);
4222 p
= input_line_pointer
;
4224 ++ input_line_pointer
;
4225 unwind
.personality_routine
= symbol_find_or_make (name
);
4227 demand_empty_rest_of_line ();
4231 /* Parse a directive saving core registers. */
4234 s_arm_unwind_save_core (void)
4240 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4243 as_bad (_("expected register list"));
4244 ignore_rest_of_line ();
4248 demand_empty_rest_of_line ();
4250 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4251 into .unwind_save {..., sp...}. We aren't bothered about the value of
4252 ip because it is clobbered by calls. */
4253 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4254 && (range
& 0x3000) == 0x1000)
4256 unwind
.opcode_count
--;
4257 unwind
.sp_restored
= 0;
4258 range
= (range
| 0x2000) & ~0x1000;
4259 unwind
.pending_offset
= 0;
4265 /* See if we can use the short opcodes. These pop a block of up to 8
4266 registers starting with r4, plus maybe r14. */
4267 for (n
= 0; n
< 8; n
++)
4269 /* Break at the first non-saved register. */
4270 if ((range
& (1 << (n
+ 4))) == 0)
4273 /* See if there are any other bits set. */
4274 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4276 /* Use the long form. */
4277 op
= 0x8000 | ((range
>> 4) & 0xfff);
4278 add_unwind_opcode (op
, 2);
4282 /* Use the short form. */
4284 op
= 0xa8; /* Pop r14. */
4286 op
= 0xa0; /* Do not pop r14. */
4288 add_unwind_opcode (op
, 1);
4295 op
= 0xb100 | (range
& 0xf);
4296 add_unwind_opcode (op
, 2);
4299 /* Record the number of bytes pushed. */
4300 for (n
= 0; n
< 16; n
++)
4302 if (range
& (1 << n
))
4303 unwind
.frame_size
+= 4;
4308 /* Parse a directive saving FPA registers. */
4311 s_arm_unwind_save_fpa (int reg
)
4317 /* Get Number of registers to transfer. */
4318 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4321 exp
.X_op
= O_illegal
;
4323 if (exp
.X_op
!= O_constant
)
4325 as_bad (_("expected , <constant>"));
4326 ignore_rest_of_line ();
4330 num_regs
= exp
.X_add_number
;
4332 if (num_regs
< 1 || num_regs
> 4)
4334 as_bad (_("number of registers must be in the range [1:4]"));
4335 ignore_rest_of_line ();
4339 demand_empty_rest_of_line ();
4344 op
= 0xb4 | (num_regs
- 1);
4345 add_unwind_opcode (op
, 1);
4350 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4351 add_unwind_opcode (op
, 2);
4353 unwind
.frame_size
+= num_regs
* 12;
4357 /* Parse a directive saving VFP registers for ARMv6 and above. */
4360 s_arm_unwind_save_vfp_armv6 (void)
4365 int num_vfpv3_regs
= 0;
4366 int num_regs_below_16
;
4367 bfd_boolean partial_match
;
4369 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4373 as_bad (_("expected register list"));
4374 ignore_rest_of_line ();
4378 demand_empty_rest_of_line ();
4380 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4381 than FSTMX/FLDMX-style ones). */
4383 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4385 num_vfpv3_regs
= count
;
4386 else if (start
+ count
> 16)
4387 num_vfpv3_regs
= start
+ count
- 16;
4389 if (num_vfpv3_regs
> 0)
4391 int start_offset
= start
> 16 ? start
- 16 : 0;
4392 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4393 add_unwind_opcode (op
, 2);
4396 /* Generate opcode for registers numbered in the range 0 .. 15. */
4397 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4398 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4399 if (num_regs_below_16
> 0)
4401 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4402 add_unwind_opcode (op
, 2);
4405 unwind
.frame_size
+= count
* 8;
4409 /* Parse a directive saving VFP registers for pre-ARMv6. */
4412 s_arm_unwind_save_vfp (void)
4417 bfd_boolean partial_match
;
4419 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4423 as_bad (_("expected register list"));
4424 ignore_rest_of_line ();
4428 demand_empty_rest_of_line ();
4433 op
= 0xb8 | (count
- 1);
4434 add_unwind_opcode (op
, 1);
4439 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4440 add_unwind_opcode (op
, 2);
4442 unwind
.frame_size
+= count
* 8 + 4;
4446 /* Parse a directive saving iWMMXt data registers. */
4449 s_arm_unwind_save_mmxwr (void)
4457 if (*input_line_pointer
== '{')
4458 input_line_pointer
++;
4462 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4466 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4471 as_tsktsk (_("register list not in ascending order"));
4474 if (*input_line_pointer
== '-')
4476 input_line_pointer
++;
4477 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4480 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4483 else if (reg
>= hi_reg
)
4485 as_bad (_("bad register range"));
4488 for (; reg
< hi_reg
; reg
++)
4492 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4494 skip_past_char (&input_line_pointer
, '}');
4496 demand_empty_rest_of_line ();
4498 /* Generate any deferred opcodes because we're going to be looking at
4500 flush_pending_unwind ();
4502 for (i
= 0; i
< 16; i
++)
4504 if (mask
& (1 << i
))
4505 unwind
.frame_size
+= 8;
4508 /* Attempt to combine with a previous opcode. We do this because gcc
4509 likes to output separate unwind directives for a single block of
4511 if (unwind
.opcode_count
> 0)
4513 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4514 if ((i
& 0xf8) == 0xc0)
4517 /* Only merge if the blocks are contiguous. */
4520 if ((mask
& 0xfe00) == (1 << 9))
4522 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4523 unwind
.opcode_count
--;
4526 else if (i
== 6 && unwind
.opcode_count
>= 2)
4528 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4532 op
= 0xffff << (reg
- 1);
4534 && ((mask
& op
) == (1u << (reg
- 1))))
4536 op
= (1 << (reg
+ i
+ 1)) - 1;
4537 op
&= ~((1 << reg
) - 1);
4539 unwind
.opcode_count
-= 2;
4546 /* We want to generate opcodes in the order the registers have been
4547 saved, ie. descending order. */
4548 for (reg
= 15; reg
>= -1; reg
--)
4550 /* Save registers in blocks. */
4552 || !(mask
& (1 << reg
)))
4554 /* We found an unsaved reg. Generate opcodes to save the
4561 op
= 0xc0 | (hi_reg
- 10);
4562 add_unwind_opcode (op
, 1);
4567 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4568 add_unwind_opcode (op
, 2);
4577 ignore_rest_of_line ();
4581 s_arm_unwind_save_mmxwcg (void)
4588 if (*input_line_pointer
== '{')
4589 input_line_pointer
++;
4591 skip_whitespace (input_line_pointer
);
4595 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4599 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4605 as_tsktsk (_("register list not in ascending order"));
4608 if (*input_line_pointer
== '-')
4610 input_line_pointer
++;
4611 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4614 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4617 else if (reg
>= hi_reg
)
4619 as_bad (_("bad register range"));
4622 for (; reg
< hi_reg
; reg
++)
4626 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4628 skip_past_char (&input_line_pointer
, '}');
4630 demand_empty_rest_of_line ();
4632 /* Generate any deferred opcodes because we're going to be looking at
4634 flush_pending_unwind ();
4636 for (reg
= 0; reg
< 16; reg
++)
4638 if (mask
& (1 << reg
))
4639 unwind
.frame_size
+= 4;
4642 add_unwind_opcode (op
, 2);
4645 ignore_rest_of_line ();
4649 /* Parse an unwind_save directive.
4650 If the argument is non-zero, this is a .vsave directive. */
4653 s_arm_unwind_save (int arch_v6
)
4656 struct reg_entry
*reg
;
4657 bfd_boolean had_brace
= FALSE
;
4659 if (!unwind
.proc_start
)
4660 as_bad (MISSING_FNSTART
);
4662 /* Figure out what sort of save we have. */
4663 peek
= input_line_pointer
;
4671 reg
= arm_reg_parse_multi (&peek
);
4675 as_bad (_("register expected"));
4676 ignore_rest_of_line ();
4685 as_bad (_("FPA .unwind_save does not take a register list"));
4686 ignore_rest_of_line ();
4689 input_line_pointer
= peek
;
4690 s_arm_unwind_save_fpa (reg
->number
);
4694 s_arm_unwind_save_core ();
4699 s_arm_unwind_save_vfp_armv6 ();
4701 s_arm_unwind_save_vfp ();
4704 case REG_TYPE_MMXWR
:
4705 s_arm_unwind_save_mmxwr ();
4708 case REG_TYPE_MMXWCG
:
4709 s_arm_unwind_save_mmxwcg ();
4713 as_bad (_(".unwind_save does not support this kind of register"));
4714 ignore_rest_of_line ();
4719 /* Parse an unwind_movsp directive. */
4722 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4728 if (!unwind
.proc_start
)
4729 as_bad (MISSING_FNSTART
);
4731 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4734 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4735 ignore_rest_of_line ();
4739 /* Optional constant. */
4740 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4742 if (immediate_for_directive (&offset
) == FAIL
)
4748 demand_empty_rest_of_line ();
4750 if (reg
== REG_SP
|| reg
== REG_PC
)
4752 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4756 if (unwind
.fp_reg
!= REG_SP
)
4757 as_bad (_("unexpected .unwind_movsp directive"));
4759 /* Generate opcode to restore the value. */
4761 add_unwind_opcode (op
, 1);
4763 /* Record the information for later. */
4764 unwind
.fp_reg
= reg
;
4765 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4766 unwind
.sp_restored
= 1;
4769 /* Parse an unwind_pad directive. */
4772 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4776 if (!unwind
.proc_start
)
4777 as_bad (MISSING_FNSTART
);
4779 if (immediate_for_directive (&offset
) == FAIL
)
4784 as_bad (_("stack increment must be multiple of 4"));
4785 ignore_rest_of_line ();
4789 /* Don't generate any opcodes, just record the details for later. */
4790 unwind
.frame_size
+= offset
;
4791 unwind
.pending_offset
+= offset
;
4793 demand_empty_rest_of_line ();
4796 /* Parse an unwind_setfp directive. */
4799 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4805 if (!unwind
.proc_start
)
4806 as_bad (MISSING_FNSTART
);
4808 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4809 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4812 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4814 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4816 as_bad (_("expected <reg>, <reg>"));
4817 ignore_rest_of_line ();
4821 /* Optional constant. */
4822 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4824 if (immediate_for_directive (&offset
) == FAIL
)
4830 demand_empty_rest_of_line ();
4832 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4834 as_bad (_("register must be either sp or set by a previous"
4835 "unwind_movsp directive"));
4839 /* Don't generate any opcodes, just record the information for later. */
4840 unwind
.fp_reg
= fp_reg
;
4842 if (sp_reg
== REG_SP
)
4843 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4845 unwind
.fp_offset
-= offset
;
4848 /* Parse an unwind_raw directive. */
4851 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4854 /* This is an arbitrary limit. */
4855 unsigned char op
[16];
4858 if (!unwind
.proc_start
)
4859 as_bad (MISSING_FNSTART
);
4862 if (exp
.X_op
== O_constant
4863 && skip_past_comma (&input_line_pointer
) != FAIL
)
4865 unwind
.frame_size
+= exp
.X_add_number
;
4869 exp
.X_op
= O_illegal
;
4871 if (exp
.X_op
!= O_constant
)
4873 as_bad (_("expected <offset>, <opcode>"));
4874 ignore_rest_of_line ();
4880 /* Parse the opcode. */
4885 as_bad (_("unwind opcode too long"));
4886 ignore_rest_of_line ();
4888 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4890 as_bad (_("invalid unwind opcode"));
4891 ignore_rest_of_line ();
4894 op
[count
++] = exp
.X_add_number
;
4896 /* Parse the next byte. */
4897 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4903 /* Add the opcode bytes in reverse order. */
4905 add_unwind_opcode (op
[count
], 1);
4907 demand_empty_rest_of_line ();
4911 /* Parse a .eabi_attribute directive. */
4914 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4916 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4918 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4919 attributes_set_explicitly
[tag
] = 1;
4922 /* Emit a tls fix for the symbol. */
4925 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4929 #ifdef md_flush_pending_output
4930 md_flush_pending_output ();
4933 #ifdef md_cons_align
4937 /* Since we're just labelling the code, there's no need to define a
4940 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4941 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4942 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4943 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4945 #endif /* OBJ_ELF */
4947 static void s_arm_arch (int);
4948 static void s_arm_object_arch (int);
4949 static void s_arm_cpu (int);
4950 static void s_arm_fpu (int);
4951 static void s_arm_arch_extension (int);
4956 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4963 if (exp
.X_op
== O_symbol
)
4964 exp
.X_op
= O_secrel
;
4966 emit_expr (&exp
, 4);
4968 while (*input_line_pointer
++ == ',');
4970 input_line_pointer
--;
4971 demand_empty_rest_of_line ();
4976 arm_is_largest_exponent_ok (int precision
)
4978 /* precision == 1 ensures that this will only return
4979 true for 16 bit floats. */
4980 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
4984 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
4988 enum fp_16bit_format new_format
;
4990 new_format
= ARM_FP16_FORMAT_DEFAULT
;
4992 name
= input_line_pointer
;
4993 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
4994 input_line_pointer
++;
4996 saved_char
= *input_line_pointer
;
4997 *input_line_pointer
= 0;
4999 if (strcasecmp (name
, "ieee") == 0)
5000 new_format
= ARM_FP16_FORMAT_IEEE
;
5001 else if (strcasecmp (name
, "alternative") == 0)
5002 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5005 as_bad (_("unrecognised float16 format \"%s\""), name
);
5009 /* Only set fp16_format if it is still the default (aka not already
5011 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5012 fp16_format
= new_format
;
5015 if (new_format
!= fp16_format
)
5016 as_warn (_("float16 format cannot be set more than once, ignoring."));
5020 *input_line_pointer
= saved_char
;
5021 ignore_rest_of_line ();
5024 /* This table describes all the machine specific pseudo-ops the assembler
5025 has to support. The fields are:
5026 pseudo-op name without dot
5027 function to call to execute this pseudo-op
5028 Integer arg to pass to the function. */
5030 const pseudo_typeS md_pseudo_table
[] =
5032 /* Never called because '.req' does not start a line. */
5033 { "req", s_req
, 0 },
5034 /* Following two are likewise never called. */
5037 { "unreq", s_unreq
, 0 },
5038 { "bss", s_bss
, 0 },
5039 { "align", s_align_ptwo
, 2 },
5040 { "arm", s_arm
, 0 },
5041 { "thumb", s_thumb
, 0 },
5042 { "code", s_code
, 0 },
5043 { "force_thumb", s_force_thumb
, 0 },
5044 { "thumb_func", s_thumb_func
, 0 },
5045 { "thumb_set", s_thumb_set
, 0 },
5046 { "even", s_even
, 0 },
5047 { "ltorg", s_ltorg
, 0 },
5048 { "pool", s_ltorg
, 0 },
5049 { "syntax", s_syntax
, 0 },
5050 { "cpu", s_arm_cpu
, 0 },
5051 { "arch", s_arm_arch
, 0 },
5052 { "object_arch", s_arm_object_arch
, 0 },
5053 { "fpu", s_arm_fpu
, 0 },
5054 { "arch_extension", s_arm_arch_extension
, 0 },
5056 { "word", s_arm_elf_cons
, 4 },
5057 { "long", s_arm_elf_cons
, 4 },
5058 { "inst.n", s_arm_elf_inst
, 2 },
5059 { "inst.w", s_arm_elf_inst
, 4 },
5060 { "inst", s_arm_elf_inst
, 0 },
5061 { "rel31", s_arm_rel31
, 0 },
5062 { "fnstart", s_arm_unwind_fnstart
, 0 },
5063 { "fnend", s_arm_unwind_fnend
, 0 },
5064 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5065 { "personality", s_arm_unwind_personality
, 0 },
5066 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5067 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5068 { "save", s_arm_unwind_save
, 0 },
5069 { "vsave", s_arm_unwind_save
, 1 },
5070 { "movsp", s_arm_unwind_movsp
, 0 },
5071 { "pad", s_arm_unwind_pad
, 0 },
5072 { "setfp", s_arm_unwind_setfp
, 0 },
5073 { "unwind_raw", s_arm_unwind_raw
, 0 },
5074 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5075 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5079 /* These are used for dwarf. */
5083 /* These are used for dwarf2. */
5084 { "file", dwarf2_directive_file
, 0 },
5085 { "loc", dwarf2_directive_loc
, 0 },
5086 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5088 { "extend", float_cons
, 'x' },
5089 { "ldouble", float_cons
, 'x' },
5090 { "packed", float_cons
, 'p' },
5092 {"secrel32", pe_directive_secrel
, 0},
5095 /* These are for compatibility with CodeComposer Studio. */
5096 {"ref", s_ccs_ref
, 0},
5097 {"def", s_ccs_def
, 0},
5098 {"asmfunc", s_ccs_asmfunc
, 0},
5099 {"endasmfunc", s_ccs_endasmfunc
, 0},
5101 {"float16", float_cons
, 'h' },
5102 {"float16_format", set_fp16_format
, 0 },
5107 /* Parser functions used exclusively in instruction operands. */
5109 /* Generic immediate-value read function for use in insn parsing.
5110 STR points to the beginning of the immediate (the leading #);
5111 VAL receives the value; if the value is outside [MIN, MAX]
5112 issue an error. PREFIX_OPT is true if the immediate prefix is
5116 parse_immediate (char **str
, int *val
, int min
, int max
,
5117 bfd_boolean prefix_opt
)
5121 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5122 if (exp
.X_op
!= O_constant
)
5124 inst
.error
= _("constant expression required");
5128 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5130 inst
.error
= _("immediate value out of range");
5134 *val
= exp
.X_add_number
;
5138 /* Less-generic immediate-value read function with the possibility of loading a
5139 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5140 instructions. Puts the result directly in inst.operands[i]. */
5143 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5144 bfd_boolean allow_symbol_p
)
5147 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5150 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5152 if (exp_p
->X_op
== O_constant
)
5154 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5155 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5156 O_constant. We have to be careful not to break compilation for
5157 32-bit X_add_number, though. */
5158 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5160 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5161 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5163 inst
.operands
[i
].regisimm
= 1;
5166 else if (exp_p
->X_op
== O_big
5167 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5169 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5171 /* Bignums have their least significant bits in
5172 generic_bignum[0]. Make sure we put 32 bits in imm and
5173 32 bits in reg, in a (hopefully) portable way. */
5174 gas_assert (parts
!= 0);
5176 /* Make sure that the number is not too big.
5177 PR 11972: Bignums can now be sign-extended to the
5178 size of a .octa so check that the out of range bits
5179 are all zero or all one. */
5180 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5182 LITTLENUM_TYPE m
= -1;
5184 if (generic_bignum
[parts
* 2] != 0
5185 && generic_bignum
[parts
* 2] != m
)
5188 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5189 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5193 inst
.operands
[i
].imm
= 0;
5194 for (j
= 0; j
< parts
; j
++, idx
++)
5195 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5196 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5197 inst
.operands
[i
].reg
= 0;
5198 for (j
= 0; j
< parts
; j
++, idx
++)
5199 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5200 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5201 inst
.operands
[i
].regisimm
= 1;
5203 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5211 /* Returns the pseudo-register number of an FPA immediate constant,
5212 or FAIL if there isn't a valid constant here. */
5215 parse_fpa_immediate (char ** str
)
5217 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5223 /* First try and match exact strings, this is to guarantee
5224 that some formats will work even for cross assembly. */
5226 for (i
= 0; fp_const
[i
]; i
++)
5228 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5232 *str
+= strlen (fp_const
[i
]);
5233 if (is_end_of_line
[(unsigned char) **str
])
5239 /* Just because we didn't get a match doesn't mean that the constant
5240 isn't valid, just that it is in a format that we don't
5241 automatically recognize. Try parsing it with the standard
5242 expression routines. */
5244 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5246 /* Look for a raw floating point number. */
5247 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5248 && is_end_of_line
[(unsigned char) *save_in
])
5250 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5252 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5254 if (words
[j
] != fp_values
[i
][j
])
5258 if (j
== MAX_LITTLENUMS
)
5266 /* Try and parse a more complex expression, this will probably fail
5267 unless the code uses a floating point prefix (eg "0f"). */
5268 save_in
= input_line_pointer
;
5269 input_line_pointer
= *str
;
5270 if (expression (&exp
) == absolute_section
5271 && exp
.X_op
== O_big
5272 && exp
.X_add_number
< 0)
5274 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5276 #define X_PRECISION 5
5277 #define E_PRECISION 15L
5278 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5280 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5282 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5284 if (words
[j
] != fp_values
[i
][j
])
5288 if (j
== MAX_LITTLENUMS
)
5290 *str
= input_line_pointer
;
5291 input_line_pointer
= save_in
;
5298 *str
= input_line_pointer
;
5299 input_line_pointer
= save_in
;
5300 inst
.error
= _("invalid FPA immediate expression");
5304 /* Returns 1 if a number has "quarter-precision" float format
5305 0baBbbbbbc defgh000 00000000 00000000. */
5308 is_quarter_float (unsigned imm
)
5310 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5311 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5315 /* Detect the presence of a floating point or integer zero constant,
5319 parse_ifimm_zero (char **in
)
5323 if (!is_immediate_prefix (**in
))
5325 /* In unified syntax, all prefixes are optional. */
5326 if (!unified_syntax
)
5332 /* Accept #0x0 as a synonym for #0. */
5333 if (strncmp (*in
, "0x", 2) == 0)
5336 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5341 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5342 &generic_floating_point_number
);
5345 && generic_floating_point_number
.sign
== '+'
5346 && (generic_floating_point_number
.low
5347 > generic_floating_point_number
.leader
))
5353 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5354 0baBbbbbbc defgh000 00000000 00000000.
5355 The zero and minus-zero cases need special handling, since they can't be
5356 encoded in the "quarter-precision" float format, but can nonetheless be
5357 loaded as integer constants. */
5360 parse_qfloat_immediate (char **ccp
, int *immed
)
5364 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5365 int found_fpchar
= 0;
5367 skip_past_char (&str
, '#');
5369 /* We must not accidentally parse an integer as a floating-point number. Make
5370 sure that the value we parse is not an integer by checking for special
5371 characters '.' or 'e'.
5372 FIXME: This is a horrible hack, but doing better is tricky because type
5373 information isn't in a very usable state at parse time. */
5375 skip_whitespace (fpnum
);
5377 if (strncmp (fpnum
, "0x", 2) == 0)
5381 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5382 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5392 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5394 unsigned fpword
= 0;
5397 /* Our FP word must be 32 bits (single-precision FP). */
5398 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5400 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5404 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5417 /* Shift operands. */
5420 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5423 struct asm_shift_name
5426 enum shift_kind kind
;
5429 /* Third argument to parse_shift. */
5430 enum parse_shift_mode
5432 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5433 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5434 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5435 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5436 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5437 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5440 /* Parse a <shift> specifier on an ARM data processing instruction.
5441 This has three forms:
5443 (LSL|LSR|ASL|ASR|ROR) Rs
5444 (LSL|LSR|ASL|ASR|ROR) #imm
5447 Note that ASL is assimilated to LSL in the instruction encoding, and
5448 RRX to ROR #0 (which cannot be written as such). */
5451 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5453 const struct asm_shift_name
*shift_name
;
5454 enum shift_kind shift
;
5459 for (p
= *str
; ISALPHA (*p
); p
++)
5464 inst
.error
= _("shift expression expected");
5468 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5471 if (shift_name
== NULL
)
5473 inst
.error
= _("shift expression expected");
5477 shift
= shift_name
->kind
;
5481 case NO_SHIFT_RESTRICT
:
5482 case SHIFT_IMMEDIATE
:
5483 if (shift
== SHIFT_UXTW
)
5485 inst
.error
= _("'UXTW' not allowed here");
5490 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5491 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5493 inst
.error
= _("'LSL' or 'ASR' required");
5498 case SHIFT_LSL_IMMEDIATE
:
5499 if (shift
!= SHIFT_LSL
)
5501 inst
.error
= _("'LSL' required");
5506 case SHIFT_ASR_IMMEDIATE
:
5507 if (shift
!= SHIFT_ASR
)
5509 inst
.error
= _("'ASR' required");
5513 case SHIFT_UXTW_IMMEDIATE
:
5514 if (shift
!= SHIFT_UXTW
)
5516 inst
.error
= _("'UXTW' required");
5524 if (shift
!= SHIFT_RRX
)
5526 /* Whitespace can appear here if the next thing is a bare digit. */
5527 skip_whitespace (p
);
5529 if (mode
== NO_SHIFT_RESTRICT
5530 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5532 inst
.operands
[i
].imm
= reg
;
5533 inst
.operands
[i
].immisreg
= 1;
5535 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5538 inst
.operands
[i
].shift_kind
= shift
;
5539 inst
.operands
[i
].shifted
= 1;
5544 /* Parse a <shifter_operand> for an ARM data processing instruction:
5547 #<immediate>, <rotate>
5551 where <shift> is defined by parse_shift above, and <rotate> is a
5552 multiple of 2 between 0 and 30. Validation of immediate operands
5553 is deferred to md_apply_fix. */
5556 parse_shifter_operand (char **str
, int i
)
5561 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5563 inst
.operands
[i
].reg
= value
;
5564 inst
.operands
[i
].isreg
= 1;
5566 /* parse_shift will override this if appropriate */
5567 inst
.relocs
[0].exp
.X_op
= O_constant
;
5568 inst
.relocs
[0].exp
.X_add_number
= 0;
5570 if (skip_past_comma (str
) == FAIL
)
5573 /* Shift operation on register. */
5574 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5577 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5580 if (skip_past_comma (str
) == SUCCESS
)
5582 /* #x, y -- ie explicit rotation by Y. */
5583 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5586 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5588 inst
.error
= _("constant expression expected");
5592 value
= exp
.X_add_number
;
5593 if (value
< 0 || value
> 30 || value
% 2 != 0)
5595 inst
.error
= _("invalid rotation");
5598 if (inst
.relocs
[0].exp
.X_add_number
< 0
5599 || inst
.relocs
[0].exp
.X_add_number
> 255)
5601 inst
.error
= _("invalid constant");
5605 /* Encode as specified. */
5606 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5610 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5611 inst
.relocs
[0].pc_rel
= 0;
5615 /* Group relocation information. Each entry in the table contains the
5616 textual name of the relocation as may appear in assembler source
5617 and must end with a colon.
5618 Along with this textual name are the relocation codes to be used if
5619 the corresponding instruction is an ALU instruction (ADD or SUB only),
5620 an LDR, an LDRS, or an LDC. */
5622 struct group_reloc_table_entry
5633 /* Varieties of non-ALU group relocation. */
5641 static struct group_reloc_table_entry group_reloc_table
[] =
5642 { /* Program counter relative: */
5644 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5649 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5650 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5651 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5652 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5654 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5659 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5660 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5661 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5662 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5664 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5665 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5666 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5667 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5668 /* Section base relative */
5670 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5675 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5676 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5677 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5678 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5680 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5685 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5686 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5687 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5688 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5690 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5691 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5692 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5693 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5694 /* Absolute thumb alu relocations. */
5696 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5701 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5706 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5711 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5716 /* Given the address of a pointer pointing to the textual name of a group
5717 relocation as may appear in assembler source, attempt to find its details
5718 in group_reloc_table. The pointer will be updated to the character after
5719 the trailing colon. On failure, FAIL will be returned; SUCCESS
5720 otherwise. On success, *entry will be updated to point at the relevant
5721 group_reloc_table entry. */
5724 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5727 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5729 int length
= strlen (group_reloc_table
[i
].name
);
5731 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5732 && (*str
)[length
] == ':')
5734 *out
= &group_reloc_table
[i
];
5735 *str
+= (length
+ 1);
5743 /* Parse a <shifter_operand> for an ARM data processing instruction
5744 (as for parse_shifter_operand) where group relocations are allowed:
5747 #<immediate>, <rotate>
5748 #:<group_reloc>:<expression>
5752 where <group_reloc> is one of the strings defined in group_reloc_table.
5753 The hashes are optional.
5755 Everything else is as for parse_shifter_operand. */
5757 static parse_operand_result
5758 parse_shifter_operand_group_reloc (char **str
, int i
)
5760 /* Determine if we have the sequence of characters #: or just :
5761 coming next. If we do, then we check for a group relocation.
5762 If we don't, punt the whole lot to parse_shifter_operand. */
5764 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5765 || (*str
)[0] == ':')
5767 struct group_reloc_table_entry
*entry
;
5769 if ((*str
)[0] == '#')
5774 /* Try to parse a group relocation. Anything else is an error. */
5775 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5777 inst
.error
= _("unknown group relocation");
5778 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5781 /* We now have the group relocation table entry corresponding to
5782 the name in the assembler source. Next, we parse the expression. */
5783 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5784 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5786 /* Record the relocation type (always the ALU variant here). */
5787 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5788 gas_assert (inst
.relocs
[0].type
!= 0);
5790 return PARSE_OPERAND_SUCCESS
;
5793 return parse_shifter_operand (str
, i
) == SUCCESS
5794 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5796 /* Never reached. */
5799 /* Parse a Neon alignment expression. Information is written to
5800 inst.operands[i]. We assume the initial ':' has been skipped.
5802 align .imm = align << 8, .immisalign=1, .preind=0 */
5803 static parse_operand_result
5804 parse_neon_alignment (char **str
, int i
)
5809 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5811 if (exp
.X_op
!= O_constant
)
5813 inst
.error
= _("alignment must be constant");
5814 return PARSE_OPERAND_FAIL
;
5817 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5818 inst
.operands
[i
].immisalign
= 1;
5819 /* Alignments are not pre-indexes. */
5820 inst
.operands
[i
].preind
= 0;
5823 return PARSE_OPERAND_SUCCESS
;
5826 /* Parse all forms of an ARM address expression. Information is written
5827 to inst.operands[i] and/or inst.relocs[0].
5829 Preindexed addressing (.preind=1):
5831 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5832 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5833 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5834 .shift_kind=shift .relocs[0].exp=shift_imm
5836 These three may have a trailing ! which causes .writeback to be set also.
5838 Postindexed addressing (.postind=1, .writeback=1):
5840 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5841 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5842 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5843 .shift_kind=shift .relocs[0].exp=shift_imm
5845 Unindexed addressing (.preind=0, .postind=0):
5847 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5851 [Rn]{!} shorthand for [Rn,#0]{!}
5852 =immediate .isreg=0 .relocs[0].exp=immediate
5853 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5855 It is the caller's responsibility to check for addressing modes not
5856 supported by the instruction, and to set inst.relocs[0].type. */
5858 static parse_operand_result
5859 parse_address_main (char **str
, int i
, int group_relocations
,
5860 group_reloc_type group_type
)
5865 if (skip_past_char (&p
, '[') == FAIL
)
5867 if (skip_past_char (&p
, '=') == FAIL
)
5869 /* Bare address - translate to PC-relative offset. */
5870 inst
.relocs
[0].pc_rel
= 1;
5871 inst
.operands
[i
].reg
= REG_PC
;
5872 inst
.operands
[i
].isreg
= 1;
5873 inst
.operands
[i
].preind
= 1;
5875 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5876 return PARSE_OPERAND_FAIL
;
5878 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5879 /*allow_symbol_p=*/TRUE
))
5880 return PARSE_OPERAND_FAIL
;
5883 return PARSE_OPERAND_SUCCESS
;
5886 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5887 skip_whitespace (p
);
5889 if (group_type
== GROUP_MVE
)
5891 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5892 struct neon_type_el et
;
5893 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5895 inst
.operands
[i
].isquad
= 1;
5897 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5899 inst
.error
= BAD_ADDR_MODE
;
5900 return PARSE_OPERAND_FAIL
;
5903 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5905 if (group_type
== GROUP_MVE
)
5906 inst
.error
= BAD_ADDR_MODE
;
5908 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5909 return PARSE_OPERAND_FAIL
;
5911 inst
.operands
[i
].reg
= reg
;
5912 inst
.operands
[i
].isreg
= 1;
5914 if (skip_past_comma (&p
) == SUCCESS
)
5916 inst
.operands
[i
].preind
= 1;
5919 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5921 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5922 struct neon_type_el et
;
5923 if (group_type
== GROUP_MVE
5924 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5926 inst
.operands
[i
].immisreg
= 2;
5927 inst
.operands
[i
].imm
= reg
;
5929 if (skip_past_comma (&p
) == SUCCESS
)
5931 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5933 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5934 inst
.relocs
[0].exp
.X_add_number
= 0;
5937 return PARSE_OPERAND_FAIL
;
5940 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5942 inst
.operands
[i
].imm
= reg
;
5943 inst
.operands
[i
].immisreg
= 1;
5945 if (skip_past_comma (&p
) == SUCCESS
)
5946 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5947 return PARSE_OPERAND_FAIL
;
5949 else if (skip_past_char (&p
, ':') == SUCCESS
)
5951 /* FIXME: '@' should be used here, but it's filtered out by generic
5952 code before we get to see it here. This may be subject to
5954 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5956 if (result
!= PARSE_OPERAND_SUCCESS
)
5961 if (inst
.operands
[i
].negative
)
5963 inst
.operands
[i
].negative
= 0;
5967 if (group_relocations
5968 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5970 struct group_reloc_table_entry
*entry
;
5972 /* Skip over the #: or : sequence. */
5978 /* Try to parse a group relocation. Anything else is an
5980 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5982 inst
.error
= _("unknown group relocation");
5983 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5986 /* We now have the group relocation table entry corresponding to
5987 the name in the assembler source. Next, we parse the
5989 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5990 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5992 /* Record the relocation type. */
5997 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6002 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6007 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6014 if (inst
.relocs
[0].type
== 0)
6016 inst
.error
= _("this group relocation is not allowed on this instruction");
6017 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6024 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6025 return PARSE_OPERAND_FAIL
;
6026 /* If the offset is 0, find out if it's a +0 or -0. */
6027 if (inst
.relocs
[0].exp
.X_op
== O_constant
6028 && inst
.relocs
[0].exp
.X_add_number
== 0)
6030 skip_whitespace (q
);
6034 skip_whitespace (q
);
6037 inst
.operands
[i
].negative
= 1;
6042 else if (skip_past_char (&p
, ':') == SUCCESS
)
6044 /* FIXME: '@' should be used here, but it's filtered out by generic code
6045 before we get to see it here. This may be subject to change. */
6046 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6048 if (result
!= PARSE_OPERAND_SUCCESS
)
6052 if (skip_past_char (&p
, ']') == FAIL
)
6054 inst
.error
= _("']' expected");
6055 return PARSE_OPERAND_FAIL
;
6058 if (skip_past_char (&p
, '!') == SUCCESS
)
6059 inst
.operands
[i
].writeback
= 1;
6061 else if (skip_past_comma (&p
) == SUCCESS
)
6063 if (skip_past_char (&p
, '{') == SUCCESS
)
6065 /* [Rn], {expr} - unindexed, with option */
6066 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6067 0, 255, TRUE
) == FAIL
)
6068 return PARSE_OPERAND_FAIL
;
6070 if (skip_past_char (&p
, '}') == FAIL
)
6072 inst
.error
= _("'}' expected at end of 'option' field");
6073 return PARSE_OPERAND_FAIL
;
6075 if (inst
.operands
[i
].preind
)
6077 inst
.error
= _("cannot combine index with option");
6078 return PARSE_OPERAND_FAIL
;
6081 return PARSE_OPERAND_SUCCESS
;
6085 inst
.operands
[i
].postind
= 1;
6086 inst
.operands
[i
].writeback
= 1;
6088 if (inst
.operands
[i
].preind
)
6090 inst
.error
= _("cannot combine pre- and post-indexing");
6091 return PARSE_OPERAND_FAIL
;
6095 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6097 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6098 struct neon_type_el et
;
6099 if (group_type
== GROUP_MVE
6100 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6102 inst
.operands
[i
].immisreg
= 2;
6103 inst
.operands
[i
].imm
= reg
;
6105 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6107 /* We might be using the immediate for alignment already. If we
6108 are, OR the register number into the low-order bits. */
6109 if (inst
.operands
[i
].immisalign
)
6110 inst
.operands
[i
].imm
|= reg
;
6112 inst
.operands
[i
].imm
= reg
;
6113 inst
.operands
[i
].immisreg
= 1;
6115 if (skip_past_comma (&p
) == SUCCESS
)
6116 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6117 return PARSE_OPERAND_FAIL
;
6123 if (inst
.operands
[i
].negative
)
6125 inst
.operands
[i
].negative
= 0;
6128 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6129 return PARSE_OPERAND_FAIL
;
6130 /* If the offset is 0, find out if it's a +0 or -0. */
6131 if (inst
.relocs
[0].exp
.X_op
== O_constant
6132 && inst
.relocs
[0].exp
.X_add_number
== 0)
6134 skip_whitespace (q
);
6138 skip_whitespace (q
);
6141 inst
.operands
[i
].negative
= 1;
6147 /* If at this point neither .preind nor .postind is set, we have a
6148 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6149 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6151 inst
.operands
[i
].preind
= 1;
6152 inst
.relocs
[0].exp
.X_op
= O_constant
;
6153 inst
.relocs
[0].exp
.X_add_number
= 0;
6156 return PARSE_OPERAND_SUCCESS
;
6160 parse_address (char **str
, int i
)
6162 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6166 static parse_operand_result
6167 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6169 return parse_address_main (str
, i
, 1, type
);
6172 /* Parse an operand for a MOVW or MOVT instruction. */
6174 parse_half (char **str
)
6179 skip_past_char (&p
, '#');
6180 if (strncasecmp (p
, ":lower16:", 9) == 0)
6181 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6182 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6183 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6185 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6188 skip_whitespace (p
);
6191 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6194 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6196 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6198 inst
.error
= _("constant expression expected");
6201 if (inst
.relocs
[0].exp
.X_add_number
< 0
6202 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6204 inst
.error
= _("immediate value out of range");
6212 /* Miscellaneous. */
6214 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6215 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6217 parse_psr (char **str
, bfd_boolean lhs
)
6220 unsigned long psr_field
;
6221 const struct asm_psr
*psr
;
6223 bfd_boolean is_apsr
= FALSE
;
6224 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6226 /* PR gas/12698: If the user has specified -march=all then m_profile will
6227 be TRUE, but we want to ignore it in this case as we are building for any
6228 CPU type, including non-m variants. */
6229 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6232 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6233 feature for ease of use and backwards compatibility. */
6235 if (strncasecmp (p
, "SPSR", 4) == 0)
6238 goto unsupported_psr
;
6240 psr_field
= SPSR_BIT
;
6242 else if (strncasecmp (p
, "CPSR", 4) == 0)
6245 goto unsupported_psr
;
6249 else if (strncasecmp (p
, "APSR", 4) == 0)
6251 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6252 and ARMv7-R architecture CPUs. */
6261 while (ISALNUM (*p
) || *p
== '_');
6263 if (strncasecmp (start
, "iapsr", 5) == 0
6264 || strncasecmp (start
, "eapsr", 5) == 0
6265 || strncasecmp (start
, "xpsr", 4) == 0
6266 || strncasecmp (start
, "psr", 3) == 0)
6267 p
= start
+ strcspn (start
, "rR") + 1;
6269 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6275 /* If APSR is being written, a bitfield may be specified. Note that
6276 APSR itself is handled above. */
6277 if (psr
->field
<= 3)
6279 psr_field
= psr
->field
;
6285 /* M-profile MSR instructions have the mask field set to "10", except
6286 *PSR variants which modify APSR, which may use a different mask (and
6287 have been handled already). Do that by setting the PSR_f field
6289 return psr
->field
| (lhs
? PSR_f
: 0);
6292 goto unsupported_psr
;
6298 /* A suffix follows. */
6304 while (ISALNUM (*p
) || *p
== '_');
6308 /* APSR uses a notation for bits, rather than fields. */
6309 unsigned int nzcvq_bits
= 0;
6310 unsigned int g_bit
= 0;
6313 for (bit
= start
; bit
!= p
; bit
++)
6315 switch (TOLOWER (*bit
))
6318 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6322 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6326 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6330 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6334 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6338 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6342 inst
.error
= _("unexpected bit specified after APSR");
6347 if (nzcvq_bits
== 0x1f)
6352 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6354 inst
.error
= _("selected processor does not "
6355 "support DSP extension");
6362 if ((nzcvq_bits
& 0x20) != 0
6363 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6364 || (g_bit
& 0x2) != 0)
6366 inst
.error
= _("bad bitmask specified after APSR");
6372 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6377 psr_field
|= psr
->field
;
6383 goto error
; /* Garbage after "[CS]PSR". */
6385 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6386 is deprecated, but allow it anyway. */
6390 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6393 else if (!m_profile
)
6394 /* These bits are never right for M-profile devices: don't set them
6395 (only code paths which read/write APSR reach here). */
6396 psr_field
|= (PSR_c
| PSR_f
);
6402 inst
.error
= _("selected processor does not support requested special "
6403 "purpose register");
6407 inst
.error
= _("flag for {c}psr instruction expected");
6412 parse_sys_vldr_vstr (char **str
)
6421 {"FPSCR", 0x1, 0x0},
6422 {"FPSCR_nzcvqc", 0x2, 0x0},
6425 {"FPCXTNS", 0x6, 0x1},
6426 {"FPCXTS", 0x7, 0x1}
6428 char *op_end
= strchr (*str
, ',');
6429 size_t op_strlen
= op_end
- *str
;
6431 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6433 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6435 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6444 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6445 value suitable for splatting into the AIF field of the instruction. */
6448 parse_cps_flags (char **str
)
6457 case '\0': case ',':
6460 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6461 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6462 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6465 inst
.error
= _("unrecognized CPS flag");
6470 if (saw_a_flag
== 0)
6472 inst
.error
= _("missing CPS flags");
6480 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6481 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6484 parse_endian_specifier (char **str
)
6489 if (strncasecmp (s
, "BE", 2))
6491 else if (strncasecmp (s
, "LE", 2))
6495 inst
.error
= _("valid endian specifiers are be or le");
6499 if (ISALNUM (s
[2]) || s
[2] == '_')
6501 inst
.error
= _("valid endian specifiers are be or le");
6506 return little_endian
;
6509 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6510 value suitable for poking into the rotate field of an sxt or sxta
6511 instruction, or FAIL on error. */
6514 parse_ror (char **str
)
6519 if (strncasecmp (s
, "ROR", 3) == 0)
6523 inst
.error
= _("missing rotation field after comma");
6527 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6532 case 0: *str
= s
; return 0x0;
6533 case 8: *str
= s
; return 0x1;
6534 case 16: *str
= s
; return 0x2;
6535 case 24: *str
= s
; return 0x3;
6538 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6543 /* Parse a conditional code (from conds[] below). The value returned is in the
6544 range 0 .. 14, or FAIL. */
6546 parse_cond (char **str
)
6549 const struct asm_cond
*c
;
6551 /* Condition codes are always 2 characters, so matching up to
6552 3 characters is sufficient. */
6557 while (ISALPHA (*q
) && n
< 3)
6559 cond
[n
] = TOLOWER (*q
);
6564 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6567 inst
.error
= _("condition required");
6575 /* Parse an option for a barrier instruction. Returns the encoding for the
6578 parse_barrier (char **str
)
6581 const struct asm_barrier_opt
*o
;
6584 while (ISALPHA (*q
))
6587 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6592 if (!mark_feature_used (&o
->arch
))
6599 /* Parse the operands of a table branch instruction. Similar to a memory
6602 parse_tb (char **str
)
6607 if (skip_past_char (&p
, '[') == FAIL
)
6609 inst
.error
= _("'[' expected");
6613 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6615 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6618 inst
.operands
[0].reg
= reg
;
6620 if (skip_past_comma (&p
) == FAIL
)
6622 inst
.error
= _("',' expected");
6626 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6628 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6631 inst
.operands
[0].imm
= reg
;
6633 if (skip_past_comma (&p
) == SUCCESS
)
6635 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6637 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6639 inst
.error
= _("invalid shift");
6642 inst
.operands
[0].shifted
= 1;
6645 if (skip_past_char (&p
, ']') == FAIL
)
6647 inst
.error
= _("']' expected");
6654 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6655 information on the types the operands can take and how they are encoded.
6656 Up to four operands may be read; this function handles setting the
6657 ".present" field for each read operand itself.
6658 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6659 else returns FAIL. */
6662 parse_neon_mov (char **str
, int *which_operand
)
6664 int i
= *which_operand
, val
;
6665 enum arm_reg_type rtype
;
6667 struct neon_type_el optype
;
6669 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6671 /* Cases 17 or 19. */
6672 inst
.operands
[i
].reg
= val
;
6673 inst
.operands
[i
].isvec
= 1;
6674 inst
.operands
[i
].isscalar
= 2;
6675 inst
.operands
[i
].vectype
= optype
;
6676 inst
.operands
[i
++].present
= 1;
6678 if (skip_past_comma (&ptr
) == FAIL
)
6681 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6683 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6684 inst
.operands
[i
].reg
= val
;
6685 inst
.operands
[i
].isreg
= 1;
6686 inst
.operands
[i
].present
= 1;
6688 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6690 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6691 inst
.operands
[i
].reg
= val
;
6692 inst
.operands
[i
].isvec
= 1;
6693 inst
.operands
[i
].isscalar
= 2;
6694 inst
.operands
[i
].vectype
= optype
;
6695 inst
.operands
[i
++].present
= 1;
6697 if (skip_past_comma (&ptr
) == FAIL
)
6700 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6703 inst
.operands
[i
].reg
= val
;
6704 inst
.operands
[i
].isreg
= 1;
6705 inst
.operands
[i
++].present
= 1;
6707 if (skip_past_comma (&ptr
) == FAIL
)
6710 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6713 inst
.operands
[i
].reg
= val
;
6714 inst
.operands
[i
].isreg
= 1;
6715 inst
.operands
[i
].present
= 1;
6719 first_error (_("expected ARM or MVE vector register"));
6723 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6725 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6726 inst
.operands
[i
].reg
= val
;
6727 inst
.operands
[i
].isscalar
= 1;
6728 inst
.operands
[i
].vectype
= optype
;
6729 inst
.operands
[i
++].present
= 1;
6731 if (skip_past_comma (&ptr
) == FAIL
)
6734 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6737 inst
.operands
[i
].reg
= val
;
6738 inst
.operands
[i
].isreg
= 1;
6739 inst
.operands
[i
].present
= 1;
6741 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6743 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6746 /* Cases 0, 1, 2, 3, 5 (D only). */
6747 if (skip_past_comma (&ptr
) == FAIL
)
6750 inst
.operands
[i
].reg
= val
;
6751 inst
.operands
[i
].isreg
= 1;
6752 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6753 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6754 inst
.operands
[i
].isvec
= 1;
6755 inst
.operands
[i
].vectype
= optype
;
6756 inst
.operands
[i
++].present
= 1;
6758 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6760 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6761 Case 13: VMOV <Sd>, <Rm> */
6762 inst
.operands
[i
].reg
= val
;
6763 inst
.operands
[i
].isreg
= 1;
6764 inst
.operands
[i
].present
= 1;
6766 if (rtype
== REG_TYPE_NQ
)
6768 first_error (_("can't use Neon quad register here"));
6771 else if (rtype
!= REG_TYPE_VFS
)
6774 if (skip_past_comma (&ptr
) == FAIL
)
6776 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6778 inst
.operands
[i
].reg
= val
;
6779 inst
.operands
[i
].isreg
= 1;
6780 inst
.operands
[i
].present
= 1;
6783 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6785 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6788 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6789 Case 1: VMOV<c><q> <Dd>, <Dm>
6790 Case 8: VMOV.F32 <Sd>, <Sm>
6791 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6793 inst
.operands
[i
].reg
= val
;
6794 inst
.operands
[i
].isreg
= 1;
6795 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6796 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6797 inst
.operands
[i
].isvec
= 1;
6798 inst
.operands
[i
].vectype
= optype
;
6799 inst
.operands
[i
].present
= 1;
6801 if (skip_past_comma (&ptr
) == SUCCESS
)
6806 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6809 inst
.operands
[i
].reg
= val
;
6810 inst
.operands
[i
].isreg
= 1;
6811 inst
.operands
[i
++].present
= 1;
6813 if (skip_past_comma (&ptr
) == FAIL
)
6816 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6819 inst
.operands
[i
].reg
= val
;
6820 inst
.operands
[i
].isreg
= 1;
6821 inst
.operands
[i
].present
= 1;
6824 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6825 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6826 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6827 Case 10: VMOV.F32 <Sd>, #<imm>
6828 Case 11: VMOV.F64 <Dd>, #<imm> */
6829 inst
.operands
[i
].immisfloat
= 1;
6830 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6832 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6833 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6837 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6841 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6843 /* Cases 6, 7, 16, 18. */
6844 inst
.operands
[i
].reg
= val
;
6845 inst
.operands
[i
].isreg
= 1;
6846 inst
.operands
[i
++].present
= 1;
6848 if (skip_past_comma (&ptr
) == FAIL
)
6851 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6853 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6854 inst
.operands
[i
].reg
= val
;
6855 inst
.operands
[i
].isscalar
= 2;
6856 inst
.operands
[i
].present
= 1;
6857 inst
.operands
[i
].vectype
= optype
;
6859 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6861 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6862 inst
.operands
[i
].reg
= val
;
6863 inst
.operands
[i
].isscalar
= 1;
6864 inst
.operands
[i
].present
= 1;
6865 inst
.operands
[i
].vectype
= optype
;
6867 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6869 inst
.operands
[i
].reg
= val
;
6870 inst
.operands
[i
].isreg
= 1;
6871 inst
.operands
[i
++].present
= 1;
6873 if (skip_past_comma (&ptr
) == FAIL
)
6876 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6879 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6881 inst
.operands
[i
].reg
= val
;
6882 inst
.operands
[i
].isreg
= 1;
6883 inst
.operands
[i
].isvec
= 1;
6884 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6885 inst
.operands
[i
].vectype
= optype
;
6886 inst
.operands
[i
].present
= 1;
6888 if (rtype
== REG_TYPE_VFS
)
6892 if (skip_past_comma (&ptr
) == FAIL
)
6894 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6897 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6900 inst
.operands
[i
].reg
= val
;
6901 inst
.operands
[i
].isreg
= 1;
6902 inst
.operands
[i
].isvec
= 1;
6903 inst
.operands
[i
].issingle
= 1;
6904 inst
.operands
[i
].vectype
= optype
;
6905 inst
.operands
[i
].present
= 1;
6910 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6913 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6914 inst
.operands
[i
].reg
= val
;
6915 inst
.operands
[i
].isvec
= 1;
6916 inst
.operands
[i
].isscalar
= 2;
6917 inst
.operands
[i
].vectype
= optype
;
6918 inst
.operands
[i
++].present
= 1;
6920 if (skip_past_comma (&ptr
) == FAIL
)
6923 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6926 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6929 inst
.operands
[i
].reg
= val
;
6930 inst
.operands
[i
].isvec
= 1;
6931 inst
.operands
[i
].isscalar
= 2;
6932 inst
.operands
[i
].vectype
= optype
;
6933 inst
.operands
[i
].present
= 1;
6937 first_error (_("VFP single, double or MVE vector register"
6943 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6947 inst
.operands
[i
].reg
= val
;
6948 inst
.operands
[i
].isreg
= 1;
6949 inst
.operands
[i
].isvec
= 1;
6950 inst
.operands
[i
].issingle
= 1;
6951 inst
.operands
[i
].vectype
= optype
;
6952 inst
.operands
[i
].present
= 1;
6957 first_error (_("parse error"));
6961 /* Successfully parsed the operands. Update args. */
6967 first_error (_("expected comma"));
6971 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6975 /* Use this macro when the operand constraints are different
6976 for ARM and THUMB (e.g. ldrd). */
6977 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6978 ((arm_operand) | ((thumb_operand) << 16))
6980 /* Matcher codes for parse_operands. */
6981 enum operand_parse_code
6983 OP_stop
, /* end of line */
6985 OP_RR
, /* ARM register */
6986 OP_RRnpc
, /* ARM register, not r15 */
6987 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6988 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6989 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6990 optional trailing ! */
6991 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6992 OP_RCP
, /* Coprocessor number */
6993 OP_RCN
, /* Coprocessor register */
6994 OP_RF
, /* FPA register */
6995 OP_RVS
, /* VFP single precision register */
6996 OP_RVD
, /* VFP double precision register (0..15) */
6997 OP_RND
, /* Neon double precision register (0..31) */
6998 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6999 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7001 OP_RNQ
, /* Neon quad precision register */
7002 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7003 OP_RVSD
, /* VFP single or double precision register */
7004 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7005 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7006 OP_RNSD
, /* Neon single or double precision register */
7007 OP_RNDQ
, /* Neon double or quad precision register */
7008 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7009 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7010 OP_RNSDQ
, /* Neon single, double or quad precision register */
7011 OP_RNSC
, /* Neon scalar D[X] */
7012 OP_RVC
, /* VFP control register */
7013 OP_RMF
, /* Maverick F register */
7014 OP_RMD
, /* Maverick D register */
7015 OP_RMFX
, /* Maverick FX register */
7016 OP_RMDX
, /* Maverick DX register */
7017 OP_RMAX
, /* Maverick AX register */
7018 OP_RMDS
, /* Maverick DSPSC register */
7019 OP_RIWR
, /* iWMMXt wR register */
7020 OP_RIWC
, /* iWMMXt wC register */
7021 OP_RIWG
, /* iWMMXt wCG register */
7022 OP_RXA
, /* XScale accumulator register */
7024 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7026 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7028 OP_RMQ
, /* MVE vector register. */
7029 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7030 OP_RMQRR
, /* MVE vector or ARM register. */
7032 /* New operands for Armv8.1-M Mainline. */
7033 OP_LR
, /* ARM LR register */
7034 OP_RRe
, /* ARM register, only even numbered. */
7035 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7036 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7037 OP_RR_ZR
, /* ARM register or ZR but no PC */
7039 OP_REGLST
, /* ARM register list */
7040 OP_CLRMLST
, /* CLRM register list */
7041 OP_VRSLST
, /* VFP single-precision register list */
7042 OP_VRDLST
, /* VFP double-precision register list */
7043 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7044 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7045 OP_NSTRLST
, /* Neon element/structure list */
7046 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7047 OP_MSTRLST2
, /* MVE vector list with two elements. */
7048 OP_MSTRLST4
, /* MVE vector list with four elements. */
7050 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7051 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7052 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7053 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7055 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7056 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7057 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7058 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7060 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7061 scalar, or ARM register. */
7062 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7063 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7064 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7066 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7067 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7068 OP_VMOV
, /* Neon VMOV operands. */
7069 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7070 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7072 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7073 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7075 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7076 OP_VLDR
, /* VLDR operand. */
7078 OP_I0
, /* immediate zero */
7079 OP_I7
, /* immediate value 0 .. 7 */
7080 OP_I15
, /* 0 .. 15 */
7081 OP_I16
, /* 1 .. 16 */
7082 OP_I16z
, /* 0 .. 16 */
7083 OP_I31
, /* 0 .. 31 */
7084 OP_I31w
, /* 0 .. 31, optional trailing ! */
7085 OP_I32
, /* 1 .. 32 */
7086 OP_I32z
, /* 0 .. 32 */
7087 OP_I48_I64
, /* 48 or 64 */
7088 OP_I63
, /* 0 .. 63 */
7089 OP_I63s
, /* -64 .. 63 */
7090 OP_I64
, /* 1 .. 64 */
7091 OP_I64z
, /* 0 .. 64 */
7092 OP_I255
, /* 0 .. 255 */
7094 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7095 OP_I7b
, /* 0 .. 7 */
7096 OP_I15b
, /* 0 .. 15 */
7097 OP_I31b
, /* 0 .. 31 */
7099 OP_SH
, /* shifter operand */
7100 OP_SHG
, /* shifter operand with possible group relocation */
7101 OP_ADDR
, /* Memory address expression (any mode) */
7102 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7103 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7104 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7105 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7106 OP_EXP
, /* arbitrary expression */
7107 OP_EXPi
, /* same, with optional immediate prefix */
7108 OP_EXPr
, /* same, with optional relocation suffix */
7109 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7110 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7111 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7112 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7114 OP_CPSF
, /* CPS flags */
7115 OP_ENDI
, /* Endianness specifier */
7116 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7117 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7118 OP_COND
, /* conditional code */
7119 OP_TB
, /* Table branch. */
7121 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7123 OP_RRnpc_I0
, /* ARM register or literal 0 */
7124 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7125 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7126 OP_RF_IF
, /* FPA register or immediate */
7127 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7128 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7130 /* Optional operands. */
7131 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7132 OP_oI31b
, /* 0 .. 31 */
7133 OP_oI32b
, /* 1 .. 32 */
7134 OP_oI32z
, /* 0 .. 32 */
7135 OP_oIffffb
, /* 0 .. 65535 */
7136 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7138 OP_oRR
, /* ARM register */
7139 OP_oLR
, /* ARM LR register */
7140 OP_oRRnpc
, /* ARM register, not the PC */
7141 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7142 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7143 OP_oRND
, /* Optional Neon double precision register */
7144 OP_oRNQ
, /* Optional Neon quad precision register */
7145 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7146 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7147 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7148 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7150 OP_oSHll
, /* LSL immediate */
7151 OP_oSHar
, /* ASR immediate */
7152 OP_oSHllar
, /* LSL or ASR immediate */
7153 OP_oROR
, /* ROR 0/8/16/24 */
7154 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7156 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7158 /* Some pre-defined mixed (ARM/THUMB) operands. */
7159 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7160 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7161 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7163 OP_FIRST_OPTIONAL
= OP_oI7b
7166 /* Generic instruction operand parser. This does no encoding and no
7167 semantic validation; it merely squirrels values away in the inst
7168 structure. Returns SUCCESS or FAIL depending on whether the
7169 specified grammar matched. */
7171 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7173 unsigned const int *upat
= pattern
;
7174 char *backtrack_pos
= 0;
7175 const char *backtrack_error
= 0;
7176 int i
, val
= 0, backtrack_index
= 0;
7177 enum arm_reg_type rtype
;
7178 parse_operand_result result
;
7179 unsigned int op_parse_code
;
7180 bfd_boolean partial_match
;
7182 #define po_char_or_fail(chr) \
7185 if (skip_past_char (&str, chr) == FAIL) \
7190 #define po_reg_or_fail(regtype) \
7193 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7194 & inst.operands[i].vectype); \
7197 first_error (_(reg_expected_msgs[regtype])); \
7200 inst.operands[i].reg = val; \
7201 inst.operands[i].isreg = 1; \
7202 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7203 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7204 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7205 || rtype == REG_TYPE_VFD \
7206 || rtype == REG_TYPE_NQ); \
7207 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7211 #define po_reg_or_goto(regtype, label) \
7214 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7215 & inst.operands[i].vectype); \
7219 inst.operands[i].reg = val; \
7220 inst.operands[i].isreg = 1; \
7221 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7222 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7223 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7224 || rtype == REG_TYPE_VFD \
7225 || rtype == REG_TYPE_NQ); \
7226 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7230 #define po_imm_or_fail(min, max, popt) \
7233 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7235 inst.operands[i].imm = val; \
7239 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7243 my_get_expression (&exp, &str, popt); \
7244 if (exp.X_op != O_constant) \
7246 inst.error = _("constant expression required"); \
7249 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7251 inst.error = _("immediate value 48 or 64 expected"); \
7254 inst.operands[i].imm = exp.X_add_number; \
7258 #define po_scalar_or_goto(elsz, label, reg_type) \
7261 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7265 inst.operands[i].reg = val; \
7266 inst.operands[i].isscalar = 1; \
7270 #define po_misc_or_fail(expr) \
7278 #define po_misc_or_fail_no_backtrack(expr) \
7282 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7283 backtrack_pos = 0; \
7284 if (result != PARSE_OPERAND_SUCCESS) \
7289 #define po_barrier_or_imm(str) \
7292 val = parse_barrier (&str); \
7293 if (val == FAIL && ! ISALPHA (*str)) \
7296 /* ISB can only take SY as an option. */ \
7297 || ((inst.instruction & 0xf0) == 0x60 \
7300 inst.error = _("invalid barrier type"); \
7301 backtrack_pos = 0; \
7307 skip_whitespace (str
);
7309 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7311 op_parse_code
= upat
[i
];
7312 if (op_parse_code
>= 1<<16)
7313 op_parse_code
= thumb
? (op_parse_code
>> 16)
7314 : (op_parse_code
& ((1<<16)-1));
7316 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7318 /* Remember where we are in case we need to backtrack. */
7319 backtrack_pos
= str
;
7320 backtrack_error
= inst
.error
;
7321 backtrack_index
= i
;
7324 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7325 po_char_or_fail (',');
7327 switch (op_parse_code
)
7339 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7340 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7341 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7342 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7343 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7344 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7347 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7351 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7354 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7356 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7358 /* Also accept generic coprocessor regs for unknown registers. */
7360 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7362 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7363 existing register with a value of 0, this seems like the
7364 best way to parse P0. */
7366 if (strncasecmp (str
, "P0", 2) == 0)
7369 inst
.operands
[i
].isreg
= 1;
7370 inst
.operands
[i
].reg
= 13;
7375 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7376 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7377 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7378 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7379 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7380 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7381 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7382 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7383 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7384 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7387 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7390 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7391 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7393 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7398 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7402 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7404 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7407 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7409 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7412 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7414 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7419 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7422 po_reg_or_fail (REG_TYPE_NSDQ
);
7426 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7430 po_reg_or_fail (REG_TYPE_MQ
);
7432 /* Neon scalar. Using an element size of 8 means that some invalid
7433 scalars are accepted here, so deal with those in later code. */
7434 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7438 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7441 po_imm_or_fail (0, 0, TRUE
);
7446 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7450 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7455 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7458 if (parse_ifimm_zero (&str
))
7459 inst
.operands
[i
].imm
= 0;
7463 = _("only floating point zero is allowed as immediate value");
7471 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7474 po_reg_or_fail (REG_TYPE_RN
);
7478 case OP_RNSDQ_RNSC_MQ_RR
:
7479 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7482 case OP_RNSDQ_RNSC_MQ
:
7483 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7488 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7492 po_reg_or_fail (REG_TYPE_NSDQ
);
7499 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7502 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7505 po_reg_or_fail (REG_TYPE_NSD
);
7509 case OP_RNDQMQ_RNSC_RR
:
7510 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7513 case OP_RNDQ_RNSC_RR
:
7514 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7516 case OP_RNDQMQ_RNSC
:
7517 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7522 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7525 po_reg_or_fail (REG_TYPE_NDQ
);
7531 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7534 po_reg_or_fail (REG_TYPE_VFD
);
7539 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7540 not careful then bad things might happen. */
7541 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7544 case OP_RNDQMQ_Ibig
:
7545 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7550 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7553 /* There's a possibility of getting a 64-bit immediate here, so
7554 we need special handling. */
7555 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7558 inst
.error
= _("immediate value is out of range");
7564 case OP_RNDQMQ_I63b_RR
:
7565 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7568 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7573 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7576 po_imm_or_fail (0, 63, TRUE
);
7581 po_char_or_fail ('[');
7582 po_reg_or_fail (REG_TYPE_RN
);
7583 po_char_or_fail (']');
7589 po_reg_or_fail (REG_TYPE_RN
);
7590 if (skip_past_char (&str
, '!') == SUCCESS
)
7591 inst
.operands
[i
].writeback
= 1;
7595 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7596 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7597 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7598 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7599 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7600 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7601 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7602 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7603 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7604 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7605 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7606 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7607 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7609 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7611 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7612 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7614 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7615 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7616 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7617 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7619 /* Immediate variants */
7621 po_char_or_fail ('{');
7622 po_imm_or_fail (0, 255, TRUE
);
7623 po_char_or_fail ('}');
7627 /* The expression parser chokes on a trailing !, so we have
7628 to find it first and zap it. */
7631 while (*s
&& *s
!= ',')
7636 inst
.operands
[i
].writeback
= 1;
7638 po_imm_or_fail (0, 31, TRUE
);
7646 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7651 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7656 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7658 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7660 val
= parse_reloc (&str
);
7663 inst
.error
= _("unrecognized relocation suffix");
7666 else if (val
!= BFD_RELOC_UNUSED
)
7668 inst
.operands
[i
].imm
= val
;
7669 inst
.operands
[i
].hasreloc
= 1;
7675 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7677 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7679 inst
.operands
[i
].hasreloc
= 1;
7681 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7683 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7684 inst
.operands
[i
].hasreloc
= 0;
7688 /* Operand for MOVW or MOVT. */
7690 po_misc_or_fail (parse_half (&str
));
7693 /* Register or expression. */
7694 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7695 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7697 /* Register or immediate. */
7698 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7699 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7701 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7702 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7704 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7706 if (!is_immediate_prefix (*str
))
7709 val
= parse_fpa_immediate (&str
);
7712 /* FPA immediates are encoded as registers 8-15.
7713 parse_fpa_immediate has already applied the offset. */
7714 inst
.operands
[i
].reg
= val
;
7715 inst
.operands
[i
].isreg
= 1;
7718 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7719 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7721 /* Two kinds of register. */
7724 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7726 || (rege
->type
!= REG_TYPE_MMXWR
7727 && rege
->type
!= REG_TYPE_MMXWC
7728 && rege
->type
!= REG_TYPE_MMXWCG
))
7730 inst
.error
= _("iWMMXt data or control register expected");
7733 inst
.operands
[i
].reg
= rege
->number
;
7734 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7740 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7742 || (rege
->type
!= REG_TYPE_MMXWC
7743 && rege
->type
!= REG_TYPE_MMXWCG
))
7745 inst
.error
= _("iWMMXt control register expected");
7748 inst
.operands
[i
].reg
= rege
->number
;
7749 inst
.operands
[i
].isreg
= 1;
7754 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7755 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7756 case OP_oROR
: val
= parse_ror (&str
); break;
7758 case OP_COND
: val
= parse_cond (&str
); break;
7759 case OP_oBARRIER_I15
:
7760 po_barrier_or_imm (str
); break;
7762 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7768 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7769 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7771 inst
.error
= _("Banked registers are not available with this "
7777 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7781 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7784 val
= parse_sys_vldr_vstr (&str
);
7788 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7791 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7793 if (strncasecmp (str
, "APSR_", 5) == 0)
7800 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7801 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7802 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7803 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7804 default: found
= 16;
7808 inst
.operands
[i
].isvec
= 1;
7809 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7810 inst
.operands
[i
].reg
= REG_PC
;
7817 po_misc_or_fail (parse_tb (&str
));
7820 /* Register lists. */
7822 val
= parse_reg_list (&str
, REGLIST_RN
);
7825 inst
.operands
[i
].writeback
= 1;
7831 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7835 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7840 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7845 /* Allow Q registers too. */
7846 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7847 REGLIST_NEON_D
, &partial_match
);
7851 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7852 REGLIST_VFP_S
, &partial_match
);
7853 inst
.operands
[i
].issingle
= 1;
7858 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7859 REGLIST_VFP_D_VPR
, &partial_match
);
7860 if (val
== FAIL
&& !partial_match
)
7863 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7864 REGLIST_VFP_S_VPR
, &partial_match
);
7865 inst
.operands
[i
].issingle
= 1;
7870 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7871 REGLIST_NEON_D
, &partial_match
);
7876 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7877 1, &inst
.operands
[i
].vectype
);
7878 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7882 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7883 0, &inst
.operands
[i
].vectype
);
7886 /* Addressing modes */
7888 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7892 po_misc_or_fail (parse_address (&str
, i
));
7896 po_misc_or_fail_no_backtrack (
7897 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7901 po_misc_or_fail_no_backtrack (
7902 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7906 po_misc_or_fail_no_backtrack (
7907 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7911 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7915 po_misc_or_fail_no_backtrack (
7916 parse_shifter_operand_group_reloc (&str
, i
));
7920 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7924 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7928 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7933 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7938 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7941 po_reg_or_fail (REG_TYPE_ZR
);
7945 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7948 /* Various value-based sanity checks and shared operations. We
7949 do not signal immediate failures for the register constraints;
7950 this allows a syntax error to take precedence. */
7951 switch (op_parse_code
)
7959 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7960 inst
.error
= BAD_PC
;
7965 case OP_RRnpcsp_I32
:
7966 if (inst
.operands
[i
].isreg
)
7968 if (inst
.operands
[i
].reg
== REG_PC
)
7969 inst
.error
= BAD_PC
;
7970 else if (inst
.operands
[i
].reg
== REG_SP
7971 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7972 relaxed since ARMv8-A. */
7973 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7976 inst
.error
= BAD_SP
;
7982 if (inst
.operands
[i
].isreg
7983 && inst
.operands
[i
].reg
== REG_PC
7984 && (inst
.operands
[i
].writeback
|| thumb
))
7985 inst
.error
= BAD_PC
;
7990 if (inst
.operands
[i
].isreg
)
8000 case OP_oBARRIER_I15
:
8013 inst
.operands
[i
].imm
= val
;
8018 if (inst
.operands
[i
].reg
!= REG_LR
)
8019 inst
.error
= _("operand must be LR register");
8025 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8026 inst
.error
= BAD_PC
;
8030 if (inst
.operands
[i
].isreg
8031 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8032 inst
.error
= BAD_ODD
;
8036 if (inst
.operands
[i
].isreg
)
8038 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8039 inst
.error
= BAD_EVEN
;
8040 else if (inst
.operands
[i
].reg
== REG_SP
)
8041 as_tsktsk (MVE_BAD_SP
);
8042 else if (inst
.operands
[i
].reg
== REG_PC
)
8043 inst
.error
= BAD_PC
;
8051 /* If we get here, this operand was successfully parsed. */
8052 inst
.operands
[i
].present
= 1;
8056 inst
.error
= BAD_ARGS
;
8061 /* The parse routine should already have set inst.error, but set a
8062 default here just in case. */
8064 inst
.error
= BAD_SYNTAX
;
8068 /* Do not backtrack over a trailing optional argument that
8069 absorbed some text. We will only fail again, with the
8070 'garbage following instruction' error message, which is
8071 probably less helpful than the current one. */
8072 if (backtrack_index
== i
&& backtrack_pos
!= str
8073 && upat
[i
+1] == OP_stop
)
8076 inst
.error
= BAD_SYNTAX
;
8080 /* Try again, skipping the optional argument at backtrack_pos. */
8081 str
= backtrack_pos
;
8082 inst
.error
= backtrack_error
;
8083 inst
.operands
[backtrack_index
].present
= 0;
8084 i
= backtrack_index
;
8088 /* Check that we have parsed all the arguments. */
8089 if (*str
!= '\0' && !inst
.error
)
8090 inst
.error
= _("garbage following instruction");
8092 return inst
.error
? FAIL
: SUCCESS
;
8095 #undef po_char_or_fail
8096 #undef po_reg_or_fail
8097 #undef po_reg_or_goto
8098 #undef po_imm_or_fail
8099 #undef po_scalar_or_fail
8100 #undef po_barrier_or_imm
8102 /* Shorthand macro for instruction encoding functions issuing errors. */
8103 #define constraint(expr, err) \
8114 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8115 instructions are unpredictable if these registers are used. This
8116 is the BadReg predicate in ARM's Thumb-2 documentation.
8118 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8119 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8120 #define reject_bad_reg(reg) \
8122 if (reg == REG_PC) \
8124 inst.error = BAD_PC; \
8127 else if (reg == REG_SP \
8128 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8130 inst.error = BAD_SP; \
8135 /* If REG is R13 (the stack pointer), warn that its use is
8137 #define warn_deprecated_sp(reg) \
8139 if (warn_on_deprecated && reg == REG_SP) \
8140 as_tsktsk (_("use of r13 is deprecated")); \
8143 /* Functions for operand encoding. ARM, then Thumb. */
8145 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8147 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8149 The only binary encoding difference is the Coprocessor number. Coprocessor
8150 9 is used for half-precision calculations or conversions. The format of the
8151 instruction is the same as the equivalent Coprocessor 10 instruction that
8152 exists for Single-Precision operation. */
8155 do_scalar_fp16_v82_encode (void)
8157 if (inst
.cond
< COND_ALWAYS
)
8158 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8159 " the behaviour is UNPREDICTABLE"));
8160 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8163 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8164 mark_feature_used (&arm_ext_fp16
);
8167 /* If VAL can be encoded in the immediate field of an ARM instruction,
8168 return the encoded form. Otherwise, return FAIL. */
8171 encode_arm_immediate (unsigned int val
)
8178 for (i
= 2; i
< 32; i
+= 2)
8179 if ((a
= rotate_left (val
, i
)) <= 0xff)
8180 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8185 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8186 return the encoded form. Otherwise, return FAIL. */
8188 encode_thumb32_immediate (unsigned int val
)
8195 for (i
= 1; i
<= 24; i
++)
8198 if ((val
& ~(0xff << i
)) == 0)
8199 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8203 if (val
== ((a
<< 16) | a
))
8205 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8209 if (val
== ((a
<< 16) | a
))
8210 return 0x200 | (a
>> 8);
8214 /* Encode a VFP SP or DP register number into inst.instruction. */
8217 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8219 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8222 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8225 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8228 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8233 first_error (_("D register out of range for selected VFP version"));
8241 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8245 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8249 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8253 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8257 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8261 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8269 /* Encode a <shift> in an ARM-format instruction. The immediate,
8270 if any, is handled by md_apply_fix. */
8272 encode_arm_shift (int i
)
8274 /* register-shifted register. */
8275 if (inst
.operands
[i
].immisreg
)
8278 for (op_index
= 0; op_index
<= i
; ++op_index
)
8280 /* Check the operand only when it's presented. In pre-UAL syntax,
8281 if the destination register is the same as the first operand, two
8282 register form of the instruction can be used. */
8283 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8284 && inst
.operands
[op_index
].reg
== REG_PC
)
8285 as_warn (UNPRED_REG ("r15"));
8288 if (inst
.operands
[i
].imm
== REG_PC
)
8289 as_warn (UNPRED_REG ("r15"));
8292 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8293 inst
.instruction
|= SHIFT_ROR
<< 5;
8296 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8297 if (inst
.operands
[i
].immisreg
)
8299 inst
.instruction
|= SHIFT_BY_REG
;
8300 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8303 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8308 encode_arm_shifter_operand (int i
)
8310 if (inst
.operands
[i
].isreg
)
8312 inst
.instruction
|= inst
.operands
[i
].reg
;
8313 encode_arm_shift (i
);
8317 inst
.instruction
|= INST_IMMEDIATE
;
8318 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8319 inst
.instruction
|= inst
.operands
[i
].imm
;
8323 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8325 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8328 Generate an error if the operand is not a register. */
8329 constraint (!inst
.operands
[i
].isreg
,
8330 _("Instruction does not support =N addresses"));
8332 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8334 if (inst
.operands
[i
].preind
)
8338 inst
.error
= _("instruction does not accept preindexed addressing");
8341 inst
.instruction
|= PRE_INDEX
;
8342 if (inst
.operands
[i
].writeback
)
8343 inst
.instruction
|= WRITE_BACK
;
8346 else if (inst
.operands
[i
].postind
)
8348 gas_assert (inst
.operands
[i
].writeback
);
8350 inst
.instruction
|= WRITE_BACK
;
8352 else /* unindexed - only for coprocessor */
8354 inst
.error
= _("instruction does not accept unindexed addressing");
8358 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8359 && (((inst
.instruction
& 0x000f0000) >> 16)
8360 == ((inst
.instruction
& 0x0000f000) >> 12)))
8361 as_warn ((inst
.instruction
& LOAD_BIT
)
8362 ? _("destination register same as write-back base")
8363 : _("source register same as write-back base"));
8366 /* inst.operands[i] was set up by parse_address. Encode it into an
8367 ARM-format mode 2 load or store instruction. If is_t is true,
8368 reject forms that cannot be used with a T instruction (i.e. not
8371 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8373 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8375 encode_arm_addr_mode_common (i
, is_t
);
8377 if (inst
.operands
[i
].immisreg
)
8379 constraint ((inst
.operands
[i
].imm
== REG_PC
8380 || (is_pc
&& inst
.operands
[i
].writeback
)),
8382 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8383 inst
.instruction
|= inst
.operands
[i
].imm
;
8384 if (!inst
.operands
[i
].negative
)
8385 inst
.instruction
|= INDEX_UP
;
8386 if (inst
.operands
[i
].shifted
)
8388 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8389 inst
.instruction
|= SHIFT_ROR
<< 5;
8392 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8393 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8397 else /* immediate offset in inst.relocs[0] */
8399 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8401 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8403 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8404 cannot use PC in addressing.
8405 PC cannot be used in writeback addressing, either. */
8406 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8409 /* Use of PC in str is deprecated for ARMv7. */
8410 if (warn_on_deprecated
8412 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8413 as_tsktsk (_("use of PC in this instruction is deprecated"));
8416 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8418 /* Prefer + for zero encoded value. */
8419 if (!inst
.operands
[i
].negative
)
8420 inst
.instruction
|= INDEX_UP
;
8421 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8426 /* inst.operands[i] was set up by parse_address. Encode it into an
8427 ARM-format mode 3 load or store instruction. Reject forms that
8428 cannot be used with such instructions. If is_t is true, reject
8429 forms that cannot be used with a T instruction (i.e. not
8432 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8434 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8436 inst
.error
= _("instruction does not accept scaled register index");
8440 encode_arm_addr_mode_common (i
, is_t
);
8442 if (inst
.operands
[i
].immisreg
)
8444 constraint ((inst
.operands
[i
].imm
== REG_PC
8445 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8447 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8449 inst
.instruction
|= inst
.operands
[i
].imm
;
8450 if (!inst
.operands
[i
].negative
)
8451 inst
.instruction
|= INDEX_UP
;
8453 else /* immediate offset in inst.relocs[0] */
8455 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8456 && inst
.operands
[i
].writeback
),
8458 inst
.instruction
|= HWOFFSET_IMM
;
8459 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8461 /* Prefer + for zero encoded value. */
8462 if (!inst
.operands
[i
].negative
)
8463 inst
.instruction
|= INDEX_UP
;
8465 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8470 /* Write immediate bits [7:0] to the following locations:
8472 |28/24|23 19|18 16|15 4|3 0|
8473 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8475 This function is used by VMOV/VMVN/VORR/VBIC. */
8478 neon_write_immbits (unsigned immbits
)
8480 inst
.instruction
|= immbits
& 0xf;
8481 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8482 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8485 /* Invert low-order SIZE bits of XHI:XLO. */
8488 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8490 unsigned immlo
= xlo
? *xlo
: 0;
8491 unsigned immhi
= xhi
? *xhi
: 0;
8496 immlo
= (~immlo
) & 0xff;
8500 immlo
= (~immlo
) & 0xffff;
8504 immhi
= (~immhi
) & 0xffffffff;
8508 immlo
= (~immlo
) & 0xffffffff;
8522 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8526 neon_bits_same_in_bytes (unsigned imm
)
8528 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8529 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8530 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8531 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8534 /* For immediate of above form, return 0bABCD. */
8537 neon_squash_bits (unsigned imm
)
8539 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8540 | ((imm
& 0x01000000) >> 21);
8543 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8546 neon_qfloat_bits (unsigned imm
)
8548 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8551 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8552 the instruction. *OP is passed as the initial value of the op field, and
8553 may be set to a different value depending on the constant (i.e.
8554 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8555 MVN). If the immediate looks like a repeated pattern then also
8556 try smaller element sizes. */
8559 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8560 unsigned *immbits
, int *op
, int size
,
8561 enum neon_el_type type
)
8563 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8565 if (type
== NT_float
&& !float_p
)
8568 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8570 if (size
!= 32 || *op
== 1)
8572 *immbits
= neon_qfloat_bits (immlo
);
8578 if (neon_bits_same_in_bytes (immhi
)
8579 && neon_bits_same_in_bytes (immlo
))
8583 *immbits
= (neon_squash_bits (immhi
) << 4)
8584 | neon_squash_bits (immlo
);
8595 if (immlo
== (immlo
& 0x000000ff))
8600 else if (immlo
== (immlo
& 0x0000ff00))
8602 *immbits
= immlo
>> 8;
8605 else if (immlo
== (immlo
& 0x00ff0000))
8607 *immbits
= immlo
>> 16;
8610 else if (immlo
== (immlo
& 0xff000000))
8612 *immbits
= immlo
>> 24;
8615 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8617 *immbits
= (immlo
>> 8) & 0xff;
8620 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8622 *immbits
= (immlo
>> 16) & 0xff;
8626 if ((immlo
& 0xffff) != (immlo
>> 16))
8633 if (immlo
== (immlo
& 0x000000ff))
8638 else if (immlo
== (immlo
& 0x0000ff00))
8640 *immbits
= immlo
>> 8;
8644 if ((immlo
& 0xff) != (immlo
>> 8))
8649 if (immlo
== (immlo
& 0x000000ff))
8651 /* Don't allow MVN with 8-bit immediate. */
8661 #if defined BFD_HOST_64_BIT
8662 /* Returns TRUE if double precision value V may be cast
8663 to single precision without loss of accuracy. */
8666 is_double_a_single (bfd_int64_t v
)
8668 int exp
= (int)((v
>> 52) & 0x7FF);
8669 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8671 return (exp
== 0 || exp
== 0x7FF
8672 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8673 && (mantissa
& 0x1FFFFFFFl
) == 0;
8676 /* Returns a double precision value casted to single precision
8677 (ignoring the least significant bits in exponent and mantissa). */
8680 double_to_single (bfd_int64_t v
)
8682 int sign
= (int) ((v
>> 63) & 1l);
8683 int exp
= (int) ((v
>> 52) & 0x7FF);
8684 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8690 exp
= exp
- 1023 + 127;
8699 /* No denormalized numbers. */
8705 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8707 #endif /* BFD_HOST_64_BIT */
8716 static void do_vfp_nsyn_opcode (const char *);
8718 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8719 Determine whether it can be performed with a move instruction; if
8720 it can, convert inst.instruction to that move instruction and
8721 return TRUE; if it can't, convert inst.instruction to a literal-pool
8722 load and return FALSE. If this is not a valid thing to do in the
8723 current context, set inst.error and return TRUE.
8725 inst.operands[i] describes the destination register. */
8728 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8731 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8732 bfd_boolean arm_p
= (t
== CONST_ARM
);
8735 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8739 if ((inst
.instruction
& tbit
) == 0)
8741 inst
.error
= _("invalid pseudo operation");
8745 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8746 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8747 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8749 inst
.error
= _("constant expression expected");
8753 if (inst
.relocs
[0].exp
.X_op
== O_constant
8754 || inst
.relocs
[0].exp
.X_op
== O_big
)
8756 #if defined BFD_HOST_64_BIT
8761 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8763 LITTLENUM_TYPE w
[X_PRECISION
];
8766 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8768 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8770 /* FIXME: Should we check words w[2..5] ? */
8775 #if defined BFD_HOST_64_BIT
8777 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8778 << LITTLENUM_NUMBER_OF_BITS
)
8779 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8780 << LITTLENUM_NUMBER_OF_BITS
)
8781 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8782 << LITTLENUM_NUMBER_OF_BITS
)
8783 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8785 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8786 | (l
[0] & LITTLENUM_MASK
);
8790 v
= inst
.relocs
[0].exp
.X_add_number
;
8792 if (!inst
.operands
[i
].issingle
)
8796 /* LDR should not use lead in a flag-setting instruction being
8797 chosen so we do not check whether movs can be used. */
8799 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8800 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8801 && inst
.operands
[i
].reg
!= 13
8802 && inst
.operands
[i
].reg
!= 15)
8804 /* Check if on thumb2 it can be done with a mov.w, mvn or
8805 movw instruction. */
8806 unsigned int newimm
;
8807 bfd_boolean isNegated
;
8809 newimm
= encode_thumb32_immediate (v
);
8810 if (newimm
!= (unsigned int) FAIL
)
8814 newimm
= encode_thumb32_immediate (~v
);
8815 if (newimm
!= (unsigned int) FAIL
)
8819 /* The number can be loaded with a mov.w or mvn
8821 if (newimm
!= (unsigned int) FAIL
8822 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8824 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8825 | (inst
.operands
[i
].reg
<< 8));
8826 /* Change to MOVN. */
8827 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8828 inst
.instruction
|= (newimm
& 0x800) << 15;
8829 inst
.instruction
|= (newimm
& 0x700) << 4;
8830 inst
.instruction
|= (newimm
& 0x0ff);
8833 /* The number can be loaded with a movw instruction. */
8834 else if ((v
& ~0xFFFF) == 0
8835 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8837 int imm
= v
& 0xFFFF;
8839 inst
.instruction
= 0xf2400000; /* MOVW. */
8840 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8841 inst
.instruction
|= (imm
& 0xf000) << 4;
8842 inst
.instruction
|= (imm
& 0x0800) << 15;
8843 inst
.instruction
|= (imm
& 0x0700) << 4;
8844 inst
.instruction
|= (imm
& 0x00ff);
8845 /* In case this replacement is being done on Armv8-M
8846 Baseline we need to make sure to disable the
8847 instruction size check, as otherwise GAS will reject
8848 the use of this T32 instruction. */
8856 int value
= encode_arm_immediate (v
);
8860 /* This can be done with a mov instruction. */
8861 inst
.instruction
&= LITERAL_MASK
;
8862 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8863 inst
.instruction
|= value
& 0xfff;
8867 value
= encode_arm_immediate (~ v
);
8870 /* This can be done with a mvn instruction. */
8871 inst
.instruction
&= LITERAL_MASK
;
8872 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8873 inst
.instruction
|= value
& 0xfff;
8877 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8880 unsigned immbits
= 0;
8881 unsigned immlo
= inst
.operands
[1].imm
;
8882 unsigned immhi
= inst
.operands
[1].regisimm
8883 ? inst
.operands
[1].reg
8884 : inst
.relocs
[0].exp
.X_unsigned
8886 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8887 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8888 &op
, 64, NT_invtype
);
8892 neon_invert_size (&immlo
, &immhi
, 64);
8894 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8895 &op
, 64, NT_invtype
);
8900 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8906 /* Fill other bits in vmov encoding for both thumb and arm. */
8908 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8910 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8911 neon_write_immbits (immbits
);
8919 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8920 if (inst
.operands
[i
].issingle
8921 && is_quarter_float (inst
.operands
[1].imm
)
8922 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8924 inst
.operands
[1].imm
=
8925 neon_qfloat_bits (v
);
8926 do_vfp_nsyn_opcode ("fconsts");
8930 /* If our host does not support a 64-bit type then we cannot perform
8931 the following optimization. This mean that there will be a
8932 discrepancy between the output produced by an assembler built for
8933 a 32-bit-only host and the output produced from a 64-bit host, but
8934 this cannot be helped. */
8935 #if defined BFD_HOST_64_BIT
8936 else if (!inst
.operands
[1].issingle
8937 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8939 if (is_double_a_single (v
)
8940 && is_quarter_float (double_to_single (v
)))
8942 inst
.operands
[1].imm
=
8943 neon_qfloat_bits (double_to_single (v
));
8944 do_vfp_nsyn_opcode ("fconstd");
8952 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8953 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8956 inst
.operands
[1].reg
= REG_PC
;
8957 inst
.operands
[1].isreg
= 1;
8958 inst
.operands
[1].preind
= 1;
8959 inst
.relocs
[0].pc_rel
= 1;
8960 inst
.relocs
[0].type
= (thumb_p
8961 ? BFD_RELOC_ARM_THUMB_OFFSET
8963 ? BFD_RELOC_ARM_HWLITERAL
8964 : BFD_RELOC_ARM_LITERAL
));
8968 /* inst.operands[i] was set up by parse_address. Encode it into an
8969 ARM-format instruction. Reject all forms which cannot be encoded
8970 into a coprocessor load/store instruction. If wb_ok is false,
8971 reject use of writeback; if unind_ok is false, reject use of
8972 unindexed addressing. If reloc_override is not 0, use it instead
8973 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8974 (in which case it is preserved). */
8977 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8979 if (!inst
.operands
[i
].isreg
)
8982 if (! inst
.operands
[0].isvec
)
8984 inst
.error
= _("invalid co-processor operand");
8987 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8991 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8993 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8995 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8997 gas_assert (!inst
.operands
[i
].writeback
);
9000 inst
.error
= _("instruction does not support unindexed addressing");
9003 inst
.instruction
|= inst
.operands
[i
].imm
;
9004 inst
.instruction
|= INDEX_UP
;
9008 if (inst
.operands
[i
].preind
)
9009 inst
.instruction
|= PRE_INDEX
;
9011 if (inst
.operands
[i
].writeback
)
9013 if (inst
.operands
[i
].reg
== REG_PC
)
9015 inst
.error
= _("pc may not be used with write-back");
9020 inst
.error
= _("instruction does not support writeback");
9023 inst
.instruction
|= WRITE_BACK
;
9027 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9028 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9029 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9030 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9033 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9035 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9038 /* Prefer + for zero encoded value. */
9039 if (!inst
.operands
[i
].negative
)
9040 inst
.instruction
|= INDEX_UP
;
9045 /* Functions for instruction encoding, sorted by sub-architecture.
9046 First some generics; their names are taken from the conventional
9047 bit positions for register arguments in ARM format instructions. */
9057 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9063 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9069 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9070 inst
.instruction
|= inst
.operands
[1].reg
;
9076 inst
.instruction
|= inst
.operands
[0].reg
;
9077 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9083 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9084 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9090 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9091 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9097 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9098 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9102 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9104 if (ARM_CPU_IS_ANY (cpu_variant
))
9106 as_tsktsk ("%s", msg
);
9109 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9121 unsigned Rn
= inst
.operands
[2].reg
;
9122 /* Enforce restrictions on SWP instruction. */
9123 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9125 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9126 _("Rn must not overlap other operands"));
9128 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9130 if (!check_obsolete (&arm_ext_v8
,
9131 _("swp{b} use is obsoleted for ARMv8 and later"))
9132 && warn_on_deprecated
9133 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9134 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9137 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9138 inst
.instruction
|= inst
.operands
[1].reg
;
9139 inst
.instruction
|= Rn
<< 16;
9145 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9146 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9147 inst
.instruction
|= inst
.operands
[2].reg
;
9153 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9154 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9155 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9156 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9158 inst
.instruction
|= inst
.operands
[0].reg
;
9159 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9160 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9166 inst
.instruction
|= inst
.operands
[0].imm
;
9172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9173 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9176 /* ARM instructions, in alphabetical order by function name (except
9177 that wrapper functions appear immediately after the function they
9180 /* This is a pseudo-op of the form "adr rd, label" to be converted
9181 into a relative address of the form "add rd, pc, #label-.-8". */
9186 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9188 /* Frag hacking will turn this into a sub instruction if the offset turns
9189 out to be negative. */
9190 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9191 inst
.relocs
[0].pc_rel
= 1;
9192 inst
.relocs
[0].exp
.X_add_number
-= 8;
9194 if (support_interwork
9195 && inst
.relocs
[0].exp
.X_op
== O_symbol
9196 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9197 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9198 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9199 inst
.relocs
[0].exp
.X_add_number
|= 1;
9202 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9203 into a relative address of the form:
9204 add rd, pc, #low(label-.-8)"
9205 add rd, rd, #high(label-.-8)" */
9210 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9212 /* Frag hacking will turn this into a sub instruction if the offset turns
9213 out to be negative. */
9214 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9215 inst
.relocs
[0].pc_rel
= 1;
9216 inst
.size
= INSN_SIZE
* 2;
9217 inst
.relocs
[0].exp
.X_add_number
-= 8;
9219 if (support_interwork
9220 && inst
.relocs
[0].exp
.X_op
== O_symbol
9221 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9222 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9223 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9224 inst
.relocs
[0].exp
.X_add_number
|= 1;
9230 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9231 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9233 if (!inst
.operands
[1].present
)
9234 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9236 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9237 encode_arm_shifter_operand (2);
9243 if (inst
.operands
[0].present
)
9244 inst
.instruction
|= inst
.operands
[0].imm
;
9246 inst
.instruction
|= 0xf;
9252 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9253 constraint (msb
> 32, _("bit-field extends past end of register"));
9254 /* The instruction encoding stores the LSB and MSB,
9255 not the LSB and width. */
9256 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9257 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9258 inst
.instruction
|= (msb
- 1) << 16;
9266 /* #0 in second position is alternative syntax for bfc, which is
9267 the same instruction but with REG_PC in the Rm field. */
9268 if (!inst
.operands
[1].isreg
)
9269 inst
.operands
[1].reg
= REG_PC
;
9271 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9272 constraint (msb
> 32, _("bit-field extends past end of register"));
9273 /* The instruction encoding stores the LSB and MSB,
9274 not the LSB and width. */
9275 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9276 inst
.instruction
|= inst
.operands
[1].reg
;
9277 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9278 inst
.instruction
|= (msb
- 1) << 16;
9284 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9285 _("bit-field extends past end of register"));
9286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9287 inst
.instruction
|= inst
.operands
[1].reg
;
9288 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9289 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9292 /* ARM V5 breakpoint instruction (argument parse)
9293 BKPT <16 bit unsigned immediate>
9294 Instruction is not conditional.
9295 The bit pattern given in insns[] has the COND_ALWAYS condition,
9296 and it is an error if the caller tried to override that. */
9301 /* Top 12 of 16 bits to bits 19:8. */
9302 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9304 /* Bottom 4 of 16 bits to bits 3:0. */
9305 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9309 encode_branch (int default_reloc
)
9311 if (inst
.operands
[0].hasreloc
)
9313 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9314 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9315 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9316 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9317 ? BFD_RELOC_ARM_PLT32
9318 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9321 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9322 inst
.relocs
[0].pc_rel
= 1;
9329 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9330 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9333 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9340 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9342 if (inst
.cond
== COND_ALWAYS
)
9343 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9345 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9349 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9352 /* ARM V5 branch-link-exchange instruction (argument parse)
9353 BLX <target_addr> ie BLX(1)
9354 BLX{<condition>} <Rm> ie BLX(2)
9355 Unfortunately, there are two different opcodes for this mnemonic.
9356 So, the insns[].value is not used, and the code here zaps values
9357 into inst.instruction.
9358 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9363 if (inst
.operands
[0].isreg
)
9365 /* Arg is a register; the opcode provided by insns[] is correct.
9366 It is not illegal to do "blx pc", just useless. */
9367 if (inst
.operands
[0].reg
== REG_PC
)
9368 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9370 inst
.instruction
|= inst
.operands
[0].reg
;
9374 /* Arg is an address; this instruction cannot be executed
9375 conditionally, and the opcode must be adjusted.
9376 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9377 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9378 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9379 inst
.instruction
= 0xfa000000;
9380 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9387 bfd_boolean want_reloc
;
9389 if (inst
.operands
[0].reg
== REG_PC
)
9390 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9392 inst
.instruction
|= inst
.operands
[0].reg
;
9393 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9394 it is for ARMv4t or earlier. */
9395 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9396 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9397 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9401 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9406 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9410 /* ARM v5TEJ. Jump to Jazelle code. */
9415 if (inst
.operands
[0].reg
== REG_PC
)
9416 as_tsktsk (_("use of r15 in bxj is not really useful"));
9418 inst
.instruction
|= inst
.operands
[0].reg
;
9421 /* Co-processor data operation:
9422 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9423 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9427 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9428 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9429 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9430 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9431 inst
.instruction
|= inst
.operands
[4].reg
;
9432 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9438 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9439 encode_arm_shifter_operand (1);
9442 /* Transfer between coprocessor and ARM registers.
9443 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9448 No special properties. */
9450 struct deprecated_coproc_regs_s
9457 arm_feature_set deprecated
;
9458 arm_feature_set obsoleted
;
9459 const char *dep_msg
;
9460 const char *obs_msg
;
9463 #define DEPR_ACCESS_V8 \
9464 N_("This coprocessor register access is deprecated in ARMv8")
9466 /* Table of all deprecated coprocessor registers. */
9467 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9469 {15, 0, 7, 10, 5, /* CP15DMB. */
9470 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9471 DEPR_ACCESS_V8
, NULL
},
9472 {15, 0, 7, 10, 4, /* CP15DSB. */
9473 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9474 DEPR_ACCESS_V8
, NULL
},
9475 {15, 0, 7, 5, 4, /* CP15ISB. */
9476 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9477 DEPR_ACCESS_V8
, NULL
},
9478 {14, 6, 1, 0, 0, /* TEEHBR. */
9479 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9480 DEPR_ACCESS_V8
, NULL
},
9481 {14, 6, 0, 0, 0, /* TEECR. */
9482 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9483 DEPR_ACCESS_V8
, NULL
},
9486 #undef DEPR_ACCESS_V8
9488 static const size_t deprecated_coproc_reg_count
=
9489 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9497 Rd
= inst
.operands
[2].reg
;
9500 if (inst
.instruction
== 0xee000010
9501 || inst
.instruction
== 0xfe000010)
9503 reject_bad_reg (Rd
);
9504 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9506 constraint (Rd
== REG_SP
, BAD_SP
);
9511 if (inst
.instruction
== 0xe000010)
9512 constraint (Rd
== REG_PC
, BAD_PC
);
9515 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9517 const struct deprecated_coproc_regs_s
*r
=
9518 deprecated_coproc_regs
+ i
;
9520 if (inst
.operands
[0].reg
== r
->cp
9521 && inst
.operands
[1].imm
== r
->opc1
9522 && inst
.operands
[3].reg
== r
->crn
9523 && inst
.operands
[4].reg
== r
->crm
9524 && inst
.operands
[5].imm
== r
->opc2
)
9526 if (! ARM_CPU_IS_ANY (cpu_variant
)
9527 && warn_on_deprecated
9528 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9529 as_tsktsk ("%s", r
->dep_msg
);
9533 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9534 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9535 inst
.instruction
|= Rd
<< 12;
9536 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9537 inst
.instruction
|= inst
.operands
[4].reg
;
9538 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9541 /* Transfer between coprocessor register and pair of ARM registers.
9542 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9547 Two XScale instructions are special cases of these:
9549 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9550 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9552 Result unpredictable if Rd or Rn is R15. */
9559 Rd
= inst
.operands
[2].reg
;
9560 Rn
= inst
.operands
[3].reg
;
9564 reject_bad_reg (Rd
);
9565 reject_bad_reg (Rn
);
9569 constraint (Rd
== REG_PC
, BAD_PC
);
9570 constraint (Rn
== REG_PC
, BAD_PC
);
9573 /* Only check the MRRC{2} variants. */
9574 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9576 /* If Rd == Rn, error that the operation is
9577 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9578 constraint (Rd
== Rn
, BAD_OVERLAP
);
9581 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9582 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9583 inst
.instruction
|= Rd
<< 12;
9584 inst
.instruction
|= Rn
<< 16;
9585 inst
.instruction
|= inst
.operands
[4].reg
;
9591 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9592 if (inst
.operands
[1].present
)
9594 inst
.instruction
|= CPSI_MMOD
;
9595 inst
.instruction
|= inst
.operands
[1].imm
;
9602 inst
.instruction
|= inst
.operands
[0].imm
;
9608 unsigned Rd
, Rn
, Rm
;
9610 Rd
= inst
.operands
[0].reg
;
9611 Rn
= (inst
.operands
[1].present
9612 ? inst
.operands
[1].reg
: Rd
);
9613 Rm
= inst
.operands
[2].reg
;
9615 constraint ((Rd
== REG_PC
), BAD_PC
);
9616 constraint ((Rn
== REG_PC
), BAD_PC
);
9617 constraint ((Rm
== REG_PC
), BAD_PC
);
9619 inst
.instruction
|= Rd
<< 16;
9620 inst
.instruction
|= Rn
<< 0;
9621 inst
.instruction
|= Rm
<< 8;
9627 /* There is no IT instruction in ARM mode. We
9628 process it to do the validation as if in
9629 thumb mode, just in case the code gets
9630 assembled for thumb using the unified syntax. */
9635 set_pred_insn_type (IT_INSN
);
9636 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9637 now_pred
.cc
= inst
.operands
[0].imm
;
9641 /* If there is only one register in the register list,
9642 then return its register number. Otherwise return -1. */
9644 only_one_reg_in_list (int range
)
9646 int i
= ffs (range
) - 1;
9647 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9651 encode_ldmstm(int from_push_pop_mnem
)
9653 int base_reg
= inst
.operands
[0].reg
;
9654 int range
= inst
.operands
[1].imm
;
9657 inst
.instruction
|= base_reg
<< 16;
9658 inst
.instruction
|= range
;
9660 if (inst
.operands
[1].writeback
)
9661 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9663 if (inst
.operands
[0].writeback
)
9665 inst
.instruction
|= WRITE_BACK
;
9666 /* Check for unpredictable uses of writeback. */
9667 if (inst
.instruction
& LOAD_BIT
)
9669 /* Not allowed in LDM type 2. */
9670 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9671 && ((range
& (1 << REG_PC
)) == 0))
9672 as_warn (_("writeback of base register is UNPREDICTABLE"));
9673 /* Only allowed if base reg not in list for other types. */
9674 else if (range
& (1 << base_reg
))
9675 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9679 /* Not allowed for type 2. */
9680 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9681 as_warn (_("writeback of base register is UNPREDICTABLE"));
9682 /* Only allowed if base reg not in list, or first in list. */
9683 else if ((range
& (1 << base_reg
))
9684 && (range
& ((1 << base_reg
) - 1)))
9685 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9689 /* If PUSH/POP has only one register, then use the A2 encoding. */
9690 one_reg
= only_one_reg_in_list (range
);
9691 if (from_push_pop_mnem
&& one_reg
>= 0)
9693 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9695 if (is_push
&& one_reg
== 13 /* SP */)
9696 /* PR 22483: The A2 encoding cannot be used when
9697 pushing the stack pointer as this is UNPREDICTABLE. */
9700 inst
.instruction
&= A_COND_MASK
;
9701 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9702 inst
.instruction
|= one_reg
<< 12;
9709 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9712 /* ARMv5TE load-consecutive (argument parse)
9721 constraint (inst
.operands
[0].reg
% 2 != 0,
9722 _("first transfer register must be even"));
9723 constraint (inst
.operands
[1].present
9724 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9725 _("can only transfer two consecutive registers"));
9726 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9727 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9729 if (!inst
.operands
[1].present
)
9730 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9732 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9733 register and the first register written; we have to diagnose
9734 overlap between the base and the second register written here. */
9736 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9737 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9738 as_warn (_("base register written back, and overlaps "
9739 "second transfer register"));
9741 if (!(inst
.instruction
& V4_STR_BIT
))
9743 /* For an index-register load, the index register must not overlap the
9744 destination (even if not write-back). */
9745 if (inst
.operands
[2].immisreg
9746 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9747 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9748 as_warn (_("index register overlaps transfer register"));
9750 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9751 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9757 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9758 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9759 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9760 || inst
.operands
[1].negative
9761 /* This can arise if the programmer has written
9763 or if they have mistakenly used a register name as the last
9766 It is very difficult to distinguish between these two cases
9767 because "rX" might actually be a label. ie the register
9768 name has been occluded by a symbol of the same name. So we
9769 just generate a general 'bad addressing mode' type error
9770 message and leave it up to the programmer to discover the
9771 true cause and fix their mistake. */
9772 || (inst
.operands
[1].reg
== REG_PC
),
9775 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9776 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9777 _("offset must be zero in ARM encoding"));
9779 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9781 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9782 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9783 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9789 constraint (inst
.operands
[0].reg
% 2 != 0,
9790 _("even register required"));
9791 constraint (inst
.operands
[1].present
9792 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9793 _("can only load two consecutive registers"));
9794 /* If op 1 were present and equal to PC, this function wouldn't
9795 have been called in the first place. */
9796 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9798 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9799 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9802 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9803 which is not a multiple of four is UNPREDICTABLE. */
9805 check_ldr_r15_aligned (void)
9807 constraint (!(inst
.operands
[1].immisreg
)
9808 && (inst
.operands
[0].reg
== REG_PC
9809 && inst
.operands
[1].reg
== REG_PC
9810 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9811 _("ldr to register 15 must be 4-byte aligned"));
9817 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9818 if (!inst
.operands
[1].isreg
)
9819 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9821 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9822 check_ldr_r15_aligned ();
9828 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9830 if (inst
.operands
[1].preind
)
9832 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9833 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9834 _("this instruction requires a post-indexed address"));
9836 inst
.operands
[1].preind
= 0;
9837 inst
.operands
[1].postind
= 1;
9838 inst
.operands
[1].writeback
= 1;
9840 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9841 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9844 /* Halfword and signed-byte load/store operations. */
9849 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9850 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9851 if (!inst
.operands
[1].isreg
)
9852 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9854 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9860 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9862 if (inst
.operands
[1].preind
)
9864 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9865 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9866 _("this instruction requires a post-indexed address"));
9868 inst
.operands
[1].preind
= 0;
9869 inst
.operands
[1].postind
= 1;
9870 inst
.operands
[1].writeback
= 1;
9872 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9873 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9876 /* Co-processor register load/store.
9877 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9881 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9882 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9883 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9889 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9890 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9891 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9892 && !(inst
.instruction
& 0x00400000))
9893 as_tsktsk (_("Rd and Rm should be different in mla"));
9895 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9896 inst
.instruction
|= inst
.operands
[1].reg
;
9897 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9898 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9904 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9905 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9907 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9908 encode_arm_shifter_operand (1);
9911 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9918 top
= (inst
.instruction
& 0x00400000) != 0;
9919 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9920 _(":lower16: not allowed in this instruction"));
9921 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9922 _(":upper16: not allowed in this instruction"));
9923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9924 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9926 imm
= inst
.relocs
[0].exp
.X_add_number
;
9927 /* The value is in two pieces: 0:11, 16:19. */
9928 inst
.instruction
|= (imm
& 0x00000fff);
9929 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9934 do_vfp_nsyn_mrs (void)
9936 if (inst
.operands
[0].isvec
)
9938 if (inst
.operands
[1].reg
!= 1)
9939 first_error (_("operand 1 must be FPSCR"));
9940 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9941 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9942 do_vfp_nsyn_opcode ("fmstat");
9944 else if (inst
.operands
[1].isvec
)
9945 do_vfp_nsyn_opcode ("fmrx");
9953 do_vfp_nsyn_msr (void)
9955 if (inst
.operands
[0].isvec
)
9956 do_vfp_nsyn_opcode ("fmxr");
9966 unsigned Rt
= inst
.operands
[0].reg
;
9968 if (thumb_mode
&& Rt
== REG_SP
)
9970 inst
.error
= BAD_SP
;
9974 switch (inst
.operands
[1].reg
)
9976 /* MVFR2 is only valid for Armv8-A. */
9978 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9982 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9983 case 1: /* fpscr. */
9984 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9985 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9989 case 14: /* fpcxt_ns. */
9990 case 15: /* fpcxt_s. */
9991 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
9992 _("selected processor does not support instruction"));
9995 case 2: /* fpscr_nzcvqc. */
9998 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
9999 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10000 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10001 _("selected processor does not support instruction"));
10002 if (inst
.operands
[0].reg
!= 2
10003 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10004 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10011 /* APSR_ sets isvec. All other refs to PC are illegal. */
10012 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10014 inst
.error
= BAD_PC
;
10018 /* If we get through parsing the register name, we just insert the number
10019 generated into the instruction without further validation. */
10020 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10021 inst
.instruction
|= (Rt
<< 12);
10027 unsigned Rt
= inst
.operands
[1].reg
;
10030 reject_bad_reg (Rt
);
10031 else if (Rt
== REG_PC
)
10033 inst
.error
= BAD_PC
;
10037 switch (inst
.operands
[0].reg
)
10039 /* MVFR2 is only valid for Armv8-A. */
10041 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10045 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10046 case 1: /* fpcr. */
10047 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10048 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10052 case 14: /* fpcxt_ns. */
10053 case 15: /* fpcxt_s. */
10054 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10055 _("selected processor does not support instruction"));
10058 case 2: /* fpscr_nzcvqc. */
10059 case 12: /* vpr. */
10061 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10062 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10063 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10064 _("selected processor does not support instruction"));
10065 if (inst
.operands
[0].reg
!= 2
10066 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10067 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10074 /* If we get through parsing the register name, we just insert the number
10075 generated into the instruction without further validation. */
10076 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10077 inst
.instruction
|= (Rt
<< 12);
10085 if (do_vfp_nsyn_mrs () == SUCCESS
)
10088 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10091 if (inst
.operands
[1].isreg
)
10093 br
= inst
.operands
[1].reg
;
10094 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10095 as_bad (_("bad register for mrs"));
10099 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10100 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10102 _("'APSR', 'CPSR' or 'SPSR' expected"));
10103 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10106 inst
.instruction
|= br
;
10109 /* Two possible forms:
10110 "{C|S}PSR_<field>, Rm",
10111 "{C|S}PSR_f, #expression". */
10116 if (do_vfp_nsyn_msr () == SUCCESS
)
10119 inst
.instruction
|= inst
.operands
[0].imm
;
10120 if (inst
.operands
[1].isreg
)
10121 inst
.instruction
|= inst
.operands
[1].reg
;
10124 inst
.instruction
|= INST_IMMEDIATE
;
10125 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10126 inst
.relocs
[0].pc_rel
= 0;
10133 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10135 if (!inst
.operands
[2].present
)
10136 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10137 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10138 inst
.instruction
|= inst
.operands
[1].reg
;
10139 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10141 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10142 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10143 as_tsktsk (_("Rd and Rm should be different in mul"));
10146 /* Long Multiply Parser
10147 UMULL RdLo, RdHi, Rm, Rs
10148 SMULL RdLo, RdHi, Rm, Rs
10149 UMLAL RdLo, RdHi, Rm, Rs
10150 SMLAL RdLo, RdHi, Rm, Rs. */
10155 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10156 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10157 inst
.instruction
|= inst
.operands
[2].reg
;
10158 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10160 /* rdhi and rdlo must be different. */
10161 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10162 as_tsktsk (_("rdhi and rdlo must be different"));
10164 /* rdhi, rdlo and rm must all be different before armv6. */
10165 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10166 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10167 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10168 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10174 if (inst
.operands
[0].present
10175 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10177 /* Architectural NOP hints are CPSR sets with no bits selected. */
10178 inst
.instruction
&= 0xf0000000;
10179 inst
.instruction
|= 0x0320f000;
10180 if (inst
.operands
[0].present
)
10181 inst
.instruction
|= inst
.operands
[0].imm
;
10185 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10186 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10187 Condition defaults to COND_ALWAYS.
10188 Error if Rd, Rn or Rm are R15. */
10193 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10194 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10195 inst
.instruction
|= inst
.operands
[2].reg
;
10196 if (inst
.operands
[3].present
)
10197 encode_arm_shift (3);
10200 /* ARM V6 PKHTB (Argument Parse). */
10205 if (!inst
.operands
[3].present
)
10207 /* If the shift specifier is omitted, turn the instruction
10208 into pkhbt rd, rm, rn. */
10209 inst
.instruction
&= 0xfff00010;
10210 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10211 inst
.instruction
|= inst
.operands
[1].reg
;
10212 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10216 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10217 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10218 inst
.instruction
|= inst
.operands
[2].reg
;
10219 encode_arm_shift (3);
10223 /* ARMv5TE: Preload-Cache
10224 MP Extensions: Preload for write
10228 Syntactically, like LDR with B=1, W=0, L=1. */
10233 constraint (!inst
.operands
[0].isreg
,
10234 _("'[' expected after PLD mnemonic"));
10235 constraint (inst
.operands
[0].postind
,
10236 _("post-indexed expression used in preload instruction"));
10237 constraint (inst
.operands
[0].writeback
,
10238 _("writeback used in preload instruction"));
10239 constraint (!inst
.operands
[0].preind
,
10240 _("unindexed addressing used in preload instruction"));
10241 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10244 /* ARMv7: PLI <addr_mode> */
10248 constraint (!inst
.operands
[0].isreg
,
10249 _("'[' expected after PLI mnemonic"));
10250 constraint (inst
.operands
[0].postind
,
10251 _("post-indexed expression used in preload instruction"));
10252 constraint (inst
.operands
[0].writeback
,
10253 _("writeback used in preload instruction"));
10254 constraint (!inst
.operands
[0].preind
,
10255 _("unindexed addressing used in preload instruction"));
10256 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10257 inst
.instruction
&= ~PRE_INDEX
;
10263 constraint (inst
.operands
[0].writeback
,
10264 _("push/pop do not support {reglist}^"));
10265 inst
.operands
[1] = inst
.operands
[0];
10266 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10267 inst
.operands
[0].isreg
= 1;
10268 inst
.operands
[0].writeback
= 1;
10269 inst
.operands
[0].reg
= REG_SP
;
10270 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10273 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10274 word at the specified address and the following word
10276 Unconditionally executed.
10277 Error if Rn is R15. */
10282 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10283 if (inst
.operands
[0].writeback
)
10284 inst
.instruction
|= WRITE_BACK
;
10287 /* ARM V6 ssat (argument parse). */
10292 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10293 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10294 inst
.instruction
|= inst
.operands
[2].reg
;
10296 if (inst
.operands
[3].present
)
10297 encode_arm_shift (3);
10300 /* ARM V6 usat (argument parse). */
10305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10306 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10307 inst
.instruction
|= inst
.operands
[2].reg
;
10309 if (inst
.operands
[3].present
)
10310 encode_arm_shift (3);
10313 /* ARM V6 ssat16 (argument parse). */
10318 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10319 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10320 inst
.instruction
|= inst
.operands
[2].reg
;
10326 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10327 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10328 inst
.instruction
|= inst
.operands
[2].reg
;
10331 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10332 preserving the other bits.
10334 setend <endian_specifier>, where <endian_specifier> is either
10340 if (warn_on_deprecated
10341 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10342 as_tsktsk (_("setend use is deprecated for ARMv8"));
10344 if (inst
.operands
[0].imm
)
10345 inst
.instruction
|= 0x200;
10351 unsigned int Rm
= (inst
.operands
[1].present
10352 ? inst
.operands
[1].reg
10353 : inst
.operands
[0].reg
);
10355 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10356 inst
.instruction
|= Rm
;
10357 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10359 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10360 inst
.instruction
|= SHIFT_BY_REG
;
10361 /* PR 12854: Error on extraneous shifts. */
10362 constraint (inst
.operands
[2].shifted
,
10363 _("extraneous shift as part of operand to shift insn"));
10366 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10372 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10373 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10375 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10376 inst
.relocs
[0].pc_rel
= 0;
10382 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10383 inst
.relocs
[0].pc_rel
= 0;
10389 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10390 inst
.relocs
[0].pc_rel
= 0;
10396 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10397 _("selected processor does not support SETPAN instruction"));
10399 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10405 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10406 _("selected processor does not support SETPAN instruction"));
10408 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10411 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10412 SMLAxy{cond} Rd,Rm,Rs,Rn
10413 SMLAWy{cond} Rd,Rm,Rs,Rn
10414 Error if any register is R15. */
10419 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10420 inst
.instruction
|= inst
.operands
[1].reg
;
10421 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10422 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10425 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10426 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10427 Error if any register is R15.
10428 Warning if Rdlo == Rdhi. */
10433 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10434 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10435 inst
.instruction
|= inst
.operands
[2].reg
;
10436 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10438 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10439 as_tsktsk (_("rdhi and rdlo must be different"));
10442 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10443 SMULxy{cond} Rd,Rm,Rs
10444 Error if any register is R15. */
10449 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10450 inst
.instruction
|= inst
.operands
[1].reg
;
10451 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10454 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10455 the same for both ARM and Thumb-2. */
10462 if (inst
.operands
[0].present
)
10464 reg
= inst
.operands
[0].reg
;
10465 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10470 inst
.instruction
|= reg
<< 16;
10471 inst
.instruction
|= inst
.operands
[1].imm
;
10472 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10473 inst
.instruction
|= WRITE_BACK
;
10476 /* ARM V6 strex (argument parse). */
10481 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10482 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10483 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10484 || inst
.operands
[2].negative
10485 /* See comment in do_ldrex(). */
10486 || (inst
.operands
[2].reg
== REG_PC
),
10489 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10490 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10492 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10493 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10494 _("offset must be zero in ARM encoding"));
10496 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10497 inst
.instruction
|= inst
.operands
[1].reg
;
10498 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10499 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10503 do_t_strexbh (void)
10505 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10506 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10507 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10508 || inst
.operands
[2].negative
,
10511 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10512 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10520 constraint (inst
.operands
[1].reg
% 2 != 0,
10521 _("even register required"));
10522 constraint (inst
.operands
[2].present
10523 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10524 _("can only store two consecutive registers"));
10525 /* If op 2 were present and equal to PC, this function wouldn't
10526 have been called in the first place. */
10527 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10529 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10530 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10531 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10534 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10535 inst
.instruction
|= inst
.operands
[1].reg
;
10536 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10543 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10544 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10552 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10553 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10558 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10559 extends it to 32-bits, and adds the result to a value in another
10560 register. You can specify a rotation by 0, 8, 16, or 24 bits
10561 before extracting the 16-bit value.
10562 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10563 Condition defaults to COND_ALWAYS.
10564 Error if any register uses R15. */
10569 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10570 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10571 inst
.instruction
|= inst
.operands
[2].reg
;
10572 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10577 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10578 Condition defaults to COND_ALWAYS.
10579 Error if any register uses R15. */
10584 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10585 inst
.instruction
|= inst
.operands
[1].reg
;
10586 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10589 /* VFP instructions. In a logical order: SP variant first, monad
10590 before dyad, arithmetic then move then load/store. */
10593 do_vfp_sp_monadic (void)
10595 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10596 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10599 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10600 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10604 do_vfp_sp_dyadic (void)
10606 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10607 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10608 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10612 do_vfp_sp_compare_z (void)
10614 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10618 do_vfp_dp_sp_cvt (void)
10620 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10621 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10625 do_vfp_sp_dp_cvt (void)
10627 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10628 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10632 do_vfp_reg_from_sp (void)
10634 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10635 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10638 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10639 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10643 do_vfp_reg2_from_sp2 (void)
10645 constraint (inst
.operands
[2].imm
!= 2,
10646 _("only two consecutive VFP SP registers allowed here"));
10647 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10648 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10649 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10653 do_vfp_sp_from_reg (void)
10655 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10656 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10659 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10660 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10664 do_vfp_sp2_from_reg2 (void)
10666 constraint (inst
.operands
[0].imm
!= 2,
10667 _("only two consecutive VFP SP registers allowed here"));
10668 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10669 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10670 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10674 do_vfp_sp_ldst (void)
10676 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10677 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10681 do_vfp_dp_ldst (void)
10683 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10684 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10689 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10691 if (inst
.operands
[0].writeback
)
10692 inst
.instruction
|= WRITE_BACK
;
10694 constraint (ldstm_type
!= VFP_LDSTMIA
,
10695 _("this addressing mode requires base-register writeback"));
10696 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10697 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10698 inst
.instruction
|= inst
.operands
[1].imm
;
10702 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10706 if (inst
.operands
[0].writeback
)
10707 inst
.instruction
|= WRITE_BACK
;
10709 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10710 _("this addressing mode requires base-register writeback"));
10712 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10713 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10715 count
= inst
.operands
[1].imm
<< 1;
10716 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10719 inst
.instruction
|= count
;
10723 do_vfp_sp_ldstmia (void)
10725 vfp_sp_ldstm (VFP_LDSTMIA
);
10729 do_vfp_sp_ldstmdb (void)
10731 vfp_sp_ldstm (VFP_LDSTMDB
);
10735 do_vfp_dp_ldstmia (void)
10737 vfp_dp_ldstm (VFP_LDSTMIA
);
10741 do_vfp_dp_ldstmdb (void)
10743 vfp_dp_ldstm (VFP_LDSTMDB
);
10747 do_vfp_xp_ldstmia (void)
10749 vfp_dp_ldstm (VFP_LDSTMIAX
);
10753 do_vfp_xp_ldstmdb (void)
10755 vfp_dp_ldstm (VFP_LDSTMDBX
);
10759 do_vfp_dp_rd_rm (void)
10761 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10762 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10765 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10766 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10770 do_vfp_dp_rn_rd (void)
10772 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10773 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10777 do_vfp_dp_rd_rn (void)
10779 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10780 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10784 do_vfp_dp_rd_rn_rm (void)
10786 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10787 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10790 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10791 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10792 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10796 do_vfp_dp_rd (void)
10798 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10802 do_vfp_dp_rm_rd_rn (void)
10804 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10805 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10808 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10809 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10810 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10813 /* VFPv3 instructions. */
10815 do_vfp_sp_const (void)
10817 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10818 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10819 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10823 do_vfp_dp_const (void)
10825 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10826 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10827 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10831 vfp_conv (int srcsize
)
10833 int immbits
= srcsize
- inst
.operands
[1].imm
;
10835 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10837 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10838 i.e. immbits must be in range 0 - 16. */
10839 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10842 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10844 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10845 i.e. immbits must be in range 0 - 31. */
10846 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10850 inst
.instruction
|= (immbits
& 1) << 5;
10851 inst
.instruction
|= (immbits
>> 1);
10855 do_vfp_sp_conv_16 (void)
10857 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10862 do_vfp_dp_conv_16 (void)
10864 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10869 do_vfp_sp_conv_32 (void)
10871 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10876 do_vfp_dp_conv_32 (void)
10878 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10882 /* FPA instructions. Also in a logical order. */
10887 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10888 inst
.instruction
|= inst
.operands
[1].reg
;
10892 do_fpa_ldmstm (void)
10894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10895 switch (inst
.operands
[1].imm
)
10897 case 1: inst
.instruction
|= CP_T_X
; break;
10898 case 2: inst
.instruction
|= CP_T_Y
; break;
10899 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10904 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10906 /* The instruction specified "ea" or "fd", so we can only accept
10907 [Rn]{!}. The instruction does not really support stacking or
10908 unstacking, so we have to emulate these by setting appropriate
10909 bits and offsets. */
10910 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10911 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10912 _("this instruction does not support indexing"));
10914 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10915 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10917 if (!(inst
.instruction
& INDEX_UP
))
10918 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10920 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10922 inst
.operands
[2].preind
= 0;
10923 inst
.operands
[2].postind
= 1;
10927 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10930 /* iWMMXt instructions: strictly in alphabetical order. */
10933 do_iwmmxt_tandorc (void)
10935 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10939 do_iwmmxt_textrc (void)
10941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10942 inst
.instruction
|= inst
.operands
[1].imm
;
10946 do_iwmmxt_textrm (void)
10948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10949 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10950 inst
.instruction
|= inst
.operands
[2].imm
;
10954 do_iwmmxt_tinsr (void)
10956 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10957 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10958 inst
.instruction
|= inst
.operands
[2].imm
;
10962 do_iwmmxt_tmia (void)
10964 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10965 inst
.instruction
|= inst
.operands
[1].reg
;
10966 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10970 do_iwmmxt_waligni (void)
10972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10973 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10974 inst
.instruction
|= inst
.operands
[2].reg
;
10975 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10979 do_iwmmxt_wmerge (void)
10981 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10982 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10983 inst
.instruction
|= inst
.operands
[2].reg
;
10984 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10988 do_iwmmxt_wmov (void)
10990 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10991 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10992 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10993 inst
.instruction
|= inst
.operands
[1].reg
;
10997 do_iwmmxt_wldstbh (void)
11000 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11002 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11004 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11005 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
11009 do_iwmmxt_wldstw (void)
11011 /* RIWR_RIWC clears .isreg for a control register. */
11012 if (!inst
.operands
[0].isreg
)
11014 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11015 inst
.instruction
|= 0xf0000000;
11018 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11019 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
11023 do_iwmmxt_wldstd (void)
11025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11026 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11027 && inst
.operands
[1].immisreg
)
11029 inst
.instruction
&= ~0x1a000ff;
11030 inst
.instruction
|= (0xfU
<< 28);
11031 if (inst
.operands
[1].preind
)
11032 inst
.instruction
|= PRE_INDEX
;
11033 if (!inst
.operands
[1].negative
)
11034 inst
.instruction
|= INDEX_UP
;
11035 if (inst
.operands
[1].writeback
)
11036 inst
.instruction
|= WRITE_BACK
;
11037 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11038 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11039 inst
.instruction
|= inst
.operands
[1].imm
;
11042 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11046 do_iwmmxt_wshufh (void)
11048 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11049 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11050 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11051 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11055 do_iwmmxt_wzero (void)
11057 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11058 inst
.instruction
|= inst
.operands
[0].reg
;
11059 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11060 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11064 do_iwmmxt_wrwrwr_or_imm5 (void)
11066 if (inst
.operands
[2].isreg
)
11069 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11070 _("immediate operand requires iWMMXt2"));
11072 if (inst
.operands
[2].imm
== 0)
11074 switch ((inst
.instruction
>> 20) & 0xf)
11080 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11081 inst
.operands
[2].imm
= 16;
11082 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11088 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11089 inst
.operands
[2].imm
= 32;
11090 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11097 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11099 wrn
= (inst
.instruction
>> 16) & 0xf;
11100 inst
.instruction
&= 0xff0fff0f;
11101 inst
.instruction
|= wrn
;
11102 /* Bail out here; the instruction is now assembled. */
11107 /* Map 32 -> 0, etc. */
11108 inst
.operands
[2].imm
&= 0x1f;
11109 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11113 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11114 operations first, then control, shift, and load/store. */
11116 /* Insns like "foo X,Y,Z". */
11119 do_mav_triple (void)
11121 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11122 inst
.instruction
|= inst
.operands
[1].reg
;
11123 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11126 /* Insns like "foo W,X,Y,Z".
11127 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11132 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11133 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11134 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11135 inst
.instruction
|= inst
.operands
[3].reg
;
11138 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11140 do_mav_dspsc (void)
11142 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11145 /* Maverick shift immediate instructions.
11146 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11147 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11150 do_mav_shift (void)
11152 int imm
= inst
.operands
[2].imm
;
11154 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11155 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11157 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11158 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11159 Bit 4 should be 0. */
11160 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11162 inst
.instruction
|= imm
;
11165 /* XScale instructions. Also sorted arithmetic before move. */
11167 /* Xscale multiply-accumulate (argument parse)
11170 MIAxycc acc0,Rm,Rs. */
11175 inst
.instruction
|= inst
.operands
[1].reg
;
11176 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11179 /* Xscale move-accumulator-register (argument parse)
11181 MARcc acc0,RdLo,RdHi. */
11186 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11187 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11190 /* Xscale move-register-accumulator (argument parse)
11192 MRAcc RdLo,RdHi,acc0. */
11197 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11198 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11199 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11202 /* Encoding functions relevant only to Thumb. */
11204 /* inst.operands[i] is a shifted-register operand; encode
11205 it into inst.instruction in the format used by Thumb32. */
11208 encode_thumb32_shifted_operand (int i
)
11210 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11211 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11213 constraint (inst
.operands
[i
].immisreg
,
11214 _("shift by register not allowed in thumb mode"));
11215 inst
.instruction
|= inst
.operands
[i
].reg
;
11216 if (shift
== SHIFT_RRX
)
11217 inst
.instruction
|= SHIFT_ROR
<< 4;
11220 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11221 _("expression too complex"));
11223 constraint (value
> 32
11224 || (value
== 32 && (shift
== SHIFT_LSL
11225 || shift
== SHIFT_ROR
)),
11226 _("shift expression is too large"));
11230 else if (value
== 32)
11233 inst
.instruction
|= shift
<< 4;
11234 inst
.instruction
|= (value
& 0x1c) << 10;
11235 inst
.instruction
|= (value
& 0x03) << 6;
11240 /* inst.operands[i] was set up by parse_address. Encode it into a
11241 Thumb32 format load or store instruction. Reject forms that cannot
11242 be used with such instructions. If is_t is true, reject forms that
11243 cannot be used with a T instruction; if is_d is true, reject forms
11244 that cannot be used with a D instruction. If it is a store insn,
11245 reject PC in Rn. */
11248 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11250 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11252 constraint (!inst
.operands
[i
].isreg
,
11253 _("Instruction does not support =N addresses"));
11255 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11256 if (inst
.operands
[i
].immisreg
)
11258 constraint (is_pc
, BAD_PC_ADDRESSING
);
11259 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11260 constraint (inst
.operands
[i
].negative
,
11261 _("Thumb does not support negative register indexing"));
11262 constraint (inst
.operands
[i
].postind
,
11263 _("Thumb does not support register post-indexing"));
11264 constraint (inst
.operands
[i
].writeback
,
11265 _("Thumb does not support register indexing with writeback"));
11266 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11267 _("Thumb supports only LSL in shifted register indexing"));
11269 inst
.instruction
|= inst
.operands
[i
].imm
;
11270 if (inst
.operands
[i
].shifted
)
11272 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11273 _("expression too complex"));
11274 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11275 || inst
.relocs
[0].exp
.X_add_number
> 3,
11276 _("shift out of range"));
11277 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11279 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11281 else if (inst
.operands
[i
].preind
)
11283 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11284 constraint (is_t
&& inst
.operands
[i
].writeback
,
11285 _("cannot use writeback with this instruction"));
11286 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11287 BAD_PC_ADDRESSING
);
11291 inst
.instruction
|= 0x01000000;
11292 if (inst
.operands
[i
].writeback
)
11293 inst
.instruction
|= 0x00200000;
11297 inst
.instruction
|= 0x00000c00;
11298 if (inst
.operands
[i
].writeback
)
11299 inst
.instruction
|= 0x00000100;
11301 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11303 else if (inst
.operands
[i
].postind
)
11305 gas_assert (inst
.operands
[i
].writeback
);
11306 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11307 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11310 inst
.instruction
|= 0x00200000;
11312 inst
.instruction
|= 0x00000900;
11313 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11315 else /* unindexed - only for coprocessor */
11316 inst
.error
= _("instruction does not accept unindexed addressing");
11319 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11320 encodings (the latter only in post-V6T2 cores). The index is the
11321 value used in the insns table below. When there is more than one
11322 possible 16-bit encoding for the instruction, this table always
11324 Also contains several pseudo-instructions used during relaxation. */
11325 #define T16_32_TAB \
11326 X(_adc, 4140, eb400000), \
11327 X(_adcs, 4140, eb500000), \
11328 X(_add, 1c00, eb000000), \
11329 X(_adds, 1c00, eb100000), \
11330 X(_addi, 0000, f1000000), \
11331 X(_addis, 0000, f1100000), \
11332 X(_add_pc,000f, f20f0000), \
11333 X(_add_sp,000d, f10d0000), \
11334 X(_adr, 000f, f20f0000), \
11335 X(_and, 4000, ea000000), \
11336 X(_ands, 4000, ea100000), \
11337 X(_asr, 1000, fa40f000), \
11338 X(_asrs, 1000, fa50f000), \
11339 X(_b, e000, f000b000), \
11340 X(_bcond, d000, f0008000), \
11341 X(_bf, 0000, f040e001), \
11342 X(_bfcsel,0000, f000e001), \
11343 X(_bfx, 0000, f060e001), \
11344 X(_bfl, 0000, f000c001), \
11345 X(_bflx, 0000, f070e001), \
11346 X(_bic, 4380, ea200000), \
11347 X(_bics, 4380, ea300000), \
11348 X(_cinc, 0000, ea509000), \
11349 X(_cinv, 0000, ea50a000), \
11350 X(_cmn, 42c0, eb100f00), \
11351 X(_cmp, 2800, ebb00f00), \
11352 X(_cneg, 0000, ea50b000), \
11353 X(_cpsie, b660, f3af8400), \
11354 X(_cpsid, b670, f3af8600), \
11355 X(_cpy, 4600, ea4f0000), \
11356 X(_csel, 0000, ea508000), \
11357 X(_cset, 0000, ea5f900f), \
11358 X(_csetm, 0000, ea5fa00f), \
11359 X(_csinc, 0000, ea509000), \
11360 X(_csinv, 0000, ea50a000), \
11361 X(_csneg, 0000, ea50b000), \
11362 X(_dec_sp,80dd, f1ad0d00), \
11363 X(_dls, 0000, f040e001), \
11364 X(_dlstp, 0000, f000e001), \
11365 X(_eor, 4040, ea800000), \
11366 X(_eors, 4040, ea900000), \
11367 X(_inc_sp,00dd, f10d0d00), \
11368 X(_lctp, 0000, f00fe001), \
11369 X(_ldmia, c800, e8900000), \
11370 X(_ldr, 6800, f8500000), \
11371 X(_ldrb, 7800, f8100000), \
11372 X(_ldrh, 8800, f8300000), \
11373 X(_ldrsb, 5600, f9100000), \
11374 X(_ldrsh, 5e00, f9300000), \
11375 X(_ldr_pc,4800, f85f0000), \
11376 X(_ldr_pc2,4800, f85f0000), \
11377 X(_ldr_sp,9800, f85d0000), \
11378 X(_le, 0000, f00fc001), \
11379 X(_letp, 0000, f01fc001), \
11380 X(_lsl, 0000, fa00f000), \
11381 X(_lsls, 0000, fa10f000), \
11382 X(_lsr, 0800, fa20f000), \
11383 X(_lsrs, 0800, fa30f000), \
11384 X(_mov, 2000, ea4f0000), \
11385 X(_movs, 2000, ea5f0000), \
11386 X(_mul, 4340, fb00f000), \
11387 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11388 X(_mvn, 43c0, ea6f0000), \
11389 X(_mvns, 43c0, ea7f0000), \
11390 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11391 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11392 X(_orr, 4300, ea400000), \
11393 X(_orrs, 4300, ea500000), \
11394 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11395 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11396 X(_rev, ba00, fa90f080), \
11397 X(_rev16, ba40, fa90f090), \
11398 X(_revsh, bac0, fa90f0b0), \
11399 X(_ror, 41c0, fa60f000), \
11400 X(_rors, 41c0, fa70f000), \
11401 X(_sbc, 4180, eb600000), \
11402 X(_sbcs, 4180, eb700000), \
11403 X(_stmia, c000, e8800000), \
11404 X(_str, 6000, f8400000), \
11405 X(_strb, 7000, f8000000), \
11406 X(_strh, 8000, f8200000), \
11407 X(_str_sp,9000, f84d0000), \
11408 X(_sub, 1e00, eba00000), \
11409 X(_subs, 1e00, ebb00000), \
11410 X(_subi, 8000, f1a00000), \
11411 X(_subis, 8000, f1b00000), \
11412 X(_sxtb, b240, fa4ff080), \
11413 X(_sxth, b200, fa0ff080), \
11414 X(_tst, 4200, ea100f00), \
11415 X(_uxtb, b2c0, fa5ff080), \
11416 X(_uxth, b280, fa1ff080), \
11417 X(_nop, bf00, f3af8000), \
11418 X(_yield, bf10, f3af8001), \
11419 X(_wfe, bf20, f3af8002), \
11420 X(_wfi, bf30, f3af8003), \
11421 X(_wls, 0000, f040c001), \
11422 X(_wlstp, 0000, f000c001), \
11423 X(_sev, bf40, f3af8004), \
11424 X(_sevl, bf50, f3af8005), \
11425 X(_udf, de00, f7f0a000)
11427 /* To catch errors in encoding functions, the codes are all offset by
11428 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11429 as 16-bit instructions. */
11430 #define X(a,b,c) T_MNEM##a
11431 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11434 #define X(a,b,c) 0x##b
11435 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11436 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11439 #define X(a,b,c) 0x##c
11440 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11441 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11442 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11446 /* Thumb instruction encoders, in alphabetical order. */
11448 /* ADDW or SUBW. */
11451 do_t_add_sub_w (void)
11455 Rd
= inst
.operands
[0].reg
;
11456 Rn
= inst
.operands
[1].reg
;
11458 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11459 is the SP-{plus,minus}-immediate form of the instruction. */
11461 constraint (Rd
== REG_PC
, BAD_PC
);
11463 reject_bad_reg (Rd
);
11465 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11466 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11469 /* Parse an add or subtract instruction. We get here with inst.instruction
11470 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11473 do_t_add_sub (void)
11477 Rd
= inst
.operands
[0].reg
;
11478 Rs
= (inst
.operands
[1].present
11479 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11480 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11483 set_pred_insn_type_last ();
11485 if (unified_syntax
)
11488 bfd_boolean narrow
;
11491 flags
= (inst
.instruction
== T_MNEM_adds
11492 || inst
.instruction
== T_MNEM_subs
);
11494 narrow
= !in_pred_block ();
11496 narrow
= in_pred_block ();
11497 if (!inst
.operands
[2].isreg
)
11501 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11502 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11504 add
= (inst
.instruction
== T_MNEM_add
11505 || inst
.instruction
== T_MNEM_adds
);
11507 if (inst
.size_req
!= 4)
11509 /* Attempt to use a narrow opcode, with relaxation if
11511 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11512 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11513 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11514 opcode
= T_MNEM_add_sp
;
11515 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11516 opcode
= T_MNEM_add_pc
;
11517 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11520 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11522 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11526 inst
.instruction
= THUMB_OP16(opcode
);
11527 inst
.instruction
|= (Rd
<< 4) | Rs
;
11528 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11529 || (inst
.relocs
[0].type
11530 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11532 if (inst
.size_req
== 2)
11533 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11535 inst
.relax
= opcode
;
11539 constraint (inst
.size_req
== 2, BAD_HIREG
);
11541 if (inst
.size_req
== 4
11542 || (inst
.size_req
!= 2 && !opcode
))
11544 constraint ((inst
.relocs
[0].type
11545 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11546 && (inst
.relocs
[0].type
11547 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11548 THUMB1_RELOC_ONLY
);
11551 constraint (add
, BAD_PC
);
11552 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11553 _("only SUBS PC, LR, #const allowed"));
11554 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11555 _("expression too complex"));
11556 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11557 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11558 _("immediate value out of range"));
11559 inst
.instruction
= T2_SUBS_PC_LR
11560 | inst
.relocs
[0].exp
.X_add_number
;
11561 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11564 else if (Rs
== REG_PC
)
11566 /* Always use addw/subw. */
11567 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11568 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11572 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11573 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11576 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11578 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11580 inst
.instruction
|= Rd
<< 8;
11581 inst
.instruction
|= Rs
<< 16;
11586 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11587 unsigned int shift
= inst
.operands
[2].shift_kind
;
11589 Rn
= inst
.operands
[2].reg
;
11590 /* See if we can do this with a 16-bit instruction. */
11591 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11593 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11598 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11599 || inst
.instruction
== T_MNEM_add
)
11601 : T_OPCODE_SUB_R3
);
11602 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11606 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11608 /* Thumb-1 cores (except v6-M) require at least one high
11609 register in a narrow non flag setting add. */
11610 if (Rd
> 7 || Rn
> 7
11611 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11612 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11619 inst
.instruction
= T_OPCODE_ADD_HI
;
11620 inst
.instruction
|= (Rd
& 8) << 4;
11621 inst
.instruction
|= (Rd
& 7);
11622 inst
.instruction
|= Rn
<< 3;
11628 constraint (Rd
== REG_PC
, BAD_PC
);
11629 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11630 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11631 constraint (Rs
== REG_PC
, BAD_PC
);
11632 reject_bad_reg (Rn
);
11634 /* If we get here, it can't be done in 16 bits. */
11635 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11636 _("shift must be constant"));
11637 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11638 inst
.instruction
|= Rd
<< 8;
11639 inst
.instruction
|= Rs
<< 16;
11640 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11641 _("shift value over 3 not allowed in thumb mode"));
11642 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11643 _("only LSL shift allowed in thumb mode"));
11644 encode_thumb32_shifted_operand (2);
11649 constraint (inst
.instruction
== T_MNEM_adds
11650 || inst
.instruction
== T_MNEM_subs
,
11653 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11655 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11656 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11659 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11660 ? 0x0000 : 0x8000);
11661 inst
.instruction
|= (Rd
<< 4) | Rs
;
11662 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11666 Rn
= inst
.operands
[2].reg
;
11667 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11669 /* We now have Rd, Rs, and Rn set to registers. */
11670 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11672 /* Can't do this for SUB. */
11673 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11674 inst
.instruction
= T_OPCODE_ADD_HI
;
11675 inst
.instruction
|= (Rd
& 8) << 4;
11676 inst
.instruction
|= (Rd
& 7);
11678 inst
.instruction
|= Rn
<< 3;
11680 inst
.instruction
|= Rs
<< 3;
11682 constraint (1, _("dest must overlap one source register"));
11686 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11687 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11688 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11698 Rd
= inst
.operands
[0].reg
;
11699 reject_bad_reg (Rd
);
11701 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11703 /* Defer to section relaxation. */
11704 inst
.relax
= inst
.instruction
;
11705 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11706 inst
.instruction
|= Rd
<< 4;
11708 else if (unified_syntax
&& inst
.size_req
!= 2)
11710 /* Generate a 32-bit opcode. */
11711 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11712 inst
.instruction
|= Rd
<< 8;
11713 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11714 inst
.relocs
[0].pc_rel
= 1;
11718 /* Generate a 16-bit opcode. */
11719 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11720 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11721 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11722 inst
.relocs
[0].pc_rel
= 1;
11723 inst
.instruction
|= Rd
<< 4;
11726 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11727 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11728 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11729 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11730 inst
.relocs
[0].exp
.X_add_number
+= 1;
11733 /* Arithmetic instructions for which there is just one 16-bit
11734 instruction encoding, and it allows only two low registers.
11735 For maximal compatibility with ARM syntax, we allow three register
11736 operands even when Thumb-32 instructions are not available, as long
11737 as the first two are identical. For instance, both "sbc r0,r1" and
11738 "sbc r0,r0,r1" are allowed. */
11744 Rd
= inst
.operands
[0].reg
;
11745 Rs
= (inst
.operands
[1].present
11746 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11747 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11748 Rn
= inst
.operands
[2].reg
;
11750 reject_bad_reg (Rd
);
11751 reject_bad_reg (Rs
);
11752 if (inst
.operands
[2].isreg
)
11753 reject_bad_reg (Rn
);
11755 if (unified_syntax
)
11757 if (!inst
.operands
[2].isreg
)
11759 /* For an immediate, we always generate a 32-bit opcode;
11760 section relaxation will shrink it later if possible. */
11761 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11762 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11763 inst
.instruction
|= Rd
<< 8;
11764 inst
.instruction
|= Rs
<< 16;
11765 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11769 bfd_boolean narrow
;
11771 /* See if we can do this with a 16-bit instruction. */
11772 if (THUMB_SETS_FLAGS (inst
.instruction
))
11773 narrow
= !in_pred_block ();
11775 narrow
= in_pred_block ();
11777 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11779 if (inst
.operands
[2].shifted
)
11781 if (inst
.size_req
== 4)
11787 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11788 inst
.instruction
|= Rd
;
11789 inst
.instruction
|= Rn
<< 3;
11793 /* If we get here, it can't be done in 16 bits. */
11794 constraint (inst
.operands
[2].shifted
11795 && inst
.operands
[2].immisreg
,
11796 _("shift must be constant"));
11797 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11798 inst
.instruction
|= Rd
<< 8;
11799 inst
.instruction
|= Rs
<< 16;
11800 encode_thumb32_shifted_operand (2);
11805 /* On its face this is a lie - the instruction does set the
11806 flags. However, the only supported mnemonic in this mode
11807 says it doesn't. */
11808 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11810 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11811 _("unshifted register required"));
11812 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11813 constraint (Rd
!= Rs
,
11814 _("dest and source1 must be the same register"));
11816 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11817 inst
.instruction
|= Rd
;
11818 inst
.instruction
|= Rn
<< 3;
11822 /* Similarly, but for instructions where the arithmetic operation is
11823 commutative, so we can allow either of them to be different from
11824 the destination operand in a 16-bit instruction. For instance, all
11825 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11832 Rd
= inst
.operands
[0].reg
;
11833 Rs
= (inst
.operands
[1].present
11834 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11835 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11836 Rn
= inst
.operands
[2].reg
;
11838 reject_bad_reg (Rd
);
11839 reject_bad_reg (Rs
);
11840 if (inst
.operands
[2].isreg
)
11841 reject_bad_reg (Rn
);
11843 if (unified_syntax
)
11845 if (!inst
.operands
[2].isreg
)
11847 /* For an immediate, we always generate a 32-bit opcode;
11848 section relaxation will shrink it later if possible. */
11849 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11850 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11851 inst
.instruction
|= Rd
<< 8;
11852 inst
.instruction
|= Rs
<< 16;
11853 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11857 bfd_boolean narrow
;
11859 /* See if we can do this with a 16-bit instruction. */
11860 if (THUMB_SETS_FLAGS (inst
.instruction
))
11861 narrow
= !in_pred_block ();
11863 narrow
= in_pred_block ();
11865 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11867 if (inst
.operands
[2].shifted
)
11869 if (inst
.size_req
== 4)
11876 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11877 inst
.instruction
|= Rd
;
11878 inst
.instruction
|= Rn
<< 3;
11883 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11884 inst
.instruction
|= Rd
;
11885 inst
.instruction
|= Rs
<< 3;
11890 /* If we get here, it can't be done in 16 bits. */
11891 constraint (inst
.operands
[2].shifted
11892 && inst
.operands
[2].immisreg
,
11893 _("shift must be constant"));
11894 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11895 inst
.instruction
|= Rd
<< 8;
11896 inst
.instruction
|= Rs
<< 16;
11897 encode_thumb32_shifted_operand (2);
11902 /* On its face this is a lie - the instruction does set the
11903 flags. However, the only supported mnemonic in this mode
11904 says it doesn't. */
11905 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11907 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11908 _("unshifted register required"));
11909 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11911 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11912 inst
.instruction
|= Rd
;
11915 inst
.instruction
|= Rn
<< 3;
11917 inst
.instruction
|= Rs
<< 3;
11919 constraint (1, _("dest must overlap one source register"));
11927 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11928 constraint (msb
> 32, _("bit-field extends past end of register"));
11929 /* The instruction encoding stores the LSB and MSB,
11930 not the LSB and width. */
11931 Rd
= inst
.operands
[0].reg
;
11932 reject_bad_reg (Rd
);
11933 inst
.instruction
|= Rd
<< 8;
11934 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11935 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11936 inst
.instruction
|= msb
- 1;
11945 Rd
= inst
.operands
[0].reg
;
11946 reject_bad_reg (Rd
);
11948 /* #0 in second position is alternative syntax for bfc, which is
11949 the same instruction but with REG_PC in the Rm field. */
11950 if (!inst
.operands
[1].isreg
)
11954 Rn
= inst
.operands
[1].reg
;
11955 reject_bad_reg (Rn
);
11958 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11959 constraint (msb
> 32, _("bit-field extends past end of register"));
11960 /* The instruction encoding stores the LSB and MSB,
11961 not the LSB and width. */
11962 inst
.instruction
|= Rd
<< 8;
11963 inst
.instruction
|= Rn
<< 16;
11964 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11965 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11966 inst
.instruction
|= msb
- 1;
11974 Rd
= inst
.operands
[0].reg
;
11975 Rn
= inst
.operands
[1].reg
;
11977 reject_bad_reg (Rd
);
11978 reject_bad_reg (Rn
);
11980 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11981 _("bit-field extends past end of register"));
11982 inst
.instruction
|= Rd
<< 8;
11983 inst
.instruction
|= Rn
<< 16;
11984 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11985 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11986 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11989 /* ARM V5 Thumb BLX (argument parse)
11990 BLX <target_addr> which is BLX(1)
11991 BLX <Rm> which is BLX(2)
11992 Unfortunately, there are two different opcodes for this mnemonic.
11993 So, the insns[].value is not used, and the code here zaps values
11994 into inst.instruction.
11996 ??? How to take advantage of the additional two bits of displacement
11997 available in Thumb32 mode? Need new relocation? */
12002 set_pred_insn_type_last ();
12004 if (inst
.operands
[0].isreg
)
12006 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12007 /* We have a register, so this is BLX(2). */
12008 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12012 /* No register. This must be BLX(1). */
12013 inst
.instruction
= 0xf000e800;
12014 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12023 bfd_reloc_code_real_type reloc
;
12026 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12028 if (in_pred_block ())
12030 /* Conditional branches inside IT blocks are encoded as unconditional
12032 cond
= COND_ALWAYS
;
12037 if (cond
!= COND_ALWAYS
)
12038 opcode
= T_MNEM_bcond
;
12040 opcode
= inst
.instruction
;
12043 && (inst
.size_req
== 4
12044 || (inst
.size_req
!= 2
12045 && (inst
.operands
[0].hasreloc
12046 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12048 inst
.instruction
= THUMB_OP32(opcode
);
12049 if (cond
== COND_ALWAYS
)
12050 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12053 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12054 _("selected architecture does not support "
12055 "wide conditional branch instruction"));
12057 gas_assert (cond
!= 0xF);
12058 inst
.instruction
|= cond
<< 22;
12059 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12064 inst
.instruction
= THUMB_OP16(opcode
);
12065 if (cond
== COND_ALWAYS
)
12066 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12069 inst
.instruction
|= cond
<< 8;
12070 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12072 /* Allow section relaxation. */
12073 if (unified_syntax
&& inst
.size_req
!= 2)
12074 inst
.relax
= opcode
;
12076 inst
.relocs
[0].type
= reloc
;
12077 inst
.relocs
[0].pc_rel
= 1;
12080 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12081 between the two is the maximum immediate allowed - which is passed in
12084 do_t_bkpt_hlt1 (int range
)
12086 constraint (inst
.cond
!= COND_ALWAYS
,
12087 _("instruction is always unconditional"));
12088 if (inst
.operands
[0].present
)
12090 constraint (inst
.operands
[0].imm
> range
,
12091 _("immediate value out of range"));
12092 inst
.instruction
|= inst
.operands
[0].imm
;
12095 set_pred_insn_type (NEUTRAL_IT_INSN
);
12101 do_t_bkpt_hlt1 (63);
12107 do_t_bkpt_hlt1 (255);
12111 do_t_branch23 (void)
12113 set_pred_insn_type_last ();
12114 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12116 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12117 this file. We used to simply ignore the PLT reloc type here --
12118 the branch encoding is now needed to deal with TLSCALL relocs.
12119 So if we see a PLT reloc now, put it back to how it used to be to
12120 keep the preexisting behaviour. */
12121 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12122 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12124 #if defined(OBJ_COFF)
12125 /* If the destination of the branch is a defined symbol which does not have
12126 the THUMB_FUNC attribute, then we must be calling a function which has
12127 the (interfacearm) attribute. We look for the Thumb entry point to that
12128 function and change the branch to refer to that function instead. */
12129 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12130 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12131 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12132 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12133 inst
.relocs
[0].exp
.X_add_symbol
12134 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12141 set_pred_insn_type_last ();
12142 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12143 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12144 should cause the alignment to be checked once it is known. This is
12145 because BX PC only works if the instruction is word aligned. */
12153 set_pred_insn_type_last ();
12154 Rm
= inst
.operands
[0].reg
;
12155 reject_bad_reg (Rm
);
12156 inst
.instruction
|= Rm
<< 16;
12165 Rd
= inst
.operands
[0].reg
;
12166 Rm
= inst
.operands
[1].reg
;
12168 reject_bad_reg (Rd
);
12169 reject_bad_reg (Rm
);
12171 inst
.instruction
|= Rd
<< 8;
12172 inst
.instruction
|= Rm
<< 16;
12173 inst
.instruction
|= Rm
;
12176 /* For the Armv8.1-M conditional instructions. */
12180 unsigned Rd
, Rn
, Rm
;
12183 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12185 Rd
= inst
.operands
[0].reg
;
12186 switch (inst
.instruction
)
12192 Rn
= inst
.operands
[1].reg
;
12193 Rm
= inst
.operands
[2].reg
;
12194 cond
= inst
.operands
[3].imm
;
12195 constraint (Rn
== REG_SP
, BAD_SP
);
12196 constraint (Rm
== REG_SP
, BAD_SP
);
12202 Rn
= inst
.operands
[1].reg
;
12203 cond
= inst
.operands
[2].imm
;
12204 /* Invert the last bit to invert the cond. */
12205 cond
= TOGGLE_BIT (cond
, 0);
12206 constraint (Rn
== REG_SP
, BAD_SP
);
12212 cond
= inst
.operands
[1].imm
;
12213 /* Invert the last bit to invert the cond. */
12214 cond
= TOGGLE_BIT (cond
, 0);
12222 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12223 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12224 inst
.instruction
|= Rd
<< 8;
12225 inst
.instruction
|= Rn
<< 16;
12226 inst
.instruction
|= Rm
;
12227 inst
.instruction
|= cond
<< 4;
12233 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12239 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12240 inst
.instruction
|= inst
.operands
[0].imm
;
12246 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12248 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12249 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12251 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12252 inst
.instruction
= 0xf3af8000;
12253 inst
.instruction
|= imod
<< 9;
12254 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12255 if (inst
.operands
[1].present
)
12256 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12260 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12261 && (inst
.operands
[0].imm
& 4),
12262 _("selected processor does not support 'A' form "
12263 "of this instruction"));
12264 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12265 _("Thumb does not support the 2-argument "
12266 "form of this instruction"));
12267 inst
.instruction
|= inst
.operands
[0].imm
;
12271 /* THUMB CPY instruction (argument parse). */
12276 if (inst
.size_req
== 4)
12278 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12279 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12280 inst
.instruction
|= inst
.operands
[1].reg
;
12284 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12285 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12286 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12293 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12294 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12295 inst
.instruction
|= inst
.operands
[0].reg
;
12296 inst
.relocs
[0].pc_rel
= 1;
12297 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12303 inst
.instruction
|= inst
.operands
[0].imm
;
12309 unsigned Rd
, Rn
, Rm
;
12311 Rd
= inst
.operands
[0].reg
;
12312 Rn
= (inst
.operands
[1].present
12313 ? inst
.operands
[1].reg
: Rd
);
12314 Rm
= inst
.operands
[2].reg
;
12316 reject_bad_reg (Rd
);
12317 reject_bad_reg (Rn
);
12318 reject_bad_reg (Rm
);
12320 inst
.instruction
|= Rd
<< 8;
12321 inst
.instruction
|= Rn
<< 16;
12322 inst
.instruction
|= Rm
;
12328 if (unified_syntax
&& inst
.size_req
== 4)
12329 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12331 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12337 unsigned int cond
= inst
.operands
[0].imm
;
12339 set_pred_insn_type (IT_INSN
);
12340 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12341 now_pred
.cc
= cond
;
12342 now_pred
.warn_deprecated
= FALSE
;
12343 now_pred
.type
= SCALAR_PRED
;
12345 /* If the condition is a negative condition, invert the mask. */
12346 if ((cond
& 0x1) == 0x0)
12348 unsigned int mask
= inst
.instruction
& 0x000f;
12350 if ((mask
& 0x7) == 0)
12352 /* No conversion needed. */
12353 now_pred
.block_length
= 1;
12355 else if ((mask
& 0x3) == 0)
12358 now_pred
.block_length
= 2;
12360 else if ((mask
& 0x1) == 0)
12363 now_pred
.block_length
= 3;
12368 now_pred
.block_length
= 4;
12371 inst
.instruction
&= 0xfff0;
12372 inst
.instruction
|= mask
;
12375 inst
.instruction
|= cond
<< 4;
12378 /* Helper function used for both push/pop and ldm/stm. */
12380 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12381 bfd_boolean writeback
)
12383 bfd_boolean load
, store
;
12385 gas_assert (base
!= -1 || !do_io
);
12386 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12387 store
= do_io
&& !load
;
12389 if (mask
& (1 << 13))
12390 inst
.error
= _("SP not allowed in register list");
12392 if (do_io
&& (mask
& (1 << base
)) != 0
12394 inst
.error
= _("having the base register in the register list when "
12395 "using write back is UNPREDICTABLE");
12399 if (mask
& (1 << 15))
12401 if (mask
& (1 << 14))
12402 inst
.error
= _("LR and PC should not both be in register list");
12404 set_pred_insn_type_last ();
12409 if (mask
& (1 << 15))
12410 inst
.error
= _("PC not allowed in register list");
12413 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12415 /* Single register transfers implemented as str/ldr. */
12418 if (inst
.instruction
& (1 << 23))
12419 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12421 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12425 if (inst
.instruction
& (1 << 23))
12426 inst
.instruction
= 0x00800000; /* ia -> [base] */
12428 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12431 inst
.instruction
|= 0xf8400000;
12433 inst
.instruction
|= 0x00100000;
12435 mask
= ffs (mask
) - 1;
12438 else if (writeback
)
12439 inst
.instruction
|= WRITE_BACK
;
12441 inst
.instruction
|= mask
;
12443 inst
.instruction
|= base
<< 16;
12449 /* This really doesn't seem worth it. */
12450 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12451 _("expression too complex"));
12452 constraint (inst
.operands
[1].writeback
,
12453 _("Thumb load/store multiple does not support {reglist}^"));
12455 if (unified_syntax
)
12457 bfd_boolean narrow
;
12461 /* See if we can use a 16-bit instruction. */
12462 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12463 && inst
.size_req
!= 4
12464 && !(inst
.operands
[1].imm
& ~0xff))
12466 mask
= 1 << inst
.operands
[0].reg
;
12468 if (inst
.operands
[0].reg
<= 7)
12470 if (inst
.instruction
== T_MNEM_stmia
12471 ? inst
.operands
[0].writeback
12472 : (inst
.operands
[0].writeback
12473 == !(inst
.operands
[1].imm
& mask
)))
12475 if (inst
.instruction
== T_MNEM_stmia
12476 && (inst
.operands
[1].imm
& mask
)
12477 && (inst
.operands
[1].imm
& (mask
- 1)))
12478 as_warn (_("value stored for r%d is UNKNOWN"),
12479 inst
.operands
[0].reg
);
12481 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12482 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12483 inst
.instruction
|= inst
.operands
[1].imm
;
12486 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12488 /* This means 1 register in reg list one of 3 situations:
12489 1. Instruction is stmia, but without writeback.
12490 2. lmdia without writeback, but with Rn not in
12492 3. ldmia with writeback, but with Rn in reglist.
12493 Case 3 is UNPREDICTABLE behaviour, so we handle
12494 case 1 and 2 which can be converted into a 16-bit
12495 str or ldr. The SP cases are handled below. */
12496 unsigned long opcode
;
12497 /* First, record an error for Case 3. */
12498 if (inst
.operands
[1].imm
& mask
12499 && inst
.operands
[0].writeback
)
12501 _("having the base register in the register list when "
12502 "using write back is UNPREDICTABLE");
12504 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12506 inst
.instruction
= THUMB_OP16 (opcode
);
12507 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12508 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12512 else if (inst
.operands
[0] .reg
== REG_SP
)
12514 if (inst
.operands
[0].writeback
)
12517 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12518 ? T_MNEM_push
: T_MNEM_pop
);
12519 inst
.instruction
|= inst
.operands
[1].imm
;
12522 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12525 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12526 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12527 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12535 if (inst
.instruction
< 0xffff)
12536 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12538 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12539 inst
.operands
[1].imm
,
12540 inst
.operands
[0].writeback
);
12545 constraint (inst
.operands
[0].reg
> 7
12546 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12547 constraint (inst
.instruction
!= T_MNEM_ldmia
12548 && inst
.instruction
!= T_MNEM_stmia
,
12549 _("Thumb-2 instruction only valid in unified syntax"));
12550 if (inst
.instruction
== T_MNEM_stmia
)
12552 if (!inst
.operands
[0].writeback
)
12553 as_warn (_("this instruction will write back the base register"));
12554 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12555 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12556 as_warn (_("value stored for r%d is UNKNOWN"),
12557 inst
.operands
[0].reg
);
12561 if (!inst
.operands
[0].writeback
12562 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12563 as_warn (_("this instruction will write back the base register"));
12564 else if (inst
.operands
[0].writeback
12565 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12566 as_warn (_("this instruction will not write back the base register"));
12569 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12570 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12571 inst
.instruction
|= inst
.operands
[1].imm
;
12578 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12579 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12580 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12581 || inst
.operands
[1].negative
,
12584 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12586 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12587 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12588 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12594 if (!inst
.operands
[1].present
)
12596 constraint (inst
.operands
[0].reg
== REG_LR
,
12597 _("r14 not allowed as first register "
12598 "when second register is omitted"));
12599 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12601 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12604 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12605 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12606 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12612 unsigned long opcode
;
12615 if (inst
.operands
[0].isreg
12616 && !inst
.operands
[0].preind
12617 && inst
.operands
[0].reg
== REG_PC
)
12618 set_pred_insn_type_last ();
12620 opcode
= inst
.instruction
;
12621 if (unified_syntax
)
12623 if (!inst
.operands
[1].isreg
)
12625 if (opcode
<= 0xffff)
12626 inst
.instruction
= THUMB_OP32 (opcode
);
12627 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12630 if (inst
.operands
[1].isreg
12631 && !inst
.operands
[1].writeback
12632 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12633 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12634 && opcode
<= 0xffff
12635 && inst
.size_req
!= 4)
12637 /* Insn may have a 16-bit form. */
12638 Rn
= inst
.operands
[1].reg
;
12639 if (inst
.operands
[1].immisreg
)
12641 inst
.instruction
= THUMB_OP16 (opcode
);
12643 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12645 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12646 reject_bad_reg (inst
.operands
[1].imm
);
12648 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12649 && opcode
!= T_MNEM_ldrsb
)
12650 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12651 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12658 if (inst
.relocs
[0].pc_rel
)
12659 opcode
= T_MNEM_ldr_pc2
;
12661 opcode
= T_MNEM_ldr_pc
;
12665 if (opcode
== T_MNEM_ldr
)
12666 opcode
= T_MNEM_ldr_sp
;
12668 opcode
= T_MNEM_str_sp
;
12670 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12674 inst
.instruction
= inst
.operands
[0].reg
;
12675 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12677 inst
.instruction
|= THUMB_OP16 (opcode
);
12678 if (inst
.size_req
== 2)
12679 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12681 inst
.relax
= opcode
;
12685 /* Definitely a 32-bit variant. */
12687 /* Warning for Erratum 752419. */
12688 if (opcode
== T_MNEM_ldr
12689 && inst
.operands
[0].reg
== REG_SP
12690 && inst
.operands
[1].writeback
== 1
12691 && !inst
.operands
[1].immisreg
)
12693 if (no_cpu_selected ()
12694 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12695 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12696 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12697 as_warn (_("This instruction may be unpredictable "
12698 "if executed on M-profile cores "
12699 "with interrupts enabled."));
12702 /* Do some validations regarding addressing modes. */
12703 if (inst
.operands
[1].immisreg
)
12704 reject_bad_reg (inst
.operands
[1].imm
);
12706 constraint (inst
.operands
[1].writeback
== 1
12707 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12710 inst
.instruction
= THUMB_OP32 (opcode
);
12711 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12712 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12713 check_ldr_r15_aligned ();
12717 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12719 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12721 /* Only [Rn,Rm] is acceptable. */
12722 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12723 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12724 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12725 || inst
.operands
[1].negative
,
12726 _("Thumb does not support this addressing mode"));
12727 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12731 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12732 if (!inst
.operands
[1].isreg
)
12733 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12736 constraint (!inst
.operands
[1].preind
12737 || inst
.operands
[1].shifted
12738 || inst
.operands
[1].writeback
,
12739 _("Thumb does not support this addressing mode"));
12740 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12742 constraint (inst
.instruction
& 0x0600,
12743 _("byte or halfword not valid for base register"));
12744 constraint (inst
.operands
[1].reg
== REG_PC
12745 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12746 _("r15 based store not allowed"));
12747 constraint (inst
.operands
[1].immisreg
,
12748 _("invalid base register for register offset"));
12750 if (inst
.operands
[1].reg
== REG_PC
)
12751 inst
.instruction
= T_OPCODE_LDR_PC
;
12752 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12753 inst
.instruction
= T_OPCODE_LDR_SP
;
12755 inst
.instruction
= T_OPCODE_STR_SP
;
12757 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12758 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12762 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12763 if (!inst
.operands
[1].immisreg
)
12765 /* Immediate offset. */
12766 inst
.instruction
|= inst
.operands
[0].reg
;
12767 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12768 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12772 /* Register offset. */
12773 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12774 constraint (inst
.operands
[1].negative
,
12775 _("Thumb does not support this addressing mode"));
12778 switch (inst
.instruction
)
12780 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12781 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12782 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12783 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12784 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12785 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12786 case 0x5600 /* ldrsb */:
12787 case 0x5e00 /* ldrsh */: break;
12791 inst
.instruction
|= inst
.operands
[0].reg
;
12792 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12793 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12799 if (!inst
.operands
[1].present
)
12801 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12802 constraint (inst
.operands
[0].reg
== REG_LR
,
12803 _("r14 not allowed here"));
12804 constraint (inst
.operands
[0].reg
== REG_R12
,
12805 _("r12 not allowed here"));
12808 if (inst
.operands
[2].writeback
12809 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12810 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12811 as_warn (_("base register written back, and overlaps "
12812 "one of transfer registers"));
12814 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12815 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12816 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12822 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12823 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12829 unsigned Rd
, Rn
, Rm
, Ra
;
12831 Rd
= inst
.operands
[0].reg
;
12832 Rn
= inst
.operands
[1].reg
;
12833 Rm
= inst
.operands
[2].reg
;
12834 Ra
= inst
.operands
[3].reg
;
12836 reject_bad_reg (Rd
);
12837 reject_bad_reg (Rn
);
12838 reject_bad_reg (Rm
);
12839 reject_bad_reg (Ra
);
12841 inst
.instruction
|= Rd
<< 8;
12842 inst
.instruction
|= Rn
<< 16;
12843 inst
.instruction
|= Rm
;
12844 inst
.instruction
|= Ra
<< 12;
12850 unsigned RdLo
, RdHi
, Rn
, Rm
;
12852 RdLo
= inst
.operands
[0].reg
;
12853 RdHi
= inst
.operands
[1].reg
;
12854 Rn
= inst
.operands
[2].reg
;
12855 Rm
= inst
.operands
[3].reg
;
12857 reject_bad_reg (RdLo
);
12858 reject_bad_reg (RdHi
);
12859 reject_bad_reg (Rn
);
12860 reject_bad_reg (Rm
);
12862 inst
.instruction
|= RdLo
<< 12;
12863 inst
.instruction
|= RdHi
<< 8;
12864 inst
.instruction
|= Rn
<< 16;
12865 inst
.instruction
|= Rm
;
12869 do_t_mov_cmp (void)
12873 Rn
= inst
.operands
[0].reg
;
12874 Rm
= inst
.operands
[1].reg
;
12877 set_pred_insn_type_last ();
12879 if (unified_syntax
)
12881 int r0off
= (inst
.instruction
== T_MNEM_mov
12882 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12883 unsigned long opcode
;
12884 bfd_boolean narrow
;
12885 bfd_boolean low_regs
;
12887 low_regs
= (Rn
<= 7 && Rm
<= 7);
12888 opcode
= inst
.instruction
;
12889 if (in_pred_block ())
12890 narrow
= opcode
!= T_MNEM_movs
;
12892 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12893 if (inst
.size_req
== 4
12894 || inst
.operands
[1].shifted
)
12897 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12898 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12899 && !inst
.operands
[1].shifted
12903 inst
.instruction
= T2_SUBS_PC_LR
;
12907 if (opcode
== T_MNEM_cmp
)
12909 constraint (Rn
== REG_PC
, BAD_PC
);
12912 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12914 warn_deprecated_sp (Rm
);
12915 /* R15 was documented as a valid choice for Rm in ARMv6,
12916 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12917 tools reject R15, so we do too. */
12918 constraint (Rm
== REG_PC
, BAD_PC
);
12921 reject_bad_reg (Rm
);
12923 else if (opcode
== T_MNEM_mov
12924 || opcode
== T_MNEM_movs
)
12926 if (inst
.operands
[1].isreg
)
12928 if (opcode
== T_MNEM_movs
)
12930 reject_bad_reg (Rn
);
12931 reject_bad_reg (Rm
);
12935 /* This is mov.n. */
12936 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12937 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12939 as_tsktsk (_("Use of r%u as a source register is "
12940 "deprecated when r%u is the destination "
12941 "register."), Rm
, Rn
);
12946 /* This is mov.w. */
12947 constraint (Rn
== REG_PC
, BAD_PC
);
12948 constraint (Rm
== REG_PC
, BAD_PC
);
12949 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12950 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12954 reject_bad_reg (Rn
);
12957 if (!inst
.operands
[1].isreg
)
12959 /* Immediate operand. */
12960 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12962 if (low_regs
&& narrow
)
12964 inst
.instruction
= THUMB_OP16 (opcode
);
12965 inst
.instruction
|= Rn
<< 8;
12966 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12967 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12969 if (inst
.size_req
== 2)
12970 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12972 inst
.relax
= opcode
;
12977 constraint ((inst
.relocs
[0].type
12978 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12979 && (inst
.relocs
[0].type
12980 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12981 THUMB1_RELOC_ONLY
);
12983 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12984 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12985 inst
.instruction
|= Rn
<< r0off
;
12986 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12989 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12990 && (inst
.instruction
== T_MNEM_mov
12991 || inst
.instruction
== T_MNEM_movs
))
12993 /* Register shifts are encoded as separate shift instructions. */
12994 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12996 if (in_pred_block ())
13001 if (inst
.size_req
== 4)
13004 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13010 switch (inst
.operands
[1].shift_kind
)
13013 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13016 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13019 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13022 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13028 inst
.instruction
= opcode
;
13031 inst
.instruction
|= Rn
;
13032 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13037 inst
.instruction
|= CONDS_BIT
;
13039 inst
.instruction
|= Rn
<< 8;
13040 inst
.instruction
|= Rm
<< 16;
13041 inst
.instruction
|= inst
.operands
[1].imm
;
13046 /* Some mov with immediate shift have narrow variants.
13047 Register shifts are handled above. */
13048 if (low_regs
&& inst
.operands
[1].shifted
13049 && (inst
.instruction
== T_MNEM_mov
13050 || inst
.instruction
== T_MNEM_movs
))
13052 if (in_pred_block ())
13053 narrow
= (inst
.instruction
== T_MNEM_mov
);
13055 narrow
= (inst
.instruction
== T_MNEM_movs
);
13060 switch (inst
.operands
[1].shift_kind
)
13062 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13063 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13064 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13065 default: narrow
= FALSE
; break;
13071 inst
.instruction
|= Rn
;
13072 inst
.instruction
|= Rm
<< 3;
13073 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13077 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13078 inst
.instruction
|= Rn
<< r0off
;
13079 encode_thumb32_shifted_operand (1);
13083 switch (inst
.instruction
)
13086 /* In v4t or v5t a move of two lowregs produces unpredictable
13087 results. Don't allow this. */
13090 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13091 "MOV Rd, Rs with two low registers is not "
13092 "permitted on this architecture");
13093 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13097 inst
.instruction
= T_OPCODE_MOV_HR
;
13098 inst
.instruction
|= (Rn
& 0x8) << 4;
13099 inst
.instruction
|= (Rn
& 0x7);
13100 inst
.instruction
|= Rm
<< 3;
13104 /* We know we have low registers at this point.
13105 Generate LSLS Rd, Rs, #0. */
13106 inst
.instruction
= T_OPCODE_LSL_I
;
13107 inst
.instruction
|= Rn
;
13108 inst
.instruction
|= Rm
<< 3;
13114 inst
.instruction
= T_OPCODE_CMP_LR
;
13115 inst
.instruction
|= Rn
;
13116 inst
.instruction
|= Rm
<< 3;
13120 inst
.instruction
= T_OPCODE_CMP_HR
;
13121 inst
.instruction
|= (Rn
& 0x8) << 4;
13122 inst
.instruction
|= (Rn
& 0x7);
13123 inst
.instruction
|= Rm
<< 3;
13130 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13132 /* PR 10443: Do not silently ignore shifted operands. */
13133 constraint (inst
.operands
[1].shifted
,
13134 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13136 if (inst
.operands
[1].isreg
)
13138 if (Rn
< 8 && Rm
< 8)
13140 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13141 since a MOV instruction produces unpredictable results. */
13142 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13143 inst
.instruction
= T_OPCODE_ADD_I3
;
13145 inst
.instruction
= T_OPCODE_CMP_LR
;
13147 inst
.instruction
|= Rn
;
13148 inst
.instruction
|= Rm
<< 3;
13152 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13153 inst
.instruction
= T_OPCODE_MOV_HR
;
13155 inst
.instruction
= T_OPCODE_CMP_HR
;
13161 constraint (Rn
> 7,
13162 _("only lo regs allowed with immediate"));
13163 inst
.instruction
|= Rn
<< 8;
13164 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13175 top
= (inst
.instruction
& 0x00800000) != 0;
13176 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13178 constraint (top
, _(":lower16: not allowed in this instruction"));
13179 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13181 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13183 constraint (!top
, _(":upper16: not allowed in this instruction"));
13184 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13187 Rd
= inst
.operands
[0].reg
;
13188 reject_bad_reg (Rd
);
13190 inst
.instruction
|= Rd
<< 8;
13191 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13193 imm
= inst
.relocs
[0].exp
.X_add_number
;
13194 inst
.instruction
|= (imm
& 0xf000) << 4;
13195 inst
.instruction
|= (imm
& 0x0800) << 15;
13196 inst
.instruction
|= (imm
& 0x0700) << 4;
13197 inst
.instruction
|= (imm
& 0x00ff);
13202 do_t_mvn_tst (void)
13206 Rn
= inst
.operands
[0].reg
;
13207 Rm
= inst
.operands
[1].reg
;
13209 if (inst
.instruction
== T_MNEM_cmp
13210 || inst
.instruction
== T_MNEM_cmn
)
13211 constraint (Rn
== REG_PC
, BAD_PC
);
13213 reject_bad_reg (Rn
);
13214 reject_bad_reg (Rm
);
13216 if (unified_syntax
)
13218 int r0off
= (inst
.instruction
== T_MNEM_mvn
13219 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13220 bfd_boolean narrow
;
13222 if (inst
.size_req
== 4
13223 || inst
.instruction
> 0xffff
13224 || inst
.operands
[1].shifted
13225 || Rn
> 7 || Rm
> 7)
13227 else if (inst
.instruction
== T_MNEM_cmn
13228 || inst
.instruction
== T_MNEM_tst
)
13230 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13231 narrow
= !in_pred_block ();
13233 narrow
= in_pred_block ();
13235 if (!inst
.operands
[1].isreg
)
13237 /* For an immediate, we always generate a 32-bit opcode;
13238 section relaxation will shrink it later if possible. */
13239 if (inst
.instruction
< 0xffff)
13240 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13241 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13242 inst
.instruction
|= Rn
<< r0off
;
13243 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13247 /* See if we can do this with a 16-bit instruction. */
13250 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13251 inst
.instruction
|= Rn
;
13252 inst
.instruction
|= Rm
<< 3;
13256 constraint (inst
.operands
[1].shifted
13257 && inst
.operands
[1].immisreg
,
13258 _("shift must be constant"));
13259 if (inst
.instruction
< 0xffff)
13260 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13261 inst
.instruction
|= Rn
<< r0off
;
13262 encode_thumb32_shifted_operand (1);
13268 constraint (inst
.instruction
> 0xffff
13269 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13270 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13271 _("unshifted register required"));
13272 constraint (Rn
> 7 || Rm
> 7,
13275 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13276 inst
.instruction
|= Rn
;
13277 inst
.instruction
|= Rm
<< 3;
13286 if (do_vfp_nsyn_mrs () == SUCCESS
)
13289 Rd
= inst
.operands
[0].reg
;
13290 reject_bad_reg (Rd
);
13291 inst
.instruction
|= Rd
<< 8;
13293 if (inst
.operands
[1].isreg
)
13295 unsigned br
= inst
.operands
[1].reg
;
13296 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13297 as_bad (_("bad register for mrs"));
13299 inst
.instruction
|= br
& (0xf << 16);
13300 inst
.instruction
|= (br
& 0x300) >> 4;
13301 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13305 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13307 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13309 /* PR gas/12698: The constraint is only applied for m_profile.
13310 If the user has specified -march=all, we want to ignore it as
13311 we are building for any CPU type, including non-m variants. */
13312 bfd_boolean m_profile
=
13313 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13314 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13315 "not support requested special purpose register"));
13318 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13320 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13321 _("'APSR', 'CPSR' or 'SPSR' expected"));
13323 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13324 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13325 inst
.instruction
|= 0xf0000;
13335 if (do_vfp_nsyn_msr () == SUCCESS
)
13338 constraint (!inst
.operands
[1].isreg
,
13339 _("Thumb encoding does not support an immediate here"));
13341 if (inst
.operands
[0].isreg
)
13342 flags
= (int)(inst
.operands
[0].reg
);
13344 flags
= inst
.operands
[0].imm
;
13346 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13348 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13350 /* PR gas/12698: The constraint is only applied for m_profile.
13351 If the user has specified -march=all, we want to ignore it as
13352 we are building for any CPU type, including non-m variants. */
13353 bfd_boolean m_profile
=
13354 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13355 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13356 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13357 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13358 && bits
!= PSR_f
)) && m_profile
,
13359 _("selected processor does not support requested special "
13360 "purpose register"));
13363 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13364 "requested special purpose register"));
13366 Rn
= inst
.operands
[1].reg
;
13367 reject_bad_reg (Rn
);
13369 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13370 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13371 inst
.instruction
|= (flags
& 0x300) >> 4;
13372 inst
.instruction
|= (flags
& 0xff);
13373 inst
.instruction
|= Rn
<< 16;
13379 bfd_boolean narrow
;
13380 unsigned Rd
, Rn
, Rm
;
13382 if (!inst
.operands
[2].present
)
13383 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13385 Rd
= inst
.operands
[0].reg
;
13386 Rn
= inst
.operands
[1].reg
;
13387 Rm
= inst
.operands
[2].reg
;
13389 if (unified_syntax
)
13391 if (inst
.size_req
== 4
13397 else if (inst
.instruction
== T_MNEM_muls
)
13398 narrow
= !in_pred_block ();
13400 narrow
= in_pred_block ();
13404 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13405 constraint (Rn
> 7 || Rm
> 7,
13412 /* 16-bit MULS/Conditional MUL. */
13413 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13414 inst
.instruction
|= Rd
;
13417 inst
.instruction
|= Rm
<< 3;
13419 inst
.instruction
|= Rn
<< 3;
13421 constraint (1, _("dest must overlap one source register"));
13425 constraint (inst
.instruction
!= T_MNEM_mul
,
13426 _("Thumb-2 MUL must not set flags"));
13428 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13429 inst
.instruction
|= Rd
<< 8;
13430 inst
.instruction
|= Rn
<< 16;
13431 inst
.instruction
|= Rm
<< 0;
13433 reject_bad_reg (Rd
);
13434 reject_bad_reg (Rn
);
13435 reject_bad_reg (Rm
);
13442 unsigned RdLo
, RdHi
, Rn
, Rm
;
13444 RdLo
= inst
.operands
[0].reg
;
13445 RdHi
= inst
.operands
[1].reg
;
13446 Rn
= inst
.operands
[2].reg
;
13447 Rm
= inst
.operands
[3].reg
;
13449 reject_bad_reg (RdLo
);
13450 reject_bad_reg (RdHi
);
13451 reject_bad_reg (Rn
);
13452 reject_bad_reg (Rm
);
13454 inst
.instruction
|= RdLo
<< 12;
13455 inst
.instruction
|= RdHi
<< 8;
13456 inst
.instruction
|= Rn
<< 16;
13457 inst
.instruction
|= Rm
;
13460 as_tsktsk (_("rdhi and rdlo must be different"));
13466 set_pred_insn_type (NEUTRAL_IT_INSN
);
13468 if (unified_syntax
)
13470 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13472 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13473 inst
.instruction
|= inst
.operands
[0].imm
;
13477 /* PR9722: Check for Thumb2 availability before
13478 generating a thumb2 nop instruction. */
13479 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13481 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13482 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13485 inst
.instruction
= 0x46c0;
13490 constraint (inst
.operands
[0].present
,
13491 _("Thumb does not support NOP with hints"));
13492 inst
.instruction
= 0x46c0;
13499 if (unified_syntax
)
13501 bfd_boolean narrow
;
13503 if (THUMB_SETS_FLAGS (inst
.instruction
))
13504 narrow
= !in_pred_block ();
13506 narrow
= in_pred_block ();
13507 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13509 if (inst
.size_req
== 4)
13514 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13515 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13516 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13520 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13521 inst
.instruction
|= inst
.operands
[0].reg
;
13522 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13527 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13529 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13531 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13532 inst
.instruction
|= inst
.operands
[0].reg
;
13533 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13542 Rd
= inst
.operands
[0].reg
;
13543 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13545 reject_bad_reg (Rd
);
13546 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13547 reject_bad_reg (Rn
);
13549 inst
.instruction
|= Rd
<< 8;
13550 inst
.instruction
|= Rn
<< 16;
13552 if (!inst
.operands
[2].isreg
)
13554 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13555 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13561 Rm
= inst
.operands
[2].reg
;
13562 reject_bad_reg (Rm
);
13564 constraint (inst
.operands
[2].shifted
13565 && inst
.operands
[2].immisreg
,
13566 _("shift must be constant"));
13567 encode_thumb32_shifted_operand (2);
13574 unsigned Rd
, Rn
, Rm
;
13576 Rd
= inst
.operands
[0].reg
;
13577 Rn
= inst
.operands
[1].reg
;
13578 Rm
= inst
.operands
[2].reg
;
13580 reject_bad_reg (Rd
);
13581 reject_bad_reg (Rn
);
13582 reject_bad_reg (Rm
);
13584 inst
.instruction
|= Rd
<< 8;
13585 inst
.instruction
|= Rn
<< 16;
13586 inst
.instruction
|= Rm
;
13587 if (inst
.operands
[3].present
)
13589 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13590 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13591 _("expression too complex"));
13592 inst
.instruction
|= (val
& 0x1c) << 10;
13593 inst
.instruction
|= (val
& 0x03) << 6;
13600 if (!inst
.operands
[3].present
)
13604 inst
.instruction
&= ~0x00000020;
13606 /* PR 10168. Swap the Rm and Rn registers. */
13607 Rtmp
= inst
.operands
[1].reg
;
13608 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13609 inst
.operands
[2].reg
= Rtmp
;
13617 if (inst
.operands
[0].immisreg
)
13618 reject_bad_reg (inst
.operands
[0].imm
);
13620 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13624 do_t_push_pop (void)
13628 constraint (inst
.operands
[0].writeback
,
13629 _("push/pop do not support {reglist}^"));
13630 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13631 _("expression too complex"));
13633 mask
= inst
.operands
[0].imm
;
13634 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13635 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13636 else if (inst
.size_req
!= 4
13637 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13638 ? REG_LR
: REG_PC
)))
13640 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13641 inst
.instruction
|= THUMB_PP_PC_LR
;
13642 inst
.instruction
|= mask
& 0xff;
13644 else if (unified_syntax
)
13646 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13647 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13651 inst
.error
= _("invalid register list to push/pop instruction");
13659 if (unified_syntax
)
13660 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13663 inst
.error
= _("invalid register list to push/pop instruction");
13669 do_t_vscclrm (void)
13671 if (inst
.operands
[0].issingle
)
13673 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13674 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13675 inst
.instruction
|= inst
.operands
[0].imm
;
13679 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13680 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13681 inst
.instruction
|= 1 << 8;
13682 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13691 Rd
= inst
.operands
[0].reg
;
13692 Rm
= inst
.operands
[1].reg
;
13694 reject_bad_reg (Rd
);
13695 reject_bad_reg (Rm
);
13697 inst
.instruction
|= Rd
<< 8;
13698 inst
.instruction
|= Rm
<< 16;
13699 inst
.instruction
|= Rm
;
13707 Rd
= inst
.operands
[0].reg
;
13708 Rm
= inst
.operands
[1].reg
;
13710 reject_bad_reg (Rd
);
13711 reject_bad_reg (Rm
);
13713 if (Rd
<= 7 && Rm
<= 7
13714 && inst
.size_req
!= 4)
13716 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13717 inst
.instruction
|= Rd
;
13718 inst
.instruction
|= Rm
<< 3;
13720 else if (unified_syntax
)
13722 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13723 inst
.instruction
|= Rd
<< 8;
13724 inst
.instruction
|= Rm
<< 16;
13725 inst
.instruction
|= Rm
;
13728 inst
.error
= BAD_HIREG
;
13736 Rd
= inst
.operands
[0].reg
;
13737 Rm
= inst
.operands
[1].reg
;
13739 reject_bad_reg (Rd
);
13740 reject_bad_reg (Rm
);
13742 inst
.instruction
|= Rd
<< 8;
13743 inst
.instruction
|= Rm
;
13751 Rd
= inst
.operands
[0].reg
;
13752 Rs
= (inst
.operands
[1].present
13753 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13754 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13756 reject_bad_reg (Rd
);
13757 reject_bad_reg (Rs
);
13758 if (inst
.operands
[2].isreg
)
13759 reject_bad_reg (inst
.operands
[2].reg
);
13761 inst
.instruction
|= Rd
<< 8;
13762 inst
.instruction
|= Rs
<< 16;
13763 if (!inst
.operands
[2].isreg
)
13765 bfd_boolean narrow
;
13767 if ((inst
.instruction
& 0x00100000) != 0)
13768 narrow
= !in_pred_block ();
13770 narrow
= in_pred_block ();
13772 if (Rd
> 7 || Rs
> 7)
13775 if (inst
.size_req
== 4 || !unified_syntax
)
13778 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13779 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13782 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13783 relaxation, but it doesn't seem worth the hassle. */
13786 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13787 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13788 inst
.instruction
|= Rs
<< 3;
13789 inst
.instruction
|= Rd
;
13793 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13794 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13798 encode_thumb32_shifted_operand (2);
13804 if (warn_on_deprecated
13805 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13806 as_tsktsk (_("setend use is deprecated for ARMv8"));
13808 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13809 if (inst
.operands
[0].imm
)
13810 inst
.instruction
|= 0x8;
13816 if (!inst
.operands
[1].present
)
13817 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13819 if (unified_syntax
)
13821 bfd_boolean narrow
;
13824 switch (inst
.instruction
)
13827 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13829 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13831 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13833 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13837 if (THUMB_SETS_FLAGS (inst
.instruction
))
13838 narrow
= !in_pred_block ();
13840 narrow
= in_pred_block ();
13841 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13843 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13845 if (inst
.operands
[2].isreg
13846 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13847 || inst
.operands
[2].reg
> 7))
13849 if (inst
.size_req
== 4)
13852 reject_bad_reg (inst
.operands
[0].reg
);
13853 reject_bad_reg (inst
.operands
[1].reg
);
13857 if (inst
.operands
[2].isreg
)
13859 reject_bad_reg (inst
.operands
[2].reg
);
13860 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13861 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13862 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13863 inst
.instruction
|= inst
.operands
[2].reg
;
13865 /* PR 12854: Error on extraneous shifts. */
13866 constraint (inst
.operands
[2].shifted
,
13867 _("extraneous shift as part of operand to shift insn"));
13871 inst
.operands
[1].shifted
= 1;
13872 inst
.operands
[1].shift_kind
= shift_kind
;
13873 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13874 ? T_MNEM_movs
: T_MNEM_mov
);
13875 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13876 encode_thumb32_shifted_operand (1);
13877 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13878 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13883 if (inst
.operands
[2].isreg
)
13885 switch (shift_kind
)
13887 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13888 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13889 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13890 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13894 inst
.instruction
|= inst
.operands
[0].reg
;
13895 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13897 /* PR 12854: Error on extraneous shifts. */
13898 constraint (inst
.operands
[2].shifted
,
13899 _("extraneous shift as part of operand to shift insn"));
13903 switch (shift_kind
)
13905 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13906 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13907 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13910 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13911 inst
.instruction
|= inst
.operands
[0].reg
;
13912 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13918 constraint (inst
.operands
[0].reg
> 7
13919 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13920 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13922 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13924 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13925 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13926 _("source1 and dest must be same register"));
13928 switch (inst
.instruction
)
13930 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13931 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13932 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13933 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13937 inst
.instruction
|= inst
.operands
[0].reg
;
13938 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13940 /* PR 12854: Error on extraneous shifts. */
13941 constraint (inst
.operands
[2].shifted
,
13942 _("extraneous shift as part of operand to shift insn"));
13946 switch (inst
.instruction
)
13948 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13949 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13950 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13951 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13954 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13955 inst
.instruction
|= inst
.operands
[0].reg
;
13956 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13964 unsigned Rd
, Rn
, Rm
;
13966 Rd
= inst
.operands
[0].reg
;
13967 Rn
= inst
.operands
[1].reg
;
13968 Rm
= inst
.operands
[2].reg
;
13970 reject_bad_reg (Rd
);
13971 reject_bad_reg (Rn
);
13972 reject_bad_reg (Rm
);
13974 inst
.instruction
|= Rd
<< 8;
13975 inst
.instruction
|= Rn
<< 16;
13976 inst
.instruction
|= Rm
;
13982 unsigned Rd
, Rn
, Rm
;
13984 Rd
= inst
.operands
[0].reg
;
13985 Rm
= inst
.operands
[1].reg
;
13986 Rn
= inst
.operands
[2].reg
;
13988 reject_bad_reg (Rd
);
13989 reject_bad_reg (Rn
);
13990 reject_bad_reg (Rm
);
13992 inst
.instruction
|= Rd
<< 8;
13993 inst
.instruction
|= Rn
<< 16;
13994 inst
.instruction
|= Rm
;
14000 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14001 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14002 _("SMC is not permitted on this architecture"));
14003 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14004 _("expression too complex"));
14005 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14007 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14008 inst
.instruction
|= (value
& 0x000f) << 16;
14010 /* PR gas/15623: SMC instructions must be last in an IT block. */
14011 set_pred_insn_type_last ();
14017 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14019 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14020 inst
.instruction
|= (value
& 0x0fff);
14021 inst
.instruction
|= (value
& 0xf000) << 4;
14025 do_t_ssat_usat (int bias
)
14029 Rd
= inst
.operands
[0].reg
;
14030 Rn
= inst
.operands
[2].reg
;
14032 reject_bad_reg (Rd
);
14033 reject_bad_reg (Rn
);
14035 inst
.instruction
|= Rd
<< 8;
14036 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14037 inst
.instruction
|= Rn
<< 16;
14039 if (inst
.operands
[3].present
)
14041 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14043 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14045 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14046 _("expression too complex"));
14048 if (shift_amount
!= 0)
14050 constraint (shift_amount
> 31,
14051 _("shift expression is too large"));
14053 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14054 inst
.instruction
|= 0x00200000; /* sh bit. */
14056 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14057 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14065 do_t_ssat_usat (1);
14073 Rd
= inst
.operands
[0].reg
;
14074 Rn
= inst
.operands
[2].reg
;
14076 reject_bad_reg (Rd
);
14077 reject_bad_reg (Rn
);
14079 inst
.instruction
|= Rd
<< 8;
14080 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14081 inst
.instruction
|= Rn
<< 16;
14087 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14088 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14089 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14090 || inst
.operands
[2].negative
,
14093 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14095 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14096 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14097 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14098 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14104 if (!inst
.operands
[2].present
)
14105 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14107 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14108 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14109 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14112 inst
.instruction
|= inst
.operands
[0].reg
;
14113 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14114 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14115 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14121 unsigned Rd
, Rn
, Rm
;
14123 Rd
= inst
.operands
[0].reg
;
14124 Rn
= inst
.operands
[1].reg
;
14125 Rm
= inst
.operands
[2].reg
;
14127 reject_bad_reg (Rd
);
14128 reject_bad_reg (Rn
);
14129 reject_bad_reg (Rm
);
14131 inst
.instruction
|= Rd
<< 8;
14132 inst
.instruction
|= Rn
<< 16;
14133 inst
.instruction
|= Rm
;
14134 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14142 Rd
= inst
.operands
[0].reg
;
14143 Rm
= inst
.operands
[1].reg
;
14145 reject_bad_reg (Rd
);
14146 reject_bad_reg (Rm
);
14148 if (inst
.instruction
<= 0xffff
14149 && inst
.size_req
!= 4
14150 && Rd
<= 7 && Rm
<= 7
14151 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14153 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14154 inst
.instruction
|= Rd
;
14155 inst
.instruction
|= Rm
<< 3;
14157 else if (unified_syntax
)
14159 if (inst
.instruction
<= 0xffff)
14160 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14161 inst
.instruction
|= Rd
<< 8;
14162 inst
.instruction
|= Rm
;
14163 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14167 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14168 _("Thumb encoding does not support rotation"));
14169 constraint (1, BAD_HIREG
);
14176 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14185 half
= (inst
.instruction
& 0x10) != 0;
14186 set_pred_insn_type_last ();
14187 constraint (inst
.operands
[0].immisreg
,
14188 _("instruction requires register index"));
14190 Rn
= inst
.operands
[0].reg
;
14191 Rm
= inst
.operands
[0].imm
;
14193 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14194 constraint (Rn
== REG_SP
, BAD_SP
);
14195 reject_bad_reg (Rm
);
14197 constraint (!half
&& inst
.operands
[0].shifted
,
14198 _("instruction does not allow shifted index"));
14199 inst
.instruction
|= (Rn
<< 16) | Rm
;
14205 if (!inst
.operands
[0].present
)
14206 inst
.operands
[0].imm
= 0;
14208 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14210 constraint (inst
.size_req
== 2,
14211 _("immediate value out of range"));
14212 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14213 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14214 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14218 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14219 inst
.instruction
|= inst
.operands
[0].imm
;
14222 set_pred_insn_type (NEUTRAL_IT_INSN
);
14229 do_t_ssat_usat (0);
14237 Rd
= inst
.operands
[0].reg
;
14238 Rn
= inst
.operands
[2].reg
;
14240 reject_bad_reg (Rd
);
14241 reject_bad_reg (Rn
);
14243 inst
.instruction
|= Rd
<< 8;
14244 inst
.instruction
|= inst
.operands
[1].imm
;
14245 inst
.instruction
|= Rn
<< 16;
14248 /* Checking the range of the branch offset (VAL) with NBITS bits
14249 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14251 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14253 gas_assert (nbits
> 0 && nbits
<= 32);
14256 int cmp
= (1 << (nbits
- 1));
14257 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14262 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14268 /* For branches in Armv8.1-M Mainline. */
14270 do_t_branch_future (void)
14272 unsigned long insn
= inst
.instruction
;
14274 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14275 if (inst
.operands
[0].hasreloc
== 0)
14277 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14278 as_bad (BAD_BRANCH_OFF
);
14280 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14284 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14285 inst
.relocs
[0].pc_rel
= 1;
14291 if (inst
.operands
[1].hasreloc
== 0)
14293 int val
= inst
.operands
[1].imm
;
14294 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14295 as_bad (BAD_BRANCH_OFF
);
14297 int immA
= (val
& 0x0001f000) >> 12;
14298 int immB
= (val
& 0x00000ffc) >> 2;
14299 int immC
= (val
& 0x00000002) >> 1;
14300 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14304 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14305 inst
.relocs
[1].pc_rel
= 1;
14310 if (inst
.operands
[1].hasreloc
== 0)
14312 int val
= inst
.operands
[1].imm
;
14313 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14314 as_bad (BAD_BRANCH_OFF
);
14316 int immA
= (val
& 0x0007f000) >> 12;
14317 int immB
= (val
& 0x00000ffc) >> 2;
14318 int immC
= (val
& 0x00000002) >> 1;
14319 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14323 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14324 inst
.relocs
[1].pc_rel
= 1;
14328 case T_MNEM_bfcsel
:
14330 if (inst
.operands
[1].hasreloc
== 0)
14332 int val
= inst
.operands
[1].imm
;
14333 int immA
= (val
& 0x00001000) >> 12;
14334 int immB
= (val
& 0x00000ffc) >> 2;
14335 int immC
= (val
& 0x00000002) >> 1;
14336 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14340 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14341 inst
.relocs
[1].pc_rel
= 1;
14345 if (inst
.operands
[2].hasreloc
== 0)
14347 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14348 int val2
= inst
.operands
[2].imm
;
14349 int val0
= inst
.operands
[0].imm
& 0x1f;
14350 int diff
= val2
- val0
;
14352 inst
.instruction
|= 1 << 17; /* T bit. */
14353 else if (diff
!= 2)
14354 as_bad (_("out of range label-relative fixup value"));
14358 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14359 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14360 inst
.relocs
[2].pc_rel
= 1;
14364 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14365 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14370 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14377 /* Helper function for do_t_loloop to handle relocations. */
14379 v8_1_loop_reloc (int is_le
)
14381 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14383 int value
= inst
.relocs
[0].exp
.X_add_number
;
14384 value
= (is_le
) ? -value
: value
;
14386 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14387 as_bad (BAD_BRANCH_OFF
);
14391 immh
= (value
& 0x00000ffc) >> 2;
14392 imml
= (value
& 0x00000002) >> 1;
14394 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14398 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14399 inst
.relocs
[0].pc_rel
= 1;
14403 /* For shifts with four operands in MVE. */
14405 do_mve_scalar_shift1 (void)
14407 unsigned int value
= inst
.operands
[2].imm
;
14409 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14410 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14412 /* Setting the bit for saturation. */
14413 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14415 /* Assuming Rm is already checked not to be 11x1. */
14416 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14417 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14418 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14421 /* For shifts in MVE. */
14423 do_mve_scalar_shift (void)
14425 if (!inst
.operands
[2].present
)
14427 inst
.operands
[2] = inst
.operands
[1];
14428 inst
.operands
[1].reg
= 0xf;
14431 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14432 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14434 if (inst
.operands
[2].isreg
)
14436 /* Assuming Rm is already checked not to be 11x1. */
14437 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14438 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14439 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14443 /* Assuming imm is already checked as [1,32]. */
14444 unsigned int value
= inst
.operands
[2].imm
;
14445 inst
.instruction
|= (value
& 0x1c) << 10;
14446 inst
.instruction
|= (value
& 0x03) << 6;
14447 /* Change last 4 bits from 0xd to 0xf. */
14448 inst
.instruction
|= 0x2;
14452 /* MVE instruction encoder helpers. */
14453 #define M_MNEM_vabav 0xee800f01
14454 #define M_MNEM_vmladav 0xeef00e00
14455 #define M_MNEM_vmladava 0xeef00e20
14456 #define M_MNEM_vmladavx 0xeef01e00
14457 #define M_MNEM_vmladavax 0xeef01e20
14458 #define M_MNEM_vmlsdav 0xeef00e01
14459 #define M_MNEM_vmlsdava 0xeef00e21
14460 #define M_MNEM_vmlsdavx 0xeef01e01
14461 #define M_MNEM_vmlsdavax 0xeef01e21
14462 #define M_MNEM_vmullt 0xee011e00
14463 #define M_MNEM_vmullb 0xee010e00
14464 #define M_MNEM_vctp 0xf000e801
14465 #define M_MNEM_vst20 0xfc801e00
14466 #define M_MNEM_vst21 0xfc801e20
14467 #define M_MNEM_vst40 0xfc801e01
14468 #define M_MNEM_vst41 0xfc801e21
14469 #define M_MNEM_vst42 0xfc801e41
14470 #define M_MNEM_vst43 0xfc801e61
14471 #define M_MNEM_vld20 0xfc901e00
14472 #define M_MNEM_vld21 0xfc901e20
14473 #define M_MNEM_vld40 0xfc901e01
14474 #define M_MNEM_vld41 0xfc901e21
14475 #define M_MNEM_vld42 0xfc901e41
14476 #define M_MNEM_vld43 0xfc901e61
14477 #define M_MNEM_vstrb 0xec000e00
14478 #define M_MNEM_vstrh 0xec000e10
14479 #define M_MNEM_vstrw 0xec000e40
14480 #define M_MNEM_vstrd 0xec000e50
14481 #define M_MNEM_vldrb 0xec100e00
14482 #define M_MNEM_vldrh 0xec100e10
14483 #define M_MNEM_vldrw 0xec100e40
14484 #define M_MNEM_vldrd 0xec100e50
14485 #define M_MNEM_vmovlt 0xeea01f40
14486 #define M_MNEM_vmovlb 0xeea00f40
14487 #define M_MNEM_vmovnt 0xfe311e81
14488 #define M_MNEM_vmovnb 0xfe310e81
14489 #define M_MNEM_vadc 0xee300f00
14490 #define M_MNEM_vadci 0xee301f00
14491 #define M_MNEM_vbrsr 0xfe011e60
14492 #define M_MNEM_vaddlv 0xee890f00
14493 #define M_MNEM_vaddlva 0xee890f20
14494 #define M_MNEM_vaddv 0xeef10f00
14495 #define M_MNEM_vaddva 0xeef10f20
14496 #define M_MNEM_vddup 0xee011f6e
14497 #define M_MNEM_vdwdup 0xee011f60
14498 #define M_MNEM_vidup 0xee010f6e
14499 #define M_MNEM_viwdup 0xee010f60
14500 #define M_MNEM_vmaxv 0xeee20f00
14501 #define M_MNEM_vmaxav 0xeee00f00
14502 #define M_MNEM_vminv 0xeee20f80
14503 #define M_MNEM_vminav 0xeee00f80
14504 #define M_MNEM_vmlaldav 0xee800e00
14505 #define M_MNEM_vmlaldava 0xee800e20
14506 #define M_MNEM_vmlaldavx 0xee801e00
14507 #define M_MNEM_vmlaldavax 0xee801e20
14508 #define M_MNEM_vmlsldav 0xee800e01
14509 #define M_MNEM_vmlsldava 0xee800e21
14510 #define M_MNEM_vmlsldavx 0xee801e01
14511 #define M_MNEM_vmlsldavax 0xee801e21
14512 #define M_MNEM_vrmlaldavhx 0xee801f00
14513 #define M_MNEM_vrmlaldavhax 0xee801f20
14514 #define M_MNEM_vrmlsldavh 0xfe800e01
14515 #define M_MNEM_vrmlsldavha 0xfe800e21
14516 #define M_MNEM_vrmlsldavhx 0xfe801e01
14517 #define M_MNEM_vrmlsldavhax 0xfe801e21
14518 #define M_MNEM_vqmovnt 0xee331e01
14519 #define M_MNEM_vqmovnb 0xee330e01
14520 #define M_MNEM_vqmovunt 0xee311e81
14521 #define M_MNEM_vqmovunb 0xee310e81
14522 #define M_MNEM_vshrnt 0xee801fc1
14523 #define M_MNEM_vshrnb 0xee800fc1
14524 #define M_MNEM_vrshrnt 0xfe801fc1
14525 #define M_MNEM_vqshrnt 0xee801f40
14526 #define M_MNEM_vqshrnb 0xee800f40
14527 #define M_MNEM_vqshrunt 0xee801fc0
14528 #define M_MNEM_vqshrunb 0xee800fc0
14529 #define M_MNEM_vrshrnb 0xfe800fc1
14530 #define M_MNEM_vqrshrnt 0xee801f41
14531 #define M_MNEM_vqrshrnb 0xee800f41
14532 #define M_MNEM_vqrshrunt 0xfe801fc0
14533 #define M_MNEM_vqrshrunb 0xfe800fc0
14535 /* Bfloat16 instruction encoder helpers. */
14536 #define B_MNEM_vfmat 0xfc300850
14537 #define B_MNEM_vfmab 0xfc300810
14539 /* Neon instruction encoder helpers. */
14541 /* Encodings for the different types for various Neon opcodes. */
14543 /* An "invalid" code for the following tables. */
14546 struct neon_tab_entry
14549 unsigned float_or_poly
;
14550 unsigned scalar_or_imm
;
14553 /* Map overloaded Neon opcodes to their respective encodings. */
14554 #define NEON_ENC_TAB \
14555 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14556 X(vabdl, 0x0800700, N_INV, N_INV), \
14557 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14558 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14559 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14560 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14561 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14562 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14563 X(vaddl, 0x0800000, N_INV, N_INV), \
14564 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14565 X(vsubl, 0x0800200, N_INV, N_INV), \
14566 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14567 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14568 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14569 /* Register variants of the following two instructions are encoded as
14570 vcge / vcgt with the operands reversed. */ \
14571 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14572 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14573 X(vfma, N_INV, 0x0000c10, N_INV), \
14574 X(vfms, N_INV, 0x0200c10, N_INV), \
14575 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14576 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14577 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14578 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14579 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14580 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14581 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14582 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14583 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14584 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14585 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14586 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14587 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14588 X(vshl, 0x0000400, N_INV, 0x0800510), \
14589 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14590 X(vand, 0x0000110, N_INV, 0x0800030), \
14591 X(vbic, 0x0100110, N_INV, 0x0800030), \
14592 X(veor, 0x1000110, N_INV, N_INV), \
14593 X(vorn, 0x0300110, N_INV, 0x0800010), \
14594 X(vorr, 0x0200110, N_INV, 0x0800010), \
14595 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14596 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14597 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14598 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14599 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14600 X(vst1, 0x0000000, 0x0800000, N_INV), \
14601 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14602 X(vst2, 0x0000100, 0x0800100, N_INV), \
14603 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14604 X(vst3, 0x0000200, 0x0800200, N_INV), \
14605 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14606 X(vst4, 0x0000300, 0x0800300, N_INV), \
14607 X(vmovn, 0x1b20200, N_INV, N_INV), \
14608 X(vtrn, 0x1b20080, N_INV, N_INV), \
14609 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14610 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14611 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14612 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14613 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14614 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14615 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14616 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14617 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14618 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14619 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14620 X(vseleq, 0xe000a00, N_INV, N_INV), \
14621 X(vselvs, 0xe100a00, N_INV, N_INV), \
14622 X(vselge, 0xe200a00, N_INV, N_INV), \
14623 X(vselgt, 0xe300a00, N_INV, N_INV), \
14624 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14625 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14626 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14627 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14628 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14629 X(aes, 0x3b00300, N_INV, N_INV), \
14630 X(sha3op, 0x2000c00, N_INV, N_INV), \
14631 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14632 X(sha2op, 0x3ba0380, N_INV, N_INV)
14636 #define X(OPC,I,F,S) N_MNEM_##OPC
14641 static const struct neon_tab_entry neon_enc_tab
[] =
14643 #define X(OPC,I,F,S) { (I), (F), (S) }
14648 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14649 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14650 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14651 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14652 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14653 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14654 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14655 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14656 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14657 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14658 #define NEON_ENC_SINGLE_(X) \
14659 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14660 #define NEON_ENC_DOUBLE_(X) \
14661 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14662 #define NEON_ENC_FPV8_(X) \
14663 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14665 #define NEON_ENCODE(type, inst) \
14668 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14669 inst.is_neon = 1; \
14673 #define check_neon_suffixes \
14676 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14678 as_bad (_("invalid neon suffix for non neon instruction")); \
14684 /* Define shapes for instruction operands. The following mnemonic characters
14685 are used in this table:
14687 F - VFP S<n> register
14688 D - Neon D<n> register
14689 Q - Neon Q<n> register
14693 L - D<n> register list
14695 This table is used to generate various data:
14696 - enumerations of the form NS_DDR to be used as arguments to
14698 - a table classifying shapes into single, double, quad, mixed.
14699 - a table used to drive neon_select_shape. */
14701 #define NEON_SHAPE_DEF \
14702 X(4, (R, R, Q, Q), QUAD), \
14703 X(4, (Q, R, R, I), QUAD), \
14704 X(4, (R, R, S, S), QUAD), \
14705 X(4, (S, S, R, R), QUAD), \
14706 X(3, (Q, R, I), QUAD), \
14707 X(3, (I, Q, Q), QUAD), \
14708 X(3, (I, Q, R), QUAD), \
14709 X(3, (R, Q, Q), QUAD), \
14710 X(3, (D, D, D), DOUBLE), \
14711 X(3, (Q, Q, Q), QUAD), \
14712 X(3, (D, D, I), DOUBLE), \
14713 X(3, (Q, Q, I), QUAD), \
14714 X(3, (D, D, S), DOUBLE), \
14715 X(3, (Q, Q, S), QUAD), \
14716 X(3, (Q, Q, R), QUAD), \
14717 X(3, (R, R, Q), QUAD), \
14718 X(2, (R, Q), QUAD), \
14719 X(2, (D, D), DOUBLE), \
14720 X(2, (Q, Q), QUAD), \
14721 X(2, (D, S), DOUBLE), \
14722 X(2, (Q, S), QUAD), \
14723 X(2, (D, R), DOUBLE), \
14724 X(2, (Q, R), QUAD), \
14725 X(2, (D, I), DOUBLE), \
14726 X(2, (Q, I), QUAD), \
14727 X(3, (D, L, D), DOUBLE), \
14728 X(2, (D, Q), MIXED), \
14729 X(2, (Q, D), MIXED), \
14730 X(3, (D, Q, I), MIXED), \
14731 X(3, (Q, D, I), MIXED), \
14732 X(3, (Q, D, D), MIXED), \
14733 X(3, (D, Q, Q), MIXED), \
14734 X(3, (Q, Q, D), MIXED), \
14735 X(3, (Q, D, S), MIXED), \
14736 X(3, (D, Q, S), MIXED), \
14737 X(4, (D, D, D, I), DOUBLE), \
14738 X(4, (Q, Q, Q, I), QUAD), \
14739 X(4, (D, D, S, I), DOUBLE), \
14740 X(4, (Q, Q, S, I), QUAD), \
14741 X(2, (F, F), SINGLE), \
14742 X(3, (F, F, F), SINGLE), \
14743 X(2, (F, I), SINGLE), \
14744 X(2, (F, D), MIXED), \
14745 X(2, (D, F), MIXED), \
14746 X(3, (F, F, I), MIXED), \
14747 X(4, (R, R, F, F), SINGLE), \
14748 X(4, (F, F, R, R), SINGLE), \
14749 X(3, (D, R, R), DOUBLE), \
14750 X(3, (R, R, D), DOUBLE), \
14751 X(2, (S, R), SINGLE), \
14752 X(2, (R, S), SINGLE), \
14753 X(2, (F, R), SINGLE), \
14754 X(2, (R, F), SINGLE), \
14755 /* Used for MVE tail predicated loop instructions. */\
14756 X(2, (R, R), QUAD), \
14757 /* Half float shape supported so far. */\
14758 X (2, (H, D), MIXED), \
14759 X (2, (D, H), MIXED), \
14760 X (2, (H, F), MIXED), \
14761 X (2, (F, H), MIXED), \
14762 X (2, (H, H), HALF), \
14763 X (2, (H, R), HALF), \
14764 X (2, (R, H), HALF), \
14765 X (2, (H, I), HALF), \
14766 X (3, (H, H, H), HALF), \
14767 X (3, (H, F, I), MIXED), \
14768 X (3, (F, H, I), MIXED), \
14769 X (3, (D, H, H), MIXED), \
14770 X (3, (D, H, S), MIXED)
14772 #define S2(A,B) NS_##A##B
14773 #define S3(A,B,C) NS_##A##B##C
14774 #define S4(A,B,C,D) NS_##A##B##C##D
14776 #define X(N, L, C) S##N L
14789 enum neon_shape_class
14798 #define X(N, L, C) SC_##C
14800 static enum neon_shape_class neon_shape_class
[] =
14819 /* Register widths of above. */
14820 static unsigned neon_shape_el_size
[] =
14832 struct neon_shape_info
14835 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14838 #define S2(A,B) { SE_##A, SE_##B }
14839 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14840 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14842 #define X(N, L, C) { N, S##N L }
14844 static struct neon_shape_info neon_shape_tab
[] =
14854 /* Bit masks used in type checking given instructions.
14855 'N_EQK' means the type must be the same as (or based on in some way) the key
14856 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14857 set, various other bits can be set as well in order to modify the meaning of
14858 the type constraint. */
14860 enum neon_type_mask
14884 N_BF16
= 0x0400000,
14885 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14886 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14887 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14888 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14889 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14890 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14891 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14892 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14893 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14894 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14895 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14897 N_MAX_NONSPECIAL
= N_P64
14900 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14902 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14903 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14904 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14905 #define N_S_32 (N_S8 | N_S16 | N_S32)
14906 #define N_F_16_32 (N_F16 | N_F32)
14907 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14908 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14909 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14910 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14911 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14912 #define N_F_MVE (N_F16 | N_F32)
14913 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14915 /* Pass this as the first type argument to neon_check_type to ignore types
14917 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14919 /* Select a "shape" for the current instruction (describing register types or
14920 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14921 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14922 function of operand parsing, so this function doesn't need to be called.
14923 Shapes should be listed in order of decreasing length. */
14925 static enum neon_shape
14926 neon_select_shape (enum neon_shape shape
, ...)
14929 enum neon_shape first_shape
= shape
;
14931 /* Fix missing optional operands. FIXME: we don't know at this point how
14932 many arguments we should have, so this makes the assumption that we have
14933 > 1. This is true of all current Neon opcodes, I think, but may not be
14934 true in the future. */
14935 if (!inst
.operands
[1].present
)
14936 inst
.operands
[1] = inst
.operands
[0];
14938 va_start (ap
, shape
);
14940 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14945 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14947 if (!inst
.operands
[j
].present
)
14953 switch (neon_shape_tab
[shape
].el
[j
])
14955 /* If a .f16, .16, .u16, .s16 type specifier is given over
14956 a VFP single precision register operand, it's essentially
14957 means only half of the register is used.
14959 If the type specifier is given after the mnemonics, the
14960 information is stored in inst.vectype. If the type specifier
14961 is given after register operand, the information is stored
14962 in inst.operands[].vectype.
14964 When there is only one type specifier, and all the register
14965 operands are the same type of hardware register, the type
14966 specifier applies to all register operands.
14968 If no type specifier is given, the shape is inferred from
14969 operand information.
14972 vadd.f16 s0, s1, s2: NS_HHH
14973 vabs.f16 s0, s1: NS_HH
14974 vmov.f16 s0, r1: NS_HR
14975 vmov.f16 r0, s1: NS_RH
14976 vcvt.f16 r0, s1: NS_RH
14977 vcvt.f16.s32 s2, s2, #29: NS_HFI
14978 vcvt.f16.s32 s2, s2: NS_HF
14981 if (!(inst
.operands
[j
].isreg
14982 && inst
.operands
[j
].isvec
14983 && inst
.operands
[j
].issingle
14984 && !inst
.operands
[j
].isquad
14985 && ((inst
.vectype
.elems
== 1
14986 && inst
.vectype
.el
[0].size
== 16)
14987 || (inst
.vectype
.elems
> 1
14988 && inst
.vectype
.el
[j
].size
== 16)
14989 || (inst
.vectype
.elems
== 0
14990 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14991 && inst
.operands
[j
].vectype
.size
== 16))))
14996 if (!(inst
.operands
[j
].isreg
14997 && inst
.operands
[j
].isvec
14998 && inst
.operands
[j
].issingle
14999 && !inst
.operands
[j
].isquad
15000 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15001 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15002 || (inst
.vectype
.elems
== 0
15003 && (inst
.operands
[j
].vectype
.size
== 32
15004 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15009 if (!(inst
.operands
[j
].isreg
15010 && inst
.operands
[j
].isvec
15011 && !inst
.operands
[j
].isquad
15012 && !inst
.operands
[j
].issingle
))
15017 if (!(inst
.operands
[j
].isreg
15018 && !inst
.operands
[j
].isvec
))
15023 if (!(inst
.operands
[j
].isreg
15024 && inst
.operands
[j
].isvec
15025 && inst
.operands
[j
].isquad
15026 && !inst
.operands
[j
].issingle
))
15031 if (!(!inst
.operands
[j
].isreg
15032 && !inst
.operands
[j
].isscalar
))
15037 if (!(!inst
.operands
[j
].isreg
15038 && inst
.operands
[j
].isscalar
))
15048 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15049 /* We've matched all the entries in the shape table, and we don't
15050 have any left over operands which have not been matched. */
15056 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15057 first_error (_("invalid instruction shape"));
15062 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15063 means the Q bit should be set). */
15066 neon_quad (enum neon_shape shape
)
15068 return neon_shape_class
[shape
] == SC_QUAD
;
15072 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15075 /* Allow modification to be made to types which are constrained to be
15076 based on the key element, based on bits set alongside N_EQK. */
15077 if ((typebits
& N_EQK
) != 0)
15079 if ((typebits
& N_HLF
) != 0)
15081 else if ((typebits
& N_DBL
) != 0)
15083 if ((typebits
& N_SGN
) != 0)
15084 *g_type
= NT_signed
;
15085 else if ((typebits
& N_UNS
) != 0)
15086 *g_type
= NT_unsigned
;
15087 else if ((typebits
& N_INT
) != 0)
15088 *g_type
= NT_integer
;
15089 else if ((typebits
& N_FLT
) != 0)
15090 *g_type
= NT_float
;
15091 else if ((typebits
& N_SIZ
) != 0)
15092 *g_type
= NT_untyped
;
15096 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15097 operand type, i.e. the single type specified in a Neon instruction when it
15098 is the only one given. */
15100 static struct neon_type_el
15101 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15103 struct neon_type_el dest
= *key
;
15105 gas_assert ((thisarg
& N_EQK
) != 0);
15107 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15112 /* Convert Neon type and size into compact bitmask representation. */
15114 static enum neon_type_mask
15115 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15122 case 8: return N_8
;
15123 case 16: return N_16
;
15124 case 32: return N_32
;
15125 case 64: return N_64
;
15133 case 8: return N_I8
;
15134 case 16: return N_I16
;
15135 case 32: return N_I32
;
15136 case 64: return N_I64
;
15144 case 16: return N_F16
;
15145 case 32: return N_F32
;
15146 case 64: return N_F64
;
15154 case 8: return N_P8
;
15155 case 16: return N_P16
;
15156 case 64: return N_P64
;
15164 case 8: return N_S8
;
15165 case 16: return N_S16
;
15166 case 32: return N_S32
;
15167 case 64: return N_S64
;
15175 case 8: return N_U8
;
15176 case 16: return N_U16
;
15177 case 32: return N_U32
;
15178 case 64: return N_U64
;
15184 if (size
== 16) return N_BF16
;
15193 /* Convert compact Neon bitmask type representation to a type and size. Only
15194 handles the case where a single bit is set in the mask. */
15197 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15198 enum neon_type_mask mask
)
15200 if ((mask
& N_EQK
) != 0)
15203 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15205 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15208 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15210 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15215 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15217 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15218 *type
= NT_unsigned
;
15219 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15220 *type
= NT_integer
;
15221 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15222 *type
= NT_untyped
;
15223 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15225 else if ((mask
& (N_F_ALL
)) != 0)
15227 else if ((mask
& (N_BF16
)) != 0)
15235 /* Modify a bitmask of allowed types. This is only needed for type
15239 modify_types_allowed (unsigned allowed
, unsigned mods
)
15242 enum neon_el_type type
;
15248 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15250 if (el_type_of_type_chk (&type
, &size
,
15251 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15253 neon_modify_type_size (mods
, &type
, &size
);
15254 destmask
|= type_chk_of_el_type (type
, size
);
15261 /* Check type and return type classification.
15262 The manual states (paraphrase): If one datatype is given, it indicates the
15264 - the second operand, if there is one
15265 - the operand, if there is no second operand
15266 - the result, if there are no operands.
15267 This isn't quite good enough though, so we use a concept of a "key" datatype
15268 which is set on a per-instruction basis, which is the one which matters when
15269 only one data type is written.
15270 Note: this function has side-effects (e.g. filling in missing operands). All
15271 Neon instructions should call it before performing bit encoding. */
15273 static struct neon_type_el
15274 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15277 unsigned i
, pass
, key_el
= 0;
15278 unsigned types
[NEON_MAX_TYPE_ELS
];
15279 enum neon_el_type k_type
= NT_invtype
;
15280 unsigned k_size
= -1u;
15281 struct neon_type_el badtype
= {NT_invtype
, -1};
15282 unsigned key_allowed
= 0;
15284 /* Optional registers in Neon instructions are always (not) in operand 1.
15285 Fill in the missing operand here, if it was omitted. */
15286 if (els
> 1 && !inst
.operands
[1].present
)
15287 inst
.operands
[1] = inst
.operands
[0];
15289 /* Suck up all the varargs. */
15291 for (i
= 0; i
< els
; i
++)
15293 unsigned thisarg
= va_arg (ap
, unsigned);
15294 if (thisarg
== N_IGNORE_TYPE
)
15299 types
[i
] = thisarg
;
15300 if ((thisarg
& N_KEY
) != 0)
15305 if (inst
.vectype
.elems
> 0)
15306 for (i
= 0; i
< els
; i
++)
15307 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15309 first_error (_("types specified in both the mnemonic and operands"));
15313 /* Duplicate inst.vectype elements here as necessary.
15314 FIXME: No idea if this is exactly the same as the ARM assembler,
15315 particularly when an insn takes one register and one non-register
15317 if (inst
.vectype
.elems
== 1 && els
> 1)
15320 inst
.vectype
.elems
= els
;
15321 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15322 for (j
= 0; j
< els
; j
++)
15324 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15327 else if (inst
.vectype
.elems
== 0 && els
> 0)
15330 /* No types were given after the mnemonic, so look for types specified
15331 after each operand. We allow some flexibility here; as long as the
15332 "key" operand has a type, we can infer the others. */
15333 for (j
= 0; j
< els
; j
++)
15334 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15335 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15337 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15339 for (j
= 0; j
< els
; j
++)
15340 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15341 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15346 first_error (_("operand types can't be inferred"));
15350 else if (inst
.vectype
.elems
!= els
)
15352 first_error (_("type specifier has the wrong number of parts"));
15356 for (pass
= 0; pass
< 2; pass
++)
15358 for (i
= 0; i
< els
; i
++)
15360 unsigned thisarg
= types
[i
];
15361 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15362 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15363 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15364 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15366 /* Decay more-specific signed & unsigned types to sign-insensitive
15367 integer types if sign-specific variants are unavailable. */
15368 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15369 && (types_allowed
& N_SU_ALL
) == 0)
15370 g_type
= NT_integer
;
15372 /* If only untyped args are allowed, decay any more specific types to
15373 them. Some instructions only care about signs for some element
15374 sizes, so handle that properly. */
15375 if (((types_allowed
& N_UNT
) == 0)
15376 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15377 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15378 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15379 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15380 g_type
= NT_untyped
;
15384 if ((thisarg
& N_KEY
) != 0)
15388 key_allowed
= thisarg
& ~N_KEY
;
15390 /* Check architecture constraint on FP16 extension. */
15392 && k_type
== NT_float
15393 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15395 inst
.error
= _(BAD_FP16
);
15402 if ((thisarg
& N_VFP
) != 0)
15404 enum neon_shape_el regshape
;
15405 unsigned regwidth
, match
;
15407 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15410 first_error (_("invalid instruction shape"));
15413 regshape
= neon_shape_tab
[ns
].el
[i
];
15414 regwidth
= neon_shape_el_size
[regshape
];
15416 /* In VFP mode, operands must match register widths. If we
15417 have a key operand, use its width, else use the width of
15418 the current operand. */
15424 /* FP16 will use a single precision register. */
15425 if (regwidth
== 32 && match
== 16)
15427 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15431 inst
.error
= _(BAD_FP16
);
15436 if (regwidth
!= match
)
15438 first_error (_("operand size must match register width"));
15443 if ((thisarg
& N_EQK
) == 0)
15445 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15447 if ((given_type
& types_allowed
) == 0)
15449 first_error (BAD_SIMD_TYPE
);
15455 enum neon_el_type mod_k_type
= k_type
;
15456 unsigned mod_k_size
= k_size
;
15457 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15458 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15460 first_error (_("inconsistent types in Neon instruction"));
15468 return inst
.vectype
.el
[key_el
];
15471 /* Neon-style VFP instruction forwarding. */
15473 /* Thumb VFP instructions have 0xE in the condition field. */
15476 do_vfp_cond_or_thumb (void)
15481 inst
.instruction
|= 0xe0000000;
15483 inst
.instruction
|= inst
.cond
<< 28;
15486 /* Look up and encode a simple mnemonic, for use as a helper function for the
15487 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15488 etc. It is assumed that operand parsing has already been done, and that the
15489 operands are in the form expected by the given opcode (this isn't necessarily
15490 the same as the form in which they were parsed, hence some massaging must
15491 take place before this function is called).
15492 Checks current arch version against that in the looked-up opcode. */
15495 do_vfp_nsyn_opcode (const char *opname
)
15497 const struct asm_opcode
*opcode
;
15499 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15504 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15505 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15512 inst
.instruction
= opcode
->tvalue
;
15513 opcode
->tencode ();
15517 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15518 opcode
->aencode ();
15523 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15525 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15527 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15530 do_vfp_nsyn_opcode ("fadds");
15532 do_vfp_nsyn_opcode ("fsubs");
15534 /* ARMv8.2 fp16 instruction. */
15536 do_scalar_fp16_v82_encode ();
15541 do_vfp_nsyn_opcode ("faddd");
15543 do_vfp_nsyn_opcode ("fsubd");
15547 /* Check operand types to see if this is a VFP instruction, and if so call
15551 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15553 enum neon_shape rs
;
15554 struct neon_type_el et
;
15559 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15560 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15564 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15565 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15566 N_F_ALL
| N_KEY
| N_VFP
);
15573 if (et
.type
!= NT_invtype
)
15584 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15586 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15588 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15591 do_vfp_nsyn_opcode ("fmacs");
15593 do_vfp_nsyn_opcode ("fnmacs");
15595 /* ARMv8.2 fp16 instruction. */
15597 do_scalar_fp16_v82_encode ();
15602 do_vfp_nsyn_opcode ("fmacd");
15604 do_vfp_nsyn_opcode ("fnmacd");
15609 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15611 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15613 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15616 do_vfp_nsyn_opcode ("ffmas");
15618 do_vfp_nsyn_opcode ("ffnmas");
15620 /* ARMv8.2 fp16 instruction. */
15622 do_scalar_fp16_v82_encode ();
15627 do_vfp_nsyn_opcode ("ffmad");
15629 do_vfp_nsyn_opcode ("ffnmad");
15634 do_vfp_nsyn_mul (enum neon_shape rs
)
15636 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15638 do_vfp_nsyn_opcode ("fmuls");
15640 /* ARMv8.2 fp16 instruction. */
15642 do_scalar_fp16_v82_encode ();
15645 do_vfp_nsyn_opcode ("fmuld");
15649 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15651 int is_neg
= (inst
.instruction
& 0x80) != 0;
15652 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15654 if (rs
== NS_FF
|| rs
== NS_HH
)
15657 do_vfp_nsyn_opcode ("fnegs");
15659 do_vfp_nsyn_opcode ("fabss");
15661 /* ARMv8.2 fp16 instruction. */
15663 do_scalar_fp16_v82_encode ();
15668 do_vfp_nsyn_opcode ("fnegd");
15670 do_vfp_nsyn_opcode ("fabsd");
15674 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15675 insns belong to Neon, and are handled elsewhere. */
15678 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15680 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15684 do_vfp_nsyn_opcode ("fldmdbs");
15686 do_vfp_nsyn_opcode ("fldmias");
15691 do_vfp_nsyn_opcode ("fstmdbs");
15693 do_vfp_nsyn_opcode ("fstmias");
15698 do_vfp_nsyn_sqrt (void)
15700 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15701 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15703 if (rs
== NS_FF
|| rs
== NS_HH
)
15705 do_vfp_nsyn_opcode ("fsqrts");
15707 /* ARMv8.2 fp16 instruction. */
15709 do_scalar_fp16_v82_encode ();
15712 do_vfp_nsyn_opcode ("fsqrtd");
15716 do_vfp_nsyn_div (void)
15718 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15719 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15720 N_F_ALL
| N_KEY
| N_VFP
);
15722 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15724 do_vfp_nsyn_opcode ("fdivs");
15726 /* ARMv8.2 fp16 instruction. */
15728 do_scalar_fp16_v82_encode ();
15731 do_vfp_nsyn_opcode ("fdivd");
15735 do_vfp_nsyn_nmul (void)
15737 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15738 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15739 N_F_ALL
| N_KEY
| N_VFP
);
15741 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15743 NEON_ENCODE (SINGLE
, inst
);
15744 do_vfp_sp_dyadic ();
15746 /* ARMv8.2 fp16 instruction. */
15748 do_scalar_fp16_v82_encode ();
15752 NEON_ENCODE (DOUBLE
, inst
);
15753 do_vfp_dp_rd_rn_rm ();
15755 do_vfp_cond_or_thumb ();
15759 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15763 neon_logbits (unsigned x
)
15765 return ffs (x
) - 4;
15768 #define LOW4(R) ((R) & 0xf)
15769 #define HI1(R) (((R) >> 4) & 1)
15772 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15777 first_error (BAD_EL_TYPE
);
15780 switch (inst
.operands
[0].imm
)
15783 first_error (_("invalid condition"));
15805 /* only accept eq and ne. */
15806 if (inst
.operands
[0].imm
> 1)
15808 first_error (_("invalid condition"));
15811 return inst
.operands
[0].imm
;
15813 if (inst
.operands
[0].imm
== 0x2)
15815 else if (inst
.operands
[0].imm
== 0x8)
15819 first_error (_("invalid condition"));
15823 switch (inst
.operands
[0].imm
)
15826 first_error (_("invalid condition"));
15842 /* Should be unreachable. */
15846 /* For VCTP (create vector tail predicate) in MVE. */
15851 unsigned size
= 0x0;
15853 if (inst
.cond
> COND_ALWAYS
)
15854 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15856 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15858 /* This is a typical MVE instruction which has no type but have size 8, 16,
15859 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15860 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15861 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15862 dt
= inst
.vectype
.el
[0].size
;
15864 /* Setting this does not indicate an actual NEON instruction, but only
15865 indicates that the mnemonic accepts neon-style type suffixes. */
15879 first_error (_("Type is not allowed for this instruction"));
15881 inst
.instruction
|= size
<< 20;
15882 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15888 /* We are dealing with a vector predicated block. */
15889 if (inst
.operands
[0].present
)
15891 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15892 struct neon_type_el et
15893 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15896 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15898 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15900 if (et
.type
== NT_invtype
)
15903 if (et
.type
== NT_float
)
15905 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15907 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15908 inst
.instruction
|= (et
.size
== 16) << 28;
15909 inst
.instruction
|= 0x3 << 20;
15913 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15915 inst
.instruction
|= 1 << 28;
15916 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15919 if (inst
.operands
[2].isquad
)
15921 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15922 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15923 inst
.instruction
|= (fcond
& 0x2) >> 1;
15927 if (inst
.operands
[2].reg
== REG_SP
)
15928 as_tsktsk (MVE_BAD_SP
);
15929 inst
.instruction
|= 1 << 6;
15930 inst
.instruction
|= (fcond
& 0x2) << 4;
15931 inst
.instruction
|= inst
.operands
[2].reg
;
15933 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15934 inst
.instruction
|= (fcond
& 0x4) << 10;
15935 inst
.instruction
|= (fcond
& 0x1) << 7;
15938 set_pred_insn_type (VPT_INSN
);
15940 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15941 | ((inst
.instruction
& 0xe000) >> 13);
15942 now_pred
.warn_deprecated
= FALSE
;
15943 now_pred
.type
= VECTOR_PRED
;
15950 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15951 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15952 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15953 if (!inst
.operands
[2].present
)
15954 first_error (_("MVE vector or ARM register expected"));
15955 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15957 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15958 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15959 && inst
.operands
[1].isquad
)
15961 inst
.instruction
= N_MNEM_vcmp
;
15965 if (inst
.cond
> COND_ALWAYS
)
15966 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15968 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15970 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15971 struct neon_type_el et
15972 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15975 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15976 && !inst
.operands
[2].iszr
, BAD_PC
);
15978 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15980 inst
.instruction
= 0xee010f00;
15981 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15982 inst
.instruction
|= (fcond
& 0x4) << 10;
15983 inst
.instruction
|= (fcond
& 0x1) << 7;
15984 if (et
.type
== NT_float
)
15986 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15988 inst
.instruction
|= (et
.size
== 16) << 28;
15989 inst
.instruction
|= 0x3 << 20;
15993 inst
.instruction
|= 1 << 28;
15994 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15996 if (inst
.operands
[2].isquad
)
15998 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15999 inst
.instruction
|= (fcond
& 0x2) >> 1;
16000 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16004 if (inst
.operands
[2].reg
== REG_SP
)
16005 as_tsktsk (MVE_BAD_SP
);
16006 inst
.instruction
|= 1 << 6;
16007 inst
.instruction
|= (fcond
& 0x2) << 4;
16008 inst
.instruction
|= inst
.operands
[2].reg
;
16016 do_mve_vmaxa_vmina (void)
16018 if (inst
.cond
> COND_ALWAYS
)
16019 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16021 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16023 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16024 struct neon_type_el et
16025 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16027 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16028 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16029 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16030 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16031 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16036 do_mve_vfmas (void)
16038 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16039 struct neon_type_el et
16040 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16042 if (inst
.cond
> COND_ALWAYS
)
16043 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16045 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16047 if (inst
.operands
[2].reg
== REG_SP
)
16048 as_tsktsk (MVE_BAD_SP
);
16049 else if (inst
.operands
[2].reg
== REG_PC
)
16050 as_tsktsk (MVE_BAD_PC
);
16052 inst
.instruction
|= (et
.size
== 16) << 28;
16053 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16054 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16055 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16056 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16057 inst
.instruction
|= inst
.operands
[2].reg
;
16062 do_mve_viddup (void)
16064 if (inst
.cond
> COND_ALWAYS
)
16065 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16067 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16069 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16070 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16071 _("immediate must be either 1, 2, 4 or 8"));
16073 enum neon_shape rs
;
16074 struct neon_type_el et
;
16076 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16078 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16079 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16084 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16085 if (inst
.operands
[2].reg
== REG_SP
)
16086 as_tsktsk (MVE_BAD_SP
);
16087 else if (inst
.operands
[2].reg
== REG_PC
)
16088 first_error (BAD_PC
);
16090 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16091 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16092 Rm
= inst
.operands
[2].reg
>> 1;
16094 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16095 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16096 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16097 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16098 inst
.instruction
|= (imm
> 2) << 7;
16099 inst
.instruction
|= Rm
<< 1;
16100 inst
.instruction
|= (imm
== 2 || imm
== 8);
16105 do_mve_vmlas (void)
16107 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16108 struct neon_type_el et
16109 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16111 if (inst
.operands
[2].reg
== REG_PC
)
16112 as_tsktsk (MVE_BAD_PC
);
16113 else if (inst
.operands
[2].reg
== REG_SP
)
16114 as_tsktsk (MVE_BAD_SP
);
16116 if (inst
.cond
> COND_ALWAYS
)
16117 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16119 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16121 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16122 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16123 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16124 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16125 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16126 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16127 inst
.instruction
|= inst
.operands
[2].reg
;
16132 do_mve_vshll (void)
16134 struct neon_type_el et
16135 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16137 if (inst
.cond
> COND_ALWAYS
)
16138 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16140 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16142 int imm
= inst
.operands
[2].imm
;
16143 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16144 _("immediate value out of range"));
16146 if ((unsigned)imm
== et
.size
)
16148 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16149 inst
.instruction
|= 0x110001;
16153 inst
.instruction
|= (et
.size
+ imm
) << 16;
16154 inst
.instruction
|= 0x800140;
16157 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16158 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16159 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16160 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16161 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16166 do_mve_vshlc (void)
16168 if (inst
.cond
> COND_ALWAYS
)
16169 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16171 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16173 if (inst
.operands
[1].reg
== REG_PC
)
16174 as_tsktsk (MVE_BAD_PC
);
16175 else if (inst
.operands
[1].reg
== REG_SP
)
16176 as_tsktsk (MVE_BAD_SP
);
16178 int imm
= inst
.operands
[2].imm
;
16179 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16181 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16182 inst
.instruction
|= (imm
& 0x1f) << 16;
16183 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16184 inst
.instruction
|= inst
.operands
[1].reg
;
16189 do_mve_vshrn (void)
16192 switch (inst
.instruction
)
16194 case M_MNEM_vshrnt
:
16195 case M_MNEM_vshrnb
:
16196 case M_MNEM_vrshrnt
:
16197 case M_MNEM_vrshrnb
:
16198 types
= N_I16
| N_I32
;
16200 case M_MNEM_vqshrnt
:
16201 case M_MNEM_vqshrnb
:
16202 case M_MNEM_vqrshrnt
:
16203 case M_MNEM_vqrshrnb
:
16204 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16206 case M_MNEM_vqshrunt
:
16207 case M_MNEM_vqshrunb
:
16208 case M_MNEM_vqrshrunt
:
16209 case M_MNEM_vqrshrunb
:
16210 types
= N_S16
| N_S32
;
16216 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16218 if (inst
.cond
> COND_ALWAYS
)
16219 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16221 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16223 unsigned Qd
= inst
.operands
[0].reg
;
16224 unsigned Qm
= inst
.operands
[1].reg
;
16225 unsigned imm
= inst
.operands
[2].imm
;
16226 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16228 ? _("immediate operand expected in the range [1,8]")
16229 : _("immediate operand expected in the range [1,16]"));
16231 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16232 inst
.instruction
|= HI1 (Qd
) << 22;
16233 inst
.instruction
|= (et
.size
- imm
) << 16;
16234 inst
.instruction
|= LOW4 (Qd
) << 12;
16235 inst
.instruction
|= HI1 (Qm
) << 5;
16236 inst
.instruction
|= LOW4 (Qm
);
16241 do_mve_vqmovn (void)
16243 struct neon_type_el et
;
16244 if (inst
.instruction
== M_MNEM_vqmovnt
16245 || inst
.instruction
== M_MNEM_vqmovnb
)
16246 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16247 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16249 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16251 if (inst
.cond
> COND_ALWAYS
)
16252 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16254 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16256 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16257 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16258 inst
.instruction
|= (et
.size
== 32) << 18;
16259 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16260 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16261 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16266 do_mve_vpsel (void)
16268 neon_select_shape (NS_QQQ
, NS_NULL
);
16270 if (inst
.cond
> COND_ALWAYS
)
16271 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16273 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16275 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16276 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16277 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16278 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16279 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16280 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16285 do_mve_vpnot (void)
16287 if (inst
.cond
> COND_ALWAYS
)
16288 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16290 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16294 do_mve_vmaxnma_vminnma (void)
16296 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16297 struct neon_type_el et
16298 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16300 if (inst
.cond
> COND_ALWAYS
)
16301 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16303 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16305 inst
.instruction
|= (et
.size
== 16) << 28;
16306 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16307 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16308 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16309 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16314 do_mve_vcmul (void)
16316 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16317 struct neon_type_el et
16318 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16320 if (inst
.cond
> COND_ALWAYS
)
16321 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16323 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16325 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16326 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16327 _("immediate out of range"));
16329 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16330 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16331 as_tsktsk (BAD_MVE_SRCDEST
);
16333 inst
.instruction
|= (et
.size
== 32) << 28;
16334 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16335 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16336 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16337 inst
.instruction
|= (rot
> 90) << 12;
16338 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16339 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16340 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16341 inst
.instruction
|= (rot
== 90 || rot
== 270);
16345 /* To handle the Low Overhead Loop instructions
16346 in Armv8.1-M Mainline and MVE. */
16350 unsigned long insn
= inst
.instruction
;
16352 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16354 if (insn
== T_MNEM_lctp
)
16357 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16359 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16361 struct neon_type_el et
16362 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16363 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16370 constraint (!inst
.operands
[0].present
,
16372 /* fall through. */
16375 if (!inst
.operands
[0].present
)
16376 inst
.instruction
|= 1 << 21;
16378 v8_1_loop_reloc (TRUE
);
16383 v8_1_loop_reloc (FALSE
);
16384 /* fall through. */
16387 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16389 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16390 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16391 else if (inst
.operands
[1].reg
== REG_PC
)
16392 as_tsktsk (MVE_BAD_PC
);
16393 if (inst
.operands
[1].reg
== REG_SP
)
16394 as_tsktsk (MVE_BAD_SP
);
16396 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16406 do_vfp_nsyn_cmp (void)
16408 enum neon_shape rs
;
16409 if (!inst
.operands
[0].isreg
)
16416 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16417 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16421 if (inst
.operands
[1].isreg
)
16423 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16424 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16426 if (rs
== NS_FF
|| rs
== NS_HH
)
16428 NEON_ENCODE (SINGLE
, inst
);
16429 do_vfp_sp_monadic ();
16433 NEON_ENCODE (DOUBLE
, inst
);
16434 do_vfp_dp_rd_rm ();
16439 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16440 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16442 switch (inst
.instruction
& 0x0fffffff)
16445 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16448 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16454 if (rs
== NS_FI
|| rs
== NS_HI
)
16456 NEON_ENCODE (SINGLE
, inst
);
16457 do_vfp_sp_compare_z ();
16461 NEON_ENCODE (DOUBLE
, inst
);
16465 do_vfp_cond_or_thumb ();
16467 /* ARMv8.2 fp16 instruction. */
16468 if (rs
== NS_HI
|| rs
== NS_HH
)
16469 do_scalar_fp16_v82_encode ();
16473 nsyn_insert_sp (void)
16475 inst
.operands
[1] = inst
.operands
[0];
16476 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16477 inst
.operands
[0].reg
= REG_SP
;
16478 inst
.operands
[0].isreg
= 1;
16479 inst
.operands
[0].writeback
= 1;
16480 inst
.operands
[0].present
= 1;
16484 do_vfp_nsyn_push (void)
16488 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16489 _("register list must contain at least 1 and at most 16 "
16492 if (inst
.operands
[1].issingle
)
16493 do_vfp_nsyn_opcode ("fstmdbs");
16495 do_vfp_nsyn_opcode ("fstmdbd");
16499 do_vfp_nsyn_pop (void)
16503 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16504 _("register list must contain at least 1 and at most 16 "
16507 if (inst
.operands
[1].issingle
)
16508 do_vfp_nsyn_opcode ("fldmias");
16510 do_vfp_nsyn_opcode ("fldmiad");
16513 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16514 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16517 neon_dp_fixup (struct arm_it
* insn
)
16519 unsigned int i
= insn
->instruction
;
16524 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16535 insn
->instruction
= i
;
16539 mve_encode_qqr (int size
, int U
, int fp
)
16541 if (inst
.operands
[2].reg
== REG_SP
)
16542 as_tsktsk (MVE_BAD_SP
);
16543 else if (inst
.operands
[2].reg
== REG_PC
)
16544 as_tsktsk (MVE_BAD_PC
);
16549 if (((unsigned)inst
.instruction
) == 0xd00)
16550 inst
.instruction
= 0xee300f40;
16552 else if (((unsigned)inst
.instruction
) == 0x200d00)
16553 inst
.instruction
= 0xee301f40;
16555 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16556 inst
.instruction
= 0xee310e60;
16558 /* Setting size which is 1 for F16 and 0 for F32. */
16559 inst
.instruction
|= (size
== 16) << 28;
16564 if (((unsigned)inst
.instruction
) == 0x800)
16565 inst
.instruction
= 0xee010f40;
16567 else if (((unsigned)inst
.instruction
) == 0x1000800)
16568 inst
.instruction
= 0xee011f40;
16570 else if (((unsigned)inst
.instruction
) == 0)
16571 inst
.instruction
= 0xee000f40;
16573 else if (((unsigned)inst
.instruction
) == 0x200)
16574 inst
.instruction
= 0xee001f40;
16576 else if (((unsigned)inst
.instruction
) == 0x900)
16577 inst
.instruction
= 0xee010e40;
16579 else if (((unsigned)inst
.instruction
) == 0x910)
16580 inst
.instruction
= 0xee011e60;
16582 else if (((unsigned)inst
.instruction
) == 0x10)
16583 inst
.instruction
= 0xee000f60;
16585 else if (((unsigned)inst
.instruction
) == 0x210)
16586 inst
.instruction
= 0xee001f60;
16588 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16589 inst
.instruction
= 0xee000e40;
16591 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16592 inst
.instruction
= 0xee010e60;
16594 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16595 inst
.instruction
= 0xfe010e60;
16598 inst
.instruction
|= U
<< 28;
16600 /* Setting bits for size. */
16601 inst
.instruction
|= neon_logbits (size
) << 20;
16603 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16604 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16605 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16606 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16607 inst
.instruction
|= inst
.operands
[2].reg
;
16612 mve_encode_rqq (unsigned bit28
, unsigned size
)
16614 inst
.instruction
|= bit28
<< 28;
16615 inst
.instruction
|= neon_logbits (size
) << 20;
16616 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16617 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16618 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16619 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16620 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16625 mve_encode_qqq (int ubit
, int size
)
16628 inst
.instruction
|= (ubit
!= 0) << 28;
16629 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16630 inst
.instruction
|= neon_logbits (size
) << 20;
16631 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16632 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16633 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16634 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16635 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16641 mve_encode_rq (unsigned bit28
, unsigned size
)
16643 inst
.instruction
|= bit28
<< 28;
16644 inst
.instruction
|= neon_logbits (size
) << 18;
16645 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16646 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16651 mve_encode_rrqq (unsigned U
, unsigned size
)
16653 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16655 inst
.instruction
|= U
<< 28;
16656 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16657 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16658 inst
.instruction
|= (size
== 32) << 16;
16659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16660 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16661 inst
.instruction
|= inst
.operands
[3].reg
;
16665 /* Helper function for neon_three_same handling the operands. */
16667 neon_three_args (int isquad
)
16669 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16670 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16671 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16672 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16673 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16674 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16675 inst
.instruction
|= (isquad
!= 0) << 6;
16679 /* Encode insns with bit pattern:
16681 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16682 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16684 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16685 different meaning for some instruction. */
16688 neon_three_same (int isquad
, int ubit
, int size
)
16690 neon_three_args (isquad
);
16691 inst
.instruction
|= (ubit
!= 0) << 24;
16693 inst
.instruction
|= neon_logbits (size
) << 20;
16695 neon_dp_fixup (&inst
);
16698 /* Encode instructions of the form:
16700 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16701 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16703 Don't write size if SIZE == -1. */
16706 neon_two_same (int qbit
, int ubit
, int size
)
16708 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16709 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16710 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16711 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16712 inst
.instruction
|= (qbit
!= 0) << 6;
16713 inst
.instruction
|= (ubit
!= 0) << 24;
16716 inst
.instruction
|= neon_logbits (size
) << 18;
16718 neon_dp_fixup (&inst
);
16721 enum vfp_or_neon_is_neon_bits
16724 NEON_CHECK_ARCH
= 2,
16725 NEON_CHECK_ARCH8
= 4
16728 /* Call this function if an instruction which may have belonged to the VFP or
16729 Neon instruction sets, but turned out to be a Neon instruction (due to the
16730 operand types involved, etc.). We have to check and/or fix-up a couple of
16733 - Make sure the user hasn't attempted to make a Neon instruction
16735 - Alter the value in the condition code field if necessary.
16736 - Make sure that the arch supports Neon instructions.
16738 Which of these operations take place depends on bits from enum
16739 vfp_or_neon_is_neon_bits.
16741 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16742 current instruction's condition is COND_ALWAYS, the condition field is
16743 changed to inst.uncond_value. This is necessary because instructions shared
16744 between VFP and Neon may be conditional for the VFP variants only, and the
16745 unconditional Neon version must have, e.g., 0xF in the condition field. */
16748 vfp_or_neon_is_neon (unsigned check
)
16750 /* Conditions are always legal in Thumb mode (IT blocks). */
16751 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16753 if (inst
.cond
!= COND_ALWAYS
)
16755 first_error (_(BAD_COND
));
16758 if (inst
.uncond_value
!= -1)
16759 inst
.instruction
|= inst
.uncond_value
<< 28;
16763 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16764 || ((check
& NEON_CHECK_ARCH8
)
16765 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16767 first_error (_(BAD_FPU
));
16775 /* Return TRUE if the SIMD instruction is available for the current
16776 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16777 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16778 vfp_or_neon_is_neon for the NEON specific checks. */
16781 check_simd_pred_availability (int fp
, unsigned check
)
16783 if (inst
.cond
> COND_ALWAYS
)
16785 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16787 inst
.error
= BAD_FPU
;
16790 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16792 else if (inst
.cond
< COND_ALWAYS
)
16794 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16795 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16796 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16801 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16802 && vfp_or_neon_is_neon (check
) == FAIL
)
16805 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16806 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16811 /* Neon instruction encoders, in approximate order of appearance. */
16814 do_neon_dyadic_i_su (void)
16816 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16819 enum neon_shape rs
;
16820 struct neon_type_el et
;
16821 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16822 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16824 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16826 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16830 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16832 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16836 do_neon_dyadic_i64_su (void)
16838 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16840 enum neon_shape rs
;
16841 struct neon_type_el et
;
16842 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16844 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16845 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16849 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16850 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16853 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16855 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16859 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16862 unsigned size
= et
.size
>> 3;
16863 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16864 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16865 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16866 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16867 inst
.instruction
|= (isquad
!= 0) << 6;
16868 inst
.instruction
|= immbits
<< 16;
16869 inst
.instruction
|= (size
>> 3) << 7;
16870 inst
.instruction
|= (size
& 0x7) << 19;
16872 inst
.instruction
|= (uval
!= 0) << 24;
16874 neon_dp_fixup (&inst
);
16880 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16883 if (!inst
.operands
[2].isreg
)
16885 enum neon_shape rs
;
16886 struct neon_type_el et
;
16887 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16889 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16890 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16894 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16895 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16897 int imm
= inst
.operands
[2].imm
;
16899 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16900 _("immediate out of range for shift"));
16901 NEON_ENCODE (IMMED
, inst
);
16902 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16906 enum neon_shape rs
;
16907 struct neon_type_el et
;
16908 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16910 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16911 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16915 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16916 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16922 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16923 _("invalid instruction shape"));
16924 if (inst
.operands
[2].reg
== REG_SP
)
16925 as_tsktsk (MVE_BAD_SP
);
16926 else if (inst
.operands
[2].reg
== REG_PC
)
16927 as_tsktsk (MVE_BAD_PC
);
16929 inst
.instruction
= 0xee311e60;
16930 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16931 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16932 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16933 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16934 inst
.instruction
|= inst
.operands
[2].reg
;
16941 /* VSHL/VQSHL 3-register variants have syntax such as:
16943 whereas other 3-register operations encoded by neon_three_same have
16946 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16947 operands[2].reg here. */
16948 tmp
= inst
.operands
[2].reg
;
16949 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16950 inst
.operands
[1].reg
= tmp
;
16951 NEON_ENCODE (INTEGER
, inst
);
16952 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16958 do_neon_qshl (void)
16960 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16963 if (!inst
.operands
[2].isreg
)
16965 enum neon_shape rs
;
16966 struct neon_type_el et
;
16967 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16969 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16970 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16974 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16975 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16977 int imm
= inst
.operands
[2].imm
;
16979 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16980 _("immediate out of range for shift"));
16981 NEON_ENCODE (IMMED
, inst
);
16982 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16986 enum neon_shape rs
;
16987 struct neon_type_el et
;
16989 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16991 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16992 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16996 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16997 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17002 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17003 _("invalid instruction shape"));
17004 if (inst
.operands
[2].reg
== REG_SP
)
17005 as_tsktsk (MVE_BAD_SP
);
17006 else if (inst
.operands
[2].reg
== REG_PC
)
17007 as_tsktsk (MVE_BAD_PC
);
17009 inst
.instruction
= 0xee311ee0;
17010 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17011 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17012 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17013 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17014 inst
.instruction
|= inst
.operands
[2].reg
;
17021 /* See note in do_neon_shl. */
17022 tmp
= inst
.operands
[2].reg
;
17023 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17024 inst
.operands
[1].reg
= tmp
;
17025 NEON_ENCODE (INTEGER
, inst
);
17026 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17032 do_neon_rshl (void)
17034 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17037 enum neon_shape rs
;
17038 struct neon_type_el et
;
17039 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17041 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17042 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17046 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17047 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17054 if (inst
.operands
[2].reg
== REG_PC
)
17055 as_tsktsk (MVE_BAD_PC
);
17056 else if (inst
.operands
[2].reg
== REG_SP
)
17057 as_tsktsk (MVE_BAD_SP
);
17059 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17060 _("invalid instruction shape"));
17062 if (inst
.instruction
== 0x0000510)
17063 /* We are dealing with vqrshl. */
17064 inst
.instruction
= 0xee331ee0;
17066 /* We are dealing with vrshl. */
17067 inst
.instruction
= 0xee331e60;
17069 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17070 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17071 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17072 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17073 inst
.instruction
|= inst
.operands
[2].reg
;
17078 tmp
= inst
.operands
[2].reg
;
17079 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17080 inst
.operands
[1].reg
= tmp
;
17081 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17086 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17088 /* Handle .I8 pseudo-instructions. */
17091 /* Unfortunately, this will make everything apart from zero out-of-range.
17092 FIXME is this the intended semantics? There doesn't seem much point in
17093 accepting .I8 if so. */
17094 immediate
|= immediate
<< 8;
17100 if (immediate
== (immediate
& 0x000000ff))
17102 *immbits
= immediate
;
17105 else if (immediate
== (immediate
& 0x0000ff00))
17107 *immbits
= immediate
>> 8;
17110 else if (immediate
== (immediate
& 0x00ff0000))
17112 *immbits
= immediate
>> 16;
17115 else if (immediate
== (immediate
& 0xff000000))
17117 *immbits
= immediate
>> 24;
17120 if ((immediate
& 0xffff) != (immediate
>> 16))
17121 goto bad_immediate
;
17122 immediate
&= 0xffff;
17125 if (immediate
== (immediate
& 0x000000ff))
17127 *immbits
= immediate
;
17130 else if (immediate
== (immediate
& 0x0000ff00))
17132 *immbits
= immediate
>> 8;
17137 first_error (_("immediate value out of range"));
17142 do_neon_logic (void)
17144 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17146 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17148 && !check_simd_pred_availability (FALSE
,
17149 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17151 else if (rs
!= NS_QQQ
17152 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17153 first_error (BAD_FPU
);
17155 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17156 /* U bit and size field were set as part of the bitmask. */
17157 NEON_ENCODE (INTEGER
, inst
);
17158 neon_three_same (neon_quad (rs
), 0, -1);
17162 const int three_ops_form
= (inst
.operands
[2].present
17163 && !inst
.operands
[2].isreg
);
17164 const int immoperand
= (three_ops_form
? 2 : 1);
17165 enum neon_shape rs
= (three_ops_form
17166 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17167 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17168 /* Because neon_select_shape makes the second operand a copy of the first
17169 if the second operand is not present. */
17171 && !check_simd_pred_availability (FALSE
,
17172 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17174 else if (rs
!= NS_QQI
17175 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17176 first_error (BAD_FPU
);
17178 struct neon_type_el et
;
17179 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17180 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17182 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17185 if (et
.type
== NT_invtype
)
17187 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17192 if (three_ops_form
)
17193 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17194 _("first and second operands shall be the same register"));
17196 NEON_ENCODE (IMMED
, inst
);
17198 immbits
= inst
.operands
[immoperand
].imm
;
17201 /* .i64 is a pseudo-op, so the immediate must be a repeating
17203 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17204 inst
.operands
[immoperand
].reg
: 0))
17206 /* Set immbits to an invalid constant. */
17207 immbits
= 0xdeadbeef;
17214 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17218 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17222 /* Pseudo-instruction for VBIC. */
17223 neon_invert_size (&immbits
, 0, et
.size
);
17224 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17228 /* Pseudo-instruction for VORR. */
17229 neon_invert_size (&immbits
, 0, et
.size
);
17230 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17240 inst
.instruction
|= neon_quad (rs
) << 6;
17241 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17242 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17243 inst
.instruction
|= cmode
<< 8;
17244 neon_write_immbits (immbits
);
17246 neon_dp_fixup (&inst
);
17251 do_neon_bitfield (void)
17253 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17254 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17255 neon_three_same (neon_quad (rs
), 0, -1);
17259 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17262 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17263 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17265 if (et
.type
== NT_float
)
17267 NEON_ENCODE (FLOAT
, inst
);
17269 mve_encode_qqr (et
.size
, 0, 1);
17271 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17275 NEON_ENCODE (INTEGER
, inst
);
17277 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17279 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17285 do_neon_dyadic_if_su_d (void)
17287 /* This version only allow D registers, but that constraint is enforced during
17288 operand parsing so we don't need to do anything extra here. */
17289 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17293 do_neon_dyadic_if_i_d (void)
17295 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17296 affected if we specify unsigned args. */
17297 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17301 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17303 constraint (size
< 32, BAD_ADDR_MODE
);
17304 constraint (size
!= elsize
, BAD_EL_TYPE
);
17305 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17306 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17307 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17308 _("destination register and offset register may not be the"
17311 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17318 constraint ((imm
% (size
/ 8) != 0)
17319 || imm
> (0x7f << neon_logbits (size
)),
17320 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17321 " range of +/-[0,508]")
17322 : _("immediate must be a multiple of 8 in the"
17323 " range of +/-[0,1016]"));
17324 inst
.instruction
|= 0x11 << 24;
17325 inst
.instruction
|= add
<< 23;
17326 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17327 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17328 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17329 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17330 inst
.instruction
|= 1 << 12;
17331 inst
.instruction
|= (size
== 64) << 8;
17332 inst
.instruction
&= 0xffffff00;
17333 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17334 inst
.instruction
|= imm
>> neon_logbits (size
);
17338 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17340 unsigned os
= inst
.operands
[1].imm
>> 5;
17341 unsigned type
= inst
.vectype
.el
[0].type
;
17342 constraint (os
!= 0 && size
== 8,
17343 _("can not shift offsets when accessing less than half-word"));
17344 constraint (os
&& os
!= neon_logbits (size
),
17345 _("shift immediate must be 1, 2 or 3 for half-word, word"
17346 " or double-word accesses respectively"));
17347 if (inst
.operands
[1].reg
== REG_PC
)
17348 as_tsktsk (MVE_BAD_PC
);
17353 constraint (elsize
>= 64, BAD_EL_TYPE
);
17356 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17360 constraint (elsize
!= size
, BAD_EL_TYPE
);
17365 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17369 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17370 _("destination register and offset register may not be"
17372 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17373 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17375 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17379 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17382 inst
.instruction
|= 1 << 23;
17383 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17384 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17385 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17386 inst
.instruction
|= neon_logbits (elsize
) << 7;
17387 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17388 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17389 inst
.instruction
|= !!os
;
17393 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17395 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17397 constraint (size
>= 64, BAD_ADDR_MODE
);
17401 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17404 constraint (elsize
!= size
, BAD_EL_TYPE
);
17411 constraint (elsize
!= size
&& type
!= NT_unsigned
17412 && type
!= NT_signed
, BAD_EL_TYPE
);
17416 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17419 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17427 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17432 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17435 constraint (1, _("immediate must be a multiple of 2 in the"
17436 " range of +/-[0,254]"));
17439 constraint (1, _("immediate must be a multiple of 4 in the"
17440 " range of +/-[0,508]"));
17445 if (size
!= elsize
)
17447 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17448 constraint (inst
.operands
[0].reg
> 14,
17449 _("MVE vector register in the range [Q0..Q7] expected"));
17450 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17451 inst
.instruction
|= (size
== 16) << 19;
17452 inst
.instruction
|= neon_logbits (elsize
) << 7;
17456 if (inst
.operands
[1].reg
== REG_PC
)
17457 as_tsktsk (MVE_BAD_PC
);
17458 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17459 as_tsktsk (MVE_BAD_SP
);
17460 inst
.instruction
|= 1 << 12;
17461 inst
.instruction
|= neon_logbits (size
) << 7;
17463 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17464 inst
.instruction
|= add
<< 23;
17465 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17466 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17467 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17468 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17469 inst
.instruction
&= 0xffffff80;
17470 inst
.instruction
|= imm
>> neon_logbits (size
);
17475 do_mve_vstr_vldr (void)
17480 if (inst
.cond
> COND_ALWAYS
)
17481 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17483 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17485 switch (inst
.instruction
)
17492 /* fall through. */
17498 /* fall through. */
17504 /* fall through. */
17510 /* fall through. */
17515 unsigned elsize
= inst
.vectype
.el
[0].size
;
17517 if (inst
.operands
[1].isquad
)
17519 /* We are dealing with [Q, imm]{!} cases. */
17520 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17524 if (inst
.operands
[1].immisreg
== 2)
17526 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17527 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17529 else if (!inst
.operands
[1].immisreg
)
17531 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17532 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17535 constraint (1, BAD_ADDR_MODE
);
17542 do_mve_vst_vld (void)
17544 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17547 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17548 || inst
.relocs
[0].exp
.X_add_number
!= 0
17549 || inst
.operands
[1].immisreg
!= 0,
17551 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17552 if (inst
.operands
[1].reg
== REG_PC
)
17553 as_tsktsk (MVE_BAD_PC
);
17554 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17555 as_tsktsk (MVE_BAD_SP
);
17558 /* These instructions are one of the "exceptions" mentioned in
17559 handle_pred_state. They are MVE instructions that are not VPT compatible
17560 and do not accept a VPT code, thus appending such a code is a syntax
17562 if (inst
.cond
> COND_ALWAYS
)
17563 first_error (BAD_SYNTAX
);
17564 /* If we append a scalar condition code we can set this to
17565 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17566 else if (inst
.cond
< COND_ALWAYS
)
17567 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17569 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17571 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17572 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17573 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17574 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17575 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17580 do_mve_vaddlv (void)
17582 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17583 struct neon_type_el et
17584 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17586 if (et
.type
== NT_invtype
)
17587 first_error (BAD_EL_TYPE
);
17589 if (inst
.cond
> COND_ALWAYS
)
17590 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17592 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17594 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17596 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17597 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17598 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17599 inst
.instruction
|= inst
.operands
[2].reg
;
17604 do_neon_dyadic_if_su (void)
17606 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17607 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17610 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17611 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17612 && et
.type
== NT_float
17613 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17615 if (!check_simd_pred_availability (et
.type
== NT_float
,
17616 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17619 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17623 do_neon_addsub_if_i (void)
17625 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17626 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17629 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17630 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17631 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17633 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17634 /* If we are parsing Q registers and the element types match MVE, which NEON
17635 also supports, then we must check whether this is an instruction that can
17636 be used by both MVE/NEON. This distinction can be made based on whether
17637 they are predicated or not. */
17638 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17640 if (!check_simd_pred_availability (et
.type
== NT_float
,
17641 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17646 /* If they are either in a D register or are using an unsupported. */
17648 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17652 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17653 affected if we specify unsigned args. */
17654 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17657 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17659 V<op> A,B (A is operand 0, B is operand 2)
17664 so handle that case specially. */
17667 neon_exchange_operands (void)
17669 if (inst
.operands
[1].present
)
17671 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17673 /* Swap operands[1] and operands[2]. */
17674 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17675 inst
.operands
[1] = inst
.operands
[2];
17676 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17681 inst
.operands
[1] = inst
.operands
[2];
17682 inst
.operands
[2] = inst
.operands
[0];
17687 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17689 if (inst
.operands
[2].isreg
)
17692 neon_exchange_operands ();
17693 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17697 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17698 struct neon_type_el et
= neon_check_type (2, rs
,
17699 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17701 NEON_ENCODE (IMMED
, inst
);
17702 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17703 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17704 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17705 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17706 inst
.instruction
|= neon_quad (rs
) << 6;
17707 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17708 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17710 neon_dp_fixup (&inst
);
17717 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17721 do_neon_cmp_inv (void)
17723 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17729 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17732 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17733 scalars, which are encoded in 5 bits, M : Rm.
17734 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17735 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17738 Dot Product instructions are similar to multiply instructions except elsize
17739 should always be 32.
17741 This function translates SCALAR, which is GAS's internal encoding of indexed
17742 scalar register, to raw encoding. There is also register and index range
17743 check based on ELSIZE. */
17746 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17748 unsigned regno
= NEON_SCALAR_REG (scalar
);
17749 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17754 if (regno
> 7 || elno
> 3)
17756 return regno
| (elno
<< 3);
17759 if (regno
> 15 || elno
> 1)
17761 return regno
| (elno
<< 4);
17765 first_error (_("scalar out of range for multiply instruction"));
17771 /* Encode multiply / multiply-accumulate scalar instructions. */
17774 neon_mul_mac (struct neon_type_el et
, int ubit
)
17778 /* Give a more helpful error message if we have an invalid type. */
17779 if (et
.type
== NT_invtype
)
17782 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17783 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17784 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17785 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17786 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17787 inst
.instruction
|= LOW4 (scalar
);
17788 inst
.instruction
|= HI1 (scalar
) << 5;
17789 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17790 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17791 inst
.instruction
|= (ubit
!= 0) << 24;
17793 neon_dp_fixup (&inst
);
17797 do_neon_mac_maybe_scalar (void)
17799 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17802 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17805 if (inst
.operands
[2].isscalar
)
17807 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17808 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17809 struct neon_type_el et
= neon_check_type (3, rs
,
17810 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17811 NEON_ENCODE (SCALAR
, inst
);
17812 neon_mul_mac (et
, neon_quad (rs
));
17814 else if (!inst
.operands
[2].isvec
)
17816 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17818 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17819 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17821 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17825 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17826 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17827 affected if we specify unsigned args. */
17828 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17833 do_bfloat_vfma (void)
17835 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17836 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17837 enum neon_shape rs
;
17840 if (inst
.instruction
!= B_MNEM_vfmab
)
17843 inst
.instruction
= B_MNEM_vfmat
;
17846 if (inst
.operands
[2].isscalar
)
17848 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17849 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17851 inst
.instruction
|= (1 << 25);
17852 int index
= inst
.operands
[2].reg
& 0xf;
17853 constraint (!(index
< 4), _("index must be in the range 0 to 3"));
17854 inst
.operands
[2].reg
>>= 4;
17855 constraint (!(inst
.operands
[2].reg
< 8),
17856 _("indexed register must be less than 8"));
17857 neon_three_args (t_bit
);
17858 inst
.instruction
|= ((index
& 1) << 3);
17859 inst
.instruction
|= ((index
& 2) << 4);
17863 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17864 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17865 neon_three_args (t_bit
);
17871 do_neon_fmac (void)
17873 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17874 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17877 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17880 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17882 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17883 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17889 if (inst
.operands
[2].reg
== REG_SP
)
17890 as_tsktsk (MVE_BAD_SP
);
17891 else if (inst
.operands
[2].reg
== REG_PC
)
17892 as_tsktsk (MVE_BAD_PC
);
17894 inst
.instruction
= 0xee310e40;
17895 inst
.instruction
|= (et
.size
== 16) << 28;
17896 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17897 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17898 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17899 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17900 inst
.instruction
|= inst
.operands
[2].reg
;
17907 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17910 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17916 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
17917 inst
.cond
== COND_ALWAYS
)
17919 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17920 inst
.instruction
= N_MNEM_vfma
;
17921 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17923 return do_neon_fmac();
17934 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17935 struct neon_type_el et
= neon_check_type (3, rs
,
17936 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17937 neon_three_same (neon_quad (rs
), 0, et
.size
);
17940 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17941 same types as the MAC equivalents. The polynomial type for this instruction
17942 is encoded the same as the integer type. */
17947 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17950 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17953 if (inst
.operands
[2].isscalar
)
17955 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17956 do_neon_mac_maybe_scalar ();
17960 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17962 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17963 struct neon_type_el et
17964 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17965 if (et
.type
== NT_float
)
17966 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17969 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17973 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17974 neon_dyadic_misc (NT_poly
,
17975 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17981 do_neon_qdmulh (void)
17983 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17986 if (inst
.operands
[2].isscalar
)
17988 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17989 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17990 struct neon_type_el et
= neon_check_type (3, rs
,
17991 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17992 NEON_ENCODE (SCALAR
, inst
);
17993 neon_mul_mac (et
, neon_quad (rs
));
17997 enum neon_shape rs
;
17998 struct neon_type_el et
;
17999 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18001 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18002 et
= neon_check_type (3, rs
,
18003 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18007 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18008 et
= neon_check_type (3, rs
,
18009 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18012 NEON_ENCODE (INTEGER
, inst
);
18014 mve_encode_qqr (et
.size
, 0, 0);
18016 /* The U bit (rounding) comes from bit mask. */
18017 neon_three_same (neon_quad (rs
), 0, et
.size
);
18022 do_mve_vaddv (void)
18024 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18025 struct neon_type_el et
18026 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18028 if (et
.type
== NT_invtype
)
18029 first_error (BAD_EL_TYPE
);
18031 if (inst
.cond
> COND_ALWAYS
)
18032 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18034 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18036 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18038 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18042 do_mve_vhcadd (void)
18044 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18045 struct neon_type_el et
18046 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18048 if (inst
.cond
> COND_ALWAYS
)
18049 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18051 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18053 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18054 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18056 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18057 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18058 "operand makes instruction UNPREDICTABLE"));
18060 mve_encode_qqq (0, et
.size
);
18061 inst
.instruction
|= (rot
== 270) << 12;
18066 do_mve_vqdmull (void)
18068 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18069 struct neon_type_el et
18070 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18073 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18074 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18075 as_tsktsk (BAD_MVE_SRCDEST
);
18077 if (inst
.cond
> COND_ALWAYS
)
18078 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18080 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18084 mve_encode_qqq (et
.size
== 32, 64);
18085 inst
.instruction
|= 1;
18089 mve_encode_qqr (64, et
.size
== 32, 0);
18090 inst
.instruction
|= 0x3 << 5;
18097 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18098 struct neon_type_el et
18099 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18101 if (et
.type
== NT_invtype
)
18102 first_error (BAD_EL_TYPE
);
18104 if (inst
.cond
> COND_ALWAYS
)
18105 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18107 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18109 mve_encode_qqq (0, 64);
18113 do_mve_vbrsr (void)
18115 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18116 struct neon_type_el et
18117 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18119 if (inst
.cond
> COND_ALWAYS
)
18120 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18122 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18124 mve_encode_qqr (et
.size
, 0, 0);
18130 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18132 if (inst
.cond
> COND_ALWAYS
)
18133 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18135 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18137 mve_encode_qqq (1, 64);
18141 do_mve_vmulh (void)
18143 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18144 struct neon_type_el et
18145 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18147 if (inst
.cond
> COND_ALWAYS
)
18148 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18150 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18152 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18156 do_mve_vqdmlah (void)
18158 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18159 struct neon_type_el et
18160 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18162 if (inst
.cond
> COND_ALWAYS
)
18163 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18165 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18167 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18171 do_mve_vqdmladh (void)
18173 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18174 struct neon_type_el et
18175 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18177 if (inst
.cond
> COND_ALWAYS
)
18178 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18180 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18182 mve_encode_qqq (0, et
.size
);
18187 do_mve_vmull (void)
18190 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18191 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18192 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18193 && inst
.cond
== COND_ALWAYS
18194 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18199 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18200 N_SUF_32
| N_F64
| N_P8
18201 | N_P16
| N_I_MVE
| N_KEY
);
18202 if (((et
.type
== NT_poly
) && et
.size
== 8
18203 && ARM_CPU_IS_ANY (cpu_variant
))
18204 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
18211 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18212 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18213 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18215 /* We are dealing with MVE's vmullt. */
18217 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18218 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18219 as_tsktsk (BAD_MVE_SRCDEST
);
18221 if (inst
.cond
> COND_ALWAYS
)
18222 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18224 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18226 if (et
.type
== NT_poly
)
18227 mve_encode_qqq (neon_logbits (et
.size
), 64);
18229 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18234 inst
.instruction
= N_MNEM_vmul
;
18237 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18242 do_mve_vabav (void)
18244 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18249 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18252 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18253 | N_S16
| N_S32
| N_U8
| N_U16
18256 if (inst
.cond
> COND_ALWAYS
)
18257 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18259 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18261 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18265 do_mve_vmladav (void)
18267 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18268 struct neon_type_el et
= neon_check_type (3, rs
,
18269 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18271 if (et
.type
== NT_unsigned
18272 && (inst
.instruction
== M_MNEM_vmladavx
18273 || inst
.instruction
== M_MNEM_vmladavax
18274 || inst
.instruction
== M_MNEM_vmlsdav
18275 || inst
.instruction
== M_MNEM_vmlsdava
18276 || inst
.instruction
== M_MNEM_vmlsdavx
18277 || inst
.instruction
== M_MNEM_vmlsdavax
))
18278 first_error (BAD_SIMD_TYPE
);
18280 constraint (inst
.operands
[2].reg
> 14,
18281 _("MVE vector register in the range [Q0..Q7] expected"));
18283 if (inst
.cond
> COND_ALWAYS
)
18284 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18286 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18288 if (inst
.instruction
== M_MNEM_vmlsdav
18289 || inst
.instruction
== M_MNEM_vmlsdava
18290 || inst
.instruction
== M_MNEM_vmlsdavx
18291 || inst
.instruction
== M_MNEM_vmlsdavax
)
18292 inst
.instruction
|= (et
.size
== 8) << 28;
18294 inst
.instruction
|= (et
.size
== 8) << 8;
18296 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18297 inst
.instruction
|= (et
.size
== 32) << 16;
18301 do_mve_vmlaldav (void)
18303 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18304 struct neon_type_el et
18305 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18306 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18308 if (et
.type
== NT_unsigned
18309 && (inst
.instruction
== M_MNEM_vmlsldav
18310 || inst
.instruction
== M_MNEM_vmlsldava
18311 || inst
.instruction
== M_MNEM_vmlsldavx
18312 || inst
.instruction
== M_MNEM_vmlsldavax
))
18313 first_error (BAD_SIMD_TYPE
);
18315 if (inst
.cond
> COND_ALWAYS
)
18316 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18318 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18320 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18324 do_mve_vrmlaldavh (void)
18326 struct neon_type_el et
;
18327 if (inst
.instruction
== M_MNEM_vrmlsldavh
18328 || inst
.instruction
== M_MNEM_vrmlsldavha
18329 || inst
.instruction
== M_MNEM_vrmlsldavhx
18330 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18332 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18333 if (inst
.operands
[1].reg
== REG_SP
)
18334 as_tsktsk (MVE_BAD_SP
);
18338 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18339 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18340 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18342 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18343 N_U32
| N_S32
| N_KEY
);
18344 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18345 with vmax/min instructions, making the use of SP in assembly really
18346 nonsensical, so instead of issuing a warning like we do for other uses
18347 of SP for the odd register operand we error out. */
18348 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18351 /* Make sure we still check the second operand is an odd one and that PC is
18352 disallowed. This because we are parsing for any GPR operand, to be able
18353 to distinguish between giving a warning or an error for SP as described
18355 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18356 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18358 if (inst
.cond
> COND_ALWAYS
)
18359 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18361 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18363 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18368 do_mve_vmaxnmv (void)
18370 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18371 struct neon_type_el et
18372 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18374 if (inst
.cond
> COND_ALWAYS
)
18375 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18377 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18379 if (inst
.operands
[0].reg
== REG_SP
)
18380 as_tsktsk (MVE_BAD_SP
);
18381 else if (inst
.operands
[0].reg
== REG_PC
)
18382 as_tsktsk (MVE_BAD_PC
);
18384 mve_encode_rq (et
.size
== 16, 64);
18388 do_mve_vmaxv (void)
18390 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18391 struct neon_type_el et
;
18393 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18394 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18396 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18398 if (inst
.cond
> COND_ALWAYS
)
18399 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18401 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18403 if (inst
.operands
[0].reg
== REG_SP
)
18404 as_tsktsk (MVE_BAD_SP
);
18405 else if (inst
.operands
[0].reg
== REG_PC
)
18406 as_tsktsk (MVE_BAD_PC
);
18408 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18413 do_neon_qrdmlah (void)
18415 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18417 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18419 /* Check we're on the correct architecture. */
18420 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18422 = _("instruction form not available on this architecture.");
18423 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18425 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18426 record_feature_use (&fpu_neon_ext_v8_1
);
18428 if (inst
.operands
[2].isscalar
)
18430 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18431 struct neon_type_el et
= neon_check_type (3, rs
,
18432 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18433 NEON_ENCODE (SCALAR
, inst
);
18434 neon_mul_mac (et
, neon_quad (rs
));
18438 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18439 struct neon_type_el et
= neon_check_type (3, rs
,
18440 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18441 NEON_ENCODE (INTEGER
, inst
);
18442 /* The U bit (rounding) comes from bit mask. */
18443 neon_three_same (neon_quad (rs
), 0, et
.size
);
18448 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18449 struct neon_type_el et
18450 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18452 NEON_ENCODE (INTEGER
, inst
);
18453 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18458 do_neon_fcmp_absolute (void)
18460 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18461 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18462 N_F_16_32
| N_KEY
);
18463 /* Size field comes from bit mask. */
18464 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18468 do_neon_fcmp_absolute_inv (void)
18470 neon_exchange_operands ();
18471 do_neon_fcmp_absolute ();
18475 do_neon_step (void)
18477 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18478 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18479 N_F_16_32
| N_KEY
);
18480 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18484 do_neon_abs_neg (void)
18486 enum neon_shape rs
;
18487 struct neon_type_el et
;
18489 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18492 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18493 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18495 if (!check_simd_pred_availability (et
.type
== NT_float
,
18496 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18499 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18500 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18501 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18502 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18503 inst
.instruction
|= neon_quad (rs
) << 6;
18504 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18505 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18507 neon_dp_fixup (&inst
);
18513 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18516 enum neon_shape rs
;
18517 struct neon_type_el et
;
18518 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18520 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18521 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18525 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18526 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18530 int imm
= inst
.operands
[2].imm
;
18531 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18532 _("immediate out of range for insert"));
18533 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18539 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18542 enum neon_shape rs
;
18543 struct neon_type_el et
;
18544 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18546 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18547 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18551 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18552 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18555 int imm
= inst
.operands
[2].imm
;
18556 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18557 _("immediate out of range for insert"));
18558 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18562 do_neon_qshlu_imm (void)
18564 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18567 enum neon_shape rs
;
18568 struct neon_type_el et
;
18569 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18571 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18572 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18576 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18577 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18578 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18581 int imm
= inst
.operands
[2].imm
;
18582 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18583 _("immediate out of range for shift"));
18584 /* Only encodes the 'U present' variant of the instruction.
18585 In this case, signed types have OP (bit 8) set to 0.
18586 Unsigned types have OP set to 1. */
18587 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18588 /* The rest of the bits are the same as other immediate shifts. */
18589 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18593 do_neon_qmovn (void)
18595 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18596 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18597 /* Saturating move where operands can be signed or unsigned, and the
18598 destination has the same signedness. */
18599 NEON_ENCODE (INTEGER
, inst
);
18600 if (et
.type
== NT_unsigned
)
18601 inst
.instruction
|= 0xc0;
18603 inst
.instruction
|= 0x80;
18604 neon_two_same (0, 1, et
.size
/ 2);
18608 do_neon_qmovun (void)
18610 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18611 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18612 /* Saturating move with unsigned results. Operands must be signed. */
18613 NEON_ENCODE (INTEGER
, inst
);
18614 neon_two_same (0, 1, et
.size
/ 2);
18618 do_neon_rshift_sat_narrow (void)
18620 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18621 or unsigned. If operands are unsigned, results must also be unsigned. */
18622 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18623 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18624 int imm
= inst
.operands
[2].imm
;
18625 /* This gets the bounds check, size encoding and immediate bits calculation
18629 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18630 VQMOVN.I<size> <Dd>, <Qm>. */
18633 inst
.operands
[2].present
= 0;
18634 inst
.instruction
= N_MNEM_vqmovn
;
18639 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18640 _("immediate out of range"));
18641 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18645 do_neon_rshift_sat_narrow_u (void)
18647 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18648 or unsigned. If operands are unsigned, results must also be unsigned. */
18649 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18650 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18651 int imm
= inst
.operands
[2].imm
;
18652 /* This gets the bounds check, size encoding and immediate bits calculation
18656 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18657 VQMOVUN.I<size> <Dd>, <Qm>. */
18660 inst
.operands
[2].present
= 0;
18661 inst
.instruction
= N_MNEM_vqmovun
;
18666 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18667 _("immediate out of range"));
18668 /* FIXME: The manual is kind of unclear about what value U should have in
18669 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18671 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18675 do_neon_movn (void)
18677 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18678 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18679 NEON_ENCODE (INTEGER
, inst
);
18680 neon_two_same (0, 1, et
.size
/ 2);
18684 do_neon_rshift_narrow (void)
18686 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18687 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18688 int imm
= inst
.operands
[2].imm
;
18689 /* This gets the bounds check, size encoding and immediate bits calculation
18693 /* If immediate is zero then we are a pseudo-instruction for
18694 VMOVN.I<size> <Dd>, <Qm> */
18697 inst
.operands
[2].present
= 0;
18698 inst
.instruction
= N_MNEM_vmovn
;
18703 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18704 _("immediate out of range for narrowing operation"));
18705 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18709 do_neon_shll (void)
18711 /* FIXME: Type checking when lengthening. */
18712 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18713 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18714 unsigned imm
= inst
.operands
[2].imm
;
18716 if (imm
== et
.size
)
18718 /* Maximum shift variant. */
18719 NEON_ENCODE (INTEGER
, inst
);
18720 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18721 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18722 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18723 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18724 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18726 neon_dp_fixup (&inst
);
18730 /* A more-specific type check for non-max versions. */
18731 et
= neon_check_type (2, NS_QDI
,
18732 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18733 NEON_ENCODE (IMMED
, inst
);
18734 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18738 /* Check the various types for the VCVT instruction, and return which version
18739 the current instruction is. */
18741 #define CVT_FLAVOUR_VAR \
18742 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18743 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18744 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18745 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18746 /* Half-precision conversions. */ \
18747 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18748 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18749 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18750 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18751 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18752 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18753 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18754 Compared with single/double precision variants, only the co-processor \
18755 field is different, so the encoding flow is reused here. */ \
18756 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18757 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18758 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18759 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18760 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18761 /* VFP instructions. */ \
18762 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18763 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18764 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18765 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18766 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18767 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18768 /* VFP instructions with bitshift. */ \
18769 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18770 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18771 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18772 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18773 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18774 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18775 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18776 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18778 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18779 neon_cvt_flavour_##C,
18781 /* The different types of conversions we can do. */
18782 enum neon_cvt_flavour
18785 neon_cvt_flavour_invalid
,
18786 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18791 static enum neon_cvt_flavour
18792 get_neon_cvt_flavour (enum neon_shape rs
)
18794 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18795 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18796 if (et.type != NT_invtype) \
18798 inst.error = NULL; \
18799 return (neon_cvt_flavour_##C); \
18802 struct neon_type_el et
;
18803 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18804 || rs
== NS_FF
) ? N_VFP
: 0;
18805 /* The instruction versions which take an immediate take one register
18806 argument, which is extended to the width of the full register. Thus the
18807 "source" and "destination" registers must have the same width. Hack that
18808 here by making the size equal to the key (wider, in this case) operand. */
18809 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18813 return neon_cvt_flavour_invalid
;
18828 /* Neon-syntax VFP conversions. */
18831 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18833 const char *opname
= 0;
18835 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18836 || rs
== NS_FHI
|| rs
== NS_HFI
)
18838 /* Conversions with immediate bitshift. */
18839 const char *enc
[] =
18841 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18847 if (flavour
< (int) ARRAY_SIZE (enc
))
18849 opname
= enc
[flavour
];
18850 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18851 _("operands 0 and 1 must be the same register"));
18852 inst
.operands
[1] = inst
.operands
[2];
18853 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18858 /* Conversions without bitshift. */
18859 const char *enc
[] =
18861 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18867 if (flavour
< (int) ARRAY_SIZE (enc
))
18868 opname
= enc
[flavour
];
18872 do_vfp_nsyn_opcode (opname
);
18874 /* ARMv8.2 fp16 VCVT instruction. */
18875 if (flavour
== neon_cvt_flavour_s32_f16
18876 || flavour
== neon_cvt_flavour_u32_f16
18877 || flavour
== neon_cvt_flavour_f16_u32
18878 || flavour
== neon_cvt_flavour_f16_s32
)
18879 do_scalar_fp16_v82_encode ();
18883 do_vfp_nsyn_cvtz (void)
18885 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18886 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18887 const char *enc
[] =
18889 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18895 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18896 do_vfp_nsyn_opcode (enc
[flavour
]);
18900 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18901 enum neon_cvt_mode mode
)
18906 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18907 D register operands. */
18908 if (flavour
== neon_cvt_flavour_s32_f64
18909 || flavour
== neon_cvt_flavour_u32_f64
)
18910 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18913 if (flavour
== neon_cvt_flavour_s32_f16
18914 || flavour
== neon_cvt_flavour_u32_f16
)
18915 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18918 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18922 case neon_cvt_flavour_s32_f64
:
18926 case neon_cvt_flavour_s32_f32
:
18930 case neon_cvt_flavour_s32_f16
:
18934 case neon_cvt_flavour_u32_f64
:
18938 case neon_cvt_flavour_u32_f32
:
18942 case neon_cvt_flavour_u32_f16
:
18947 first_error (_("invalid instruction shape"));
18953 case neon_cvt_mode_a
: rm
= 0; break;
18954 case neon_cvt_mode_n
: rm
= 1; break;
18955 case neon_cvt_mode_p
: rm
= 2; break;
18956 case neon_cvt_mode_m
: rm
= 3; break;
18957 default: first_error (_("invalid rounding mode")); return;
18960 NEON_ENCODE (FPV8
, inst
);
18961 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18962 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18963 inst
.instruction
|= sz
<< 8;
18965 /* ARMv8.2 fp16 VCVT instruction. */
18966 if (flavour
== neon_cvt_flavour_s32_f16
18967 ||flavour
== neon_cvt_flavour_u32_f16
)
18968 do_scalar_fp16_v82_encode ();
18969 inst
.instruction
|= op
<< 7;
18970 inst
.instruction
|= rm
<< 16;
18971 inst
.instruction
|= 0xf0000000;
18972 inst
.is_neon
= TRUE
;
18976 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18978 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18979 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18980 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18982 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18984 if (flavour
== neon_cvt_flavour_invalid
)
18987 /* PR11109: Handle round-to-zero for VCVT conversions. */
18988 if (mode
== neon_cvt_mode_z
18989 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18990 && (flavour
== neon_cvt_flavour_s16_f16
18991 || flavour
== neon_cvt_flavour_u16_f16
18992 || flavour
== neon_cvt_flavour_s32_f32
18993 || flavour
== neon_cvt_flavour_u32_f32
18994 || flavour
== neon_cvt_flavour_s32_f64
18995 || flavour
== neon_cvt_flavour_u32_f64
)
18996 && (rs
== NS_FD
|| rs
== NS_FF
))
18998 do_vfp_nsyn_cvtz ();
19002 /* ARMv8.2 fp16 VCVT conversions. */
19003 if (mode
== neon_cvt_mode_z
19004 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19005 && (flavour
== neon_cvt_flavour_s32_f16
19006 || flavour
== neon_cvt_flavour_u32_f16
)
19009 do_vfp_nsyn_cvtz ();
19010 do_scalar_fp16_v82_encode ();
19014 /* VFP rather than Neon conversions. */
19015 if (flavour
>= neon_cvt_flavour_first_fp
)
19017 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19018 do_vfp_nsyn_cvt (rs
, flavour
);
19020 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19028 if (mode
== neon_cvt_mode_z
19029 && (flavour
== neon_cvt_flavour_f16_s16
19030 || flavour
== neon_cvt_flavour_f16_u16
19031 || flavour
== neon_cvt_flavour_s16_f16
19032 || flavour
== neon_cvt_flavour_u16_f16
19033 || flavour
== neon_cvt_flavour_f32_u32
19034 || flavour
== neon_cvt_flavour_f32_s32
19035 || flavour
== neon_cvt_flavour_s32_f32
19036 || flavour
== neon_cvt_flavour_u32_f32
))
19038 if (!check_simd_pred_availability (TRUE
,
19039 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19042 else if (mode
== neon_cvt_mode_n
)
19044 /* We are dealing with vcvt with the 'ne' condition. */
19046 inst
.instruction
= N_MNEM_vcvt
;
19047 do_neon_cvt_1 (neon_cvt_mode_z
);
19050 /* fall through. */
19054 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19055 0x0000100, 0x1000100, 0x0, 0x1000000};
19057 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19058 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19061 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19063 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19064 _("immediate value out of range"));
19067 case neon_cvt_flavour_f16_s16
:
19068 case neon_cvt_flavour_f16_u16
:
19069 case neon_cvt_flavour_s16_f16
:
19070 case neon_cvt_flavour_u16_f16
:
19071 constraint (inst
.operands
[2].imm
> 16,
19072 _("immediate value out of range"));
19074 case neon_cvt_flavour_f32_u32
:
19075 case neon_cvt_flavour_f32_s32
:
19076 case neon_cvt_flavour_s32_f32
:
19077 case neon_cvt_flavour_u32_f32
:
19078 constraint (inst
.operands
[2].imm
> 32,
19079 _("immediate value out of range"));
19082 inst
.error
= BAD_FPU
;
19087 /* Fixed-point conversion with #0 immediate is encoded as an
19088 integer conversion. */
19089 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19091 NEON_ENCODE (IMMED
, inst
);
19092 if (flavour
!= neon_cvt_flavour_invalid
)
19093 inst
.instruction
|= enctab
[flavour
];
19094 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19095 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19096 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19097 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19098 inst
.instruction
|= neon_quad (rs
) << 6;
19099 inst
.instruction
|= 1 << 21;
19100 if (flavour
< neon_cvt_flavour_s16_f16
)
19102 inst
.instruction
|= 1 << 21;
19103 immbits
= 32 - inst
.operands
[2].imm
;
19104 inst
.instruction
|= immbits
<< 16;
19108 inst
.instruction
|= 3 << 20;
19109 immbits
= 16 - inst
.operands
[2].imm
;
19110 inst
.instruction
|= immbits
<< 16;
19111 inst
.instruction
&= ~(1 << 9);
19114 neon_dp_fixup (&inst
);
19119 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19120 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19121 && (flavour
== neon_cvt_flavour_s16_f16
19122 || flavour
== neon_cvt_flavour_u16_f16
19123 || flavour
== neon_cvt_flavour_s32_f32
19124 || flavour
== neon_cvt_flavour_u32_f32
))
19126 if (!check_simd_pred_availability (TRUE
,
19127 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19130 else if (mode
== neon_cvt_mode_z
19131 && (flavour
== neon_cvt_flavour_f16_s16
19132 || flavour
== neon_cvt_flavour_f16_u16
19133 || flavour
== neon_cvt_flavour_s16_f16
19134 || flavour
== neon_cvt_flavour_u16_f16
19135 || flavour
== neon_cvt_flavour_f32_u32
19136 || flavour
== neon_cvt_flavour_f32_s32
19137 || flavour
== neon_cvt_flavour_s32_f32
19138 || flavour
== neon_cvt_flavour_u32_f32
))
19140 if (!check_simd_pred_availability (TRUE
,
19141 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19144 /* fall through. */
19146 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19149 NEON_ENCODE (FLOAT
, inst
);
19150 if (!check_simd_pred_availability (TRUE
,
19151 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19154 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19155 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19156 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19157 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19158 inst
.instruction
|= neon_quad (rs
) << 6;
19159 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19160 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19161 inst
.instruction
|= mode
<< 8;
19162 if (flavour
== neon_cvt_flavour_u16_f16
19163 || flavour
== neon_cvt_flavour_s16_f16
)
19164 /* Mask off the original size bits and reencode them. */
19165 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19168 inst
.instruction
|= 0xfc000000;
19170 inst
.instruction
|= 0xf0000000;
19176 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19177 0x100, 0x180, 0x0, 0x080};
19179 NEON_ENCODE (INTEGER
, inst
);
19181 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19183 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19187 if (flavour
!= neon_cvt_flavour_invalid
)
19188 inst
.instruction
|= enctab
[flavour
];
19190 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19191 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19192 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19193 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19194 inst
.instruction
|= neon_quad (rs
) << 6;
19195 if (flavour
>= neon_cvt_flavour_s16_f16
19196 && flavour
<= neon_cvt_flavour_f16_u16
)
19197 /* Half precision. */
19198 inst
.instruction
|= 1 << 18;
19200 inst
.instruction
|= 2 << 18;
19202 neon_dp_fixup (&inst
);
19207 /* Half-precision conversions for Advanced SIMD -- neon. */
19210 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19214 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19216 as_bad (_("operand size must match register width"));
19221 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19223 as_bad (_("operand size must match register width"));
19229 if (flavour
== neon_cvt_flavour_bf16_f32
)
19231 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19233 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19234 /* VCVT.bf16.f32. */
19235 inst
.instruction
= 0x11b60640;
19238 /* VCVT.f16.f32. */
19239 inst
.instruction
= 0x3b60600;
19242 /* VCVT.f32.f16. */
19243 inst
.instruction
= 0x3b60700;
19245 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19246 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19247 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19248 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19249 neon_dp_fixup (&inst
);
19253 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19254 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19255 do_vfp_nsyn_cvt (rs
, flavour
);
19257 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19262 do_neon_cvtr (void)
19264 do_neon_cvt_1 (neon_cvt_mode_x
);
19270 do_neon_cvt_1 (neon_cvt_mode_z
);
19274 do_neon_cvta (void)
19276 do_neon_cvt_1 (neon_cvt_mode_a
);
19280 do_neon_cvtn (void)
19282 do_neon_cvt_1 (neon_cvt_mode_n
);
19286 do_neon_cvtp (void)
19288 do_neon_cvt_1 (neon_cvt_mode_p
);
19292 do_neon_cvtm (void)
19294 do_neon_cvt_1 (neon_cvt_mode_m
);
19298 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19301 mark_feature_used (&fpu_vfp_ext_armv8
);
19303 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19304 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19305 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19306 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19307 inst
.instruction
|= to
? 0x10000 : 0;
19308 inst
.instruction
|= t
? 0x80 : 0;
19309 inst
.instruction
|= is_double
? 0x100 : 0;
19310 do_vfp_cond_or_thumb ();
19314 do_neon_cvttb_1 (bfd_boolean t
)
19316 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19317 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19321 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19323 int single_to_half
= 0;
19324 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19327 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19329 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19330 && (flavour
== neon_cvt_flavour_u16_f16
19331 || flavour
== neon_cvt_flavour_s16_f16
19332 || flavour
== neon_cvt_flavour_f16_s16
19333 || flavour
== neon_cvt_flavour_f16_u16
19334 || flavour
== neon_cvt_flavour_u32_f32
19335 || flavour
== neon_cvt_flavour_s32_f32
19336 || flavour
== neon_cvt_flavour_f32_s32
19337 || flavour
== neon_cvt_flavour_f32_u32
))
19340 inst
.instruction
= N_MNEM_vcvt
;
19341 set_pred_insn_type (INSIDE_VPT_INSN
);
19342 do_neon_cvt_1 (neon_cvt_mode_z
);
19345 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19346 single_to_half
= 1;
19347 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19349 first_error (BAD_FPU
);
19353 inst
.instruction
= 0xee3f0e01;
19354 inst
.instruction
|= single_to_half
<< 28;
19355 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19356 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19357 inst
.instruction
|= t
<< 12;
19358 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19359 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19362 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19365 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19367 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19370 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19372 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19374 /* The VCVTB and VCVTT instructions with D-register operands
19375 don't work for SP only targets. */
19376 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19380 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19382 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19384 /* The VCVTB and VCVTT instructions with D-register operands
19385 don't work for SP only targets. */
19386 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19390 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19392 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19394 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19396 inst
.instruction
|= (1 << 8);
19397 inst
.instruction
&= ~(1 << 9);
19398 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19405 do_neon_cvtb (void)
19407 do_neon_cvttb_1 (FALSE
);
19412 do_neon_cvtt (void)
19414 do_neon_cvttb_1 (TRUE
);
19418 neon_move_immediate (void)
19420 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19421 struct neon_type_el et
= neon_check_type (2, rs
,
19422 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19423 unsigned immlo
, immhi
= 0, immbits
;
19424 int op
, cmode
, float_p
;
19426 constraint (et
.type
== NT_invtype
,
19427 _("operand size must be specified for immediate VMOV"));
19429 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19430 op
= (inst
.instruction
& (1 << 5)) != 0;
19432 immlo
= inst
.operands
[1].imm
;
19433 if (inst
.operands
[1].regisimm
)
19434 immhi
= inst
.operands
[1].reg
;
19436 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19437 _("immediate has bits set outside the operand size"));
19439 float_p
= inst
.operands
[1].immisfloat
;
19441 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19442 et
.size
, et
.type
)) == FAIL
)
19444 /* Invert relevant bits only. */
19445 neon_invert_size (&immlo
, &immhi
, et
.size
);
19446 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19447 with one or the other; those cases are caught by
19448 neon_cmode_for_move_imm. */
19450 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19451 &op
, et
.size
, et
.type
)) == FAIL
)
19453 first_error (_("immediate out of range"));
19458 inst
.instruction
&= ~(1 << 5);
19459 inst
.instruction
|= op
<< 5;
19461 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19462 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19463 inst
.instruction
|= neon_quad (rs
) << 6;
19464 inst
.instruction
|= cmode
<< 8;
19466 neon_write_immbits (immbits
);
19472 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19475 if (inst
.operands
[1].isreg
)
19477 enum neon_shape rs
;
19478 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19479 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19481 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19483 NEON_ENCODE (INTEGER
, inst
);
19484 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19485 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19486 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19487 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19488 inst
.instruction
|= neon_quad (rs
) << 6;
19492 NEON_ENCODE (IMMED
, inst
);
19493 neon_move_immediate ();
19496 neon_dp_fixup (&inst
);
19498 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19500 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19501 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19502 _("immediate value out of range"));
19506 /* Encode instructions of form:
19508 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19509 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19512 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19514 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19515 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19516 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19517 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19518 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19519 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19520 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19521 inst
.instruction
|= neon_logbits (size
) << 20;
19523 neon_dp_fixup (&inst
);
19527 do_neon_dyadic_long (void)
19529 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19532 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19535 NEON_ENCODE (INTEGER
, inst
);
19536 /* FIXME: Type checking for lengthening op. */
19537 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19538 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19539 neon_mixed_length (et
, et
.size
);
19541 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19542 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19544 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19545 in an IT block with le/lt conditions. */
19547 if (inst
.cond
== 0xf)
19549 else if (inst
.cond
== 0x10)
19552 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19554 if (inst
.instruction
== N_MNEM_vaddl
)
19556 inst
.instruction
= N_MNEM_vadd
;
19557 do_neon_addsub_if_i ();
19559 else if (inst
.instruction
== N_MNEM_vsubl
)
19561 inst
.instruction
= N_MNEM_vsub
;
19562 do_neon_addsub_if_i ();
19564 else if (inst
.instruction
== N_MNEM_vabdl
)
19566 inst
.instruction
= N_MNEM_vabd
;
19567 do_neon_dyadic_if_su ();
19571 first_error (BAD_FPU
);
19575 do_neon_abal (void)
19577 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19578 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19579 neon_mixed_length (et
, et
.size
);
19583 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19585 if (inst
.operands
[2].isscalar
)
19587 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19588 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19589 NEON_ENCODE (SCALAR
, inst
);
19590 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19594 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19595 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19596 NEON_ENCODE (INTEGER
, inst
);
19597 neon_mixed_length (et
, et
.size
);
19602 do_neon_mac_maybe_scalar_long (void)
19604 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19607 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19608 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19611 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19613 unsigned regno
= NEON_SCALAR_REG (scalar
);
19614 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19618 if (regno
> 7 || elno
> 3)
19621 return ((regno
& 0x7)
19622 | ((elno
& 0x1) << 3)
19623 | (((elno
>> 1) & 0x1) << 5));
19627 if (regno
> 15 || elno
> 1)
19630 return (((regno
& 0x1) << 5)
19631 | ((regno
>> 1) & 0x7)
19632 | ((elno
& 0x1) << 3));
19636 first_error (_("scalar out of range for multiply instruction"));
19641 do_neon_fmac_maybe_scalar_long (int subtype
)
19643 enum neon_shape rs
;
19645 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19646 field (bits[21:20]) has different meaning. For scalar index variant, it's
19647 used to differentiate add and subtract, otherwise it's with fixed value
19651 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19652 be a scalar index register. */
19653 if (inst
.operands
[2].isscalar
)
19655 high8
= 0xfe000000;
19658 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19662 high8
= 0xfc000000;
19665 inst
.instruction
|= (0x1 << 23);
19666 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19670 if (inst
.cond
!= COND_ALWAYS
)
19671 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19672 "behaviour is UNPREDICTABLE"));
19674 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19677 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19680 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19681 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19682 so we simply pass -1 as size. */
19683 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19684 neon_three_same (quad_p
, 0, size
);
19686 /* Undo neon_dp_fixup. Redo the high eight bits. */
19687 inst
.instruction
&= 0x00ffffff;
19688 inst
.instruction
|= high8
;
19690 #define LOW1(R) ((R) & 0x1)
19691 #define HI4(R) (((R) >> 1) & 0xf)
19692 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19693 whether the instruction is in Q form and whether Vm is a scalar indexed
19695 if (inst
.operands
[2].isscalar
)
19698 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19699 inst
.instruction
&= 0xffffffd0;
19700 inst
.instruction
|= rm
;
19704 /* Redo Rn as well. */
19705 inst
.instruction
&= 0xfff0ff7f;
19706 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19707 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19712 /* Redo Rn and Rm. */
19713 inst
.instruction
&= 0xfff0ff50;
19714 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19715 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19716 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19717 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19722 do_neon_vfmal (void)
19724 return do_neon_fmac_maybe_scalar_long (0);
19728 do_neon_vfmsl (void)
19730 return do_neon_fmac_maybe_scalar_long (1);
19734 do_neon_dyadic_wide (void)
19736 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19737 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19738 neon_mixed_length (et
, et
.size
);
19742 do_neon_dyadic_narrow (void)
19744 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19745 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19746 /* Operand sign is unimportant, and the U bit is part of the opcode,
19747 so force the operand type to integer. */
19748 et
.type
= NT_integer
;
19749 neon_mixed_length (et
, et
.size
/ 2);
19753 do_neon_mul_sat_scalar_long (void)
19755 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19759 do_neon_vmull (void)
19761 if (inst
.operands
[2].isscalar
)
19762 do_neon_mac_maybe_scalar_long ();
19765 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19766 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19768 if (et
.type
== NT_poly
)
19769 NEON_ENCODE (POLY
, inst
);
19771 NEON_ENCODE (INTEGER
, inst
);
19773 /* For polynomial encoding the U bit must be zero, and the size must
19774 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19775 obviously, as 0b10). */
19778 /* Check we're on the correct architecture. */
19779 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19781 _("Instruction form not available on this architecture.");
19786 neon_mixed_length (et
, et
.size
);
19793 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19794 struct neon_type_el et
= neon_check_type (3, rs
,
19795 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19796 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19798 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19799 _("shift out of range"));
19800 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19801 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19802 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19803 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19804 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19805 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19806 inst
.instruction
|= neon_quad (rs
) << 6;
19807 inst
.instruction
|= imm
<< 8;
19809 neon_dp_fixup (&inst
);
19815 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19818 enum neon_shape rs
;
19819 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19820 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19822 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19824 struct neon_type_el et
= neon_check_type (2, rs
,
19825 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19827 unsigned op
= (inst
.instruction
>> 7) & 3;
19828 /* N (width of reversed regions) is encoded as part of the bitmask. We
19829 extract it here to check the elements to be reversed are smaller.
19830 Otherwise we'd get a reserved instruction. */
19831 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19833 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19834 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19835 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19836 " operands makes instruction UNPREDICTABLE"));
19838 gas_assert (elsize
!= 0);
19839 constraint (et
.size
>= elsize
,
19840 _("elements must be smaller than reversal region"));
19841 neon_two_same (neon_quad (rs
), 1, et
.size
);
19847 if (inst
.operands
[1].isscalar
)
19849 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19851 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19852 struct neon_type_el et
= neon_check_type (2, rs
,
19853 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19854 unsigned sizebits
= et
.size
>> 3;
19855 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19856 int logsize
= neon_logbits (et
.size
);
19857 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19859 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19862 NEON_ENCODE (SCALAR
, inst
);
19863 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19864 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19865 inst
.instruction
|= LOW4 (dm
);
19866 inst
.instruction
|= HI1 (dm
) << 5;
19867 inst
.instruction
|= neon_quad (rs
) << 6;
19868 inst
.instruction
|= x
<< 17;
19869 inst
.instruction
|= sizebits
<< 16;
19871 neon_dp_fixup (&inst
);
19875 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19876 struct neon_type_el et
= neon_check_type (2, rs
,
19877 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19880 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19884 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19887 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19889 if (inst
.operands
[1].reg
== REG_SP
)
19890 as_tsktsk (MVE_BAD_SP
);
19891 else if (inst
.operands
[1].reg
== REG_PC
)
19892 as_tsktsk (MVE_BAD_PC
);
19895 /* Duplicate ARM register to lanes of vector. */
19896 NEON_ENCODE (ARMREG
, inst
);
19899 case 8: inst
.instruction
|= 0x400000; break;
19900 case 16: inst
.instruction
|= 0x000020; break;
19901 case 32: inst
.instruction
|= 0x000000; break;
19904 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19905 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19906 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19907 inst
.instruction
|= neon_quad (rs
) << 21;
19908 /* The encoding for this instruction is identical for the ARM and Thumb
19909 variants, except for the condition field. */
19910 do_vfp_cond_or_thumb ();
19915 do_mve_mov (int toQ
)
19917 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19919 if (inst
.cond
> COND_ALWAYS
)
19920 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19922 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19931 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19932 _("Index one must be [2,3] and index two must be two less than"
19934 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19935 _("General purpose registers may not be the same"));
19936 constraint (inst
.operands
[Rt
].reg
== REG_SP
19937 || inst
.operands
[Rt2
].reg
== REG_SP
,
19939 constraint (inst
.operands
[Rt
].reg
== REG_PC
19940 || inst
.operands
[Rt2
].reg
== REG_PC
,
19943 inst
.instruction
= 0xec000f00;
19944 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19945 inst
.instruction
|= !!toQ
<< 20;
19946 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19947 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19948 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19949 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19955 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19958 if (inst
.cond
> COND_ALWAYS
)
19959 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19961 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19963 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19966 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19967 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19968 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19969 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19970 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19975 /* VMOV has particularly many variations. It can be one of:
19976 0. VMOV<c><q> <Qd>, <Qm>
19977 1. VMOV<c><q> <Dd>, <Dm>
19978 (Register operations, which are VORR with Rm = Rn.)
19979 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19980 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19982 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19983 (ARM register to scalar.)
19984 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19985 (Two ARM registers to vector.)
19986 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19987 (Scalar to ARM register.)
19988 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19989 (Vector to two ARM registers.)
19990 8. VMOV.F32 <Sd>, <Sm>
19991 9. VMOV.F64 <Dd>, <Dm>
19992 (VFP register moves.)
19993 10. VMOV.F32 <Sd>, #imm
19994 11. VMOV.F64 <Dd>, #imm
19995 (VFP float immediate load.)
19996 12. VMOV <Rd>, <Sm>
19997 (VFP single to ARM reg.)
19998 13. VMOV <Sd>, <Rm>
19999 (ARM reg to VFP single.)
20000 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20001 (Two ARM regs to two VFP singles.)
20002 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20003 (Two VFP singles to two ARM regs.)
20004 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20005 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20006 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20007 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20009 These cases can be disambiguated using neon_select_shape, except cases 1/9
20010 and 3/11 which depend on the operand type too.
20012 All the encoded bits are hardcoded by this function.
20014 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20015 Cases 5, 7 may be used with VFPv2 and above.
20017 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20018 can specify a type where it doesn't make sense to, and is ignored). */
20023 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20024 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20025 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20026 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20028 struct neon_type_el et
;
20029 const char *ldconst
= 0;
20033 case NS_DD
: /* case 1/9. */
20034 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20035 /* It is not an error here if no type is given. */
20038 /* In MVE we interpret the following instructions as same, so ignoring
20039 the following type (float) and size (64) checks.
20040 a: VMOV<c><q> <Dd>, <Dm>
20041 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20042 if ((et
.type
== NT_float
&& et
.size
== 64)
20043 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20045 do_vfp_nsyn_opcode ("fcpyd");
20048 /* fall through. */
20050 case NS_QQ
: /* case 0/1. */
20052 if (!check_simd_pred_availability (FALSE
,
20053 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20055 /* The architecture manual I have doesn't explicitly state which
20056 value the U bit should have for register->register moves, but
20057 the equivalent VORR instruction has U = 0, so do that. */
20058 inst
.instruction
= 0x0200110;
20059 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20060 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20061 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20062 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20063 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20064 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20065 inst
.instruction
|= neon_quad (rs
) << 6;
20067 neon_dp_fixup (&inst
);
20071 case NS_DI
: /* case 3/11. */
20072 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20074 if (et
.type
== NT_float
&& et
.size
== 64)
20076 /* case 11 (fconstd). */
20077 ldconst
= "fconstd";
20078 goto encode_fconstd
;
20080 /* fall through. */
20082 case NS_QI
: /* case 2/3. */
20083 if (!check_simd_pred_availability (FALSE
,
20084 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20086 inst
.instruction
= 0x0800010;
20087 neon_move_immediate ();
20088 neon_dp_fixup (&inst
);
20091 case NS_SR
: /* case 4. */
20093 unsigned bcdebits
= 0;
20095 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20096 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20098 /* .<size> is optional here, defaulting to .32. */
20099 if (inst
.vectype
.elems
== 0
20100 && inst
.operands
[0].vectype
.type
== NT_invtype
20101 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20103 inst
.vectype
.el
[0].type
= NT_untyped
;
20104 inst
.vectype
.el
[0].size
= 32;
20105 inst
.vectype
.elems
= 1;
20108 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20109 logsize
= neon_logbits (et
.size
);
20113 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20114 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20119 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20120 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20124 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20126 if (inst
.operands
[1].reg
== REG_SP
)
20127 as_tsktsk (MVE_BAD_SP
);
20128 else if (inst
.operands
[1].reg
== REG_PC
)
20129 as_tsktsk (MVE_BAD_PC
);
20131 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20133 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20134 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20139 case 8: bcdebits
= 0x8; break;
20140 case 16: bcdebits
= 0x1; break;
20141 case 32: bcdebits
= 0x0; break;
20145 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20147 inst
.instruction
= 0xe000b10;
20148 do_vfp_cond_or_thumb ();
20149 inst
.instruction
|= LOW4 (dn
) << 16;
20150 inst
.instruction
|= HI1 (dn
) << 7;
20151 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20152 inst
.instruction
|= (bcdebits
& 3) << 5;
20153 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20154 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20158 case NS_DRR
: /* case 5 (fmdrr). */
20159 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20160 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20163 inst
.instruction
= 0xc400b10;
20164 do_vfp_cond_or_thumb ();
20165 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20166 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20167 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20168 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20171 case NS_RS
: /* case 6. */
20174 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20175 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20176 unsigned abcdebits
= 0;
20178 /* .<dt> is optional here, defaulting to .32. */
20179 if (inst
.vectype
.elems
== 0
20180 && inst
.operands
[0].vectype
.type
== NT_invtype
20181 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20183 inst
.vectype
.el
[0].type
= NT_untyped
;
20184 inst
.vectype
.el
[0].size
= 32;
20185 inst
.vectype
.elems
= 1;
20188 et
= neon_check_type (2, NS_NULL
,
20189 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20190 logsize
= neon_logbits (et
.size
);
20194 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20195 && vfp_or_neon_is_neon (NEON_CHECK_CC
20196 | NEON_CHECK_ARCH
) == FAIL
)
20201 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20202 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20206 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20208 if (inst
.operands
[0].reg
== REG_SP
)
20209 as_tsktsk (MVE_BAD_SP
);
20210 else if (inst
.operands
[0].reg
== REG_PC
)
20211 as_tsktsk (MVE_BAD_PC
);
20214 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20216 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20217 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20221 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20222 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20223 case 32: abcdebits
= 0x00; break;
20227 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20228 inst
.instruction
= 0xe100b10;
20229 do_vfp_cond_or_thumb ();
20230 inst
.instruction
|= LOW4 (dn
) << 16;
20231 inst
.instruction
|= HI1 (dn
) << 7;
20232 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20233 inst
.instruction
|= (abcdebits
& 3) << 5;
20234 inst
.instruction
|= (abcdebits
>> 2) << 21;
20235 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20239 case NS_RRD
: /* case 7 (fmrrd). */
20240 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20241 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20244 inst
.instruction
= 0xc500b10;
20245 do_vfp_cond_or_thumb ();
20246 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20247 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20248 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20249 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20252 case NS_FF
: /* case 8 (fcpys). */
20253 do_vfp_nsyn_opcode ("fcpys");
20257 case NS_FI
: /* case 10 (fconsts). */
20258 ldconst
= "fconsts";
20260 if (!inst
.operands
[1].immisfloat
)
20263 /* Immediate has to fit in 8 bits so float is enough. */
20264 float imm
= (float) inst
.operands
[1].imm
;
20265 memcpy (&new_imm
, &imm
, sizeof (float));
20266 /* But the assembly may have been written to provide an integer
20267 bit pattern that equates to a float, so check that the
20268 conversion has worked. */
20269 if (is_quarter_float (new_imm
))
20271 if (is_quarter_float (inst
.operands
[1].imm
))
20272 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20274 inst
.operands
[1].imm
= new_imm
;
20275 inst
.operands
[1].immisfloat
= 1;
20279 if (is_quarter_float (inst
.operands
[1].imm
))
20281 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20282 do_vfp_nsyn_opcode (ldconst
);
20284 /* ARMv8.2 fp16 vmov.f16 instruction. */
20286 do_scalar_fp16_v82_encode ();
20289 first_error (_("immediate out of range"));
20293 case NS_RF
: /* case 12 (fmrs). */
20294 do_vfp_nsyn_opcode ("fmrs");
20295 /* ARMv8.2 fp16 vmov.f16 instruction. */
20297 do_scalar_fp16_v82_encode ();
20301 case NS_FR
: /* case 13 (fmsr). */
20302 do_vfp_nsyn_opcode ("fmsr");
20303 /* ARMv8.2 fp16 vmov.f16 instruction. */
20305 do_scalar_fp16_v82_encode ();
20315 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20316 (one of which is a list), but we have parsed four. Do some fiddling to
20317 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20319 case NS_RRFF
: /* case 14 (fmrrs). */
20320 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20321 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20323 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20324 _("VFP registers must be adjacent"));
20325 inst
.operands
[2].imm
= 2;
20326 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20327 do_vfp_nsyn_opcode ("fmrrs");
20330 case NS_FFRR
: /* case 15 (fmsrr). */
20331 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20332 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20334 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20335 _("VFP registers must be adjacent"));
20336 inst
.operands
[1] = inst
.operands
[2];
20337 inst
.operands
[2] = inst
.operands
[3];
20338 inst
.operands
[0].imm
= 2;
20339 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20340 do_vfp_nsyn_opcode ("fmsrr");
20344 /* neon_select_shape has determined that the instruction
20345 shape is wrong and has already set the error message. */
20356 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20357 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20358 && !inst
.operands
[2].present
))
20360 inst
.instruction
= 0;
20363 set_pred_insn_type (INSIDE_IT_INSN
);
20368 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20371 if (inst
.cond
!= COND_ALWAYS
)
20372 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20374 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20375 | N_S16
| N_U16
| N_KEY
);
20377 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20378 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20379 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20380 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20381 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20382 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20387 do_neon_rshift_round_imm (void)
20389 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20392 enum neon_shape rs
;
20393 struct neon_type_el et
;
20395 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20397 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20398 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20402 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20403 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20405 int imm
= inst
.operands
[2].imm
;
20407 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20410 inst
.operands
[2].present
= 0;
20415 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20416 _("immediate out of range for shift"));
20417 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20422 do_neon_movhf (void)
20424 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20425 constraint (rs
!= NS_HH
, _("invalid suffix"));
20427 if (inst
.cond
!= COND_ALWAYS
)
20431 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20432 " the behaviour is UNPREDICTABLE"));
20436 inst
.error
= BAD_COND
;
20441 do_vfp_sp_monadic ();
20444 inst
.instruction
|= 0xf0000000;
20448 do_neon_movl (void)
20450 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20451 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20452 unsigned sizebits
= et
.size
>> 3;
20453 inst
.instruction
|= sizebits
<< 19;
20454 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20460 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20461 struct neon_type_el et
= neon_check_type (2, rs
,
20462 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20463 NEON_ENCODE (INTEGER
, inst
);
20464 neon_two_same (neon_quad (rs
), 1, et
.size
);
20468 do_neon_zip_uzp (void)
20470 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20471 struct neon_type_el et
= neon_check_type (2, rs
,
20472 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20473 if (rs
== NS_DD
&& et
.size
== 32)
20475 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20476 inst
.instruction
= N_MNEM_vtrn
;
20480 neon_two_same (neon_quad (rs
), 1, et
.size
);
20484 do_neon_sat_abs_neg (void)
20486 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20489 enum neon_shape rs
;
20490 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20491 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20493 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20494 struct neon_type_el et
= neon_check_type (2, rs
,
20495 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20496 neon_two_same (neon_quad (rs
), 1, et
.size
);
20500 do_neon_pair_long (void)
20502 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20503 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20504 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20505 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20506 neon_two_same (neon_quad (rs
), 1, et
.size
);
20510 do_neon_recip_est (void)
20512 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20513 struct neon_type_el et
= neon_check_type (2, rs
,
20514 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20515 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20516 neon_two_same (neon_quad (rs
), 1, et
.size
);
20522 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20525 enum neon_shape rs
;
20526 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20527 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20529 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20531 struct neon_type_el et
= neon_check_type (2, rs
,
20532 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20533 neon_two_same (neon_quad (rs
), 1, et
.size
);
20539 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20542 enum neon_shape rs
;
20543 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20544 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20546 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20548 struct neon_type_el et
= neon_check_type (2, rs
,
20549 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20550 neon_two_same (neon_quad (rs
), 1, et
.size
);
20556 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20557 struct neon_type_el et
= neon_check_type (2, rs
,
20558 N_EQK
| N_INT
, N_8
| N_KEY
);
20559 neon_two_same (neon_quad (rs
), 1, et
.size
);
20565 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20566 neon_two_same (neon_quad (rs
), 1, -1);
20570 do_neon_tbl_tbx (void)
20572 unsigned listlenbits
;
20573 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20575 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20577 first_error (_("bad list length for table lookup"));
20581 listlenbits
= inst
.operands
[1].imm
- 1;
20582 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20583 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20584 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20585 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20586 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20587 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20588 inst
.instruction
|= listlenbits
<< 8;
20590 neon_dp_fixup (&inst
);
20594 do_neon_ldm_stm (void)
20596 /* P, U and L bits are part of bitmask. */
20597 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20598 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20600 if (inst
.operands
[1].issingle
)
20602 do_vfp_nsyn_ldm_stm (is_dbmode
);
20606 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20607 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20609 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20610 _("register list must contain at least 1 and at most 16 "
20613 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20614 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20615 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20616 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20618 inst
.instruction
|= offsetbits
;
20620 do_vfp_cond_or_thumb ();
20624 do_neon_ldr_str (void)
20626 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20628 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20629 And is UNPREDICTABLE in thumb mode. */
20631 && inst
.operands
[1].reg
== REG_PC
20632 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20635 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20636 else if (warn_on_deprecated
)
20637 as_tsktsk (_("Use of PC here is deprecated"));
20640 if (inst
.operands
[0].issingle
)
20643 do_vfp_nsyn_opcode ("flds");
20645 do_vfp_nsyn_opcode ("fsts");
20647 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20648 if (inst
.vectype
.el
[0].size
== 16)
20649 do_scalar_fp16_v82_encode ();
20654 do_vfp_nsyn_opcode ("fldd");
20656 do_vfp_nsyn_opcode ("fstd");
20661 do_t_vldr_vstr_sysreg (void)
20663 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20664 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20666 /* Use of PC is UNPREDICTABLE. */
20667 if (inst
.operands
[1].reg
== REG_PC
)
20668 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20670 if (inst
.operands
[1].immisreg
)
20671 inst
.error
= _("instruction does not accept register index");
20673 if (!inst
.operands
[1].isreg
)
20674 inst
.error
= _("instruction does not accept PC-relative addressing");
20676 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20677 inst
.error
= _("immediate value out of range");
20679 inst
.instruction
= 0xec000f80;
20681 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20682 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20683 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20684 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20688 do_vldr_vstr (void)
20690 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20692 /* VLDR/VSTR (System Register). */
20695 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20696 as_bad (_("Instruction not permitted on this architecture"));
20698 do_t_vldr_vstr_sysreg ();
20703 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20704 as_bad (_("Instruction not permitted on this architecture"));
20705 do_neon_ldr_str ();
20709 /* "interleave" version also handles non-interleaving register VLD1/VST1
20713 do_neon_ld_st_interleave (void)
20715 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20716 N_8
| N_16
| N_32
| N_64
);
20717 unsigned alignbits
= 0;
20719 /* The bits in this table go:
20720 0: register stride of one (0) or two (1)
20721 1,2: register list length, minus one (1, 2, 3, 4).
20722 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20723 We use -1 for invalid entries. */
20724 const int typetable
[] =
20726 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20727 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20728 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20729 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20733 if (et
.type
== NT_invtype
)
20736 if (inst
.operands
[1].immisalign
)
20737 switch (inst
.operands
[1].imm
>> 8)
20739 case 64: alignbits
= 1; break;
20741 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20742 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20743 goto bad_alignment
;
20747 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20748 goto bad_alignment
;
20753 first_error (_("bad alignment"));
20757 inst
.instruction
|= alignbits
<< 4;
20758 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20760 /* Bits [4:6] of the immediate in a list specifier encode register stride
20761 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20762 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20763 up the right value for "type" in a table based on this value and the given
20764 list style, then stick it back. */
20765 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20766 | (((inst
.instruction
>> 8) & 3) << 3);
20768 typebits
= typetable
[idx
];
20770 constraint (typebits
== -1, _("bad list type for instruction"));
20771 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20774 inst
.instruction
&= ~0xf00;
20775 inst
.instruction
|= typebits
<< 8;
20778 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20779 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20780 otherwise. The variable arguments are a list of pairs of legal (size, align)
20781 values, terminated with -1. */
20784 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20787 int result
= FAIL
, thissize
, thisalign
;
20789 if (!inst
.operands
[1].immisalign
)
20795 va_start (ap
, do_alignment
);
20799 thissize
= va_arg (ap
, int);
20800 if (thissize
== -1)
20802 thisalign
= va_arg (ap
, int);
20804 if (size
== thissize
&& align
== thisalign
)
20807 while (result
!= SUCCESS
);
20811 if (result
== SUCCESS
)
20814 first_error (_("unsupported alignment for instruction"));
20820 do_neon_ld_st_lane (void)
20822 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20823 int align_good
, do_alignment
= 0;
20824 int logsize
= neon_logbits (et
.size
);
20825 int align
= inst
.operands
[1].imm
>> 8;
20826 int n
= (inst
.instruction
>> 8) & 3;
20827 int max_el
= 64 / et
.size
;
20829 if (et
.type
== NT_invtype
)
20832 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20833 _("bad list length"));
20834 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20835 _("scalar index out of range"));
20836 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20838 _("stride of 2 unavailable when element size is 8"));
20842 case 0: /* VLD1 / VST1. */
20843 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20845 if (align_good
== FAIL
)
20849 unsigned alignbits
= 0;
20852 case 16: alignbits
= 0x1; break;
20853 case 32: alignbits
= 0x3; break;
20856 inst
.instruction
|= alignbits
<< 4;
20860 case 1: /* VLD2 / VST2. */
20861 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20862 16, 32, 32, 64, -1);
20863 if (align_good
== FAIL
)
20866 inst
.instruction
|= 1 << 4;
20869 case 2: /* VLD3 / VST3. */
20870 constraint (inst
.operands
[1].immisalign
,
20871 _("can't use alignment with this instruction"));
20874 case 3: /* VLD4 / VST4. */
20875 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20876 16, 64, 32, 64, 32, 128, -1);
20877 if (align_good
== FAIL
)
20881 unsigned alignbits
= 0;
20884 case 8: alignbits
= 0x1; break;
20885 case 16: alignbits
= 0x1; break;
20886 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20889 inst
.instruction
|= alignbits
<< 4;
20896 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20897 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20898 inst
.instruction
|= 1 << (4 + logsize
);
20900 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20901 inst
.instruction
|= logsize
<< 10;
20904 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20907 do_neon_ld_dup (void)
20909 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20910 int align_good
, do_alignment
= 0;
20912 if (et
.type
== NT_invtype
)
20915 switch ((inst
.instruction
>> 8) & 3)
20917 case 0: /* VLD1. */
20918 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20919 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20920 &do_alignment
, 16, 16, 32, 32, -1);
20921 if (align_good
== FAIL
)
20923 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20926 case 2: inst
.instruction
|= 1 << 5; break;
20927 default: first_error (_("bad list length")); return;
20929 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20932 case 1: /* VLD2. */
20933 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20934 &do_alignment
, 8, 16, 16, 32, 32, 64,
20936 if (align_good
== FAIL
)
20938 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20939 _("bad list length"));
20940 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20941 inst
.instruction
|= 1 << 5;
20942 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20945 case 2: /* VLD3. */
20946 constraint (inst
.operands
[1].immisalign
,
20947 _("can't use alignment with this instruction"));
20948 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20949 _("bad list length"));
20950 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20951 inst
.instruction
|= 1 << 5;
20952 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20955 case 3: /* VLD4. */
20957 int align
= inst
.operands
[1].imm
>> 8;
20958 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20959 16, 64, 32, 64, 32, 128, -1);
20960 if (align_good
== FAIL
)
20962 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20963 _("bad list length"));
20964 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20965 inst
.instruction
|= 1 << 5;
20966 if (et
.size
== 32 && align
== 128)
20967 inst
.instruction
|= 0x3 << 6;
20969 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20976 inst
.instruction
|= do_alignment
<< 4;
20979 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20980 apart from bits [11:4]. */
20983 do_neon_ldx_stx (void)
20985 if (inst
.operands
[1].isreg
)
20986 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20988 switch (NEON_LANE (inst
.operands
[0].imm
))
20990 case NEON_INTERLEAVE_LANES
:
20991 NEON_ENCODE (INTERLV
, inst
);
20992 do_neon_ld_st_interleave ();
20995 case NEON_ALL_LANES
:
20996 NEON_ENCODE (DUP
, inst
);
20997 if (inst
.instruction
== N_INV
)
20999 first_error ("only loads support such operands");
21006 NEON_ENCODE (LANE
, inst
);
21007 do_neon_ld_st_lane ();
21010 /* L bit comes from bit mask. */
21011 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21012 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21013 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21015 if (inst
.operands
[1].postind
)
21017 int postreg
= inst
.operands
[1].imm
& 0xf;
21018 constraint (!inst
.operands
[1].immisreg
,
21019 _("post-index must be a register"));
21020 constraint (postreg
== 0xd || postreg
== 0xf,
21021 _("bad register for post-index"));
21022 inst
.instruction
|= postreg
;
21026 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21027 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21028 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21031 if (inst
.operands
[1].writeback
)
21033 inst
.instruction
|= 0xd;
21036 inst
.instruction
|= 0xf;
21040 inst
.instruction
|= 0xf9000000;
21042 inst
.instruction
|= 0xf4000000;
21047 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21049 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21050 D register operands. */
21051 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21052 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21055 NEON_ENCODE (FPV8
, inst
);
21057 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21059 do_vfp_sp_dyadic ();
21061 /* ARMv8.2 fp16 instruction. */
21063 do_scalar_fp16_v82_encode ();
21066 do_vfp_dp_rd_rn_rm ();
21069 inst
.instruction
|= 0x100;
21071 inst
.instruction
|= 0xf0000000;
21077 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21079 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21080 first_error (_("invalid instruction shape"));
21086 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21087 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21089 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21092 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21095 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21099 do_vrint_1 (enum neon_cvt_mode mode
)
21101 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21102 struct neon_type_el et
;
21107 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21108 D register operands. */
21109 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21110 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21113 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21115 if (et
.type
!= NT_invtype
)
21117 /* VFP encodings. */
21118 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21119 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21120 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21122 NEON_ENCODE (FPV8
, inst
);
21123 if (rs
== NS_FF
|| rs
== NS_HH
)
21124 do_vfp_sp_monadic ();
21126 do_vfp_dp_rd_rm ();
21130 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21131 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21132 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21133 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21134 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21135 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21136 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21140 inst
.instruction
|= (rs
== NS_DD
) << 8;
21141 do_vfp_cond_or_thumb ();
21143 /* ARMv8.2 fp16 vrint instruction. */
21145 do_scalar_fp16_v82_encode ();
21149 /* Neon encodings (or something broken...). */
21151 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21153 if (et
.type
== NT_invtype
)
21156 if (!check_simd_pred_availability (TRUE
,
21157 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21160 NEON_ENCODE (FLOAT
, inst
);
21162 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21163 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21164 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21165 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21166 inst
.instruction
|= neon_quad (rs
) << 6;
21167 /* Mask off the original size bits and reencode them. */
21168 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21169 | neon_logbits (et
.size
) << 18);
21173 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21174 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21175 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21176 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21177 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21178 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21179 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21184 inst
.instruction
|= 0xfc000000;
21186 inst
.instruction
|= 0xf0000000;
21193 do_vrint_1 (neon_cvt_mode_x
);
21199 do_vrint_1 (neon_cvt_mode_z
);
21205 do_vrint_1 (neon_cvt_mode_r
);
21211 do_vrint_1 (neon_cvt_mode_a
);
21217 do_vrint_1 (neon_cvt_mode_n
);
21223 do_vrint_1 (neon_cvt_mode_p
);
21229 do_vrint_1 (neon_cvt_mode_m
);
21233 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21235 unsigned regno
= NEON_SCALAR_REG (opnd
);
21236 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21238 if (elsize
== 16 && elno
< 2 && regno
< 16)
21239 return regno
| (elno
<< 4);
21240 else if (elsize
== 32 && elno
== 0)
21243 first_error (_("scalar out of range"));
21250 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21251 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21252 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21253 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21254 _("expression too complex"));
21255 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21256 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21257 _("immediate out of range"));
21260 if (!check_simd_pred_availability (TRUE
,
21261 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21264 if (inst
.operands
[2].isscalar
)
21266 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21267 first_error (_("invalid instruction shape"));
21268 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21269 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21270 N_KEY
| N_F16
| N_F32
).size
;
21271 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21273 inst
.instruction
= 0xfe000800;
21274 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21275 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21276 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21277 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21278 inst
.instruction
|= LOW4 (m
);
21279 inst
.instruction
|= HI1 (m
) << 5;
21280 inst
.instruction
|= neon_quad (rs
) << 6;
21281 inst
.instruction
|= rot
<< 20;
21282 inst
.instruction
|= (size
== 32) << 23;
21286 enum neon_shape rs
;
21287 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21288 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21290 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21292 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21293 N_KEY
| N_F16
| N_F32
).size
;
21294 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21295 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21296 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21297 as_tsktsk (BAD_MVE_SRCDEST
);
21299 neon_three_same (neon_quad (rs
), 0, -1);
21300 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21301 inst
.instruction
|= 0xfc200800;
21302 inst
.instruction
|= rot
<< 23;
21303 inst
.instruction
|= (size
== 32) << 20;
21310 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21311 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21312 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21313 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21314 _("expression too complex"));
21316 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21317 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21318 enum neon_shape rs
;
21319 struct neon_type_el et
;
21320 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21322 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21323 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21327 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21328 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21330 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21331 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21332 "operand makes instruction UNPREDICTABLE"));
21335 if (et
.type
== NT_invtype
)
21338 if (!check_simd_pred_availability (et
.type
== NT_float
,
21339 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21342 if (et
.type
== NT_float
)
21344 neon_three_same (neon_quad (rs
), 0, -1);
21345 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21346 inst
.instruction
|= 0xfc800800;
21347 inst
.instruction
|= (rot
== 270) << 24;
21348 inst
.instruction
|= (et
.size
== 32) << 20;
21352 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21353 inst
.instruction
= 0xfe000f00;
21354 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21355 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21356 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21357 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21358 inst
.instruction
|= (rot
== 270) << 12;
21359 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21360 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21361 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21366 /* Dot Product instructions encoding support. */
21369 do_neon_dotproduct (int unsigned_p
)
21371 enum neon_shape rs
;
21372 unsigned scalar_oprd2
= 0;
21375 if (inst
.cond
!= COND_ALWAYS
)
21376 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21377 "is UNPREDICTABLE"));
21379 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21382 /* Dot Product instructions are in three-same D/Q register format or the third
21383 operand can be a scalar index register. */
21384 if (inst
.operands
[2].isscalar
)
21386 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21387 high8
= 0xfe000000;
21388 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21392 high8
= 0xfc000000;
21393 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21397 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21399 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21401 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21402 Product instruction, so we pass 0 as the "ubit" parameter. And the
21403 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21404 neon_three_same (neon_quad (rs
), 0, 32);
21406 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21407 different NEON three-same encoding. */
21408 inst
.instruction
&= 0x00ffffff;
21409 inst
.instruction
|= high8
;
21410 /* Encode 'U' bit which indicates signedness. */
21411 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21412 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21413 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21414 the instruction encoding. */
21415 if (inst
.operands
[2].isscalar
)
21417 inst
.instruction
&= 0xffffffd0;
21418 inst
.instruction
|= LOW4 (scalar_oprd2
);
21419 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21423 /* Dot Product instructions for signed integer. */
21426 do_neon_dotproduct_s (void)
21428 return do_neon_dotproduct (0);
21431 /* Dot Product instructions for unsigned integer. */
21434 do_neon_dotproduct_u (void)
21436 return do_neon_dotproduct (1);
21439 /* Crypto v1 instructions. */
21441 do_crypto_2op_1 (unsigned elttype
, int op
)
21443 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21445 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21451 NEON_ENCODE (INTEGER
, inst
);
21452 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21453 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21454 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21455 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21457 inst
.instruction
|= op
<< 6;
21460 inst
.instruction
|= 0xfc000000;
21462 inst
.instruction
|= 0xf0000000;
21466 do_crypto_3op_1 (int u
, int op
)
21468 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21470 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21471 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21476 NEON_ENCODE (INTEGER
, inst
);
21477 neon_three_same (1, u
, 8 << op
);
21483 do_crypto_2op_1 (N_8
, 0);
21489 do_crypto_2op_1 (N_8
, 1);
21495 do_crypto_2op_1 (N_8
, 2);
21501 do_crypto_2op_1 (N_8
, 3);
21507 do_crypto_3op_1 (0, 0);
21513 do_crypto_3op_1 (0, 1);
21519 do_crypto_3op_1 (0, 2);
21525 do_crypto_3op_1 (0, 3);
21531 do_crypto_3op_1 (1, 0);
21537 do_crypto_3op_1 (1, 1);
21541 do_sha256su1 (void)
21543 do_crypto_3op_1 (1, 2);
21549 do_crypto_2op_1 (N_32
, -1);
21555 do_crypto_2op_1 (N_32
, 0);
21559 do_sha256su0 (void)
21561 do_crypto_2op_1 (N_32
, 1);
21565 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21567 unsigned int Rd
= inst
.operands
[0].reg
;
21568 unsigned int Rn
= inst
.operands
[1].reg
;
21569 unsigned int Rm
= inst
.operands
[2].reg
;
21571 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21572 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21573 inst
.instruction
|= LOW4 (Rn
) << 16;
21574 inst
.instruction
|= LOW4 (Rm
);
21575 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21576 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21578 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21579 as_warn (UNPRED_REG ("r15"));
21621 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21623 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21624 do_vfp_sp_dp_cvt ();
21625 do_vfp_cond_or_thumb ();
21631 enum neon_shape rs
;
21632 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
21633 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21634 if (inst
.operands
[2].isscalar
)
21636 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21637 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
21639 inst
.instruction
|= (1 << 25);
21640 int index
= inst
.operands
[2].reg
& 0xf;
21641 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21642 inst
.operands
[2].reg
>>= 4;
21643 constraint (!(inst
.operands
[2].reg
< 16),
21644 _("indexed register must be less than 16"));
21645 neon_three_args (rs
== NS_QQS
);
21646 inst
.instruction
|= (index
<< 5);
21650 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21651 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
21652 neon_three_args (rs
== NS_QQQ
);
21659 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21660 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
21662 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
21663 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21665 neon_three_args (1);
21669 /* Overall per-instruction processing. */
21671 /* We need to be able to fix up arbitrary expressions in some statements.
21672 This is so that we can handle symbols that are an arbitrary distance from
21673 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21674 which returns part of an address in a form which will be valid for
21675 a data instruction. We do this by pushing the expression into a symbol
21676 in the expr_section, and creating a fix for that. */
21679 fix_new_arm (fragS
* frag
,
21693 /* Create an absolute valued symbol, so we have something to
21694 refer to in the object file. Unfortunately for us, gas's
21695 generic expression parsing will already have folded out
21696 any use of .set foo/.type foo %function that may have
21697 been used to set type information of the target location,
21698 that's being specified symbolically. We have to presume
21699 the user knows what they are doing. */
21703 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21705 symbol
= symbol_find_or_make (name
);
21706 S_SET_SEGMENT (symbol
, absolute_section
);
21707 symbol_set_frag (symbol
, &zero_address_frag
);
21708 S_SET_VALUE (symbol
, exp
->X_add_number
);
21709 exp
->X_op
= O_symbol
;
21710 exp
->X_add_symbol
= symbol
;
21711 exp
->X_add_number
= 0;
21717 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21718 (enum bfd_reloc_code_real
) reloc
);
21722 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21723 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21727 /* Mark whether the fix is to a THUMB instruction, or an ARM
21729 new_fix
->tc_fix_data
= thumb_mode
;
21732 /* Create a frg for an instruction requiring relaxation. */
21734 output_relax_insn (void)
21740 /* The size of the instruction is unknown, so tie the debug info to the
21741 start of the instruction. */
21742 dwarf2_emit_insn (0);
21744 switch (inst
.relocs
[0].exp
.X_op
)
21747 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21748 offset
= inst
.relocs
[0].exp
.X_add_number
;
21752 offset
= inst
.relocs
[0].exp
.X_add_number
;
21755 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21759 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21760 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21761 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21764 /* Write a 32-bit thumb instruction to buf. */
21766 put_thumb32_insn (char * buf
, unsigned long insn
)
21768 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21769 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21773 output_inst (const char * str
)
21779 as_bad ("%s -- `%s'", inst
.error
, str
);
21784 output_relax_insn ();
21787 if (inst
.size
== 0)
21790 to
= frag_more (inst
.size
);
21791 /* PR 9814: Record the thumb mode into the current frag so that we know
21792 what type of NOP padding to use, if necessary. We override any previous
21793 setting so that if the mode has changed then the NOPS that we use will
21794 match the encoding of the last instruction in the frag. */
21795 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21797 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21799 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21800 put_thumb32_insn (to
, inst
.instruction
);
21802 else if (inst
.size
> INSN_SIZE
)
21804 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21805 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21806 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21809 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21812 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21814 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21815 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21816 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21817 inst
.relocs
[r
].type
);
21820 dwarf2_emit_insn (inst
.size
);
21824 output_it_inst (int cond
, int mask
, char * to
)
21826 unsigned long instruction
= 0xbf00;
21829 instruction
|= mask
;
21830 instruction
|= cond
<< 4;
21834 to
= frag_more (2);
21836 dwarf2_emit_insn (2);
21840 md_number_to_chars (to
, instruction
, 2);
21845 /* Tag values used in struct asm_opcode's tag field. */
21848 OT_unconditional
, /* Instruction cannot be conditionalized.
21849 The ARM condition field is still 0xE. */
21850 OT_unconditionalF
, /* Instruction cannot be conditionalized
21851 and carries 0xF in its ARM condition field. */
21852 OT_csuffix
, /* Instruction takes a conditional suffix. */
21853 OT_csuffixF
, /* Some forms of the instruction take a scalar
21854 conditional suffix, others place 0xF where the
21855 condition field would be, others take a vector
21856 conditional suffix. */
21857 OT_cinfix3
, /* Instruction takes a conditional infix,
21858 beginning at character index 3. (In
21859 unified mode, it becomes a suffix.) */
21860 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21861 tsts, cmps, cmns, and teqs. */
21862 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21863 character index 3, even in unified mode. Used for
21864 legacy instructions where suffix and infix forms
21865 may be ambiguous. */
21866 OT_csuf_or_in3
, /* Instruction takes either a conditional
21867 suffix or an infix at character index 3. */
21868 OT_odd_infix_unc
, /* This is the unconditional variant of an
21869 instruction that takes a conditional infix
21870 at an unusual position. In unified mode,
21871 this variant will accept a suffix. */
21872 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21873 are the conditional variants of instructions that
21874 take conditional infixes in unusual positions.
21875 The infix appears at character index
21876 (tag - OT_odd_infix_0). These are not accepted
21877 in unified mode. */
21880 /* Subroutine of md_assemble, responsible for looking up the primary
21881 opcode from the mnemonic the user wrote. STR points to the
21882 beginning of the mnemonic.
21884 This is not simply a hash table lookup, because of conditional
21885 variants. Most instructions have conditional variants, which are
21886 expressed with a _conditional affix_ to the mnemonic. If we were
21887 to encode each conditional variant as a literal string in the opcode
21888 table, it would have approximately 20,000 entries.
21890 Most mnemonics take this affix as a suffix, and in unified syntax,
21891 'most' is upgraded to 'all'. However, in the divided syntax, some
21892 instructions take the affix as an infix, notably the s-variants of
21893 the arithmetic instructions. Of those instructions, all but six
21894 have the infix appear after the third character of the mnemonic.
21896 Accordingly, the algorithm for looking up primary opcodes given
21899 1. Look up the identifier in the opcode table.
21900 If we find a match, go to step U.
21902 2. Look up the last two characters of the identifier in the
21903 conditions table. If we find a match, look up the first N-2
21904 characters of the identifier in the opcode table. If we
21905 find a match, go to step CE.
21907 3. Look up the fourth and fifth characters of the identifier in
21908 the conditions table. If we find a match, extract those
21909 characters from the identifier, and look up the remaining
21910 characters in the opcode table. If we find a match, go
21915 U. Examine the tag field of the opcode structure, in case this is
21916 one of the six instructions with its conditional infix in an
21917 unusual place. If it is, the tag tells us where to find the
21918 infix; look it up in the conditions table and set inst.cond
21919 accordingly. Otherwise, this is an unconditional instruction.
21920 Again set inst.cond accordingly. Return the opcode structure.
21922 CE. Examine the tag field to make sure this is an instruction that
21923 should receive a conditional suffix. If it is not, fail.
21924 Otherwise, set inst.cond from the suffix we already looked up,
21925 and return the opcode structure.
21927 CM. Examine the tag field to make sure this is an instruction that
21928 should receive a conditional infix after the third character.
21929 If it is not, fail. Otherwise, undo the edits to the current
21930 line of input and proceed as for case CE. */
21932 static const struct asm_opcode
*
21933 opcode_lookup (char **str
)
21937 const struct asm_opcode
*opcode
;
21938 const struct asm_cond
*cond
;
21941 /* Scan up to the end of the mnemonic, which must end in white space,
21942 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21943 for (base
= end
= *str
; *end
!= '\0'; end
++)
21944 if (*end
== ' ' || *end
== '.')
21950 /* Handle a possible width suffix and/or Neon type suffix. */
21955 /* The .w and .n suffixes are only valid if the unified syntax is in
21957 if (unified_syntax
&& end
[1] == 'w')
21959 else if (unified_syntax
&& end
[1] == 'n')
21964 inst
.vectype
.elems
= 0;
21966 *str
= end
+ offset
;
21968 if (end
[offset
] == '.')
21970 /* See if we have a Neon type suffix (possible in either unified or
21971 non-unified ARM syntax mode). */
21972 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21975 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21981 /* Look for unaffixed or special-case affixed mnemonic. */
21982 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21987 if (opcode
->tag
< OT_odd_infix_0
)
21989 inst
.cond
= COND_ALWAYS
;
21993 if (warn_on_deprecated
&& unified_syntax
)
21994 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21995 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21996 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21999 inst
.cond
= cond
->value
;
22002 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22004 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22006 if (end
- base
< 2)
22009 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
22010 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22012 /* If this opcode can not be vector predicated then don't accept it with a
22013 vector predication code. */
22014 if (opcode
&& !opcode
->mayBeVecPred
)
22017 if (!opcode
|| !cond
)
22019 /* Cannot have a conditional suffix on a mnemonic of less than two
22021 if (end
- base
< 3)
22024 /* Look for suffixed mnemonic. */
22026 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22027 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22031 if (opcode
&& cond
)
22034 switch (opcode
->tag
)
22036 case OT_cinfix3_legacy
:
22037 /* Ignore conditional suffixes matched on infix only mnemonics. */
22041 case OT_cinfix3_deprecated
:
22042 case OT_odd_infix_unc
:
22043 if (!unified_syntax
)
22045 /* Fall through. */
22049 case OT_csuf_or_in3
:
22050 inst
.cond
= cond
->value
;
22053 case OT_unconditional
:
22054 case OT_unconditionalF
:
22056 inst
.cond
= cond
->value
;
22059 /* Delayed diagnostic. */
22060 inst
.error
= BAD_COND
;
22061 inst
.cond
= COND_ALWAYS
;
22070 /* Cannot have a usual-position infix on a mnemonic of less than
22071 six characters (five would be a suffix). */
22072 if (end
- base
< 6)
22075 /* Look for infixed mnemonic in the usual position. */
22077 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22081 memcpy (save
, affix
, 2);
22082 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22083 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22085 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22086 memcpy (affix
, save
, 2);
22089 && (opcode
->tag
== OT_cinfix3
22090 || opcode
->tag
== OT_cinfix3_deprecated
22091 || opcode
->tag
== OT_csuf_or_in3
22092 || opcode
->tag
== OT_cinfix3_legacy
))
22095 if (warn_on_deprecated
&& unified_syntax
22096 && (opcode
->tag
== OT_cinfix3
22097 || opcode
->tag
== OT_cinfix3_deprecated
))
22098 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22100 inst
.cond
= cond
->value
;
22107 /* This function generates an initial IT instruction, leaving its block
22108 virtually open for the new instructions. Eventually,
22109 the mask will be updated by now_pred_add_mask () each time
22110 a new instruction needs to be included in the IT block.
22111 Finally, the block is closed with close_automatic_it_block ().
22112 The block closure can be requested either from md_assemble (),
22113 a tencode (), or due to a label hook. */
22116 new_automatic_it_block (int cond
)
22118 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22119 now_pred
.mask
= 0x18;
22120 now_pred
.cc
= cond
;
22121 now_pred
.block_length
= 1;
22122 mapping_state (MAP_THUMB
);
22123 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22124 now_pred
.warn_deprecated
= FALSE
;
22125 now_pred
.insn_cond
= TRUE
;
22128 /* Close an automatic IT block.
22129 See comments in new_automatic_it_block (). */
22132 close_automatic_it_block (void)
22134 now_pred
.mask
= 0x10;
22135 now_pred
.block_length
= 0;
22138 /* Update the mask of the current automatically-generated IT
22139 instruction. See comments in new_automatic_it_block (). */
22142 now_pred_add_mask (int cond
)
22144 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22145 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22146 | ((bitvalue) << (nbit)))
22147 const int resulting_bit
= (cond
& 1);
22149 now_pred
.mask
&= 0xf;
22150 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22152 (5 - now_pred
.block_length
));
22153 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22155 ((5 - now_pred
.block_length
) - 1));
22156 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22159 #undef SET_BIT_VALUE
22162 /* The IT blocks handling machinery is accessed through the these functions:
22163 it_fsm_pre_encode () from md_assemble ()
22164 set_pred_insn_type () optional, from the tencode functions
22165 set_pred_insn_type_last () ditto
22166 in_pred_block () ditto
22167 it_fsm_post_encode () from md_assemble ()
22168 force_automatic_it_block_close () from label handling functions
22171 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22172 initializing the IT insn type with a generic initial value depending
22173 on the inst.condition.
22174 2) During the tencode function, two things may happen:
22175 a) The tencode function overrides the IT insn type by
22176 calling either set_pred_insn_type (type) or
22177 set_pred_insn_type_last ().
22178 b) The tencode function queries the IT block state by
22179 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22181 Both set_pred_insn_type and in_pred_block run the internal FSM state
22182 handling function (handle_pred_state), because: a) setting the IT insn
22183 type may incur in an invalid state (exiting the function),
22184 and b) querying the state requires the FSM to be updated.
22185 Specifically we want to avoid creating an IT block for conditional
22186 branches, so it_fsm_pre_encode is actually a guess and we can't
22187 determine whether an IT block is required until the tencode () routine
22188 has decided what type of instruction this actually it.
22189 Because of this, if set_pred_insn_type and in_pred_block have to be
22190 used, set_pred_insn_type has to be called first.
22192 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22193 that determines the insn IT type depending on the inst.cond code.
22194 When a tencode () routine encodes an instruction that can be
22195 either outside an IT block, or, in the case of being inside, has to be
22196 the last one, set_pred_insn_type_last () will determine the proper
22197 IT instruction type based on the inst.cond code. Otherwise,
22198 set_pred_insn_type can be called for overriding that logic or
22199 for covering other cases.
22201 Calling handle_pred_state () may not transition the IT block state to
22202 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22203 still queried. Instead, if the FSM determines that the state should
22204 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22205 after the tencode () function: that's what it_fsm_post_encode () does.
22207 Since in_pred_block () calls the state handling function to get an
22208 updated state, an error may occur (due to invalid insns combination).
22209 In that case, inst.error is set.
22210 Therefore, inst.error has to be checked after the execution of
22211 the tencode () routine.
22213 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22214 any pending state change (if any) that didn't take place in
22215 handle_pred_state () as explained above. */
22218 it_fsm_pre_encode (void)
22220 if (inst
.cond
!= COND_ALWAYS
)
22221 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22223 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22225 now_pred
.state_handled
= 0;
22228 /* IT state FSM handling function. */
22229 /* MVE instructions and non-MVE instructions are handled differently because of
22230 the introduction of VPT blocks.
22231 Specifications say that any non-MVE instruction inside a VPT block is
22232 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22233 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22234 few exceptions we have MVE_UNPREDICABLE_INSN.
22235 The error messages provided depending on the different combinations possible
22236 are described in the cases below:
22237 For 'most' MVE instructions:
22238 1) In an IT block, with an IT code: syntax error
22239 2) In an IT block, with a VPT code: error: must be in a VPT block
22240 3) In an IT block, with no code: warning: UNPREDICTABLE
22241 4) In a VPT block, with an IT code: syntax error
22242 5) In a VPT block, with a VPT code: OK!
22243 6) In a VPT block, with no code: error: missing code
22244 7) Outside a pred block, with an IT code: error: syntax error
22245 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22246 9) Outside a pred block, with no code: OK!
22247 For non-MVE instructions:
22248 10) In an IT block, with an IT code: OK!
22249 11) In an IT block, with a VPT code: syntax error
22250 12) In an IT block, with no code: error: missing code
22251 13) In a VPT block, with an IT code: error: should be in an IT block
22252 14) In a VPT block, with a VPT code: syntax error
22253 15) In a VPT block, with no code: UNPREDICTABLE
22254 16) Outside a pred block, with an IT code: error: should be in an IT block
22255 17) Outside a pred block, with a VPT code: syntax error
22256 18) Outside a pred block, with no code: OK!
22261 handle_pred_state (void)
22263 now_pred
.state_handled
= 1;
22264 now_pred
.insn_cond
= FALSE
;
22266 switch (now_pred
.state
)
22268 case OUTSIDE_PRED_BLOCK
:
22269 switch (inst
.pred_insn_type
)
22271 case MVE_UNPREDICABLE_INSN
:
22272 case MVE_OUTSIDE_PRED_INSN
:
22273 if (inst
.cond
< COND_ALWAYS
)
22275 /* Case 7: Outside a pred block, with an IT code: error: syntax
22277 inst
.error
= BAD_SYNTAX
;
22280 /* Case 9: Outside a pred block, with no code: OK! */
22282 case OUTSIDE_PRED_INSN
:
22283 if (inst
.cond
> COND_ALWAYS
)
22285 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22287 inst
.error
= BAD_SYNTAX
;
22290 /* Case 18: Outside a pred block, with no code: OK! */
22293 case INSIDE_VPT_INSN
:
22294 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22296 inst
.error
= BAD_OUT_VPT
;
22299 case INSIDE_IT_INSN
:
22300 case INSIDE_IT_LAST_INSN
:
22301 if (inst
.cond
< COND_ALWAYS
)
22303 /* Case 16: Outside a pred block, with an IT code: error: should
22304 be in an IT block. */
22305 if (thumb_mode
== 0)
22308 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22309 as_tsktsk (_("Warning: conditional outside an IT block"\
22314 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22315 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22317 /* Automatically generate the IT instruction. */
22318 new_automatic_it_block (inst
.cond
);
22319 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22320 close_automatic_it_block ();
22324 inst
.error
= BAD_OUT_IT
;
22330 else if (inst
.cond
> COND_ALWAYS
)
22332 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22334 inst
.error
= BAD_SYNTAX
;
22339 case IF_INSIDE_IT_LAST_INSN
:
22340 case NEUTRAL_IT_INSN
:
22344 if (inst
.cond
!= COND_ALWAYS
)
22345 first_error (BAD_SYNTAX
);
22346 now_pred
.state
= MANUAL_PRED_BLOCK
;
22347 now_pred
.block_length
= 0;
22348 now_pred
.type
= VECTOR_PRED
;
22352 now_pred
.state
= MANUAL_PRED_BLOCK
;
22353 now_pred
.block_length
= 0;
22354 now_pred
.type
= SCALAR_PRED
;
22359 case AUTOMATIC_PRED_BLOCK
:
22360 /* Three things may happen now:
22361 a) We should increment current it block size;
22362 b) We should close current it block (closing insn or 4 insns);
22363 c) We should close current it block and start a new one (due
22364 to incompatible conditions or
22365 4 insns-length block reached). */
22367 switch (inst
.pred_insn_type
)
22369 case INSIDE_VPT_INSN
:
22371 case MVE_UNPREDICABLE_INSN
:
22372 case MVE_OUTSIDE_PRED_INSN
:
22374 case OUTSIDE_PRED_INSN
:
22375 /* The closure of the block shall happen immediately,
22376 so any in_pred_block () call reports the block as closed. */
22377 force_automatic_it_block_close ();
22380 case INSIDE_IT_INSN
:
22381 case INSIDE_IT_LAST_INSN
:
22382 case IF_INSIDE_IT_LAST_INSN
:
22383 now_pred
.block_length
++;
22385 if (now_pred
.block_length
> 4
22386 || !now_pred_compatible (inst
.cond
))
22388 force_automatic_it_block_close ();
22389 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
22390 new_automatic_it_block (inst
.cond
);
22394 now_pred
.insn_cond
= TRUE
;
22395 now_pred_add_mask (inst
.cond
);
22398 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
22399 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
22400 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
22401 close_automatic_it_block ();
22404 case NEUTRAL_IT_INSN
:
22405 now_pred
.block_length
++;
22406 now_pred
.insn_cond
= TRUE
;
22408 if (now_pred
.block_length
> 4)
22409 force_automatic_it_block_close ();
22411 now_pred_add_mask (now_pred
.cc
& 1);
22415 close_automatic_it_block ();
22416 now_pred
.state
= MANUAL_PRED_BLOCK
;
22421 case MANUAL_PRED_BLOCK
:
22424 if (now_pred
.type
== SCALAR_PRED
)
22426 /* Check conditional suffixes. */
22427 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
22428 now_pred
.mask
<<= 1;
22429 now_pred
.mask
&= 0x1f;
22430 is_last
= (now_pred
.mask
== 0x10);
22434 now_pred
.cc
^= (now_pred
.mask
>> 4);
22435 cond
= now_pred
.cc
+ 0xf;
22436 now_pred
.mask
<<= 1;
22437 now_pred
.mask
&= 0x1f;
22438 is_last
= now_pred
.mask
== 0x10;
22440 now_pred
.insn_cond
= TRUE
;
22442 switch (inst
.pred_insn_type
)
22444 case OUTSIDE_PRED_INSN
:
22445 if (now_pred
.type
== SCALAR_PRED
)
22447 if (inst
.cond
== COND_ALWAYS
)
22449 /* Case 12: In an IT block, with no code: error: missing
22451 inst
.error
= BAD_NOT_IT
;
22454 else if (inst
.cond
> COND_ALWAYS
)
22456 /* Case 11: In an IT block, with a VPT code: syntax error.
22458 inst
.error
= BAD_SYNTAX
;
22461 else if (thumb_mode
)
22463 /* This is for some special cases where a non-MVE
22464 instruction is not allowed in an IT block, such as cbz,
22465 but are put into one with a condition code.
22466 You could argue this should be a syntax error, but we
22467 gave the 'not allowed in IT block' diagnostic in the
22468 past so we will keep doing so. */
22469 inst
.error
= BAD_NOT_IT
;
22476 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22477 as_tsktsk (MVE_NOT_VPT
);
22480 case MVE_OUTSIDE_PRED_INSN
:
22481 if (now_pred
.type
== SCALAR_PRED
)
22483 if (inst
.cond
== COND_ALWAYS
)
22485 /* Case 3: In an IT block, with no code: warning:
22487 as_tsktsk (MVE_NOT_IT
);
22490 else if (inst
.cond
< COND_ALWAYS
)
22492 /* Case 1: In an IT block, with an IT code: syntax error.
22494 inst
.error
= BAD_SYNTAX
;
22502 if (inst
.cond
< COND_ALWAYS
)
22504 /* Case 4: In a VPT block, with an IT code: syntax error.
22506 inst
.error
= BAD_SYNTAX
;
22509 else if (inst
.cond
== COND_ALWAYS
)
22511 /* Case 6: In a VPT block, with no code: error: missing
22513 inst
.error
= BAD_NOT_VPT
;
22521 case MVE_UNPREDICABLE_INSN
:
22522 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22524 case INSIDE_IT_INSN
:
22525 if (inst
.cond
> COND_ALWAYS
)
22527 /* Case 11: In an IT block, with a VPT code: syntax error. */
22528 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22529 inst
.error
= BAD_SYNTAX
;
22532 else if (now_pred
.type
== SCALAR_PRED
)
22534 /* Case 10: In an IT block, with an IT code: OK! */
22535 if (cond
!= inst
.cond
)
22537 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22544 /* Case 13: In a VPT block, with an IT code: error: should be
22546 inst
.error
= BAD_OUT_IT
;
22551 case INSIDE_VPT_INSN
:
22552 if (now_pred
.type
== SCALAR_PRED
)
22554 /* Case 2: In an IT block, with a VPT code: error: must be in a
22556 inst
.error
= BAD_OUT_VPT
;
22559 /* Case 5: In a VPT block, with a VPT code: OK! */
22560 else if (cond
!= inst
.cond
)
22562 inst
.error
= BAD_VPT_COND
;
22566 case INSIDE_IT_LAST_INSN
:
22567 case IF_INSIDE_IT_LAST_INSN
:
22568 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22570 /* Case 4: In a VPT block, with an IT code: syntax error. */
22571 /* Case 11: In an IT block, with a VPT code: syntax error. */
22572 inst
.error
= BAD_SYNTAX
;
22575 else if (cond
!= inst
.cond
)
22577 inst
.error
= BAD_IT_COND
;
22582 inst
.error
= BAD_BRANCH
;
22587 case NEUTRAL_IT_INSN
:
22588 /* The BKPT instruction is unconditional even in a IT or VPT
22593 if (now_pred
.type
== SCALAR_PRED
)
22595 inst
.error
= BAD_IT_IT
;
22598 /* fall through. */
22600 if (inst
.cond
== COND_ALWAYS
)
22602 /* Executing a VPT/VPST instruction inside an IT block or a
22603 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22605 if (now_pred
.type
== SCALAR_PRED
)
22606 as_tsktsk (MVE_NOT_IT
);
22608 as_tsktsk (MVE_NOT_VPT
);
22613 /* VPT/VPST do not accept condition codes. */
22614 inst
.error
= BAD_SYNTAX
;
22625 struct depr_insn_mask
22627 unsigned long pattern
;
22628 unsigned long mask
;
22629 const char* description
;
22632 /* List of 16-bit instruction patterns deprecated in an IT block in
22634 static const struct depr_insn_mask depr_it_insns
[] = {
22635 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22636 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22637 { 0xa000, 0xb800, N_("ADR") },
22638 { 0x4800, 0xf800, N_("Literal loads") },
22639 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22640 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22641 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22642 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22643 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22648 it_fsm_post_encode (void)
22652 if (!now_pred
.state_handled
)
22653 handle_pred_state ();
22655 if (now_pred
.insn_cond
22656 && !now_pred
.warn_deprecated
22657 && warn_on_deprecated
22658 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22659 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22661 if (inst
.instruction
>= 0x10000)
22663 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22664 "performance deprecated in ARMv8-A and ARMv8-R"));
22665 now_pred
.warn_deprecated
= TRUE
;
22669 const struct depr_insn_mask
*p
= depr_it_insns
;
22671 while (p
->mask
!= 0)
22673 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22675 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22676 "instructions of the following class are "
22677 "performance deprecated in ARMv8-A and "
22678 "ARMv8-R: %s"), p
->description
);
22679 now_pred
.warn_deprecated
= TRUE
;
22687 if (now_pred
.block_length
> 1)
22689 as_tsktsk (_("IT blocks containing more than one conditional "
22690 "instruction are performance deprecated in ARMv8-A and "
22692 now_pred
.warn_deprecated
= TRUE
;
22696 is_last
= (now_pred
.mask
== 0x10);
22699 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22705 force_automatic_it_block_close (void)
22707 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22709 close_automatic_it_block ();
22710 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22716 in_pred_block (void)
22718 if (!now_pred
.state_handled
)
22719 handle_pred_state ();
22721 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22724 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22725 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22726 here, hence the "known" in the function name. */
22729 known_t32_only_insn (const struct asm_opcode
*opcode
)
22731 /* Original Thumb-1 wide instruction. */
22732 if (opcode
->tencode
== do_t_blx
22733 || opcode
->tencode
== do_t_branch23
22734 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22735 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22738 /* Wide-only instruction added to ARMv8-M Baseline. */
22739 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22740 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22741 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22742 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22748 /* Whether wide instruction variant can be used if available for a valid OPCODE
22752 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22754 if (known_t32_only_insn (opcode
))
22757 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22758 of variant T3 of B.W is checked in do_t_branch. */
22759 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22760 && opcode
->tencode
== do_t_branch
)
22763 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22764 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22765 && opcode
->tencode
== do_t_mov_cmp
22766 /* Make sure CMP instruction is not affected. */
22767 && opcode
->aencode
== do_mov
)
22770 /* Wide instruction variants of all instructions with narrow *and* wide
22771 variants become available with ARMv6t2. Other opcodes are either
22772 narrow-only or wide-only and are thus available if OPCODE is valid. */
22773 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22776 /* OPCODE with narrow only instruction variant or wide variant not
22782 md_assemble (char *str
)
22785 const struct asm_opcode
* opcode
;
22787 /* Align the previous label if needed. */
22788 if (last_label_seen
!= NULL
)
22790 symbol_set_frag (last_label_seen
, frag_now
);
22791 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22792 S_SET_SEGMENT (last_label_seen
, now_seg
);
22795 memset (&inst
, '\0', sizeof (inst
));
22797 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22798 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22800 opcode
= opcode_lookup (&p
);
22803 /* It wasn't an instruction, but it might be a register alias of
22804 the form alias .req reg, or a Neon .dn/.qn directive. */
22805 if (! create_register_alias (str
, p
)
22806 && ! create_neon_reg_alias (str
, p
))
22807 as_bad (_("bad instruction `%s'"), str
);
22812 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22813 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22815 /* The value which unconditional instructions should have in place of the
22816 condition field. */
22817 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22821 arm_feature_set variant
;
22823 variant
= cpu_variant
;
22824 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22825 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22826 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22827 /* Check that this instruction is supported for this CPU. */
22828 if (!opcode
->tvariant
22829 || (thumb_mode
== 1
22830 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22832 if (opcode
->tencode
== do_t_swi
)
22833 as_bad (_("SVC is not permitted on this architecture"));
22835 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22838 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22839 && opcode
->tencode
!= do_t_branch
)
22841 as_bad (_("Thumb does not support conditional execution"));
22845 /* Two things are addressed here:
22846 1) Implicit require narrow instructions on Thumb-1.
22847 This avoids relaxation accidentally introducing Thumb-2
22849 2) Reject wide instructions in non Thumb-2 cores.
22851 Only instructions with narrow and wide variants need to be handled
22852 but selecting all non wide-only instructions is easier. */
22853 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22854 && !t32_insn_ok (variant
, opcode
))
22856 if (inst
.size_req
== 0)
22858 else if (inst
.size_req
== 4)
22860 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22861 as_bad (_("selected processor does not support 32bit wide "
22862 "variant of instruction `%s'"), str
);
22864 as_bad (_("selected processor does not support `%s' in "
22865 "Thumb-2 mode"), str
);
22870 inst
.instruction
= opcode
->tvalue
;
22872 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22874 /* Prepare the pred_insn_type for those encodings that don't set
22876 it_fsm_pre_encode ();
22878 opcode
->tencode ();
22880 it_fsm_post_encode ();
22883 if (!(inst
.error
|| inst
.relax
))
22885 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22886 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22887 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22889 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22894 /* Something has gone badly wrong if we try to relax a fixed size
22896 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22898 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22899 *opcode
->tvariant
);
22900 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22901 set those bits when Thumb-2 32-bit instructions are seen. The impact
22902 of relaxable instructions will be considered later after we finish all
22904 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22905 variant
= arm_arch_none
;
22907 variant
= cpu_variant
;
22908 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22909 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22912 check_neon_suffixes
;
22916 mapping_state (MAP_THUMB
);
22919 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22923 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22924 is_bx
= (opcode
->aencode
== do_bx
);
22926 /* Check that this instruction is supported for this CPU. */
22927 if (!(is_bx
&& fix_v4bx
)
22928 && !(opcode
->avariant
&&
22929 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22931 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22936 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22940 inst
.instruction
= opcode
->avalue
;
22941 if (opcode
->tag
== OT_unconditionalF
)
22942 inst
.instruction
|= 0xFU
<< 28;
22944 inst
.instruction
|= inst
.cond
<< 28;
22945 inst
.size
= INSN_SIZE
;
22946 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22948 it_fsm_pre_encode ();
22949 opcode
->aencode ();
22950 it_fsm_post_encode ();
22952 /* Arm mode bx is marked as both v4T and v5 because it's still required
22953 on a hypothetical non-thumb v5 core. */
22955 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22957 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22958 *opcode
->avariant
);
22960 check_neon_suffixes
;
22964 mapping_state (MAP_ARM
);
22969 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22977 check_pred_blocks_finished (void)
22982 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22983 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22984 == MANUAL_PRED_BLOCK
)
22986 if (now_pred
.type
== SCALAR_PRED
)
22987 as_warn (_("section '%s' finished with an open IT block."),
22990 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22994 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22996 if (now_pred
.type
== SCALAR_PRED
)
22997 as_warn (_("file finished with an open IT block."));
22999 as_warn (_("file finished with an open VPT/VPST block."));
23004 /* Various frobbings of labels and their addresses. */
23007 arm_start_line_hook (void)
23009 last_label_seen
= NULL
;
23013 arm_frob_label (symbolS
* sym
)
23015 last_label_seen
= sym
;
23017 ARM_SET_THUMB (sym
, thumb_mode
);
23019 #if defined OBJ_COFF || defined OBJ_ELF
23020 ARM_SET_INTERWORK (sym
, support_interwork
);
23023 force_automatic_it_block_close ();
23025 /* Note - do not allow local symbols (.Lxxx) to be labelled
23026 as Thumb functions. This is because these labels, whilst
23027 they exist inside Thumb code, are not the entry points for
23028 possible ARM->Thumb calls. Also, these labels can be used
23029 as part of a computed goto or switch statement. eg gcc
23030 can generate code that looks like this:
23032 ldr r2, [pc, .Laaa]
23042 The first instruction loads the address of the jump table.
23043 The second instruction converts a table index into a byte offset.
23044 The third instruction gets the jump address out of the table.
23045 The fourth instruction performs the jump.
23047 If the address stored at .Laaa is that of a symbol which has the
23048 Thumb_Func bit set, then the linker will arrange for this address
23049 to have the bottom bit set, which in turn would mean that the
23050 address computation performed by the third instruction would end
23051 up with the bottom bit set. Since the ARM is capable of unaligned
23052 word loads, the instruction would then load the incorrect address
23053 out of the jump table, and chaos would ensue. */
23054 if (label_is_thumb_function_name
23055 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23056 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23058 /* When the address of a Thumb function is taken the bottom
23059 bit of that address should be set. This will allow
23060 interworking between Arm and Thumb functions to work
23063 THUMB_SET_FUNC (sym
, 1);
23065 label_is_thumb_function_name
= FALSE
;
23068 dwarf2_emit_label (sym
);
23072 arm_data_in_code (void)
23074 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
23076 *input_line_pointer
= '/';
23077 input_line_pointer
+= 5;
23078 *input_line_pointer
= 0;
23086 arm_canonicalize_symbol_name (char * name
)
23090 if (thumb_mode
&& (len
= strlen (name
)) > 5
23091 && streq (name
+ len
- 5, "/data"))
23092 *(name
+ len
- 5) = 0;
23097 /* Table of all register names defined by default. The user can
23098 define additional names with .req. Note that all register names
23099 should appear in both upper and lowercase variants. Some registers
23100 also have mixed-case names. */
23102 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23103 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23104 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23105 #define REGSET(p,t) \
23106 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23107 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23108 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23109 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23110 #define REGSETH(p,t) \
23111 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23112 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23113 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23114 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23115 #define REGSET2(p,t) \
23116 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23117 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23118 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23119 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23120 #define SPLRBANK(base,bank,t) \
23121 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23122 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23123 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23124 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23125 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23126 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23128 static const struct reg_entry reg_names
[] =
23130 /* ARM integer registers. */
23131 REGSET(r
, RN
), REGSET(R
, RN
),
23133 /* ATPCS synonyms. */
23134 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23135 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23136 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23138 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23139 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23140 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23142 /* Well-known aliases. */
23143 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23144 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23146 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23147 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23149 /* Defining the new Zero register from ARMv8.1-M. */
23153 /* Coprocessor numbers. */
23154 REGSET(p
, CP
), REGSET(P
, CP
),
23156 /* Coprocessor register numbers. The "cr" variants are for backward
23158 REGSET(c
, CN
), REGSET(C
, CN
),
23159 REGSET(cr
, CN
), REGSET(CR
, CN
),
23161 /* ARM banked registers. */
23162 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23163 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23164 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23165 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23166 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23167 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23168 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23170 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23171 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23172 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23173 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23174 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23175 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23176 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23177 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23179 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23180 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23181 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23182 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23183 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23184 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23185 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23186 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23187 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23189 /* FPA registers. */
23190 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23191 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23193 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23194 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23196 /* VFP SP registers. */
23197 REGSET(s
,VFS
), REGSET(S
,VFS
),
23198 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23200 /* VFP DP Registers. */
23201 REGSET(d
,VFD
), REGSET(D
,VFD
),
23202 /* Extra Neon DP registers. */
23203 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23205 /* Neon QP registers. */
23206 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23208 /* VFP control registers. */
23209 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23210 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23211 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23212 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23213 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23214 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23215 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23216 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23217 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23218 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23219 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23221 /* Maverick DSP coprocessor registers. */
23222 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23223 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23225 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23226 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23227 REGDEF(dspsc
,0,DSPSC
),
23229 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23230 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23231 REGDEF(DSPSC
,0,DSPSC
),
23233 /* iWMMXt data registers - p0, c0-15. */
23234 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23236 /* iWMMXt control registers - p1, c0-3. */
23237 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23238 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23239 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23240 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23242 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23243 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23244 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23245 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23246 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23248 /* XScale accumulator registers. */
23249 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23255 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23256 within psr_required_here. */
23257 static const struct asm_psr psrs
[] =
23259 /* Backward compatibility notation. Note that "all" is no longer
23260 truly all possible PSR bits. */
23261 {"all", PSR_c
| PSR_f
},
23265 /* Individual flags. */
23271 /* Combinations of flags. */
23272 {"fs", PSR_f
| PSR_s
},
23273 {"fx", PSR_f
| PSR_x
},
23274 {"fc", PSR_f
| PSR_c
},
23275 {"sf", PSR_s
| PSR_f
},
23276 {"sx", PSR_s
| PSR_x
},
23277 {"sc", PSR_s
| PSR_c
},
23278 {"xf", PSR_x
| PSR_f
},
23279 {"xs", PSR_x
| PSR_s
},
23280 {"xc", PSR_x
| PSR_c
},
23281 {"cf", PSR_c
| PSR_f
},
23282 {"cs", PSR_c
| PSR_s
},
23283 {"cx", PSR_c
| PSR_x
},
23284 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23285 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23286 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23287 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23288 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23289 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23290 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23291 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23292 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23293 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23294 {"scf", PSR_s
| PSR_c
| PSR_f
},
23295 {"scx", PSR_s
| PSR_c
| PSR_x
},
23296 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23297 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23298 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23299 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23300 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23301 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23302 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23303 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23304 {"csf", PSR_c
| PSR_s
| PSR_f
},
23305 {"csx", PSR_c
| PSR_s
| PSR_x
},
23306 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23307 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23308 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23309 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23310 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23311 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23312 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23313 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23314 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23315 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23316 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23317 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23318 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23319 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23320 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23321 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23322 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23323 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23324 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23325 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23326 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23327 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23328 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23329 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23330 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23331 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23334 /* Table of V7M psr names. */
23335 static const struct asm_psr v7m_psrs
[] =
23337 {"apsr", 0x0 }, {"APSR", 0x0 },
23338 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23339 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23340 {"psr", 0x3 }, {"PSR", 0x3 },
23341 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23342 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23343 {"epsr", 0x6 }, {"EPSR", 0x6 },
23344 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23345 {"msp", 0x8 }, {"MSP", 0x8 },
23346 {"psp", 0x9 }, {"PSP", 0x9 },
23347 {"msplim", 0xa }, {"MSPLIM", 0xa },
23348 {"psplim", 0xb }, {"PSPLIM", 0xb },
23349 {"primask", 0x10}, {"PRIMASK", 0x10},
23350 {"basepri", 0x11}, {"BASEPRI", 0x11},
23351 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23352 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23353 {"control", 0x14}, {"CONTROL", 0x14},
23354 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23355 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23356 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23357 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23358 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23359 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23360 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23361 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23362 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
23365 /* Table of all shift-in-operand names. */
23366 static const struct asm_shift_name shift_names
[] =
23368 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
23369 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
23370 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
23371 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
23372 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
23373 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
23374 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
23377 /* Table of all explicit relocation names. */
23379 static struct reloc_entry reloc_names
[] =
23381 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
23382 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
23383 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
23384 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
23385 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
23386 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
23387 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
23388 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
23389 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
23390 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
23391 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
23392 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
23393 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
23394 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
23395 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
23396 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
23397 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
23398 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
23399 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
23400 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
23401 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23402 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23403 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
23404 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
23405 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
23406 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
23407 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
23411 /* Table of all conditional affixes. */
23412 static const struct asm_cond conds
[] =
23416 {"cs", 0x2}, {"hs", 0x2},
23417 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23430 static const struct asm_cond vconds
[] =
23436 #define UL_BARRIER(L,U,CODE,FEAT) \
23437 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23438 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
23440 static struct asm_barrier_opt barrier_opt_names
[] =
23442 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
23443 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
23444 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
23445 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
23446 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
23447 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
23448 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
23449 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
23450 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
23451 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
23452 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
23453 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
23454 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
23455 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
23456 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
23457 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
23462 /* Table of ARM-format instructions. */
23464 /* Macros for gluing together operand strings. N.B. In all cases
23465 other than OPS0, the trailing OP_stop comes from default
23466 zero-initialization of the unspecified elements of the array. */
23467 #define OPS0() { OP_stop, }
23468 #define OPS1(a) { OP_##a, }
23469 #define OPS2(a,b) { OP_##a,OP_##b, }
23470 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23471 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23472 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23473 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23475 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23476 This is useful when mixing operands for ARM and THUMB, i.e. using the
23477 MIX_ARM_THUMB_OPERANDS macro.
23478 In order to use these macros, prefix the number of operands with _
23480 #define OPS_1(a) { a, }
23481 #define OPS_2(a,b) { a,b, }
23482 #define OPS_3(a,b,c) { a,b,c, }
23483 #define OPS_4(a,b,c,d) { a,b,c,d, }
23484 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23485 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23487 /* These macros abstract out the exact format of the mnemonic table and
23488 save some repeated characters. */
23490 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23491 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23492 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23493 THUMB_VARIANT, do_##ae, do_##te, 0 }
23495 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23496 a T_MNEM_xyz enumerator. */
23497 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23498 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23499 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23500 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23502 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23503 infix after the third character. */
23504 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23505 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23506 THUMB_VARIANT, do_##ae, do_##te, 0 }
23507 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23508 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23509 THUMB_VARIANT, do_##ae, do_##te, 0 }
23510 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23511 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23512 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23513 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23514 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23515 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23516 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23517 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23519 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23520 field is still 0xE. Many of the Thumb variants can be executed
23521 conditionally, so this is checked separately. */
23522 #define TUE(mnem, op, top, nops, ops, ae, te) \
23523 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23524 THUMB_VARIANT, do_##ae, do_##te, 0 }
23526 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23527 Used by mnemonics that have very minimal differences in the encoding for
23528 ARM and Thumb variants and can be handled in a common function. */
23529 #define TUEc(mnem, op, top, nops, ops, en) \
23530 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23531 THUMB_VARIANT, do_##en, do_##en, 0 }
23533 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23534 condition code field. */
23535 #define TUF(mnem, op, top, nops, ops, ae, te) \
23536 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23537 THUMB_VARIANT, do_##ae, do_##te, 0 }
23539 /* ARM-only variants of all the above. */
23540 #define CE(mnem, op, nops, ops, ae) \
23541 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23543 #define C3(mnem, op, nops, ops, ae) \
23544 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23546 /* Thumb-only variants of TCE and TUE. */
23547 #define ToC(mnem, top, nops, ops, te) \
23548 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23551 #define ToU(mnem, top, nops, ops, te) \
23552 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23555 /* T_MNEM_xyz enumerator variants of ToC. */
23556 #define toC(mnem, top, nops, ops, te) \
23557 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23560 /* T_MNEM_xyz enumerator variants of ToU. */
23561 #define toU(mnem, top, nops, ops, te) \
23562 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23565 /* Legacy mnemonics that always have conditional infix after the third
23567 #define CL(mnem, op, nops, ops, ae) \
23568 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23569 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23571 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23572 #define cCE(mnem, op, nops, ops, ae) \
23573 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23575 /* mov instructions that are shared between coprocessor and MVE. */
23576 #define mcCE(mnem, op, nops, ops, ae) \
23577 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23579 /* Legacy coprocessor instructions where conditional infix and conditional
23580 suffix are ambiguous. For consistency this includes all FPA instructions,
23581 not just the potentially ambiguous ones. */
23582 #define cCL(mnem, op, nops, ops, ae) \
23583 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23584 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23586 /* Coprocessor, takes either a suffix or a position-3 infix
23587 (for an FPA corner case). */
23588 #define C3E(mnem, op, nops, ops, ae) \
23589 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23590 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23592 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23593 { m1 #m2 m3, OPS##nops ops, \
23594 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23595 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23597 #define CM(m1, m2, op, nops, ops, ae) \
23598 xCM_ (m1, , m2, op, nops, ops, ae), \
23599 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23600 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23601 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23602 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23603 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23604 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23605 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23606 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23607 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23608 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23609 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23610 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23611 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23612 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23613 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23614 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23615 xCM_ (m1, le, m2, op, nops, ops, ae), \
23616 xCM_ (m1, al, m2, op, nops, ops, ae)
23618 #define UE(mnem, op, nops, ops, ae) \
23619 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23621 #define UF(mnem, op, nops, ops, ae) \
23622 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23624 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23625 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23626 use the same encoding function for each. */
23627 #define NUF(mnem, op, nops, ops, enc) \
23628 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23629 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23631 /* Neon data processing, version which indirects through neon_enc_tab for
23632 the various overloaded versions of opcodes. */
23633 #define nUF(mnem, op, nops, ops, enc) \
23634 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23635 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23637 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23639 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23640 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23641 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23643 #define NCE(mnem, op, nops, ops, enc) \
23644 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23646 #define NCEF(mnem, op, nops, ops, enc) \
23647 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23649 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23650 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23651 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23652 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23654 #define nCE(mnem, op, nops, ops, enc) \
23655 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23657 #define nCEF(mnem, op, nops, ops, enc) \
23658 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23661 #define mCEF(mnem, op, nops, ops, enc) \
23662 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23663 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23666 /* nCEF but for MVE predicated instructions. */
23667 #define mnCEF(mnem, op, nops, ops, enc) \
23668 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23670 /* nCE but for MVE predicated instructions. */
23671 #define mnCE(mnem, op, nops, ops, enc) \
23672 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23674 /* NUF but for potentially MVE predicated instructions. */
23675 #define MNUF(mnem, op, nops, ops, enc) \
23676 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23677 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23679 /* nUF but for potentially MVE predicated instructions. */
23680 #define mnUF(mnem, op, nops, ops, enc) \
23681 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23682 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23684 /* ToC but for potentially MVE predicated instructions. */
23685 #define mToC(mnem, top, nops, ops, te) \
23686 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23689 /* NCE but for MVE predicated instructions. */
23690 #define MNCE(mnem, op, nops, ops, enc) \
23691 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23693 /* NCEF but for MVE predicated instructions. */
23694 #define MNCEF(mnem, op, nops, ops, enc) \
23695 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23698 static const struct asm_opcode insns
[] =
23700 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23701 #define THUMB_VARIANT & arm_ext_v4t
23702 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23703 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23704 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23705 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23706 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23707 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23708 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23709 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23710 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23711 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23712 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23713 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23714 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23715 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23716 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23717 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23719 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23720 for setting PSR flag bits. They are obsolete in V6 and do not
23721 have Thumb equivalents. */
23722 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23723 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23724 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23725 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23726 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23727 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23728 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23729 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23730 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23732 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23733 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23734 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23735 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23737 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23738 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23739 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23741 OP_ADDRGLDR
),ldst
, t_ldst
),
23742 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23744 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23745 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23746 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23747 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23748 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23749 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23751 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23752 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23755 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23756 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23757 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23758 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23760 /* Thumb-compatibility pseudo ops. */
23761 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23762 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23763 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23764 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23765 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23766 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23767 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23768 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23769 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23770 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23771 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23772 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23774 /* These may simplify to neg. */
23775 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23776 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23778 #undef THUMB_VARIANT
23779 #define THUMB_VARIANT & arm_ext_os
23781 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23782 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23784 #undef THUMB_VARIANT
23785 #define THUMB_VARIANT & arm_ext_v6
23787 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23789 /* V1 instructions with no Thumb analogue prior to V6T2. */
23790 #undef THUMB_VARIANT
23791 #define THUMB_VARIANT & arm_ext_v6t2
23793 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23794 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23795 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23797 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23798 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23799 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23800 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23802 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23803 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23805 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23806 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23808 /* V1 instructions with no Thumb analogue at all. */
23809 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23810 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23812 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23813 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23814 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23815 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23816 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23817 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23818 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23819 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23822 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23823 #undef THUMB_VARIANT
23824 #define THUMB_VARIANT & arm_ext_v4t
23826 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23827 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23829 #undef THUMB_VARIANT
23830 #define THUMB_VARIANT & arm_ext_v6t2
23832 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23833 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23835 /* Generic coprocessor instructions. */
23836 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23837 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23838 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23839 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23840 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23841 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23842 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23845 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23847 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23848 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23851 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23852 #undef THUMB_VARIANT
23853 #define THUMB_VARIANT & arm_ext_msr
23855 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23856 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23859 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23860 #undef THUMB_VARIANT
23861 #define THUMB_VARIANT & arm_ext_v6t2
23863 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23864 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23865 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23866 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23867 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23868 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23869 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23870 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23873 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23874 #undef THUMB_VARIANT
23875 #define THUMB_VARIANT & arm_ext_v4t
23877 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23878 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23879 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23880 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23881 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23882 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23885 #define ARM_VARIANT & arm_ext_v4t_5
23887 /* ARM Architecture 4T. */
23888 /* Note: bx (and blx) are required on V5, even if the processor does
23889 not support Thumb. */
23890 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23893 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23894 #undef THUMB_VARIANT
23895 #define THUMB_VARIANT & arm_ext_v5t
23897 /* Note: blx has 2 variants; the .value coded here is for
23898 BLX(2). Only this variant has conditional execution. */
23899 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23900 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23902 #undef THUMB_VARIANT
23903 #define THUMB_VARIANT & arm_ext_v6t2
23905 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23906 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23907 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23908 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23909 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23910 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23911 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23912 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23915 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23916 #undef THUMB_VARIANT
23917 #define THUMB_VARIANT & arm_ext_v5exp
23919 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23920 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23921 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23922 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23924 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23925 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23927 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23928 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23929 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23930 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23932 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23933 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23934 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23935 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23937 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23938 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23940 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23941 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23942 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23943 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23946 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23947 #undef THUMB_VARIANT
23948 #define THUMB_VARIANT & arm_ext_v6t2
23950 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23951 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23953 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23954 ADDRGLDRS
), ldrd
, t_ldstd
),
23956 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23957 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23960 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23962 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23965 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23966 #undef THUMB_VARIANT
23967 #define THUMB_VARIANT & arm_ext_v6
23969 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23970 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23971 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23972 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23973 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23974 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23975 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23976 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23977 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23978 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23980 #undef THUMB_VARIANT
23981 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23983 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23984 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23986 #undef THUMB_VARIANT
23987 #define THUMB_VARIANT & arm_ext_v6t2
23989 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23990 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23992 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23993 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23995 /* ARM V6 not included in V7M. */
23996 #undef THUMB_VARIANT
23997 #define THUMB_VARIANT & arm_ext_v6_notm
23998 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23999 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24000 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24001 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24002 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24003 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24004 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24005 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24006 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24007 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24008 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24009 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24010 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24011 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24012 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24013 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24014 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24015 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24016 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24018 /* ARM V6 not included in V7M (eg. integer SIMD). */
24019 #undef THUMB_VARIANT
24020 #define THUMB_VARIANT & arm_ext_v6_dsp
24021 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24022 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24023 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24024 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24025 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24026 /* Old name for QASX. */
24027 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24028 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24029 /* Old name for QSAX. */
24030 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24031 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24032 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24033 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24034 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24035 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24036 /* Old name for SASX. */
24037 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24038 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24039 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24040 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24041 /* Old name for SHASX. */
24042 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24043 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24044 /* Old name for SHSAX. */
24045 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24046 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24047 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24048 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24049 /* Old name for SSAX. */
24050 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24051 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24052 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24053 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24054 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24055 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24056 /* Old name for UASX. */
24057 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24058 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24059 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24060 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24061 /* Old name for UHASX. */
24062 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24063 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24064 /* Old name for UHSAX. */
24065 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24066 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24067 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24068 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24069 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24070 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24071 /* Old name for UQASX. */
24072 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24073 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24074 /* Old name for UQSAX. */
24075 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24076 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24077 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24078 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24079 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24080 /* Old name for USAX. */
24081 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24082 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24083 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24084 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24085 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24086 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24087 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24088 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24089 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24090 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24091 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24092 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24093 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24094 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24095 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24096 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24097 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24098 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24099 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24100 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24101 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24102 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24103 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24104 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24105 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24106 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24107 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24108 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24109 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24110 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24111 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24112 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24113 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24114 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24117 #define ARM_VARIANT & arm_ext_v6k_v6t2
24118 #undef THUMB_VARIANT
24119 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24121 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24122 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24123 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24124 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24126 #undef THUMB_VARIANT
24127 #define THUMB_VARIANT & arm_ext_v6_notm
24128 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24130 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24131 RRnpcb
), strexd
, t_strexd
),
24133 #undef THUMB_VARIANT
24134 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24135 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24137 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24139 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24141 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24143 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24146 #define ARM_VARIANT & arm_ext_sec
24147 #undef THUMB_VARIANT
24148 #define THUMB_VARIANT & arm_ext_sec
24150 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24153 #define ARM_VARIANT & arm_ext_virt
24154 #undef THUMB_VARIANT
24155 #define THUMB_VARIANT & arm_ext_virt
24157 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24158 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24161 #define ARM_VARIANT & arm_ext_pan
24162 #undef THUMB_VARIANT
24163 #define THUMB_VARIANT & arm_ext_pan
24165 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24168 #define ARM_VARIANT & arm_ext_v6t2
24169 #undef THUMB_VARIANT
24170 #define THUMB_VARIANT & arm_ext_v6t2
24172 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24173 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24174 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24175 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24177 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24178 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24180 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24181 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24182 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24183 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24186 #define ARM_VARIANT & arm_ext_v3
24187 #undef THUMB_VARIANT
24188 #define THUMB_VARIANT & arm_ext_v6t2
24190 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24191 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24192 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24195 #define ARM_VARIANT & arm_ext_v6t2
24196 #undef THUMB_VARIANT
24197 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24198 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24199 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24201 /* Thumb-only instructions. */
24203 #define ARM_VARIANT NULL
24204 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24205 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24207 /* ARM does not really have an IT instruction, so always allow it.
24208 The opcode is copied from Thumb in order to allow warnings in
24209 -mimplicit-it=[never | arm] modes. */
24211 #define ARM_VARIANT & arm_ext_v1
24212 #undef THUMB_VARIANT
24213 #define THUMB_VARIANT & arm_ext_v6t2
24215 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24216 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24217 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24218 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24219 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24220 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24221 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24222 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24223 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24224 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24225 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24226 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24227 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24228 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24229 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24230 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24231 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24232 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24234 /* Thumb2 only instructions. */
24236 #define ARM_VARIANT NULL
24238 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24239 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24240 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24241 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24242 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24243 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24245 /* Hardware division instructions. */
24247 #define ARM_VARIANT & arm_ext_adiv
24248 #undef THUMB_VARIANT
24249 #define THUMB_VARIANT & arm_ext_div
24251 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24252 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24254 /* ARM V6M/V7 instructions. */
24256 #define ARM_VARIANT & arm_ext_barrier
24257 #undef THUMB_VARIANT
24258 #define THUMB_VARIANT & arm_ext_barrier
24260 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24261 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24262 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24264 /* ARM V7 instructions. */
24266 #define ARM_VARIANT & arm_ext_v7
24267 #undef THUMB_VARIANT
24268 #define THUMB_VARIANT & arm_ext_v7
24270 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24271 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24274 #define ARM_VARIANT & arm_ext_mp
24275 #undef THUMB_VARIANT
24276 #define THUMB_VARIANT & arm_ext_mp
24278 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24280 /* AArchv8 instructions. */
24282 #define ARM_VARIANT & arm_ext_v8
24284 /* Instructions shared between armv8-a and armv8-m. */
24285 #undef THUMB_VARIANT
24286 #define THUMB_VARIANT & arm_ext_atomics
24288 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24289 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24290 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24291 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24292 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24293 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24294 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24295 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24296 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24297 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24299 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24301 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24303 #undef THUMB_VARIANT
24304 #define THUMB_VARIANT & arm_ext_v8
24306 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24307 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24309 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24312 /* Defined in V8 but is in undefined encoding space for earlier
24313 architectures. However earlier architectures are required to treat
24314 this instuction as a semihosting trap as well. Hence while not explicitly
24315 defined as such, it is in fact correct to define the instruction for all
24317 #undef THUMB_VARIANT
24318 #define THUMB_VARIANT & arm_ext_v1
24320 #define ARM_VARIANT & arm_ext_v1
24321 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24323 /* ARMv8 T32 only. */
24325 #define ARM_VARIANT NULL
24326 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24327 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24328 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24330 /* FP for ARMv8. */
24332 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24333 #undef THUMB_VARIANT
24334 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24336 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24337 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24338 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24339 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24340 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24341 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24342 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24343 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24344 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24345 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24346 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24348 /* Crypto v1 extensions. */
24350 #define ARM_VARIANT & fpu_crypto_ext_armv8
24351 #undef THUMB_VARIANT
24352 #define THUMB_VARIANT & fpu_crypto_ext_armv8
24354 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
24355 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
24356 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
24357 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
24358 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
24359 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
24360 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
24361 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
24362 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
24363 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
24364 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
24365 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
24366 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
24367 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
24370 #define ARM_VARIANT & crc_ext_armv8
24371 #undef THUMB_VARIANT
24372 #define THUMB_VARIANT & crc_ext_armv8
24373 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
24374 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
24375 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
24376 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
24377 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
24378 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
24380 /* ARMv8.2 RAS extension. */
24382 #define ARM_VARIANT & arm_ext_ras
24383 #undef THUMB_VARIANT
24384 #define THUMB_VARIANT & arm_ext_ras
24385 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
24388 #define ARM_VARIANT & arm_ext_v8_3
24389 #undef THUMB_VARIANT
24390 #define THUMB_VARIANT & arm_ext_v8_3
24391 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
24394 #define ARM_VARIANT & fpu_neon_ext_dotprod
24395 #undef THUMB_VARIANT
24396 #define THUMB_VARIANT & fpu_neon_ext_dotprod
24397 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
24398 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
24401 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
24402 #undef THUMB_VARIANT
24403 #define THUMB_VARIANT NULL
24405 cCE("wfs", e200110
, 1, (RR
), rd
),
24406 cCE("rfs", e300110
, 1, (RR
), rd
),
24407 cCE("wfc", e400110
, 1, (RR
), rd
),
24408 cCE("rfc", e500110
, 1, (RR
), rd
),
24410 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24411 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24412 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24413 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24415 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24416 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24417 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24418 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24420 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
24421 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
24422 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
24423 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
24424 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
24425 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
24426 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
24427 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
24428 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
24429 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
24430 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
24431 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
24433 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
24434 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
24435 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
24436 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
24437 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
24438 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
24439 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
24440 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
24441 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
24442 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
24443 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
24444 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
24446 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
24447 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
24448 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
24449 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
24450 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
24451 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
24452 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
24453 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
24454 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
24455 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
24456 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
24457 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
24459 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
24460 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
24461 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
24462 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
24463 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
24464 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
24465 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
24466 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
24467 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
24468 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
24469 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
24470 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
24472 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
24473 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24474 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24475 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24476 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24477 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24478 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24479 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24480 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24481 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24482 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24483 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24485 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24486 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24487 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24488 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24489 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24490 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24491 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24492 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24493 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24494 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24495 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24496 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24498 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24499 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24500 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24501 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24502 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24503 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24504 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24505 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24506 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24507 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24508 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24509 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24511 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24512 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24513 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24514 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24515 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24516 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24517 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24518 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24519 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24520 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24521 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24522 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24524 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24525 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24526 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24527 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24528 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24529 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24530 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24531 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24532 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24533 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24534 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24535 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24537 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24538 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24539 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24540 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24541 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24542 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24543 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24544 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24545 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24546 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24547 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24548 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24550 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24551 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24552 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24553 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24554 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24555 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24556 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24557 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24558 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24559 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24560 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24561 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24563 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24564 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24565 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24566 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24567 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24568 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24569 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24570 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24571 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24572 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24573 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24574 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24576 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24577 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24578 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24579 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24580 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24581 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24582 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24583 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24584 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24585 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24586 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24587 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24589 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24590 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24591 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24592 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24593 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24594 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24595 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24596 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24597 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24598 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24599 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24600 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24602 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24603 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24604 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24605 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24606 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24607 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24608 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24609 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24610 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24611 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24612 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24613 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24615 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24616 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24617 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24618 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24619 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24620 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24621 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24622 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24623 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24624 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24625 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24626 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24628 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24629 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24630 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24631 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24632 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24633 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24634 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24635 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24636 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24637 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24638 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24639 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24641 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24642 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24643 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24644 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24645 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24646 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24647 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24648 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24649 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24650 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24651 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24652 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24654 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24655 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24656 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24657 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24658 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24659 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24660 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24661 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24662 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24663 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24664 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24665 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24667 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24668 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24669 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24670 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24671 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24672 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24673 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24674 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24675 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24676 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24677 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24678 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24680 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24681 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24682 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24683 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24684 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24685 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24686 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24687 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24688 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24689 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24690 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24691 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24693 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24694 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24695 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24696 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24697 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24698 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24699 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24700 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24701 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24702 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24703 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24704 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24706 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24707 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24708 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24709 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24710 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24711 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24712 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24713 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24714 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24715 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24716 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24717 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24719 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24720 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24721 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24722 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24723 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24724 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24725 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24726 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24727 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24728 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24729 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24730 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24732 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24733 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24734 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24735 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24736 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24737 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24738 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24739 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24740 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24741 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24742 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24743 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24745 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24746 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24747 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24748 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24749 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24750 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24751 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24752 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24753 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24754 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24755 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24756 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24758 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24759 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24760 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24761 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24762 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24763 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24764 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24765 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24766 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24767 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24768 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24769 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24771 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24772 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24773 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24774 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24775 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24776 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24777 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24778 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24779 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24780 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24781 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24782 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24784 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24785 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24786 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24787 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24788 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24789 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24790 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24791 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24792 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24793 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24794 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24795 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24797 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24798 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24799 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24800 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24802 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24803 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24804 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24805 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24806 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24807 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24808 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24809 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24810 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24811 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24812 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24813 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24815 /* The implementation of the FIX instruction is broken on some
24816 assemblers, in that it accepts a precision specifier as well as a
24817 rounding specifier, despite the fact that this is meaningless.
24818 To be more compatible, we accept it as well, though of course it
24819 does not set any bits. */
24820 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24821 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24822 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24823 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24824 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24825 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24826 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24827 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24828 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24829 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24830 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24831 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24832 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24834 /* Instructions that were new with the real FPA, call them V2. */
24836 #define ARM_VARIANT & fpu_fpa_ext_v2
24838 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24839 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24840 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24841 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24842 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24843 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24846 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24847 #undef THUMB_VARIANT
24848 #define THUMB_VARIANT & arm_ext_v6t2
24849 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24850 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
24851 #undef THUMB_VARIANT
24853 /* Moves and type conversions. */
24854 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24855 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24856 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24857 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24858 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24859 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24860 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24861 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24862 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24864 /* Memory operations. */
24865 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24866 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24867 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24868 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24869 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24870 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24871 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24872 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24873 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24874 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24875 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24876 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24877 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24878 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24879 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24880 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24881 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24882 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24884 /* Monadic operations. */
24885 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24886 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24887 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24889 /* Dyadic operations. */
24890 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24891 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24892 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24893 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24894 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24895 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24896 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24897 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24898 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24901 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24902 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24903 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24904 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24906 /* Double precision load/store are still present on single precision
24907 implementations. */
24908 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24909 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24910 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24911 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24912 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24913 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24914 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24915 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24916 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24917 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24920 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24922 /* Moves and type conversions. */
24923 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24924 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24925 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24926 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24927 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24928 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24929 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24930 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24931 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24932 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24933 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24934 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24936 /* Monadic operations. */
24937 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24938 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24939 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24941 /* Dyadic operations. */
24942 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24943 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24944 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24945 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24946 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24947 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24948 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24949 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24950 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24953 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24954 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24955 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24956 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24958 /* Instructions which may belong to either the Neon or VFP instruction sets.
24959 Individual encoder functions perform additional architecture checks. */
24961 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24962 #undef THUMB_VARIANT
24963 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24965 /* These mnemonics are unique to VFP. */
24966 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24967 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24968 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24969 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24970 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24971 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24972 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24973 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24975 /* Mnemonics shared by Neon and VFP. */
24976 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24978 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24979 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24980 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24981 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24982 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24983 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24985 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24986 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24987 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24988 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24991 /* NOTE: All VMOV encoding is special-cased! */
24992 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24994 #undef THUMB_VARIANT
24995 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24996 by different feature bits. Since we are setting the Thumb guard, we can
24997 require Thumb-1 which makes it a nop guard and set the right feature bit in
24998 do_vldr_vstr (). */
24999 #define THUMB_VARIANT & arm_ext_v4t
25000 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25001 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25004 #define ARM_VARIANT & arm_ext_fp16
25005 #undef THUMB_VARIANT
25006 #define THUMB_VARIANT & arm_ext_fp16
25007 /* New instructions added from v8.2, allowing the extraction and insertion of
25008 the upper 16 bits of a 32-bit vector register. */
25009 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25010 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25012 /* New backported fma/fms instructions optional in v8.2. */
25013 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25014 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25016 #undef THUMB_VARIANT
25017 #define THUMB_VARIANT & fpu_neon_ext_v1
25019 #define ARM_VARIANT & fpu_neon_ext_v1
25021 /* Data processing with three registers of the same length. */
25022 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25023 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25024 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25025 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25026 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25027 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25028 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25029 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25030 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25031 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25032 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25033 /* If not immediate, fall back to neon_dyadic_i64_su.
25034 shl should accept I8 I16 I32 I64,
25035 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25036 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25037 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25038 /* Logic ops, types optional & ignored. */
25039 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25040 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25041 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25042 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25043 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25044 /* Bitfield ops, untyped. */
25045 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25046 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25047 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25048 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25049 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25050 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25051 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25052 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25053 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25054 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25055 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25056 back to neon_dyadic_if_su. */
25057 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25058 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25059 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25060 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25061 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25062 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25063 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25064 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25065 /* Comparison. Type I8 I16 I32 F32. */
25066 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25067 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25068 /* As above, D registers only. */
25069 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25070 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25071 /* Int and float variants, signedness unimportant. */
25072 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25073 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25074 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25075 /* Add/sub take types I8 I16 I32 I64 F32. */
25076 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25077 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25078 /* vtst takes sizes 8, 16, 32. */
25079 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25080 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25081 /* VMUL takes I8 I16 I32 F32 P8. */
25082 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25083 /* VQD{R}MULH takes S16 S32. */
25084 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25085 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25086 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25087 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25088 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25089 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25090 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25091 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25092 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25093 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25094 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25095 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25096 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25097 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25098 /* ARM v8.1 extension. */
25099 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25100 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25101 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25103 /* Two address, int/float. Types S8 S16 S32 F32. */
25104 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25105 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25107 /* Data processing with two registers and a shift amount. */
25108 /* Right shifts, and variants with rounding.
25109 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25110 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25111 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25112 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25113 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25114 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25115 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25116 /* Shift and insert. Sizes accepted 8 16 32 64. */
25117 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25118 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25119 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25120 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25121 /* Right shift immediate, saturating & narrowing, with rounding variants.
25122 Types accepted S16 S32 S64 U16 U32 U64. */
25123 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25124 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25125 /* As above, unsigned. Types accepted S16 S32 S64. */
25126 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25127 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25128 /* Right shift narrowing. Types accepted I16 I32 I64. */
25129 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25130 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25131 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25132 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25133 /* CVT with optional immediate for fixed-point variant. */
25134 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25136 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25138 /* Data processing, three registers of different lengths. */
25139 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25140 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25141 /* If not scalar, fall back to neon_dyadic_long.
25142 Vector types as above, scalar types S16 S32 U16 U32. */
25143 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25144 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25145 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25146 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25147 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25148 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25149 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25150 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25151 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25152 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25153 /* Saturating doubling multiplies. Types S16 S32. */
25154 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25155 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25156 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25157 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25158 S16 S32 U16 U32. */
25159 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25161 /* Extract. Size 8. */
25162 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25163 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25165 /* Two registers, miscellaneous. */
25166 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25167 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25168 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25169 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25170 /* Vector replicate. Sizes 8 16 32. */
25171 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25172 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25173 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25174 /* VMOVN. Types I16 I32 I64. */
25175 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25176 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25177 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25178 /* VQMOVUN. Types S16 S32 S64. */
25179 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25180 /* VZIP / VUZP. Sizes 8 16 32. */
25181 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25182 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25183 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25184 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25185 /* VQABS / VQNEG. Types S8 S16 S32. */
25186 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25187 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25188 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25189 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25190 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25191 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25192 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25193 /* Reciprocal estimates. Types U32 F16 F32. */
25194 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25195 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25196 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25197 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25198 /* VCLS. Types S8 S16 S32. */
25199 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25200 /* VCLZ. Types I8 I16 I32. */
25201 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25202 /* VCNT. Size 8. */
25203 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25204 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25205 /* Two address, untyped. */
25206 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25207 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25208 /* VTRN. Sizes 8 16 32. */
25209 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25210 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25212 /* Table lookup. Size 8. */
25213 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25214 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25216 #undef THUMB_VARIANT
25217 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25219 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25221 /* Neon element/structure load/store. */
25222 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25223 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25224 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25225 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25226 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25227 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25228 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25229 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25231 #undef THUMB_VARIANT
25232 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25234 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25235 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25236 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25237 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25238 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25239 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25240 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25241 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25242 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25243 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25245 #undef THUMB_VARIANT
25246 #define THUMB_VARIANT & fpu_vfp_ext_v3
25248 #define ARM_VARIANT & fpu_vfp_ext_v3
25250 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25251 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25252 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25253 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25254 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25255 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25256 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25257 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25258 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25261 #define ARM_VARIANT & fpu_vfp_ext_fma
25262 #undef THUMB_VARIANT
25263 #define THUMB_VARIANT & fpu_vfp_ext_fma
25264 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25265 VFP FMA variant; NEON and VFP FMA always includes the NEON
25266 FMA instructions. */
25267 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25268 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25269 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25271 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25272 the v form should always be used. */
25273 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25274 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25275 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25276 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25277 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25278 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25280 #undef THUMB_VARIANT
25282 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25284 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25285 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25286 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25287 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25288 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25289 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25290 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25291 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25294 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25296 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25297 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25298 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25299 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25300 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25301 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25302 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25303 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25304 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25305 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25306 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25307 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25308 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25309 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25310 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25311 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25312 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25313 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25314 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25315 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25316 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25317 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25318 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25319 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25320 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25321 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25322 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25323 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25324 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25325 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25326 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25327 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25328 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25329 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25330 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25331 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25332 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25333 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25334 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25335 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25336 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25337 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25338 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25339 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25340 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25341 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25342 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25343 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25344 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25345 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25346 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25347 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25348 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25349 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25350 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25351 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25352 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25353 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25354 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25355 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25356 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25357 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25358 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25359 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25360 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25361 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25362 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25363 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25364 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25365 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25366 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25367 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25368 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25369 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25370 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25371 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25372 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25373 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25374 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25375 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25376 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25377 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25378 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25379 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25380 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25381 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25382 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25383 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25384 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
25385 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25386 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25387 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25388 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25389 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25390 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25391 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25392 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25393 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25394 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25395 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25396 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25397 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25398 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25399 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25400 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25401 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25402 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25403 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25404 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25405 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25406 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
25407 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25408 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25409 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25410 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25411 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25412 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25413 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25414 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25415 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25416 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25417 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25418 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25419 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25420 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25421 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25422 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25423 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25424 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25425 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25426 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25427 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25428 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25429 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25430 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25431 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25432 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25433 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25434 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25435 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25436 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25437 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25438 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25439 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25440 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25441 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25442 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25443 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25444 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25445 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25446 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25447 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25448 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25449 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25450 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25451 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25452 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25453 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25454 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25455 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25456 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25457 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
25460 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25462 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
25463 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
25464 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
25465 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25466 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25467 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25468 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25469 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25470 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25471 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25472 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25473 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25474 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25475 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25476 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25477 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25478 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25479 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25480 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25481 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25482 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25483 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25484 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25485 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25486 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25487 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25488 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25489 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25490 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25491 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25492 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25493 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25494 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25495 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25496 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25497 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25498 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25499 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25500 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25501 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25502 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25503 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25504 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25505 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25506 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25507 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25508 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25509 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25510 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25511 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25512 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25513 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25514 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25515 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25516 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25517 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25518 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25521 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25523 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25524 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25525 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25526 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25527 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25528 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25529 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25530 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25531 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25532 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25533 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25534 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25535 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25536 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25537 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25538 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25539 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25540 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25541 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25542 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25543 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25544 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25545 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25546 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25547 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25548 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25549 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25550 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25551 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25552 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25553 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25554 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25555 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25556 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25557 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25558 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25559 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25560 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25561 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25562 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25563 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25564 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25565 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25566 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25567 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25568 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25569 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25570 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25571 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25572 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25573 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25574 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25575 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25576 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25577 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25578 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25579 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25580 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25581 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25582 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25583 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25584 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25585 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25586 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25587 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25588 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25589 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25590 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25591 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25592 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25593 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25594 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25595 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25596 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25597 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25598 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25600 /* ARMv8.5-A instructions. */
25602 #define ARM_VARIANT & arm_ext_sb
25603 #undef THUMB_VARIANT
25604 #define THUMB_VARIANT & arm_ext_sb
25605 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25608 #define ARM_VARIANT & arm_ext_predres
25609 #undef THUMB_VARIANT
25610 #define THUMB_VARIANT & arm_ext_predres
25611 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25612 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25613 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25615 /* ARMv8-M instructions. */
25617 #define ARM_VARIANT NULL
25618 #undef THUMB_VARIANT
25619 #define THUMB_VARIANT & arm_ext_v8m
25620 ToU("sg", e97fe97f
, 0, (), noargs
),
25621 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25622 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25623 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25624 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25625 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25626 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25628 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25629 instructions behave as nop if no VFP is present. */
25630 #undef THUMB_VARIANT
25631 #define THUMB_VARIANT & arm_ext_v8m_main
25632 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25633 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25635 /* Armv8.1-M Mainline instructions. */
25636 #undef THUMB_VARIANT
25637 #define THUMB_VARIANT & arm_ext_v8_1m_main
25638 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25639 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25640 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25641 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25642 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
25643 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
25644 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25645 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25646 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25648 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25649 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25650 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25651 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25652 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25654 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25655 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25656 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25658 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25659 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25661 #undef THUMB_VARIANT
25662 #define THUMB_VARIANT & mve_ext
25663 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25664 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25665 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25666 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25667 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
25668 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25669 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25670 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25671 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25672 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25673 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25674 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25675 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25676 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25677 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25679 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25680 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25681 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25682 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25683 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25684 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25685 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25686 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25687 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25688 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25689 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25690 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25691 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25692 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25693 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25695 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25696 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25697 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25698 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25699 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25700 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25701 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25702 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25703 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25704 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25705 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25706 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25707 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25708 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25709 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25711 /* MVE and MVE FP only. */
25712 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25713 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
25714 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25715 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25716 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25717 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25718 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25719 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25720 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25721 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25722 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25723 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25724 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25725 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25726 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25727 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25728 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25729 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25731 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25732 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25733 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25734 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25735 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25736 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25737 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25738 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25739 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25740 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25741 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25742 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25743 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25744 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25745 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25746 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25747 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25748 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25749 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25750 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25752 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25753 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25754 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25755 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25756 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25757 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25758 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25759 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25760 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25761 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25762 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25763 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25764 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25765 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25766 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25767 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25768 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25770 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25771 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25772 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25773 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25774 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25775 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25776 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25777 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25778 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25779 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25780 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25781 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25782 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25783 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25784 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25785 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25786 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25787 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25788 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25789 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25791 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25792 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25793 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25794 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25795 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25797 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25798 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25799 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25800 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25801 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25802 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25803 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25804 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25805 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25806 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25807 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25808 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25809 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25810 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25811 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25812 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25813 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25815 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25816 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25817 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25818 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25819 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25820 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25821 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25822 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25823 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25824 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25825 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25826 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25828 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25829 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25830 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25832 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25833 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25834 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25835 toU("lctp", _lctp
, 0, (), t_loloop
),
25837 #undef THUMB_VARIANT
25838 #define THUMB_VARIANT & mve_fp_ext
25839 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25840 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25841 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25842 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25843 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25844 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25845 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25846 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25849 #define ARM_VARIANT & fpu_vfp_ext_v1
25850 #undef THUMB_VARIANT
25851 #define THUMB_VARIANT & arm_ext_v6t2
25852 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25853 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25855 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25858 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25860 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25861 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25862 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25863 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25865 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25866 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25867 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25869 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25870 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25872 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25873 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25875 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25876 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25879 #define ARM_VARIANT & fpu_vfp_ext_v2
25881 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25882 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25883 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25884 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25887 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25888 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25889 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25890 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25891 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25892 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25893 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25896 #define ARM_VARIANT & fpu_neon_ext_v1
25897 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25898 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25899 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25900 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25901 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25902 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25903 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25904 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25905 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25906 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25907 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25908 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25909 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25910 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25911 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25912 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25913 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25914 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25915 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25916 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25917 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25918 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25919 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25920 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25921 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25922 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25923 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25924 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25925 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25926 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25927 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25928 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25929 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25930 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25931 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25932 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25933 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25936 #define ARM_VARIANT & arm_ext_v8_3
25937 #undef THUMB_VARIANT
25938 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25939 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25940 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25943 #define ARM_VARIANT &arm_ext_bf16
25944 #undef THUMB_VARIANT
25945 #define THUMB_VARIANT &arm_ext_bf16
25946 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
25947 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
25948 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
25951 #define ARM_VARIANT &arm_ext_i8mm
25952 #undef THUMB_VARIANT
25953 #define THUMB_VARIANT &arm_ext_i8mm
25954 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
25955 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
25956 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
25957 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
25958 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
25961 #undef THUMB_VARIANT
25993 /* MD interface: bits in the object file. */
25995 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25996 for use in the a.out file, and stores them in the array pointed to by buf.
25997 This knows about the endian-ness of the target machine and does
25998 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25999 2 (short) and 4 (long) Floating numbers are put out as a series of
26000 LITTLENUMS (shorts, here at least). */
26003 md_number_to_chars (char * buf
, valueT val
, int n
)
26005 if (target_big_endian
)
26006 number_to_chars_bigendian (buf
, val
, n
);
26008 number_to_chars_littleendian (buf
, val
, n
);
26012 md_chars_to_number (char * buf
, int n
)
26015 unsigned char * where
= (unsigned char *) buf
;
26017 if (target_big_endian
)
26022 result
|= (*where
++ & 255);
26030 result
|= (where
[n
] & 255);
26037 /* MD interface: Sections. */
26039 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26040 that an rs_machine_dependent frag may reach. */
26043 arm_frag_max_var (fragS
*fragp
)
26045 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26046 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26048 Note that we generate relaxable instructions even for cases that don't
26049 really need it, like an immediate that's a trivial constant. So we're
26050 overestimating the instruction size for some of those cases. Rather
26051 than putting more intelligence here, it would probably be better to
26052 avoid generating a relaxation frag in the first place when it can be
26053 determined up front that a short instruction will suffice. */
26055 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26059 /* Estimate the size of a frag before relaxing. Assume everything fits in
26063 md_estimate_size_before_relax (fragS
* fragp
,
26064 segT segtype ATTRIBUTE_UNUSED
)
26070 /* Convert a machine dependent frag. */
26073 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26075 unsigned long insn
;
26076 unsigned long old_op
;
26084 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26086 old_op
= bfd_get_16(abfd
, buf
);
26087 if (fragp
->fr_symbol
)
26089 exp
.X_op
= O_symbol
;
26090 exp
.X_add_symbol
= fragp
->fr_symbol
;
26094 exp
.X_op
= O_constant
;
26096 exp
.X_add_number
= fragp
->fr_offset
;
26097 opcode
= fragp
->fr_subtype
;
26100 case T_MNEM_ldr_pc
:
26101 case T_MNEM_ldr_pc2
:
26102 case T_MNEM_ldr_sp
:
26103 case T_MNEM_str_sp
:
26110 if (fragp
->fr_var
== 4)
26112 insn
= THUMB_OP32 (opcode
);
26113 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26115 insn
|= (old_op
& 0x700) << 4;
26119 insn
|= (old_op
& 7) << 12;
26120 insn
|= (old_op
& 0x38) << 13;
26122 insn
|= 0x00000c00;
26123 put_thumb32_insn (buf
, insn
);
26124 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26128 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26130 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26133 if (fragp
->fr_var
== 4)
26135 insn
= THUMB_OP32 (opcode
);
26136 insn
|= (old_op
& 0xf0) << 4;
26137 put_thumb32_insn (buf
, insn
);
26138 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26142 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26143 exp
.X_add_number
-= 4;
26151 if (fragp
->fr_var
== 4)
26153 int r0off
= (opcode
== T_MNEM_mov
26154 || opcode
== T_MNEM_movs
) ? 0 : 8;
26155 insn
= THUMB_OP32 (opcode
);
26156 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26157 insn
|= (old_op
& 0x700) << r0off
;
26158 put_thumb32_insn (buf
, insn
);
26159 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26163 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26168 if (fragp
->fr_var
== 4)
26170 insn
= THUMB_OP32(opcode
);
26171 put_thumb32_insn (buf
, insn
);
26172 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26175 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26179 if (fragp
->fr_var
== 4)
26181 insn
= THUMB_OP32(opcode
);
26182 insn
|= (old_op
& 0xf00) << 14;
26183 put_thumb32_insn (buf
, insn
);
26184 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26187 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26190 case T_MNEM_add_sp
:
26191 case T_MNEM_add_pc
:
26192 case T_MNEM_inc_sp
:
26193 case T_MNEM_dec_sp
:
26194 if (fragp
->fr_var
== 4)
26196 /* ??? Choose between add and addw. */
26197 insn
= THUMB_OP32 (opcode
);
26198 insn
|= (old_op
& 0xf0) << 4;
26199 put_thumb32_insn (buf
, insn
);
26200 if (opcode
== T_MNEM_add_pc
)
26201 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26203 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26206 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26214 if (fragp
->fr_var
== 4)
26216 insn
= THUMB_OP32 (opcode
);
26217 insn
|= (old_op
& 0xf0) << 4;
26218 insn
|= (old_op
& 0xf) << 16;
26219 put_thumb32_insn (buf
, insn
);
26220 if (insn
& (1 << 20))
26221 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26223 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26226 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26232 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26233 (enum bfd_reloc_code_real
) reloc_type
);
26234 fixp
->fx_file
= fragp
->fr_file
;
26235 fixp
->fx_line
= fragp
->fr_line
;
26236 fragp
->fr_fix
+= fragp
->fr_var
;
26238 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26239 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26240 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26241 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26244 /* Return the size of a relaxable immediate operand instruction.
26245 SHIFT and SIZE specify the form of the allowable immediate. */
26247 relax_immediate (fragS
*fragp
, int size
, int shift
)
26253 /* ??? Should be able to do better than this. */
26254 if (fragp
->fr_symbol
)
26257 low
= (1 << shift
) - 1;
26258 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26259 offset
= fragp
->fr_offset
;
26260 /* Force misaligned offsets to 32-bit variant. */
26263 if (offset
& ~mask
)
26268 /* Get the address of a symbol during relaxation. */
26270 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26276 sym
= fragp
->fr_symbol
;
26277 sym_frag
= symbol_get_frag (sym
);
26278 know (S_GET_SEGMENT (sym
) != absolute_section
26279 || sym_frag
== &zero_address_frag
);
26280 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26282 /* If frag has yet to be reached on this pass, assume it will
26283 move by STRETCH just as we did. If this is not so, it will
26284 be because some frag between grows, and that will force
26288 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26292 /* Adjust stretch for any alignment frag. Note that if have
26293 been expanding the earlier code, the symbol may be
26294 defined in what appears to be an earlier frag. FIXME:
26295 This doesn't handle the fr_subtype field, which specifies
26296 a maximum number of bytes to skip when doing an
26298 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26300 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26303 stretch
= - ((- stretch
)
26304 & ~ ((1 << (int) f
->fr_offset
) - 1));
26306 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
26318 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
26321 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
26326 /* Assume worst case for symbols not known to be in the same section. */
26327 if (fragp
->fr_symbol
== NULL
26328 || !S_IS_DEFINED (fragp
->fr_symbol
)
26329 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26330 || S_IS_WEAK (fragp
->fr_symbol
))
26333 val
= relaxed_symbol_addr (fragp
, stretch
);
26334 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
26335 addr
= (addr
+ 4) & ~3;
26336 /* Force misaligned targets to 32-bit variant. */
26340 if (val
< 0 || val
> 1020)
26345 /* Return the size of a relaxable add/sub immediate instruction. */
26347 relax_addsub (fragS
*fragp
, asection
*sec
)
26352 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26353 op
= bfd_get_16(sec
->owner
, buf
);
26354 if ((op
& 0xf) == ((op
>> 4) & 0xf))
26355 return relax_immediate (fragp
, 8, 0);
26357 return relax_immediate (fragp
, 3, 0);
26360 /* Return TRUE iff the definition of symbol S could be pre-empted
26361 (overridden) at link or load time. */
26363 symbol_preemptible (symbolS
*s
)
26365 /* Weak symbols can always be pre-empted. */
26369 /* Non-global symbols cannot be pre-empted. */
26370 if (! S_IS_EXTERNAL (s
))
26374 /* In ELF, a global symbol can be marked protected, or private. In that
26375 case it can't be pre-empted (other definitions in the same link unit
26376 would violate the ODR). */
26377 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
26381 /* Other global symbols might be pre-empted. */
26385 /* Return the size of a relaxable branch instruction. BITS is the
26386 size of the offset field in the narrow instruction. */
26389 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
26395 /* Assume worst case for symbols not known to be in the same section. */
26396 if (!S_IS_DEFINED (fragp
->fr_symbol
)
26397 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26398 || S_IS_WEAK (fragp
->fr_symbol
))
26402 /* A branch to a function in ARM state will require interworking. */
26403 if (S_IS_DEFINED (fragp
->fr_symbol
)
26404 && ARM_IS_FUNC (fragp
->fr_symbol
))
26408 if (symbol_preemptible (fragp
->fr_symbol
))
26411 val
= relaxed_symbol_addr (fragp
, stretch
);
26412 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
26415 /* Offset is a signed value *2 */
26417 if (val
>= limit
|| val
< -limit
)
26423 /* Relax a machine dependent frag. This returns the amount by which
26424 the current size of the frag should change. */
26427 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
26432 oldsize
= fragp
->fr_var
;
26433 switch (fragp
->fr_subtype
)
26435 case T_MNEM_ldr_pc2
:
26436 newsize
= relax_adr (fragp
, sec
, stretch
);
26438 case T_MNEM_ldr_pc
:
26439 case T_MNEM_ldr_sp
:
26440 case T_MNEM_str_sp
:
26441 newsize
= relax_immediate (fragp
, 8, 2);
26445 newsize
= relax_immediate (fragp
, 5, 2);
26449 newsize
= relax_immediate (fragp
, 5, 1);
26453 newsize
= relax_immediate (fragp
, 5, 0);
26456 newsize
= relax_adr (fragp
, sec
, stretch
);
26462 newsize
= relax_immediate (fragp
, 8, 0);
26465 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
26468 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
26470 case T_MNEM_add_sp
:
26471 case T_MNEM_add_pc
:
26472 newsize
= relax_immediate (fragp
, 8, 2);
26474 case T_MNEM_inc_sp
:
26475 case T_MNEM_dec_sp
:
26476 newsize
= relax_immediate (fragp
, 7, 2);
26482 newsize
= relax_addsub (fragp
, sec
);
26488 fragp
->fr_var
= newsize
;
26489 /* Freeze wide instructions that are at or before the same location as
26490 in the previous pass. This avoids infinite loops.
26491 Don't freeze them unconditionally because targets may be artificially
26492 misaligned by the expansion of preceding frags. */
26493 if (stretch
<= 0 && newsize
> 2)
26495 md_convert_frag (sec
->owner
, sec
, fragp
);
26499 return newsize
- oldsize
;
26502 /* Round up a section size to the appropriate boundary. */
26505 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26511 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26512 of an rs_align_code fragment. */
26515 arm_handle_align (fragS
* fragP
)
26517 static unsigned char const arm_noop
[2][2][4] =
26520 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26521 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26524 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26525 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26528 static unsigned char const thumb_noop
[2][2][2] =
26531 {0xc0, 0x46}, /* LE */
26532 {0x46, 0xc0}, /* BE */
26535 {0x00, 0xbf}, /* LE */
26536 {0xbf, 0x00} /* BE */
26539 static unsigned char const wide_thumb_noop
[2][4] =
26540 { /* Wide Thumb-2 */
26541 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26542 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26545 unsigned bytes
, fix
, noop_size
;
26547 const unsigned char * noop
;
26548 const unsigned char *narrow_noop
= NULL
;
26553 if (fragP
->fr_type
!= rs_align_code
)
26556 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26557 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26560 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26561 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26563 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26565 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26567 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26568 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26570 narrow_noop
= thumb_noop
[1][target_big_endian
];
26571 noop
= wide_thumb_noop
[target_big_endian
];
26574 noop
= thumb_noop
[0][target_big_endian
];
26582 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26583 ? selected_cpu
: arm_arch_none
,
26585 [target_big_endian
];
26592 fragP
->fr_var
= noop_size
;
26594 if (bytes
& (noop_size
- 1))
26596 fix
= bytes
& (noop_size
- 1);
26598 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26600 memset (p
, 0, fix
);
26607 if (bytes
& noop_size
)
26609 /* Insert a narrow noop. */
26610 memcpy (p
, narrow_noop
, noop_size
);
26612 bytes
-= noop_size
;
26616 /* Use wide noops for the remainder */
26620 while (bytes
>= noop_size
)
26622 memcpy (p
, noop
, noop_size
);
26624 bytes
-= noop_size
;
26628 fragP
->fr_fix
+= fix
;
26631 /* Called from md_do_align. Used to create an alignment
26632 frag in a code section. */
26635 arm_frag_align_code (int n
, int max
)
26639 /* We assume that there will never be a requirement
26640 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26641 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26646 _("alignments greater than %d bytes not supported in .text sections."),
26647 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26648 as_fatal ("%s", err_msg
);
26651 p
= frag_var (rs_align_code
,
26652 MAX_MEM_FOR_RS_ALIGN_CODE
,
26654 (relax_substateT
) max
,
26661 /* Perform target specific initialisation of a frag.
26662 Note - despite the name this initialisation is not done when the frag
26663 is created, but only when its type is assigned. A frag can be created
26664 and used a long time before its type is set, so beware of assuming that
26665 this initialisation is performed first. */
26669 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26671 /* Record whether this frag is in an ARM or a THUMB area. */
26672 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26675 #else /* OBJ_ELF is defined. */
26677 arm_init_frag (fragS
* fragP
, int max_chars
)
26679 bfd_boolean frag_thumb_mode
;
26681 /* If the current ARM vs THUMB mode has not already
26682 been recorded into this frag then do so now. */
26683 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26684 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26686 /* PR 21809: Do not set a mapping state for debug sections
26687 - it just confuses other tools. */
26688 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
26691 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26693 /* Record a mapping symbol for alignment frags. We will delete this
26694 later if the alignment ends up empty. */
26695 switch (fragP
->fr_type
)
26698 case rs_align_test
:
26700 mapping_state_2 (MAP_DATA
, max_chars
);
26702 case rs_align_code
:
26703 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26710 /* When we change sections we need to issue a new mapping symbol. */
26713 arm_elf_change_section (void)
26715 /* Link an unlinked unwind index table section to the .text section. */
26716 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26717 && elf_linked_to_section (now_seg
) == NULL
)
26718 elf_linked_to_section (now_seg
) = text_section
;
26722 arm_elf_section_type (const char * str
, size_t len
)
26724 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26725 return SHT_ARM_EXIDX
;
26730 /* Code to deal with unwinding tables. */
26732 static void add_unwind_adjustsp (offsetT
);
26734 /* Generate any deferred unwind frame offset. */
26737 flush_pending_unwind (void)
26741 offset
= unwind
.pending_offset
;
26742 unwind
.pending_offset
= 0;
26744 add_unwind_adjustsp (offset
);
26747 /* Add an opcode to this list for this function. Two-byte opcodes should
26748 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26752 add_unwind_opcode (valueT op
, int length
)
26754 /* Add any deferred stack adjustment. */
26755 if (unwind
.pending_offset
)
26756 flush_pending_unwind ();
26758 unwind
.sp_restored
= 0;
26760 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26762 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26763 if (unwind
.opcodes
)
26764 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26765 unwind
.opcode_alloc
);
26767 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26772 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26774 unwind
.opcode_count
++;
26778 /* Add unwind opcodes to adjust the stack pointer. */
26781 add_unwind_adjustsp (offsetT offset
)
26785 if (offset
> 0x200)
26787 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26792 /* Long form: 0xb2, uleb128. */
26793 /* This might not fit in a word so add the individual bytes,
26794 remembering the list is built in reverse order. */
26795 o
= (valueT
) ((offset
- 0x204) >> 2);
26797 add_unwind_opcode (0, 1);
26799 /* Calculate the uleb128 encoding of the offset. */
26803 bytes
[n
] = o
& 0x7f;
26809 /* Add the insn. */
26811 add_unwind_opcode (bytes
[n
- 1], 1);
26812 add_unwind_opcode (0xb2, 1);
26814 else if (offset
> 0x100)
26816 /* Two short opcodes. */
26817 add_unwind_opcode (0x3f, 1);
26818 op
= (offset
- 0x104) >> 2;
26819 add_unwind_opcode (op
, 1);
26821 else if (offset
> 0)
26823 /* Short opcode. */
26824 op
= (offset
- 4) >> 2;
26825 add_unwind_opcode (op
, 1);
26827 else if (offset
< 0)
26830 while (offset
> 0x100)
26832 add_unwind_opcode (0x7f, 1);
26835 op
= ((offset
- 4) >> 2) | 0x40;
26836 add_unwind_opcode (op
, 1);
26840 /* Finish the list of unwind opcodes for this function. */
26843 finish_unwind_opcodes (void)
26847 if (unwind
.fp_used
)
26849 /* Adjust sp as necessary. */
26850 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26851 flush_pending_unwind ();
26853 /* After restoring sp from the frame pointer. */
26854 op
= 0x90 | unwind
.fp_reg
;
26855 add_unwind_opcode (op
, 1);
26858 flush_pending_unwind ();
26862 /* Start an exception table entry. If idx is nonzero this is an index table
26866 start_unwind_section (const segT text_seg
, int idx
)
26868 const char * text_name
;
26869 const char * prefix
;
26870 const char * prefix_once
;
26871 const char * group_name
;
26879 prefix
= ELF_STRING_ARM_unwind
;
26880 prefix_once
= ELF_STRING_ARM_unwind_once
;
26881 type
= SHT_ARM_EXIDX
;
26885 prefix
= ELF_STRING_ARM_unwind_info
;
26886 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26887 type
= SHT_PROGBITS
;
26890 text_name
= segment_name (text_seg
);
26891 if (streq (text_name
, ".text"))
26894 if (strncmp (text_name
, ".gnu.linkonce.t.",
26895 strlen (".gnu.linkonce.t.")) == 0)
26897 prefix
= prefix_once
;
26898 text_name
+= strlen (".gnu.linkonce.t.");
26901 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26907 /* Handle COMDAT group. */
26908 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26910 group_name
= elf_group_name (text_seg
);
26911 if (group_name
== NULL
)
26913 as_bad (_("Group section `%s' has no group signature"),
26914 segment_name (text_seg
));
26915 ignore_rest_of_line ();
26918 flags
|= SHF_GROUP
;
26922 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26925 /* Set the section link for index tables. */
26927 elf_linked_to_section (now_seg
) = text_seg
;
26931 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26932 personality routine data. Returns zero, or the index table value for
26933 an inline entry. */
26936 create_unwind_entry (int have_data
)
26941 /* The current word of data. */
26943 /* The number of bytes left in this word. */
26946 finish_unwind_opcodes ();
26948 /* Remember the current text section. */
26949 unwind
.saved_seg
= now_seg
;
26950 unwind
.saved_subseg
= now_subseg
;
26952 start_unwind_section (now_seg
, 0);
26954 if (unwind
.personality_routine
== NULL
)
26956 if (unwind
.personality_index
== -2)
26959 as_bad (_("handlerdata in cantunwind frame"));
26960 return 1; /* EXIDX_CANTUNWIND. */
26963 /* Use a default personality routine if none is specified. */
26964 if (unwind
.personality_index
== -1)
26966 if (unwind
.opcode_count
> 3)
26967 unwind
.personality_index
= 1;
26969 unwind
.personality_index
= 0;
26972 /* Space for the personality routine entry. */
26973 if (unwind
.personality_index
== 0)
26975 if (unwind
.opcode_count
> 3)
26976 as_bad (_("too many unwind opcodes for personality routine 0"));
26980 /* All the data is inline in the index table. */
26983 while (unwind
.opcode_count
> 0)
26985 unwind
.opcode_count
--;
26986 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26990 /* Pad with "finish" opcodes. */
26992 data
= (data
<< 8) | 0xb0;
26999 /* We get two opcodes "free" in the first word. */
27000 size
= unwind
.opcode_count
- 2;
27004 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27005 if (unwind
.personality_index
!= -1)
27007 as_bad (_("attempt to recreate an unwind entry"));
27011 /* An extra byte is required for the opcode count. */
27012 size
= unwind
.opcode_count
+ 1;
27015 size
= (size
+ 3) >> 2;
27017 as_bad (_("too many unwind opcodes"));
27019 frag_align (2, 0, 0);
27020 record_alignment (now_seg
, 2);
27021 unwind
.table_entry
= expr_build_dot ();
27023 /* Allocate the table entry. */
27024 ptr
= frag_more ((size
<< 2) + 4);
27025 /* PR 13449: Zero the table entries in case some of them are not used. */
27026 memset (ptr
, 0, (size
<< 2) + 4);
27027 where
= frag_now_fix () - ((size
<< 2) + 4);
27029 switch (unwind
.personality_index
)
27032 /* ??? Should this be a PLT generating relocation? */
27033 /* Custom personality routine. */
27034 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27035 BFD_RELOC_ARM_PREL31
);
27040 /* Set the first byte to the number of additional words. */
27041 data
= size
> 0 ? size
- 1 : 0;
27045 /* ABI defined personality routines. */
27047 /* Three opcodes bytes are packed into the first word. */
27054 /* The size and first two opcode bytes go in the first word. */
27055 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27060 /* Should never happen. */
27064 /* Pack the opcodes into words (MSB first), reversing the list at the same
27066 while (unwind
.opcode_count
> 0)
27070 md_number_to_chars (ptr
, data
, 4);
27075 unwind
.opcode_count
--;
27077 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27080 /* Finish off the last word. */
27083 /* Pad with "finish" opcodes. */
27085 data
= (data
<< 8) | 0xb0;
27087 md_number_to_chars (ptr
, data
, 4);
27092 /* Add an empty descriptor if there is no user-specified data. */
27093 ptr
= frag_more (4);
27094 md_number_to_chars (ptr
, 0, 4);
27101 /* Initialize the DWARF-2 unwind information for this procedure. */
27104 tc_arm_frame_initial_instructions (void)
27106 cfi_add_CFA_def_cfa (REG_SP
, 0);
27108 #endif /* OBJ_ELF */
27110 /* Convert REGNAME to a DWARF-2 register number. */
27113 tc_arm_regname_to_dw2regnum (char *regname
)
27115 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27119 /* PR 16694: Allow VFP registers as well. */
27120 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27124 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27133 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27137 exp
.X_op
= O_secrel
;
27138 exp
.X_add_symbol
= symbol
;
27139 exp
.X_add_number
= 0;
27140 emit_expr (&exp
, size
);
27144 /* MD interface: Symbol and relocation handling. */
27146 /* Return the address within the segment that a PC-relative fixup is
27147 relative to. For ARM, PC-relative fixups applied to instructions
27148 are generally relative to the location of the fixup plus 8 bytes.
27149 Thumb branches are offset by 4, and Thumb loads relative to PC
27150 require special handling. */
27153 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27155 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27157 /* If this is pc-relative and we are going to emit a relocation
27158 then we just want to put out any pipeline compensation that the linker
27159 will need. Otherwise we want to use the calculated base.
27160 For WinCE we skip the bias for externals as well, since this
27161 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27163 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27164 || (arm_force_relocation (fixP
)
27166 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27172 switch (fixP
->fx_r_type
)
27174 /* PC relative addressing on the Thumb is slightly odd as the
27175 bottom two bits of the PC are forced to zero for the
27176 calculation. This happens *after* application of the
27177 pipeline offset. However, Thumb adrl already adjusts for
27178 this, so we need not do it again. */
27179 case BFD_RELOC_ARM_THUMB_ADD
:
27182 case BFD_RELOC_ARM_THUMB_OFFSET
:
27183 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27184 case BFD_RELOC_ARM_T32_ADD_PC12
:
27185 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27186 return (base
+ 4) & ~3;
27188 /* Thumb branches are simply offset by +4. */
27189 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27190 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27191 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27192 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27193 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27194 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27195 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27196 case BFD_RELOC_ARM_THUMB_BF17
:
27197 case BFD_RELOC_ARM_THUMB_BF19
:
27198 case BFD_RELOC_ARM_THUMB_BF13
:
27199 case BFD_RELOC_ARM_THUMB_LOOP12
:
27202 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27204 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27205 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27206 && ARM_IS_FUNC (fixP
->fx_addsy
)
27207 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27208 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27211 /* BLX is like branches above, but forces the low two bits of PC to
27213 case BFD_RELOC_THUMB_PCREL_BLX
:
27215 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27216 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27217 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27218 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27219 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27220 return (base
+ 4) & ~3;
27222 /* ARM mode branches are offset by +8. However, the Windows CE
27223 loader expects the relocation not to take this into account. */
27224 case BFD_RELOC_ARM_PCREL_BLX
:
27226 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27227 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27228 && ARM_IS_FUNC (fixP
->fx_addsy
)
27229 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27230 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27233 case BFD_RELOC_ARM_PCREL_CALL
:
27235 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27236 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27237 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27238 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27239 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27242 case BFD_RELOC_ARM_PCREL_BRANCH
:
27243 case BFD_RELOC_ARM_PCREL_JUMP
:
27244 case BFD_RELOC_ARM_PLT32
:
27246 /* When handling fixups immediately, because we have already
27247 discovered the value of a symbol, or the address of the frag involved
27248 we must account for the offset by +8, as the OS loader will never see the reloc.
27249 see fixup_segment() in write.c
27250 The S_IS_EXTERNAL test handles the case of global symbols.
27251 Those need the calculated base, not just the pipe compensation the linker will need. */
27253 && fixP
->fx_addsy
!= NULL
27254 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27255 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27263 /* ARM mode loads relative to PC are also offset by +8. Unlike
27264 branches, the Windows CE loader *does* expect the relocation
27265 to take this into account. */
27266 case BFD_RELOC_ARM_OFFSET_IMM
:
27267 case BFD_RELOC_ARM_OFFSET_IMM8
:
27268 case BFD_RELOC_ARM_HWLITERAL
:
27269 case BFD_RELOC_ARM_LITERAL
:
27270 case BFD_RELOC_ARM_CP_OFF_IMM
:
27274 /* Other PC-relative relocations are un-offset. */
27280 static bfd_boolean flag_warn_syms
= TRUE
;
27283 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27285 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27286 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27287 does mean that the resulting code might be very confusing to the reader.
27288 Also this warning can be triggered if the user omits an operand before
27289 an immediate address, eg:
27293 GAS treats this as an assignment of the value of the symbol foo to a
27294 symbol LDR, and so (without this code) it will not issue any kind of
27295 warning or error message.
27297 Note - ARM instructions are case-insensitive but the strings in the hash
27298 table are all stored in lower case, so we must first ensure that name is
27300 if (flag_warn_syms
&& arm_ops_hsh
)
27302 char * nbuf
= strdup (name
);
27305 for (p
= nbuf
; *p
; p
++)
27307 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27309 static struct hash_control
* already_warned
= NULL
;
27311 if (already_warned
== NULL
)
27312 already_warned
= hash_new ();
27313 /* Only warn about the symbol once. To keep the code
27314 simple we let hash_insert do the lookup for us. */
27315 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
27316 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
27325 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
27326 Otherwise we have no need to default values of symbols. */
27329 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
27332 if (name
[0] == '_' && name
[1] == 'G'
27333 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
27337 if (symbol_find (name
))
27338 as_bad (_("GOT already in the symbol table"));
27340 GOT_symbol
= symbol_new (name
, undefined_section
,
27341 (valueT
) 0, & zero_address_frag
);
27351 /* Subroutine of md_apply_fix. Check to see if an immediate can be
27352 computed as two separate immediate values, added together. We
27353 already know that this value cannot be computed by just one ARM
27356 static unsigned int
27357 validate_immediate_twopart (unsigned int val
,
27358 unsigned int * highpart
)
27363 for (i
= 0; i
< 32; i
+= 2)
27364 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
27370 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
27372 else if (a
& 0xff0000)
27374 if (a
& 0xff000000)
27376 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
27380 gas_assert (a
& 0xff000000);
27381 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
27384 return (a
& 0xff) | (i
<< 7);
27391 validate_offset_imm (unsigned int val
, int hwse
)
27393 if ((hwse
&& val
> 255) || val
> 4095)
27398 /* Subroutine of md_apply_fix. Do those data_ops which can take a
27399 negative immediate constant by altering the instruction. A bit of
27404 by inverting the second operand, and
27407 by negating the second operand. */
27410 negate_data_op (unsigned long * instruction
,
27411 unsigned long value
)
27414 unsigned long negated
, inverted
;
27416 negated
= encode_arm_immediate (-value
);
27417 inverted
= encode_arm_immediate (~value
);
27419 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
27422 /* First negates. */
27423 case OPCODE_SUB
: /* ADD <-> SUB */
27424 new_inst
= OPCODE_ADD
;
27429 new_inst
= OPCODE_SUB
;
27433 case OPCODE_CMP
: /* CMP <-> CMN */
27434 new_inst
= OPCODE_CMN
;
27439 new_inst
= OPCODE_CMP
;
27443 /* Now Inverted ops. */
27444 case OPCODE_MOV
: /* MOV <-> MVN */
27445 new_inst
= OPCODE_MVN
;
27450 new_inst
= OPCODE_MOV
;
27454 case OPCODE_AND
: /* AND <-> BIC */
27455 new_inst
= OPCODE_BIC
;
27460 new_inst
= OPCODE_AND
;
27464 case OPCODE_ADC
: /* ADC <-> SBC */
27465 new_inst
= OPCODE_SBC
;
27470 new_inst
= OPCODE_ADC
;
27474 /* We cannot do anything. */
27479 if (value
== (unsigned) FAIL
)
27482 *instruction
&= OPCODE_MASK
;
27483 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
27487 /* Like negate_data_op, but for Thumb-2. */
27489 static unsigned int
27490 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
27494 unsigned int negated
, inverted
;
27496 negated
= encode_thumb32_immediate (-value
);
27497 inverted
= encode_thumb32_immediate (~value
);
27499 rd
= (*instruction
>> 8) & 0xf;
27500 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
27503 /* ADD <-> SUB. Includes CMP <-> CMN. */
27504 case T2_OPCODE_SUB
:
27505 new_inst
= T2_OPCODE_ADD
;
27509 case T2_OPCODE_ADD
:
27510 new_inst
= T2_OPCODE_SUB
;
27514 /* ORR <-> ORN. Includes MOV <-> MVN. */
27515 case T2_OPCODE_ORR
:
27516 new_inst
= T2_OPCODE_ORN
;
27520 case T2_OPCODE_ORN
:
27521 new_inst
= T2_OPCODE_ORR
;
27525 /* AND <-> BIC. TST has no inverted equivalent. */
27526 case T2_OPCODE_AND
:
27527 new_inst
= T2_OPCODE_BIC
;
27534 case T2_OPCODE_BIC
:
27535 new_inst
= T2_OPCODE_AND
;
27540 case T2_OPCODE_ADC
:
27541 new_inst
= T2_OPCODE_SBC
;
27545 case T2_OPCODE_SBC
:
27546 new_inst
= T2_OPCODE_ADC
;
27550 /* We cannot do anything. */
27555 if (value
== (unsigned int)FAIL
)
27558 *instruction
&= T2_OPCODE_MASK
;
27559 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27563 /* Read a 32-bit thumb instruction from buf. */
27565 static unsigned long
27566 get_thumb32_insn (char * buf
)
27568 unsigned long insn
;
27569 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27570 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27575 /* We usually want to set the low bit on the address of thumb function
27576 symbols. In particular .word foo - . should have the low bit set.
27577 Generic code tries to fold the difference of two symbols to
27578 a constant. Prevent this and force a relocation when the first symbols
27579 is a thumb function. */
27582 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27584 if (op
== O_subtract
27585 && l
->X_op
== O_symbol
27586 && r
->X_op
== O_symbol
27587 && THUMB_IS_FUNC (l
->X_add_symbol
))
27589 l
->X_op
= O_subtract
;
27590 l
->X_op_symbol
= r
->X_add_symbol
;
27591 l
->X_add_number
-= r
->X_add_number
;
27595 /* Process as normal. */
27599 /* Encode Thumb2 unconditional branches and calls. The encoding
27600 for the 2 are identical for the immediate values. */
27603 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27605 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27608 addressT S
, I1
, I2
, lo
, hi
;
27610 S
= (value
>> 24) & 0x01;
27611 I1
= (value
>> 23) & 0x01;
27612 I2
= (value
>> 22) & 0x01;
27613 hi
= (value
>> 12) & 0x3ff;
27614 lo
= (value
>> 1) & 0x7ff;
27615 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27616 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27617 newval
|= (S
<< 10) | hi
;
27618 newval2
&= ~T2I1I2MASK
;
27619 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27620 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27621 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27625 md_apply_fix (fixS
* fixP
,
27629 offsetT value
= * valP
;
27631 unsigned int newimm
;
27632 unsigned long temp
;
27634 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27636 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27638 /* Note whether this will delete the relocation. */
27640 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27643 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27644 consistency with the behaviour on 32-bit hosts. Remember value
27646 value
&= 0xffffffff;
27647 value
^= 0x80000000;
27648 value
-= 0x80000000;
27651 fixP
->fx_addnumber
= value
;
27653 /* Same treatment for fixP->fx_offset. */
27654 fixP
->fx_offset
&= 0xffffffff;
27655 fixP
->fx_offset
^= 0x80000000;
27656 fixP
->fx_offset
-= 0x80000000;
27658 switch (fixP
->fx_r_type
)
27660 case BFD_RELOC_NONE
:
27661 /* This will need to go in the object file. */
27665 case BFD_RELOC_ARM_IMMEDIATE
:
27666 /* We claim that this fixup has been processed here,
27667 even if in fact we generate an error because we do
27668 not have a reloc for it, so tc_gen_reloc will reject it. */
27671 if (fixP
->fx_addsy
)
27673 const char *msg
= 0;
27675 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27676 msg
= _("undefined symbol %s used as an immediate value");
27677 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27678 msg
= _("symbol %s is in a different section");
27679 else if (S_IS_WEAK (fixP
->fx_addsy
))
27680 msg
= _("symbol %s is weak and may be overridden later");
27684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27685 msg
, S_GET_NAME (fixP
->fx_addsy
));
27690 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27692 /* If the offset is negative, we should use encoding A2 for ADR. */
27693 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27694 newimm
= negate_data_op (&temp
, value
);
27697 newimm
= encode_arm_immediate (value
);
27699 /* If the instruction will fail, see if we can fix things up by
27700 changing the opcode. */
27701 if (newimm
== (unsigned int) FAIL
)
27702 newimm
= negate_data_op (&temp
, value
);
27703 /* MOV accepts both ARM modified immediate (A1 encoding) and
27704 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27705 When disassembling, MOV is preferred when there is no encoding
27707 if (newimm
== (unsigned int) FAIL
27708 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27709 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27710 && !((temp
>> SBIT_SHIFT
) & 0x1)
27711 && value
>= 0 && value
<= 0xffff)
27713 /* Clear bits[23:20] to change encoding from A1 to A2. */
27714 temp
&= 0xff0fffff;
27715 /* Encoding high 4bits imm. Code below will encode the remaining
27717 temp
|= (value
& 0x0000f000) << 4;
27718 newimm
= value
& 0x00000fff;
27722 if (newimm
== (unsigned int) FAIL
)
27724 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27725 _("invalid constant (%lx) after fixup"),
27726 (unsigned long) value
);
27730 newimm
|= (temp
& 0xfffff000);
27731 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27734 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27736 unsigned int highpart
= 0;
27737 unsigned int newinsn
= 0xe1a00000; /* nop. */
27739 if (fixP
->fx_addsy
)
27741 const char *msg
= 0;
27743 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27744 msg
= _("undefined symbol %s used as an immediate value");
27745 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27746 msg
= _("symbol %s is in a different section");
27747 else if (S_IS_WEAK (fixP
->fx_addsy
))
27748 msg
= _("symbol %s is weak and may be overridden later");
27752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27753 msg
, S_GET_NAME (fixP
->fx_addsy
));
27758 newimm
= encode_arm_immediate (value
);
27759 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27761 /* If the instruction will fail, see if we can fix things up by
27762 changing the opcode. */
27763 if (newimm
== (unsigned int) FAIL
27764 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27766 /* No ? OK - try using two ADD instructions to generate
27768 newimm
= validate_immediate_twopart (value
, & highpart
);
27770 /* Yes - then make sure that the second instruction is
27772 if (newimm
!= (unsigned int) FAIL
)
27774 /* Still No ? Try using a negated value. */
27775 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27776 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27777 /* Otherwise - give up. */
27780 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27781 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27786 /* Replace the first operand in the 2nd instruction (which
27787 is the PC) with the destination register. We have
27788 already added in the PC in the first instruction and we
27789 do not want to do it again. */
27790 newinsn
&= ~ 0xf0000;
27791 newinsn
|= ((newinsn
& 0x0f000) << 4);
27794 newimm
|= (temp
& 0xfffff000);
27795 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27797 highpart
|= (newinsn
& 0xfffff000);
27798 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27802 case BFD_RELOC_ARM_OFFSET_IMM
:
27803 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27805 /* Fall through. */
27807 case BFD_RELOC_ARM_LITERAL
:
27813 if (validate_offset_imm (value
, 0) == FAIL
)
27815 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27817 _("invalid literal constant: pool needs to be closer"));
27819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27820 _("bad immediate value for offset (%ld)"),
27825 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27827 newval
&= 0xfffff000;
27830 newval
&= 0xff7ff000;
27831 newval
|= value
| (sign
? INDEX_UP
: 0);
27833 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27836 case BFD_RELOC_ARM_OFFSET_IMM8
:
27837 case BFD_RELOC_ARM_HWLITERAL
:
27843 if (validate_offset_imm (value
, 1) == FAIL
)
27845 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27846 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27847 _("invalid literal constant: pool needs to be closer"));
27849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27850 _("bad immediate value for 8-bit offset (%ld)"),
27855 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27857 newval
&= 0xfffff0f0;
27860 newval
&= 0xff7ff0f0;
27861 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27863 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27866 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27867 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27868 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27869 _("bad immediate value for offset (%ld)"), (long) value
);
27872 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27874 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27877 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27878 /* This is a complicated relocation used for all varieties of Thumb32
27879 load/store instruction with immediate offset:
27881 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27882 *4, optional writeback(W)
27883 (doubleword load/store)
27885 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27886 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27887 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27888 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27889 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27891 Uppercase letters indicate bits that are already encoded at
27892 this point. Lowercase letters are our problem. For the
27893 second block of instructions, the secondary opcode nybble
27894 (bits 8..11) is present, and bit 23 is zero, even if this is
27895 a PC-relative operation. */
27896 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27898 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27900 if ((newval
& 0xf0000000) == 0xe0000000)
27902 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27904 newval
|= (1 << 23);
27907 if (value
% 4 != 0)
27909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27910 _("offset not a multiple of 4"));
27916 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27917 _("offset out of range"));
27922 else if ((newval
& 0x000f0000) == 0x000f0000)
27924 /* PC-relative, 12-bit offset. */
27926 newval
|= (1 << 23);
27931 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27932 _("offset out of range"));
27937 else if ((newval
& 0x00000100) == 0x00000100)
27939 /* Writeback: 8-bit, +/- offset. */
27941 newval
|= (1 << 9);
27946 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27947 _("offset out of range"));
27952 else if ((newval
& 0x00000f00) == 0x00000e00)
27954 /* T-instruction: positive 8-bit offset. */
27955 if (value
< 0 || value
> 0xff)
27957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27958 _("offset out of range"));
27966 /* Positive 12-bit or negative 8-bit offset. */
27970 newval
|= (1 << 23);
27980 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27981 _("offset out of range"));
27988 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27989 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27992 case BFD_RELOC_ARM_SHIFT_IMM
:
27993 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27994 if (((unsigned long) value
) > 32
27996 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27999 _("shift expression is too large"));
28004 /* Shifts of zero must be done as lsl. */
28006 else if (value
== 32)
28008 newval
&= 0xfffff07f;
28009 newval
|= (value
& 0x1f) << 7;
28010 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28013 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28014 case BFD_RELOC_ARM_T32_ADD_IMM
:
28015 case BFD_RELOC_ARM_T32_IMM12
:
28016 case BFD_RELOC_ARM_T32_ADD_PC12
:
28017 /* We claim that this fixup has been processed here,
28018 even if in fact we generate an error because we do
28019 not have a reloc for it, so tc_gen_reloc will reject it. */
28023 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28026 _("undefined symbol %s used as an immediate value"),
28027 S_GET_NAME (fixP
->fx_addsy
));
28031 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28033 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28036 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28037 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28038 Thumb2 modified immediate encoding (T2). */
28039 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28040 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28042 newimm
= encode_thumb32_immediate (value
);
28043 if (newimm
== (unsigned int) FAIL
)
28044 newimm
= thumb32_negate_data_op (&newval
, value
);
28046 if (newimm
== (unsigned int) FAIL
)
28048 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28050 /* Turn add/sum into addw/subw. */
28051 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28052 newval
= (newval
& 0xfeffffff) | 0x02000000;
28053 /* No flat 12-bit imm encoding for addsw/subsw. */
28054 if ((newval
& 0x00100000) == 0)
28056 /* 12 bit immediate for addw/subw. */
28060 newval
^= 0x00a00000;
28063 newimm
= (unsigned int) FAIL
;
28070 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28071 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28072 disassembling, MOV is preferred when there is no encoding
28074 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28075 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28076 but with the Rn field [19:16] set to 1111. */
28077 && (((newval
>> 16) & 0xf) == 0xf)
28078 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28079 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28080 && value
>= 0 && value
<= 0xffff)
28082 /* Toggle bit[25] to change encoding from T2 to T3. */
28084 /* Clear bits[19:16]. */
28085 newval
&= 0xfff0ffff;
28086 /* Encoding high 4bits imm. Code below will encode the
28087 remaining low 12bits. */
28088 newval
|= (value
& 0x0000f000) << 4;
28089 newimm
= value
& 0x00000fff;
28094 if (newimm
== (unsigned int)FAIL
)
28096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28097 _("invalid constant (%lx) after fixup"),
28098 (unsigned long) value
);
28102 newval
|= (newimm
& 0x800) << 15;
28103 newval
|= (newimm
& 0x700) << 4;
28104 newval
|= (newimm
& 0x0ff);
28106 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28107 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28110 case BFD_RELOC_ARM_SMC
:
28111 if (((unsigned long) value
) > 0xf)
28112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28113 _("invalid smc expression"));
28115 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28116 newval
|= (value
& 0xf);
28117 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28120 case BFD_RELOC_ARM_HVC
:
28121 if (((unsigned long) value
) > 0xffff)
28122 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28123 _("invalid hvc expression"));
28124 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28125 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28126 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28129 case BFD_RELOC_ARM_SWI
:
28130 if (fixP
->tc_fix_data
!= 0)
28132 if (((unsigned long) value
) > 0xff)
28133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28134 _("invalid swi expression"));
28135 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28137 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28141 if (((unsigned long) value
) > 0x00ffffff)
28142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28143 _("invalid swi expression"));
28144 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28146 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28150 case BFD_RELOC_ARM_MULTI
:
28151 if (((unsigned long) value
) > 0xffff)
28152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28153 _("invalid expression in load/store multiple"));
28154 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28155 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28159 case BFD_RELOC_ARM_PCREL_CALL
:
28161 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28163 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28164 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28165 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28166 /* Flip the bl to blx. This is a simple flip
28167 bit here because we generate PCREL_CALL for
28168 unconditional bls. */
28170 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28171 newval
= newval
| 0x10000000;
28172 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28178 goto arm_branch_common
;
28180 case BFD_RELOC_ARM_PCREL_JUMP
:
28181 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28183 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28184 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28185 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28187 /* This would map to a bl<cond>, b<cond>,
28188 b<always> to a Thumb function. We
28189 need to force a relocation for this particular
28191 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28194 /* Fall through. */
28196 case BFD_RELOC_ARM_PLT32
:
28198 case BFD_RELOC_ARM_PCREL_BRANCH
:
28200 goto arm_branch_common
;
28202 case BFD_RELOC_ARM_PCREL_BLX
:
28205 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28207 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28208 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28209 && ARM_IS_FUNC (fixP
->fx_addsy
))
28211 /* Flip the blx to a bl and warn. */
28212 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28213 newval
= 0xeb000000;
28214 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28215 _("blx to '%s' an ARM ISA state function changed to bl"),
28217 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28223 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28224 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28228 /* We are going to store value (shifted right by two) in the
28229 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28230 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28233 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28234 _("misaligned branch destination"));
28235 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
28236 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
28237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28239 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28241 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28242 newval
|= (value
>> 2) & 0x00ffffff;
28243 /* Set the H bit on BLX instructions. */
28247 newval
|= 0x01000000;
28249 newval
&= ~0x01000000;
28251 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28255 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28256 /* CBZ can only branch forward. */
28258 /* Attempts to use CBZ to branch to the next instruction
28259 (which, strictly speaking, are prohibited) will be turned into
28262 FIXME: It may be better to remove the instruction completely and
28263 perform relaxation. */
28266 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28267 newval
= 0xbf00; /* NOP encoding T1 */
28268 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28275 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28277 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28278 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28279 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28284 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28285 if (out_of_range_p (value
, 8))
28286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28288 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28290 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28291 newval
|= (value
& 0x1ff) >> 1;
28292 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28296 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28297 if (out_of_range_p (value
, 11))
28298 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28300 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28302 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28303 newval
|= (value
& 0xfff) >> 1;
28304 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28308 /* This relocation is misnamed, it should be BRANCH21. */
28309 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28311 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28312 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28313 && ARM_IS_FUNC (fixP
->fx_addsy
)
28314 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28316 /* Force a relocation for a branch 20 bits wide. */
28319 if (out_of_range_p (value
, 20))
28320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28321 _("conditional branch out of range"));
28323 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28326 addressT S
, J1
, J2
, lo
, hi
;
28328 S
= (value
& 0x00100000) >> 20;
28329 J2
= (value
& 0x00080000) >> 19;
28330 J1
= (value
& 0x00040000) >> 18;
28331 hi
= (value
& 0x0003f000) >> 12;
28332 lo
= (value
& 0x00000ffe) >> 1;
28334 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28335 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28336 newval
|= (S
<< 10) | hi
;
28337 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
28338 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28339 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28343 case BFD_RELOC_THUMB_PCREL_BLX
:
28344 /* If there is a blx from a thumb state function to
28345 another thumb function flip this to a bl and warn
28349 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28350 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28351 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28353 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28354 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28355 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28357 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28358 newval
= newval
| 0x1000;
28359 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28360 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28365 goto thumb_bl_common
;
28367 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28368 /* A bl from Thumb state ISA to an internal ARM state function
28369 is converted to a blx. */
28371 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28372 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28373 && ARM_IS_FUNC (fixP
->fx_addsy
)
28374 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28376 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28377 newval
= newval
& ~0x1000;
28378 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28379 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
28385 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28386 /* For a BLX instruction, make sure that the relocation is rounded up
28387 to a word boundary. This follows the semantics of the instruction
28388 which specifies that bit 1 of the target address will come from bit
28389 1 of the base address. */
28390 value
= (value
+ 3) & ~ 3;
28393 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
28394 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28395 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28398 if (out_of_range_p (value
, 22))
28400 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
28401 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28402 else if (out_of_range_p (value
, 24))
28403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28404 _("Thumb2 branch out of range"));
28407 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28408 encode_thumb2_b_bl_offset (buf
, value
);
28412 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28413 if (out_of_range_p (value
, 24))
28414 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28416 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28417 encode_thumb2_b_bl_offset (buf
, value
);
28422 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28427 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28428 md_number_to_chars (buf
, value
, 2);
28432 case BFD_RELOC_ARM_TLS_CALL
:
28433 case BFD_RELOC_ARM_THM_TLS_CALL
:
28434 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28435 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28436 case BFD_RELOC_ARM_TLS_GOTDESC
:
28437 case BFD_RELOC_ARM_TLS_GD32
:
28438 case BFD_RELOC_ARM_TLS_LE32
:
28439 case BFD_RELOC_ARM_TLS_IE32
:
28440 case BFD_RELOC_ARM_TLS_LDM32
:
28441 case BFD_RELOC_ARM_TLS_LDO32
:
28442 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28445 /* Same handling as above, but with the arm_fdpic guard. */
28446 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28447 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28448 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28451 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28455 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28456 _("Relocation supported only in FDPIC mode"));
28460 case BFD_RELOC_ARM_GOT32
:
28461 case BFD_RELOC_ARM_GOTOFF
:
28464 case BFD_RELOC_ARM_GOT_PREL
:
28465 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28466 md_number_to_chars (buf
, value
, 4);
28469 case BFD_RELOC_ARM_TARGET2
:
28470 /* TARGET2 is not partial-inplace, so we need to write the
28471 addend here for REL targets, because it won't be written out
28472 during reloc processing later. */
28473 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28474 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
28477 /* Relocations for FDPIC. */
28478 case BFD_RELOC_ARM_GOTFUNCDESC
:
28479 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28480 case BFD_RELOC_ARM_FUNCDESC
:
28483 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28484 md_number_to_chars (buf
, 0, 4);
28488 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28489 _("Relocation supported only in FDPIC mode"));
28494 case BFD_RELOC_RVA
:
28496 case BFD_RELOC_ARM_TARGET1
:
28497 case BFD_RELOC_ARM_ROSEGREL32
:
28498 case BFD_RELOC_ARM_SBREL32
:
28499 case BFD_RELOC_32_PCREL
:
28501 case BFD_RELOC_32_SECREL
:
28503 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28505 /* For WinCE we only do this for pcrel fixups. */
28506 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28508 md_number_to_chars (buf
, value
, 4);
28512 case BFD_RELOC_ARM_PREL31
:
28513 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28515 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28516 if ((value
^ (value
>> 1)) & 0x40000000)
28518 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28519 _("rel31 relocation overflow"));
28521 newval
|= value
& 0x7fffffff;
28522 md_number_to_chars (buf
, newval
, 4);
28527 case BFD_RELOC_ARM_CP_OFF_IMM
:
28528 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28529 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28530 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28531 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28533 newval
= get_thumb32_insn (buf
);
28534 if ((newval
& 0x0f200f00) == 0x0d000900)
28536 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28537 has permitted values that are multiples of 2, in the range 0
28539 if (value
< -510 || value
> 510 || (value
& 1))
28540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28541 _("co-processor offset out of range"));
28543 else if ((newval
& 0xfe001f80) == 0xec000f80)
28545 if (value
< -511 || value
> 512 || (value
& 3))
28546 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28547 _("co-processor offset out of range"));
28549 else if (value
< -1023 || value
> 1023 || (value
& 3))
28550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28551 _("co-processor offset out of range"));
28556 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28557 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28558 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28560 newval
= get_thumb32_insn (buf
);
28563 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28564 newval
&= 0xffffff80;
28566 newval
&= 0xffffff00;
28570 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28571 newval
&= 0xff7fff80;
28573 newval
&= 0xff7fff00;
28574 if ((newval
& 0x0f200f00) == 0x0d000900)
28576 /* This is a fp16 vstr/vldr.
28578 It requires the immediate offset in the instruction is shifted
28579 left by 1 to be a half-word offset.
28581 Here, left shift by 1 first, and later right shift by 2
28582 should get the right offset. */
28585 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28587 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28588 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28589 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28591 put_thumb32_insn (buf
, newval
);
28594 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28595 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28596 if (value
< -255 || value
> 255)
28597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28598 _("co-processor offset out of range"));
28600 goto cp_off_common
;
28602 case BFD_RELOC_ARM_THUMB_OFFSET
:
28603 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28604 /* Exactly what ranges, and where the offset is inserted depends
28605 on the type of instruction, we can establish this from the
28607 switch (newval
>> 12)
28609 case 4: /* PC load. */
28610 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28611 forced to zero for these loads; md_pcrel_from has already
28612 compensated for this. */
28614 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28615 _("invalid offset, target not word aligned (0x%08lX)"),
28616 (((unsigned long) fixP
->fx_frag
->fr_address
28617 + (unsigned long) fixP
->fx_where
) & ~3)
28618 + (unsigned long) value
);
28620 if (value
& ~0x3fc)
28621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28622 _("invalid offset, value too big (0x%08lX)"),
28625 newval
|= value
>> 2;
28628 case 9: /* SP load/store. */
28629 if (value
& ~0x3fc)
28630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28631 _("invalid offset, value too big (0x%08lX)"),
28633 newval
|= value
>> 2;
28636 case 6: /* Word load/store. */
28638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28639 _("invalid offset, value too big (0x%08lX)"),
28641 newval
|= value
<< 4; /* 6 - 2. */
28644 case 7: /* Byte load/store. */
28646 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28647 _("invalid offset, value too big (0x%08lX)"),
28649 newval
|= value
<< 6;
28652 case 8: /* Halfword load/store. */
28654 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28655 _("invalid offset, value too big (0x%08lX)"),
28657 newval
|= value
<< 5; /* 6 - 1. */
28661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28662 "Unable to process relocation for thumb opcode: %lx",
28663 (unsigned long) newval
);
28666 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28669 case BFD_RELOC_ARM_THUMB_ADD
:
28670 /* This is a complicated relocation, since we use it for all of
28671 the following immediate relocations:
28675 9bit ADD/SUB SP word-aligned
28676 10bit ADD PC/SP word-aligned
28678 The type of instruction being processed is encoded in the
28685 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28687 int rd
= (newval
>> 4) & 0xf;
28688 int rs
= newval
& 0xf;
28689 int subtract
= !!(newval
& 0x8000);
28691 /* Check for HI regs, only very restricted cases allowed:
28692 Adjusting SP, and using PC or SP to get an address. */
28693 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28694 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28696 _("invalid Hi register with immediate"));
28698 /* If value is negative, choose the opposite instruction. */
28702 subtract
= !subtract
;
28704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28705 _("immediate value out of range"));
28710 if (value
& ~0x1fc)
28711 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28712 _("invalid immediate for stack address calculation"));
28713 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28714 newval
|= value
>> 2;
28716 else if (rs
== REG_PC
|| rs
== REG_SP
)
28718 /* PR gas/18541. If the addition is for a defined symbol
28719 within range of an ADR instruction then accept it. */
28722 && fixP
->fx_addsy
!= NULL
)
28726 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28727 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28728 || S_IS_WEAK (fixP
->fx_addsy
))
28730 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28731 _("address calculation needs a strongly defined nearby symbol"));
28735 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28737 /* Round up to the next 4-byte boundary. */
28742 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28746 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28747 _("symbol too far away"));
28757 if (subtract
|| value
& ~0x3fc)
28758 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28759 _("invalid immediate for address calculation (value = 0x%08lX)"),
28760 (unsigned long) (subtract
? - value
: value
));
28761 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28763 newval
|= value
>> 2;
28768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28769 _("immediate value out of range"));
28770 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28771 newval
|= (rd
<< 8) | value
;
28776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28777 _("immediate value out of range"));
28778 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28779 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28782 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28785 case BFD_RELOC_ARM_THUMB_IMM
:
28786 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28787 if (value
< 0 || value
> 255)
28788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28789 _("invalid immediate: %ld is out of range"),
28792 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28795 case BFD_RELOC_ARM_THUMB_SHIFT
:
28796 /* 5bit shift value (0..32). LSL cannot take 32. */
28797 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28798 temp
= newval
& 0xf800;
28799 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28801 _("invalid shift value: %ld"), (long) value
);
28802 /* Shifts of zero must be encoded as LSL. */
28804 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28805 /* Shifts of 32 are encoded as zero. */
28806 else if (value
== 32)
28808 newval
|= value
<< 6;
28809 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28812 case BFD_RELOC_VTABLE_INHERIT
:
28813 case BFD_RELOC_VTABLE_ENTRY
:
28817 case BFD_RELOC_ARM_MOVW
:
28818 case BFD_RELOC_ARM_MOVT
:
28819 case BFD_RELOC_ARM_THUMB_MOVW
:
28820 case BFD_RELOC_ARM_THUMB_MOVT
:
28821 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28823 /* REL format relocations are limited to a 16-bit addend. */
28824 if (!fixP
->fx_done
)
28826 if (value
< -0x8000 || value
> 0x7fff)
28827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28828 _("offset out of range"));
28830 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28831 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28836 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28837 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28839 newval
= get_thumb32_insn (buf
);
28840 newval
&= 0xfbf08f00;
28841 newval
|= (value
& 0xf000) << 4;
28842 newval
|= (value
& 0x0800) << 15;
28843 newval
|= (value
& 0x0700) << 4;
28844 newval
|= (value
& 0x00ff);
28845 put_thumb32_insn (buf
, newval
);
28849 newval
= md_chars_to_number (buf
, 4);
28850 newval
&= 0xfff0f000;
28851 newval
|= value
& 0x0fff;
28852 newval
|= (value
& 0xf000) << 4;
28853 md_number_to_chars (buf
, newval
, 4);
28858 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28859 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28860 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28861 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28862 gas_assert (!fixP
->fx_done
);
28865 bfd_boolean is_mov
;
28866 bfd_vma encoded_addend
= value
;
28868 /* Check that addend can be encoded in instruction. */
28869 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28870 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28871 _("the offset 0x%08lX is not representable"),
28872 (unsigned long) encoded_addend
);
28874 /* Extract the instruction. */
28875 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28876 is_mov
= (insn
& 0xf800) == 0x2000;
28881 if (!seg
->use_rela_p
)
28882 insn
|= encoded_addend
;
28888 /* Extract the instruction. */
28889 /* Encoding is the following
28894 /* The following conditions must be true :
28899 rd
= (insn
>> 4) & 0xf;
28901 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28903 _("Unable to process relocation for thumb opcode: %lx"),
28904 (unsigned long) insn
);
28906 /* Encode as ADD immediate8 thumb 1 code. */
28907 insn
= 0x3000 | (rd
<< 8);
28909 /* Place the encoded addend into the first 8 bits of the
28911 if (!seg
->use_rela_p
)
28912 insn
|= encoded_addend
;
28915 /* Update the instruction. */
28916 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28920 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28921 case BFD_RELOC_ARM_ALU_PC_G0
:
28922 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28923 case BFD_RELOC_ARM_ALU_PC_G1
:
28924 case BFD_RELOC_ARM_ALU_PC_G2
:
28925 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28926 case BFD_RELOC_ARM_ALU_SB_G0
:
28927 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28928 case BFD_RELOC_ARM_ALU_SB_G1
:
28929 case BFD_RELOC_ARM_ALU_SB_G2
:
28930 gas_assert (!fixP
->fx_done
);
28931 if (!seg
->use_rela_p
)
28934 bfd_vma encoded_addend
;
28935 bfd_vma addend_abs
= llabs (value
);
28937 /* Check that the absolute value of the addend can be
28938 expressed as an 8-bit constant plus a rotation. */
28939 encoded_addend
= encode_arm_immediate (addend_abs
);
28940 if (encoded_addend
== (unsigned int) FAIL
)
28941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28942 _("the offset 0x%08lX is not representable"),
28943 (unsigned long) addend_abs
);
28945 /* Extract the instruction. */
28946 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28948 /* If the addend is positive, use an ADD instruction.
28949 Otherwise use a SUB. Take care not to destroy the S bit. */
28950 insn
&= 0xff1fffff;
28956 /* Place the encoded addend into the first 12 bits of the
28958 insn
&= 0xfffff000;
28959 insn
|= encoded_addend
;
28961 /* Update the instruction. */
28962 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28966 case BFD_RELOC_ARM_LDR_PC_G0
:
28967 case BFD_RELOC_ARM_LDR_PC_G1
:
28968 case BFD_RELOC_ARM_LDR_PC_G2
:
28969 case BFD_RELOC_ARM_LDR_SB_G0
:
28970 case BFD_RELOC_ARM_LDR_SB_G1
:
28971 case BFD_RELOC_ARM_LDR_SB_G2
:
28972 gas_assert (!fixP
->fx_done
);
28973 if (!seg
->use_rela_p
)
28976 bfd_vma addend_abs
= llabs (value
);
28978 /* Check that the absolute value of the addend can be
28979 encoded in 12 bits. */
28980 if (addend_abs
>= 0x1000)
28981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28982 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28983 (unsigned long) addend_abs
);
28985 /* Extract the instruction. */
28986 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28988 /* If the addend is negative, clear bit 23 of the instruction.
28989 Otherwise set it. */
28991 insn
&= ~(1 << 23);
28995 /* Place the absolute value of the addend into the first 12 bits
28996 of the instruction. */
28997 insn
&= 0xfffff000;
28998 insn
|= addend_abs
;
29000 /* Update the instruction. */
29001 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29005 case BFD_RELOC_ARM_LDRS_PC_G0
:
29006 case BFD_RELOC_ARM_LDRS_PC_G1
:
29007 case BFD_RELOC_ARM_LDRS_PC_G2
:
29008 case BFD_RELOC_ARM_LDRS_SB_G0
:
29009 case BFD_RELOC_ARM_LDRS_SB_G1
:
29010 case BFD_RELOC_ARM_LDRS_SB_G2
:
29011 gas_assert (!fixP
->fx_done
);
29012 if (!seg
->use_rela_p
)
29015 bfd_vma addend_abs
= llabs (value
);
29017 /* Check that the absolute value of the addend can be
29018 encoded in 8 bits. */
29019 if (addend_abs
>= 0x100)
29020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29021 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29022 (unsigned long) addend_abs
);
29024 /* Extract the instruction. */
29025 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29027 /* If the addend is negative, clear bit 23 of the instruction.
29028 Otherwise set it. */
29030 insn
&= ~(1 << 23);
29034 /* Place the first four bits of the absolute value of the addend
29035 into the first 4 bits of the instruction, and the remaining
29036 four into bits 8 .. 11. */
29037 insn
&= 0xfffff0f0;
29038 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29040 /* Update the instruction. */
29041 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29045 case BFD_RELOC_ARM_LDC_PC_G0
:
29046 case BFD_RELOC_ARM_LDC_PC_G1
:
29047 case BFD_RELOC_ARM_LDC_PC_G2
:
29048 case BFD_RELOC_ARM_LDC_SB_G0
:
29049 case BFD_RELOC_ARM_LDC_SB_G1
:
29050 case BFD_RELOC_ARM_LDC_SB_G2
:
29051 gas_assert (!fixP
->fx_done
);
29052 if (!seg
->use_rela_p
)
29055 bfd_vma addend_abs
= llabs (value
);
29057 /* Check that the absolute value of the addend is a multiple of
29058 four and, when divided by four, fits in 8 bits. */
29059 if (addend_abs
& 0x3)
29060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29061 _("bad offset 0x%08lX (must be word-aligned)"),
29062 (unsigned long) addend_abs
);
29064 if ((addend_abs
>> 2) > 0xff)
29065 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29066 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29067 (unsigned long) addend_abs
);
29069 /* Extract the instruction. */
29070 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29072 /* If the addend is negative, clear bit 23 of the instruction.
29073 Otherwise set it. */
29075 insn
&= ~(1 << 23);
29079 /* Place the addend (divided by four) into the first eight
29080 bits of the instruction. */
29081 insn
&= 0xfffffff0;
29082 insn
|= addend_abs
>> 2;
29084 /* Update the instruction. */
29085 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29089 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29091 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29092 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29093 && ARM_IS_FUNC (fixP
->fx_addsy
)
29094 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29096 /* Force a relocation for a branch 5 bits wide. */
29099 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
29100 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29103 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29105 addressT boff
= value
>> 1;
29107 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29108 newval
|= (boff
<< 7);
29109 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29113 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29115 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29116 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29117 && ARM_IS_FUNC (fixP
->fx_addsy
)
29118 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29122 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
29123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29124 _("branch out of range"));
29126 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29128 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29130 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29131 addressT diff
= value
- boff
;
29135 newval
|= 1 << 1; /* T bit. */
29137 else if (diff
!= 2)
29139 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29140 _("out of range label-relative fixup value"));
29142 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29146 case BFD_RELOC_ARM_THUMB_BF17
:
29148 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29149 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29150 && ARM_IS_FUNC (fixP
->fx_addsy
)
29151 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29153 /* Force a relocation for a branch 17 bits wide. */
29157 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
29158 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29161 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29164 addressT immA
, immB
, immC
;
29166 immA
= (value
& 0x0001f000) >> 12;
29167 immB
= (value
& 0x00000ffc) >> 2;
29168 immC
= (value
& 0x00000002) >> 1;
29170 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29171 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29173 newval2
|= (immC
<< 11) | (immB
<< 1);
29174 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29175 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29179 case BFD_RELOC_ARM_THUMB_BF19
:
29181 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29182 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29183 && ARM_IS_FUNC (fixP
->fx_addsy
)
29184 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29186 /* Force a relocation for a branch 19 bits wide. */
29190 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29191 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29194 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29197 addressT immA
, immB
, immC
;
29199 immA
= (value
& 0x0007f000) >> 12;
29200 immB
= (value
& 0x00000ffc) >> 2;
29201 immC
= (value
& 0x00000002) >> 1;
29203 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29204 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29206 newval2
|= (immC
<< 11) | (immB
<< 1);
29207 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29208 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29212 case BFD_RELOC_ARM_THUMB_BF13
:
29214 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29215 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29216 && ARM_IS_FUNC (fixP
->fx_addsy
)
29217 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29219 /* Force a relocation for a branch 13 bits wide. */
29223 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29224 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29227 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29230 addressT immA
, immB
, immC
;
29232 immA
= (value
& 0x00001000) >> 12;
29233 immB
= (value
& 0x00000ffc) >> 2;
29234 immC
= (value
& 0x00000002) >> 1;
29236 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29237 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29239 newval2
|= (immC
<< 11) | (immB
<< 1);
29240 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29241 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29245 case BFD_RELOC_ARM_THUMB_LOOP12
:
29247 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29248 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29249 && ARM_IS_FUNC (fixP
->fx_addsy
)
29250 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29252 /* Force a relocation for a branch 12 bits wide. */
29256 bfd_vma insn
= get_thumb32_insn (buf
);
29257 /* le lr, <label>, le <label> or letp lr, <label> */
29258 if (((insn
& 0xffffffff) == 0xf00fc001)
29259 || ((insn
& 0xffffffff) == 0xf02fc001)
29260 || ((insn
& 0xffffffff) == 0xf01fc001))
29263 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29264 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29266 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29268 addressT imml
, immh
;
29270 immh
= (value
& 0x00000ffc) >> 2;
29271 imml
= (value
& 0x00000002) >> 1;
29273 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29274 newval
|= (imml
<< 11) | (immh
<< 1);
29275 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29279 case BFD_RELOC_ARM_V4BX
:
29280 /* This will need to go in the object file. */
29284 case BFD_RELOC_UNUSED
:
29286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29287 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29291 /* Translate internal representation of relocation info to BFD target
29295 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29298 bfd_reloc_code_real_type code
;
29300 reloc
= XNEW (arelent
);
29302 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29303 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29304 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29306 if (fixp
->fx_pcrel
)
29308 if (section
->use_rela_p
)
29309 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
29311 fixp
->fx_offset
= reloc
->address
;
29313 reloc
->addend
= fixp
->fx_offset
;
29315 switch (fixp
->fx_r_type
)
29318 if (fixp
->fx_pcrel
)
29320 code
= BFD_RELOC_8_PCREL
;
29323 /* Fall through. */
29326 if (fixp
->fx_pcrel
)
29328 code
= BFD_RELOC_16_PCREL
;
29331 /* Fall through. */
29334 if (fixp
->fx_pcrel
)
29336 code
= BFD_RELOC_32_PCREL
;
29339 /* Fall through. */
29341 case BFD_RELOC_ARM_MOVW
:
29342 if (fixp
->fx_pcrel
)
29344 code
= BFD_RELOC_ARM_MOVW_PCREL
;
29347 /* Fall through. */
29349 case BFD_RELOC_ARM_MOVT
:
29350 if (fixp
->fx_pcrel
)
29352 code
= BFD_RELOC_ARM_MOVT_PCREL
;
29355 /* Fall through. */
29357 case BFD_RELOC_ARM_THUMB_MOVW
:
29358 if (fixp
->fx_pcrel
)
29360 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
29363 /* Fall through. */
29365 case BFD_RELOC_ARM_THUMB_MOVT
:
29366 if (fixp
->fx_pcrel
)
29368 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
29371 /* Fall through. */
29373 case BFD_RELOC_NONE
:
29374 case BFD_RELOC_ARM_PCREL_BRANCH
:
29375 case BFD_RELOC_ARM_PCREL_BLX
:
29376 case BFD_RELOC_RVA
:
29377 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
29378 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
29379 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
29380 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29381 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29382 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29383 case BFD_RELOC_VTABLE_ENTRY
:
29384 case BFD_RELOC_VTABLE_INHERIT
:
29386 case BFD_RELOC_32_SECREL
:
29388 code
= fixp
->fx_r_type
;
29391 case BFD_RELOC_THUMB_PCREL_BLX
:
29393 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
29394 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29397 code
= BFD_RELOC_THUMB_PCREL_BLX
;
29400 case BFD_RELOC_ARM_LITERAL
:
29401 case BFD_RELOC_ARM_HWLITERAL
:
29402 /* If this is called then the a literal has
29403 been referenced across a section boundary. */
29404 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29405 _("literal referenced across section boundary"));
29409 case BFD_RELOC_ARM_TLS_CALL
:
29410 case BFD_RELOC_ARM_THM_TLS_CALL
:
29411 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29412 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29413 case BFD_RELOC_ARM_GOT32
:
29414 case BFD_RELOC_ARM_GOTOFF
:
29415 case BFD_RELOC_ARM_GOT_PREL
:
29416 case BFD_RELOC_ARM_PLT32
:
29417 case BFD_RELOC_ARM_TARGET1
:
29418 case BFD_RELOC_ARM_ROSEGREL32
:
29419 case BFD_RELOC_ARM_SBREL32
:
29420 case BFD_RELOC_ARM_PREL31
:
29421 case BFD_RELOC_ARM_TARGET2
:
29422 case BFD_RELOC_ARM_TLS_LDO32
:
29423 case BFD_RELOC_ARM_PCREL_CALL
:
29424 case BFD_RELOC_ARM_PCREL_JUMP
:
29425 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29426 case BFD_RELOC_ARM_ALU_PC_G0
:
29427 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29428 case BFD_RELOC_ARM_ALU_PC_G1
:
29429 case BFD_RELOC_ARM_ALU_PC_G2
:
29430 case BFD_RELOC_ARM_LDR_PC_G0
:
29431 case BFD_RELOC_ARM_LDR_PC_G1
:
29432 case BFD_RELOC_ARM_LDR_PC_G2
:
29433 case BFD_RELOC_ARM_LDRS_PC_G0
:
29434 case BFD_RELOC_ARM_LDRS_PC_G1
:
29435 case BFD_RELOC_ARM_LDRS_PC_G2
:
29436 case BFD_RELOC_ARM_LDC_PC_G0
:
29437 case BFD_RELOC_ARM_LDC_PC_G1
:
29438 case BFD_RELOC_ARM_LDC_PC_G2
:
29439 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29440 case BFD_RELOC_ARM_ALU_SB_G0
:
29441 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29442 case BFD_RELOC_ARM_ALU_SB_G1
:
29443 case BFD_RELOC_ARM_ALU_SB_G2
:
29444 case BFD_RELOC_ARM_LDR_SB_G0
:
29445 case BFD_RELOC_ARM_LDR_SB_G1
:
29446 case BFD_RELOC_ARM_LDR_SB_G2
:
29447 case BFD_RELOC_ARM_LDRS_SB_G0
:
29448 case BFD_RELOC_ARM_LDRS_SB_G1
:
29449 case BFD_RELOC_ARM_LDRS_SB_G2
:
29450 case BFD_RELOC_ARM_LDC_SB_G0
:
29451 case BFD_RELOC_ARM_LDC_SB_G1
:
29452 case BFD_RELOC_ARM_LDC_SB_G2
:
29453 case BFD_RELOC_ARM_V4BX
:
29454 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29455 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29456 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29457 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29458 case BFD_RELOC_ARM_GOTFUNCDESC
:
29459 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29460 case BFD_RELOC_ARM_FUNCDESC
:
29461 case BFD_RELOC_ARM_THUMB_BF17
:
29462 case BFD_RELOC_ARM_THUMB_BF19
:
29463 case BFD_RELOC_ARM_THUMB_BF13
:
29464 code
= fixp
->fx_r_type
;
29467 case BFD_RELOC_ARM_TLS_GOTDESC
:
29468 case BFD_RELOC_ARM_TLS_GD32
:
29469 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29470 case BFD_RELOC_ARM_TLS_LE32
:
29471 case BFD_RELOC_ARM_TLS_IE32
:
29472 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29473 case BFD_RELOC_ARM_TLS_LDM32
:
29474 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29475 /* BFD will include the symbol's address in the addend.
29476 But we don't want that, so subtract it out again here. */
29477 if (!S_IS_COMMON (fixp
->fx_addsy
))
29478 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
29479 code
= fixp
->fx_r_type
;
29483 case BFD_RELOC_ARM_IMMEDIATE
:
29484 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29485 _("internal relocation (type: IMMEDIATE) not fixed up"));
29488 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
29489 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29490 _("ADRL used for a symbol not defined in the same file"));
29493 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29494 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29495 case BFD_RELOC_ARM_THUMB_LOOP12
:
29496 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29497 _("%s used for a symbol not defined in the same file"),
29498 bfd_get_reloc_code_name (fixp
->fx_r_type
));
29501 case BFD_RELOC_ARM_OFFSET_IMM
:
29502 if (section
->use_rela_p
)
29504 code
= fixp
->fx_r_type
;
29508 if (fixp
->fx_addsy
!= NULL
29509 && !S_IS_DEFINED (fixp
->fx_addsy
)
29510 && S_IS_LOCAL (fixp
->fx_addsy
))
29512 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29513 _("undefined local label `%s'"),
29514 S_GET_NAME (fixp
->fx_addsy
));
29518 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29519 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29526 switch (fixp
->fx_r_type
)
29528 case BFD_RELOC_NONE
: type
= "NONE"; break;
29529 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29530 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29531 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29532 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29533 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29534 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29535 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29536 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29537 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29538 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29539 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29540 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29541 default: type
= _("<unknown>"); break;
29543 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29544 _("cannot represent %s relocation in this object file format"),
29551 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29553 && fixp
->fx_addsy
== GOT_symbol
)
29555 code
= BFD_RELOC_ARM_GOTPC
;
29556 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29560 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29562 if (reloc
->howto
== NULL
)
29564 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29565 _("cannot represent %s relocation in this object file format"),
29566 bfd_get_reloc_code_name (code
));
29570 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29571 vtable entry to be used in the relocation's section offset. */
29572 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29573 reloc
->address
= fixp
->fx_offset
;
29578 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29581 cons_fix_new_arm (fragS
* frag
,
29585 bfd_reloc_code_real_type reloc
)
29590 FIXME: @@ Should look at CPU word size. */
29594 reloc
= BFD_RELOC_8
;
29597 reloc
= BFD_RELOC_16
;
29601 reloc
= BFD_RELOC_32
;
29604 reloc
= BFD_RELOC_64
;
29609 if (exp
->X_op
== O_secrel
)
29611 exp
->X_op
= O_symbol
;
29612 reloc
= BFD_RELOC_32_SECREL
;
29616 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29619 #if defined (OBJ_COFF)
29621 arm_validate_fix (fixS
* fixP
)
29623 /* If the destination of the branch is a defined symbol which does not have
29624 the THUMB_FUNC attribute, then we must be calling a function which has
29625 the (interfacearm) attribute. We look for the Thumb entry point to that
29626 function and change the branch to refer to that function instead. */
29627 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29628 && fixP
->fx_addsy
!= NULL
29629 && S_IS_DEFINED (fixP
->fx_addsy
)
29630 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29632 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29639 arm_force_relocation (struct fix
* fixp
)
29641 #if defined (OBJ_COFF) && defined (TE_PE)
29642 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29646 /* In case we have a call or a branch to a function in ARM ISA mode from
29647 a thumb function or vice-versa force the relocation. These relocations
29648 are cleared off for some cores that might have blx and simple transformations
29652 switch (fixp
->fx_r_type
)
29654 case BFD_RELOC_ARM_PCREL_JUMP
:
29655 case BFD_RELOC_ARM_PCREL_CALL
:
29656 case BFD_RELOC_THUMB_PCREL_BLX
:
29657 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29661 case BFD_RELOC_ARM_PCREL_BLX
:
29662 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29663 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29664 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29665 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29674 /* Resolve these relocations even if the symbol is extern or weak.
29675 Technically this is probably wrong due to symbol preemption.
29676 In practice these relocations do not have enough range to be useful
29677 at dynamic link time, and some code (e.g. in the Linux kernel)
29678 expects these references to be resolved. */
29679 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29680 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29681 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29682 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29683 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29684 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29685 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29686 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29687 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29688 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29689 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29690 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29691 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29692 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29695 /* Always leave these relocations for the linker. */
29696 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29697 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29698 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29701 /* Always generate relocations against function symbols. */
29702 if (fixp
->fx_r_type
== BFD_RELOC_32
29704 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29707 return generic_force_reloc (fixp
);
29710 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29711 /* Relocations against function names must be left unadjusted,
29712 so that the linker can use this information to generate interworking
29713 stubs. The MIPS version of this function
29714 also prevents relocations that are mips-16 specific, but I do not
29715 know why it does this.
29718 There is one other problem that ought to be addressed here, but
29719 which currently is not: Taking the address of a label (rather
29720 than a function) and then later jumping to that address. Such
29721 addresses also ought to have their bottom bit set (assuming that
29722 they reside in Thumb code), but at the moment they will not. */
29725 arm_fix_adjustable (fixS
* fixP
)
29727 if (fixP
->fx_addsy
== NULL
)
29730 /* Preserve relocations against symbols with function type. */
29731 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29734 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29735 && fixP
->fx_subsy
== NULL
)
29738 /* We need the symbol name for the VTABLE entries. */
29739 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29740 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29743 /* Don't allow symbols to be discarded on GOT related relocs. */
29744 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29745 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29746 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29747 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29748 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29749 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29750 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29751 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29752 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29753 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29754 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29755 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29756 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29757 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29758 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29759 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29760 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29763 /* Similarly for group relocations. */
29764 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29765 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29766 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29769 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29770 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29771 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29772 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29773 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29774 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29775 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29776 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29777 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29780 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29781 offsets, so keep these symbols. */
29782 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29783 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29788 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29792 elf32_arm_target_format (void)
29795 return (target_big_endian
29796 ? "elf32-bigarm-symbian"
29797 : "elf32-littlearm-symbian");
29798 #elif defined (TE_VXWORKS)
29799 return (target_big_endian
29800 ? "elf32-bigarm-vxworks"
29801 : "elf32-littlearm-vxworks");
29802 #elif defined (TE_NACL)
29803 return (target_big_endian
29804 ? "elf32-bigarm-nacl"
29805 : "elf32-littlearm-nacl");
29809 if (target_big_endian
)
29810 return "elf32-bigarm-fdpic";
29812 return "elf32-littlearm-fdpic";
29816 if (target_big_endian
)
29817 return "elf32-bigarm";
29819 return "elf32-littlearm";
29825 armelf_frob_symbol (symbolS
* symp
,
29828 elf_frob_symbol (symp
, puntp
);
29832 /* MD interface: Finalization. */
29837 literal_pool
* pool
;
29839 /* Ensure that all the predication blocks are properly closed. */
29840 check_pred_blocks_finished ();
29842 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29844 /* Put it at the end of the relevant section. */
29845 subseg_set (pool
->section
, pool
->sub_section
);
29847 arm_elf_change_section ();
29854 /* Remove any excess mapping symbols generated for alignment frags in
29855 SEC. We may have created a mapping symbol before a zero byte
29856 alignment; remove it if there's a mapping symbol after the
29859 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29860 void *dummy ATTRIBUTE_UNUSED
)
29862 segment_info_type
*seginfo
= seg_info (sec
);
29865 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29868 for (fragp
= seginfo
->frchainP
->frch_root
;
29870 fragp
= fragp
->fr_next
)
29872 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29873 fragS
*next
= fragp
->fr_next
;
29875 /* Variable-sized frags have been converted to fixed size by
29876 this point. But if this was variable-sized to start with,
29877 there will be a fixed-size frag after it. So don't handle
29879 if (sym
== NULL
|| next
== NULL
)
29882 if (S_GET_VALUE (sym
) < next
->fr_address
)
29883 /* Not at the end of this frag. */
29885 know (S_GET_VALUE (sym
) == next
->fr_address
);
29889 if (next
->tc_frag_data
.first_map
!= NULL
)
29891 /* Next frag starts with a mapping symbol. Discard this
29893 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29897 if (next
->fr_next
== NULL
)
29899 /* This mapping symbol is at the end of the section. Discard
29901 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29902 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29906 /* As long as we have empty frags without any mapping symbols,
29908 /* If the next frag is non-empty and does not start with a
29909 mapping symbol, then this mapping symbol is required. */
29910 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29913 next
= next
->fr_next
;
29915 while (next
!= NULL
);
29920 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29924 arm_adjust_symtab (void)
29929 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29931 if (ARM_IS_THUMB (sym
))
29933 if (THUMB_IS_FUNC (sym
))
29935 /* Mark the symbol as a Thumb function. */
29936 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29937 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29938 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29940 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29941 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29943 as_bad (_("%s: unexpected function type: %d"),
29944 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29946 else switch (S_GET_STORAGE_CLASS (sym
))
29949 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29952 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29955 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29963 if (ARM_IS_INTERWORK (sym
))
29964 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29971 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29973 if (ARM_IS_THUMB (sym
))
29975 elf_symbol_type
* elf_sym
;
29977 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29978 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29980 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29981 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29983 /* If it's a .thumb_func, declare it as so,
29984 otherwise tag label as .code 16. */
29985 if (THUMB_IS_FUNC (sym
))
29986 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29987 ST_BRANCH_TO_THUMB
);
29988 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29989 elf_sym
->internal_elf_sym
.st_info
=
29990 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29995 /* Remove any overlapping mapping symbols generated by alignment frags. */
29996 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29997 /* Now do generic ELF adjustments. */
29998 elf_adjust_symtab ();
30002 /* MD interface: Initialization. */
30005 set_constant_flonums (void)
30009 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30010 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30014 /* Auto-select Thumb mode if it's the only available instruction set for the
30015 given architecture. */
30018 autoselect_thumb_from_cpu_variant (void)
30020 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30021 opcode_select (16);
30030 if ( (arm_ops_hsh
= hash_new ()) == NULL
30031 || (arm_cond_hsh
= hash_new ()) == NULL
30032 || (arm_vcond_hsh
= hash_new ()) == NULL
30033 || (arm_shift_hsh
= hash_new ()) == NULL
30034 || (arm_psr_hsh
= hash_new ()) == NULL
30035 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
30036 || (arm_reg_hsh
= hash_new ()) == NULL
30037 || (arm_reloc_hsh
= hash_new ()) == NULL
30038 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
30039 as_fatal (_("virtual memory exhausted"));
30041 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30042 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
30043 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30044 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
30045 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30046 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
30047 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30048 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
30049 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30050 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
30051 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30052 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30053 (void *) (v7m_psrs
+ i
));
30054 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30055 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
30057 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30059 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30060 (void *) (barrier_opt_names
+ i
));
30062 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30064 struct reloc_entry
* entry
= reloc_names
+ i
;
30066 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30067 /* This makes encode_branch() use the EABI versions of this relocation. */
30068 entry
->reloc
= BFD_RELOC_UNUSED
;
30070 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
30074 set_constant_flonums ();
30076 /* Set the cpu variant based on the command-line options. We prefer
30077 -mcpu= over -march= if both are set (as for GCC); and we prefer
30078 -mfpu= over any other way of setting the floating point unit.
30079 Use of legacy options with new options are faulted. */
30082 if (mcpu_cpu_opt
|| march_cpu_opt
)
30083 as_bad (_("use of old and new-style options to set CPU type"));
30085 selected_arch
= *legacy_cpu
;
30087 else if (mcpu_cpu_opt
)
30089 selected_arch
= *mcpu_cpu_opt
;
30090 selected_ext
= *mcpu_ext_opt
;
30092 else if (march_cpu_opt
)
30094 selected_arch
= *march_cpu_opt
;
30095 selected_ext
= *march_ext_opt
;
30097 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30102 as_bad (_("use of old and new-style options to set FPU type"));
30104 selected_fpu
= *legacy_fpu
;
30107 selected_fpu
= *mfpu_opt
;
30110 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30111 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30112 /* Some environments specify a default FPU. If they don't, infer it
30113 from the processor. */
30115 selected_fpu
= *mcpu_fpu_opt
;
30116 else if (march_fpu_opt
)
30117 selected_fpu
= *march_fpu_opt
;
30119 selected_fpu
= fpu_default
;
30123 if (ARM_FEATURE_ZERO (selected_fpu
))
30125 if (!no_cpu_selected ())
30126 selected_fpu
= fpu_default
;
30128 selected_fpu
= fpu_arch_fpa
;
30132 if (ARM_FEATURE_ZERO (selected_arch
))
30134 selected_arch
= cpu_default
;
30135 selected_cpu
= selected_arch
;
30137 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30139 /* Autodection of feature mode: allow all features in cpu_variant but leave
30140 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30141 after all instruction have been processed and we can decide what CPU
30142 should be selected. */
30143 if (ARM_FEATURE_ZERO (selected_arch
))
30144 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30146 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30149 autoselect_thumb_from_cpu_variant ();
30151 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30153 #if defined OBJ_COFF || defined OBJ_ELF
30155 unsigned int flags
= 0;
30157 #if defined OBJ_ELF
30158 flags
= meabi_flags
;
30160 switch (meabi_flags
)
30162 case EF_ARM_EABI_UNKNOWN
:
30164 /* Set the flags in the private structure. */
30165 if (uses_apcs_26
) flags
|= F_APCS26
;
30166 if (support_interwork
) flags
|= F_INTERWORK
;
30167 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30168 if (pic_code
) flags
|= F_PIC
;
30169 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30170 flags
|= F_SOFT_FLOAT
;
30172 switch (mfloat_abi_opt
)
30174 case ARM_FLOAT_ABI_SOFT
:
30175 case ARM_FLOAT_ABI_SOFTFP
:
30176 flags
|= F_SOFT_FLOAT
;
30179 case ARM_FLOAT_ABI_HARD
:
30180 if (flags
& F_SOFT_FLOAT
)
30181 as_bad (_("hard-float conflicts with specified fpu"));
30185 /* Using pure-endian doubles (even if soft-float). */
30186 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30187 flags
|= F_VFP_FLOAT
;
30189 #if defined OBJ_ELF
30190 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30191 flags
|= EF_ARM_MAVERICK_FLOAT
;
30194 case EF_ARM_EABI_VER4
:
30195 case EF_ARM_EABI_VER5
:
30196 /* No additional flags to set. */
30203 bfd_set_private_flags (stdoutput
, flags
);
30205 /* We have run out flags in the COFF header to encode the
30206 status of ATPCS support, so instead we create a dummy,
30207 empty, debug section called .arm.atpcs. */
30212 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30216 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30217 bfd_set_section_size (sec
, 0);
30218 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30224 /* Record the CPU type as well. */
30225 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30226 mach
= bfd_mach_arm_iWMMXt2
;
30227 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30228 mach
= bfd_mach_arm_iWMMXt
;
30229 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30230 mach
= bfd_mach_arm_XScale
;
30231 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30232 mach
= bfd_mach_arm_ep9312
;
30233 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30234 mach
= bfd_mach_arm_5TE
;
30235 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30237 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30238 mach
= bfd_mach_arm_5T
;
30240 mach
= bfd_mach_arm_5
;
30242 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30244 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30245 mach
= bfd_mach_arm_4T
;
30247 mach
= bfd_mach_arm_4
;
30249 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30250 mach
= bfd_mach_arm_3M
;
30251 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30252 mach
= bfd_mach_arm_3
;
30253 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30254 mach
= bfd_mach_arm_2a
;
30255 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30256 mach
= bfd_mach_arm_2
;
30258 mach
= bfd_mach_arm_unknown
;
30260 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30263 /* Command line processing. */
30266 Invocation line includes a switch not recognized by the base assembler.
30267 See if it's a processor-specific option.
30269 This routine is somewhat complicated by the need for backwards
30270 compatibility (since older releases of gcc can't be changed).
30271 The new options try to make the interface as compatible as
30274 New options (supported) are:
30276 -mcpu=<cpu name> Assemble for selected processor
30277 -march=<architecture name> Assemble for selected architecture
30278 -mfpu=<fpu architecture> Assemble for selected FPU.
30279 -EB/-mbig-endian Big-endian
30280 -EL/-mlittle-endian Little-endian
30281 -k Generate PIC code
30282 -mthumb Start in Thumb mode
30283 -mthumb-interwork Code supports ARM/Thumb interworking
30285 -m[no-]warn-deprecated Warn about deprecated features
30286 -m[no-]warn-syms Warn when symbols match instructions
30288 For now we will also provide support for:
30290 -mapcs-32 32-bit Program counter
30291 -mapcs-26 26-bit Program counter
30292 -macps-float Floats passed in FP registers
30293 -mapcs-reentrant Reentrant code
30295 (sometime these will probably be replaced with -mapcs=<list of options>
30296 and -matpcs=<list of options>)
30298 The remaining options are only supported for back-wards compatibility.
30299 Cpu variants, the arm part is optional:
30300 -m[arm]1 Currently not supported.
30301 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30302 -m[arm]3 Arm 3 processor
30303 -m[arm]6[xx], Arm 6 processors
30304 -m[arm]7[xx][t][[d]m] Arm 7 processors
30305 -m[arm]8[10] Arm 8 processors
30306 -m[arm]9[20][tdmi] Arm 9 processors
30307 -mstrongarm[110[0]] StrongARM processors
30308 -mxscale XScale processors
30309 -m[arm]v[2345[t[e]]] Arm architectures
30310 -mall All (except the ARM1)
30312 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30313 -mfpe-old (No float load/store multiples)
30314 -mvfpxd VFP Single precision
30316 -mno-fpu Disable all floating point instructions
30318 The following CPU names are recognized:
30319 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30320 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
30321 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
30322 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
30323 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
30324 arm10t arm10e, arm1020t, arm1020e, arm10200e,
30325 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
30329 const char * md_shortopts
= "m:k";
30331 #ifdef ARM_BI_ENDIAN
30332 #define OPTION_EB (OPTION_MD_BASE + 0)
30333 #define OPTION_EL (OPTION_MD_BASE + 1)
30335 #if TARGET_BYTES_BIG_ENDIAN
30336 #define OPTION_EB (OPTION_MD_BASE + 0)
30338 #define OPTION_EL (OPTION_MD_BASE + 1)
30341 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
30342 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
30344 struct option md_longopts
[] =
30347 {"EB", no_argument
, NULL
, OPTION_EB
},
30350 {"EL", no_argument
, NULL
, OPTION_EL
},
30352 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
30354 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
30356 {NULL
, no_argument
, NULL
, 0}
30359 size_t md_longopts_size
= sizeof (md_longopts
);
30361 struct arm_option_table
30363 const char * option
; /* Option name to match. */
30364 const char * help
; /* Help information. */
30365 int * var
; /* Variable to change. */
30366 int value
; /* What to change it to. */
30367 const char * deprecated
; /* If non-null, print this message. */
30370 struct arm_option_table arm_opts
[] =
30372 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
30373 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
30374 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30375 &support_interwork
, 1, NULL
},
30376 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
30377 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
30378 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
30380 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
30381 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
30382 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
30383 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
30386 /* These are recognized by the assembler, but have no affect on code. */
30387 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
30388 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
30390 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
30391 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30392 &warn_on_deprecated
, 0, NULL
},
30393 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
30394 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
30395 {NULL
, NULL
, NULL
, 0, NULL
}
30398 struct arm_legacy_option_table
30400 const char * option
; /* Option name to match. */
30401 const arm_feature_set
** var
; /* Variable to change. */
30402 const arm_feature_set value
; /* What to change it to. */
30403 const char * deprecated
; /* If non-null, print this message. */
30406 const struct arm_legacy_option_table arm_legacy_opts
[] =
30408 /* DON'T add any new processors to this list -- we want the whole list
30409 to go away... Add them to the processors table instead. */
30410 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30411 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30412 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30413 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30414 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30415 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30416 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30417 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30418 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30419 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30420 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30421 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30422 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30423 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30424 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30425 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30426 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30427 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30428 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30429 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30430 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30431 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30432 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30433 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30434 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30435 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30436 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30437 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30438 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30439 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30440 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30441 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30442 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30443 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30444 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30445 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30446 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30447 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30448 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30449 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30450 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30451 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30452 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30453 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30454 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30455 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30456 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30457 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30458 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30459 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30460 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30461 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30462 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30463 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30464 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30465 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30466 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30467 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30468 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30469 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30470 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30471 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30472 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30473 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30474 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30475 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30476 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30477 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30478 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
30479 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
30480 N_("use -mcpu=strongarm110")},
30481 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
30482 N_("use -mcpu=strongarm1100")},
30483 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
30484 N_("use -mcpu=strongarm1110")},
30485 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
30486 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
30487 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
30489 /* Architecture variants -- don't add any more to this list either. */
30490 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30491 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30492 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30493 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30494 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30495 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30496 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30497 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30498 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30499 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30500 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30501 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30502 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30503 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30504 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30505 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30506 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30507 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30509 /* Floating point variants -- don't add any more to this list either. */
30510 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30511 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30512 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30513 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30514 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30516 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30519 struct arm_cpu_option_table
30523 const arm_feature_set value
;
30524 const arm_feature_set ext
;
30525 /* For some CPUs we assume an FPU unless the user explicitly sets
30527 const arm_feature_set default_fpu
;
30528 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30530 const char * canonical_name
;
30533 /* This list should, at a minimum, contain all the cpu names
30534 recognized by GCC. */
30535 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30537 static const struct arm_cpu_option_table arm_cpus
[] =
30539 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30542 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30545 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30548 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30551 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30554 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30557 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30560 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30563 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30566 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30569 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30572 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30575 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30578 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30581 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30584 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30587 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30590 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30593 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30596 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30599 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30602 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30605 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30608 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30611 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30614 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30617 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30620 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30623 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30626 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30629 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30632 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30635 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30638 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30641 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30644 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30647 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30650 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30653 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30656 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30659 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30662 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30665 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30668 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30671 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30674 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30678 /* For V5 or later processors we default to using VFP; but the user
30679 should really set the FPU type explicitly. */
30680 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30683 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30686 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30689 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30692 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30695 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30698 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30701 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30704 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30707 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30710 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30713 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30716 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30719 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30722 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30725 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30728 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30731 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30734 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30737 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30740 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30743 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30746 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30749 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30752 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30755 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30758 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30761 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30764 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30767 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30770 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30773 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30776 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30779 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30782 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30785 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30788 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30789 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30791 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30793 FPU_ARCH_NEON_VFP_V4
),
30794 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30795 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30796 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30797 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30798 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30799 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30800 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30802 FPU_ARCH_NEON_VFP_V4
),
30803 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30805 FPU_ARCH_NEON_VFP_V4
),
30806 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30808 FPU_ARCH_NEON_VFP_V4
),
30809 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30810 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30811 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30812 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30813 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30814 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30815 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30816 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30817 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30818 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30819 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30820 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30821 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30822 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30823 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30824 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30825 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30826 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30827 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30828 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30829 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30830 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30831 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30832 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30833 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30834 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30835 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30836 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
30837 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30838 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30839 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
30840 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30841 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30842 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30843 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30844 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30845 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30848 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30850 FPU_ARCH_VFP_V3D16
),
30851 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30852 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30854 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30855 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30856 FPU_ARCH_VFP_V3D16
),
30857 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30858 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30859 FPU_ARCH_VFP_V3D16
),
30860 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30861 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30862 FPU_ARCH_NEON_VFP_ARMV8
),
30863 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
30864 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30866 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30867 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30869 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30872 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30875 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30878 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30881 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30884 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30887 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30890 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30891 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30892 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30893 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30894 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30895 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30896 /* ??? XSCALE is really an architecture. */
30897 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30901 /* ??? iwmmxt is not a processor. */
30902 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30905 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30908 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30913 ARM_CPU_OPT ("ep9312", "ARM920T",
30914 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30915 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30917 /* Marvell processors. */
30918 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30919 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30920 FPU_ARCH_VFP_V3D16
),
30921 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30922 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30923 FPU_ARCH_NEON_VFP_V4
),
30925 /* APM X-Gene family. */
30926 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30928 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30929 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30930 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30931 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30933 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30937 struct arm_ext_table
30941 const arm_feature_set merge
;
30942 const arm_feature_set clear
;
30945 struct arm_arch_option_table
30949 const arm_feature_set value
;
30950 const arm_feature_set default_fpu
;
30951 const struct arm_ext_table
* ext_table
;
30954 /* Used to add support for +E and +noE extension. */
30955 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30956 /* Used to add support for a +E extension. */
30957 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30958 /* Used to add support for a +noE extension. */
30959 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30961 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30962 ~0 & ~FPU_ENDIAN_PURE)
30964 static const struct arm_ext_table armv5te_ext_table
[] =
30966 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30967 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30970 static const struct arm_ext_table armv7_ext_table
[] =
30972 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30973 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30976 static const struct arm_ext_table armv7ve_ext_table
[] =
30978 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30979 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30980 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30981 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30982 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30983 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30984 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30986 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30987 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30989 /* Aliases for +simd. */
30990 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30992 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30993 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30994 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30996 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30999 static const struct arm_ext_table armv7a_ext_table
[] =
31001 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31002 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31003 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31004 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31005 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31006 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31007 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31009 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31010 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31012 /* Aliases for +simd. */
31013 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31014 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31016 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31017 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31019 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31020 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31021 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31024 static const struct arm_ext_table armv7r_ext_table
[] =
31026 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31027 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31028 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31029 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31030 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31031 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31032 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31033 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31034 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31037 static const struct arm_ext_table armv7em_ext_table
[] =
31039 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31040 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31041 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31042 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31043 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31044 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31045 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31048 static const struct arm_ext_table armv8a_ext_table
[] =
31050 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
31051 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31052 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31053 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31055 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31056 should use the +simd option to turn on FP. */
31057 ARM_REMOVE ("fp", ALL_FP
),
31058 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31059 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31060 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31064 static const struct arm_ext_table armv81a_ext_table
[] =
31066 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31067 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31068 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31070 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31071 should use the +simd option to turn on FP. */
31072 ARM_REMOVE ("fp", ALL_FP
),
31073 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31074 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31075 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31078 static const struct arm_ext_table armv82a_ext_table
[] =
31080 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31081 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31082 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31083 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31084 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31085 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31087 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31088 should use the +simd option to turn on FP. */
31089 ARM_REMOVE ("fp", ALL_FP
),
31090 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31091 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31092 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31095 static const struct arm_ext_table armv84a_ext_table
[] =
31097 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31098 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31099 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31100 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31102 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31103 should use the +simd option to turn on FP. */
31104 ARM_REMOVE ("fp", ALL_FP
),
31105 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31106 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31107 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31110 static const struct arm_ext_table armv85a_ext_table
[] =
31112 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31113 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31114 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31115 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31117 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31118 should use the +simd option to turn on FP. */
31119 ARM_REMOVE ("fp", ALL_FP
),
31120 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31123 static const struct arm_ext_table armv86a_ext_table
[] =
31125 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31128 static const struct arm_ext_table armv8m_main_ext_table
[] =
31130 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31131 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
31132 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31133 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31134 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31137 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31139 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31140 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
31142 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31143 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31146 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31147 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31148 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
31149 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
31151 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31152 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
31153 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31154 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31157 static const struct arm_ext_table armv8r_ext_table
[] =
31159 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
31160 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31161 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31162 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31163 ARM_REMOVE ("fp", ALL_FP
),
31164 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31165 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31168 /* This list should, at a minimum, contain all the architecture names
31169 recognized by GCC. */
31170 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31171 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31172 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31174 static const struct arm_arch_option_table arm_archs
[] =
31176 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31177 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31178 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31179 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31180 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31181 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31182 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31183 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31184 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31185 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31186 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31187 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31188 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31189 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31190 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31191 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31192 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31193 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31194 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31195 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31196 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31197 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31198 kept to preserve existing behaviour. */
31199 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31200 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31201 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31202 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31203 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31204 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31205 kept to preserve existing behaviour. */
31206 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31207 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31208 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31209 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31210 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31211 /* The official spelling of the ARMv7 profile variants is the dashed form.
31212 Accept the non-dashed form for compatibility with old toolchains. */
31213 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31214 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31215 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31216 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31217 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31218 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31219 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31220 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31221 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31222 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31224 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31226 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31227 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31228 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31229 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31230 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31231 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31232 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31233 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
31234 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31235 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31236 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31237 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31239 #undef ARM_ARCH_OPT
31241 /* ISA extensions in the co-processor and main instruction set space. */
31243 struct arm_option_extension_value_table
31247 const arm_feature_set merge_value
;
31248 const arm_feature_set clear_value
;
31249 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31250 indicates that an extension is available for all architectures while
31251 ARM_ANY marks an empty entry. */
31252 const arm_feature_set allowed_archs
[2];
31255 /* The following table must be in alphabetical order with a NULL last entry. */
31257 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31258 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31260 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31261 use the context sensitive approach using arm_ext_table's. */
31262 static const struct arm_option_extension_value_table arm_extensions
[] =
31264 ARM_EXT_OPT ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
31265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
31267 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
31268 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31269 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31270 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31271 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31272 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31273 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31275 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31276 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31277 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31278 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31279 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31280 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31283 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31284 | ARM_EXT2_FP16_FML
),
31285 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31286 | ARM_EXT2_FP16_FML
),
31288 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31289 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31290 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31291 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31292 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31293 Thumb divide instruction. Due to this having the same name as the
31294 previous entry, this will be ignored when doing command-line parsing and
31295 only considered by build attribute selection code. */
31296 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31297 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31298 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
31299 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
31300 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
31301 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
31302 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
31303 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
31304 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
31305 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31306 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31307 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31308 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31309 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31310 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31311 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
31312 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
31313 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
31314 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31315 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31316 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31318 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
31319 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
31320 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31321 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
31322 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
31323 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31324 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31325 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31327 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31328 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31329 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
31330 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31331 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
31332 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
31333 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31334 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
31336 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
31337 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31338 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
31339 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
31340 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
31344 /* ISA floating-point and Advanced SIMD extensions. */
31345 struct arm_option_fpu_value_table
31348 const arm_feature_set value
;
31351 /* This list should, at a minimum, contain all the fpu names
31352 recognized by GCC. */
31353 static const struct arm_option_fpu_value_table arm_fpus
[] =
31355 {"softfpa", FPU_NONE
},
31356 {"fpe", FPU_ARCH_FPE
},
31357 {"fpe2", FPU_ARCH_FPE
},
31358 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
31359 {"fpa", FPU_ARCH_FPA
},
31360 {"fpa10", FPU_ARCH_FPA
},
31361 {"fpa11", FPU_ARCH_FPA
},
31362 {"arm7500fe", FPU_ARCH_FPA
},
31363 {"softvfp", FPU_ARCH_VFP
},
31364 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
31365 {"vfp", FPU_ARCH_VFP_V2
},
31366 {"vfp9", FPU_ARCH_VFP_V2
},
31367 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
31368 {"vfp10", FPU_ARCH_VFP_V2
},
31369 {"vfp10-r0", FPU_ARCH_VFP_V1
},
31370 {"vfpxd", FPU_ARCH_VFP_V1xD
},
31371 {"vfpv2", FPU_ARCH_VFP_V2
},
31372 {"vfpv3", FPU_ARCH_VFP_V3
},
31373 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
31374 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
31375 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
31376 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
31377 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
31378 {"arm1020t", FPU_ARCH_VFP_V1
},
31379 {"arm1020e", FPU_ARCH_VFP_V2
},
31380 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
31381 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
31382 {"maverick", FPU_ARCH_MAVERICK
},
31383 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31384 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31385 {"neon-fp16", FPU_ARCH_NEON_FP16
},
31386 {"vfpv4", FPU_ARCH_VFP_V4
},
31387 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
31388 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
31389 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
31390 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
31391 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
31392 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
31393 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
31394 {"crypto-neon-fp-armv8",
31395 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
31396 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
31397 {"crypto-neon-fp-armv8.1",
31398 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
31399 {NULL
, ARM_ARCH_NONE
}
31402 struct arm_option_value_table
31408 static const struct arm_option_value_table arm_float_abis
[] =
31410 {"hard", ARM_FLOAT_ABI_HARD
},
31411 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
31412 {"soft", ARM_FLOAT_ABI_SOFT
},
31417 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
31418 static const struct arm_option_value_table arm_eabis
[] =
31420 {"gnu", EF_ARM_EABI_UNKNOWN
},
31421 {"4", EF_ARM_EABI_VER4
},
31422 {"5", EF_ARM_EABI_VER5
},
31427 struct arm_long_option_table
31429 const char * option
; /* Substring to match. */
31430 const char * help
; /* Help information. */
31431 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
31432 const char * deprecated
; /* If non-null, print this message. */
31436 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
31437 arm_feature_set
*ext_set
,
31438 const struct arm_ext_table
*ext_table
)
31440 /* We insist on extensions being specified in alphabetical order, and with
31441 extensions being added before being removed. We achieve this by having
31442 the global ARM_EXTENSIONS table in alphabetical order, and using the
31443 ADDING_VALUE variable to indicate whether we are adding an extension (1)
31444 or removing it (0) and only allowing it to change in the order
31446 const struct arm_option_extension_value_table
* opt
= NULL
;
31447 const arm_feature_set arm_any
= ARM_ANY
;
31448 int adding_value
= -1;
31450 while (str
!= NULL
&& *str
!= 0)
31457 as_bad (_("invalid architectural extension"));
31462 ext
= strchr (str
, '+');
31467 len
= strlen (str
);
31469 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
31471 if (adding_value
!= 0)
31474 opt
= arm_extensions
;
31482 if (adding_value
== -1)
31485 opt
= arm_extensions
;
31487 else if (adding_value
!= 1)
31489 as_bad (_("must specify extensions to add before specifying "
31490 "those to remove"));
31497 as_bad (_("missing architectural extension"));
31501 gas_assert (adding_value
!= -1);
31502 gas_assert (opt
!= NULL
);
31504 if (ext_table
!= NULL
)
31506 const struct arm_ext_table
* ext_opt
= ext_table
;
31507 bfd_boolean found
= FALSE
;
31508 for (; ext_opt
->name
!= NULL
; ext_opt
++)
31509 if (ext_opt
->name_len
== len
31510 && strncmp (ext_opt
->name
, str
, len
) == 0)
31514 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
31515 /* TODO: Option not supported. When we remove the
31516 legacy table this case should error out. */
31519 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
31523 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
31524 /* TODO: Option not supported. When we remove the
31525 legacy table this case should error out. */
31527 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31539 /* Scan over the options table trying to find an exact match. */
31540 for (; opt
->name
!= NULL
; opt
++)
31541 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31543 int i
, nb_allowed_archs
=
31544 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31545 /* Check we can apply the extension to this architecture. */
31546 for (i
= 0; i
< nb_allowed_archs
; i
++)
31549 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31551 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31554 if (i
== nb_allowed_archs
)
31556 as_bad (_("extension does not apply to the base architecture"));
31560 /* Add or remove the extension. */
31562 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31564 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31566 /* Allowing Thumb division instructions for ARMv7 in autodetection
31567 rely on this break so that duplicate extensions (extensions
31568 with the same name as a previous extension in the list) are not
31569 considered for command-line parsing. */
31573 if (opt
->name
== NULL
)
31575 /* Did we fail to find an extension because it wasn't specified in
31576 alphabetical order, or because it does not exist? */
31578 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31579 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31582 if (opt
->name
== NULL
)
31583 as_bad (_("unknown architectural extension `%s'"), str
);
31585 as_bad (_("architectural extensions must be specified in "
31586 "alphabetical order"));
31592 /* We should skip the extension we've just matched the next time
31604 arm_parse_fp16_opt (const char *str
)
31606 if (strcasecmp (str
, "ieee") == 0)
31607 fp16_format
= ARM_FP16_FORMAT_IEEE
;
31608 else if (strcasecmp (str
, "alternative") == 0)
31609 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
31612 as_bad (_("unrecognised float16 format \"%s\""), str
);
31620 arm_parse_cpu (const char *str
)
31622 const struct arm_cpu_option_table
*opt
;
31623 const char *ext
= strchr (str
, '+');
31629 len
= strlen (str
);
31633 as_bad (_("missing cpu name `%s'"), str
);
31637 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31638 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31640 mcpu_cpu_opt
= &opt
->value
;
31641 if (mcpu_ext_opt
== NULL
)
31642 mcpu_ext_opt
= XNEW (arm_feature_set
);
31643 *mcpu_ext_opt
= opt
->ext
;
31644 mcpu_fpu_opt
= &opt
->default_fpu
;
31645 if (opt
->canonical_name
)
31647 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31648 strcpy (selected_cpu_name
, opt
->canonical_name
);
31654 if (len
>= sizeof selected_cpu_name
)
31655 len
= (sizeof selected_cpu_name
) - 1;
31657 for (i
= 0; i
< len
; i
++)
31658 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31659 selected_cpu_name
[i
] = 0;
31663 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31668 as_bad (_("unknown cpu `%s'"), str
);
31673 arm_parse_arch (const char *str
)
31675 const struct arm_arch_option_table
*opt
;
31676 const char *ext
= strchr (str
, '+');
31682 len
= strlen (str
);
31686 as_bad (_("missing architecture name `%s'"), str
);
31690 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31691 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31693 march_cpu_opt
= &opt
->value
;
31694 if (march_ext_opt
== NULL
)
31695 march_ext_opt
= XNEW (arm_feature_set
);
31696 *march_ext_opt
= arm_arch_none
;
31697 march_fpu_opt
= &opt
->default_fpu
;
31698 selected_ctx_ext_table
= opt
->ext_table
;
31699 strcpy (selected_cpu_name
, opt
->name
);
31702 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31708 as_bad (_("unknown architecture `%s'\n"), str
);
31713 arm_parse_fpu (const char * str
)
31715 const struct arm_option_fpu_value_table
* opt
;
31717 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31718 if (streq (opt
->name
, str
))
31720 mfpu_opt
= &opt
->value
;
31724 as_bad (_("unknown floating point format `%s'\n"), str
);
31729 arm_parse_float_abi (const char * str
)
31731 const struct arm_option_value_table
* opt
;
31733 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31734 if (streq (opt
->name
, str
))
31736 mfloat_abi_opt
= opt
->value
;
31740 as_bad (_("unknown floating point abi `%s'\n"), str
);
31746 arm_parse_eabi (const char * str
)
31748 const struct arm_option_value_table
*opt
;
31750 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31751 if (streq (opt
->name
, str
))
31753 meabi_flags
= opt
->value
;
31756 as_bad (_("unknown EABI `%s'\n"), str
);
31762 arm_parse_it_mode (const char * str
)
31764 bfd_boolean ret
= TRUE
;
31766 if (streq ("arm", str
))
31767 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31768 else if (streq ("thumb", str
))
31769 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31770 else if (streq ("always", str
))
31771 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31772 else if (streq ("never", str
))
31773 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31776 as_bad (_("unknown implicit IT mode `%s', should be "\
31777 "arm, thumb, always, or never."), str
);
31785 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31787 codecomposer_syntax
= TRUE
;
31788 arm_comment_chars
[0] = ';';
31789 arm_line_separator_chars
[0] = 0;
31793 struct arm_long_option_table arm_long_opts
[] =
31795 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31796 arm_parse_cpu
, NULL
},
31797 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31798 arm_parse_arch
, NULL
},
31799 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31800 arm_parse_fpu
, NULL
},
31801 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31802 arm_parse_float_abi
, NULL
},
31804 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31805 arm_parse_eabi
, NULL
},
31807 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31808 arm_parse_it_mode
, NULL
},
31809 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31810 arm_ccs_mode
, NULL
},
31812 N_("[ieee|alternative]\n\
31813 set the encoding for half precision floating point "
31814 "numbers to IEEE\n\
31815 or Arm alternative format."),
31816 arm_parse_fp16_opt
, NULL
},
31817 {NULL
, NULL
, 0, NULL
}
31821 md_parse_option (int c
, const char * arg
)
31823 struct arm_option_table
*opt
;
31824 const struct arm_legacy_option_table
*fopt
;
31825 struct arm_long_option_table
*lopt
;
31831 target_big_endian
= 1;
31837 target_big_endian
= 0;
31841 case OPTION_FIX_V4BX
:
31849 #endif /* OBJ_ELF */
31852 /* Listing option. Just ignore these, we don't support additional
31857 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31859 if (c
== opt
->option
[0]
31860 && ((arg
== NULL
&& opt
->option
[1] == 0)
31861 || streq (arg
, opt
->option
+ 1)))
31863 /* If the option is deprecated, tell the user. */
31864 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31865 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31866 arg
? arg
: "", _(opt
->deprecated
));
31868 if (opt
->var
!= NULL
)
31869 *opt
->var
= opt
->value
;
31875 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31877 if (c
== fopt
->option
[0]
31878 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31879 || streq (arg
, fopt
->option
+ 1)))
31881 /* If the option is deprecated, tell the user. */
31882 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31883 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31884 arg
? arg
: "", _(fopt
->deprecated
));
31886 if (fopt
->var
!= NULL
)
31887 *fopt
->var
= &fopt
->value
;
31893 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31895 /* These options are expected to have an argument. */
31896 if (c
== lopt
->option
[0]
31898 && strncmp (arg
, lopt
->option
+ 1,
31899 strlen (lopt
->option
+ 1)) == 0)
31901 /* If the option is deprecated, tell the user. */
31902 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31903 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31904 _(lopt
->deprecated
));
31906 /* Call the sup-option parser. */
31907 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31918 md_show_usage (FILE * fp
)
31920 struct arm_option_table
*opt
;
31921 struct arm_long_option_table
*lopt
;
31923 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31925 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31926 if (opt
->help
!= NULL
)
31927 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31929 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31930 if (lopt
->help
!= NULL
)
31931 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31935 -EB assemble code for a big-endian cpu\n"));
31940 -EL assemble code for a little-endian cpu\n"));
31944 --fix-v4bx Allow BX in ARMv4 code\n"));
31948 --fdpic generate an FDPIC object file\n"));
31949 #endif /* OBJ_ELF */
31957 arm_feature_set flags
;
31958 } cpu_arch_ver_table
;
31960 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31961 chronologically for architectures, with an exception for ARMv6-M and
31962 ARMv6S-M due to legacy reasons. No new architecture should have a
31963 special case. This allows for build attribute selection results to be
31964 stable when new architectures are added. */
31965 static const cpu_arch_ver_table cpu_arch_ver
[] =
31967 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31968 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31969 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31970 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31971 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31972 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31973 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31974 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31975 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31976 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31977 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31978 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31979 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31980 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31981 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31982 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31983 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31984 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31985 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31986 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31987 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31988 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31989 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31990 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31992 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31993 always selected build attributes to match those of ARMv6-M
31994 (resp. ARMv6S-M). However, due to these architectures being a strict
31995 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31996 would be selected when fully respecting chronology of architectures.
31997 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31998 move them before ARMv7 architectures. */
31999 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32000 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32002 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32003 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32004 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32005 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32006 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32007 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32008 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32009 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32010 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32011 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32012 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32013 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32014 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32015 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32016 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32017 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32018 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32019 {-1, ARM_ARCH_NONE
}
32022 /* Set an attribute if it has not already been set by the user. */
32025 aeabi_set_attribute_int (int tag
, int value
)
32028 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32029 || !attributes_set_explicitly
[tag
])
32030 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32034 aeabi_set_attribute_string (int tag
, const char *value
)
32037 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32038 || !attributes_set_explicitly
[tag
])
32039 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32042 /* Return whether features in the *NEEDED feature set are available via
32043 extensions for the architecture whose feature set is *ARCH_FSET. */
32046 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32047 const arm_feature_set
*needed
)
32049 int i
, nb_allowed_archs
;
32050 arm_feature_set ext_fset
;
32051 const struct arm_option_extension_value_table
*opt
;
32053 ext_fset
= arm_arch_none
;
32054 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32056 /* Extension does not provide any feature we need. */
32057 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32061 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32062 for (i
= 0; i
< nb_allowed_archs
; i
++)
32065 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32068 /* Extension is available, add it. */
32069 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32070 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32074 /* Can we enable all features in *needed? */
32075 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32078 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32079 a given architecture feature set *ARCH_EXT_FSET including extension feature
32080 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32081 - if true, check for an exact match of the architecture modulo extensions;
32082 - otherwise, select build attribute value of the first superset
32083 architecture released so that results remains stable when new architectures
32085 For -march/-mcpu=all the build attribute value of the most featureful
32086 architecture is returned. Tag_CPU_arch_profile result is returned in
32090 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32091 const arm_feature_set
*ext_fset
,
32092 char *profile
, int exact_match
)
32094 arm_feature_set arch_fset
;
32095 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32097 /* Select most featureful architecture with all its extensions if building
32098 for -march=all as the feature sets used to set build attributes. */
32099 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32101 /* Force revisiting of decision for each new architecture. */
32102 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32104 return TAG_CPU_ARCH_V8
;
32107 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32109 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32111 arm_feature_set known_arch_fset
;
32113 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32116 /* Base architecture match user-specified architecture and
32117 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32118 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32123 /* Base architecture match user-specified architecture only
32124 (eg. ARMv6-M in the same case as above). Record it in case we
32125 find a match with above condition. */
32126 else if (p_ver_ret
== NULL
32127 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32133 /* Architecture has all features wanted. */
32134 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32136 arm_feature_set added_fset
;
32138 /* Compute features added by this architecture over the one
32139 recorded in p_ver_ret. */
32140 if (p_ver_ret
!= NULL
)
32141 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32143 /* First architecture that match incl. with extensions, or the
32144 only difference in features over the recorded match is
32145 features that were optional and are now mandatory. */
32146 if (p_ver_ret
== NULL
32147 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32153 else if (p_ver_ret
== NULL
)
32155 arm_feature_set needed_ext_fset
;
32157 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32159 /* Architecture has all features needed when using some
32160 extensions. Record it and continue searching in case there
32161 exist an architecture providing all needed features without
32162 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32164 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32171 if (p_ver_ret
== NULL
)
32175 /* Tag_CPU_arch_profile. */
32176 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32177 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32178 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32179 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
32181 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
32183 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32187 return p_ver_ret
->val
;
32190 /* Set the public EABI object attributes. */
32193 aeabi_set_public_attributes (void)
32195 char profile
= '\0';
32198 int fp16_optional
= 0;
32199 int skip_exact_match
= 0;
32200 arm_feature_set flags
, flags_arch
, flags_ext
;
32202 /* Autodetection mode, choose the architecture based the instructions
32204 if (no_cpu_selected ())
32206 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32208 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32209 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32211 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32212 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32214 /* Code run during relaxation relies on selected_cpu being set. */
32215 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32216 flags_ext
= arm_arch_none
;
32217 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32218 selected_ext
= flags_ext
;
32219 selected_cpu
= flags
;
32221 /* Otherwise, choose the architecture based on the capabilities of the
32225 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32226 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32227 flags_ext
= selected_ext
;
32228 flags
= selected_cpu
;
32230 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32232 /* Allow the user to override the reported architecture. */
32233 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32235 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32236 flags_ext
= arm_arch_none
;
32239 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32241 /* When this function is run again after relaxation has happened there is no
32242 way to determine whether an architecture or CPU was specified by the user:
32243 - selected_cpu is set above for relaxation to work;
32244 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32245 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32246 Therefore, if not in -march=all case we first try an exact match and fall
32247 back to autodetection. */
32248 if (!skip_exact_match
)
32249 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32251 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32253 as_bad (_("no architecture contains all the instructions used\n"));
32255 /* Tag_CPU_name. */
32256 if (selected_cpu_name
[0])
32260 q
= selected_cpu_name
;
32261 if (strncmp (q
, "armv", 4) == 0)
32266 for (i
= 0; q
[i
]; i
++)
32267 q
[i
] = TOUPPER (q
[i
]);
32269 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32272 /* Tag_CPU_arch. */
32273 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32275 /* Tag_CPU_arch_profile. */
32276 if (profile
!= '\0')
32277 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32279 /* Tag_DSP_extension. */
32280 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
32281 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
32283 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32284 /* Tag_ARM_ISA_use. */
32285 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
32286 || ARM_FEATURE_ZERO (flags_arch
))
32287 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
32289 /* Tag_THUMB_ISA_use. */
32290 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
32291 || ARM_FEATURE_ZERO (flags_arch
))
32295 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32296 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
32298 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
32302 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
32305 /* Tag_VFP_arch. */
32306 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
32307 aeabi_set_attribute_int (Tag_VFP_arch
,
32308 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32310 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
32311 aeabi_set_attribute_int (Tag_VFP_arch
,
32312 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32314 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
32317 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
32319 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
32321 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
32324 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
32325 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
32326 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
32327 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
32328 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
32330 /* Tag_ABI_HardFP_use. */
32331 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
32332 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
32333 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
32335 /* Tag_WMMX_arch. */
32336 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
32337 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
32338 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
32339 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
32341 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
32342 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
32343 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
32344 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
32345 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
32346 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
32348 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
32350 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
32354 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
32359 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
32360 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
32361 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
32362 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
32364 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
32365 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
32366 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
32370 We set Tag_DIV_use to two when integer divide instructions have been used
32371 in ARM state, or when Thumb integer divide instructions have been used,
32372 but we have no architecture profile set, nor have we any ARM instructions.
32374 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
32375 by the base architecture.
32377 For new architectures we will have to check these tests. */
32378 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32379 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32380 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
32381 aeabi_set_attribute_int (Tag_DIV_use
, 0);
32382 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
32383 || (profile
== '\0'
32384 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
32385 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
32386 aeabi_set_attribute_int (Tag_DIV_use
, 2);
32388 /* Tag_MP_extension_use. */
32389 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
32390 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
32392 /* Tag Virtualization_use. */
32393 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
32395 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
32398 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
32400 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
32401 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
32404 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
32405 finished and free extension feature bits which will not be used anymore. */
32408 arm_md_post_relax (void)
32410 aeabi_set_public_attributes ();
32411 XDELETE (mcpu_ext_opt
);
32412 mcpu_ext_opt
= NULL
;
32413 XDELETE (march_ext_opt
);
32414 march_ext_opt
= NULL
;
32417 /* Add the default contents for the .ARM.attributes section. */
32422 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
32425 aeabi_set_public_attributes ();
32427 #endif /* OBJ_ELF */
32429 /* Parse a .cpu directive. */
32432 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
32434 const struct arm_cpu_option_table
*opt
;
32438 name
= input_line_pointer
;
32439 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32440 input_line_pointer
++;
32441 saved_char
= *input_line_pointer
;
32442 *input_line_pointer
= 0;
32444 /* Skip the first "all" entry. */
32445 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
32446 if (streq (opt
->name
, name
))
32448 selected_arch
= opt
->value
;
32449 selected_ext
= opt
->ext
;
32450 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32451 if (opt
->canonical_name
)
32452 strcpy (selected_cpu_name
, opt
->canonical_name
);
32456 for (i
= 0; opt
->name
[i
]; i
++)
32457 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32459 selected_cpu_name
[i
] = 0;
32461 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32463 *input_line_pointer
= saved_char
;
32464 demand_empty_rest_of_line ();
32467 as_bad (_("unknown cpu `%s'"), name
);
32468 *input_line_pointer
= saved_char
;
32469 ignore_rest_of_line ();
32472 /* Parse a .arch directive. */
32475 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
32477 const struct arm_arch_option_table
*opt
;
32481 name
= input_line_pointer
;
32482 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32483 input_line_pointer
++;
32484 saved_char
= *input_line_pointer
;
32485 *input_line_pointer
= 0;
32487 /* Skip the first "all" entry. */
32488 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32489 if (streq (opt
->name
, name
))
32491 selected_arch
= opt
->value
;
32492 selected_ext
= arm_arch_none
;
32493 selected_cpu
= selected_arch
;
32494 strcpy (selected_cpu_name
, opt
->name
);
32495 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32496 *input_line_pointer
= saved_char
;
32497 demand_empty_rest_of_line ();
32501 as_bad (_("unknown architecture `%s'\n"), name
);
32502 *input_line_pointer
= saved_char
;
32503 ignore_rest_of_line ();
32506 /* Parse a .object_arch directive. */
32509 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
32511 const struct arm_arch_option_table
*opt
;
32515 name
= input_line_pointer
;
32516 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32517 input_line_pointer
++;
32518 saved_char
= *input_line_pointer
;
32519 *input_line_pointer
= 0;
32521 /* Skip the first "all" entry. */
32522 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32523 if (streq (opt
->name
, name
))
32525 selected_object_arch
= opt
->value
;
32526 *input_line_pointer
= saved_char
;
32527 demand_empty_rest_of_line ();
32531 as_bad (_("unknown architecture `%s'\n"), name
);
32532 *input_line_pointer
= saved_char
;
32533 ignore_rest_of_line ();
32536 /* Parse a .arch_extension directive. */
32539 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
32541 const struct arm_option_extension_value_table
*opt
;
32544 int adding_value
= 1;
32546 name
= input_line_pointer
;
32547 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32548 input_line_pointer
++;
32549 saved_char
= *input_line_pointer
;
32550 *input_line_pointer
= 0;
32552 if (strlen (name
) >= 2
32553 && strncmp (name
, "no", 2) == 0)
32559 /* Check the context specific extension table */
32560 if (selected_ctx_ext_table
)
32562 const struct arm_ext_table
* ext_opt
;
32563 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
32565 if (streq (ext_opt
->name
, name
))
32569 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32570 /* TODO: Option not supported. When we remove the
32571 legacy table this case should error out. */
32573 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32577 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
32579 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32580 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32581 *input_line_pointer
= saved_char
;
32582 demand_empty_rest_of_line ();
32588 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32589 if (streq (opt
->name
, name
))
32591 int i
, nb_allowed_archs
=
32592 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32593 for (i
= 0; i
< nb_allowed_archs
; i
++)
32596 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32598 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32602 if (i
== nb_allowed_archs
)
32604 as_bad (_("architectural extension `%s' is not allowed for the "
32605 "current base architecture"), name
);
32610 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32613 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32615 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32616 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32617 *input_line_pointer
= saved_char
;
32618 demand_empty_rest_of_line ();
32619 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32620 on this return so that duplicate extensions (extensions with the
32621 same name as a previous extension in the list) are not considered
32622 for command-line parsing. */
32626 if (opt
->name
== NULL
)
32627 as_bad (_("unknown architecture extension `%s'\n"), name
);
32629 *input_line_pointer
= saved_char
;
32630 ignore_rest_of_line ();
32633 /* Parse a .fpu directive. */
32636 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32638 const struct arm_option_fpu_value_table
*opt
;
32642 name
= input_line_pointer
;
32643 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32644 input_line_pointer
++;
32645 saved_char
= *input_line_pointer
;
32646 *input_line_pointer
= 0;
32648 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32649 if (streq (opt
->name
, name
))
32651 selected_fpu
= opt
->value
;
32652 #ifndef CPU_DEFAULT
32653 if (no_cpu_selected ())
32654 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32657 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32658 *input_line_pointer
= saved_char
;
32659 demand_empty_rest_of_line ();
32663 as_bad (_("unknown floating point format `%s'\n"), name
);
32664 *input_line_pointer
= saved_char
;
32665 ignore_rest_of_line ();
32668 /* Copy symbol information. */
32671 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32673 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32677 /* Given a symbolic attribute NAME, return the proper integer value.
32678 Returns -1 if the attribute is not known. */
32681 arm_convert_symbolic_attribute (const char *name
)
32683 static const struct
32688 attribute_table
[] =
32690 /* When you modify this table you should
32691 also modify the list in doc/c-arm.texi. */
32692 #define T(tag) {#tag, tag}
32693 T (Tag_CPU_raw_name
),
32696 T (Tag_CPU_arch_profile
),
32697 T (Tag_ARM_ISA_use
),
32698 T (Tag_THUMB_ISA_use
),
32702 T (Tag_Advanced_SIMD_arch
),
32703 T (Tag_PCS_config
),
32704 T (Tag_ABI_PCS_R9_use
),
32705 T (Tag_ABI_PCS_RW_data
),
32706 T (Tag_ABI_PCS_RO_data
),
32707 T (Tag_ABI_PCS_GOT_use
),
32708 T (Tag_ABI_PCS_wchar_t
),
32709 T (Tag_ABI_FP_rounding
),
32710 T (Tag_ABI_FP_denormal
),
32711 T (Tag_ABI_FP_exceptions
),
32712 T (Tag_ABI_FP_user_exceptions
),
32713 T (Tag_ABI_FP_number_model
),
32714 T (Tag_ABI_align_needed
),
32715 T (Tag_ABI_align8_needed
),
32716 T (Tag_ABI_align_preserved
),
32717 T (Tag_ABI_align8_preserved
),
32718 T (Tag_ABI_enum_size
),
32719 T (Tag_ABI_HardFP_use
),
32720 T (Tag_ABI_VFP_args
),
32721 T (Tag_ABI_WMMX_args
),
32722 T (Tag_ABI_optimization_goals
),
32723 T (Tag_ABI_FP_optimization_goals
),
32724 T (Tag_compatibility
),
32725 T (Tag_CPU_unaligned_access
),
32726 T (Tag_FP_HP_extension
),
32727 T (Tag_VFP_HP_extension
),
32728 T (Tag_ABI_FP_16bit_format
),
32729 T (Tag_MPextension_use
),
32731 T (Tag_nodefaults
),
32732 T (Tag_also_compatible_with
),
32733 T (Tag_conformance
),
32735 T (Tag_Virtualization_use
),
32736 T (Tag_DSP_extension
),
32738 /* We deliberately do not include Tag_MPextension_use_legacy. */
32746 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32747 if (streq (name
, attribute_table
[i
].name
))
32748 return attribute_table
[i
].tag
;
32753 /* Apply sym value for relocations only in the case that they are for
32754 local symbols in the same segment as the fixup and you have the
32755 respective architectural feature for blx and simple switches. */
32758 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32761 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32762 /* PR 17444: If the local symbol is in a different section then a reloc
32763 will always be generated for it, so applying the symbol value now
32764 will result in a double offset being stored in the relocation. */
32765 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32766 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32768 switch (fixP
->fx_r_type
)
32770 case BFD_RELOC_ARM_PCREL_BLX
:
32771 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32772 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32776 case BFD_RELOC_ARM_PCREL_CALL
:
32777 case BFD_RELOC_THUMB_PCREL_BLX
:
32778 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32789 #endif /* OBJ_ELF */