1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_arch_any
= ARM_ANY
;
213 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
214 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
215 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
216 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
218 static const arm_feature_set arm_cext_iwmmxt2
=
219 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
220 static const arm_feature_set arm_cext_iwmmxt
=
221 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
222 static const arm_feature_set arm_cext_xscale
=
223 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
224 static const arm_feature_set arm_cext_maverick
=
225 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
226 static const arm_feature_set fpu_fpa_ext_v1
=
227 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
228 static const arm_feature_set fpu_fpa_ext_v2
=
229 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
230 static const arm_feature_set fpu_vfp_ext_v1xd
=
231 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
232 static const arm_feature_set fpu_vfp_ext_v1
=
233 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
234 static const arm_feature_set fpu_vfp_ext_v2
=
235 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
236 static const arm_feature_set fpu_vfp_ext_v3xd
=
237 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
238 static const arm_feature_set fpu_vfp_ext_v3
=
239 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
240 static const arm_feature_set fpu_vfp_ext_d32
=
241 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
242 static const arm_feature_set fpu_neon_ext_v1
=
243 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
244 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
245 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
246 static const arm_feature_set fpu_vfp_fp16
=
247 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
248 static const arm_feature_set fpu_neon_ext_fma
=
249 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
250 static const arm_feature_set fpu_vfp_ext_fma
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
252 static const arm_feature_set fpu_vfp_ext_armv8
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
254 static const arm_feature_set fpu_vfp_ext_armv8xd
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
256 static const arm_feature_set fpu_neon_ext_armv8
=
257 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
258 static const arm_feature_set fpu_crypto_ext_armv8
=
259 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
260 static const arm_feature_set crc_ext_armv8
=
261 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
262 static const arm_feature_set fpu_neon_ext_v8_1
=
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
| FPU_NEON_EXT_RDMA
);
265 static int mfloat_abi_opt
= -1;
266 /* Record user cpu selection for object attributes. */
267 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
268 /* Must be long enough to hold any of the names in arm_cpus. */
269 static char selected_cpu_name
[20];
271 extern FLONUM_TYPE generic_floating_point_number
;
273 /* Return if no cpu was selected on command-line. */
275 no_cpu_selected (void)
277 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
282 static int meabi_flags
= EABI_DEFAULT
;
284 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
287 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
292 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
297 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
298 symbolS
* GOT_symbol
;
301 /* 0: assemble for ARM,
302 1: assemble for Thumb,
303 2: assemble for Thumb even though target CPU does not support thumb
305 static int thumb_mode
= 0;
306 /* A value distinct from the possible values for thumb_mode that we
307 can use to record whether thumb_mode has been copied into the
308 tc_frag_data field of a frag. */
309 #define MODE_RECORDED (1 << 4)
311 /* Specifies the intrinsic IT insn behavior mode. */
312 enum implicit_it_mode
314 IMPLICIT_IT_MODE_NEVER
= 0x00,
315 IMPLICIT_IT_MODE_ARM
= 0x01,
316 IMPLICIT_IT_MODE_THUMB
= 0x02,
317 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
319 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
321 /* If unified_syntax is true, we are processing the new unified
322 ARM/Thumb syntax. Important differences from the old ARM mode:
324 - Immediate operands do not require a # prefix.
325 - Conditional affixes always appear at the end of the
326 instruction. (For backward compatibility, those instructions
327 that formerly had them in the middle, continue to accept them
329 - The IT instruction may appear, and if it does is validated
330 against subsequent conditional affixes. It does not generate
333 Important differences from the old Thumb mode:
335 - Immediate operands do not require a # prefix.
336 - Most of the V6T2 instructions are only available in unified mode.
337 - The .N and .W suffixes are recognized and honored (it is an error
338 if they cannot be honored).
339 - All instructions set the flags if and only if they have an 's' affix.
340 - Conditional affixes may be used. They are validated against
341 preceding IT instructions. Unlike ARM mode, you cannot use a
342 conditional affix except in the scope of an IT instruction. */
344 static bfd_boolean unified_syntax
= FALSE
;
346 /* An immediate operand can start with #, and ld*, st*, pld operands
347 can contain [ and ]. We need to tell APP not to elide whitespace
348 before a [, which can appear as the first operand for pld.
349 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
350 const char arm_symbol_chars
[] = "#[]{}";
365 enum neon_el_type type
;
369 #define NEON_MAX_TYPE_ELS 4
373 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
377 enum it_instruction_type
382 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
383 if inside, should be the last one. */
384 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
385 i.e. BKPT and NOP. */
386 IT_INSN
/* The IT insn has been parsed. */
389 /* The maximum number of operands we need. */
390 #define ARM_IT_MAX_OPERANDS 6
395 unsigned long instruction
;
399 /* "uncond_value" is set to the value in place of the conditional field in
400 unconditional versions of the instruction, or -1 if nothing is
403 struct neon_type vectype
;
404 /* This does not indicate an actual NEON instruction, only that
405 the mnemonic accepts neon-style type suffixes. */
407 /* Set to the opcode if the instruction needs relaxation.
408 Zero if the instruction is not relaxed. */
412 bfd_reloc_code_real_type type
;
417 enum it_instruction_type it_insn_type
;
423 struct neon_type_el vectype
;
424 unsigned present
: 1; /* Operand present. */
425 unsigned isreg
: 1; /* Operand was a register. */
426 unsigned immisreg
: 1; /* .imm field is a second register. */
427 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
428 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
429 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
430 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
431 instructions. This allows us to disambiguate ARM <-> vector insns. */
432 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
433 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
434 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
435 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
436 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
437 unsigned writeback
: 1; /* Operand has trailing ! */
438 unsigned preind
: 1; /* Preindexed address. */
439 unsigned postind
: 1; /* Postindexed address. */
440 unsigned negative
: 1; /* Index register was negated. */
441 unsigned shifted
: 1; /* Shift applied to operation. */
442 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
443 } operands
[ARM_IT_MAX_OPERANDS
];
446 static struct arm_it inst
;
448 #define NUM_FLOAT_VALS 8
450 const char * fp_const
[] =
452 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
455 /* Number of littlenums required to hold an extended precision number. */
456 #define MAX_LITTLENUMS 6
458 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
468 #define CP_T_X 0x00008000
469 #define CP_T_Y 0x00400000
471 #define CONDS_BIT 0x00100000
472 #define LOAD_BIT 0x00100000
474 #define DOUBLE_LOAD_FLAG 0x00000001
478 const char * template_name
;
482 #define COND_ALWAYS 0xE
486 const char * template_name
;
490 struct asm_barrier_opt
492 const char * template_name
;
494 const arm_feature_set arch
;
497 /* The bit that distinguishes CPSR and SPSR. */
498 #define SPSR_BIT (1 << 22)
500 /* The individual PSR flag bits. */
501 #define PSR_c (1 << 16)
502 #define PSR_x (1 << 17)
503 #define PSR_s (1 << 18)
504 #define PSR_f (1 << 19)
509 bfd_reloc_code_real_type reloc
;
514 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
515 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
520 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
523 /* Bits for DEFINED field in neon_typed_alias. */
524 #define NTA_HASTYPE 1
525 #define NTA_HASINDEX 2
527 struct neon_typed_alias
529 unsigned char defined
;
531 struct neon_type_el eltype
;
534 /* ARM register categories. This includes coprocessor numbers and various
535 architecture extensions' registers. */
562 /* Structure for a hash table entry for a register.
563 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
564 information which states whether a vector type or index is specified (for a
565 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
571 unsigned char builtin
;
572 struct neon_typed_alias
* neon
;
575 /* Diagnostics used when we don't get a register of the expected type. */
576 const char * const reg_expected_msgs
[] =
578 N_("ARM register expected"),
579 N_("bad or missing co-processor number"),
580 N_("co-processor register expected"),
581 N_("FPA register expected"),
582 N_("VFP single precision register expected"),
583 N_("VFP/Neon double precision register expected"),
584 N_("Neon quad precision register expected"),
585 N_("VFP single or double precision register expected"),
586 N_("Neon double or quad precision register expected"),
587 N_("VFP single, double or Neon quad precision register expected"),
588 N_("VFP system register expected"),
589 N_("Maverick MVF register expected"),
590 N_("Maverick MVD register expected"),
591 N_("Maverick MVFX register expected"),
592 N_("Maverick MVDX register expected"),
593 N_("Maverick MVAX register expected"),
594 N_("Maverick DSPSC register expected"),
595 N_("iWMMXt data register expected"),
596 N_("iWMMXt control register expected"),
597 N_("iWMMXt scalar register expected"),
598 N_("XScale accumulator register expected"),
601 /* Some well known registers that we refer to directly elsewhere. */
607 /* ARM instructions take 4bytes in the object file, Thumb instructions
613 /* Basic string to match. */
614 const char * template_name
;
616 /* Parameters to instruction. */
617 unsigned int operands
[8];
619 /* Conditional tag - see opcode_lookup. */
620 unsigned int tag
: 4;
622 /* Basic instruction code. */
623 unsigned int avalue
: 28;
625 /* Thumb-format instruction code. */
628 /* Which architecture variant provides this instruction. */
629 const arm_feature_set
* avariant
;
630 const arm_feature_set
* tvariant
;
632 /* Function to call to encode instruction in ARM format. */
633 void (* aencode
) (void);
635 /* Function to call to encode instruction in Thumb format. */
636 void (* tencode
) (void);
639 /* Defines for various bits that we will want to toggle. */
640 #define INST_IMMEDIATE 0x02000000
641 #define OFFSET_REG 0x02000000
642 #define HWOFFSET_IMM 0x00400000
643 #define SHIFT_BY_REG 0x00000010
644 #define PRE_INDEX 0x01000000
645 #define INDEX_UP 0x00800000
646 #define WRITE_BACK 0x00200000
647 #define LDM_TYPE_2_OR_3 0x00400000
648 #define CPSI_MMOD 0x00020000
650 #define LITERAL_MASK 0xf000f000
651 #define OPCODE_MASK 0xfe1fffff
652 #define V4_STR_BIT 0x00000020
653 #define VLDR_VMOV_SAME 0x0040f000
655 #define T2_SUBS_PC_LR 0xf3de8f00
657 #define DATA_OP_SHIFT 21
659 #define T2_OPCODE_MASK 0xfe1fffff
660 #define T2_DATA_OP_SHIFT 21
662 #define A_COND_MASK 0xf0000000
663 #define A_PUSH_POP_OP_MASK 0x0fff0000
665 /* Opcodes for pushing/poping registers to/from the stack. */
666 #define A1_OPCODE_PUSH 0x092d0000
667 #define A2_OPCODE_PUSH 0x052d0004
668 #define A2_OPCODE_POP 0x049d0004
670 /* Codes to distinguish the arithmetic instructions. */
681 #define OPCODE_CMP 10
682 #define OPCODE_CMN 11
683 #define OPCODE_ORR 12
684 #define OPCODE_MOV 13
685 #define OPCODE_BIC 14
686 #define OPCODE_MVN 15
688 #define T2_OPCODE_AND 0
689 #define T2_OPCODE_BIC 1
690 #define T2_OPCODE_ORR 2
691 #define T2_OPCODE_ORN 3
692 #define T2_OPCODE_EOR 4
693 #define T2_OPCODE_ADD 8
694 #define T2_OPCODE_ADC 10
695 #define T2_OPCODE_SBC 11
696 #define T2_OPCODE_SUB 13
697 #define T2_OPCODE_RSB 14
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ROR_R 0x41c0
721 #define T_OPCODE_ASR_I 0x1000
722 #define T_OPCODE_LSL_I 0x0000
723 #define T_OPCODE_LSR_I 0x0800
725 #define T_OPCODE_MOV_I8 0x2000
726 #define T_OPCODE_CMP_I8 0x2800
727 #define T_OPCODE_CMP_LR 0x4280
728 #define T_OPCODE_MOV_HR 0x4600
729 #define T_OPCODE_CMP_HR 0x4500
731 #define T_OPCODE_LDR_PC 0x4800
732 #define T_OPCODE_LDR_SP 0x9800
733 #define T_OPCODE_STR_SP 0x9000
734 #define T_OPCODE_LDR_IW 0x6800
735 #define T_OPCODE_STR_IW 0x6000
736 #define T_OPCODE_LDR_IH 0x8800
737 #define T_OPCODE_STR_IH 0x8000
738 #define T_OPCODE_LDR_IB 0x7800
739 #define T_OPCODE_STR_IB 0x7000
740 #define T_OPCODE_LDR_RW 0x5800
741 #define T_OPCODE_STR_RW 0x5000
742 #define T_OPCODE_LDR_RH 0x5a00
743 #define T_OPCODE_STR_RH 0x5200
744 #define T_OPCODE_LDR_RB 0x5c00
745 #define T_OPCODE_STR_RB 0x5400
747 #define T_OPCODE_PUSH 0xb400
748 #define T_OPCODE_POP 0xbc00
750 #define T_OPCODE_BRANCH 0xe000
752 #define THUMB_SIZE 2 /* Size of thumb instruction. */
753 #define THUMB_PP_PC_LR 0x0100
754 #define THUMB_LOAD_BIT 0x0800
755 #define THUMB2_LOAD_BIT 0x00100000
757 #define BAD_ARGS _("bad arguments to instruction")
758 #define BAD_SP _("r13 not allowed here")
759 #define BAD_PC _("r15 not allowed here")
760 #define BAD_COND _("instruction cannot be conditional")
761 #define BAD_OVERLAP _("registers may not be the same")
762 #define BAD_HIREG _("lo register required")
763 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
764 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
765 #define BAD_BRANCH _("branch must be last instruction in IT block")
766 #define BAD_NOT_IT _("instruction not allowed in IT block")
767 #define BAD_FPU _("selected FPU does not support instruction")
768 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
769 #define BAD_IT_COND _("incorrect condition in IT block")
770 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
771 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
772 #define BAD_PC_ADDRESSING \
773 _("cannot use register index with PC-relative addressing")
774 #define BAD_PC_WRITEBACK \
775 _("cannot use writeback with PC-relative addressing")
776 #define BAD_RANGE _("branch out of range")
777 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
779 static struct hash_control
* arm_ops_hsh
;
780 static struct hash_control
* arm_cond_hsh
;
781 static struct hash_control
* arm_shift_hsh
;
782 static struct hash_control
* arm_psr_hsh
;
783 static struct hash_control
* arm_v7m_psr_hsh
;
784 static struct hash_control
* arm_reg_hsh
;
785 static struct hash_control
* arm_reloc_hsh
;
786 static struct hash_control
* arm_barrier_opt_hsh
;
788 /* Stuff needed to resolve the label ambiguity
797 symbolS
* last_label_seen
;
798 static int label_is_thumb_function_name
= FALSE
;
800 /* Literal pool structure. Held on a per-section
801 and per-sub-section basis. */
803 #define MAX_LITERAL_POOL_SIZE 1024
804 typedef struct literal_pool
806 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
807 unsigned int next_free_entry
;
813 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
815 struct literal_pool
* next
;
816 unsigned int alignment
;
819 /* Pointer to a linked list of literal pools. */
820 literal_pool
* list_of_pools
= NULL
;
822 typedef enum asmfunc_states
825 WAITING_ASMFUNC_NAME
,
829 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
832 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
834 static struct current_it now_it
;
838 now_it_compatible (int cond
)
840 return (cond
& ~1) == (now_it
.cc
& ~1);
844 conditional_insn (void)
846 return inst
.cond
!= COND_ALWAYS
;
849 static int in_it_block (void);
851 static int handle_it_state (void);
853 static void force_automatic_it_block_close (void);
855 static void it_fsm_post_encode (void);
857 #define set_it_insn_type(type) \
860 inst.it_insn_type = type; \
861 if (handle_it_state () == FAIL) \
866 #define set_it_insn_type_nonvoid(type, failret) \
869 inst.it_insn_type = type; \
870 if (handle_it_state () == FAIL) \
875 #define set_it_insn_type_last() \
878 if (inst.cond == COND_ALWAYS) \
879 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
881 set_it_insn_type (INSIDE_IT_LAST_INSN); \
887 /* This array holds the chars that always start a comment. If the
888 pre-processor is disabled, these aren't very useful. */
889 char arm_comment_chars
[] = "@";
891 /* This array holds the chars that only start a comment at the beginning of
892 a line. If the line seems to have the form '# 123 filename'
893 .line and .file directives will appear in the pre-processed output. */
894 /* Note that input_file.c hand checks for '#' at the beginning of the
895 first line of the input file. This is because the compiler outputs
896 #NO_APP at the beginning of its output. */
897 /* Also note that comments like this one will always work. */
898 const char line_comment_chars
[] = "#";
900 char arm_line_separator_chars
[] = ";";
902 /* Chars that can be used to separate mant
903 from exp in floating point numbers. */
904 const char EXP_CHARS
[] = "eE";
906 /* Chars that mean this number is a floating point constant. */
910 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
912 /* Prefix characters that indicate the start of an immediate
914 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
916 /* Separator character handling. */
918 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
921 skip_past_char (char ** str
, char c
)
923 /* PR gas/14987: Allow for whitespace before the expected character. */
924 skip_whitespace (*str
);
935 #define skip_past_comma(str) skip_past_char (str, ',')
937 /* Arithmetic expressions (possibly involving symbols). */
939 /* Return TRUE if anything in the expression is a bignum. */
942 walk_no_bignums (symbolS
* sp
)
944 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
947 if (symbol_get_value_expression (sp
)->X_add_symbol
)
949 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
950 || (symbol_get_value_expression (sp
)->X_op_symbol
951 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
957 static int in_my_get_expression
= 0;
959 /* Third argument to my_get_expression. */
960 #define GE_NO_PREFIX 0
961 #define GE_IMM_PREFIX 1
962 #define GE_OPT_PREFIX 2
963 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
964 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
965 #define GE_OPT_PREFIX_BIG 3
968 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
973 /* In unified syntax, all prefixes are optional. */
975 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
980 case GE_NO_PREFIX
: break;
982 if (!is_immediate_prefix (**str
))
984 inst
.error
= _("immediate expression requires a # prefix");
990 case GE_OPT_PREFIX_BIG
:
991 if (is_immediate_prefix (**str
))
997 memset (ep
, 0, sizeof (expressionS
));
999 save_in
= input_line_pointer
;
1000 input_line_pointer
= *str
;
1001 in_my_get_expression
= 1;
1002 seg
= expression (ep
);
1003 in_my_get_expression
= 0;
1005 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1007 /* We found a bad or missing expression in md_operand(). */
1008 *str
= input_line_pointer
;
1009 input_line_pointer
= save_in
;
1010 if (inst
.error
== NULL
)
1011 inst
.error
= (ep
->X_op
== O_absent
1012 ? _("missing expression") :_("bad expression"));
1017 if (seg
!= absolute_section
1018 && seg
!= text_section
1019 && seg
!= data_section
1020 && seg
!= bss_section
1021 && seg
!= undefined_section
)
1023 inst
.error
= _("bad segment");
1024 *str
= input_line_pointer
;
1025 input_line_pointer
= save_in
;
1032 /* Get rid of any bignums now, so that we don't generate an error for which
1033 we can't establish a line number later on. Big numbers are never valid
1034 in instructions, which is where this routine is always called. */
1035 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1036 && (ep
->X_op
== O_big
1037 || (ep
->X_add_symbol
1038 && (walk_no_bignums (ep
->X_add_symbol
)
1040 && walk_no_bignums (ep
->X_op_symbol
))))))
1042 inst
.error
= _("invalid constant");
1043 *str
= input_line_pointer
;
1044 input_line_pointer
= save_in
;
1048 *str
= input_line_pointer
;
1049 input_line_pointer
= save_in
;
1053 /* Turn a string in input_line_pointer into a floating point constant
1054 of type TYPE, and store the appropriate bytes in *LITP. The number
1055 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1056 returned, or NULL on OK.
1058 Note that fp constants aren't represent in the normal way on the ARM.
1059 In big endian mode, things are as expected. However, in little endian
1060 mode fp constants are big-endian word-wise, and little-endian byte-wise
1061 within the words. For example, (double) 1.1 in big endian mode is
1062 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1063 the byte sequence 99 99 f1 3f 9a 99 99 99.
1065 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1068 md_atof (int type
, char * litP
, int * sizeP
)
1071 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1103 return _("Unrecognized or unsupported floating point constant");
1106 t
= atof_ieee (input_line_pointer
, type
, words
);
1108 input_line_pointer
= t
;
1109 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1111 if (target_big_endian
)
1113 for (i
= 0; i
< prec
; i
++)
1115 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1116 litP
+= sizeof (LITTLENUM_TYPE
);
1121 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1122 for (i
= prec
- 1; i
>= 0; i
--)
1124 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1125 litP
+= sizeof (LITTLENUM_TYPE
);
1128 /* For a 4 byte float the order of elements in `words' is 1 0.
1129 For an 8 byte float the order is 1 0 3 2. */
1130 for (i
= 0; i
< prec
; i
+= 2)
1132 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1133 sizeof (LITTLENUM_TYPE
));
1134 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1135 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1136 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1143 /* We handle all bad expressions here, so that we can report the faulty
1144 instruction in the error message. */
1146 md_operand (expressionS
* exp
)
1148 if (in_my_get_expression
)
1149 exp
->X_op
= O_illegal
;
1152 /* Immediate values. */
1154 /* Generic immediate-value read function for use in directives.
1155 Accepts anything that 'expression' can fold to a constant.
1156 *val receives the number. */
1159 immediate_for_directive (int *val
)
1162 exp
.X_op
= O_illegal
;
1164 if (is_immediate_prefix (*input_line_pointer
))
1166 input_line_pointer
++;
1170 if (exp
.X_op
!= O_constant
)
1172 as_bad (_("expected #constant"));
1173 ignore_rest_of_line ();
1176 *val
= exp
.X_add_number
;
1181 /* Register parsing. */
1183 /* Generic register parser. CCP points to what should be the
1184 beginning of a register name. If it is indeed a valid register
1185 name, advance CCP over it and return the reg_entry structure;
1186 otherwise return NULL. Does not issue diagnostics. */
1188 static struct reg_entry
*
1189 arm_reg_parse_multi (char **ccp
)
1193 struct reg_entry
*reg
;
1195 skip_whitespace (start
);
1197 #ifdef REGISTER_PREFIX
1198 if (*start
!= REGISTER_PREFIX
)
1202 #ifdef OPTIONAL_REGISTER_PREFIX
1203 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1208 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1213 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1215 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1225 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1226 enum arm_reg_type type
)
1228 /* Alternative syntaxes are accepted for a few register classes. */
1235 /* Generic coprocessor register names are allowed for these. */
1236 if (reg
&& reg
->type
== REG_TYPE_CN
)
1241 /* For backward compatibility, a bare number is valid here. */
1243 unsigned long processor
= strtoul (start
, ccp
, 10);
1244 if (*ccp
!= start
&& processor
<= 15)
1248 case REG_TYPE_MMXWC
:
1249 /* WC includes WCG. ??? I'm not sure this is true for all
1250 instructions that take WC registers. */
1251 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1262 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1263 return value is the register number or FAIL. */
1266 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1269 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1272 /* Do not allow a scalar (reg+index) to parse as a register. */
1273 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1276 if (reg
&& reg
->type
== type
)
1279 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1286 /* Parse a Neon type specifier. *STR should point at the leading '.'
1287 character. Does no verification at this stage that the type fits the opcode
1294 Can all be legally parsed by this function.
1296 Fills in neon_type struct pointer with parsed information, and updates STR
1297 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1298 type, FAIL if not. */
1301 parse_neon_type (struct neon_type
*type
, char **str
)
1308 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1310 enum neon_el_type thistype
= NT_untyped
;
1311 unsigned thissize
= -1u;
1318 /* Just a size without an explicit type. */
1322 switch (TOLOWER (*ptr
))
1324 case 'i': thistype
= NT_integer
; break;
1325 case 'f': thistype
= NT_float
; break;
1326 case 'p': thistype
= NT_poly
; break;
1327 case 's': thistype
= NT_signed
; break;
1328 case 'u': thistype
= NT_unsigned
; break;
1330 thistype
= NT_float
;
1335 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1341 /* .f is an abbreviation for .f32. */
1342 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1347 thissize
= strtoul (ptr
, &ptr
, 10);
1349 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1352 as_bad (_("bad size %d in type specifier"), thissize
);
1360 type
->el
[type
->elems
].type
= thistype
;
1361 type
->el
[type
->elems
].size
= thissize
;
1366 /* Empty/missing type is not a successful parse. */
1367 if (type
->elems
== 0)
1375 /* Errors may be set multiple times during parsing or bit encoding
1376 (particularly in the Neon bits), but usually the earliest error which is set
1377 will be the most meaningful. Avoid overwriting it with later (cascading)
1378 errors by calling this function. */
1381 first_error (const char *err
)
1387 /* Parse a single type, e.g. ".s32", leading period included. */
1389 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1392 struct neon_type optype
;
1396 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1398 if (optype
.elems
== 1)
1399 *vectype
= optype
.el
[0];
1402 first_error (_("only one type should be specified for operand"));
1408 first_error (_("vector type expected"));
1420 /* Special meanings for indices (which have a range of 0-7), which will fit into
1423 #define NEON_ALL_LANES 15
1424 #define NEON_INTERLEAVE_LANES 14
1426 /* Parse either a register or a scalar, with an optional type. Return the
1427 register number, and optionally fill in the actual type of the register
1428 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1429 type/index information in *TYPEINFO. */
1432 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1433 enum arm_reg_type
*rtype
,
1434 struct neon_typed_alias
*typeinfo
)
1437 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1438 struct neon_typed_alias atype
;
1439 struct neon_type_el parsetype
;
1443 atype
.eltype
.type
= NT_invtype
;
1444 atype
.eltype
.size
= -1;
1446 /* Try alternate syntax for some types of register. Note these are mutually
1447 exclusive with the Neon syntax extensions. */
1450 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1458 /* Undo polymorphism when a set of register types may be accepted. */
1459 if ((type
== REG_TYPE_NDQ
1460 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1461 || (type
== REG_TYPE_VFSD
1462 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1463 || (type
== REG_TYPE_NSDQ
1464 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1465 || reg
->type
== REG_TYPE_NQ
))
1466 || (type
== REG_TYPE_MMXWC
1467 && (reg
->type
== REG_TYPE_MMXWCG
)))
1468 type
= (enum arm_reg_type
) reg
->type
;
1470 if (type
!= reg
->type
)
1476 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1478 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1480 first_error (_("can't redefine type for operand"));
1483 atype
.defined
|= NTA_HASTYPE
;
1484 atype
.eltype
= parsetype
;
1487 if (skip_past_char (&str
, '[') == SUCCESS
)
1489 if (type
!= REG_TYPE_VFD
)
1491 first_error (_("only D registers may be indexed"));
1495 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1497 first_error (_("can't change index for operand"));
1501 atype
.defined
|= NTA_HASINDEX
;
1503 if (skip_past_char (&str
, ']') == SUCCESS
)
1504 atype
.index
= NEON_ALL_LANES
;
1509 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1511 if (exp
.X_op
!= O_constant
)
1513 first_error (_("constant expression required"));
1517 if (skip_past_char (&str
, ']') == FAIL
)
1520 atype
.index
= exp
.X_add_number
;
1535 /* Like arm_reg_parse, but allow allow the following extra features:
1536 - If RTYPE is non-zero, return the (possibly restricted) type of the
1537 register (e.g. Neon double or quad reg when either has been requested).
1538 - If this is a Neon vector type with additional type information, fill
1539 in the struct pointed to by VECTYPE (if non-NULL).
1540 This function will fault on encountering a scalar. */
1543 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1544 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1546 struct neon_typed_alias atype
;
1548 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1553 /* Do not allow regname(... to parse as a register. */
1557 /* Do not allow a scalar (reg+index) to parse as a register. */
1558 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1560 first_error (_("register operand expected, but got scalar"));
1565 *vectype
= atype
.eltype
;
1572 #define NEON_SCALAR_REG(X) ((X) >> 4)
1573 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1575 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1576 have enough information to be able to do a good job bounds-checking. So, we
1577 just do easy checks here, and do further checks later. */
1580 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1584 struct neon_typed_alias atype
;
1586 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1588 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1591 if (atype
.index
== NEON_ALL_LANES
)
1593 first_error (_("scalar must have an index"));
1596 else if (atype
.index
>= 64 / elsize
)
1598 first_error (_("scalar index out of range"));
1603 *type
= atype
.eltype
;
1607 return reg
* 16 + atype
.index
;
1610 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1613 parse_reg_list (char ** strp
)
1615 char * str
= * strp
;
1619 /* We come back here if we get ranges concatenated by '+' or '|'. */
1622 skip_whitespace (str
);
1636 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1638 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1648 first_error (_("bad range in register list"));
1652 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1654 if (range
& (1 << i
))
1656 (_("Warning: duplicated register (r%d) in register list"),
1664 if (range
& (1 << reg
))
1665 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1667 else if (reg
<= cur_reg
)
1668 as_tsktsk (_("Warning: register range not in ascending order"));
1673 while (skip_past_comma (&str
) != FAIL
1674 || (in_range
= 1, *str
++ == '-'));
1677 if (skip_past_char (&str
, '}') == FAIL
)
1679 first_error (_("missing `}'"));
1687 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1690 if (exp
.X_op
== O_constant
)
1692 if (exp
.X_add_number
1693 != (exp
.X_add_number
& 0x0000ffff))
1695 inst
.error
= _("invalid register mask");
1699 if ((range
& exp
.X_add_number
) != 0)
1701 int regno
= range
& exp
.X_add_number
;
1704 regno
= (1 << regno
) - 1;
1706 (_("Warning: duplicated register (r%d) in register list"),
1710 range
|= exp
.X_add_number
;
1714 if (inst
.reloc
.type
!= 0)
1716 inst
.error
= _("expression too complex");
1720 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1721 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1722 inst
.reloc
.pc_rel
= 0;
1726 if (*str
== '|' || *str
== '+')
1732 while (another_range
);
1738 /* Types of registers in a list. */
1747 /* Parse a VFP register list. If the string is invalid return FAIL.
1748 Otherwise return the number of registers, and set PBASE to the first
1749 register. Parses registers of type ETYPE.
1750 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1751 - Q registers can be used to specify pairs of D registers
1752 - { } can be omitted from around a singleton register list
1753 FIXME: This is not implemented, as it would require backtracking in
1756 This could be done (the meaning isn't really ambiguous), but doesn't
1757 fit in well with the current parsing framework.
1758 - 32 D registers may be used (also true for VFPv3).
1759 FIXME: Types are ignored in these register lists, which is probably a
1763 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1768 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1772 unsigned long mask
= 0;
1775 if (skip_past_char (&str
, '{') == FAIL
)
1777 inst
.error
= _("expecting {");
1784 regtype
= REG_TYPE_VFS
;
1789 regtype
= REG_TYPE_VFD
;
1792 case REGLIST_NEON_D
:
1793 regtype
= REG_TYPE_NDQ
;
1797 if (etype
!= REGLIST_VFP_S
)
1799 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1800 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1804 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1807 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1814 base_reg
= max_regs
;
1818 int setmask
= 1, addregs
= 1;
1820 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1822 if (new_base
== FAIL
)
1824 first_error (_(reg_expected_msgs
[regtype
]));
1828 if (new_base
>= max_regs
)
1830 first_error (_("register out of range in list"));
1834 /* Note: a value of 2 * n is returned for the register Q<n>. */
1835 if (regtype
== REG_TYPE_NQ
)
1841 if (new_base
< base_reg
)
1842 base_reg
= new_base
;
1844 if (mask
& (setmask
<< new_base
))
1846 first_error (_("invalid register list"));
1850 if ((mask
>> new_base
) != 0 && ! warned
)
1852 as_tsktsk (_("register list not in ascending order"));
1856 mask
|= setmask
<< new_base
;
1859 if (*str
== '-') /* We have the start of a range expression */
1865 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1868 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1872 if (high_range
>= max_regs
)
1874 first_error (_("register out of range in list"));
1878 if (regtype
== REG_TYPE_NQ
)
1879 high_range
= high_range
+ 1;
1881 if (high_range
<= new_base
)
1883 inst
.error
= _("register range not in ascending order");
1887 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1889 if (mask
& (setmask
<< new_base
))
1891 inst
.error
= _("invalid register list");
1895 mask
|= setmask
<< new_base
;
1900 while (skip_past_comma (&str
) != FAIL
);
1904 /* Sanity check -- should have raised a parse error above. */
1905 if (count
== 0 || count
> max_regs
)
1910 /* Final test -- the registers must be consecutive. */
1912 for (i
= 0; i
< count
; i
++)
1914 if ((mask
& (1u << i
)) == 0)
1916 inst
.error
= _("non-contiguous register range");
1926 /* True if two alias types are the same. */
1929 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1937 if (a
->defined
!= b
->defined
)
1940 if ((a
->defined
& NTA_HASTYPE
) != 0
1941 && (a
->eltype
.type
!= b
->eltype
.type
1942 || a
->eltype
.size
!= b
->eltype
.size
))
1945 if ((a
->defined
& NTA_HASINDEX
) != 0
1946 && (a
->index
!= b
->index
))
1952 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1953 The base register is put in *PBASE.
1954 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1956 The register stride (minus one) is put in bit 4 of the return value.
1957 Bits [6:5] encode the list length (minus one).
1958 The type of the list elements is put in *ELTYPE, if non-NULL. */
1960 #define NEON_LANE(X) ((X) & 0xf)
1961 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1962 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1965 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1966 struct neon_type_el
*eltype
)
1973 int leading_brace
= 0;
1974 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1975 const char *const incr_error
= _("register stride must be 1 or 2");
1976 const char *const type_error
= _("mismatched element/structure types in list");
1977 struct neon_typed_alias firsttype
;
1979 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1984 struct neon_typed_alias atype
;
1985 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1989 first_error (_(reg_expected_msgs
[rtype
]));
1996 if (rtype
== REG_TYPE_NQ
)
2002 else if (reg_incr
== -1)
2004 reg_incr
= getreg
- base_reg
;
2005 if (reg_incr
< 1 || reg_incr
> 2)
2007 first_error (_(incr_error
));
2011 else if (getreg
!= base_reg
+ reg_incr
* count
)
2013 first_error (_(incr_error
));
2017 if (! neon_alias_types_same (&atype
, &firsttype
))
2019 first_error (_(type_error
));
2023 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2027 struct neon_typed_alias htype
;
2028 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2030 lane
= NEON_INTERLEAVE_LANES
;
2031 else if (lane
!= NEON_INTERLEAVE_LANES
)
2033 first_error (_(type_error
));
2038 else if (reg_incr
!= 1)
2040 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2044 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2047 first_error (_(reg_expected_msgs
[rtype
]));
2050 if (! neon_alias_types_same (&htype
, &firsttype
))
2052 first_error (_(type_error
));
2055 count
+= hireg
+ dregs
- getreg
;
2059 /* If we're using Q registers, we can't use [] or [n] syntax. */
2060 if (rtype
== REG_TYPE_NQ
)
2066 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2070 else if (lane
!= atype
.index
)
2072 first_error (_(type_error
));
2076 else if (lane
== -1)
2077 lane
= NEON_INTERLEAVE_LANES
;
2078 else if (lane
!= NEON_INTERLEAVE_LANES
)
2080 first_error (_(type_error
));
2085 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2087 /* No lane set by [x]. We must be interleaving structures. */
2089 lane
= NEON_INTERLEAVE_LANES
;
2092 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2093 || (count
> 1 && reg_incr
== -1))
2095 first_error (_("error parsing element/structure list"));
2099 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2101 first_error (_("expected }"));
2109 *eltype
= firsttype
.eltype
;
2114 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2117 /* Parse an explicit relocation suffix on an expression. This is
2118 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2119 arm_reloc_hsh contains no entries, so this function can only
2120 succeed if there is no () after the word. Returns -1 on error,
2121 BFD_RELOC_UNUSED if there wasn't any suffix. */
2124 parse_reloc (char **str
)
2126 struct reloc_entry
*r
;
2130 return BFD_RELOC_UNUSED
;
2135 while (*q
&& *q
!= ')' && *q
!= ',')
2140 if ((r
= (struct reloc_entry
*)
2141 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2148 /* Directives: register aliases. */
2150 static struct reg_entry
*
2151 insert_reg_alias (char *str
, unsigned number
, int type
)
2153 struct reg_entry
*new_reg
;
2156 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2158 if (new_reg
->builtin
)
2159 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2161 /* Only warn about a redefinition if it's not defined as the
2163 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2164 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2169 name
= xstrdup (str
);
2170 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2172 new_reg
->name
= name
;
2173 new_reg
->number
= number
;
2174 new_reg
->type
= type
;
2175 new_reg
->builtin
= FALSE
;
2176 new_reg
->neon
= NULL
;
2178 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2185 insert_neon_reg_alias (char *str
, int number
, int type
,
2186 struct neon_typed_alias
*atype
)
2188 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2192 first_error (_("attempt to redefine typed alias"));
2198 reg
->neon
= (struct neon_typed_alias
*)
2199 xmalloc (sizeof (struct neon_typed_alias
));
2200 *reg
->neon
= *atype
;
2204 /* Look for the .req directive. This is of the form:
2206 new_register_name .req existing_register_name
2208 If we find one, or if it looks sufficiently like one that we want to
2209 handle any error here, return TRUE. Otherwise return FALSE. */
2212 create_register_alias (char * newname
, char *p
)
2214 struct reg_entry
*old
;
2215 char *oldname
, *nbuf
;
2218 /* The input scrubber ensures that whitespace after the mnemonic is
2219 collapsed to single spaces. */
2221 if (strncmp (oldname
, " .req ", 6) != 0)
2225 if (*oldname
== '\0')
2228 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2231 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2235 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2236 the desired alias name, and p points to its end. If not, then
2237 the desired alias name is in the global original_case_string. */
2238 #ifdef TC_CASE_SENSITIVE
2241 newname
= original_case_string
;
2242 nlen
= strlen (newname
);
2245 nbuf
= (char *) alloca (nlen
+ 1);
2246 memcpy (nbuf
, newname
, nlen
);
2249 /* Create aliases under the new name as stated; an all-lowercase
2250 version of the new name; and an all-uppercase version of the new
2252 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2254 for (p
= nbuf
; *p
; p
++)
2257 if (strncmp (nbuf
, newname
, nlen
))
2259 /* If this attempt to create an additional alias fails, do not bother
2260 trying to create the all-lower case alias. We will fail and issue
2261 a second, duplicate error message. This situation arises when the
2262 programmer does something like:
2265 The second .req creates the "Foo" alias but then fails to create
2266 the artificial FOO alias because it has already been created by the
2268 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2272 for (p
= nbuf
; *p
; p
++)
2275 if (strncmp (nbuf
, newname
, nlen
))
2276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2282 /* Create a Neon typed/indexed register alias using directives, e.g.:
2287 These typed registers can be used instead of the types specified after the
2288 Neon mnemonic, so long as all operands given have types. Types can also be
2289 specified directly, e.g.:
2290 vadd d0.s32, d1.s32, d2.s32 */
2293 create_neon_reg_alias (char *newname
, char *p
)
2295 enum arm_reg_type basetype
;
2296 struct reg_entry
*basereg
;
2297 struct reg_entry mybasereg
;
2298 struct neon_type ntype
;
2299 struct neon_typed_alias typeinfo
;
2300 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2303 typeinfo
.defined
= 0;
2304 typeinfo
.eltype
.type
= NT_invtype
;
2305 typeinfo
.eltype
.size
= -1;
2306 typeinfo
.index
= -1;
2310 if (strncmp (p
, " .dn ", 5) == 0)
2311 basetype
= REG_TYPE_VFD
;
2312 else if (strncmp (p
, " .qn ", 5) == 0)
2313 basetype
= REG_TYPE_NQ
;
2322 basereg
= arm_reg_parse_multi (&p
);
2324 if (basereg
&& basereg
->type
!= basetype
)
2326 as_bad (_("bad type for register"));
2330 if (basereg
== NULL
)
2333 /* Try parsing as an integer. */
2334 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2335 if (exp
.X_op
!= O_constant
)
2337 as_bad (_("expression must be constant"));
2340 basereg
= &mybasereg
;
2341 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2347 typeinfo
= *basereg
->neon
;
2349 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2351 /* We got a type. */
2352 if (typeinfo
.defined
& NTA_HASTYPE
)
2354 as_bad (_("can't redefine the type of a register alias"));
2358 typeinfo
.defined
|= NTA_HASTYPE
;
2359 if (ntype
.elems
!= 1)
2361 as_bad (_("you must specify a single type only"));
2364 typeinfo
.eltype
= ntype
.el
[0];
2367 if (skip_past_char (&p
, '[') == SUCCESS
)
2370 /* We got a scalar index. */
2372 if (typeinfo
.defined
& NTA_HASINDEX
)
2374 as_bad (_("can't redefine the index of a scalar alias"));
2378 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2380 if (exp
.X_op
!= O_constant
)
2382 as_bad (_("scalar index must be constant"));
2386 typeinfo
.defined
|= NTA_HASINDEX
;
2387 typeinfo
.index
= exp
.X_add_number
;
2389 if (skip_past_char (&p
, ']') == FAIL
)
2391 as_bad (_("expecting ]"));
2396 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2397 the desired alias name, and p points to its end. If not, then
2398 the desired alias name is in the global original_case_string. */
2399 #ifdef TC_CASE_SENSITIVE
2400 namelen
= nameend
- newname
;
2402 newname
= original_case_string
;
2403 namelen
= strlen (newname
);
2406 namebuf
= (char *) alloca (namelen
+ 1);
2407 strncpy (namebuf
, newname
, namelen
);
2408 namebuf
[namelen
] = '\0';
2410 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2411 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2413 /* Insert name in all uppercase. */
2414 for (p
= namebuf
; *p
; p
++)
2417 if (strncmp (namebuf
, newname
, namelen
))
2418 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2419 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2421 /* Insert name in all lowercase. */
2422 for (p
= namebuf
; *p
; p
++)
2425 if (strncmp (namebuf
, newname
, namelen
))
2426 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2427 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2432 /* Should never be called, as .req goes between the alias and the
2433 register name, not at the beginning of the line. */
2436 s_req (int a ATTRIBUTE_UNUSED
)
2438 as_bad (_("invalid syntax for .req directive"));
2442 s_dn (int a ATTRIBUTE_UNUSED
)
2444 as_bad (_("invalid syntax for .dn directive"));
2448 s_qn (int a ATTRIBUTE_UNUSED
)
2450 as_bad (_("invalid syntax for .qn directive"));
2453 /* The .unreq directive deletes an alias which was previously defined
2454 by .req. For example:
2460 s_unreq (int a ATTRIBUTE_UNUSED
)
2465 name
= input_line_pointer
;
2467 while (*input_line_pointer
!= 0
2468 && *input_line_pointer
!= ' '
2469 && *input_line_pointer
!= '\n')
2470 ++input_line_pointer
;
2472 saved_char
= *input_line_pointer
;
2473 *input_line_pointer
= 0;
2476 as_bad (_("invalid syntax for .unreq directive"));
2479 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2483 as_bad (_("unknown register alias '%s'"), name
);
2484 else if (reg
->builtin
)
2485 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2492 hash_delete (arm_reg_hsh
, name
, FALSE
);
2493 free ((char *) reg
->name
);
2498 /* Also locate the all upper case and all lower case versions.
2499 Do not complain if we cannot find one or the other as it
2500 was probably deleted above. */
2502 nbuf
= strdup (name
);
2503 for (p
= nbuf
; *p
; p
++)
2505 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2508 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2509 free ((char *) reg
->name
);
2515 for (p
= nbuf
; *p
; p
++)
2517 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2520 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2521 free ((char *) reg
->name
);
2531 *input_line_pointer
= saved_char
;
2532 demand_empty_rest_of_line ();
2535 /* Directives: Instruction set selection. */
2538 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2539 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2540 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2541 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2543 /* Create a new mapping symbol for the transition to STATE. */
2546 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2549 const char * symname
;
2556 type
= BSF_NO_FLAGS
;
2560 type
= BSF_NO_FLAGS
;
2564 type
= BSF_NO_FLAGS
;
2570 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2571 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2576 THUMB_SET_FUNC (symbolP
, 0);
2577 ARM_SET_THUMB (symbolP
, 0);
2578 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2582 THUMB_SET_FUNC (symbolP
, 1);
2583 ARM_SET_THUMB (symbolP
, 1);
2584 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2592 /* Save the mapping symbols for future reference. Also check that
2593 we do not place two mapping symbols at the same offset within a
2594 frag. We'll handle overlap between frags in
2595 check_mapping_symbols.
2597 If .fill or other data filling directive generates zero sized data,
2598 the mapping symbol for the following code will have the same value
2599 as the one generated for the data filling directive. In this case,
2600 we replace the old symbol with the new one at the same address. */
2603 if (frag
->tc_frag_data
.first_map
!= NULL
)
2605 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2606 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2608 frag
->tc_frag_data
.first_map
= symbolP
;
2610 if (frag
->tc_frag_data
.last_map
!= NULL
)
2612 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2613 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2614 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2616 frag
->tc_frag_data
.last_map
= symbolP
;
2619 /* We must sometimes convert a region marked as code to data during
2620 code alignment, if an odd number of bytes have to be padded. The
2621 code mapping symbol is pushed to an aligned address. */
2624 insert_data_mapping_symbol (enum mstate state
,
2625 valueT value
, fragS
*frag
, offsetT bytes
)
2627 /* If there was already a mapping symbol, remove it. */
2628 if (frag
->tc_frag_data
.last_map
!= NULL
2629 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2631 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2635 know (frag
->tc_frag_data
.first_map
== symp
);
2636 frag
->tc_frag_data
.first_map
= NULL
;
2638 frag
->tc_frag_data
.last_map
= NULL
;
2639 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2642 make_mapping_symbol (MAP_DATA
, value
, frag
);
2643 make_mapping_symbol (state
, value
+ bytes
, frag
);
2646 static void mapping_state_2 (enum mstate state
, int max_chars
);
2648 /* Set the mapping state to STATE. Only call this when about to
2649 emit some STATE bytes to the file. */
2651 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2653 mapping_state (enum mstate state
)
2655 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2657 if (mapstate
== state
)
2658 /* The mapping symbol has already been emitted.
2659 There is nothing else to do. */
2662 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2664 All ARM instructions require 4-byte alignment.
2665 (Almost) all Thumb instructions require 2-byte alignment.
2667 When emitting instructions into any section, mark the section
2670 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2671 but themselves require 2-byte alignment; this applies to some
2672 PC- relative forms. However, these cases will invovle implicit
2673 literal pool generation or an explicit .align >=2, both of
2674 which will cause the section to me marked with sufficient
2675 alignment. Thus, we don't handle those cases here. */
2676 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2678 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2679 /* This case will be evaluated later. */
2682 mapping_state_2 (state
, 0);
2685 /* Same as mapping_state, but MAX_CHARS bytes have already been
2686 allocated. Put the mapping symbol that far back. */
2689 mapping_state_2 (enum mstate state
, int max_chars
)
2691 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2693 if (!SEG_NORMAL (now_seg
))
2696 if (mapstate
== state
)
2697 /* The mapping symbol has already been emitted.
2698 There is nothing else to do. */
2701 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2702 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2704 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2705 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2708 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2711 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2712 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2716 #define mapping_state(x) ((void)0)
2717 #define mapping_state_2(x, y) ((void)0)
2720 /* Find the real, Thumb encoded start of a Thumb function. */
2724 find_real_start (symbolS
* symbolP
)
2727 const char * name
= S_GET_NAME (symbolP
);
2728 symbolS
* new_target
;
2730 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2731 #define STUB_NAME ".real_start_of"
2736 /* The compiler may generate BL instructions to local labels because
2737 it needs to perform a branch to a far away location. These labels
2738 do not have a corresponding ".real_start_of" label. We check
2739 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2740 the ".real_start_of" convention for nonlocal branches. */
2741 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2744 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2745 new_target
= symbol_find (real_start
);
2747 if (new_target
== NULL
)
2749 as_warn (_("Failed to find real start of function: %s\n"), name
);
2750 new_target
= symbolP
;
2758 opcode_select (int width
)
2765 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2766 as_bad (_("selected processor does not support THUMB opcodes"));
2769 /* No need to force the alignment, since we will have been
2770 coming from ARM mode, which is word-aligned. */
2771 record_alignment (now_seg
, 1);
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2779 as_bad (_("selected processor does not support ARM opcodes"));
2784 frag_align (2, 0, 0);
2786 record_alignment (now_seg
, 1);
2791 as_bad (_("invalid instruction size selected (%d)"), width
);
2796 s_arm (int ignore ATTRIBUTE_UNUSED
)
2799 demand_empty_rest_of_line ();
2803 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2806 demand_empty_rest_of_line ();
2810 s_code (int unused ATTRIBUTE_UNUSED
)
2814 temp
= get_absolute_expression ();
2819 opcode_select (temp
);
2823 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2828 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2830 /* If we are not already in thumb mode go into it, EVEN if
2831 the target processor does not support thumb instructions.
2832 This is used by gcc/config/arm/lib1funcs.asm for example
2833 to compile interworking support functions even if the
2834 target processor should not support interworking. */
2838 record_alignment (now_seg
, 1);
2841 demand_empty_rest_of_line ();
2845 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2849 /* The following label is the name/address of the start of a Thumb function.
2850 We need to know this for the interworking support. */
2851 label_is_thumb_function_name
= TRUE
;
2854 /* Perform a .set directive, but also mark the alias as
2855 being a thumb function. */
2858 s_thumb_set (int equiv
)
2860 /* XXX the following is a duplicate of the code for s_set() in read.c
2861 We cannot just call that code as we need to get at the symbol that
2868 /* Especial apologies for the random logic:
2869 This just grew, and could be parsed much more simply!
2871 delim
= get_symbol_name (& name
);
2872 end_name
= input_line_pointer
;
2873 (void) restore_line_pointer (delim
);
2875 if (*input_line_pointer
!= ',')
2878 as_bad (_("expected comma after name \"%s\""), name
);
2880 ignore_rest_of_line ();
2884 input_line_pointer
++;
2887 if (name
[0] == '.' && name
[1] == '\0')
2889 /* XXX - this should not happen to .thumb_set. */
2893 if ((symbolP
= symbol_find (name
)) == NULL
2894 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2897 /* When doing symbol listings, play games with dummy fragments living
2898 outside the normal fragment chain to record the file and line info
2900 if (listing
& LISTING_SYMBOLS
)
2902 extern struct list_info_struct
* listing_tail
;
2903 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2905 memset (dummy_frag
, 0, sizeof (fragS
));
2906 dummy_frag
->fr_type
= rs_fill
;
2907 dummy_frag
->line
= listing_tail
;
2908 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2909 dummy_frag
->fr_symbol
= symbolP
;
2913 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2916 /* "set" symbols are local unless otherwise specified. */
2917 SF_SET_LOCAL (symbolP
);
2918 #endif /* OBJ_COFF */
2919 } /* Make a new symbol. */
2921 symbol_table_insert (symbolP
);
2926 && S_IS_DEFINED (symbolP
)
2927 && S_GET_SEGMENT (symbolP
) != reg_section
)
2928 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2930 pseudo_set (symbolP
);
2932 demand_empty_rest_of_line ();
2934 /* XXX Now we come to the Thumb specific bit of code. */
2936 THUMB_SET_FUNC (symbolP
, 1);
2937 ARM_SET_THUMB (symbolP
, 1);
2938 #if defined OBJ_ELF || defined OBJ_COFF
2939 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2943 /* Directives: Mode selection. */
2945 /* .syntax [unified|divided] - choose the new unified syntax
2946 (same for Arm and Thumb encoding, modulo slight differences in what
2947 can be represented) or the old divergent syntax for each mode. */
2949 s_syntax (int unused ATTRIBUTE_UNUSED
)
2953 delim
= get_symbol_name (& name
);
2955 if (!strcasecmp (name
, "unified"))
2956 unified_syntax
= TRUE
;
2957 else if (!strcasecmp (name
, "divided"))
2958 unified_syntax
= FALSE
;
2961 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2964 (void) restore_line_pointer (delim
);
2965 demand_empty_rest_of_line ();
2968 /* Directives: sectioning and alignment. */
2971 s_bss (int ignore ATTRIBUTE_UNUSED
)
2973 /* We don't support putting frags in the BSS segment, we fake it by
2974 marking in_bss, then looking at s_skip for clues. */
2975 subseg_set (bss_section
, 0);
2976 demand_empty_rest_of_line ();
2978 #ifdef md_elf_section_change_hook
2979 md_elf_section_change_hook ();
2984 s_even (int ignore ATTRIBUTE_UNUSED
)
2986 /* Never make frag if expect extra pass. */
2988 frag_align (1, 0, 0);
2990 record_alignment (now_seg
, 1);
2992 demand_empty_rest_of_line ();
2995 /* Directives: CodeComposer Studio. */
2997 /* .ref (for CodeComposer Studio syntax only). */
2999 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3001 if (codecomposer_syntax
)
3002 ignore_rest_of_line ();
3004 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3007 /* If name is not NULL, then it is used for marking the beginning of a
3008 function, wherease if it is NULL then it means the function end. */
3010 asmfunc_debug (const char * name
)
3012 static const char * last_name
= NULL
;
3016 gas_assert (last_name
== NULL
);
3019 if (debug_type
== DEBUG_STABS
)
3020 stabs_generate_asm_func (name
, name
);
3024 gas_assert (last_name
!= NULL
);
3026 if (debug_type
== DEBUG_STABS
)
3027 stabs_generate_asm_endfunc (last_name
, last_name
);
3034 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3036 if (codecomposer_syntax
)
3038 switch (asmfunc_state
)
3040 case OUTSIDE_ASMFUNC
:
3041 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3044 case WAITING_ASMFUNC_NAME
:
3045 as_bad (_(".asmfunc repeated."));
3048 case WAITING_ENDASMFUNC
:
3049 as_bad (_(".asmfunc without function."));
3052 demand_empty_rest_of_line ();
3055 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3059 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3061 if (codecomposer_syntax
)
3063 switch (asmfunc_state
)
3065 case OUTSIDE_ASMFUNC
:
3066 as_bad (_(".endasmfunc without a .asmfunc."));
3069 case WAITING_ASMFUNC_NAME
:
3070 as_bad (_(".endasmfunc without function."));
3073 case WAITING_ENDASMFUNC
:
3074 asmfunc_state
= OUTSIDE_ASMFUNC
;
3075 asmfunc_debug (NULL
);
3078 demand_empty_rest_of_line ();
3081 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3085 s_ccs_def (int name
)
3087 if (codecomposer_syntax
)
3090 as_bad (_(".def pseudo-op only available with -mccs flag."));
3093 /* Directives: Literal pools. */
3095 static literal_pool
*
3096 find_literal_pool (void)
3098 literal_pool
* pool
;
3100 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3102 if (pool
->section
== now_seg
3103 && pool
->sub_section
== now_subseg
)
3110 static literal_pool
*
3111 find_or_make_literal_pool (void)
3113 /* Next literal pool ID number. */
3114 static unsigned int latest_pool_num
= 1;
3115 literal_pool
* pool
;
3117 pool
= find_literal_pool ();
3121 /* Create a new pool. */
3122 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3126 pool
->next_free_entry
= 0;
3127 pool
->section
= now_seg
;
3128 pool
->sub_section
= now_subseg
;
3129 pool
->next
= list_of_pools
;
3130 pool
->symbol
= NULL
;
3131 pool
->alignment
= 2;
3133 /* Add it to the list. */
3134 list_of_pools
= pool
;
3137 /* New pools, and emptied pools, will have a NULL symbol. */
3138 if (pool
->symbol
== NULL
)
3140 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3141 (valueT
) 0, &zero_address_frag
);
3142 pool
->id
= latest_pool_num
++;
3149 /* Add the literal in the global 'inst'
3150 structure to the relevant literal pool. */
3153 add_to_lit_pool (unsigned int nbytes
)
3155 #define PADDING_SLOT 0x1
3156 #define LIT_ENTRY_SIZE_MASK 0xFF
3157 literal_pool
* pool
;
3158 unsigned int entry
, pool_size
= 0;
3159 bfd_boolean padding_slot_p
= FALSE
;
3165 imm1
= inst
.operands
[1].imm
;
3166 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3167 : inst
.reloc
.exp
.X_unsigned
? 0
3168 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3169 if (target_big_endian
)
3172 imm2
= inst
.operands
[1].imm
;
3176 pool
= find_or_make_literal_pool ();
3178 /* Check if this literal value is already in the pool. */
3179 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3183 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3184 && (inst
.reloc
.exp
.X_op
== O_constant
)
3185 && (pool
->literals
[entry
].X_add_number
3186 == inst
.reloc
.exp
.X_add_number
)
3187 && (pool
->literals
[entry
].X_md
== nbytes
)
3188 && (pool
->literals
[entry
].X_unsigned
3189 == inst
.reloc
.exp
.X_unsigned
))
3192 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3193 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3194 && (pool
->literals
[entry
].X_add_number
3195 == inst
.reloc
.exp
.X_add_number
)
3196 && (pool
->literals
[entry
].X_add_symbol
3197 == inst
.reloc
.exp
.X_add_symbol
)
3198 && (pool
->literals
[entry
].X_op_symbol
3199 == inst
.reloc
.exp
.X_op_symbol
)
3200 && (pool
->literals
[entry
].X_md
== nbytes
))
3203 else if ((nbytes
== 8)
3204 && !(pool_size
& 0x7)
3205 && ((entry
+ 1) != pool
->next_free_entry
)
3206 && (pool
->literals
[entry
].X_op
== O_constant
)
3207 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3208 && (pool
->literals
[entry
].X_unsigned
3209 == inst
.reloc
.exp
.X_unsigned
)
3210 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3211 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3212 && (pool
->literals
[entry
+ 1].X_unsigned
3213 == inst
.reloc
.exp
.X_unsigned
))
3216 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3217 if (padding_slot_p
&& (nbytes
== 4))
3223 /* Do we need to create a new entry? */
3224 if (entry
== pool
->next_free_entry
)
3226 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3228 inst
.error
= _("literal pool overflow");
3234 /* For 8-byte entries, we align to an 8-byte boundary,
3235 and split it into two 4-byte entries, because on 32-bit
3236 host, 8-byte constants are treated as big num, thus
3237 saved in "generic_bignum" which will be overwritten
3238 by later assignments.
3240 We also need to make sure there is enough space for
3243 We also check to make sure the literal operand is a
3245 if (!(inst
.reloc
.exp
.X_op
== O_constant
3246 || inst
.reloc
.exp
.X_op
== O_big
))
3248 inst
.error
= _("invalid type for literal pool");
3251 else if (pool_size
& 0x7)
3253 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3255 inst
.error
= _("literal pool overflow");
3259 pool
->literals
[entry
] = inst
.reloc
.exp
;
3260 pool
->literals
[entry
].X_add_number
= 0;
3261 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3262 pool
->next_free_entry
+= 1;
3265 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3267 inst
.error
= _("literal pool overflow");
3271 pool
->literals
[entry
] = inst
.reloc
.exp
;
3272 pool
->literals
[entry
].X_op
= O_constant
;
3273 pool
->literals
[entry
].X_add_number
= imm1
;
3274 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3275 pool
->literals
[entry
++].X_md
= 4;
3276 pool
->literals
[entry
] = inst
.reloc
.exp
;
3277 pool
->literals
[entry
].X_op
= O_constant
;
3278 pool
->literals
[entry
].X_add_number
= imm2
;
3279 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3280 pool
->literals
[entry
].X_md
= 4;
3281 pool
->alignment
= 3;
3282 pool
->next_free_entry
+= 1;
3286 pool
->literals
[entry
] = inst
.reloc
.exp
;
3287 pool
->literals
[entry
].X_md
= 4;
3291 /* PR ld/12974: Record the location of the first source line to reference
3292 this entry in the literal pool. If it turns out during linking that the
3293 symbol does not exist we will be able to give an accurate line number for
3294 the (first use of the) missing reference. */
3295 if (debug_type
== DEBUG_DWARF2
)
3296 dwarf2_where (pool
->locs
+ entry
);
3298 pool
->next_free_entry
+= 1;
3300 else if (padding_slot_p
)
3302 pool
->literals
[entry
] = inst
.reloc
.exp
;
3303 pool
->literals
[entry
].X_md
= nbytes
;
3306 inst
.reloc
.exp
.X_op
= O_symbol
;
3307 inst
.reloc
.exp
.X_add_number
= pool_size
;
3308 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3314 tc_start_label_without_colon (void)
3316 bfd_boolean ret
= TRUE
;
3318 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3320 const char *label
= input_line_pointer
;
3322 while (!is_end_of_line
[(int) label
[-1]])
3327 as_bad (_("Invalid label '%s'"), label
);
3331 asmfunc_debug (label
);
3333 asmfunc_state
= WAITING_ENDASMFUNC
;
3339 /* Can't use symbol_new here, so have to create a symbol and then at
3340 a later date assign it a value. Thats what these functions do. */
3343 symbol_locate (symbolS
* symbolP
,
3344 const char * name
, /* It is copied, the caller can modify. */
3345 segT segment
, /* Segment identifier (SEG_<something>). */
3346 valueT valu
, /* Symbol value. */
3347 fragS
* frag
) /* Associated fragment. */
3350 char * preserved_copy_of_name
;
3352 name_length
= strlen (name
) + 1; /* +1 for \0. */
3353 obstack_grow (¬es
, name
, name_length
);
3354 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3356 #ifdef tc_canonicalize_symbol_name
3357 preserved_copy_of_name
=
3358 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3361 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3363 S_SET_SEGMENT (symbolP
, segment
);
3364 S_SET_VALUE (symbolP
, valu
);
3365 symbol_clear_list_pointers (symbolP
);
3367 symbol_set_frag (symbolP
, frag
);
3369 /* Link to end of symbol chain. */
3371 extern int symbol_table_frozen
;
3373 if (symbol_table_frozen
)
3377 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3379 obj_symbol_new_hook (symbolP
);
3381 #ifdef tc_symbol_new_hook
3382 tc_symbol_new_hook (symbolP
);
3386 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3387 #endif /* DEBUG_SYMS */
3391 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3394 literal_pool
* pool
;
3397 pool
= find_literal_pool ();
3399 || pool
->symbol
== NULL
3400 || pool
->next_free_entry
== 0)
3403 /* Align pool as you have word accesses.
3404 Only make a frag if we have to. */
3406 frag_align (pool
->alignment
, 0, 0);
3408 record_alignment (now_seg
, 2);
3411 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3412 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3414 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3416 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3417 (valueT
) frag_now_fix (), frag_now
);
3418 symbol_table_insert (pool
->symbol
);
3420 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3422 #if defined OBJ_COFF || defined OBJ_ELF
3423 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3426 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3429 if (debug_type
== DEBUG_DWARF2
)
3430 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3432 /* First output the expression in the instruction to the pool. */
3433 emit_expr (&(pool
->literals
[entry
]),
3434 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3437 /* Mark the pool as empty. */
3438 pool
->next_free_entry
= 0;
3439 pool
->symbol
= NULL
;
3443 /* Forward declarations for functions below, in the MD interface
3445 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3446 static valueT
create_unwind_entry (int);
3447 static void start_unwind_section (const segT
, int);
3448 static void add_unwind_opcode (valueT
, int);
3449 static void flush_pending_unwind (void);
3451 /* Directives: Data. */
3454 s_arm_elf_cons (int nbytes
)
3458 #ifdef md_flush_pending_output
3459 md_flush_pending_output ();
3462 if (is_it_end_of_statement ())
3464 demand_empty_rest_of_line ();
3468 #ifdef md_cons_align
3469 md_cons_align (nbytes
);
3472 mapping_state (MAP_DATA
);
3476 char *base
= input_line_pointer
;
3480 if (exp
.X_op
!= O_symbol
)
3481 emit_expr (&exp
, (unsigned int) nbytes
);
3484 char *before_reloc
= input_line_pointer
;
3485 reloc
= parse_reloc (&input_line_pointer
);
3488 as_bad (_("unrecognized relocation suffix"));
3489 ignore_rest_of_line ();
3492 else if (reloc
== BFD_RELOC_UNUSED
)
3493 emit_expr (&exp
, (unsigned int) nbytes
);
3496 reloc_howto_type
*howto
= (reloc_howto_type
*)
3497 bfd_reloc_type_lookup (stdoutput
,
3498 (bfd_reloc_code_real_type
) reloc
);
3499 int size
= bfd_get_reloc_size (howto
);
3501 if (reloc
== BFD_RELOC_ARM_PLT32
)
3503 as_bad (_("(plt) is only valid on branch targets"));
3504 reloc
= BFD_RELOC_UNUSED
;
3509 as_bad (_("%s relocations do not fit in %d bytes"),
3510 howto
->name
, nbytes
);
3513 /* We've parsed an expression stopping at O_symbol.
3514 But there may be more expression left now that we
3515 have parsed the relocation marker. Parse it again.
3516 XXX Surely there is a cleaner way to do this. */
3517 char *p
= input_line_pointer
;
3519 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3520 memcpy (save_buf
, base
, input_line_pointer
- base
);
3521 memmove (base
+ (input_line_pointer
- before_reloc
),
3522 base
, before_reloc
- base
);
3524 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3526 memcpy (base
, save_buf
, p
- base
);
3528 offset
= nbytes
- size
;
3529 p
= frag_more (nbytes
);
3530 memset (p
, 0, nbytes
);
3531 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3532 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3537 while (*input_line_pointer
++ == ',');
3539 /* Put terminator back into stream. */
3540 input_line_pointer
--;
3541 demand_empty_rest_of_line ();
3544 /* Emit an expression containing a 32-bit thumb instruction.
3545 Implementation based on put_thumb32_insn. */
3548 emit_thumb32_expr (expressionS
* exp
)
3550 expressionS exp_high
= *exp
;
3552 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3553 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3554 exp
->X_add_number
&= 0xffff;
3555 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3558 /* Guess the instruction size based on the opcode. */
3561 thumb_insn_size (int opcode
)
3563 if ((unsigned int) opcode
< 0xe800u
)
3565 else if ((unsigned int) opcode
>= 0xe8000000u
)
3572 emit_insn (expressionS
*exp
, int nbytes
)
3576 if (exp
->X_op
== O_constant
)
3581 size
= thumb_insn_size (exp
->X_add_number
);
3585 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3587 as_bad (_(".inst.n operand too big. "\
3588 "Use .inst.w instead"));
3593 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3594 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3596 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3598 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3599 emit_thumb32_expr (exp
);
3601 emit_expr (exp
, (unsigned int) size
);
3603 it_fsm_post_encode ();
3607 as_bad (_("cannot determine Thumb instruction size. " \
3608 "Use .inst.n/.inst.w instead"));
3611 as_bad (_("constant expression required"));
3616 /* Like s_arm_elf_cons but do not use md_cons_align and
3617 set the mapping state to MAP_ARM/MAP_THUMB. */
3620 s_arm_elf_inst (int nbytes
)
3622 if (is_it_end_of_statement ())
3624 demand_empty_rest_of_line ();
3628 /* Calling mapping_state () here will not change ARM/THUMB,
3629 but will ensure not to be in DATA state. */
3632 mapping_state (MAP_THUMB
);
3637 as_bad (_("width suffixes are invalid in ARM mode"));
3638 ignore_rest_of_line ();
3644 mapping_state (MAP_ARM
);
3653 if (! emit_insn (& exp
, nbytes
))
3655 ignore_rest_of_line ();
3659 while (*input_line_pointer
++ == ',');
3661 /* Put terminator back into stream. */
3662 input_line_pointer
--;
3663 demand_empty_rest_of_line ();
3666 /* Parse a .rel31 directive. */
3669 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3676 if (*input_line_pointer
== '1')
3677 highbit
= 0x80000000;
3678 else if (*input_line_pointer
!= '0')
3679 as_bad (_("expected 0 or 1"));
3681 input_line_pointer
++;
3682 if (*input_line_pointer
!= ',')
3683 as_bad (_("missing comma"));
3684 input_line_pointer
++;
3686 #ifdef md_flush_pending_output
3687 md_flush_pending_output ();
3690 #ifdef md_cons_align
3694 mapping_state (MAP_DATA
);
3699 md_number_to_chars (p
, highbit
, 4);
3700 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3701 BFD_RELOC_ARM_PREL31
);
3703 demand_empty_rest_of_line ();
3706 /* Directives: AEABI stack-unwind tables. */
3708 /* Parse an unwind_fnstart directive. Simply records the current location. */
3711 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3713 demand_empty_rest_of_line ();
3714 if (unwind
.proc_start
)
3716 as_bad (_("duplicate .fnstart directive"));
3720 /* Mark the start of the function. */
3721 unwind
.proc_start
= expr_build_dot ();
3723 /* Reset the rest of the unwind info. */
3724 unwind
.opcode_count
= 0;
3725 unwind
.table_entry
= NULL
;
3726 unwind
.personality_routine
= NULL
;
3727 unwind
.personality_index
= -1;
3728 unwind
.frame_size
= 0;
3729 unwind
.fp_offset
= 0;
3730 unwind
.fp_reg
= REG_SP
;
3732 unwind
.sp_restored
= 0;
3736 /* Parse a handlerdata directive. Creates the exception handling table entry
3737 for the function. */
3740 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3742 demand_empty_rest_of_line ();
3743 if (!unwind
.proc_start
)
3744 as_bad (MISSING_FNSTART
);
3746 if (unwind
.table_entry
)
3747 as_bad (_("duplicate .handlerdata directive"));
3749 create_unwind_entry (1);
3752 /* Parse an unwind_fnend directive. Generates the index table entry. */
3755 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3760 unsigned int marked_pr_dependency
;
3762 demand_empty_rest_of_line ();
3764 if (!unwind
.proc_start
)
3766 as_bad (_(".fnend directive without .fnstart"));
3770 /* Add eh table entry. */
3771 if (unwind
.table_entry
== NULL
)
3772 val
= create_unwind_entry (0);
3776 /* Add index table entry. This is two words. */
3777 start_unwind_section (unwind
.saved_seg
, 1);
3778 frag_align (2, 0, 0);
3779 record_alignment (now_seg
, 2);
3781 ptr
= frag_more (8);
3783 where
= frag_now_fix () - 8;
3785 /* Self relative offset of the function start. */
3786 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3787 BFD_RELOC_ARM_PREL31
);
3789 /* Indicate dependency on EHABI-defined personality routines to the
3790 linker, if it hasn't been done already. */
3791 marked_pr_dependency
3792 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3793 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3794 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3796 static const char *const name
[] =
3798 "__aeabi_unwind_cpp_pr0",
3799 "__aeabi_unwind_cpp_pr1",
3800 "__aeabi_unwind_cpp_pr2"
3802 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3803 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3804 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3805 |= 1 << unwind
.personality_index
;
3809 /* Inline exception table entry. */
3810 md_number_to_chars (ptr
+ 4, val
, 4);
3812 /* Self relative offset of the table entry. */
3813 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3814 BFD_RELOC_ARM_PREL31
);
3816 /* Restore the original section. */
3817 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3819 unwind
.proc_start
= NULL
;
3823 /* Parse an unwind_cantunwind directive. */
3826 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3828 demand_empty_rest_of_line ();
3829 if (!unwind
.proc_start
)
3830 as_bad (MISSING_FNSTART
);
3832 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3833 as_bad (_("personality routine specified for cantunwind frame"));
3835 unwind
.personality_index
= -2;
3839 /* Parse a personalityindex directive. */
3842 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3846 if (!unwind
.proc_start
)
3847 as_bad (MISSING_FNSTART
);
3849 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3850 as_bad (_("duplicate .personalityindex directive"));
3854 if (exp
.X_op
!= O_constant
3855 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3857 as_bad (_("bad personality routine number"));
3858 ignore_rest_of_line ();
3862 unwind
.personality_index
= exp
.X_add_number
;
3864 demand_empty_rest_of_line ();
3868 /* Parse a personality directive. */
3871 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3875 if (!unwind
.proc_start
)
3876 as_bad (MISSING_FNSTART
);
3878 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3879 as_bad (_("duplicate .personality directive"));
3881 c
= get_symbol_name (& name
);
3882 p
= input_line_pointer
;
3884 ++ input_line_pointer
;
3885 unwind
.personality_routine
= symbol_find_or_make (name
);
3887 demand_empty_rest_of_line ();
3891 /* Parse a directive saving core registers. */
3894 s_arm_unwind_save_core (void)
3900 range
= parse_reg_list (&input_line_pointer
);
3903 as_bad (_("expected register list"));
3904 ignore_rest_of_line ();
3908 demand_empty_rest_of_line ();
3910 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3911 into .unwind_save {..., sp...}. We aren't bothered about the value of
3912 ip because it is clobbered by calls. */
3913 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3914 && (range
& 0x3000) == 0x1000)
3916 unwind
.opcode_count
--;
3917 unwind
.sp_restored
= 0;
3918 range
= (range
| 0x2000) & ~0x1000;
3919 unwind
.pending_offset
= 0;
3925 /* See if we can use the short opcodes. These pop a block of up to 8
3926 registers starting with r4, plus maybe r14. */
3927 for (n
= 0; n
< 8; n
++)
3929 /* Break at the first non-saved register. */
3930 if ((range
& (1 << (n
+ 4))) == 0)
3933 /* See if there are any other bits set. */
3934 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3936 /* Use the long form. */
3937 op
= 0x8000 | ((range
>> 4) & 0xfff);
3938 add_unwind_opcode (op
, 2);
3942 /* Use the short form. */
3944 op
= 0xa8; /* Pop r14. */
3946 op
= 0xa0; /* Do not pop r14. */
3948 add_unwind_opcode (op
, 1);
3955 op
= 0xb100 | (range
& 0xf);
3956 add_unwind_opcode (op
, 2);
3959 /* Record the number of bytes pushed. */
3960 for (n
= 0; n
< 16; n
++)
3962 if (range
& (1 << n
))
3963 unwind
.frame_size
+= 4;
3968 /* Parse a directive saving FPA registers. */
3971 s_arm_unwind_save_fpa (int reg
)
3977 /* Get Number of registers to transfer. */
3978 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3981 exp
.X_op
= O_illegal
;
3983 if (exp
.X_op
!= O_constant
)
3985 as_bad (_("expected , <constant>"));
3986 ignore_rest_of_line ();
3990 num_regs
= exp
.X_add_number
;
3992 if (num_regs
< 1 || num_regs
> 4)
3994 as_bad (_("number of registers must be in the range [1:4]"));
3995 ignore_rest_of_line ();
3999 demand_empty_rest_of_line ();
4004 op
= 0xb4 | (num_regs
- 1);
4005 add_unwind_opcode (op
, 1);
4010 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4011 add_unwind_opcode (op
, 2);
4013 unwind
.frame_size
+= num_regs
* 12;
4017 /* Parse a directive saving VFP registers for ARMv6 and above. */
4020 s_arm_unwind_save_vfp_armv6 (void)
4025 int num_vfpv3_regs
= 0;
4026 int num_regs_below_16
;
4028 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4031 as_bad (_("expected register list"));
4032 ignore_rest_of_line ();
4036 demand_empty_rest_of_line ();
4038 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4039 than FSTMX/FLDMX-style ones). */
4041 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4043 num_vfpv3_regs
= count
;
4044 else if (start
+ count
> 16)
4045 num_vfpv3_regs
= start
+ count
- 16;
4047 if (num_vfpv3_regs
> 0)
4049 int start_offset
= start
> 16 ? start
- 16 : 0;
4050 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4051 add_unwind_opcode (op
, 2);
4054 /* Generate opcode for registers numbered in the range 0 .. 15. */
4055 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4056 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4057 if (num_regs_below_16
> 0)
4059 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4060 add_unwind_opcode (op
, 2);
4063 unwind
.frame_size
+= count
* 8;
4067 /* Parse a directive saving VFP registers for pre-ARMv6. */
4070 s_arm_unwind_save_vfp (void)
4076 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4079 as_bad (_("expected register list"));
4080 ignore_rest_of_line ();
4084 demand_empty_rest_of_line ();
4089 op
= 0xb8 | (count
- 1);
4090 add_unwind_opcode (op
, 1);
4095 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4096 add_unwind_opcode (op
, 2);
4098 unwind
.frame_size
+= count
* 8 + 4;
4102 /* Parse a directive saving iWMMXt data registers. */
4105 s_arm_unwind_save_mmxwr (void)
4113 if (*input_line_pointer
== '{')
4114 input_line_pointer
++;
4118 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4122 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4127 as_tsktsk (_("register list not in ascending order"));
4130 if (*input_line_pointer
== '-')
4132 input_line_pointer
++;
4133 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4136 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4139 else if (reg
>= hi_reg
)
4141 as_bad (_("bad register range"));
4144 for (; reg
< hi_reg
; reg
++)
4148 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4150 skip_past_char (&input_line_pointer
, '}');
4152 demand_empty_rest_of_line ();
4154 /* Generate any deferred opcodes because we're going to be looking at
4156 flush_pending_unwind ();
4158 for (i
= 0; i
< 16; i
++)
4160 if (mask
& (1 << i
))
4161 unwind
.frame_size
+= 8;
4164 /* Attempt to combine with a previous opcode. We do this because gcc
4165 likes to output separate unwind directives for a single block of
4167 if (unwind
.opcode_count
> 0)
4169 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4170 if ((i
& 0xf8) == 0xc0)
4173 /* Only merge if the blocks are contiguous. */
4176 if ((mask
& 0xfe00) == (1 << 9))
4178 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4179 unwind
.opcode_count
--;
4182 else if (i
== 6 && unwind
.opcode_count
>= 2)
4184 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4188 op
= 0xffff << (reg
- 1);
4190 && ((mask
& op
) == (1u << (reg
- 1))))
4192 op
= (1 << (reg
+ i
+ 1)) - 1;
4193 op
&= ~((1 << reg
) - 1);
4195 unwind
.opcode_count
-= 2;
4202 /* We want to generate opcodes in the order the registers have been
4203 saved, ie. descending order. */
4204 for (reg
= 15; reg
>= -1; reg
--)
4206 /* Save registers in blocks. */
4208 || !(mask
& (1 << reg
)))
4210 /* We found an unsaved reg. Generate opcodes to save the
4217 op
= 0xc0 | (hi_reg
- 10);
4218 add_unwind_opcode (op
, 1);
4223 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4224 add_unwind_opcode (op
, 2);
4233 ignore_rest_of_line ();
4237 s_arm_unwind_save_mmxwcg (void)
4244 if (*input_line_pointer
== '{')
4245 input_line_pointer
++;
4247 skip_whitespace (input_line_pointer
);
4251 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4255 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4261 as_tsktsk (_("register list not in ascending order"));
4264 if (*input_line_pointer
== '-')
4266 input_line_pointer
++;
4267 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4270 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4273 else if (reg
>= hi_reg
)
4275 as_bad (_("bad register range"));
4278 for (; reg
< hi_reg
; reg
++)
4282 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4284 skip_past_char (&input_line_pointer
, '}');
4286 demand_empty_rest_of_line ();
4288 /* Generate any deferred opcodes because we're going to be looking at
4290 flush_pending_unwind ();
4292 for (reg
= 0; reg
< 16; reg
++)
4294 if (mask
& (1 << reg
))
4295 unwind
.frame_size
+= 4;
4298 add_unwind_opcode (op
, 2);
4301 ignore_rest_of_line ();
4305 /* Parse an unwind_save directive.
4306 If the argument is non-zero, this is a .vsave directive. */
4309 s_arm_unwind_save (int arch_v6
)
4312 struct reg_entry
*reg
;
4313 bfd_boolean had_brace
= FALSE
;
4315 if (!unwind
.proc_start
)
4316 as_bad (MISSING_FNSTART
);
4318 /* Figure out what sort of save we have. */
4319 peek
= input_line_pointer
;
4327 reg
= arm_reg_parse_multi (&peek
);
4331 as_bad (_("register expected"));
4332 ignore_rest_of_line ();
4341 as_bad (_("FPA .unwind_save does not take a register list"));
4342 ignore_rest_of_line ();
4345 input_line_pointer
= peek
;
4346 s_arm_unwind_save_fpa (reg
->number
);
4350 s_arm_unwind_save_core ();
4355 s_arm_unwind_save_vfp_armv6 ();
4357 s_arm_unwind_save_vfp ();
4360 case REG_TYPE_MMXWR
:
4361 s_arm_unwind_save_mmxwr ();
4364 case REG_TYPE_MMXWCG
:
4365 s_arm_unwind_save_mmxwcg ();
4369 as_bad (_(".unwind_save does not support this kind of register"));
4370 ignore_rest_of_line ();
4375 /* Parse an unwind_movsp directive. */
4378 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4384 if (!unwind
.proc_start
)
4385 as_bad (MISSING_FNSTART
);
4387 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4390 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4391 ignore_rest_of_line ();
4395 /* Optional constant. */
4396 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4398 if (immediate_for_directive (&offset
) == FAIL
)
4404 demand_empty_rest_of_line ();
4406 if (reg
== REG_SP
|| reg
== REG_PC
)
4408 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4412 if (unwind
.fp_reg
!= REG_SP
)
4413 as_bad (_("unexpected .unwind_movsp directive"));
4415 /* Generate opcode to restore the value. */
4417 add_unwind_opcode (op
, 1);
4419 /* Record the information for later. */
4420 unwind
.fp_reg
= reg
;
4421 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4422 unwind
.sp_restored
= 1;
4425 /* Parse an unwind_pad directive. */
4428 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4432 if (!unwind
.proc_start
)
4433 as_bad (MISSING_FNSTART
);
4435 if (immediate_for_directive (&offset
) == FAIL
)
4440 as_bad (_("stack increment must be multiple of 4"));
4441 ignore_rest_of_line ();
4445 /* Don't generate any opcodes, just record the details for later. */
4446 unwind
.frame_size
+= offset
;
4447 unwind
.pending_offset
+= offset
;
4449 demand_empty_rest_of_line ();
4452 /* Parse an unwind_setfp directive. */
4455 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4461 if (!unwind
.proc_start
)
4462 as_bad (MISSING_FNSTART
);
4464 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4465 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4468 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4470 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4472 as_bad (_("expected <reg>, <reg>"));
4473 ignore_rest_of_line ();
4477 /* Optional constant. */
4478 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4480 if (immediate_for_directive (&offset
) == FAIL
)
4486 demand_empty_rest_of_line ();
4488 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4490 as_bad (_("register must be either sp or set by a previous"
4491 "unwind_movsp directive"));
4495 /* Don't generate any opcodes, just record the information for later. */
4496 unwind
.fp_reg
= fp_reg
;
4498 if (sp_reg
== REG_SP
)
4499 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4501 unwind
.fp_offset
-= offset
;
4504 /* Parse an unwind_raw directive. */
4507 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4510 /* This is an arbitrary limit. */
4511 unsigned char op
[16];
4514 if (!unwind
.proc_start
)
4515 as_bad (MISSING_FNSTART
);
4518 if (exp
.X_op
== O_constant
4519 && skip_past_comma (&input_line_pointer
) != FAIL
)
4521 unwind
.frame_size
+= exp
.X_add_number
;
4525 exp
.X_op
= O_illegal
;
4527 if (exp
.X_op
!= O_constant
)
4529 as_bad (_("expected <offset>, <opcode>"));
4530 ignore_rest_of_line ();
4536 /* Parse the opcode. */
4541 as_bad (_("unwind opcode too long"));
4542 ignore_rest_of_line ();
4544 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4546 as_bad (_("invalid unwind opcode"));
4547 ignore_rest_of_line ();
4550 op
[count
++] = exp
.X_add_number
;
4552 /* Parse the next byte. */
4553 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4559 /* Add the opcode bytes in reverse order. */
4561 add_unwind_opcode (op
[count
], 1);
4563 demand_empty_rest_of_line ();
4567 /* Parse a .eabi_attribute directive. */
4570 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4572 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4574 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4575 attributes_set_explicitly
[tag
] = 1;
4578 /* Emit a tls fix for the symbol. */
4581 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4585 #ifdef md_flush_pending_output
4586 md_flush_pending_output ();
4589 #ifdef md_cons_align
4593 /* Since we're just labelling the code, there's no need to define a
4596 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4597 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4598 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4599 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4601 #endif /* OBJ_ELF */
4603 static void s_arm_arch (int);
4604 static void s_arm_object_arch (int);
4605 static void s_arm_cpu (int);
4606 static void s_arm_fpu (int);
4607 static void s_arm_arch_extension (int);
4612 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4619 if (exp
.X_op
== O_symbol
)
4620 exp
.X_op
= O_secrel
;
4622 emit_expr (&exp
, 4);
4624 while (*input_line_pointer
++ == ',');
4626 input_line_pointer
--;
4627 demand_empty_rest_of_line ();
4631 /* This table describes all the machine specific pseudo-ops the assembler
4632 has to support. The fields are:
4633 pseudo-op name without dot
4634 function to call to execute this pseudo-op
4635 Integer arg to pass to the function. */
4637 const pseudo_typeS md_pseudo_table
[] =
4639 /* Never called because '.req' does not start a line. */
4640 { "req", s_req
, 0 },
4641 /* Following two are likewise never called. */
4644 { "unreq", s_unreq
, 0 },
4645 { "bss", s_bss
, 0 },
4646 { "align", s_align_ptwo
, 2 },
4647 { "arm", s_arm
, 0 },
4648 { "thumb", s_thumb
, 0 },
4649 { "code", s_code
, 0 },
4650 { "force_thumb", s_force_thumb
, 0 },
4651 { "thumb_func", s_thumb_func
, 0 },
4652 { "thumb_set", s_thumb_set
, 0 },
4653 { "even", s_even
, 0 },
4654 { "ltorg", s_ltorg
, 0 },
4655 { "pool", s_ltorg
, 0 },
4656 { "syntax", s_syntax
, 0 },
4657 { "cpu", s_arm_cpu
, 0 },
4658 { "arch", s_arm_arch
, 0 },
4659 { "object_arch", s_arm_object_arch
, 0 },
4660 { "fpu", s_arm_fpu
, 0 },
4661 { "arch_extension", s_arm_arch_extension
, 0 },
4663 { "word", s_arm_elf_cons
, 4 },
4664 { "long", s_arm_elf_cons
, 4 },
4665 { "inst.n", s_arm_elf_inst
, 2 },
4666 { "inst.w", s_arm_elf_inst
, 4 },
4667 { "inst", s_arm_elf_inst
, 0 },
4668 { "rel31", s_arm_rel31
, 0 },
4669 { "fnstart", s_arm_unwind_fnstart
, 0 },
4670 { "fnend", s_arm_unwind_fnend
, 0 },
4671 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4672 { "personality", s_arm_unwind_personality
, 0 },
4673 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4674 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4675 { "save", s_arm_unwind_save
, 0 },
4676 { "vsave", s_arm_unwind_save
, 1 },
4677 { "movsp", s_arm_unwind_movsp
, 0 },
4678 { "pad", s_arm_unwind_pad
, 0 },
4679 { "setfp", s_arm_unwind_setfp
, 0 },
4680 { "unwind_raw", s_arm_unwind_raw
, 0 },
4681 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4682 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4686 /* These are used for dwarf. */
4690 /* These are used for dwarf2. */
4691 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4692 { "loc", dwarf2_directive_loc
, 0 },
4693 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4695 { "extend", float_cons
, 'x' },
4696 { "ldouble", float_cons
, 'x' },
4697 { "packed", float_cons
, 'p' },
4699 {"secrel32", pe_directive_secrel
, 0},
4702 /* These are for compatibility with CodeComposer Studio. */
4703 {"ref", s_ccs_ref
, 0},
4704 {"def", s_ccs_def
, 0},
4705 {"asmfunc", s_ccs_asmfunc
, 0},
4706 {"endasmfunc", s_ccs_endasmfunc
, 0},
4711 /* Parser functions used exclusively in instruction operands. */
4713 /* Generic immediate-value read function for use in insn parsing.
4714 STR points to the beginning of the immediate (the leading #);
4715 VAL receives the value; if the value is outside [MIN, MAX]
4716 issue an error. PREFIX_OPT is true if the immediate prefix is
4720 parse_immediate (char **str
, int *val
, int min
, int max
,
4721 bfd_boolean prefix_opt
)
4724 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4725 if (exp
.X_op
!= O_constant
)
4727 inst
.error
= _("constant expression required");
4731 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4733 inst
.error
= _("immediate value out of range");
4737 *val
= exp
.X_add_number
;
4741 /* Less-generic immediate-value read function with the possibility of loading a
4742 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4743 instructions. Puts the result directly in inst.operands[i]. */
4746 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4747 bfd_boolean allow_symbol_p
)
4750 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4753 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4755 if (exp_p
->X_op
== O_constant
)
4757 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4758 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4759 O_constant. We have to be careful not to break compilation for
4760 32-bit X_add_number, though. */
4761 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4763 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4764 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4766 inst
.operands
[i
].regisimm
= 1;
4769 else if (exp_p
->X_op
== O_big
4770 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4772 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4774 /* Bignums have their least significant bits in
4775 generic_bignum[0]. Make sure we put 32 bits in imm and
4776 32 bits in reg, in a (hopefully) portable way. */
4777 gas_assert (parts
!= 0);
4779 /* Make sure that the number is not too big.
4780 PR 11972: Bignums can now be sign-extended to the
4781 size of a .octa so check that the out of range bits
4782 are all zero or all one. */
4783 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4785 LITTLENUM_TYPE m
= -1;
4787 if (generic_bignum
[parts
* 2] != 0
4788 && generic_bignum
[parts
* 2] != m
)
4791 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4792 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4796 inst
.operands
[i
].imm
= 0;
4797 for (j
= 0; j
< parts
; j
++, idx
++)
4798 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4799 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4800 inst
.operands
[i
].reg
= 0;
4801 for (j
= 0; j
< parts
; j
++, idx
++)
4802 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4803 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4804 inst
.operands
[i
].regisimm
= 1;
4806 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4814 /* Returns the pseudo-register number of an FPA immediate constant,
4815 or FAIL if there isn't a valid constant here. */
4818 parse_fpa_immediate (char ** str
)
4820 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4826 /* First try and match exact strings, this is to guarantee
4827 that some formats will work even for cross assembly. */
4829 for (i
= 0; fp_const
[i
]; i
++)
4831 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4835 *str
+= strlen (fp_const
[i
]);
4836 if (is_end_of_line
[(unsigned char) **str
])
4842 /* Just because we didn't get a match doesn't mean that the constant
4843 isn't valid, just that it is in a format that we don't
4844 automatically recognize. Try parsing it with the standard
4845 expression routines. */
4847 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4849 /* Look for a raw floating point number. */
4850 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4851 && is_end_of_line
[(unsigned char) *save_in
])
4853 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4855 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4857 if (words
[j
] != fp_values
[i
][j
])
4861 if (j
== MAX_LITTLENUMS
)
4869 /* Try and parse a more complex expression, this will probably fail
4870 unless the code uses a floating point prefix (eg "0f"). */
4871 save_in
= input_line_pointer
;
4872 input_line_pointer
= *str
;
4873 if (expression (&exp
) == absolute_section
4874 && exp
.X_op
== O_big
4875 && exp
.X_add_number
< 0)
4877 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4879 #define X_PRECISION 5
4880 #define E_PRECISION 15L
4881 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4883 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4885 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4887 if (words
[j
] != fp_values
[i
][j
])
4891 if (j
== MAX_LITTLENUMS
)
4893 *str
= input_line_pointer
;
4894 input_line_pointer
= save_in
;
4901 *str
= input_line_pointer
;
4902 input_line_pointer
= save_in
;
4903 inst
.error
= _("invalid FPA immediate expression");
4907 /* Returns 1 if a number has "quarter-precision" float format
4908 0baBbbbbbc defgh000 00000000 00000000. */
4911 is_quarter_float (unsigned imm
)
4913 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4914 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4918 /* Detect the presence of a floating point or integer zero constant,
4922 parse_ifimm_zero (char **in
)
4926 if (!is_immediate_prefix (**in
))
4931 /* Accept #0x0 as a synonym for #0. */
4932 if (strncmp (*in
, "0x", 2) == 0)
4935 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4940 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4941 &generic_floating_point_number
);
4944 && generic_floating_point_number
.sign
== '+'
4945 && (generic_floating_point_number
.low
4946 > generic_floating_point_number
.leader
))
4952 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4953 0baBbbbbbc defgh000 00000000 00000000.
4954 The zero and minus-zero cases need special handling, since they can't be
4955 encoded in the "quarter-precision" float format, but can nonetheless be
4956 loaded as integer constants. */
4959 parse_qfloat_immediate (char **ccp
, int *immed
)
4963 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4964 int found_fpchar
= 0;
4966 skip_past_char (&str
, '#');
4968 /* We must not accidentally parse an integer as a floating-point number. Make
4969 sure that the value we parse is not an integer by checking for special
4970 characters '.' or 'e'.
4971 FIXME: This is a horrible hack, but doing better is tricky because type
4972 information isn't in a very usable state at parse time. */
4974 skip_whitespace (fpnum
);
4976 if (strncmp (fpnum
, "0x", 2) == 0)
4980 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4981 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4991 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4993 unsigned fpword
= 0;
4996 /* Our FP word must be 32 bits (single-precision FP). */
4997 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4999 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5003 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5016 /* Shift operands. */
5019 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5022 struct asm_shift_name
5025 enum shift_kind kind
;
5028 /* Third argument to parse_shift. */
5029 enum parse_shift_mode
5031 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5032 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5033 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5034 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5035 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5038 /* Parse a <shift> specifier on an ARM data processing instruction.
5039 This has three forms:
5041 (LSL|LSR|ASL|ASR|ROR) Rs
5042 (LSL|LSR|ASL|ASR|ROR) #imm
5045 Note that ASL is assimilated to LSL in the instruction encoding, and
5046 RRX to ROR #0 (which cannot be written as such). */
5049 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5051 const struct asm_shift_name
*shift_name
;
5052 enum shift_kind shift
;
5057 for (p
= *str
; ISALPHA (*p
); p
++)
5062 inst
.error
= _("shift expression expected");
5066 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5069 if (shift_name
== NULL
)
5071 inst
.error
= _("shift expression expected");
5075 shift
= shift_name
->kind
;
5079 case NO_SHIFT_RESTRICT
:
5080 case SHIFT_IMMEDIATE
: break;
5082 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5083 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5085 inst
.error
= _("'LSL' or 'ASR' required");
5090 case SHIFT_LSL_IMMEDIATE
:
5091 if (shift
!= SHIFT_LSL
)
5093 inst
.error
= _("'LSL' required");
5098 case SHIFT_ASR_IMMEDIATE
:
5099 if (shift
!= SHIFT_ASR
)
5101 inst
.error
= _("'ASR' required");
5109 if (shift
!= SHIFT_RRX
)
5111 /* Whitespace can appear here if the next thing is a bare digit. */
5112 skip_whitespace (p
);
5114 if (mode
== NO_SHIFT_RESTRICT
5115 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5117 inst
.operands
[i
].imm
= reg
;
5118 inst
.operands
[i
].immisreg
= 1;
5120 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5123 inst
.operands
[i
].shift_kind
= shift
;
5124 inst
.operands
[i
].shifted
= 1;
5129 /* Parse a <shifter_operand> for an ARM data processing instruction:
5132 #<immediate>, <rotate>
5136 where <shift> is defined by parse_shift above, and <rotate> is a
5137 multiple of 2 between 0 and 30. Validation of immediate operands
5138 is deferred to md_apply_fix. */
5141 parse_shifter_operand (char **str
, int i
)
5146 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5148 inst
.operands
[i
].reg
= value
;
5149 inst
.operands
[i
].isreg
= 1;
5151 /* parse_shift will override this if appropriate */
5152 inst
.reloc
.exp
.X_op
= O_constant
;
5153 inst
.reloc
.exp
.X_add_number
= 0;
5155 if (skip_past_comma (str
) == FAIL
)
5158 /* Shift operation on register. */
5159 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5162 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5165 if (skip_past_comma (str
) == SUCCESS
)
5167 /* #x, y -- ie explicit rotation by Y. */
5168 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5171 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5173 inst
.error
= _("constant expression expected");
5177 value
= exp
.X_add_number
;
5178 if (value
< 0 || value
> 30 || value
% 2 != 0)
5180 inst
.error
= _("invalid rotation");
5183 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5185 inst
.error
= _("invalid constant");
5189 /* Encode as specified. */
5190 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5194 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5195 inst
.reloc
.pc_rel
= 0;
5199 /* Group relocation information. Each entry in the table contains the
5200 textual name of the relocation as may appear in assembler source
5201 and must end with a colon.
5202 Along with this textual name are the relocation codes to be used if
5203 the corresponding instruction is an ALU instruction (ADD or SUB only),
5204 an LDR, an LDRS, or an LDC. */
5206 struct group_reloc_table_entry
5217 /* Varieties of non-ALU group relocation. */
5224 static struct group_reloc_table_entry group_reloc_table
[] =
5225 { /* Program counter relative: */
5227 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5232 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5233 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5234 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5235 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5237 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5242 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5243 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5244 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5245 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5247 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5248 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5249 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5250 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5251 /* Section base relative */
5253 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5258 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5259 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5260 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5261 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5263 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5268 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5269 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5270 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5271 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5273 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5274 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5275 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5276 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5278 /* Given the address of a pointer pointing to the textual name of a group
5279 relocation as may appear in assembler source, attempt to find its details
5280 in group_reloc_table. The pointer will be updated to the character after
5281 the trailing colon. On failure, FAIL will be returned; SUCCESS
5282 otherwise. On success, *entry will be updated to point at the relevant
5283 group_reloc_table entry. */
5286 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5289 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5291 int length
= strlen (group_reloc_table
[i
].name
);
5293 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5294 && (*str
)[length
] == ':')
5296 *out
= &group_reloc_table
[i
];
5297 *str
+= (length
+ 1);
5305 /* Parse a <shifter_operand> for an ARM data processing instruction
5306 (as for parse_shifter_operand) where group relocations are allowed:
5309 #<immediate>, <rotate>
5310 #:<group_reloc>:<expression>
5314 where <group_reloc> is one of the strings defined in group_reloc_table.
5315 The hashes are optional.
5317 Everything else is as for parse_shifter_operand. */
5319 static parse_operand_result
5320 parse_shifter_operand_group_reloc (char **str
, int i
)
5322 /* Determine if we have the sequence of characters #: or just :
5323 coming next. If we do, then we check for a group relocation.
5324 If we don't, punt the whole lot to parse_shifter_operand. */
5326 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5327 || (*str
)[0] == ':')
5329 struct group_reloc_table_entry
*entry
;
5331 if ((*str
)[0] == '#')
5336 /* Try to parse a group relocation. Anything else is an error. */
5337 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5339 inst
.error
= _("unknown group relocation");
5340 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5343 /* We now have the group relocation table entry corresponding to
5344 the name in the assembler source. Next, we parse the expression. */
5345 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5346 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5348 /* Record the relocation type (always the ALU variant here). */
5349 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5350 gas_assert (inst
.reloc
.type
!= 0);
5352 return PARSE_OPERAND_SUCCESS
;
5355 return parse_shifter_operand (str
, i
) == SUCCESS
5356 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5358 /* Never reached. */
5361 /* Parse a Neon alignment expression. Information is written to
5362 inst.operands[i]. We assume the initial ':' has been skipped.
5364 align .imm = align << 8, .immisalign=1, .preind=0 */
5365 static parse_operand_result
5366 parse_neon_alignment (char **str
, int i
)
5371 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5373 if (exp
.X_op
!= O_constant
)
5375 inst
.error
= _("alignment must be constant");
5376 return PARSE_OPERAND_FAIL
;
5379 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5380 inst
.operands
[i
].immisalign
= 1;
5381 /* Alignments are not pre-indexes. */
5382 inst
.operands
[i
].preind
= 0;
5385 return PARSE_OPERAND_SUCCESS
;
5388 /* Parse all forms of an ARM address expression. Information is written
5389 to inst.operands[i] and/or inst.reloc.
5391 Preindexed addressing (.preind=1):
5393 [Rn, #offset] .reg=Rn .reloc.exp=offset
5394 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5395 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5396 .shift_kind=shift .reloc.exp=shift_imm
5398 These three may have a trailing ! which causes .writeback to be set also.
5400 Postindexed addressing (.postind=1, .writeback=1):
5402 [Rn], #offset .reg=Rn .reloc.exp=offset
5403 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5404 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5405 .shift_kind=shift .reloc.exp=shift_imm
5407 Unindexed addressing (.preind=0, .postind=0):
5409 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5413 [Rn]{!} shorthand for [Rn,#0]{!}
5414 =immediate .isreg=0 .reloc.exp=immediate
5415 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5417 It is the caller's responsibility to check for addressing modes not
5418 supported by the instruction, and to set inst.reloc.type. */
5420 static parse_operand_result
5421 parse_address_main (char **str
, int i
, int group_relocations
,
5422 group_reloc_type group_type
)
5427 if (skip_past_char (&p
, '[') == FAIL
)
5429 if (skip_past_char (&p
, '=') == FAIL
)
5431 /* Bare address - translate to PC-relative offset. */
5432 inst
.reloc
.pc_rel
= 1;
5433 inst
.operands
[i
].reg
= REG_PC
;
5434 inst
.operands
[i
].isreg
= 1;
5435 inst
.operands
[i
].preind
= 1;
5437 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5438 return PARSE_OPERAND_FAIL
;
5440 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5441 /*allow_symbol_p=*/TRUE
))
5442 return PARSE_OPERAND_FAIL
;
5445 return PARSE_OPERAND_SUCCESS
;
5448 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5449 skip_whitespace (p
);
5451 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5453 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5454 return PARSE_OPERAND_FAIL
;
5456 inst
.operands
[i
].reg
= reg
;
5457 inst
.operands
[i
].isreg
= 1;
5459 if (skip_past_comma (&p
) == SUCCESS
)
5461 inst
.operands
[i
].preind
= 1;
5464 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5466 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5468 inst
.operands
[i
].imm
= reg
;
5469 inst
.operands
[i
].immisreg
= 1;
5471 if (skip_past_comma (&p
) == SUCCESS
)
5472 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5473 return PARSE_OPERAND_FAIL
;
5475 else if (skip_past_char (&p
, ':') == SUCCESS
)
5477 /* FIXME: '@' should be used here, but it's filtered out by generic
5478 code before we get to see it here. This may be subject to
5480 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5482 if (result
!= PARSE_OPERAND_SUCCESS
)
5487 if (inst
.operands
[i
].negative
)
5489 inst
.operands
[i
].negative
= 0;
5493 if (group_relocations
5494 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5496 struct group_reloc_table_entry
*entry
;
5498 /* Skip over the #: or : sequence. */
5504 /* Try to parse a group relocation. Anything else is an
5506 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5508 inst
.error
= _("unknown group relocation");
5509 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5512 /* We now have the group relocation table entry corresponding to
5513 the name in the assembler source. Next, we parse the
5515 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5516 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5518 /* Record the relocation type. */
5522 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5526 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5530 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5537 if (inst
.reloc
.type
== 0)
5539 inst
.error
= _("this group relocation is not allowed on this instruction");
5540 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5546 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5547 return PARSE_OPERAND_FAIL
;
5548 /* If the offset is 0, find out if it's a +0 or -0. */
5549 if (inst
.reloc
.exp
.X_op
== O_constant
5550 && inst
.reloc
.exp
.X_add_number
== 0)
5552 skip_whitespace (q
);
5556 skip_whitespace (q
);
5559 inst
.operands
[i
].negative
= 1;
5564 else if (skip_past_char (&p
, ':') == SUCCESS
)
5566 /* FIXME: '@' should be used here, but it's filtered out by generic code
5567 before we get to see it here. This may be subject to change. */
5568 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5570 if (result
!= PARSE_OPERAND_SUCCESS
)
5574 if (skip_past_char (&p
, ']') == FAIL
)
5576 inst
.error
= _("']' expected");
5577 return PARSE_OPERAND_FAIL
;
5580 if (skip_past_char (&p
, '!') == SUCCESS
)
5581 inst
.operands
[i
].writeback
= 1;
5583 else if (skip_past_comma (&p
) == SUCCESS
)
5585 if (skip_past_char (&p
, '{') == SUCCESS
)
5587 /* [Rn], {expr} - unindexed, with option */
5588 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5589 0, 255, TRUE
) == FAIL
)
5590 return PARSE_OPERAND_FAIL
;
5592 if (skip_past_char (&p
, '}') == FAIL
)
5594 inst
.error
= _("'}' expected at end of 'option' field");
5595 return PARSE_OPERAND_FAIL
;
5597 if (inst
.operands
[i
].preind
)
5599 inst
.error
= _("cannot combine index with option");
5600 return PARSE_OPERAND_FAIL
;
5603 return PARSE_OPERAND_SUCCESS
;
5607 inst
.operands
[i
].postind
= 1;
5608 inst
.operands
[i
].writeback
= 1;
5610 if (inst
.operands
[i
].preind
)
5612 inst
.error
= _("cannot combine pre- and post-indexing");
5613 return PARSE_OPERAND_FAIL
;
5617 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5619 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5621 /* We might be using the immediate for alignment already. If we
5622 are, OR the register number into the low-order bits. */
5623 if (inst
.operands
[i
].immisalign
)
5624 inst
.operands
[i
].imm
|= reg
;
5626 inst
.operands
[i
].imm
= reg
;
5627 inst
.operands
[i
].immisreg
= 1;
5629 if (skip_past_comma (&p
) == SUCCESS
)
5630 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5631 return PARSE_OPERAND_FAIL
;
5636 if (inst
.operands
[i
].negative
)
5638 inst
.operands
[i
].negative
= 0;
5641 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5642 return PARSE_OPERAND_FAIL
;
5643 /* If the offset is 0, find out if it's a +0 or -0. */
5644 if (inst
.reloc
.exp
.X_op
== O_constant
5645 && inst
.reloc
.exp
.X_add_number
== 0)
5647 skip_whitespace (q
);
5651 skip_whitespace (q
);
5654 inst
.operands
[i
].negative
= 1;
5660 /* If at this point neither .preind nor .postind is set, we have a
5661 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5662 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5664 inst
.operands
[i
].preind
= 1;
5665 inst
.reloc
.exp
.X_op
= O_constant
;
5666 inst
.reloc
.exp
.X_add_number
= 0;
5669 return PARSE_OPERAND_SUCCESS
;
5673 parse_address (char **str
, int i
)
5675 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5679 static parse_operand_result
5680 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5682 return parse_address_main (str
, i
, 1, type
);
5685 /* Parse an operand for a MOVW or MOVT instruction. */
5687 parse_half (char **str
)
5692 skip_past_char (&p
, '#');
5693 if (strncasecmp (p
, ":lower16:", 9) == 0)
5694 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5695 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5696 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5698 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5701 skip_whitespace (p
);
5704 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5707 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5709 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5711 inst
.error
= _("constant expression expected");
5714 if (inst
.reloc
.exp
.X_add_number
< 0
5715 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5717 inst
.error
= _("immediate value out of range");
5725 /* Miscellaneous. */
5727 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5728 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5730 parse_psr (char **str
, bfd_boolean lhs
)
5733 unsigned long psr_field
;
5734 const struct asm_psr
*psr
;
5736 bfd_boolean is_apsr
= FALSE
;
5737 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5739 /* PR gas/12698: If the user has specified -march=all then m_profile will
5740 be TRUE, but we want to ignore it in this case as we are building for any
5741 CPU type, including non-m variants. */
5742 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5745 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5746 feature for ease of use and backwards compatibility. */
5748 if (strncasecmp (p
, "SPSR", 4) == 0)
5751 goto unsupported_psr
;
5753 psr_field
= SPSR_BIT
;
5755 else if (strncasecmp (p
, "CPSR", 4) == 0)
5758 goto unsupported_psr
;
5762 else if (strncasecmp (p
, "APSR", 4) == 0)
5764 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5765 and ARMv7-R architecture CPUs. */
5774 while (ISALNUM (*p
) || *p
== '_');
5776 if (strncasecmp (start
, "iapsr", 5) == 0
5777 || strncasecmp (start
, "eapsr", 5) == 0
5778 || strncasecmp (start
, "xpsr", 4) == 0
5779 || strncasecmp (start
, "psr", 3) == 0)
5780 p
= start
+ strcspn (start
, "rR") + 1;
5782 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5788 /* If APSR is being written, a bitfield may be specified. Note that
5789 APSR itself is handled above. */
5790 if (psr
->field
<= 3)
5792 psr_field
= psr
->field
;
5798 /* M-profile MSR instructions have the mask field set to "10", except
5799 *PSR variants which modify APSR, which may use a different mask (and
5800 have been handled already). Do that by setting the PSR_f field
5802 return psr
->field
| (lhs
? PSR_f
: 0);
5805 goto unsupported_psr
;
5811 /* A suffix follows. */
5817 while (ISALNUM (*p
) || *p
== '_');
5821 /* APSR uses a notation for bits, rather than fields. */
5822 unsigned int nzcvq_bits
= 0;
5823 unsigned int g_bit
= 0;
5826 for (bit
= start
; bit
!= p
; bit
++)
5828 switch (TOLOWER (*bit
))
5831 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5835 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5839 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5843 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5847 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5851 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5855 inst
.error
= _("unexpected bit specified after APSR");
5860 if (nzcvq_bits
== 0x1f)
5865 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5867 inst
.error
= _("selected processor does not "
5868 "support DSP extension");
5875 if ((nzcvq_bits
& 0x20) != 0
5876 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5877 || (g_bit
& 0x2) != 0)
5879 inst
.error
= _("bad bitmask specified after APSR");
5885 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5890 psr_field
|= psr
->field
;
5896 goto error
; /* Garbage after "[CS]PSR". */
5898 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5899 is deprecated, but allow it anyway. */
5903 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5906 else if (!m_profile
)
5907 /* These bits are never right for M-profile devices: don't set them
5908 (only code paths which read/write APSR reach here). */
5909 psr_field
|= (PSR_c
| PSR_f
);
5915 inst
.error
= _("selected processor does not support requested special "
5916 "purpose register");
5920 inst
.error
= _("flag for {c}psr instruction expected");
5924 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5925 value suitable for splatting into the AIF field of the instruction. */
5928 parse_cps_flags (char **str
)
5937 case '\0': case ',':
5940 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5941 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5942 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5945 inst
.error
= _("unrecognized CPS flag");
5950 if (saw_a_flag
== 0)
5952 inst
.error
= _("missing CPS flags");
5960 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5961 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5964 parse_endian_specifier (char **str
)
5969 if (strncasecmp (s
, "BE", 2))
5971 else if (strncasecmp (s
, "LE", 2))
5975 inst
.error
= _("valid endian specifiers are be or le");
5979 if (ISALNUM (s
[2]) || s
[2] == '_')
5981 inst
.error
= _("valid endian specifiers are be or le");
5986 return little_endian
;
5989 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5990 value suitable for poking into the rotate field of an sxt or sxta
5991 instruction, or FAIL on error. */
5994 parse_ror (char **str
)
5999 if (strncasecmp (s
, "ROR", 3) == 0)
6003 inst
.error
= _("missing rotation field after comma");
6007 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6012 case 0: *str
= s
; return 0x0;
6013 case 8: *str
= s
; return 0x1;
6014 case 16: *str
= s
; return 0x2;
6015 case 24: *str
= s
; return 0x3;
6018 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6023 /* Parse a conditional code (from conds[] below). The value returned is in the
6024 range 0 .. 14, or FAIL. */
6026 parse_cond (char **str
)
6029 const struct asm_cond
*c
;
6031 /* Condition codes are always 2 characters, so matching up to
6032 3 characters is sufficient. */
6037 while (ISALPHA (*q
) && n
< 3)
6039 cond
[n
] = TOLOWER (*q
);
6044 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6047 inst
.error
= _("condition required");
6055 /* If the given feature available in the selected CPU, mark it as used.
6056 Returns TRUE iff feature is available. */
6058 mark_feature_used (const arm_feature_set
*feature
)
6060 /* Ensure the option is valid on the current architecture. */
6061 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6064 /* Add the appropriate architecture feature for the barrier option used.
6067 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6069 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6074 /* Parse an option for a barrier instruction. Returns the encoding for the
6077 parse_barrier (char **str
)
6080 const struct asm_barrier_opt
*o
;
6083 while (ISALPHA (*q
))
6086 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6091 if (!mark_feature_used (&o
->arch
))
6098 /* Parse the operands of a table branch instruction. Similar to a memory
6101 parse_tb (char **str
)
6106 if (skip_past_char (&p
, '[') == FAIL
)
6108 inst
.error
= _("'[' expected");
6112 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6114 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6117 inst
.operands
[0].reg
= reg
;
6119 if (skip_past_comma (&p
) == FAIL
)
6121 inst
.error
= _("',' expected");
6125 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6127 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6130 inst
.operands
[0].imm
= reg
;
6132 if (skip_past_comma (&p
) == SUCCESS
)
6134 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6136 if (inst
.reloc
.exp
.X_add_number
!= 1)
6138 inst
.error
= _("invalid shift");
6141 inst
.operands
[0].shifted
= 1;
6144 if (skip_past_char (&p
, ']') == FAIL
)
6146 inst
.error
= _("']' expected");
6153 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6154 information on the types the operands can take and how they are encoded.
6155 Up to four operands may be read; this function handles setting the
6156 ".present" field for each read operand itself.
6157 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6158 else returns FAIL. */
6161 parse_neon_mov (char **str
, int *which_operand
)
6163 int i
= *which_operand
, val
;
6164 enum arm_reg_type rtype
;
6166 struct neon_type_el optype
;
6168 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6170 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6171 inst
.operands
[i
].reg
= val
;
6172 inst
.operands
[i
].isscalar
= 1;
6173 inst
.operands
[i
].vectype
= optype
;
6174 inst
.operands
[i
++].present
= 1;
6176 if (skip_past_comma (&ptr
) == FAIL
)
6179 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6182 inst
.operands
[i
].reg
= val
;
6183 inst
.operands
[i
].isreg
= 1;
6184 inst
.operands
[i
].present
= 1;
6186 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6189 /* Cases 0, 1, 2, 3, 5 (D only). */
6190 if (skip_past_comma (&ptr
) == FAIL
)
6193 inst
.operands
[i
].reg
= val
;
6194 inst
.operands
[i
].isreg
= 1;
6195 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6196 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6197 inst
.operands
[i
].isvec
= 1;
6198 inst
.operands
[i
].vectype
= optype
;
6199 inst
.operands
[i
++].present
= 1;
6201 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6203 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6204 Case 13: VMOV <Sd>, <Rm> */
6205 inst
.operands
[i
].reg
= val
;
6206 inst
.operands
[i
].isreg
= 1;
6207 inst
.operands
[i
].present
= 1;
6209 if (rtype
== REG_TYPE_NQ
)
6211 first_error (_("can't use Neon quad register here"));
6214 else if (rtype
!= REG_TYPE_VFS
)
6217 if (skip_past_comma (&ptr
) == FAIL
)
6219 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6221 inst
.operands
[i
].reg
= val
;
6222 inst
.operands
[i
].isreg
= 1;
6223 inst
.operands
[i
].present
= 1;
6226 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6229 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6230 Case 1: VMOV<c><q> <Dd>, <Dm>
6231 Case 8: VMOV.F32 <Sd>, <Sm>
6232 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6234 inst
.operands
[i
].reg
= val
;
6235 inst
.operands
[i
].isreg
= 1;
6236 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6237 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6238 inst
.operands
[i
].isvec
= 1;
6239 inst
.operands
[i
].vectype
= optype
;
6240 inst
.operands
[i
].present
= 1;
6242 if (skip_past_comma (&ptr
) == SUCCESS
)
6247 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6250 inst
.operands
[i
].reg
= val
;
6251 inst
.operands
[i
].isreg
= 1;
6252 inst
.operands
[i
++].present
= 1;
6254 if (skip_past_comma (&ptr
) == FAIL
)
6257 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6260 inst
.operands
[i
].reg
= val
;
6261 inst
.operands
[i
].isreg
= 1;
6262 inst
.operands
[i
].present
= 1;
6265 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6266 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6267 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6268 Case 10: VMOV.F32 <Sd>, #<imm>
6269 Case 11: VMOV.F64 <Dd>, #<imm> */
6270 inst
.operands
[i
].immisfloat
= 1;
6271 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6273 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6274 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6278 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6282 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6285 inst
.operands
[i
].reg
= val
;
6286 inst
.operands
[i
].isreg
= 1;
6287 inst
.operands
[i
++].present
= 1;
6289 if (skip_past_comma (&ptr
) == FAIL
)
6292 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6294 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6295 inst
.operands
[i
].reg
= val
;
6296 inst
.operands
[i
].isscalar
= 1;
6297 inst
.operands
[i
].present
= 1;
6298 inst
.operands
[i
].vectype
= optype
;
6300 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6302 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6303 inst
.operands
[i
].reg
= val
;
6304 inst
.operands
[i
].isreg
= 1;
6305 inst
.operands
[i
++].present
= 1;
6307 if (skip_past_comma (&ptr
) == FAIL
)
6310 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6313 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6317 inst
.operands
[i
].reg
= val
;
6318 inst
.operands
[i
].isreg
= 1;
6319 inst
.operands
[i
].isvec
= 1;
6320 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6321 inst
.operands
[i
].vectype
= optype
;
6322 inst
.operands
[i
].present
= 1;
6324 if (rtype
== REG_TYPE_VFS
)
6328 if (skip_past_comma (&ptr
) == FAIL
)
6330 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6333 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6336 inst
.operands
[i
].reg
= val
;
6337 inst
.operands
[i
].isreg
= 1;
6338 inst
.operands
[i
].isvec
= 1;
6339 inst
.operands
[i
].issingle
= 1;
6340 inst
.operands
[i
].vectype
= optype
;
6341 inst
.operands
[i
].present
= 1;
6344 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6348 inst
.operands
[i
].reg
= val
;
6349 inst
.operands
[i
].isreg
= 1;
6350 inst
.operands
[i
].isvec
= 1;
6351 inst
.operands
[i
].issingle
= 1;
6352 inst
.operands
[i
].vectype
= optype
;
6353 inst
.operands
[i
].present
= 1;
6358 first_error (_("parse error"));
6362 /* Successfully parsed the operands. Update args. */
6368 first_error (_("expected comma"));
6372 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6376 /* Use this macro when the operand constraints are different
6377 for ARM and THUMB (e.g. ldrd). */
6378 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6379 ((arm_operand) | ((thumb_operand) << 16))
6381 /* Matcher codes for parse_operands. */
6382 enum operand_parse_code
6384 OP_stop
, /* end of line */
6386 OP_RR
, /* ARM register */
6387 OP_RRnpc
, /* ARM register, not r15 */
6388 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6389 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6390 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6391 optional trailing ! */
6392 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6393 OP_RCP
, /* Coprocessor number */
6394 OP_RCN
, /* Coprocessor register */
6395 OP_RF
, /* FPA register */
6396 OP_RVS
, /* VFP single precision register */
6397 OP_RVD
, /* VFP double precision register (0..15) */
6398 OP_RND
, /* Neon double precision register (0..31) */
6399 OP_RNQ
, /* Neon quad precision register */
6400 OP_RVSD
, /* VFP single or double precision register */
6401 OP_RNDQ
, /* Neon double or quad precision register */
6402 OP_RNSDQ
, /* Neon single, double or quad precision register */
6403 OP_RNSC
, /* Neon scalar D[X] */
6404 OP_RVC
, /* VFP control register */
6405 OP_RMF
, /* Maverick F register */
6406 OP_RMD
, /* Maverick D register */
6407 OP_RMFX
, /* Maverick FX register */
6408 OP_RMDX
, /* Maverick DX register */
6409 OP_RMAX
, /* Maverick AX register */
6410 OP_RMDS
, /* Maverick DSPSC register */
6411 OP_RIWR
, /* iWMMXt wR register */
6412 OP_RIWC
, /* iWMMXt wC register */
6413 OP_RIWG
, /* iWMMXt wCG register */
6414 OP_RXA
, /* XScale accumulator register */
6416 OP_REGLST
, /* ARM register list */
6417 OP_VRSLST
, /* VFP single-precision register list */
6418 OP_VRDLST
, /* VFP double-precision register list */
6419 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6420 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6421 OP_NSTRLST
, /* Neon element/structure list */
6423 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6424 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6425 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6426 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6427 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6428 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6429 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6430 OP_VMOV
, /* Neon VMOV operands. */
6431 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6432 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6433 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6435 OP_I0
, /* immediate zero */
6436 OP_I7
, /* immediate value 0 .. 7 */
6437 OP_I15
, /* 0 .. 15 */
6438 OP_I16
, /* 1 .. 16 */
6439 OP_I16z
, /* 0 .. 16 */
6440 OP_I31
, /* 0 .. 31 */
6441 OP_I31w
, /* 0 .. 31, optional trailing ! */
6442 OP_I32
, /* 1 .. 32 */
6443 OP_I32z
, /* 0 .. 32 */
6444 OP_I63
, /* 0 .. 63 */
6445 OP_I63s
, /* -64 .. 63 */
6446 OP_I64
, /* 1 .. 64 */
6447 OP_I64z
, /* 0 .. 64 */
6448 OP_I255
, /* 0 .. 255 */
6450 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6451 OP_I7b
, /* 0 .. 7 */
6452 OP_I15b
, /* 0 .. 15 */
6453 OP_I31b
, /* 0 .. 31 */
6455 OP_SH
, /* shifter operand */
6456 OP_SHG
, /* shifter operand with possible group relocation */
6457 OP_ADDR
, /* Memory address expression (any mode) */
6458 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6459 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6460 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6461 OP_EXP
, /* arbitrary expression */
6462 OP_EXPi
, /* same, with optional immediate prefix */
6463 OP_EXPr
, /* same, with optional relocation suffix */
6464 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6466 OP_CPSF
, /* CPS flags */
6467 OP_ENDI
, /* Endianness specifier */
6468 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6469 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6470 OP_COND
, /* conditional code */
6471 OP_TB
, /* Table branch. */
6473 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6475 OP_RRnpc_I0
, /* ARM register or literal 0 */
6476 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6477 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6478 OP_RF_IF
, /* FPA register or immediate */
6479 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6480 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6482 /* Optional operands. */
6483 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6484 OP_oI31b
, /* 0 .. 31 */
6485 OP_oI32b
, /* 1 .. 32 */
6486 OP_oI32z
, /* 0 .. 32 */
6487 OP_oIffffb
, /* 0 .. 65535 */
6488 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6490 OP_oRR
, /* ARM register */
6491 OP_oRRnpc
, /* ARM register, not the PC */
6492 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6493 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6494 OP_oRND
, /* Optional Neon double precision register */
6495 OP_oRNQ
, /* Optional Neon quad precision register */
6496 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6497 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6498 OP_oSHll
, /* LSL immediate */
6499 OP_oSHar
, /* ASR immediate */
6500 OP_oSHllar
, /* LSL or ASR immediate */
6501 OP_oROR
, /* ROR 0/8/16/24 */
6502 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6504 /* Some pre-defined mixed (ARM/THUMB) operands. */
6505 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6506 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6507 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6509 OP_FIRST_OPTIONAL
= OP_oI7b
6512 /* Generic instruction operand parser. This does no encoding and no
6513 semantic validation; it merely squirrels values away in the inst
6514 structure. Returns SUCCESS or FAIL depending on whether the
6515 specified grammar matched. */
6517 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6519 unsigned const int *upat
= pattern
;
6520 char *backtrack_pos
= 0;
6521 const char *backtrack_error
= 0;
6522 int i
, val
= 0, backtrack_index
= 0;
6523 enum arm_reg_type rtype
;
6524 parse_operand_result result
;
6525 unsigned int op_parse_code
;
6527 #define po_char_or_fail(chr) \
6530 if (skip_past_char (&str, chr) == FAIL) \
6535 #define po_reg_or_fail(regtype) \
6538 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6539 & inst.operands[i].vectype); \
6542 first_error (_(reg_expected_msgs[regtype])); \
6545 inst.operands[i].reg = val; \
6546 inst.operands[i].isreg = 1; \
6547 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6548 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6549 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6550 || rtype == REG_TYPE_VFD \
6551 || rtype == REG_TYPE_NQ); \
6555 #define po_reg_or_goto(regtype, label) \
6558 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6559 & inst.operands[i].vectype); \
6563 inst.operands[i].reg = val; \
6564 inst.operands[i].isreg = 1; \
6565 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6566 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6567 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6568 || rtype == REG_TYPE_VFD \
6569 || rtype == REG_TYPE_NQ); \
6573 #define po_imm_or_fail(min, max, popt) \
6576 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6578 inst.operands[i].imm = val; \
6582 #define po_scalar_or_goto(elsz, label) \
6585 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6588 inst.operands[i].reg = val; \
6589 inst.operands[i].isscalar = 1; \
6593 #define po_misc_or_fail(expr) \
6601 #define po_misc_or_fail_no_backtrack(expr) \
6605 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6606 backtrack_pos = 0; \
6607 if (result != PARSE_OPERAND_SUCCESS) \
6612 #define po_barrier_or_imm(str) \
6615 val = parse_barrier (&str); \
6616 if (val == FAIL && ! ISALPHA (*str)) \
6619 /* ISB can only take SY as an option. */ \
6620 || ((inst.instruction & 0xf0) == 0x60 \
6623 inst.error = _("invalid barrier type"); \
6624 backtrack_pos = 0; \
6630 skip_whitespace (str
);
6632 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6634 op_parse_code
= upat
[i
];
6635 if (op_parse_code
>= 1<<16)
6636 op_parse_code
= thumb
? (op_parse_code
>> 16)
6637 : (op_parse_code
& ((1<<16)-1));
6639 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6641 /* Remember where we are in case we need to backtrack. */
6642 gas_assert (!backtrack_pos
);
6643 backtrack_pos
= str
;
6644 backtrack_error
= inst
.error
;
6645 backtrack_index
= i
;
6648 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6649 po_char_or_fail (',');
6651 switch (op_parse_code
)
6659 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6660 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6661 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6662 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6663 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6664 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6666 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6668 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6670 /* Also accept generic coprocessor regs for unknown registers. */
6672 po_reg_or_fail (REG_TYPE_CN
);
6674 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6675 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6676 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6677 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6678 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6679 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6680 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6681 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6682 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6683 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6685 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6687 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6688 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6690 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6692 /* Neon scalar. Using an element size of 8 means that some invalid
6693 scalars are accepted here, so deal with those in later code. */
6694 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6698 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6701 po_imm_or_fail (0, 0, TRUE
);
6706 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6711 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6714 if (parse_ifimm_zero (&str
))
6715 inst
.operands
[i
].imm
= 0;
6719 = _("only floating point zero is allowed as immediate value");
6727 po_scalar_or_goto (8, try_rr
);
6730 po_reg_or_fail (REG_TYPE_RN
);
6736 po_scalar_or_goto (8, try_nsdq
);
6739 po_reg_or_fail (REG_TYPE_NSDQ
);
6745 po_scalar_or_goto (8, try_ndq
);
6748 po_reg_or_fail (REG_TYPE_NDQ
);
6754 po_scalar_or_goto (8, try_vfd
);
6757 po_reg_or_fail (REG_TYPE_VFD
);
6762 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6763 not careful then bad things might happen. */
6764 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6769 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6772 /* There's a possibility of getting a 64-bit immediate here, so
6773 we need special handling. */
6774 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6777 inst
.error
= _("immediate value is out of range");
6785 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6788 po_imm_or_fail (0, 63, TRUE
);
6793 po_char_or_fail ('[');
6794 po_reg_or_fail (REG_TYPE_RN
);
6795 po_char_or_fail (']');
6801 po_reg_or_fail (REG_TYPE_RN
);
6802 if (skip_past_char (&str
, '!') == SUCCESS
)
6803 inst
.operands
[i
].writeback
= 1;
6807 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6808 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6809 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6810 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6811 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6812 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6813 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6814 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6815 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6816 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6817 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6818 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6820 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6822 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6823 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6825 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6826 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6827 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6828 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6830 /* Immediate variants */
6832 po_char_or_fail ('{');
6833 po_imm_or_fail (0, 255, TRUE
);
6834 po_char_or_fail ('}');
6838 /* The expression parser chokes on a trailing !, so we have
6839 to find it first and zap it. */
6842 while (*s
&& *s
!= ',')
6847 inst
.operands
[i
].writeback
= 1;
6849 po_imm_or_fail (0, 31, TRUE
);
6857 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6862 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6867 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6869 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6871 val
= parse_reloc (&str
);
6874 inst
.error
= _("unrecognized relocation suffix");
6877 else if (val
!= BFD_RELOC_UNUSED
)
6879 inst
.operands
[i
].imm
= val
;
6880 inst
.operands
[i
].hasreloc
= 1;
6885 /* Operand for MOVW or MOVT. */
6887 po_misc_or_fail (parse_half (&str
));
6890 /* Register or expression. */
6891 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6892 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6894 /* Register or immediate. */
6895 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6896 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6898 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6900 if (!is_immediate_prefix (*str
))
6903 val
= parse_fpa_immediate (&str
);
6906 /* FPA immediates are encoded as registers 8-15.
6907 parse_fpa_immediate has already applied the offset. */
6908 inst
.operands
[i
].reg
= val
;
6909 inst
.operands
[i
].isreg
= 1;
6912 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6913 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6915 /* Two kinds of register. */
6918 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6920 || (rege
->type
!= REG_TYPE_MMXWR
6921 && rege
->type
!= REG_TYPE_MMXWC
6922 && rege
->type
!= REG_TYPE_MMXWCG
))
6924 inst
.error
= _("iWMMXt data or control register expected");
6927 inst
.operands
[i
].reg
= rege
->number
;
6928 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6934 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6936 || (rege
->type
!= REG_TYPE_MMXWC
6937 && rege
->type
!= REG_TYPE_MMXWCG
))
6939 inst
.error
= _("iWMMXt control register expected");
6942 inst
.operands
[i
].reg
= rege
->number
;
6943 inst
.operands
[i
].isreg
= 1;
6948 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6949 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6950 case OP_oROR
: val
= parse_ror (&str
); break;
6951 case OP_COND
: val
= parse_cond (&str
); break;
6952 case OP_oBARRIER_I15
:
6953 po_barrier_or_imm (str
); break;
6955 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6961 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6962 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6964 inst
.error
= _("Banked registers are not available with this "
6970 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6974 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6977 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6979 if (strncasecmp (str
, "APSR_", 5) == 0)
6986 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6987 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6988 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6989 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6990 default: found
= 16;
6994 inst
.operands
[i
].isvec
= 1;
6995 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6996 inst
.operands
[i
].reg
= REG_PC
;
7003 po_misc_or_fail (parse_tb (&str
));
7006 /* Register lists. */
7008 val
= parse_reg_list (&str
);
7011 inst
.operands
[i
].writeback
= 1;
7017 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7021 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7025 /* Allow Q registers too. */
7026 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7031 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7033 inst
.operands
[i
].issingle
= 1;
7038 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7043 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7044 &inst
.operands
[i
].vectype
);
7047 /* Addressing modes */
7049 po_misc_or_fail (parse_address (&str
, i
));
7053 po_misc_or_fail_no_backtrack (
7054 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7058 po_misc_or_fail_no_backtrack (
7059 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7063 po_misc_or_fail_no_backtrack (
7064 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7068 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7072 po_misc_or_fail_no_backtrack (
7073 parse_shifter_operand_group_reloc (&str
, i
));
7077 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7081 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7085 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7089 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7092 /* Various value-based sanity checks and shared operations. We
7093 do not signal immediate failures for the register constraints;
7094 this allows a syntax error to take precedence. */
7095 switch (op_parse_code
)
7103 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7104 inst
.error
= BAD_PC
;
7109 if (inst
.operands
[i
].isreg
)
7111 if (inst
.operands
[i
].reg
== REG_PC
)
7112 inst
.error
= BAD_PC
;
7113 else if (inst
.operands
[i
].reg
== REG_SP
)
7114 inst
.error
= BAD_SP
;
7119 if (inst
.operands
[i
].isreg
7120 && inst
.operands
[i
].reg
== REG_PC
7121 && (inst
.operands
[i
].writeback
|| thumb
))
7122 inst
.error
= BAD_PC
;
7131 case OP_oBARRIER_I15
:
7140 inst
.operands
[i
].imm
= val
;
7147 /* If we get here, this operand was successfully parsed. */
7148 inst
.operands
[i
].present
= 1;
7152 inst
.error
= BAD_ARGS
;
7157 /* The parse routine should already have set inst.error, but set a
7158 default here just in case. */
7160 inst
.error
= _("syntax error");
7164 /* Do not backtrack over a trailing optional argument that
7165 absorbed some text. We will only fail again, with the
7166 'garbage following instruction' error message, which is
7167 probably less helpful than the current one. */
7168 if (backtrack_index
== i
&& backtrack_pos
!= str
7169 && upat
[i
+1] == OP_stop
)
7172 inst
.error
= _("syntax error");
7176 /* Try again, skipping the optional argument at backtrack_pos. */
7177 str
= backtrack_pos
;
7178 inst
.error
= backtrack_error
;
7179 inst
.operands
[backtrack_index
].present
= 0;
7180 i
= backtrack_index
;
7184 /* Check that we have parsed all the arguments. */
7185 if (*str
!= '\0' && !inst
.error
)
7186 inst
.error
= _("garbage following instruction");
7188 return inst
.error
? FAIL
: SUCCESS
;
7191 #undef po_char_or_fail
7192 #undef po_reg_or_fail
7193 #undef po_reg_or_goto
7194 #undef po_imm_or_fail
7195 #undef po_scalar_or_fail
7196 #undef po_barrier_or_imm
7198 /* Shorthand macro for instruction encoding functions issuing errors. */
7199 #define constraint(expr, err) \
7210 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7211 instructions are unpredictable if these registers are used. This
7212 is the BadReg predicate in ARM's Thumb-2 documentation. */
7213 #define reject_bad_reg(reg) \
7215 if (reg == REG_SP || reg == REG_PC) \
7217 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7222 /* If REG is R13 (the stack pointer), warn that its use is
7224 #define warn_deprecated_sp(reg) \
7226 if (warn_on_deprecated && reg == REG_SP) \
7227 as_tsktsk (_("use of r13 is deprecated")); \
7230 /* Functions for operand encoding. ARM, then Thumb. */
7232 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7234 /* If VAL can be encoded in the immediate field of an ARM instruction,
7235 return the encoded form. Otherwise, return FAIL. */
7238 encode_arm_immediate (unsigned int val
)
7242 for (i
= 0; i
< 32; i
+= 2)
7243 if ((a
= rotate_left (val
, i
)) <= 0xff)
7244 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7249 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7250 return the encoded form. Otherwise, return FAIL. */
7252 encode_thumb32_immediate (unsigned int val
)
7259 for (i
= 1; i
<= 24; i
++)
7262 if ((val
& ~(0xff << i
)) == 0)
7263 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7267 if (val
== ((a
<< 16) | a
))
7269 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7273 if (val
== ((a
<< 16) | a
))
7274 return 0x200 | (a
>> 8);
7278 /* Encode a VFP SP or DP register number into inst.instruction. */
7281 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7283 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7286 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7289 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7292 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7297 first_error (_("D register out of range for selected VFP version"));
7305 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7309 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7313 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7317 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7321 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7325 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7333 /* Encode a <shift> in an ARM-format instruction. The immediate,
7334 if any, is handled by md_apply_fix. */
7336 encode_arm_shift (int i
)
7338 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7339 inst
.instruction
|= SHIFT_ROR
<< 5;
7342 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7343 if (inst
.operands
[i
].immisreg
)
7345 inst
.instruction
|= SHIFT_BY_REG
;
7346 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7349 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7354 encode_arm_shifter_operand (int i
)
7356 if (inst
.operands
[i
].isreg
)
7358 inst
.instruction
|= inst
.operands
[i
].reg
;
7359 encode_arm_shift (i
);
7363 inst
.instruction
|= INST_IMMEDIATE
;
7364 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7365 inst
.instruction
|= inst
.operands
[i
].imm
;
7369 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7371 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7374 Generate an error if the operand is not a register. */
7375 constraint (!inst
.operands
[i
].isreg
,
7376 _("Instruction does not support =N addresses"));
7378 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7380 if (inst
.operands
[i
].preind
)
7384 inst
.error
= _("instruction does not accept preindexed addressing");
7387 inst
.instruction
|= PRE_INDEX
;
7388 if (inst
.operands
[i
].writeback
)
7389 inst
.instruction
|= WRITE_BACK
;
7392 else if (inst
.operands
[i
].postind
)
7394 gas_assert (inst
.operands
[i
].writeback
);
7396 inst
.instruction
|= WRITE_BACK
;
7398 else /* unindexed - only for coprocessor */
7400 inst
.error
= _("instruction does not accept unindexed addressing");
7404 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7405 && (((inst
.instruction
& 0x000f0000) >> 16)
7406 == ((inst
.instruction
& 0x0000f000) >> 12)))
7407 as_warn ((inst
.instruction
& LOAD_BIT
)
7408 ? _("destination register same as write-back base")
7409 : _("source register same as write-back base"));
7412 /* inst.operands[i] was set up by parse_address. Encode it into an
7413 ARM-format mode 2 load or store instruction. If is_t is true,
7414 reject forms that cannot be used with a T instruction (i.e. not
7417 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7419 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7421 encode_arm_addr_mode_common (i
, is_t
);
7423 if (inst
.operands
[i
].immisreg
)
7425 constraint ((inst
.operands
[i
].imm
== REG_PC
7426 || (is_pc
&& inst
.operands
[i
].writeback
)),
7428 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7429 inst
.instruction
|= inst
.operands
[i
].imm
;
7430 if (!inst
.operands
[i
].negative
)
7431 inst
.instruction
|= INDEX_UP
;
7432 if (inst
.operands
[i
].shifted
)
7434 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7435 inst
.instruction
|= SHIFT_ROR
<< 5;
7438 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7439 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7443 else /* immediate offset in inst.reloc */
7445 if (is_pc
&& !inst
.reloc
.pc_rel
)
7447 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7449 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7450 cannot use PC in addressing.
7451 PC cannot be used in writeback addressing, either. */
7452 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7455 /* Use of PC in str is deprecated for ARMv7. */
7456 if (warn_on_deprecated
7458 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7459 as_tsktsk (_("use of PC in this instruction is deprecated"));
7462 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7464 /* Prefer + for zero encoded value. */
7465 if (!inst
.operands
[i
].negative
)
7466 inst
.instruction
|= INDEX_UP
;
7467 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7472 /* inst.operands[i] was set up by parse_address. Encode it into an
7473 ARM-format mode 3 load or store instruction. Reject forms that
7474 cannot be used with such instructions. If is_t is true, reject
7475 forms that cannot be used with a T instruction (i.e. not
7478 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7480 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7482 inst
.error
= _("instruction does not accept scaled register index");
7486 encode_arm_addr_mode_common (i
, is_t
);
7488 if (inst
.operands
[i
].immisreg
)
7490 constraint ((inst
.operands
[i
].imm
== REG_PC
7491 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7493 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7495 inst
.instruction
|= inst
.operands
[i
].imm
;
7496 if (!inst
.operands
[i
].negative
)
7497 inst
.instruction
|= INDEX_UP
;
7499 else /* immediate offset in inst.reloc */
7501 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7502 && inst
.operands
[i
].writeback
),
7504 inst
.instruction
|= HWOFFSET_IMM
;
7505 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7507 /* Prefer + for zero encoded value. */
7508 if (!inst
.operands
[i
].negative
)
7509 inst
.instruction
|= INDEX_UP
;
7511 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7516 /* Write immediate bits [7:0] to the following locations:
7518 |28/24|23 19|18 16|15 4|3 0|
7519 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7521 This function is used by VMOV/VMVN/VORR/VBIC. */
7524 neon_write_immbits (unsigned immbits
)
7526 inst
.instruction
|= immbits
& 0xf;
7527 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7528 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7531 /* Invert low-order SIZE bits of XHI:XLO. */
7534 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7536 unsigned immlo
= xlo
? *xlo
: 0;
7537 unsigned immhi
= xhi
? *xhi
: 0;
7542 immlo
= (~immlo
) & 0xff;
7546 immlo
= (~immlo
) & 0xffff;
7550 immhi
= (~immhi
) & 0xffffffff;
7554 immlo
= (~immlo
) & 0xffffffff;
7568 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7572 neon_bits_same_in_bytes (unsigned imm
)
7574 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7575 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7576 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7577 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7580 /* For immediate of above form, return 0bABCD. */
7583 neon_squash_bits (unsigned imm
)
7585 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7586 | ((imm
& 0x01000000) >> 21);
7589 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7592 neon_qfloat_bits (unsigned imm
)
7594 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7597 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7598 the instruction. *OP is passed as the initial value of the op field, and
7599 may be set to a different value depending on the constant (i.e.
7600 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7601 MVN). If the immediate looks like a repeated pattern then also
7602 try smaller element sizes. */
7605 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7606 unsigned *immbits
, int *op
, int size
,
7607 enum neon_el_type type
)
7609 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7611 if (type
== NT_float
&& !float_p
)
7614 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7616 if (size
!= 32 || *op
== 1)
7618 *immbits
= neon_qfloat_bits (immlo
);
7624 if (neon_bits_same_in_bytes (immhi
)
7625 && neon_bits_same_in_bytes (immlo
))
7629 *immbits
= (neon_squash_bits (immhi
) << 4)
7630 | neon_squash_bits (immlo
);
7641 if (immlo
== (immlo
& 0x000000ff))
7646 else if (immlo
== (immlo
& 0x0000ff00))
7648 *immbits
= immlo
>> 8;
7651 else if (immlo
== (immlo
& 0x00ff0000))
7653 *immbits
= immlo
>> 16;
7656 else if (immlo
== (immlo
& 0xff000000))
7658 *immbits
= immlo
>> 24;
7661 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7663 *immbits
= (immlo
>> 8) & 0xff;
7666 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7668 *immbits
= (immlo
>> 16) & 0xff;
7672 if ((immlo
& 0xffff) != (immlo
>> 16))
7679 if (immlo
== (immlo
& 0x000000ff))
7684 else if (immlo
== (immlo
& 0x0000ff00))
7686 *immbits
= immlo
>> 8;
7690 if ((immlo
& 0xff) != (immlo
>> 8))
7695 if (immlo
== (immlo
& 0x000000ff))
7697 /* Don't allow MVN with 8-bit immediate. */
7707 #if defined BFD_HOST_64_BIT
7708 /* Returns TRUE if double precision value V may be cast
7709 to single precision without loss of accuracy. */
7712 is_double_a_single (bfd_int64_t v
)
7714 int exp
= (int)((v
>> 52) & 0x7FF);
7715 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7717 return (exp
== 0 || exp
== 0x7FF
7718 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7719 && (mantissa
& 0x1FFFFFFFl
) == 0;
7722 /* Returns a double precision value casted to single precision
7723 (ignoring the least significant bits in exponent and mantissa). */
7726 double_to_single (bfd_int64_t v
)
7728 int sign
= (int) ((v
>> 63) & 1l);
7729 int exp
= (int) ((v
>> 52) & 0x7FF);
7730 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7736 exp
= exp
- 1023 + 127;
7745 /* No denormalized numbers. */
7751 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7753 #endif /* BFD_HOST_64_BIT */
7762 static void do_vfp_nsyn_opcode (const char *);
7764 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7765 Determine whether it can be performed with a move instruction; if
7766 it can, convert inst.instruction to that move instruction and
7767 return TRUE; if it can't, convert inst.instruction to a literal-pool
7768 load and return FALSE. If this is not a valid thing to do in the
7769 current context, set inst.error and return TRUE.
7771 inst.operands[i] describes the destination register. */
7774 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7777 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7778 bfd_boolean arm_p
= (t
== CONST_ARM
);
7781 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7785 if ((inst
.instruction
& tbit
) == 0)
7787 inst
.error
= _("invalid pseudo operation");
7791 if (inst
.reloc
.exp
.X_op
!= O_constant
7792 && inst
.reloc
.exp
.X_op
!= O_symbol
7793 && inst
.reloc
.exp
.X_op
!= O_big
)
7795 inst
.error
= _("constant expression expected");
7799 if (inst
.reloc
.exp
.X_op
== O_constant
7800 || inst
.reloc
.exp
.X_op
== O_big
)
7802 #if defined BFD_HOST_64_BIT
7807 if (inst
.reloc
.exp
.X_op
== O_big
)
7809 LITTLENUM_TYPE w
[X_PRECISION
];
7812 if (inst
.reloc
.exp
.X_add_number
== -1)
7814 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7816 /* FIXME: Should we check words w[2..5] ? */
7821 #if defined BFD_HOST_64_BIT
7823 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7824 << LITTLENUM_NUMBER_OF_BITS
)
7825 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7826 << LITTLENUM_NUMBER_OF_BITS
)
7827 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7828 << LITTLENUM_NUMBER_OF_BITS
)
7829 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7831 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7832 | (l
[0] & LITTLENUM_MASK
);
7836 v
= inst
.reloc
.exp
.X_add_number
;
7838 if (!inst
.operands
[i
].issingle
)
7842 /* This can be encoded only for a low register. */
7843 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7845 /* This can be done with a mov(1) instruction. */
7846 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7847 inst
.instruction
|= v
;
7851 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
7853 /* Check if on thumb2 it can be done with a mov.w or mvn.w
7855 unsigned int newimm
;
7856 bfd_boolean isNegated
;
7858 newimm
= encode_thumb32_immediate (v
);
7859 if (newimm
!= (unsigned int) FAIL
)
7863 newimm
= encode_thumb32_immediate (~v
);
7864 if (newimm
!= (unsigned int) FAIL
)
7868 if (newimm
!= (unsigned int) FAIL
)
7870 inst
.instruction
= (0xf04f0000
7871 | (inst
.operands
[i
].reg
<< 8));
7872 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7873 inst
.instruction
|= (newimm
& 0x800) << 15;
7874 inst
.instruction
|= (newimm
& 0x700) << 4;
7875 inst
.instruction
|= (newimm
& 0x0ff);
7878 else if ((v
& ~0xFFFF) == 0)
7880 /* The number can be loaded with a mov.w instruction. */
7881 int imm
= v
& 0xFFFF;
7883 inst
.instruction
= 0xf2400000; /* MOVW. */
7884 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7885 inst
.instruction
|= (imm
& 0xf000) << 4;
7886 inst
.instruction
|= (imm
& 0x0800) << 15;
7887 inst
.instruction
|= (imm
& 0x0700) << 4;
7888 inst
.instruction
|= (imm
& 0x00ff);
7895 int value
= encode_arm_immediate (v
);
7899 /* This can be done with a mov instruction. */
7900 inst
.instruction
&= LITERAL_MASK
;
7901 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7902 inst
.instruction
|= value
& 0xfff;
7906 value
= encode_arm_immediate (~ v
);
7909 /* This can be done with a mvn instruction. */
7910 inst
.instruction
&= LITERAL_MASK
;
7911 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7912 inst
.instruction
|= value
& 0xfff;
7916 else if (t
== CONST_VEC
)
7919 unsigned immbits
= 0;
7920 unsigned immlo
= inst
.operands
[1].imm
;
7921 unsigned immhi
= inst
.operands
[1].regisimm
7922 ? inst
.operands
[1].reg
7923 : inst
.reloc
.exp
.X_unsigned
7925 : ((bfd_int64_t
)((int) immlo
)) >> 32;
7926 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7927 &op
, 64, NT_invtype
);
7931 neon_invert_size (&immlo
, &immhi
, 64);
7933 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
7934 &op
, 64, NT_invtype
);
7939 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
7945 /* Fill other bits in vmov encoding for both thumb and arm. */
7947 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
7949 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
7950 neon_write_immbits (immbits
);
7958 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
7959 if (inst
.operands
[i
].issingle
7960 && is_quarter_float (inst
.operands
[1].imm
)
7961 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
7963 inst
.operands
[1].imm
=
7964 neon_qfloat_bits (v
);
7965 do_vfp_nsyn_opcode ("fconsts");
7969 /* If our host does not support a 64-bit type then we cannot perform
7970 the following optimization. This mean that there will be a
7971 discrepancy between the output produced by an assembler built for
7972 a 32-bit-only host and the output produced from a 64-bit host, but
7973 this cannot be helped. */
7974 #if defined BFD_HOST_64_BIT
7975 else if (!inst
.operands
[1].issingle
7976 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
7978 if (is_double_a_single (v
)
7979 && is_quarter_float (double_to_single (v
)))
7981 inst
.operands
[1].imm
=
7982 neon_qfloat_bits (double_to_single (v
));
7983 do_vfp_nsyn_opcode ("fconstd");
7991 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
7992 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
7995 inst
.operands
[1].reg
= REG_PC
;
7996 inst
.operands
[1].isreg
= 1;
7997 inst
.operands
[1].preind
= 1;
7998 inst
.reloc
.pc_rel
= 1;
7999 inst
.reloc
.type
= (thumb_p
8000 ? BFD_RELOC_ARM_THUMB_OFFSET
8002 ? BFD_RELOC_ARM_HWLITERAL
8003 : BFD_RELOC_ARM_LITERAL
));
8007 /* inst.operands[i] was set up by parse_address. Encode it into an
8008 ARM-format instruction. Reject all forms which cannot be encoded
8009 into a coprocessor load/store instruction. If wb_ok is false,
8010 reject use of writeback; if unind_ok is false, reject use of
8011 unindexed addressing. If reloc_override is not 0, use it instead
8012 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8013 (in which case it is preserved). */
8016 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8018 if (!inst
.operands
[i
].isreg
)
8021 if (! inst
.operands
[0].isvec
)
8023 inst
.error
= _("invalid co-processor operand");
8026 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8030 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8032 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8034 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8036 gas_assert (!inst
.operands
[i
].writeback
);
8039 inst
.error
= _("instruction does not support unindexed addressing");
8042 inst
.instruction
|= inst
.operands
[i
].imm
;
8043 inst
.instruction
|= INDEX_UP
;
8047 if (inst
.operands
[i
].preind
)
8048 inst
.instruction
|= PRE_INDEX
;
8050 if (inst
.operands
[i
].writeback
)
8052 if (inst
.operands
[i
].reg
== REG_PC
)
8054 inst
.error
= _("pc may not be used with write-back");
8059 inst
.error
= _("instruction does not support writeback");
8062 inst
.instruction
|= WRITE_BACK
;
8066 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8067 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8068 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8069 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8072 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8074 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8077 /* Prefer + for zero encoded value. */
8078 if (!inst
.operands
[i
].negative
)
8079 inst
.instruction
|= INDEX_UP
;
8084 /* Functions for instruction encoding, sorted by sub-architecture.
8085 First some generics; their names are taken from the conventional
8086 bit positions for register arguments in ARM format instructions. */
8096 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8102 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8103 inst
.instruction
|= inst
.operands
[1].reg
;
8109 inst
.instruction
|= inst
.operands
[0].reg
;
8110 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8117 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8123 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8124 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8128 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8130 if (ARM_CPU_IS_ANY (cpu_variant
))
8132 as_tsktsk ("%s", msg
);
8135 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8147 unsigned Rn
= inst
.operands
[2].reg
;
8148 /* Enforce restrictions on SWP instruction. */
8149 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8151 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8152 _("Rn must not overlap other operands"));
8154 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8156 if (!check_obsolete (&arm_ext_v8
,
8157 _("swp{b} use is obsoleted for ARMv8 and later"))
8158 && warn_on_deprecated
8159 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8160 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8163 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8164 inst
.instruction
|= inst
.operands
[1].reg
;
8165 inst
.instruction
|= Rn
<< 16;
8171 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8172 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8173 inst
.instruction
|= inst
.operands
[2].reg
;
8179 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8180 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8181 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8182 || inst
.reloc
.exp
.X_add_number
!= 0),
8184 inst
.instruction
|= inst
.operands
[0].reg
;
8185 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8186 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8192 inst
.instruction
|= inst
.operands
[0].imm
;
8198 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8199 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8202 /* ARM instructions, in alphabetical order by function name (except
8203 that wrapper functions appear immediately after the function they
8206 /* This is a pseudo-op of the form "adr rd, label" to be converted
8207 into a relative address of the form "add rd, pc, #label-.-8". */
8212 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8214 /* Frag hacking will turn this into a sub instruction if the offset turns
8215 out to be negative. */
8216 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8217 inst
.reloc
.pc_rel
= 1;
8218 inst
.reloc
.exp
.X_add_number
-= 8;
8221 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8222 into a relative address of the form:
8223 add rd, pc, #low(label-.-8)"
8224 add rd, rd, #high(label-.-8)" */
8229 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8231 /* Frag hacking will turn this into a sub instruction if the offset turns
8232 out to be negative. */
8233 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8234 inst
.reloc
.pc_rel
= 1;
8235 inst
.size
= INSN_SIZE
* 2;
8236 inst
.reloc
.exp
.X_add_number
-= 8;
8242 if (!inst
.operands
[1].present
)
8243 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8245 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8246 encode_arm_shifter_operand (2);
8252 if (inst
.operands
[0].present
)
8253 inst
.instruction
|= inst
.operands
[0].imm
;
8255 inst
.instruction
|= 0xf;
8261 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8262 constraint (msb
> 32, _("bit-field extends past end of register"));
8263 /* The instruction encoding stores the LSB and MSB,
8264 not the LSB and width. */
8265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8266 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8267 inst
.instruction
|= (msb
- 1) << 16;
8275 /* #0 in second position is alternative syntax for bfc, which is
8276 the same instruction but with REG_PC in the Rm field. */
8277 if (!inst
.operands
[1].isreg
)
8278 inst
.operands
[1].reg
= REG_PC
;
8280 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8281 constraint (msb
> 32, _("bit-field extends past end of register"));
8282 /* The instruction encoding stores the LSB and MSB,
8283 not the LSB and width. */
8284 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8285 inst
.instruction
|= inst
.operands
[1].reg
;
8286 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8287 inst
.instruction
|= (msb
- 1) << 16;
8293 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8294 _("bit-field extends past end of register"));
8295 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8296 inst
.instruction
|= inst
.operands
[1].reg
;
8297 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8298 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8301 /* ARM V5 breakpoint instruction (argument parse)
8302 BKPT <16 bit unsigned immediate>
8303 Instruction is not conditional.
8304 The bit pattern given in insns[] has the COND_ALWAYS condition,
8305 and it is an error if the caller tried to override that. */
8310 /* Top 12 of 16 bits to bits 19:8. */
8311 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8313 /* Bottom 4 of 16 bits to bits 3:0. */
8314 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8318 encode_branch (int default_reloc
)
8320 if (inst
.operands
[0].hasreloc
)
8322 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8323 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8324 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8325 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8326 ? BFD_RELOC_ARM_PLT32
8327 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8330 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8331 inst
.reloc
.pc_rel
= 1;
8338 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8339 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8342 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8349 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8351 if (inst
.cond
== COND_ALWAYS
)
8352 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8354 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8358 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8361 /* ARM V5 branch-link-exchange instruction (argument parse)
8362 BLX <target_addr> ie BLX(1)
8363 BLX{<condition>} <Rm> ie BLX(2)
8364 Unfortunately, there are two different opcodes for this mnemonic.
8365 So, the insns[].value is not used, and the code here zaps values
8366 into inst.instruction.
8367 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8372 if (inst
.operands
[0].isreg
)
8374 /* Arg is a register; the opcode provided by insns[] is correct.
8375 It is not illegal to do "blx pc", just useless. */
8376 if (inst
.operands
[0].reg
== REG_PC
)
8377 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8379 inst
.instruction
|= inst
.operands
[0].reg
;
8383 /* Arg is an address; this instruction cannot be executed
8384 conditionally, and the opcode must be adjusted.
8385 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8386 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8387 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8388 inst
.instruction
= 0xfa000000;
8389 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8396 bfd_boolean want_reloc
;
8398 if (inst
.operands
[0].reg
== REG_PC
)
8399 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8401 inst
.instruction
|= inst
.operands
[0].reg
;
8402 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8403 it is for ARMv4t or earlier. */
8404 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8405 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8409 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8414 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8418 /* ARM v5TEJ. Jump to Jazelle code. */
8423 if (inst
.operands
[0].reg
== REG_PC
)
8424 as_tsktsk (_("use of r15 in bxj is not really useful"));
8426 inst
.instruction
|= inst
.operands
[0].reg
;
8429 /* Co-processor data operation:
8430 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8431 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8435 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8436 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8437 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8438 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8439 inst
.instruction
|= inst
.operands
[4].reg
;
8440 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8446 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8447 encode_arm_shifter_operand (1);
8450 /* Transfer between coprocessor and ARM registers.
8451 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8456 No special properties. */
8458 struct deprecated_coproc_regs_s
8465 arm_feature_set deprecated
;
8466 arm_feature_set obsoleted
;
8467 const char *dep_msg
;
8468 const char *obs_msg
;
8471 #define DEPR_ACCESS_V8 \
8472 N_("This coprocessor register access is deprecated in ARMv8")
8474 /* Table of all deprecated coprocessor registers. */
8475 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8477 {15, 0, 7, 10, 5, /* CP15DMB. */
8478 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8479 DEPR_ACCESS_V8
, NULL
},
8480 {15, 0, 7, 10, 4, /* CP15DSB. */
8481 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8482 DEPR_ACCESS_V8
, NULL
},
8483 {15, 0, 7, 5, 4, /* CP15ISB. */
8484 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8485 DEPR_ACCESS_V8
, NULL
},
8486 {14, 6, 1, 0, 0, /* TEEHBR. */
8487 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8488 DEPR_ACCESS_V8
, NULL
},
8489 {14, 6, 0, 0, 0, /* TEECR. */
8490 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8491 DEPR_ACCESS_V8
, NULL
},
8494 #undef DEPR_ACCESS_V8
8496 static const size_t deprecated_coproc_reg_count
=
8497 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8505 Rd
= inst
.operands
[2].reg
;
8508 if (inst
.instruction
== 0xee000010
8509 || inst
.instruction
== 0xfe000010)
8511 reject_bad_reg (Rd
);
8514 constraint (Rd
== REG_SP
, BAD_SP
);
8519 if (inst
.instruction
== 0xe000010)
8520 constraint (Rd
== REG_PC
, BAD_PC
);
8523 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8525 const struct deprecated_coproc_regs_s
*r
=
8526 deprecated_coproc_regs
+ i
;
8528 if (inst
.operands
[0].reg
== r
->cp
8529 && inst
.operands
[1].imm
== r
->opc1
8530 && inst
.operands
[3].reg
== r
->crn
8531 && inst
.operands
[4].reg
== r
->crm
8532 && inst
.operands
[5].imm
== r
->opc2
)
8534 if (! ARM_CPU_IS_ANY (cpu_variant
)
8535 && warn_on_deprecated
8536 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8537 as_tsktsk ("%s", r
->dep_msg
);
8541 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8542 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8543 inst
.instruction
|= Rd
<< 12;
8544 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8545 inst
.instruction
|= inst
.operands
[4].reg
;
8546 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8549 /* Transfer between coprocessor register and pair of ARM registers.
8550 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8555 Two XScale instructions are special cases of these:
8557 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8558 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8560 Result unpredictable if Rd or Rn is R15. */
8567 Rd
= inst
.operands
[2].reg
;
8568 Rn
= inst
.operands
[3].reg
;
8572 reject_bad_reg (Rd
);
8573 reject_bad_reg (Rn
);
8577 constraint (Rd
== REG_PC
, BAD_PC
);
8578 constraint (Rn
== REG_PC
, BAD_PC
);
8581 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8582 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8583 inst
.instruction
|= Rd
<< 12;
8584 inst
.instruction
|= Rn
<< 16;
8585 inst
.instruction
|= inst
.operands
[4].reg
;
8591 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8592 if (inst
.operands
[1].present
)
8594 inst
.instruction
|= CPSI_MMOD
;
8595 inst
.instruction
|= inst
.operands
[1].imm
;
8602 inst
.instruction
|= inst
.operands
[0].imm
;
8608 unsigned Rd
, Rn
, Rm
;
8610 Rd
= inst
.operands
[0].reg
;
8611 Rn
= (inst
.operands
[1].present
8612 ? inst
.operands
[1].reg
: Rd
);
8613 Rm
= inst
.operands
[2].reg
;
8615 constraint ((Rd
== REG_PC
), BAD_PC
);
8616 constraint ((Rn
== REG_PC
), BAD_PC
);
8617 constraint ((Rm
== REG_PC
), BAD_PC
);
8619 inst
.instruction
|= Rd
<< 16;
8620 inst
.instruction
|= Rn
<< 0;
8621 inst
.instruction
|= Rm
<< 8;
8627 /* There is no IT instruction in ARM mode. We
8628 process it to do the validation as if in
8629 thumb mode, just in case the code gets
8630 assembled for thumb using the unified syntax. */
8635 set_it_insn_type (IT_INSN
);
8636 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8637 now_it
.cc
= inst
.operands
[0].imm
;
8641 /* If there is only one register in the register list,
8642 then return its register number. Otherwise return -1. */
8644 only_one_reg_in_list (int range
)
8646 int i
= ffs (range
) - 1;
8647 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8651 encode_ldmstm(int from_push_pop_mnem
)
8653 int base_reg
= inst
.operands
[0].reg
;
8654 int range
= inst
.operands
[1].imm
;
8657 inst
.instruction
|= base_reg
<< 16;
8658 inst
.instruction
|= range
;
8660 if (inst
.operands
[1].writeback
)
8661 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8663 if (inst
.operands
[0].writeback
)
8665 inst
.instruction
|= WRITE_BACK
;
8666 /* Check for unpredictable uses of writeback. */
8667 if (inst
.instruction
& LOAD_BIT
)
8669 /* Not allowed in LDM type 2. */
8670 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8671 && ((range
& (1 << REG_PC
)) == 0))
8672 as_warn (_("writeback of base register is UNPREDICTABLE"));
8673 /* Only allowed if base reg not in list for other types. */
8674 else if (range
& (1 << base_reg
))
8675 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8679 /* Not allowed for type 2. */
8680 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8681 as_warn (_("writeback of base register is UNPREDICTABLE"));
8682 /* Only allowed if base reg not in list, or first in list. */
8683 else if ((range
& (1 << base_reg
))
8684 && (range
& ((1 << base_reg
) - 1)))
8685 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8689 /* If PUSH/POP has only one register, then use the A2 encoding. */
8690 one_reg
= only_one_reg_in_list (range
);
8691 if (from_push_pop_mnem
&& one_reg
>= 0)
8693 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8695 inst
.instruction
&= A_COND_MASK
;
8696 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8697 inst
.instruction
|= one_reg
<< 12;
8704 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8707 /* ARMv5TE load-consecutive (argument parse)
8716 constraint (inst
.operands
[0].reg
% 2 != 0,
8717 _("first transfer register must be even"));
8718 constraint (inst
.operands
[1].present
8719 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8720 _("can only transfer two consecutive registers"));
8721 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8722 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8724 if (!inst
.operands
[1].present
)
8725 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8727 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8728 register and the first register written; we have to diagnose
8729 overlap between the base and the second register written here. */
8731 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8732 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8733 as_warn (_("base register written back, and overlaps "
8734 "second transfer register"));
8736 if (!(inst
.instruction
& V4_STR_BIT
))
8738 /* For an index-register load, the index register must not overlap the
8739 destination (even if not write-back). */
8740 if (inst
.operands
[2].immisreg
8741 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8742 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8743 as_warn (_("index register overlaps transfer register"));
8745 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8746 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8752 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8753 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8754 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8755 || inst
.operands
[1].negative
8756 /* This can arise if the programmer has written
8758 or if they have mistakenly used a register name as the last
8761 It is very difficult to distinguish between these two cases
8762 because "rX" might actually be a label. ie the register
8763 name has been occluded by a symbol of the same name. So we
8764 just generate a general 'bad addressing mode' type error
8765 message and leave it up to the programmer to discover the
8766 true cause and fix their mistake. */
8767 || (inst
.operands
[1].reg
== REG_PC
),
8770 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8771 || inst
.reloc
.exp
.X_add_number
!= 0,
8772 _("offset must be zero in ARM encoding"));
8774 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8776 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8777 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8778 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8784 constraint (inst
.operands
[0].reg
% 2 != 0,
8785 _("even register required"));
8786 constraint (inst
.operands
[1].present
8787 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8788 _("can only load two consecutive registers"));
8789 /* If op 1 were present and equal to PC, this function wouldn't
8790 have been called in the first place. */
8791 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8793 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8794 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8797 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8798 which is not a multiple of four is UNPREDICTABLE. */
8800 check_ldr_r15_aligned (void)
8802 constraint (!(inst
.operands
[1].immisreg
)
8803 && (inst
.operands
[0].reg
== REG_PC
8804 && inst
.operands
[1].reg
== REG_PC
8805 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8806 _("ldr to register 15 must be 4-byte alligned"));
8812 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8813 if (!inst
.operands
[1].isreg
)
8814 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8816 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8817 check_ldr_r15_aligned ();
8823 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8825 if (inst
.operands
[1].preind
)
8827 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8828 || inst
.reloc
.exp
.X_add_number
!= 0,
8829 _("this instruction requires a post-indexed address"));
8831 inst
.operands
[1].preind
= 0;
8832 inst
.operands
[1].postind
= 1;
8833 inst
.operands
[1].writeback
= 1;
8835 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8836 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8839 /* Halfword and signed-byte load/store operations. */
8844 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8845 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8846 if (!inst
.operands
[1].isreg
)
8847 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8849 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8855 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8857 if (inst
.operands
[1].preind
)
8859 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8860 || inst
.reloc
.exp
.X_add_number
!= 0,
8861 _("this instruction requires a post-indexed address"));
8863 inst
.operands
[1].preind
= 0;
8864 inst
.operands
[1].postind
= 1;
8865 inst
.operands
[1].writeback
= 1;
8867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8868 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8871 /* Co-processor register load/store.
8872 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8876 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8877 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8878 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8884 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8885 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8886 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8887 && !(inst
.instruction
& 0x00400000))
8888 as_tsktsk (_("Rd and Rm should be different in mla"));
8890 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8891 inst
.instruction
|= inst
.operands
[1].reg
;
8892 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8893 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8899 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8900 encode_arm_shifter_operand (1);
8903 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8910 top
= (inst
.instruction
& 0x00400000) != 0;
8911 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8912 _(":lower16: not allowed this instruction"));
8913 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8914 _(":upper16: not allowed instruction"));
8915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8916 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8918 imm
= inst
.reloc
.exp
.X_add_number
;
8919 /* The value is in two pieces: 0:11, 16:19. */
8920 inst
.instruction
|= (imm
& 0x00000fff);
8921 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8926 do_vfp_nsyn_mrs (void)
8928 if (inst
.operands
[0].isvec
)
8930 if (inst
.operands
[1].reg
!= 1)
8931 first_error (_("operand 1 must be FPSCR"));
8932 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8933 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8934 do_vfp_nsyn_opcode ("fmstat");
8936 else if (inst
.operands
[1].isvec
)
8937 do_vfp_nsyn_opcode ("fmrx");
8945 do_vfp_nsyn_msr (void)
8947 if (inst
.operands
[0].isvec
)
8948 do_vfp_nsyn_opcode ("fmxr");
8958 unsigned Rt
= inst
.operands
[0].reg
;
8960 if (thumb_mode
&& Rt
== REG_SP
)
8962 inst
.error
= BAD_SP
;
8966 /* APSR_ sets isvec. All other refs to PC are illegal. */
8967 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8969 inst
.error
= BAD_PC
;
8973 /* If we get through parsing the register name, we just insert the number
8974 generated into the instruction without further validation. */
8975 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8976 inst
.instruction
|= (Rt
<< 12);
8982 unsigned Rt
= inst
.operands
[1].reg
;
8985 reject_bad_reg (Rt
);
8986 else if (Rt
== REG_PC
)
8988 inst
.error
= BAD_PC
;
8992 /* If we get through parsing the register name, we just insert the number
8993 generated into the instruction without further validation. */
8994 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
8995 inst
.instruction
|= (Rt
<< 12);
9003 if (do_vfp_nsyn_mrs () == SUCCESS
)
9006 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9009 if (inst
.operands
[1].isreg
)
9011 br
= inst
.operands
[1].reg
;
9012 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9013 as_bad (_("bad register for mrs"));
9017 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9018 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9020 _("'APSR', 'CPSR' or 'SPSR' expected"));
9021 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9024 inst
.instruction
|= br
;
9027 /* Two possible forms:
9028 "{C|S}PSR_<field>, Rm",
9029 "{C|S}PSR_f, #expression". */
9034 if (do_vfp_nsyn_msr () == SUCCESS
)
9037 inst
.instruction
|= inst
.operands
[0].imm
;
9038 if (inst
.operands
[1].isreg
)
9039 inst
.instruction
|= inst
.operands
[1].reg
;
9042 inst
.instruction
|= INST_IMMEDIATE
;
9043 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9044 inst
.reloc
.pc_rel
= 0;
9051 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9053 if (!inst
.operands
[2].present
)
9054 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9055 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9056 inst
.instruction
|= inst
.operands
[1].reg
;
9057 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9059 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9060 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9061 as_tsktsk (_("Rd and Rm should be different in mul"));
9064 /* Long Multiply Parser
9065 UMULL RdLo, RdHi, Rm, Rs
9066 SMULL RdLo, RdHi, Rm, Rs
9067 UMLAL RdLo, RdHi, Rm, Rs
9068 SMLAL RdLo, RdHi, Rm, Rs. */
9073 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9074 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9075 inst
.instruction
|= inst
.operands
[2].reg
;
9076 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9078 /* rdhi and rdlo must be different. */
9079 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9080 as_tsktsk (_("rdhi and rdlo must be different"));
9082 /* rdhi, rdlo and rm must all be different before armv6. */
9083 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9084 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9085 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9086 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9092 if (inst
.operands
[0].present
9093 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9095 /* Architectural NOP hints are CPSR sets with no bits selected. */
9096 inst
.instruction
&= 0xf0000000;
9097 inst
.instruction
|= 0x0320f000;
9098 if (inst
.operands
[0].present
)
9099 inst
.instruction
|= inst
.operands
[0].imm
;
9103 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9104 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9105 Condition defaults to COND_ALWAYS.
9106 Error if Rd, Rn or Rm are R15. */
9111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9112 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9113 inst
.instruction
|= inst
.operands
[2].reg
;
9114 if (inst
.operands
[3].present
)
9115 encode_arm_shift (3);
9118 /* ARM V6 PKHTB (Argument Parse). */
9123 if (!inst
.operands
[3].present
)
9125 /* If the shift specifier is omitted, turn the instruction
9126 into pkhbt rd, rm, rn. */
9127 inst
.instruction
&= 0xfff00010;
9128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9129 inst
.instruction
|= inst
.operands
[1].reg
;
9130 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9134 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9135 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9136 inst
.instruction
|= inst
.operands
[2].reg
;
9137 encode_arm_shift (3);
9141 /* ARMv5TE: Preload-Cache
9142 MP Extensions: Preload for write
9146 Syntactically, like LDR with B=1, W=0, L=1. */
9151 constraint (!inst
.operands
[0].isreg
,
9152 _("'[' expected after PLD mnemonic"));
9153 constraint (inst
.operands
[0].postind
,
9154 _("post-indexed expression used in preload instruction"));
9155 constraint (inst
.operands
[0].writeback
,
9156 _("writeback used in preload instruction"));
9157 constraint (!inst
.operands
[0].preind
,
9158 _("unindexed addressing used in preload instruction"));
9159 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9162 /* ARMv7: PLI <addr_mode> */
9166 constraint (!inst
.operands
[0].isreg
,
9167 _("'[' expected after PLI mnemonic"));
9168 constraint (inst
.operands
[0].postind
,
9169 _("post-indexed expression used in preload instruction"));
9170 constraint (inst
.operands
[0].writeback
,
9171 _("writeback used in preload instruction"));
9172 constraint (!inst
.operands
[0].preind
,
9173 _("unindexed addressing used in preload instruction"));
9174 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9175 inst
.instruction
&= ~PRE_INDEX
;
9181 constraint (inst
.operands
[0].writeback
,
9182 _("push/pop do not support {reglist}^"));
9183 inst
.operands
[1] = inst
.operands
[0];
9184 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9185 inst
.operands
[0].isreg
= 1;
9186 inst
.operands
[0].writeback
= 1;
9187 inst
.operands
[0].reg
= REG_SP
;
9188 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9191 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9192 word at the specified address and the following word
9194 Unconditionally executed.
9195 Error if Rn is R15. */
9200 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9201 if (inst
.operands
[0].writeback
)
9202 inst
.instruction
|= WRITE_BACK
;
9205 /* ARM V6 ssat (argument parse). */
9210 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9211 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9212 inst
.instruction
|= inst
.operands
[2].reg
;
9214 if (inst
.operands
[3].present
)
9215 encode_arm_shift (3);
9218 /* ARM V6 usat (argument parse). */
9223 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9224 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9225 inst
.instruction
|= inst
.operands
[2].reg
;
9227 if (inst
.operands
[3].present
)
9228 encode_arm_shift (3);
9231 /* ARM V6 ssat16 (argument parse). */
9236 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9237 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9238 inst
.instruction
|= inst
.operands
[2].reg
;
9244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9245 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9246 inst
.instruction
|= inst
.operands
[2].reg
;
9249 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9250 preserving the other bits.
9252 setend <endian_specifier>, where <endian_specifier> is either
9258 if (warn_on_deprecated
9259 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9260 as_tsktsk (_("setend use is deprecated for ARMv8"));
9262 if (inst
.operands
[0].imm
)
9263 inst
.instruction
|= 0x200;
9269 unsigned int Rm
= (inst
.operands
[1].present
9270 ? inst
.operands
[1].reg
9271 : inst
.operands
[0].reg
);
9273 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9274 inst
.instruction
|= Rm
;
9275 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9277 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9278 inst
.instruction
|= SHIFT_BY_REG
;
9279 /* PR 12854: Error on extraneous shifts. */
9280 constraint (inst
.operands
[2].shifted
,
9281 _("extraneous shift as part of operand to shift insn"));
9284 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9290 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9291 inst
.reloc
.pc_rel
= 0;
9297 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9298 inst
.reloc
.pc_rel
= 0;
9304 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9305 inst
.reloc
.pc_rel
= 0;
9311 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9312 _("selected processor does not support SETPAN instruction"));
9314 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9320 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9321 _("selected processor does not support SETPAN instruction"));
9323 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9326 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9327 SMLAxy{cond} Rd,Rm,Rs,Rn
9328 SMLAWy{cond} Rd,Rm,Rs,Rn
9329 Error if any register is R15. */
9334 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9335 inst
.instruction
|= inst
.operands
[1].reg
;
9336 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9337 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9340 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9341 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9342 Error if any register is R15.
9343 Warning if Rdlo == Rdhi. */
9348 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9349 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9350 inst
.instruction
|= inst
.operands
[2].reg
;
9351 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9353 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9354 as_tsktsk (_("rdhi and rdlo must be different"));
9357 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9358 SMULxy{cond} Rd,Rm,Rs
9359 Error if any register is R15. */
9364 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9365 inst
.instruction
|= inst
.operands
[1].reg
;
9366 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9369 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9370 the same for both ARM and Thumb-2. */
9377 if (inst
.operands
[0].present
)
9379 reg
= inst
.operands
[0].reg
;
9380 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9385 inst
.instruction
|= reg
<< 16;
9386 inst
.instruction
|= inst
.operands
[1].imm
;
9387 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9388 inst
.instruction
|= WRITE_BACK
;
9391 /* ARM V6 strex (argument parse). */
9396 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9397 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9398 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9399 || inst
.operands
[2].negative
9400 /* See comment in do_ldrex(). */
9401 || (inst
.operands
[2].reg
== REG_PC
),
9404 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9405 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9407 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9408 || inst
.reloc
.exp
.X_add_number
!= 0,
9409 _("offset must be zero in ARM encoding"));
9411 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9412 inst
.instruction
|= inst
.operands
[1].reg
;
9413 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9414 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9420 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9421 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9422 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9423 || inst
.operands
[2].negative
,
9426 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9427 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9435 constraint (inst
.operands
[1].reg
% 2 != 0,
9436 _("even register required"));
9437 constraint (inst
.operands
[2].present
9438 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9439 _("can only store two consecutive registers"));
9440 /* If op 2 were present and equal to PC, this function wouldn't
9441 have been called in the first place. */
9442 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9444 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9445 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9446 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9449 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9450 inst
.instruction
|= inst
.operands
[1].reg
;
9451 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9458 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9459 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9467 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9468 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9473 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9474 extends it to 32-bits, and adds the result to a value in another
9475 register. You can specify a rotation by 0, 8, 16, or 24 bits
9476 before extracting the 16-bit value.
9477 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9478 Condition defaults to COND_ALWAYS.
9479 Error if any register uses R15. */
9484 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9485 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9486 inst
.instruction
|= inst
.operands
[2].reg
;
9487 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9492 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9493 Condition defaults to COND_ALWAYS.
9494 Error if any register uses R15. */
9499 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9500 inst
.instruction
|= inst
.operands
[1].reg
;
9501 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9504 /* VFP instructions. In a logical order: SP variant first, monad
9505 before dyad, arithmetic then move then load/store. */
9508 do_vfp_sp_monadic (void)
9510 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9511 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9515 do_vfp_sp_dyadic (void)
9517 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9518 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9519 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9523 do_vfp_sp_compare_z (void)
9525 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9529 do_vfp_dp_sp_cvt (void)
9531 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9532 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9536 do_vfp_sp_dp_cvt (void)
9538 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9539 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9543 do_vfp_reg_from_sp (void)
9545 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9546 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9550 do_vfp_reg2_from_sp2 (void)
9552 constraint (inst
.operands
[2].imm
!= 2,
9553 _("only two consecutive VFP SP registers allowed here"));
9554 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9555 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9556 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9560 do_vfp_sp_from_reg (void)
9562 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9563 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9567 do_vfp_sp2_from_reg2 (void)
9569 constraint (inst
.operands
[0].imm
!= 2,
9570 _("only two consecutive VFP SP registers allowed here"));
9571 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9572 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9573 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9577 do_vfp_sp_ldst (void)
9579 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9580 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9584 do_vfp_dp_ldst (void)
9586 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9587 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9592 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9594 if (inst
.operands
[0].writeback
)
9595 inst
.instruction
|= WRITE_BACK
;
9597 constraint (ldstm_type
!= VFP_LDSTMIA
,
9598 _("this addressing mode requires base-register writeback"));
9599 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9600 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9601 inst
.instruction
|= inst
.operands
[1].imm
;
9605 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9609 if (inst
.operands
[0].writeback
)
9610 inst
.instruction
|= WRITE_BACK
;
9612 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9613 _("this addressing mode requires base-register writeback"));
9615 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9616 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9618 count
= inst
.operands
[1].imm
<< 1;
9619 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9622 inst
.instruction
|= count
;
9626 do_vfp_sp_ldstmia (void)
9628 vfp_sp_ldstm (VFP_LDSTMIA
);
9632 do_vfp_sp_ldstmdb (void)
9634 vfp_sp_ldstm (VFP_LDSTMDB
);
9638 do_vfp_dp_ldstmia (void)
9640 vfp_dp_ldstm (VFP_LDSTMIA
);
9644 do_vfp_dp_ldstmdb (void)
9646 vfp_dp_ldstm (VFP_LDSTMDB
);
9650 do_vfp_xp_ldstmia (void)
9652 vfp_dp_ldstm (VFP_LDSTMIAX
);
9656 do_vfp_xp_ldstmdb (void)
9658 vfp_dp_ldstm (VFP_LDSTMDBX
);
9662 do_vfp_dp_rd_rm (void)
9664 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9665 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9669 do_vfp_dp_rn_rd (void)
9671 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9672 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9676 do_vfp_dp_rd_rn (void)
9678 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9679 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9683 do_vfp_dp_rd_rn_rm (void)
9685 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9686 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9687 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9693 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9697 do_vfp_dp_rm_rd_rn (void)
9699 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9700 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9701 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9704 /* VFPv3 instructions. */
9706 do_vfp_sp_const (void)
9708 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9709 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9710 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9714 do_vfp_dp_const (void)
9716 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9717 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9718 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9722 vfp_conv (int srcsize
)
9724 int immbits
= srcsize
- inst
.operands
[1].imm
;
9726 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9728 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9729 i.e. immbits must be in range 0 - 16. */
9730 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9733 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9735 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9736 i.e. immbits must be in range 0 - 31. */
9737 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9741 inst
.instruction
|= (immbits
& 1) << 5;
9742 inst
.instruction
|= (immbits
>> 1);
9746 do_vfp_sp_conv_16 (void)
9748 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9753 do_vfp_dp_conv_16 (void)
9755 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9760 do_vfp_sp_conv_32 (void)
9762 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9767 do_vfp_dp_conv_32 (void)
9769 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9773 /* FPA instructions. Also in a logical order. */
9778 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9779 inst
.instruction
|= inst
.operands
[1].reg
;
9783 do_fpa_ldmstm (void)
9785 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9786 switch (inst
.operands
[1].imm
)
9788 case 1: inst
.instruction
|= CP_T_X
; break;
9789 case 2: inst
.instruction
|= CP_T_Y
; break;
9790 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9795 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9797 /* The instruction specified "ea" or "fd", so we can only accept
9798 [Rn]{!}. The instruction does not really support stacking or
9799 unstacking, so we have to emulate these by setting appropriate
9800 bits and offsets. */
9801 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9802 || inst
.reloc
.exp
.X_add_number
!= 0,
9803 _("this instruction does not support indexing"));
9805 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9806 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9808 if (!(inst
.instruction
& INDEX_UP
))
9809 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9811 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9813 inst
.operands
[2].preind
= 0;
9814 inst
.operands
[2].postind
= 1;
9818 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9821 /* iWMMXt instructions: strictly in alphabetical order. */
9824 do_iwmmxt_tandorc (void)
9826 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9830 do_iwmmxt_textrc (void)
9832 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9833 inst
.instruction
|= inst
.operands
[1].imm
;
9837 do_iwmmxt_textrm (void)
9839 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9840 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9841 inst
.instruction
|= inst
.operands
[2].imm
;
9845 do_iwmmxt_tinsr (void)
9847 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9848 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9849 inst
.instruction
|= inst
.operands
[2].imm
;
9853 do_iwmmxt_tmia (void)
9855 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9856 inst
.instruction
|= inst
.operands
[1].reg
;
9857 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9861 do_iwmmxt_waligni (void)
9863 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9864 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9865 inst
.instruction
|= inst
.operands
[2].reg
;
9866 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9870 do_iwmmxt_wmerge (void)
9872 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9873 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9874 inst
.instruction
|= inst
.operands
[2].reg
;
9875 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9879 do_iwmmxt_wmov (void)
9881 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9882 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9883 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9884 inst
.instruction
|= inst
.operands
[1].reg
;
9888 do_iwmmxt_wldstbh (void)
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9893 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9895 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9896 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9900 do_iwmmxt_wldstw (void)
9902 /* RIWR_RIWC clears .isreg for a control register. */
9903 if (!inst
.operands
[0].isreg
)
9905 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9906 inst
.instruction
|= 0xf0000000;
9909 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9910 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9914 do_iwmmxt_wldstd (void)
9916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9917 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9918 && inst
.operands
[1].immisreg
)
9920 inst
.instruction
&= ~0x1a000ff;
9921 inst
.instruction
|= (0xfU
<< 28);
9922 if (inst
.operands
[1].preind
)
9923 inst
.instruction
|= PRE_INDEX
;
9924 if (!inst
.operands
[1].negative
)
9925 inst
.instruction
|= INDEX_UP
;
9926 if (inst
.operands
[1].writeback
)
9927 inst
.instruction
|= WRITE_BACK
;
9928 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9929 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9930 inst
.instruction
|= inst
.operands
[1].imm
;
9933 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9937 do_iwmmxt_wshufh (void)
9939 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9940 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9941 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9942 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9946 do_iwmmxt_wzero (void)
9948 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9949 inst
.instruction
|= inst
.operands
[0].reg
;
9950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9951 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9955 do_iwmmxt_wrwrwr_or_imm5 (void)
9957 if (inst
.operands
[2].isreg
)
9960 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9961 _("immediate operand requires iWMMXt2"));
9963 if (inst
.operands
[2].imm
== 0)
9965 switch ((inst
.instruction
>> 20) & 0xf)
9971 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9972 inst
.operands
[2].imm
= 16;
9973 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9979 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9980 inst
.operands
[2].imm
= 32;
9981 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9988 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9990 wrn
= (inst
.instruction
>> 16) & 0xf;
9991 inst
.instruction
&= 0xff0fff0f;
9992 inst
.instruction
|= wrn
;
9993 /* Bail out here; the instruction is now assembled. */
9998 /* Map 32 -> 0, etc. */
9999 inst
.operands
[2].imm
&= 0x1f;
10000 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10004 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10005 operations first, then control, shift, and load/store. */
10007 /* Insns like "foo X,Y,Z". */
10010 do_mav_triple (void)
10012 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10013 inst
.instruction
|= inst
.operands
[1].reg
;
10014 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10017 /* Insns like "foo W,X,Y,Z".
10018 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10023 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10024 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10025 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10026 inst
.instruction
|= inst
.operands
[3].reg
;
10029 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10031 do_mav_dspsc (void)
10033 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10036 /* Maverick shift immediate instructions.
10037 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10038 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10041 do_mav_shift (void)
10043 int imm
= inst
.operands
[2].imm
;
10045 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10046 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10048 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10049 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10050 Bit 4 should be 0. */
10051 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10053 inst
.instruction
|= imm
;
10056 /* XScale instructions. Also sorted arithmetic before move. */
10058 /* Xscale multiply-accumulate (argument parse)
10061 MIAxycc acc0,Rm,Rs. */
10066 inst
.instruction
|= inst
.operands
[1].reg
;
10067 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10070 /* Xscale move-accumulator-register (argument parse)
10072 MARcc acc0,RdLo,RdHi. */
10077 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10078 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10081 /* Xscale move-register-accumulator (argument parse)
10083 MRAcc RdLo,RdHi,acc0. */
10088 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10090 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10093 /* Encoding functions relevant only to Thumb. */
10095 /* inst.operands[i] is a shifted-register operand; encode
10096 it into inst.instruction in the format used by Thumb32. */
10099 encode_thumb32_shifted_operand (int i
)
10101 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10102 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10104 constraint (inst
.operands
[i
].immisreg
,
10105 _("shift by register not allowed in thumb mode"));
10106 inst
.instruction
|= inst
.operands
[i
].reg
;
10107 if (shift
== SHIFT_RRX
)
10108 inst
.instruction
|= SHIFT_ROR
<< 4;
10111 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10112 _("expression too complex"));
10114 constraint (value
> 32
10115 || (value
== 32 && (shift
== SHIFT_LSL
10116 || shift
== SHIFT_ROR
)),
10117 _("shift expression is too large"));
10121 else if (value
== 32)
10124 inst
.instruction
|= shift
<< 4;
10125 inst
.instruction
|= (value
& 0x1c) << 10;
10126 inst
.instruction
|= (value
& 0x03) << 6;
10131 /* inst.operands[i] was set up by parse_address. Encode it into a
10132 Thumb32 format load or store instruction. Reject forms that cannot
10133 be used with such instructions. If is_t is true, reject forms that
10134 cannot be used with a T instruction; if is_d is true, reject forms
10135 that cannot be used with a D instruction. If it is a store insn,
10136 reject PC in Rn. */
10139 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10141 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10143 constraint (!inst
.operands
[i
].isreg
,
10144 _("Instruction does not support =N addresses"));
10146 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10147 if (inst
.operands
[i
].immisreg
)
10149 constraint (is_pc
, BAD_PC_ADDRESSING
);
10150 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10151 constraint (inst
.operands
[i
].negative
,
10152 _("Thumb does not support negative register indexing"));
10153 constraint (inst
.operands
[i
].postind
,
10154 _("Thumb does not support register post-indexing"));
10155 constraint (inst
.operands
[i
].writeback
,
10156 _("Thumb does not support register indexing with writeback"));
10157 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10158 _("Thumb supports only LSL in shifted register indexing"));
10160 inst
.instruction
|= inst
.operands
[i
].imm
;
10161 if (inst
.operands
[i
].shifted
)
10163 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10164 _("expression too complex"));
10165 constraint (inst
.reloc
.exp
.X_add_number
< 0
10166 || inst
.reloc
.exp
.X_add_number
> 3,
10167 _("shift out of range"));
10168 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10170 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10172 else if (inst
.operands
[i
].preind
)
10174 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10175 constraint (is_t
&& inst
.operands
[i
].writeback
,
10176 _("cannot use writeback with this instruction"));
10177 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10178 BAD_PC_ADDRESSING
);
10182 inst
.instruction
|= 0x01000000;
10183 if (inst
.operands
[i
].writeback
)
10184 inst
.instruction
|= 0x00200000;
10188 inst
.instruction
|= 0x00000c00;
10189 if (inst
.operands
[i
].writeback
)
10190 inst
.instruction
|= 0x00000100;
10192 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10194 else if (inst
.operands
[i
].postind
)
10196 gas_assert (inst
.operands
[i
].writeback
);
10197 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10198 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10201 inst
.instruction
|= 0x00200000;
10203 inst
.instruction
|= 0x00000900;
10204 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10206 else /* unindexed - only for coprocessor */
10207 inst
.error
= _("instruction does not accept unindexed addressing");
10210 /* Table of Thumb instructions which exist in both 16- and 32-bit
10211 encodings (the latter only in post-V6T2 cores). The index is the
10212 value used in the insns table below. When there is more than one
10213 possible 16-bit encoding for the instruction, this table always
10215 Also contains several pseudo-instructions used during relaxation. */
10216 #define T16_32_TAB \
10217 X(_adc, 4140, eb400000), \
10218 X(_adcs, 4140, eb500000), \
10219 X(_add, 1c00, eb000000), \
10220 X(_adds, 1c00, eb100000), \
10221 X(_addi, 0000, f1000000), \
10222 X(_addis, 0000, f1100000), \
10223 X(_add_pc,000f, f20f0000), \
10224 X(_add_sp,000d, f10d0000), \
10225 X(_adr, 000f, f20f0000), \
10226 X(_and, 4000, ea000000), \
10227 X(_ands, 4000, ea100000), \
10228 X(_asr, 1000, fa40f000), \
10229 X(_asrs, 1000, fa50f000), \
10230 X(_b, e000, f000b000), \
10231 X(_bcond, d000, f0008000), \
10232 X(_bic, 4380, ea200000), \
10233 X(_bics, 4380, ea300000), \
10234 X(_cmn, 42c0, eb100f00), \
10235 X(_cmp, 2800, ebb00f00), \
10236 X(_cpsie, b660, f3af8400), \
10237 X(_cpsid, b670, f3af8600), \
10238 X(_cpy, 4600, ea4f0000), \
10239 X(_dec_sp,80dd, f1ad0d00), \
10240 X(_eor, 4040, ea800000), \
10241 X(_eors, 4040, ea900000), \
10242 X(_inc_sp,00dd, f10d0d00), \
10243 X(_ldmia, c800, e8900000), \
10244 X(_ldr, 6800, f8500000), \
10245 X(_ldrb, 7800, f8100000), \
10246 X(_ldrh, 8800, f8300000), \
10247 X(_ldrsb, 5600, f9100000), \
10248 X(_ldrsh, 5e00, f9300000), \
10249 X(_ldr_pc,4800, f85f0000), \
10250 X(_ldr_pc2,4800, f85f0000), \
10251 X(_ldr_sp,9800, f85d0000), \
10252 X(_lsl, 0000, fa00f000), \
10253 X(_lsls, 0000, fa10f000), \
10254 X(_lsr, 0800, fa20f000), \
10255 X(_lsrs, 0800, fa30f000), \
10256 X(_mov, 2000, ea4f0000), \
10257 X(_movs, 2000, ea5f0000), \
10258 X(_mul, 4340, fb00f000), \
10259 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10260 X(_mvn, 43c0, ea6f0000), \
10261 X(_mvns, 43c0, ea7f0000), \
10262 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10263 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10264 X(_orr, 4300, ea400000), \
10265 X(_orrs, 4300, ea500000), \
10266 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10267 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10268 X(_rev, ba00, fa90f080), \
10269 X(_rev16, ba40, fa90f090), \
10270 X(_revsh, bac0, fa90f0b0), \
10271 X(_ror, 41c0, fa60f000), \
10272 X(_rors, 41c0, fa70f000), \
10273 X(_sbc, 4180, eb600000), \
10274 X(_sbcs, 4180, eb700000), \
10275 X(_stmia, c000, e8800000), \
10276 X(_str, 6000, f8400000), \
10277 X(_strb, 7000, f8000000), \
10278 X(_strh, 8000, f8200000), \
10279 X(_str_sp,9000, f84d0000), \
10280 X(_sub, 1e00, eba00000), \
10281 X(_subs, 1e00, ebb00000), \
10282 X(_subi, 8000, f1a00000), \
10283 X(_subis, 8000, f1b00000), \
10284 X(_sxtb, b240, fa4ff080), \
10285 X(_sxth, b200, fa0ff080), \
10286 X(_tst, 4200, ea100f00), \
10287 X(_uxtb, b2c0, fa5ff080), \
10288 X(_uxth, b280, fa1ff080), \
10289 X(_nop, bf00, f3af8000), \
10290 X(_yield, bf10, f3af8001), \
10291 X(_wfe, bf20, f3af8002), \
10292 X(_wfi, bf30, f3af8003), \
10293 X(_sev, bf40, f3af8004), \
10294 X(_sevl, bf50, f3af8005), \
10295 X(_udf, de00, f7f0a000)
10297 /* To catch errors in encoding functions, the codes are all offset by
10298 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10299 as 16-bit instructions. */
10300 #define X(a,b,c) T_MNEM##a
10301 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10304 #define X(a,b,c) 0x##b
10305 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10306 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10309 #define X(a,b,c) 0x##c
10310 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10311 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10312 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10316 /* Thumb instruction encoders, in alphabetical order. */
10318 /* ADDW or SUBW. */
10321 do_t_add_sub_w (void)
10325 Rd
= inst
.operands
[0].reg
;
10326 Rn
= inst
.operands
[1].reg
;
10328 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10329 is the SP-{plus,minus}-immediate form of the instruction. */
10331 constraint (Rd
== REG_PC
, BAD_PC
);
10333 reject_bad_reg (Rd
);
10335 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10336 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10339 /* Parse an add or subtract instruction. We get here with inst.instruction
10340 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10343 do_t_add_sub (void)
10347 Rd
= inst
.operands
[0].reg
;
10348 Rs
= (inst
.operands
[1].present
10349 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10350 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10353 set_it_insn_type_last ();
10355 if (unified_syntax
)
10358 bfd_boolean narrow
;
10361 flags
= (inst
.instruction
== T_MNEM_adds
10362 || inst
.instruction
== T_MNEM_subs
);
10364 narrow
= !in_it_block ();
10366 narrow
= in_it_block ();
10367 if (!inst
.operands
[2].isreg
)
10371 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10373 add
= (inst
.instruction
== T_MNEM_add
10374 || inst
.instruction
== T_MNEM_adds
);
10376 if (inst
.size_req
!= 4)
10378 /* Attempt to use a narrow opcode, with relaxation if
10380 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10381 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10382 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10383 opcode
= T_MNEM_add_sp
;
10384 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10385 opcode
= T_MNEM_add_pc
;
10386 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10389 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10391 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10395 inst
.instruction
= THUMB_OP16(opcode
);
10396 inst
.instruction
|= (Rd
<< 4) | Rs
;
10397 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10398 if (inst
.size_req
!= 2)
10399 inst
.relax
= opcode
;
10402 constraint (inst
.size_req
== 2, BAD_HIREG
);
10404 if (inst
.size_req
== 4
10405 || (inst
.size_req
!= 2 && !opcode
))
10409 constraint (add
, BAD_PC
);
10410 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10411 _("only SUBS PC, LR, #const allowed"));
10412 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10413 _("expression too complex"));
10414 constraint (inst
.reloc
.exp
.X_add_number
< 0
10415 || inst
.reloc
.exp
.X_add_number
> 0xff,
10416 _("immediate value out of range"));
10417 inst
.instruction
= T2_SUBS_PC_LR
10418 | inst
.reloc
.exp
.X_add_number
;
10419 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10422 else if (Rs
== REG_PC
)
10424 /* Always use addw/subw. */
10425 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10426 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10430 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10431 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10434 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10436 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10438 inst
.instruction
|= Rd
<< 8;
10439 inst
.instruction
|= Rs
<< 16;
10444 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10445 unsigned int shift
= inst
.operands
[2].shift_kind
;
10447 Rn
= inst
.operands
[2].reg
;
10448 /* See if we can do this with a 16-bit instruction. */
10449 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10451 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10456 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10457 || inst
.instruction
== T_MNEM_add
)
10459 : T_OPCODE_SUB_R3
);
10460 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10464 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10466 /* Thumb-1 cores (except v6-M) require at least one high
10467 register in a narrow non flag setting add. */
10468 if (Rd
> 7 || Rn
> 7
10469 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10470 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10477 inst
.instruction
= T_OPCODE_ADD_HI
;
10478 inst
.instruction
|= (Rd
& 8) << 4;
10479 inst
.instruction
|= (Rd
& 7);
10480 inst
.instruction
|= Rn
<< 3;
10486 constraint (Rd
== REG_PC
, BAD_PC
);
10487 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10488 constraint (Rs
== REG_PC
, BAD_PC
);
10489 reject_bad_reg (Rn
);
10491 /* If we get here, it can't be done in 16 bits. */
10492 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10493 _("shift must be constant"));
10494 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10495 inst
.instruction
|= Rd
<< 8;
10496 inst
.instruction
|= Rs
<< 16;
10497 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10498 _("shift value over 3 not allowed in thumb mode"));
10499 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10500 _("only LSL shift allowed in thumb mode"));
10501 encode_thumb32_shifted_operand (2);
10506 constraint (inst
.instruction
== T_MNEM_adds
10507 || inst
.instruction
== T_MNEM_subs
,
10510 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10512 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10513 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10516 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10517 ? 0x0000 : 0x8000);
10518 inst
.instruction
|= (Rd
<< 4) | Rs
;
10519 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10523 Rn
= inst
.operands
[2].reg
;
10524 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10526 /* We now have Rd, Rs, and Rn set to registers. */
10527 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10529 /* Can't do this for SUB. */
10530 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10531 inst
.instruction
= T_OPCODE_ADD_HI
;
10532 inst
.instruction
|= (Rd
& 8) << 4;
10533 inst
.instruction
|= (Rd
& 7);
10535 inst
.instruction
|= Rn
<< 3;
10537 inst
.instruction
|= Rs
<< 3;
10539 constraint (1, _("dest must overlap one source register"));
10543 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10544 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10545 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10555 Rd
= inst
.operands
[0].reg
;
10556 reject_bad_reg (Rd
);
10558 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10560 /* Defer to section relaxation. */
10561 inst
.relax
= inst
.instruction
;
10562 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10563 inst
.instruction
|= Rd
<< 4;
10565 else if (unified_syntax
&& inst
.size_req
!= 2)
10567 /* Generate a 32-bit opcode. */
10568 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10569 inst
.instruction
|= Rd
<< 8;
10570 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10571 inst
.reloc
.pc_rel
= 1;
10575 /* Generate a 16-bit opcode. */
10576 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10577 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10578 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10579 inst
.reloc
.pc_rel
= 1;
10581 inst
.instruction
|= Rd
<< 4;
10585 /* Arithmetic instructions for which there is just one 16-bit
10586 instruction encoding, and it allows only two low registers.
10587 For maximal compatibility with ARM syntax, we allow three register
10588 operands even when Thumb-32 instructions are not available, as long
10589 as the first two are identical. For instance, both "sbc r0,r1" and
10590 "sbc r0,r0,r1" are allowed. */
10596 Rd
= inst
.operands
[0].reg
;
10597 Rs
= (inst
.operands
[1].present
10598 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10599 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10600 Rn
= inst
.operands
[2].reg
;
10602 reject_bad_reg (Rd
);
10603 reject_bad_reg (Rs
);
10604 if (inst
.operands
[2].isreg
)
10605 reject_bad_reg (Rn
);
10607 if (unified_syntax
)
10609 if (!inst
.operands
[2].isreg
)
10611 /* For an immediate, we always generate a 32-bit opcode;
10612 section relaxation will shrink it later if possible. */
10613 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10614 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10615 inst
.instruction
|= Rd
<< 8;
10616 inst
.instruction
|= Rs
<< 16;
10617 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10621 bfd_boolean narrow
;
10623 /* See if we can do this with a 16-bit instruction. */
10624 if (THUMB_SETS_FLAGS (inst
.instruction
))
10625 narrow
= !in_it_block ();
10627 narrow
= in_it_block ();
10629 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10631 if (inst
.operands
[2].shifted
)
10633 if (inst
.size_req
== 4)
10639 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10640 inst
.instruction
|= Rd
;
10641 inst
.instruction
|= Rn
<< 3;
10645 /* If we get here, it can't be done in 16 bits. */
10646 constraint (inst
.operands
[2].shifted
10647 && inst
.operands
[2].immisreg
,
10648 _("shift must be constant"));
10649 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10650 inst
.instruction
|= Rd
<< 8;
10651 inst
.instruction
|= Rs
<< 16;
10652 encode_thumb32_shifted_operand (2);
10657 /* On its face this is a lie - the instruction does set the
10658 flags. However, the only supported mnemonic in this mode
10659 says it doesn't. */
10660 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10662 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10663 _("unshifted register required"));
10664 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10665 constraint (Rd
!= Rs
,
10666 _("dest and source1 must be the same register"));
10668 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10669 inst
.instruction
|= Rd
;
10670 inst
.instruction
|= Rn
<< 3;
10674 /* Similarly, but for instructions where the arithmetic operation is
10675 commutative, so we can allow either of them to be different from
10676 the destination operand in a 16-bit instruction. For instance, all
10677 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10684 Rd
= inst
.operands
[0].reg
;
10685 Rs
= (inst
.operands
[1].present
10686 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10687 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10688 Rn
= inst
.operands
[2].reg
;
10690 reject_bad_reg (Rd
);
10691 reject_bad_reg (Rs
);
10692 if (inst
.operands
[2].isreg
)
10693 reject_bad_reg (Rn
);
10695 if (unified_syntax
)
10697 if (!inst
.operands
[2].isreg
)
10699 /* For an immediate, we always generate a 32-bit opcode;
10700 section relaxation will shrink it later if possible. */
10701 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10702 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10703 inst
.instruction
|= Rd
<< 8;
10704 inst
.instruction
|= Rs
<< 16;
10705 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10709 bfd_boolean narrow
;
10711 /* See if we can do this with a 16-bit instruction. */
10712 if (THUMB_SETS_FLAGS (inst
.instruction
))
10713 narrow
= !in_it_block ();
10715 narrow
= in_it_block ();
10717 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10719 if (inst
.operands
[2].shifted
)
10721 if (inst
.size_req
== 4)
10728 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10729 inst
.instruction
|= Rd
;
10730 inst
.instruction
|= Rn
<< 3;
10735 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10736 inst
.instruction
|= Rd
;
10737 inst
.instruction
|= Rs
<< 3;
10742 /* If we get here, it can't be done in 16 bits. */
10743 constraint (inst
.operands
[2].shifted
10744 && inst
.operands
[2].immisreg
,
10745 _("shift must be constant"));
10746 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10747 inst
.instruction
|= Rd
<< 8;
10748 inst
.instruction
|= Rs
<< 16;
10749 encode_thumb32_shifted_operand (2);
10754 /* On its face this is a lie - the instruction does set the
10755 flags. However, the only supported mnemonic in this mode
10756 says it doesn't. */
10757 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10759 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10760 _("unshifted register required"));
10761 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10763 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10764 inst
.instruction
|= Rd
;
10767 inst
.instruction
|= Rn
<< 3;
10769 inst
.instruction
|= Rs
<< 3;
10771 constraint (1, _("dest must overlap one source register"));
10779 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10780 constraint (msb
> 32, _("bit-field extends past end of register"));
10781 /* The instruction encoding stores the LSB and MSB,
10782 not the LSB and width. */
10783 Rd
= inst
.operands
[0].reg
;
10784 reject_bad_reg (Rd
);
10785 inst
.instruction
|= Rd
<< 8;
10786 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10787 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10788 inst
.instruction
|= msb
- 1;
10797 Rd
= inst
.operands
[0].reg
;
10798 reject_bad_reg (Rd
);
10800 /* #0 in second position is alternative syntax for bfc, which is
10801 the same instruction but with REG_PC in the Rm field. */
10802 if (!inst
.operands
[1].isreg
)
10806 Rn
= inst
.operands
[1].reg
;
10807 reject_bad_reg (Rn
);
10810 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10811 constraint (msb
> 32, _("bit-field extends past end of register"));
10812 /* The instruction encoding stores the LSB and MSB,
10813 not the LSB and width. */
10814 inst
.instruction
|= Rd
<< 8;
10815 inst
.instruction
|= Rn
<< 16;
10816 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10817 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10818 inst
.instruction
|= msb
- 1;
10826 Rd
= inst
.operands
[0].reg
;
10827 Rn
= inst
.operands
[1].reg
;
10829 reject_bad_reg (Rd
);
10830 reject_bad_reg (Rn
);
10832 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10833 _("bit-field extends past end of register"));
10834 inst
.instruction
|= Rd
<< 8;
10835 inst
.instruction
|= Rn
<< 16;
10836 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10837 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10838 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10841 /* ARM V5 Thumb BLX (argument parse)
10842 BLX <target_addr> which is BLX(1)
10843 BLX <Rm> which is BLX(2)
10844 Unfortunately, there are two different opcodes for this mnemonic.
10845 So, the insns[].value is not used, and the code here zaps values
10846 into inst.instruction.
10848 ??? How to take advantage of the additional two bits of displacement
10849 available in Thumb32 mode? Need new relocation? */
10854 set_it_insn_type_last ();
10856 if (inst
.operands
[0].isreg
)
10858 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10859 /* We have a register, so this is BLX(2). */
10860 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10864 /* No register. This must be BLX(1). */
10865 inst
.instruction
= 0xf000e800;
10866 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10878 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10880 if (in_it_block ())
10882 /* Conditional branches inside IT blocks are encoded as unconditional
10884 cond
= COND_ALWAYS
;
10889 if (cond
!= COND_ALWAYS
)
10890 opcode
= T_MNEM_bcond
;
10892 opcode
= inst
.instruction
;
10895 && (inst
.size_req
== 4
10896 || (inst
.size_req
!= 2
10897 && (inst
.operands
[0].hasreloc
10898 || inst
.reloc
.exp
.X_op
== O_constant
))))
10900 inst
.instruction
= THUMB_OP32(opcode
);
10901 if (cond
== COND_ALWAYS
)
10902 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10905 gas_assert (cond
!= 0xF);
10906 inst
.instruction
|= cond
<< 22;
10907 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10912 inst
.instruction
= THUMB_OP16(opcode
);
10913 if (cond
== COND_ALWAYS
)
10914 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10917 inst
.instruction
|= cond
<< 8;
10918 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10920 /* Allow section relaxation. */
10921 if (unified_syntax
&& inst
.size_req
!= 2)
10922 inst
.relax
= opcode
;
10924 inst
.reloc
.type
= reloc
;
10925 inst
.reloc
.pc_rel
= 1;
10928 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10929 between the two is the maximum immediate allowed - which is passed in
10932 do_t_bkpt_hlt1 (int range
)
10934 constraint (inst
.cond
!= COND_ALWAYS
,
10935 _("instruction is always unconditional"));
10936 if (inst
.operands
[0].present
)
10938 constraint (inst
.operands
[0].imm
> range
,
10939 _("immediate value out of range"));
10940 inst
.instruction
|= inst
.operands
[0].imm
;
10943 set_it_insn_type (NEUTRAL_IT_INSN
);
10949 do_t_bkpt_hlt1 (63);
10955 do_t_bkpt_hlt1 (255);
10959 do_t_branch23 (void)
10961 set_it_insn_type_last ();
10962 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10964 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10965 this file. We used to simply ignore the PLT reloc type here --
10966 the branch encoding is now needed to deal with TLSCALL relocs.
10967 So if we see a PLT reloc now, put it back to how it used to be to
10968 keep the preexisting behaviour. */
10969 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10970 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10972 #if defined(OBJ_COFF)
10973 /* If the destination of the branch is a defined symbol which does not have
10974 the THUMB_FUNC attribute, then we must be calling a function which has
10975 the (interfacearm) attribute. We look for the Thumb entry point to that
10976 function and change the branch to refer to that function instead. */
10977 if ( inst
.reloc
.exp
.X_op
== O_symbol
10978 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10979 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10980 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10981 inst
.reloc
.exp
.X_add_symbol
=
10982 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10989 set_it_insn_type_last ();
10990 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10991 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10992 should cause the alignment to be checked once it is known. This is
10993 because BX PC only works if the instruction is word aligned. */
11001 set_it_insn_type_last ();
11002 Rm
= inst
.operands
[0].reg
;
11003 reject_bad_reg (Rm
);
11004 inst
.instruction
|= Rm
<< 16;
11013 Rd
= inst
.operands
[0].reg
;
11014 Rm
= inst
.operands
[1].reg
;
11016 reject_bad_reg (Rd
);
11017 reject_bad_reg (Rm
);
11019 inst
.instruction
|= Rd
<< 8;
11020 inst
.instruction
|= Rm
<< 16;
11021 inst
.instruction
|= Rm
;
11027 set_it_insn_type (OUTSIDE_IT_INSN
);
11028 inst
.instruction
|= inst
.operands
[0].imm
;
11034 set_it_insn_type (OUTSIDE_IT_INSN
);
11036 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11037 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11039 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11040 inst
.instruction
= 0xf3af8000;
11041 inst
.instruction
|= imod
<< 9;
11042 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11043 if (inst
.operands
[1].present
)
11044 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11048 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11049 && (inst
.operands
[0].imm
& 4),
11050 _("selected processor does not support 'A' form "
11051 "of this instruction"));
11052 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11053 _("Thumb does not support the 2-argument "
11054 "form of this instruction"));
11055 inst
.instruction
|= inst
.operands
[0].imm
;
11059 /* THUMB CPY instruction (argument parse). */
11064 if (inst
.size_req
== 4)
11066 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11067 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11068 inst
.instruction
|= inst
.operands
[1].reg
;
11072 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11073 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11074 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11081 set_it_insn_type (OUTSIDE_IT_INSN
);
11082 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11083 inst
.instruction
|= inst
.operands
[0].reg
;
11084 inst
.reloc
.pc_rel
= 1;
11085 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11091 inst
.instruction
|= inst
.operands
[0].imm
;
11097 unsigned Rd
, Rn
, Rm
;
11099 Rd
= inst
.operands
[0].reg
;
11100 Rn
= (inst
.operands
[1].present
11101 ? inst
.operands
[1].reg
: Rd
);
11102 Rm
= inst
.operands
[2].reg
;
11104 reject_bad_reg (Rd
);
11105 reject_bad_reg (Rn
);
11106 reject_bad_reg (Rm
);
11108 inst
.instruction
|= Rd
<< 8;
11109 inst
.instruction
|= Rn
<< 16;
11110 inst
.instruction
|= Rm
;
11116 if (unified_syntax
&& inst
.size_req
== 4)
11117 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11119 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11125 unsigned int cond
= inst
.operands
[0].imm
;
11127 set_it_insn_type (IT_INSN
);
11128 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11130 now_it
.warn_deprecated
= FALSE
;
11132 /* If the condition is a negative condition, invert the mask. */
11133 if ((cond
& 0x1) == 0x0)
11135 unsigned int mask
= inst
.instruction
& 0x000f;
11137 if ((mask
& 0x7) == 0)
11139 /* No conversion needed. */
11140 now_it
.block_length
= 1;
11142 else if ((mask
& 0x3) == 0)
11145 now_it
.block_length
= 2;
11147 else if ((mask
& 0x1) == 0)
11150 now_it
.block_length
= 3;
11155 now_it
.block_length
= 4;
11158 inst
.instruction
&= 0xfff0;
11159 inst
.instruction
|= mask
;
11162 inst
.instruction
|= cond
<< 4;
11165 /* Helper function used for both push/pop and ldm/stm. */
11167 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11171 load
= (inst
.instruction
& (1 << 20)) != 0;
11173 if (mask
& (1 << 13))
11174 inst
.error
= _("SP not allowed in register list");
11176 if ((mask
& (1 << base
)) != 0
11178 inst
.error
= _("having the base register in the register list when "
11179 "using write back is UNPREDICTABLE");
11183 if (mask
& (1 << 15))
11185 if (mask
& (1 << 14))
11186 inst
.error
= _("LR and PC should not both be in register list");
11188 set_it_insn_type_last ();
11193 if (mask
& (1 << 15))
11194 inst
.error
= _("PC not allowed in register list");
11197 if ((mask
& (mask
- 1)) == 0)
11199 /* Single register transfers implemented as str/ldr. */
11202 if (inst
.instruction
& (1 << 23))
11203 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11205 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11209 if (inst
.instruction
& (1 << 23))
11210 inst
.instruction
= 0x00800000; /* ia -> [base] */
11212 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11215 inst
.instruction
|= 0xf8400000;
11217 inst
.instruction
|= 0x00100000;
11219 mask
= ffs (mask
) - 1;
11222 else if (writeback
)
11223 inst
.instruction
|= WRITE_BACK
;
11225 inst
.instruction
|= mask
;
11226 inst
.instruction
|= base
<< 16;
11232 /* This really doesn't seem worth it. */
11233 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11234 _("expression too complex"));
11235 constraint (inst
.operands
[1].writeback
,
11236 _("Thumb load/store multiple does not support {reglist}^"));
11238 if (unified_syntax
)
11240 bfd_boolean narrow
;
11244 /* See if we can use a 16-bit instruction. */
11245 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11246 && inst
.size_req
!= 4
11247 && !(inst
.operands
[1].imm
& ~0xff))
11249 mask
= 1 << inst
.operands
[0].reg
;
11251 if (inst
.operands
[0].reg
<= 7)
11253 if (inst
.instruction
== T_MNEM_stmia
11254 ? inst
.operands
[0].writeback
11255 : (inst
.operands
[0].writeback
11256 == !(inst
.operands
[1].imm
& mask
)))
11258 if (inst
.instruction
== T_MNEM_stmia
11259 && (inst
.operands
[1].imm
& mask
)
11260 && (inst
.operands
[1].imm
& (mask
- 1)))
11261 as_warn (_("value stored for r%d is UNKNOWN"),
11262 inst
.operands
[0].reg
);
11264 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11265 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11266 inst
.instruction
|= inst
.operands
[1].imm
;
11269 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11271 /* This means 1 register in reg list one of 3 situations:
11272 1. Instruction is stmia, but without writeback.
11273 2. lmdia without writeback, but with Rn not in
11275 3. ldmia with writeback, but with Rn in reglist.
11276 Case 3 is UNPREDICTABLE behaviour, so we handle
11277 case 1 and 2 which can be converted into a 16-bit
11278 str or ldr. The SP cases are handled below. */
11279 unsigned long opcode
;
11280 /* First, record an error for Case 3. */
11281 if (inst
.operands
[1].imm
& mask
11282 && inst
.operands
[0].writeback
)
11284 _("having the base register in the register list when "
11285 "using write back is UNPREDICTABLE");
11287 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11289 inst
.instruction
= THUMB_OP16 (opcode
);
11290 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11291 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11295 else if (inst
.operands
[0] .reg
== REG_SP
)
11297 if (inst
.operands
[0].writeback
)
11300 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11301 ? T_MNEM_push
: T_MNEM_pop
);
11302 inst
.instruction
|= inst
.operands
[1].imm
;
11305 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11308 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11309 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11310 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11318 if (inst
.instruction
< 0xffff)
11319 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11321 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11322 inst
.operands
[0].writeback
);
11327 constraint (inst
.operands
[0].reg
> 7
11328 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11329 constraint (inst
.instruction
!= T_MNEM_ldmia
11330 && inst
.instruction
!= T_MNEM_stmia
,
11331 _("Thumb-2 instruction only valid in unified syntax"));
11332 if (inst
.instruction
== T_MNEM_stmia
)
11334 if (!inst
.operands
[0].writeback
)
11335 as_warn (_("this instruction will write back the base register"));
11336 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11337 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11338 as_warn (_("value stored for r%d is UNKNOWN"),
11339 inst
.operands
[0].reg
);
11343 if (!inst
.operands
[0].writeback
11344 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11345 as_warn (_("this instruction will write back the base register"));
11346 else if (inst
.operands
[0].writeback
11347 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11348 as_warn (_("this instruction will not write back the base register"));
11351 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11352 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11353 inst
.instruction
|= inst
.operands
[1].imm
;
11360 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11361 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11362 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11363 || inst
.operands
[1].negative
,
11366 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11368 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11369 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11370 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11376 if (!inst
.operands
[1].present
)
11378 constraint (inst
.operands
[0].reg
== REG_LR
,
11379 _("r14 not allowed as first register "
11380 "when second register is omitted"));
11381 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11383 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11387 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11388 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11394 unsigned long opcode
;
11397 if (inst
.operands
[0].isreg
11398 && !inst
.operands
[0].preind
11399 && inst
.operands
[0].reg
== REG_PC
)
11400 set_it_insn_type_last ();
11402 opcode
= inst
.instruction
;
11403 if (unified_syntax
)
11405 if (!inst
.operands
[1].isreg
)
11407 if (opcode
<= 0xffff)
11408 inst
.instruction
= THUMB_OP32 (opcode
);
11409 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11412 if (inst
.operands
[1].isreg
11413 && !inst
.operands
[1].writeback
11414 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11415 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11416 && opcode
<= 0xffff
11417 && inst
.size_req
!= 4)
11419 /* Insn may have a 16-bit form. */
11420 Rn
= inst
.operands
[1].reg
;
11421 if (inst
.operands
[1].immisreg
)
11423 inst
.instruction
= THUMB_OP16 (opcode
);
11425 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11427 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11428 reject_bad_reg (inst
.operands
[1].imm
);
11430 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11431 && opcode
!= T_MNEM_ldrsb
)
11432 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11433 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11440 if (inst
.reloc
.pc_rel
)
11441 opcode
= T_MNEM_ldr_pc2
;
11443 opcode
= T_MNEM_ldr_pc
;
11447 if (opcode
== T_MNEM_ldr
)
11448 opcode
= T_MNEM_ldr_sp
;
11450 opcode
= T_MNEM_str_sp
;
11452 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11456 inst
.instruction
= inst
.operands
[0].reg
;
11457 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11459 inst
.instruction
|= THUMB_OP16 (opcode
);
11460 if (inst
.size_req
== 2)
11461 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11463 inst
.relax
= opcode
;
11467 /* Definitely a 32-bit variant. */
11469 /* Warning for Erratum 752419. */
11470 if (opcode
== T_MNEM_ldr
11471 && inst
.operands
[0].reg
== REG_SP
11472 && inst
.operands
[1].writeback
== 1
11473 && !inst
.operands
[1].immisreg
)
11475 if (no_cpu_selected ()
11476 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11477 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11478 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11479 as_warn (_("This instruction may be unpredictable "
11480 "if executed on M-profile cores "
11481 "with interrupts enabled."));
11484 /* Do some validations regarding addressing modes. */
11485 if (inst
.operands
[1].immisreg
)
11486 reject_bad_reg (inst
.operands
[1].imm
);
11488 constraint (inst
.operands
[1].writeback
== 1
11489 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11492 inst
.instruction
= THUMB_OP32 (opcode
);
11493 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11494 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11495 check_ldr_r15_aligned ();
11499 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11501 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11503 /* Only [Rn,Rm] is acceptable. */
11504 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11505 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11506 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11507 || inst
.operands
[1].negative
,
11508 _("Thumb does not support this addressing mode"));
11509 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11513 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11514 if (!inst
.operands
[1].isreg
)
11515 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11518 constraint (!inst
.operands
[1].preind
11519 || inst
.operands
[1].shifted
11520 || inst
.operands
[1].writeback
,
11521 _("Thumb does not support this addressing mode"));
11522 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11524 constraint (inst
.instruction
& 0x0600,
11525 _("byte or halfword not valid for base register"));
11526 constraint (inst
.operands
[1].reg
== REG_PC
11527 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11528 _("r15 based store not allowed"));
11529 constraint (inst
.operands
[1].immisreg
,
11530 _("invalid base register for register offset"));
11532 if (inst
.operands
[1].reg
== REG_PC
)
11533 inst
.instruction
= T_OPCODE_LDR_PC
;
11534 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11535 inst
.instruction
= T_OPCODE_LDR_SP
;
11537 inst
.instruction
= T_OPCODE_STR_SP
;
11539 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11540 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11544 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11545 if (!inst
.operands
[1].immisreg
)
11547 /* Immediate offset. */
11548 inst
.instruction
|= inst
.operands
[0].reg
;
11549 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11550 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11554 /* Register offset. */
11555 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11556 constraint (inst
.operands
[1].negative
,
11557 _("Thumb does not support this addressing mode"));
11560 switch (inst
.instruction
)
11562 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11563 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11564 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11565 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11566 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11567 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11568 case 0x5600 /* ldrsb */:
11569 case 0x5e00 /* ldrsh */: break;
11573 inst
.instruction
|= inst
.operands
[0].reg
;
11574 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11575 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11581 if (!inst
.operands
[1].present
)
11583 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11584 constraint (inst
.operands
[0].reg
== REG_LR
,
11585 _("r14 not allowed here"));
11586 constraint (inst
.operands
[0].reg
== REG_R12
,
11587 _("r12 not allowed here"));
11590 if (inst
.operands
[2].writeback
11591 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11592 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11593 as_warn (_("base register written back, and overlaps "
11594 "one of transfer registers"));
11596 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11597 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11598 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11604 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11605 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11611 unsigned Rd
, Rn
, Rm
, Ra
;
11613 Rd
= inst
.operands
[0].reg
;
11614 Rn
= inst
.operands
[1].reg
;
11615 Rm
= inst
.operands
[2].reg
;
11616 Ra
= inst
.operands
[3].reg
;
11618 reject_bad_reg (Rd
);
11619 reject_bad_reg (Rn
);
11620 reject_bad_reg (Rm
);
11621 reject_bad_reg (Ra
);
11623 inst
.instruction
|= Rd
<< 8;
11624 inst
.instruction
|= Rn
<< 16;
11625 inst
.instruction
|= Rm
;
11626 inst
.instruction
|= Ra
<< 12;
11632 unsigned RdLo
, RdHi
, Rn
, Rm
;
11634 RdLo
= inst
.operands
[0].reg
;
11635 RdHi
= inst
.operands
[1].reg
;
11636 Rn
= inst
.operands
[2].reg
;
11637 Rm
= inst
.operands
[3].reg
;
11639 reject_bad_reg (RdLo
);
11640 reject_bad_reg (RdHi
);
11641 reject_bad_reg (Rn
);
11642 reject_bad_reg (Rm
);
11644 inst
.instruction
|= RdLo
<< 12;
11645 inst
.instruction
|= RdHi
<< 8;
11646 inst
.instruction
|= Rn
<< 16;
11647 inst
.instruction
|= Rm
;
11651 do_t_mov_cmp (void)
11655 Rn
= inst
.operands
[0].reg
;
11656 Rm
= inst
.operands
[1].reg
;
11659 set_it_insn_type_last ();
11661 if (unified_syntax
)
11663 int r0off
= (inst
.instruction
== T_MNEM_mov
11664 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11665 unsigned long opcode
;
11666 bfd_boolean narrow
;
11667 bfd_boolean low_regs
;
11669 low_regs
= (Rn
<= 7 && Rm
<= 7);
11670 opcode
= inst
.instruction
;
11671 if (in_it_block ())
11672 narrow
= opcode
!= T_MNEM_movs
;
11674 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11675 if (inst
.size_req
== 4
11676 || inst
.operands
[1].shifted
)
11679 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11680 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11681 && !inst
.operands
[1].shifted
11685 inst
.instruction
= T2_SUBS_PC_LR
;
11689 if (opcode
== T_MNEM_cmp
)
11691 constraint (Rn
== REG_PC
, BAD_PC
);
11694 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11696 warn_deprecated_sp (Rm
);
11697 /* R15 was documented as a valid choice for Rm in ARMv6,
11698 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11699 tools reject R15, so we do too. */
11700 constraint (Rm
== REG_PC
, BAD_PC
);
11703 reject_bad_reg (Rm
);
11705 else if (opcode
== T_MNEM_mov
11706 || opcode
== T_MNEM_movs
)
11708 if (inst
.operands
[1].isreg
)
11710 if (opcode
== T_MNEM_movs
)
11712 reject_bad_reg (Rn
);
11713 reject_bad_reg (Rm
);
11717 /* This is mov.n. */
11718 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11719 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11721 as_tsktsk (_("Use of r%u as a source register is "
11722 "deprecated when r%u is the destination "
11723 "register."), Rm
, Rn
);
11728 /* This is mov.w. */
11729 constraint (Rn
== REG_PC
, BAD_PC
);
11730 constraint (Rm
== REG_PC
, BAD_PC
);
11731 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11735 reject_bad_reg (Rn
);
11738 if (!inst
.operands
[1].isreg
)
11740 /* Immediate operand. */
11741 if (!in_it_block () && opcode
== T_MNEM_mov
)
11743 if (low_regs
&& narrow
)
11745 inst
.instruction
= THUMB_OP16 (opcode
);
11746 inst
.instruction
|= Rn
<< 8;
11747 if (inst
.size_req
== 2)
11748 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11750 inst
.relax
= opcode
;
11754 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11755 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11756 inst
.instruction
|= Rn
<< r0off
;
11757 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11760 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11761 && (inst
.instruction
== T_MNEM_mov
11762 || inst
.instruction
== T_MNEM_movs
))
11764 /* Register shifts are encoded as separate shift instructions. */
11765 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11767 if (in_it_block ())
11772 if (inst
.size_req
== 4)
11775 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11781 switch (inst
.operands
[1].shift_kind
)
11784 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11787 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11790 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11793 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11799 inst
.instruction
= opcode
;
11802 inst
.instruction
|= Rn
;
11803 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11808 inst
.instruction
|= CONDS_BIT
;
11810 inst
.instruction
|= Rn
<< 8;
11811 inst
.instruction
|= Rm
<< 16;
11812 inst
.instruction
|= inst
.operands
[1].imm
;
11817 /* Some mov with immediate shift have narrow variants.
11818 Register shifts are handled above. */
11819 if (low_regs
&& inst
.operands
[1].shifted
11820 && (inst
.instruction
== T_MNEM_mov
11821 || inst
.instruction
== T_MNEM_movs
))
11823 if (in_it_block ())
11824 narrow
= (inst
.instruction
== T_MNEM_mov
);
11826 narrow
= (inst
.instruction
== T_MNEM_movs
);
11831 switch (inst
.operands
[1].shift_kind
)
11833 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11834 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11835 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11836 default: narrow
= FALSE
; break;
11842 inst
.instruction
|= Rn
;
11843 inst
.instruction
|= Rm
<< 3;
11844 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11848 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11849 inst
.instruction
|= Rn
<< r0off
;
11850 encode_thumb32_shifted_operand (1);
11854 switch (inst
.instruction
)
11857 /* In v4t or v5t a move of two lowregs produces unpredictable
11858 results. Don't allow this. */
11861 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11862 "MOV Rd, Rs with two low registers is not "
11863 "permitted on this architecture");
11864 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11868 inst
.instruction
= T_OPCODE_MOV_HR
;
11869 inst
.instruction
|= (Rn
& 0x8) << 4;
11870 inst
.instruction
|= (Rn
& 0x7);
11871 inst
.instruction
|= Rm
<< 3;
11875 /* We know we have low registers at this point.
11876 Generate LSLS Rd, Rs, #0. */
11877 inst
.instruction
= T_OPCODE_LSL_I
;
11878 inst
.instruction
|= Rn
;
11879 inst
.instruction
|= Rm
<< 3;
11885 inst
.instruction
= T_OPCODE_CMP_LR
;
11886 inst
.instruction
|= Rn
;
11887 inst
.instruction
|= Rm
<< 3;
11891 inst
.instruction
= T_OPCODE_CMP_HR
;
11892 inst
.instruction
|= (Rn
& 0x8) << 4;
11893 inst
.instruction
|= (Rn
& 0x7);
11894 inst
.instruction
|= Rm
<< 3;
11901 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11903 /* PR 10443: Do not silently ignore shifted operands. */
11904 constraint (inst
.operands
[1].shifted
,
11905 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11907 if (inst
.operands
[1].isreg
)
11909 if (Rn
< 8 && Rm
< 8)
11911 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11912 since a MOV instruction produces unpredictable results. */
11913 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11914 inst
.instruction
= T_OPCODE_ADD_I3
;
11916 inst
.instruction
= T_OPCODE_CMP_LR
;
11918 inst
.instruction
|= Rn
;
11919 inst
.instruction
|= Rm
<< 3;
11923 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11924 inst
.instruction
= T_OPCODE_MOV_HR
;
11926 inst
.instruction
= T_OPCODE_CMP_HR
;
11932 constraint (Rn
> 7,
11933 _("only lo regs allowed with immediate"));
11934 inst
.instruction
|= Rn
<< 8;
11935 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11946 top
= (inst
.instruction
& 0x00800000) != 0;
11947 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11949 constraint (top
, _(":lower16: not allowed this instruction"));
11950 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11952 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11954 constraint (!top
, _(":upper16: not allowed this instruction"));
11955 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11958 Rd
= inst
.operands
[0].reg
;
11959 reject_bad_reg (Rd
);
11961 inst
.instruction
|= Rd
<< 8;
11962 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11964 imm
= inst
.reloc
.exp
.X_add_number
;
11965 inst
.instruction
|= (imm
& 0xf000) << 4;
11966 inst
.instruction
|= (imm
& 0x0800) << 15;
11967 inst
.instruction
|= (imm
& 0x0700) << 4;
11968 inst
.instruction
|= (imm
& 0x00ff);
11973 do_t_mvn_tst (void)
11977 Rn
= inst
.operands
[0].reg
;
11978 Rm
= inst
.operands
[1].reg
;
11980 if (inst
.instruction
== T_MNEM_cmp
11981 || inst
.instruction
== T_MNEM_cmn
)
11982 constraint (Rn
== REG_PC
, BAD_PC
);
11984 reject_bad_reg (Rn
);
11985 reject_bad_reg (Rm
);
11987 if (unified_syntax
)
11989 int r0off
= (inst
.instruction
== T_MNEM_mvn
11990 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11991 bfd_boolean narrow
;
11993 if (inst
.size_req
== 4
11994 || inst
.instruction
> 0xffff
11995 || inst
.operands
[1].shifted
11996 || Rn
> 7 || Rm
> 7)
11998 else if (inst
.instruction
== T_MNEM_cmn
11999 || inst
.instruction
== T_MNEM_tst
)
12001 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12002 narrow
= !in_it_block ();
12004 narrow
= in_it_block ();
12006 if (!inst
.operands
[1].isreg
)
12008 /* For an immediate, we always generate a 32-bit opcode;
12009 section relaxation will shrink it later if possible. */
12010 if (inst
.instruction
< 0xffff)
12011 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12012 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12013 inst
.instruction
|= Rn
<< r0off
;
12014 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12018 /* See if we can do this with a 16-bit instruction. */
12021 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12022 inst
.instruction
|= Rn
;
12023 inst
.instruction
|= Rm
<< 3;
12027 constraint (inst
.operands
[1].shifted
12028 && inst
.operands
[1].immisreg
,
12029 _("shift must be constant"));
12030 if (inst
.instruction
< 0xffff)
12031 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12032 inst
.instruction
|= Rn
<< r0off
;
12033 encode_thumb32_shifted_operand (1);
12039 constraint (inst
.instruction
> 0xffff
12040 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12041 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12042 _("unshifted register required"));
12043 constraint (Rn
> 7 || Rm
> 7,
12046 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12047 inst
.instruction
|= Rn
;
12048 inst
.instruction
|= Rm
<< 3;
12057 if (do_vfp_nsyn_mrs () == SUCCESS
)
12060 Rd
= inst
.operands
[0].reg
;
12061 reject_bad_reg (Rd
);
12062 inst
.instruction
|= Rd
<< 8;
12064 if (inst
.operands
[1].isreg
)
12066 unsigned br
= inst
.operands
[1].reg
;
12067 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12068 as_bad (_("bad register for mrs"));
12070 inst
.instruction
|= br
& (0xf << 16);
12071 inst
.instruction
|= (br
& 0x300) >> 4;
12072 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12076 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12078 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12080 /* PR gas/12698: The constraint is only applied for m_profile.
12081 If the user has specified -march=all, we want to ignore it as
12082 we are building for any CPU type, including non-m variants. */
12083 bfd_boolean m_profile
=
12084 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12085 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12086 "not support requested special purpose register"));
12089 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12091 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12092 _("'APSR', 'CPSR' or 'SPSR' expected"));
12094 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12095 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12096 inst
.instruction
|= 0xf0000;
12106 if (do_vfp_nsyn_msr () == SUCCESS
)
12109 constraint (!inst
.operands
[1].isreg
,
12110 _("Thumb encoding does not support an immediate here"));
12112 if (inst
.operands
[0].isreg
)
12113 flags
= (int)(inst
.operands
[0].reg
);
12115 flags
= inst
.operands
[0].imm
;
12117 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12119 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12121 /* PR gas/12698: The constraint is only applied for m_profile.
12122 If the user has specified -march=all, we want to ignore it as
12123 we are building for any CPU type, including non-m variants. */
12124 bfd_boolean m_profile
=
12125 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12126 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12127 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12128 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12129 && bits
!= PSR_f
)) && m_profile
,
12130 _("selected processor does not support requested special "
12131 "purpose register"));
12134 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12135 "requested special purpose register"));
12137 Rn
= inst
.operands
[1].reg
;
12138 reject_bad_reg (Rn
);
12140 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12141 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12142 inst
.instruction
|= (flags
& 0x300) >> 4;
12143 inst
.instruction
|= (flags
& 0xff);
12144 inst
.instruction
|= Rn
<< 16;
12150 bfd_boolean narrow
;
12151 unsigned Rd
, Rn
, Rm
;
12153 if (!inst
.operands
[2].present
)
12154 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12156 Rd
= inst
.operands
[0].reg
;
12157 Rn
= inst
.operands
[1].reg
;
12158 Rm
= inst
.operands
[2].reg
;
12160 if (unified_syntax
)
12162 if (inst
.size_req
== 4
12168 else if (inst
.instruction
== T_MNEM_muls
)
12169 narrow
= !in_it_block ();
12171 narrow
= in_it_block ();
12175 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12176 constraint (Rn
> 7 || Rm
> 7,
12183 /* 16-bit MULS/Conditional MUL. */
12184 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12185 inst
.instruction
|= Rd
;
12188 inst
.instruction
|= Rm
<< 3;
12190 inst
.instruction
|= Rn
<< 3;
12192 constraint (1, _("dest must overlap one source register"));
12196 constraint (inst
.instruction
!= T_MNEM_mul
,
12197 _("Thumb-2 MUL must not set flags"));
12199 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12200 inst
.instruction
|= Rd
<< 8;
12201 inst
.instruction
|= Rn
<< 16;
12202 inst
.instruction
|= Rm
<< 0;
12204 reject_bad_reg (Rd
);
12205 reject_bad_reg (Rn
);
12206 reject_bad_reg (Rm
);
12213 unsigned RdLo
, RdHi
, Rn
, Rm
;
12215 RdLo
= inst
.operands
[0].reg
;
12216 RdHi
= inst
.operands
[1].reg
;
12217 Rn
= inst
.operands
[2].reg
;
12218 Rm
= inst
.operands
[3].reg
;
12220 reject_bad_reg (RdLo
);
12221 reject_bad_reg (RdHi
);
12222 reject_bad_reg (Rn
);
12223 reject_bad_reg (Rm
);
12225 inst
.instruction
|= RdLo
<< 12;
12226 inst
.instruction
|= RdHi
<< 8;
12227 inst
.instruction
|= Rn
<< 16;
12228 inst
.instruction
|= Rm
;
12231 as_tsktsk (_("rdhi and rdlo must be different"));
12237 set_it_insn_type (NEUTRAL_IT_INSN
);
12239 if (unified_syntax
)
12241 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12243 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12244 inst
.instruction
|= inst
.operands
[0].imm
;
12248 /* PR9722: Check for Thumb2 availability before
12249 generating a thumb2 nop instruction. */
12250 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12252 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12253 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12256 inst
.instruction
= 0x46c0;
12261 constraint (inst
.operands
[0].present
,
12262 _("Thumb does not support NOP with hints"));
12263 inst
.instruction
= 0x46c0;
12270 if (unified_syntax
)
12272 bfd_boolean narrow
;
12274 if (THUMB_SETS_FLAGS (inst
.instruction
))
12275 narrow
= !in_it_block ();
12277 narrow
= in_it_block ();
12278 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12280 if (inst
.size_req
== 4)
12285 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12286 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12287 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12291 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12292 inst
.instruction
|= inst
.operands
[0].reg
;
12293 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12298 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12300 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12302 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12303 inst
.instruction
|= inst
.operands
[0].reg
;
12304 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12313 Rd
= inst
.operands
[0].reg
;
12314 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12316 reject_bad_reg (Rd
);
12317 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12318 reject_bad_reg (Rn
);
12320 inst
.instruction
|= Rd
<< 8;
12321 inst
.instruction
|= Rn
<< 16;
12323 if (!inst
.operands
[2].isreg
)
12325 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12326 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12332 Rm
= inst
.operands
[2].reg
;
12333 reject_bad_reg (Rm
);
12335 constraint (inst
.operands
[2].shifted
12336 && inst
.operands
[2].immisreg
,
12337 _("shift must be constant"));
12338 encode_thumb32_shifted_operand (2);
12345 unsigned Rd
, Rn
, Rm
;
12347 Rd
= inst
.operands
[0].reg
;
12348 Rn
= inst
.operands
[1].reg
;
12349 Rm
= inst
.operands
[2].reg
;
12351 reject_bad_reg (Rd
);
12352 reject_bad_reg (Rn
);
12353 reject_bad_reg (Rm
);
12355 inst
.instruction
|= Rd
<< 8;
12356 inst
.instruction
|= Rn
<< 16;
12357 inst
.instruction
|= Rm
;
12358 if (inst
.operands
[3].present
)
12360 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12361 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12362 _("expression too complex"));
12363 inst
.instruction
|= (val
& 0x1c) << 10;
12364 inst
.instruction
|= (val
& 0x03) << 6;
12371 if (!inst
.operands
[3].present
)
12375 inst
.instruction
&= ~0x00000020;
12377 /* PR 10168. Swap the Rm and Rn registers. */
12378 Rtmp
= inst
.operands
[1].reg
;
12379 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12380 inst
.operands
[2].reg
= Rtmp
;
12388 if (inst
.operands
[0].immisreg
)
12389 reject_bad_reg (inst
.operands
[0].imm
);
12391 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12395 do_t_push_pop (void)
12399 constraint (inst
.operands
[0].writeback
,
12400 _("push/pop do not support {reglist}^"));
12401 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12402 _("expression too complex"));
12404 mask
= inst
.operands
[0].imm
;
12405 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12406 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12407 else if (inst
.size_req
!= 4
12408 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
12409 ? REG_LR
: REG_PC
)))
12411 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12412 inst
.instruction
|= THUMB_PP_PC_LR
;
12413 inst
.instruction
|= mask
& 0xff;
12415 else if (unified_syntax
)
12417 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12418 encode_thumb2_ldmstm (13, mask
, TRUE
);
12422 inst
.error
= _("invalid register list to push/pop instruction");
12432 Rd
= inst
.operands
[0].reg
;
12433 Rm
= inst
.operands
[1].reg
;
12435 reject_bad_reg (Rd
);
12436 reject_bad_reg (Rm
);
12438 inst
.instruction
|= Rd
<< 8;
12439 inst
.instruction
|= Rm
<< 16;
12440 inst
.instruction
|= Rm
;
12448 Rd
= inst
.operands
[0].reg
;
12449 Rm
= inst
.operands
[1].reg
;
12451 reject_bad_reg (Rd
);
12452 reject_bad_reg (Rm
);
12454 if (Rd
<= 7 && Rm
<= 7
12455 && inst
.size_req
!= 4)
12457 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12458 inst
.instruction
|= Rd
;
12459 inst
.instruction
|= Rm
<< 3;
12461 else if (unified_syntax
)
12463 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12464 inst
.instruction
|= Rd
<< 8;
12465 inst
.instruction
|= Rm
<< 16;
12466 inst
.instruction
|= Rm
;
12469 inst
.error
= BAD_HIREG
;
12477 Rd
= inst
.operands
[0].reg
;
12478 Rm
= inst
.operands
[1].reg
;
12480 reject_bad_reg (Rd
);
12481 reject_bad_reg (Rm
);
12483 inst
.instruction
|= Rd
<< 8;
12484 inst
.instruction
|= Rm
;
12492 Rd
= inst
.operands
[0].reg
;
12493 Rs
= (inst
.operands
[1].present
12494 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12495 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12497 reject_bad_reg (Rd
);
12498 reject_bad_reg (Rs
);
12499 if (inst
.operands
[2].isreg
)
12500 reject_bad_reg (inst
.operands
[2].reg
);
12502 inst
.instruction
|= Rd
<< 8;
12503 inst
.instruction
|= Rs
<< 16;
12504 if (!inst
.operands
[2].isreg
)
12506 bfd_boolean narrow
;
12508 if ((inst
.instruction
& 0x00100000) != 0)
12509 narrow
= !in_it_block ();
12511 narrow
= in_it_block ();
12513 if (Rd
> 7 || Rs
> 7)
12516 if (inst
.size_req
== 4 || !unified_syntax
)
12519 if (inst
.reloc
.exp
.X_op
!= O_constant
12520 || inst
.reloc
.exp
.X_add_number
!= 0)
12523 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12524 relaxation, but it doesn't seem worth the hassle. */
12527 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12528 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12529 inst
.instruction
|= Rs
<< 3;
12530 inst
.instruction
|= Rd
;
12534 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12535 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12539 encode_thumb32_shifted_operand (2);
12545 if (warn_on_deprecated
12546 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12547 as_tsktsk (_("setend use is deprecated for ARMv8"));
12549 set_it_insn_type (OUTSIDE_IT_INSN
);
12550 if (inst
.operands
[0].imm
)
12551 inst
.instruction
|= 0x8;
12557 if (!inst
.operands
[1].present
)
12558 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12560 if (unified_syntax
)
12562 bfd_boolean narrow
;
12565 switch (inst
.instruction
)
12568 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12570 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12572 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12574 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12578 if (THUMB_SETS_FLAGS (inst
.instruction
))
12579 narrow
= !in_it_block ();
12581 narrow
= in_it_block ();
12582 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12584 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12586 if (inst
.operands
[2].isreg
12587 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12588 || inst
.operands
[2].reg
> 7))
12590 if (inst
.size_req
== 4)
12593 reject_bad_reg (inst
.operands
[0].reg
);
12594 reject_bad_reg (inst
.operands
[1].reg
);
12598 if (inst
.operands
[2].isreg
)
12600 reject_bad_reg (inst
.operands
[2].reg
);
12601 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12602 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12603 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12604 inst
.instruction
|= inst
.operands
[2].reg
;
12606 /* PR 12854: Error on extraneous shifts. */
12607 constraint (inst
.operands
[2].shifted
,
12608 _("extraneous shift as part of operand to shift insn"));
12612 inst
.operands
[1].shifted
= 1;
12613 inst
.operands
[1].shift_kind
= shift_kind
;
12614 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12615 ? T_MNEM_movs
: T_MNEM_mov
);
12616 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12617 encode_thumb32_shifted_operand (1);
12618 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12619 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12624 if (inst
.operands
[2].isreg
)
12626 switch (shift_kind
)
12628 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12629 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12630 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12631 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12635 inst
.instruction
|= inst
.operands
[0].reg
;
12636 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12638 /* PR 12854: Error on extraneous shifts. */
12639 constraint (inst
.operands
[2].shifted
,
12640 _("extraneous shift as part of operand to shift insn"));
12644 switch (shift_kind
)
12646 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12647 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12648 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12651 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12652 inst
.instruction
|= inst
.operands
[0].reg
;
12653 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12659 constraint (inst
.operands
[0].reg
> 7
12660 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12661 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12663 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12665 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12666 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12667 _("source1 and dest must be same register"));
12669 switch (inst
.instruction
)
12671 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12672 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12673 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12674 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12678 inst
.instruction
|= inst
.operands
[0].reg
;
12679 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12681 /* PR 12854: Error on extraneous shifts. */
12682 constraint (inst
.operands
[2].shifted
,
12683 _("extraneous shift as part of operand to shift insn"));
12687 switch (inst
.instruction
)
12689 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12690 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12691 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12692 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12695 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12696 inst
.instruction
|= inst
.operands
[0].reg
;
12697 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12705 unsigned Rd
, Rn
, Rm
;
12707 Rd
= inst
.operands
[0].reg
;
12708 Rn
= inst
.operands
[1].reg
;
12709 Rm
= inst
.operands
[2].reg
;
12711 reject_bad_reg (Rd
);
12712 reject_bad_reg (Rn
);
12713 reject_bad_reg (Rm
);
12715 inst
.instruction
|= Rd
<< 8;
12716 inst
.instruction
|= Rn
<< 16;
12717 inst
.instruction
|= Rm
;
12723 unsigned Rd
, Rn
, Rm
;
12725 Rd
= inst
.operands
[0].reg
;
12726 Rm
= inst
.operands
[1].reg
;
12727 Rn
= inst
.operands
[2].reg
;
12729 reject_bad_reg (Rd
);
12730 reject_bad_reg (Rn
);
12731 reject_bad_reg (Rm
);
12733 inst
.instruction
|= Rd
<< 8;
12734 inst
.instruction
|= Rn
<< 16;
12735 inst
.instruction
|= Rm
;
12741 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12742 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12743 _("SMC is not permitted on this architecture"));
12744 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12745 _("expression too complex"));
12746 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12747 inst
.instruction
|= (value
& 0xf000) >> 12;
12748 inst
.instruction
|= (value
& 0x0ff0);
12749 inst
.instruction
|= (value
& 0x000f) << 16;
12750 /* PR gas/15623: SMC instructions must be last in an IT block. */
12751 set_it_insn_type_last ();
12757 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12759 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12760 inst
.instruction
|= (value
& 0x0fff);
12761 inst
.instruction
|= (value
& 0xf000) << 4;
12765 do_t_ssat_usat (int bias
)
12769 Rd
= inst
.operands
[0].reg
;
12770 Rn
= inst
.operands
[2].reg
;
12772 reject_bad_reg (Rd
);
12773 reject_bad_reg (Rn
);
12775 inst
.instruction
|= Rd
<< 8;
12776 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12777 inst
.instruction
|= Rn
<< 16;
12779 if (inst
.operands
[3].present
)
12781 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12783 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12785 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12786 _("expression too complex"));
12788 if (shift_amount
!= 0)
12790 constraint (shift_amount
> 31,
12791 _("shift expression is too large"));
12793 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12794 inst
.instruction
|= 0x00200000; /* sh bit. */
12796 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12797 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12805 do_t_ssat_usat (1);
12813 Rd
= inst
.operands
[0].reg
;
12814 Rn
= inst
.operands
[2].reg
;
12816 reject_bad_reg (Rd
);
12817 reject_bad_reg (Rn
);
12819 inst
.instruction
|= Rd
<< 8;
12820 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12821 inst
.instruction
|= Rn
<< 16;
12827 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12828 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12829 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12830 || inst
.operands
[2].negative
,
12833 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12835 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12836 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12837 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12838 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12844 if (!inst
.operands
[2].present
)
12845 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12847 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12848 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12849 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12852 inst
.instruction
|= inst
.operands
[0].reg
;
12853 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12854 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12855 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12861 unsigned Rd
, Rn
, Rm
;
12863 Rd
= inst
.operands
[0].reg
;
12864 Rn
= inst
.operands
[1].reg
;
12865 Rm
= inst
.operands
[2].reg
;
12867 reject_bad_reg (Rd
);
12868 reject_bad_reg (Rn
);
12869 reject_bad_reg (Rm
);
12871 inst
.instruction
|= Rd
<< 8;
12872 inst
.instruction
|= Rn
<< 16;
12873 inst
.instruction
|= Rm
;
12874 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12882 Rd
= inst
.operands
[0].reg
;
12883 Rm
= inst
.operands
[1].reg
;
12885 reject_bad_reg (Rd
);
12886 reject_bad_reg (Rm
);
12888 if (inst
.instruction
<= 0xffff
12889 && inst
.size_req
!= 4
12890 && Rd
<= 7 && Rm
<= 7
12891 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12893 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12894 inst
.instruction
|= Rd
;
12895 inst
.instruction
|= Rm
<< 3;
12897 else if (unified_syntax
)
12899 if (inst
.instruction
<= 0xffff)
12900 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12901 inst
.instruction
|= Rd
<< 8;
12902 inst
.instruction
|= Rm
;
12903 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12907 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12908 _("Thumb encoding does not support rotation"));
12909 constraint (1, BAD_HIREG
);
12916 /* We have to do the following check manually as ARM_EXT_OS only applies
12918 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12920 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12921 /* This only applies to the v6m howver, not later architectures. */
12922 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12923 as_bad (_("SVC is not permitted on this architecture"));
12924 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12927 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12936 half
= (inst
.instruction
& 0x10) != 0;
12937 set_it_insn_type_last ();
12938 constraint (inst
.operands
[0].immisreg
,
12939 _("instruction requires register index"));
12941 Rn
= inst
.operands
[0].reg
;
12942 Rm
= inst
.operands
[0].imm
;
12944 constraint (Rn
== REG_SP
, BAD_SP
);
12945 reject_bad_reg (Rm
);
12947 constraint (!half
&& inst
.operands
[0].shifted
,
12948 _("instruction does not allow shifted index"));
12949 inst
.instruction
|= (Rn
<< 16) | Rm
;
12955 if (!inst
.operands
[0].present
)
12956 inst
.operands
[0].imm
= 0;
12958 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12960 constraint (inst
.size_req
== 2,
12961 _("immediate value out of range"));
12962 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12963 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12964 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12968 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12969 inst
.instruction
|= inst
.operands
[0].imm
;
12972 set_it_insn_type (NEUTRAL_IT_INSN
);
12979 do_t_ssat_usat (0);
12987 Rd
= inst
.operands
[0].reg
;
12988 Rn
= inst
.operands
[2].reg
;
12990 reject_bad_reg (Rd
);
12991 reject_bad_reg (Rn
);
12993 inst
.instruction
|= Rd
<< 8;
12994 inst
.instruction
|= inst
.operands
[1].imm
;
12995 inst
.instruction
|= Rn
<< 16;
12998 /* Neon instruction encoder helpers. */
13000 /* Encodings for the different types for various Neon opcodes. */
13002 /* An "invalid" code for the following tables. */
13005 struct neon_tab_entry
13008 unsigned float_or_poly
;
13009 unsigned scalar_or_imm
;
13012 /* Map overloaded Neon opcodes to their respective encodings. */
13013 #define NEON_ENC_TAB \
13014 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13015 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13016 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13017 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13018 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13019 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13020 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13021 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13022 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13023 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13024 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13025 /* Register variants of the following two instructions are encoded as
13026 vcge / vcgt with the operands reversed. */ \
13027 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13028 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13029 X(vfma, N_INV, 0x0000c10, N_INV), \
13030 X(vfms, N_INV, 0x0200c10, N_INV), \
13031 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13032 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13033 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13034 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13035 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13036 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13037 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13038 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13039 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13040 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13041 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13042 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13043 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13044 X(vshl, 0x0000400, N_INV, 0x0800510), \
13045 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13046 X(vand, 0x0000110, N_INV, 0x0800030), \
13047 X(vbic, 0x0100110, N_INV, 0x0800030), \
13048 X(veor, 0x1000110, N_INV, N_INV), \
13049 X(vorn, 0x0300110, N_INV, 0x0800010), \
13050 X(vorr, 0x0200110, N_INV, 0x0800010), \
13051 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13052 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13053 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13054 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13055 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13056 X(vst1, 0x0000000, 0x0800000, N_INV), \
13057 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13058 X(vst2, 0x0000100, 0x0800100, N_INV), \
13059 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13060 X(vst3, 0x0000200, 0x0800200, N_INV), \
13061 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13062 X(vst4, 0x0000300, 0x0800300, N_INV), \
13063 X(vmovn, 0x1b20200, N_INV, N_INV), \
13064 X(vtrn, 0x1b20080, N_INV, N_INV), \
13065 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13066 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13067 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13068 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13069 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13070 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13071 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13072 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13073 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13074 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13075 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13076 X(vseleq, 0xe000a00, N_INV, N_INV), \
13077 X(vselvs, 0xe100a00, N_INV, N_INV), \
13078 X(vselge, 0xe200a00, N_INV, N_INV), \
13079 X(vselgt, 0xe300a00, N_INV, N_INV), \
13080 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13081 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13082 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13083 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13084 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13085 X(aes, 0x3b00300, N_INV, N_INV), \
13086 X(sha3op, 0x2000c00, N_INV, N_INV), \
13087 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13088 X(sha2op, 0x3ba0380, N_INV, N_INV)
13092 #define X(OPC,I,F,S) N_MNEM_##OPC
13097 static const struct neon_tab_entry neon_enc_tab
[] =
13099 #define X(OPC,I,F,S) { (I), (F), (S) }
13104 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13105 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13106 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13107 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13108 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13109 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13110 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13111 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13112 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13113 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13114 #define NEON_ENC_SINGLE_(X) \
13115 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13116 #define NEON_ENC_DOUBLE_(X) \
13117 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13118 #define NEON_ENC_FPV8_(X) \
13119 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13121 #define NEON_ENCODE(type, inst) \
13124 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13125 inst.is_neon = 1; \
13129 #define check_neon_suffixes \
13132 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13134 as_bad (_("invalid neon suffix for non neon instruction")); \
13140 /* Define shapes for instruction operands. The following mnemonic characters
13141 are used in this table:
13143 F - VFP S<n> register
13144 D - Neon D<n> register
13145 Q - Neon Q<n> register
13149 L - D<n> register list
13151 This table is used to generate various data:
13152 - enumerations of the form NS_DDR to be used as arguments to
13154 - a table classifying shapes into single, double, quad, mixed.
13155 - a table used to drive neon_select_shape. */
13157 #define NEON_SHAPE_DEF \
13158 X(3, (D, D, D), DOUBLE), \
13159 X(3, (Q, Q, Q), QUAD), \
13160 X(3, (D, D, I), DOUBLE), \
13161 X(3, (Q, Q, I), QUAD), \
13162 X(3, (D, D, S), DOUBLE), \
13163 X(3, (Q, Q, S), QUAD), \
13164 X(2, (D, D), DOUBLE), \
13165 X(2, (Q, Q), QUAD), \
13166 X(2, (D, S), DOUBLE), \
13167 X(2, (Q, S), QUAD), \
13168 X(2, (D, R), DOUBLE), \
13169 X(2, (Q, R), QUAD), \
13170 X(2, (D, I), DOUBLE), \
13171 X(2, (Q, I), QUAD), \
13172 X(3, (D, L, D), DOUBLE), \
13173 X(2, (D, Q), MIXED), \
13174 X(2, (Q, D), MIXED), \
13175 X(3, (D, Q, I), MIXED), \
13176 X(3, (Q, D, I), MIXED), \
13177 X(3, (Q, D, D), MIXED), \
13178 X(3, (D, Q, Q), MIXED), \
13179 X(3, (Q, Q, D), MIXED), \
13180 X(3, (Q, D, S), MIXED), \
13181 X(3, (D, Q, S), MIXED), \
13182 X(4, (D, D, D, I), DOUBLE), \
13183 X(4, (Q, Q, Q, I), QUAD), \
13184 X(2, (F, F), SINGLE), \
13185 X(3, (F, F, F), SINGLE), \
13186 X(2, (F, I), SINGLE), \
13187 X(2, (F, D), MIXED), \
13188 X(2, (D, F), MIXED), \
13189 X(3, (F, F, I), MIXED), \
13190 X(4, (R, R, F, F), SINGLE), \
13191 X(4, (F, F, R, R), SINGLE), \
13192 X(3, (D, R, R), DOUBLE), \
13193 X(3, (R, R, D), DOUBLE), \
13194 X(2, (S, R), SINGLE), \
13195 X(2, (R, S), SINGLE), \
13196 X(2, (F, R), SINGLE), \
13197 X(2, (R, F), SINGLE)
13199 #define S2(A,B) NS_##A##B
13200 #define S3(A,B,C) NS_##A##B##C
13201 #define S4(A,B,C,D) NS_##A##B##C##D
13203 #define X(N, L, C) S##N L
13216 enum neon_shape_class
13224 #define X(N, L, C) SC_##C
13226 static enum neon_shape_class neon_shape_class
[] =
13244 /* Register widths of above. */
13245 static unsigned neon_shape_el_size
[] =
13256 struct neon_shape_info
13259 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13262 #define S2(A,B) { SE_##A, SE_##B }
13263 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13264 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13266 #define X(N, L, C) { N, S##N L }
13268 static struct neon_shape_info neon_shape_tab
[] =
13278 /* Bit masks used in type checking given instructions.
13279 'N_EQK' means the type must be the same as (or based on in some way) the key
13280 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13281 set, various other bits can be set as well in order to modify the meaning of
13282 the type constraint. */
13284 enum neon_type_mask
13308 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13309 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13310 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13311 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13312 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13313 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13314 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13315 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13316 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13317 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13318 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13320 N_MAX_NONSPECIAL
= N_P64
13323 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13325 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13326 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13327 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13328 #define N_SUF_32 (N_SU_32 | N_F32)
13329 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13330 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13332 /* Pass this as the first type argument to neon_check_type to ignore types
13334 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13336 /* Select a "shape" for the current instruction (describing register types or
13337 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13338 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13339 function of operand parsing, so this function doesn't need to be called.
13340 Shapes should be listed in order of decreasing length. */
13342 static enum neon_shape
13343 neon_select_shape (enum neon_shape shape
, ...)
13346 enum neon_shape first_shape
= shape
;
13348 /* Fix missing optional operands. FIXME: we don't know at this point how
13349 many arguments we should have, so this makes the assumption that we have
13350 > 1. This is true of all current Neon opcodes, I think, but may not be
13351 true in the future. */
13352 if (!inst
.operands
[1].present
)
13353 inst
.operands
[1] = inst
.operands
[0];
13355 va_start (ap
, shape
);
13357 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13362 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13364 if (!inst
.operands
[j
].present
)
13370 switch (neon_shape_tab
[shape
].el
[j
])
13373 if (!(inst
.operands
[j
].isreg
13374 && inst
.operands
[j
].isvec
13375 && inst
.operands
[j
].issingle
13376 && !inst
.operands
[j
].isquad
))
13381 if (!(inst
.operands
[j
].isreg
13382 && inst
.operands
[j
].isvec
13383 && !inst
.operands
[j
].isquad
13384 && !inst
.operands
[j
].issingle
))
13389 if (!(inst
.operands
[j
].isreg
13390 && !inst
.operands
[j
].isvec
))
13395 if (!(inst
.operands
[j
].isreg
13396 && inst
.operands
[j
].isvec
13397 && inst
.operands
[j
].isquad
13398 && !inst
.operands
[j
].issingle
))
13403 if (!(!inst
.operands
[j
].isreg
13404 && !inst
.operands
[j
].isscalar
))
13409 if (!(!inst
.operands
[j
].isreg
13410 && inst
.operands
[j
].isscalar
))
13420 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13421 /* We've matched all the entries in the shape table, and we don't
13422 have any left over operands which have not been matched. */
13428 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13429 first_error (_("invalid instruction shape"));
13434 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13435 means the Q bit should be set). */
13438 neon_quad (enum neon_shape shape
)
13440 return neon_shape_class
[shape
] == SC_QUAD
;
13444 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13447 /* Allow modification to be made to types which are constrained to be
13448 based on the key element, based on bits set alongside N_EQK. */
13449 if ((typebits
& N_EQK
) != 0)
13451 if ((typebits
& N_HLF
) != 0)
13453 else if ((typebits
& N_DBL
) != 0)
13455 if ((typebits
& N_SGN
) != 0)
13456 *g_type
= NT_signed
;
13457 else if ((typebits
& N_UNS
) != 0)
13458 *g_type
= NT_unsigned
;
13459 else if ((typebits
& N_INT
) != 0)
13460 *g_type
= NT_integer
;
13461 else if ((typebits
& N_FLT
) != 0)
13462 *g_type
= NT_float
;
13463 else if ((typebits
& N_SIZ
) != 0)
13464 *g_type
= NT_untyped
;
13468 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13469 operand type, i.e. the single type specified in a Neon instruction when it
13470 is the only one given. */
13472 static struct neon_type_el
13473 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13475 struct neon_type_el dest
= *key
;
13477 gas_assert ((thisarg
& N_EQK
) != 0);
13479 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13484 /* Convert Neon type and size into compact bitmask representation. */
13486 static enum neon_type_mask
13487 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13494 case 8: return N_8
;
13495 case 16: return N_16
;
13496 case 32: return N_32
;
13497 case 64: return N_64
;
13505 case 8: return N_I8
;
13506 case 16: return N_I16
;
13507 case 32: return N_I32
;
13508 case 64: return N_I64
;
13516 case 16: return N_F16
;
13517 case 32: return N_F32
;
13518 case 64: return N_F64
;
13526 case 8: return N_P8
;
13527 case 16: return N_P16
;
13528 case 64: return N_P64
;
13536 case 8: return N_S8
;
13537 case 16: return N_S16
;
13538 case 32: return N_S32
;
13539 case 64: return N_S64
;
13547 case 8: return N_U8
;
13548 case 16: return N_U16
;
13549 case 32: return N_U32
;
13550 case 64: return N_U64
;
13561 /* Convert compact Neon bitmask type representation to a type and size. Only
13562 handles the case where a single bit is set in the mask. */
13565 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13566 enum neon_type_mask mask
)
13568 if ((mask
& N_EQK
) != 0)
13571 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13573 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13575 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13577 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13582 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13584 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13585 *type
= NT_unsigned
;
13586 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13587 *type
= NT_integer
;
13588 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13589 *type
= NT_untyped
;
13590 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13592 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13600 /* Modify a bitmask of allowed types. This is only needed for type
13604 modify_types_allowed (unsigned allowed
, unsigned mods
)
13607 enum neon_el_type type
;
13613 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13615 if (el_type_of_type_chk (&type
, &size
,
13616 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13618 neon_modify_type_size (mods
, &type
, &size
);
13619 destmask
|= type_chk_of_el_type (type
, size
);
13626 /* Check type and return type classification.
13627 The manual states (paraphrase): If one datatype is given, it indicates the
13629 - the second operand, if there is one
13630 - the operand, if there is no second operand
13631 - the result, if there are no operands.
13632 This isn't quite good enough though, so we use a concept of a "key" datatype
13633 which is set on a per-instruction basis, which is the one which matters when
13634 only one data type is written.
13635 Note: this function has side-effects (e.g. filling in missing operands). All
13636 Neon instructions should call it before performing bit encoding. */
13638 static struct neon_type_el
13639 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13642 unsigned i
, pass
, key_el
= 0;
13643 unsigned types
[NEON_MAX_TYPE_ELS
];
13644 enum neon_el_type k_type
= NT_invtype
;
13645 unsigned k_size
= -1u;
13646 struct neon_type_el badtype
= {NT_invtype
, -1};
13647 unsigned key_allowed
= 0;
13649 /* Optional registers in Neon instructions are always (not) in operand 1.
13650 Fill in the missing operand here, if it was omitted. */
13651 if (els
> 1 && !inst
.operands
[1].present
)
13652 inst
.operands
[1] = inst
.operands
[0];
13654 /* Suck up all the varargs. */
13656 for (i
= 0; i
< els
; i
++)
13658 unsigned thisarg
= va_arg (ap
, unsigned);
13659 if (thisarg
== N_IGNORE_TYPE
)
13664 types
[i
] = thisarg
;
13665 if ((thisarg
& N_KEY
) != 0)
13670 if (inst
.vectype
.elems
> 0)
13671 for (i
= 0; i
< els
; i
++)
13672 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13674 first_error (_("types specified in both the mnemonic and operands"));
13678 /* Duplicate inst.vectype elements here as necessary.
13679 FIXME: No idea if this is exactly the same as the ARM assembler,
13680 particularly when an insn takes one register and one non-register
13682 if (inst
.vectype
.elems
== 1 && els
> 1)
13685 inst
.vectype
.elems
= els
;
13686 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13687 for (j
= 0; j
< els
; j
++)
13689 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13692 else if (inst
.vectype
.elems
== 0 && els
> 0)
13695 /* No types were given after the mnemonic, so look for types specified
13696 after each operand. We allow some flexibility here; as long as the
13697 "key" operand has a type, we can infer the others. */
13698 for (j
= 0; j
< els
; j
++)
13699 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13700 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13702 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13704 for (j
= 0; j
< els
; j
++)
13705 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13706 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13711 first_error (_("operand types can't be inferred"));
13715 else if (inst
.vectype
.elems
!= els
)
13717 first_error (_("type specifier has the wrong number of parts"));
13721 for (pass
= 0; pass
< 2; pass
++)
13723 for (i
= 0; i
< els
; i
++)
13725 unsigned thisarg
= types
[i
];
13726 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13727 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13728 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13729 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13731 /* Decay more-specific signed & unsigned types to sign-insensitive
13732 integer types if sign-specific variants are unavailable. */
13733 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13734 && (types_allowed
& N_SU_ALL
) == 0)
13735 g_type
= NT_integer
;
13737 /* If only untyped args are allowed, decay any more specific types to
13738 them. Some instructions only care about signs for some element
13739 sizes, so handle that properly. */
13740 if (((types_allowed
& N_UNT
) == 0)
13741 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13742 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13743 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13744 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13745 g_type
= NT_untyped
;
13749 if ((thisarg
& N_KEY
) != 0)
13753 key_allowed
= thisarg
& ~N_KEY
;
13758 if ((thisarg
& N_VFP
) != 0)
13760 enum neon_shape_el regshape
;
13761 unsigned regwidth
, match
;
13763 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13766 first_error (_("invalid instruction shape"));
13769 regshape
= neon_shape_tab
[ns
].el
[i
];
13770 regwidth
= neon_shape_el_size
[regshape
];
13772 /* In VFP mode, operands must match register widths. If we
13773 have a key operand, use its width, else use the width of
13774 the current operand. */
13780 if (regwidth
!= match
)
13782 first_error (_("operand size must match register width"));
13787 if ((thisarg
& N_EQK
) == 0)
13789 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13791 if ((given_type
& types_allowed
) == 0)
13793 first_error (_("bad type in Neon instruction"));
13799 enum neon_el_type mod_k_type
= k_type
;
13800 unsigned mod_k_size
= k_size
;
13801 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13802 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13804 first_error (_("inconsistent types in Neon instruction"));
13812 return inst
.vectype
.el
[key_el
];
13815 /* Neon-style VFP instruction forwarding. */
13817 /* Thumb VFP instructions have 0xE in the condition field. */
13820 do_vfp_cond_or_thumb (void)
13825 inst
.instruction
|= 0xe0000000;
13827 inst
.instruction
|= inst
.cond
<< 28;
13830 /* Look up and encode a simple mnemonic, for use as a helper function for the
13831 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13832 etc. It is assumed that operand parsing has already been done, and that the
13833 operands are in the form expected by the given opcode (this isn't necessarily
13834 the same as the form in which they were parsed, hence some massaging must
13835 take place before this function is called).
13836 Checks current arch version against that in the looked-up opcode. */
13839 do_vfp_nsyn_opcode (const char *opname
)
13841 const struct asm_opcode
*opcode
;
13843 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13848 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13849 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13856 inst
.instruction
= opcode
->tvalue
;
13857 opcode
->tencode ();
13861 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13862 opcode
->aencode ();
13867 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13869 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13874 do_vfp_nsyn_opcode ("fadds");
13876 do_vfp_nsyn_opcode ("fsubs");
13881 do_vfp_nsyn_opcode ("faddd");
13883 do_vfp_nsyn_opcode ("fsubd");
13887 /* Check operand types to see if this is a VFP instruction, and if so call
13891 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13893 enum neon_shape rs
;
13894 struct neon_type_el et
;
13899 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13900 et
= neon_check_type (2, rs
,
13901 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13905 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13906 et
= neon_check_type (3, rs
,
13907 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13914 if (et
.type
!= NT_invtype
)
13925 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13927 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13932 do_vfp_nsyn_opcode ("fmacs");
13934 do_vfp_nsyn_opcode ("fnmacs");
13939 do_vfp_nsyn_opcode ("fmacd");
13941 do_vfp_nsyn_opcode ("fnmacd");
13946 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13948 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13953 do_vfp_nsyn_opcode ("ffmas");
13955 do_vfp_nsyn_opcode ("ffnmas");
13960 do_vfp_nsyn_opcode ("ffmad");
13962 do_vfp_nsyn_opcode ("ffnmad");
13967 do_vfp_nsyn_mul (enum neon_shape rs
)
13970 do_vfp_nsyn_opcode ("fmuls");
13972 do_vfp_nsyn_opcode ("fmuld");
13976 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13978 int is_neg
= (inst
.instruction
& 0x80) != 0;
13979 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13984 do_vfp_nsyn_opcode ("fnegs");
13986 do_vfp_nsyn_opcode ("fabss");
13991 do_vfp_nsyn_opcode ("fnegd");
13993 do_vfp_nsyn_opcode ("fabsd");
13997 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13998 insns belong to Neon, and are handled elsewhere. */
14001 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14003 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14007 do_vfp_nsyn_opcode ("fldmdbs");
14009 do_vfp_nsyn_opcode ("fldmias");
14014 do_vfp_nsyn_opcode ("fstmdbs");
14016 do_vfp_nsyn_opcode ("fstmias");
14021 do_vfp_nsyn_sqrt (void)
14023 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14024 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14027 do_vfp_nsyn_opcode ("fsqrts");
14029 do_vfp_nsyn_opcode ("fsqrtd");
14033 do_vfp_nsyn_div (void)
14035 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14036 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14037 N_F32
| N_F64
| N_KEY
| N_VFP
);
14040 do_vfp_nsyn_opcode ("fdivs");
14042 do_vfp_nsyn_opcode ("fdivd");
14046 do_vfp_nsyn_nmul (void)
14048 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
14049 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14050 N_F32
| N_F64
| N_KEY
| N_VFP
);
14054 NEON_ENCODE (SINGLE
, inst
);
14055 do_vfp_sp_dyadic ();
14059 NEON_ENCODE (DOUBLE
, inst
);
14060 do_vfp_dp_rd_rn_rm ();
14062 do_vfp_cond_or_thumb ();
14066 do_vfp_nsyn_cmp (void)
14068 if (inst
.operands
[1].isreg
)
14070 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
14071 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
14075 NEON_ENCODE (SINGLE
, inst
);
14076 do_vfp_sp_monadic ();
14080 NEON_ENCODE (DOUBLE
, inst
);
14081 do_vfp_dp_rd_rm ();
14086 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
14087 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
14089 switch (inst
.instruction
& 0x0fffffff)
14092 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14095 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14103 NEON_ENCODE (SINGLE
, inst
);
14104 do_vfp_sp_compare_z ();
14108 NEON_ENCODE (DOUBLE
, inst
);
14112 do_vfp_cond_or_thumb ();
14116 nsyn_insert_sp (void)
14118 inst
.operands
[1] = inst
.operands
[0];
14119 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14120 inst
.operands
[0].reg
= REG_SP
;
14121 inst
.operands
[0].isreg
= 1;
14122 inst
.operands
[0].writeback
= 1;
14123 inst
.operands
[0].present
= 1;
14127 do_vfp_nsyn_push (void)
14130 if (inst
.operands
[1].issingle
)
14131 do_vfp_nsyn_opcode ("fstmdbs");
14133 do_vfp_nsyn_opcode ("fstmdbd");
14137 do_vfp_nsyn_pop (void)
14140 if (inst
.operands
[1].issingle
)
14141 do_vfp_nsyn_opcode ("fldmias");
14143 do_vfp_nsyn_opcode ("fldmiad");
14146 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14147 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14150 neon_dp_fixup (struct arm_it
* insn
)
14152 unsigned int i
= insn
->instruction
;
14157 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14168 insn
->instruction
= i
;
14171 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14175 neon_logbits (unsigned x
)
14177 return ffs (x
) - 4;
14180 #define LOW4(R) ((R) & 0xf)
14181 #define HI1(R) (((R) >> 4) & 1)
14183 /* Encode insns with bit pattern:
14185 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14186 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14188 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14189 different meaning for some instruction. */
14192 neon_three_same (int isquad
, int ubit
, int size
)
14194 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14195 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14196 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14197 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14198 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14199 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14200 inst
.instruction
|= (isquad
!= 0) << 6;
14201 inst
.instruction
|= (ubit
!= 0) << 24;
14203 inst
.instruction
|= neon_logbits (size
) << 20;
14205 neon_dp_fixup (&inst
);
14208 /* Encode instructions of the form:
14210 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14211 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14213 Don't write size if SIZE == -1. */
14216 neon_two_same (int qbit
, int ubit
, int size
)
14218 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14219 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14220 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14221 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14222 inst
.instruction
|= (qbit
!= 0) << 6;
14223 inst
.instruction
|= (ubit
!= 0) << 24;
14226 inst
.instruction
|= neon_logbits (size
) << 18;
14228 neon_dp_fixup (&inst
);
14231 /* Neon instruction encoders, in approximate order of appearance. */
14234 do_neon_dyadic_i_su (void)
14236 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14237 struct neon_type_el et
= neon_check_type (3, rs
,
14238 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14239 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14243 do_neon_dyadic_i64_su (void)
14245 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14246 struct neon_type_el et
= neon_check_type (3, rs
,
14247 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14248 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14252 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14255 unsigned size
= et
.size
>> 3;
14256 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14257 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14258 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14259 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14260 inst
.instruction
|= (isquad
!= 0) << 6;
14261 inst
.instruction
|= immbits
<< 16;
14262 inst
.instruction
|= (size
>> 3) << 7;
14263 inst
.instruction
|= (size
& 0x7) << 19;
14265 inst
.instruction
|= (uval
!= 0) << 24;
14267 neon_dp_fixup (&inst
);
14271 do_neon_shl_imm (void)
14273 if (!inst
.operands
[2].isreg
)
14275 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14276 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14277 int imm
= inst
.operands
[2].imm
;
14279 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14280 _("immediate out of range for shift"));
14281 NEON_ENCODE (IMMED
, inst
);
14282 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14286 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14287 struct neon_type_el et
= neon_check_type (3, rs
,
14288 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14291 /* VSHL/VQSHL 3-register variants have syntax such as:
14293 whereas other 3-register operations encoded by neon_three_same have
14296 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14298 tmp
= inst
.operands
[2].reg
;
14299 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14300 inst
.operands
[1].reg
= tmp
;
14301 NEON_ENCODE (INTEGER
, inst
);
14302 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14307 do_neon_qshl_imm (void)
14309 if (!inst
.operands
[2].isreg
)
14311 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14312 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14313 int imm
= inst
.operands
[2].imm
;
14315 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14316 _("immediate out of range for shift"));
14317 NEON_ENCODE (IMMED
, inst
);
14318 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14322 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14323 struct neon_type_el et
= neon_check_type (3, rs
,
14324 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14327 /* See note in do_neon_shl_imm. */
14328 tmp
= inst
.operands
[2].reg
;
14329 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14330 inst
.operands
[1].reg
= tmp
;
14331 NEON_ENCODE (INTEGER
, inst
);
14332 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14337 do_neon_rshl (void)
14339 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14340 struct neon_type_el et
= neon_check_type (3, rs
,
14341 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14344 tmp
= inst
.operands
[2].reg
;
14345 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14346 inst
.operands
[1].reg
= tmp
;
14347 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14351 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14353 /* Handle .I8 pseudo-instructions. */
14356 /* Unfortunately, this will make everything apart from zero out-of-range.
14357 FIXME is this the intended semantics? There doesn't seem much point in
14358 accepting .I8 if so. */
14359 immediate
|= immediate
<< 8;
14365 if (immediate
== (immediate
& 0x000000ff))
14367 *immbits
= immediate
;
14370 else if (immediate
== (immediate
& 0x0000ff00))
14372 *immbits
= immediate
>> 8;
14375 else if (immediate
== (immediate
& 0x00ff0000))
14377 *immbits
= immediate
>> 16;
14380 else if (immediate
== (immediate
& 0xff000000))
14382 *immbits
= immediate
>> 24;
14385 if ((immediate
& 0xffff) != (immediate
>> 16))
14386 goto bad_immediate
;
14387 immediate
&= 0xffff;
14390 if (immediate
== (immediate
& 0x000000ff))
14392 *immbits
= immediate
;
14395 else if (immediate
== (immediate
& 0x0000ff00))
14397 *immbits
= immediate
>> 8;
14402 first_error (_("immediate value out of range"));
14407 do_neon_logic (void)
14409 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14411 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14412 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14413 /* U bit and size field were set as part of the bitmask. */
14414 NEON_ENCODE (INTEGER
, inst
);
14415 neon_three_same (neon_quad (rs
), 0, -1);
14419 const int three_ops_form
= (inst
.operands
[2].present
14420 && !inst
.operands
[2].isreg
);
14421 const int immoperand
= (three_ops_form
? 2 : 1);
14422 enum neon_shape rs
= (three_ops_form
14423 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14424 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14425 struct neon_type_el et
= neon_check_type (2, rs
,
14426 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14427 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14431 if (et
.type
== NT_invtype
)
14434 if (three_ops_form
)
14435 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14436 _("first and second operands shall be the same register"));
14438 NEON_ENCODE (IMMED
, inst
);
14440 immbits
= inst
.operands
[immoperand
].imm
;
14443 /* .i64 is a pseudo-op, so the immediate must be a repeating
14445 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14446 inst
.operands
[immoperand
].reg
: 0))
14448 /* Set immbits to an invalid constant. */
14449 immbits
= 0xdeadbeef;
14456 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14460 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14464 /* Pseudo-instruction for VBIC. */
14465 neon_invert_size (&immbits
, 0, et
.size
);
14466 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14470 /* Pseudo-instruction for VORR. */
14471 neon_invert_size (&immbits
, 0, et
.size
);
14472 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14482 inst
.instruction
|= neon_quad (rs
) << 6;
14483 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14484 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14485 inst
.instruction
|= cmode
<< 8;
14486 neon_write_immbits (immbits
);
14488 neon_dp_fixup (&inst
);
14493 do_neon_bitfield (void)
14495 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14496 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14497 neon_three_same (neon_quad (rs
), 0, -1);
14501 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14504 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14505 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14507 if (et
.type
== NT_float
)
14509 NEON_ENCODE (FLOAT
, inst
);
14510 neon_three_same (neon_quad (rs
), 0, -1);
14514 NEON_ENCODE (INTEGER
, inst
);
14515 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14520 do_neon_dyadic_if_su (void)
14522 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14526 do_neon_dyadic_if_su_d (void)
14528 /* This version only allow D registers, but that constraint is enforced during
14529 operand parsing so we don't need to do anything extra here. */
14530 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14534 do_neon_dyadic_if_i_d (void)
14536 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14537 affected if we specify unsigned args. */
14538 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14541 enum vfp_or_neon_is_neon_bits
14544 NEON_CHECK_ARCH
= 2,
14545 NEON_CHECK_ARCH8
= 4
14548 /* Call this function if an instruction which may have belonged to the VFP or
14549 Neon instruction sets, but turned out to be a Neon instruction (due to the
14550 operand types involved, etc.). We have to check and/or fix-up a couple of
14553 - Make sure the user hasn't attempted to make a Neon instruction
14555 - Alter the value in the condition code field if necessary.
14556 - Make sure that the arch supports Neon instructions.
14558 Which of these operations take place depends on bits from enum
14559 vfp_or_neon_is_neon_bits.
14561 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14562 current instruction's condition is COND_ALWAYS, the condition field is
14563 changed to inst.uncond_value. This is necessary because instructions shared
14564 between VFP and Neon may be conditional for the VFP variants only, and the
14565 unconditional Neon version must have, e.g., 0xF in the condition field. */
14568 vfp_or_neon_is_neon (unsigned check
)
14570 /* Conditions are always legal in Thumb mode (IT blocks). */
14571 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14573 if (inst
.cond
!= COND_ALWAYS
)
14575 first_error (_(BAD_COND
));
14578 if (inst
.uncond_value
!= -1)
14579 inst
.instruction
|= inst
.uncond_value
<< 28;
14582 if ((check
& NEON_CHECK_ARCH
)
14583 && !mark_feature_used (&fpu_neon_ext_v1
))
14585 first_error (_(BAD_FPU
));
14589 if ((check
& NEON_CHECK_ARCH8
)
14590 && !mark_feature_used (&fpu_neon_ext_armv8
))
14592 first_error (_(BAD_FPU
));
14600 do_neon_addsub_if_i (void)
14602 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14605 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14608 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14609 affected if we specify unsigned args. */
14610 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14613 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14615 V<op> A,B (A is operand 0, B is operand 2)
14620 so handle that case specially. */
14623 neon_exchange_operands (void)
14625 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14626 if (inst
.operands
[1].present
)
14628 /* Swap operands[1] and operands[2]. */
14629 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14630 inst
.operands
[1] = inst
.operands
[2];
14631 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14635 inst
.operands
[1] = inst
.operands
[2];
14636 inst
.operands
[2] = inst
.operands
[0];
14641 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14643 if (inst
.operands
[2].isreg
)
14646 neon_exchange_operands ();
14647 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14651 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14652 struct neon_type_el et
= neon_check_type (2, rs
,
14653 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14655 NEON_ENCODE (IMMED
, inst
);
14656 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14657 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14658 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14659 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14660 inst
.instruction
|= neon_quad (rs
) << 6;
14661 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14662 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14664 neon_dp_fixup (&inst
);
14671 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14675 do_neon_cmp_inv (void)
14677 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14683 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14686 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14687 scalars, which are encoded in 5 bits, M : Rm.
14688 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14689 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14693 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14695 unsigned regno
= NEON_SCALAR_REG (scalar
);
14696 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14701 if (regno
> 7 || elno
> 3)
14703 return regno
| (elno
<< 3);
14706 if (regno
> 15 || elno
> 1)
14708 return regno
| (elno
<< 4);
14712 first_error (_("scalar out of range for multiply instruction"));
14718 /* Encode multiply / multiply-accumulate scalar instructions. */
14721 neon_mul_mac (struct neon_type_el et
, int ubit
)
14725 /* Give a more helpful error message if we have an invalid type. */
14726 if (et
.type
== NT_invtype
)
14729 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14730 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14731 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14732 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14733 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14734 inst
.instruction
|= LOW4 (scalar
);
14735 inst
.instruction
|= HI1 (scalar
) << 5;
14736 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14737 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14738 inst
.instruction
|= (ubit
!= 0) << 24;
14740 neon_dp_fixup (&inst
);
14744 do_neon_mac_maybe_scalar (void)
14746 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14749 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14752 if (inst
.operands
[2].isscalar
)
14754 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14755 struct neon_type_el et
= neon_check_type (3, rs
,
14756 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14757 NEON_ENCODE (SCALAR
, inst
);
14758 neon_mul_mac (et
, neon_quad (rs
));
14762 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14763 affected if we specify unsigned args. */
14764 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14769 do_neon_fmac (void)
14771 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14774 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14777 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14783 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14784 struct neon_type_el et
= neon_check_type (3, rs
,
14785 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14786 neon_three_same (neon_quad (rs
), 0, et
.size
);
14789 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14790 same types as the MAC equivalents. The polynomial type for this instruction
14791 is encoded the same as the integer type. */
14796 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14799 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14802 if (inst
.operands
[2].isscalar
)
14803 do_neon_mac_maybe_scalar ();
14805 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14809 do_neon_qdmulh (void)
14811 if (inst
.operands
[2].isscalar
)
14813 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14814 struct neon_type_el et
= neon_check_type (3, rs
,
14815 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14816 NEON_ENCODE (SCALAR
, inst
);
14817 neon_mul_mac (et
, neon_quad (rs
));
14821 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14822 struct neon_type_el et
= neon_check_type (3, rs
,
14823 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14824 NEON_ENCODE (INTEGER
, inst
);
14825 /* The U bit (rounding) comes from bit mask. */
14826 neon_three_same (neon_quad (rs
), 0, et
.size
);
14831 do_neon_fcmp_absolute (void)
14833 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14834 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14835 /* Size field comes from bit mask. */
14836 neon_three_same (neon_quad (rs
), 1, -1);
14840 do_neon_fcmp_absolute_inv (void)
14842 neon_exchange_operands ();
14843 do_neon_fcmp_absolute ();
14847 do_neon_step (void)
14849 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14850 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14851 neon_three_same (neon_quad (rs
), 0, -1);
14855 do_neon_abs_neg (void)
14857 enum neon_shape rs
;
14858 struct neon_type_el et
;
14860 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14863 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14866 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14867 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14869 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14870 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14871 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14872 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14873 inst
.instruction
|= neon_quad (rs
) << 6;
14874 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14875 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14877 neon_dp_fixup (&inst
);
14883 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14884 struct neon_type_el et
= neon_check_type (2, rs
,
14885 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14886 int imm
= inst
.operands
[2].imm
;
14887 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14888 _("immediate out of range for insert"));
14889 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14895 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14896 struct neon_type_el et
= neon_check_type (2, rs
,
14897 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14898 int imm
= inst
.operands
[2].imm
;
14899 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14900 _("immediate out of range for insert"));
14901 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14905 do_neon_qshlu_imm (void)
14907 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14908 struct neon_type_el et
= neon_check_type (2, rs
,
14909 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14910 int imm
= inst
.operands
[2].imm
;
14911 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14912 _("immediate out of range for shift"));
14913 /* Only encodes the 'U present' variant of the instruction.
14914 In this case, signed types have OP (bit 8) set to 0.
14915 Unsigned types have OP set to 1. */
14916 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14917 /* The rest of the bits are the same as other immediate shifts. */
14918 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14922 do_neon_qmovn (void)
14924 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14925 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14926 /* Saturating move where operands can be signed or unsigned, and the
14927 destination has the same signedness. */
14928 NEON_ENCODE (INTEGER
, inst
);
14929 if (et
.type
== NT_unsigned
)
14930 inst
.instruction
|= 0xc0;
14932 inst
.instruction
|= 0x80;
14933 neon_two_same (0, 1, et
.size
/ 2);
14937 do_neon_qmovun (void)
14939 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14940 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14941 /* Saturating move with unsigned results. Operands must be signed. */
14942 NEON_ENCODE (INTEGER
, inst
);
14943 neon_two_same (0, 1, et
.size
/ 2);
14947 do_neon_rshift_sat_narrow (void)
14949 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14950 or unsigned. If operands are unsigned, results must also be unsigned. */
14951 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14952 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14953 int imm
= inst
.operands
[2].imm
;
14954 /* This gets the bounds check, size encoding and immediate bits calculation
14958 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14959 VQMOVN.I<size> <Dd>, <Qm>. */
14962 inst
.operands
[2].present
= 0;
14963 inst
.instruction
= N_MNEM_vqmovn
;
14968 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14969 _("immediate out of range"));
14970 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14974 do_neon_rshift_sat_narrow_u (void)
14976 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14977 or unsigned. If operands are unsigned, results must also be unsigned. */
14978 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14979 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14980 int imm
= inst
.operands
[2].imm
;
14981 /* This gets the bounds check, size encoding and immediate bits calculation
14985 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14986 VQMOVUN.I<size> <Dd>, <Qm>. */
14989 inst
.operands
[2].present
= 0;
14990 inst
.instruction
= N_MNEM_vqmovun
;
14995 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14996 _("immediate out of range"));
14997 /* FIXME: The manual is kind of unclear about what value U should have in
14998 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15000 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15004 do_neon_movn (void)
15006 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15007 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15008 NEON_ENCODE (INTEGER
, inst
);
15009 neon_two_same (0, 1, et
.size
/ 2);
15013 do_neon_rshift_narrow (void)
15015 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15016 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15017 int imm
= inst
.operands
[2].imm
;
15018 /* This gets the bounds check, size encoding and immediate bits calculation
15022 /* If immediate is zero then we are a pseudo-instruction for
15023 VMOVN.I<size> <Dd>, <Qm> */
15026 inst
.operands
[2].present
= 0;
15027 inst
.instruction
= N_MNEM_vmovn
;
15032 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15033 _("immediate out of range for narrowing operation"));
15034 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15038 do_neon_shll (void)
15040 /* FIXME: Type checking when lengthening. */
15041 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15042 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15043 unsigned imm
= inst
.operands
[2].imm
;
15045 if (imm
== et
.size
)
15047 /* Maximum shift variant. */
15048 NEON_ENCODE (INTEGER
, inst
);
15049 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15050 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15051 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15052 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15053 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15055 neon_dp_fixup (&inst
);
15059 /* A more-specific type check for non-max versions. */
15060 et
= neon_check_type (2, NS_QDI
,
15061 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15062 NEON_ENCODE (IMMED
, inst
);
15063 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15067 /* Check the various types for the VCVT instruction, and return which version
15068 the current instruction is. */
15070 #define CVT_FLAVOUR_VAR \
15071 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15072 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15073 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15074 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15075 /* Half-precision conversions. */ \
15076 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15077 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15078 /* VFP instructions. */ \
15079 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15080 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15081 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15082 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15083 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15084 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15085 /* VFP instructions with bitshift. */ \
15086 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15087 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15088 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15089 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15090 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15091 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15092 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15093 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15095 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15096 neon_cvt_flavour_##C,
15098 /* The different types of conversions we can do. */
15099 enum neon_cvt_flavour
15102 neon_cvt_flavour_invalid
,
15103 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15108 static enum neon_cvt_flavour
15109 get_neon_cvt_flavour (enum neon_shape rs
)
15111 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15112 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15113 if (et.type != NT_invtype) \
15115 inst.error = NULL; \
15116 return (neon_cvt_flavour_##C); \
15119 struct neon_type_el et
;
15120 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15121 || rs
== NS_FF
) ? N_VFP
: 0;
15122 /* The instruction versions which take an immediate take one register
15123 argument, which is extended to the width of the full register. Thus the
15124 "source" and "destination" registers must have the same width. Hack that
15125 here by making the size equal to the key (wider, in this case) operand. */
15126 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15130 return neon_cvt_flavour_invalid
;
15145 /* Neon-syntax VFP conversions. */
15148 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15150 const char *opname
= 0;
15152 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
15154 /* Conversions with immediate bitshift. */
15155 const char *enc
[] =
15157 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15163 if (flavour
< (int) ARRAY_SIZE (enc
))
15165 opname
= enc
[flavour
];
15166 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15167 _("operands 0 and 1 must be the same register"));
15168 inst
.operands
[1] = inst
.operands
[2];
15169 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15174 /* Conversions without bitshift. */
15175 const char *enc
[] =
15177 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15183 if (flavour
< (int) ARRAY_SIZE (enc
))
15184 opname
= enc
[flavour
];
15188 do_vfp_nsyn_opcode (opname
);
15192 do_vfp_nsyn_cvtz (void)
15194 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
15195 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15196 const char *enc
[] =
15198 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15204 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15205 do_vfp_nsyn_opcode (enc
[flavour
]);
15209 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15210 enum neon_cvt_mode mode
)
15215 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15216 D register operands. */
15217 if (flavour
== neon_cvt_flavour_s32_f64
15218 || flavour
== neon_cvt_flavour_u32_f64
)
15219 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15222 set_it_insn_type (OUTSIDE_IT_INSN
);
15226 case neon_cvt_flavour_s32_f64
:
15230 case neon_cvt_flavour_s32_f32
:
15234 case neon_cvt_flavour_u32_f64
:
15238 case neon_cvt_flavour_u32_f32
:
15243 first_error (_("invalid instruction shape"));
15249 case neon_cvt_mode_a
: rm
= 0; break;
15250 case neon_cvt_mode_n
: rm
= 1; break;
15251 case neon_cvt_mode_p
: rm
= 2; break;
15252 case neon_cvt_mode_m
: rm
= 3; break;
15253 default: first_error (_("invalid rounding mode")); return;
15256 NEON_ENCODE (FPV8
, inst
);
15257 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15258 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15259 inst
.instruction
|= sz
<< 8;
15260 inst
.instruction
|= op
<< 7;
15261 inst
.instruction
|= rm
<< 16;
15262 inst
.instruction
|= 0xf0000000;
15263 inst
.is_neon
= TRUE
;
15267 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15269 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15270 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
15271 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15273 /* PR11109: Handle round-to-zero for VCVT conversions. */
15274 if (mode
== neon_cvt_mode_z
15275 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15276 && (flavour
== neon_cvt_flavour_s32_f32
15277 || flavour
== neon_cvt_flavour_u32_f32
15278 || flavour
== neon_cvt_flavour_s32_f64
15279 || flavour
== neon_cvt_flavour_u32_f64
)
15280 && (rs
== NS_FD
|| rs
== NS_FF
))
15282 do_vfp_nsyn_cvtz ();
15286 /* VFP rather than Neon conversions. */
15287 if (flavour
>= neon_cvt_flavour_first_fp
)
15289 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15290 do_vfp_nsyn_cvt (rs
, flavour
);
15292 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15303 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15305 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15308 /* Fixed-point conversion with #0 immediate is encoded as an
15309 integer conversion. */
15310 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15312 immbits
= 32 - inst
.operands
[2].imm
;
15313 NEON_ENCODE (IMMED
, inst
);
15314 if (flavour
!= neon_cvt_flavour_invalid
)
15315 inst
.instruction
|= enctab
[flavour
];
15316 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15317 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15318 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15319 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15320 inst
.instruction
|= neon_quad (rs
) << 6;
15321 inst
.instruction
|= 1 << 21;
15322 inst
.instruction
|= immbits
<< 16;
15324 neon_dp_fixup (&inst
);
15330 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15332 NEON_ENCODE (FLOAT
, inst
);
15333 set_it_insn_type (OUTSIDE_IT_INSN
);
15335 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15338 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15339 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15340 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15341 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15342 inst
.instruction
|= neon_quad (rs
) << 6;
15343 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
15344 inst
.instruction
|= mode
<< 8;
15346 inst
.instruction
|= 0xfc000000;
15348 inst
.instruction
|= 0xf0000000;
15354 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
15356 NEON_ENCODE (INTEGER
, inst
);
15358 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15361 if (flavour
!= neon_cvt_flavour_invalid
)
15362 inst
.instruction
|= enctab
[flavour
];
15364 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15365 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15366 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15367 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15368 inst
.instruction
|= neon_quad (rs
) << 6;
15369 inst
.instruction
|= 2 << 18;
15371 neon_dp_fixup (&inst
);
15376 /* Half-precision conversions for Advanced SIMD -- neon. */
15381 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15383 as_bad (_("operand size must match register width"));
15388 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15390 as_bad (_("operand size must match register width"));
15395 inst
.instruction
= 0x3b60600;
15397 inst
.instruction
= 0x3b60700;
15399 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15400 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15401 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15402 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15403 neon_dp_fixup (&inst
);
15407 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15408 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15409 do_vfp_nsyn_cvt (rs
, flavour
);
15411 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15416 do_neon_cvtr (void)
15418 do_neon_cvt_1 (neon_cvt_mode_x
);
15424 do_neon_cvt_1 (neon_cvt_mode_z
);
15428 do_neon_cvta (void)
15430 do_neon_cvt_1 (neon_cvt_mode_a
);
15434 do_neon_cvtn (void)
15436 do_neon_cvt_1 (neon_cvt_mode_n
);
15440 do_neon_cvtp (void)
15442 do_neon_cvt_1 (neon_cvt_mode_p
);
15446 do_neon_cvtm (void)
15448 do_neon_cvt_1 (neon_cvt_mode_m
);
15452 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15455 mark_feature_used (&fpu_vfp_ext_armv8
);
15457 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15458 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15459 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15460 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15461 inst
.instruction
|= to
? 0x10000 : 0;
15462 inst
.instruction
|= t
? 0x80 : 0;
15463 inst
.instruction
|= is_double
? 0x100 : 0;
15464 do_vfp_cond_or_thumb ();
15468 do_neon_cvttb_1 (bfd_boolean t
)
15470 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15474 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15477 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15479 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15482 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15484 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15486 /* The VCVTB and VCVTT instructions with D-register operands
15487 don't work for SP only targets. */
15488 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15492 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15494 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15496 /* The VCVTB and VCVTT instructions with D-register operands
15497 don't work for SP only targets. */
15498 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15502 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15509 do_neon_cvtb (void)
15511 do_neon_cvttb_1 (FALSE
);
15516 do_neon_cvtt (void)
15518 do_neon_cvttb_1 (TRUE
);
15522 neon_move_immediate (void)
15524 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15525 struct neon_type_el et
= neon_check_type (2, rs
,
15526 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15527 unsigned immlo
, immhi
= 0, immbits
;
15528 int op
, cmode
, float_p
;
15530 constraint (et
.type
== NT_invtype
,
15531 _("operand size must be specified for immediate VMOV"));
15533 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15534 op
= (inst
.instruction
& (1 << 5)) != 0;
15536 immlo
= inst
.operands
[1].imm
;
15537 if (inst
.operands
[1].regisimm
)
15538 immhi
= inst
.operands
[1].reg
;
15540 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15541 _("immediate has bits set outside the operand size"));
15543 float_p
= inst
.operands
[1].immisfloat
;
15545 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15546 et
.size
, et
.type
)) == FAIL
)
15548 /* Invert relevant bits only. */
15549 neon_invert_size (&immlo
, &immhi
, et
.size
);
15550 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15551 with one or the other; those cases are caught by
15552 neon_cmode_for_move_imm. */
15554 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15555 &op
, et
.size
, et
.type
)) == FAIL
)
15557 first_error (_("immediate out of range"));
15562 inst
.instruction
&= ~(1 << 5);
15563 inst
.instruction
|= op
<< 5;
15565 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15566 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15567 inst
.instruction
|= neon_quad (rs
) << 6;
15568 inst
.instruction
|= cmode
<< 8;
15570 neon_write_immbits (immbits
);
15576 if (inst
.operands
[1].isreg
)
15578 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15580 NEON_ENCODE (INTEGER
, inst
);
15581 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15582 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15583 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15584 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15585 inst
.instruction
|= neon_quad (rs
) << 6;
15589 NEON_ENCODE (IMMED
, inst
);
15590 neon_move_immediate ();
15593 neon_dp_fixup (&inst
);
15596 /* Encode instructions of form:
15598 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15599 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15602 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15604 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15605 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15606 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15607 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15608 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15609 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15610 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15611 inst
.instruction
|= neon_logbits (size
) << 20;
15613 neon_dp_fixup (&inst
);
15617 do_neon_dyadic_long (void)
15619 /* FIXME: Type checking for lengthening op. */
15620 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15621 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15622 neon_mixed_length (et
, et
.size
);
15626 do_neon_abal (void)
15628 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15629 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15630 neon_mixed_length (et
, et
.size
);
15634 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15636 if (inst
.operands
[2].isscalar
)
15638 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15639 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15640 NEON_ENCODE (SCALAR
, inst
);
15641 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15645 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15646 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15647 NEON_ENCODE (INTEGER
, inst
);
15648 neon_mixed_length (et
, et
.size
);
15653 do_neon_mac_maybe_scalar_long (void)
15655 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15659 do_neon_dyadic_wide (void)
15661 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15662 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15663 neon_mixed_length (et
, et
.size
);
15667 do_neon_dyadic_narrow (void)
15669 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15670 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15671 /* Operand sign is unimportant, and the U bit is part of the opcode,
15672 so force the operand type to integer. */
15673 et
.type
= NT_integer
;
15674 neon_mixed_length (et
, et
.size
/ 2);
15678 do_neon_mul_sat_scalar_long (void)
15680 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15684 do_neon_vmull (void)
15686 if (inst
.operands
[2].isscalar
)
15687 do_neon_mac_maybe_scalar_long ();
15690 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15691 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15693 if (et
.type
== NT_poly
)
15694 NEON_ENCODE (POLY
, inst
);
15696 NEON_ENCODE (INTEGER
, inst
);
15698 /* For polynomial encoding the U bit must be zero, and the size must
15699 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15700 obviously, as 0b10). */
15703 /* Check we're on the correct architecture. */
15704 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15706 _("Instruction form not available on this architecture.");
15711 neon_mixed_length (et
, et
.size
);
15718 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15719 struct neon_type_el et
= neon_check_type (3, rs
,
15720 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15721 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15723 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15724 _("shift out of range"));
15725 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15726 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15727 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15728 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15729 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15730 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15731 inst
.instruction
|= neon_quad (rs
) << 6;
15732 inst
.instruction
|= imm
<< 8;
15734 neon_dp_fixup (&inst
);
15740 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15741 struct neon_type_el et
= neon_check_type (2, rs
,
15742 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15743 unsigned op
= (inst
.instruction
>> 7) & 3;
15744 /* N (width of reversed regions) is encoded as part of the bitmask. We
15745 extract it here to check the elements to be reversed are smaller.
15746 Otherwise we'd get a reserved instruction. */
15747 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15748 gas_assert (elsize
!= 0);
15749 constraint (et
.size
>= elsize
,
15750 _("elements must be smaller than reversal region"));
15751 neon_two_same (neon_quad (rs
), 1, et
.size
);
15757 if (inst
.operands
[1].isscalar
)
15759 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15760 struct neon_type_el et
= neon_check_type (2, rs
,
15761 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15762 unsigned sizebits
= et
.size
>> 3;
15763 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15764 int logsize
= neon_logbits (et
.size
);
15765 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15767 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15770 NEON_ENCODE (SCALAR
, inst
);
15771 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15772 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15773 inst
.instruction
|= LOW4 (dm
);
15774 inst
.instruction
|= HI1 (dm
) << 5;
15775 inst
.instruction
|= neon_quad (rs
) << 6;
15776 inst
.instruction
|= x
<< 17;
15777 inst
.instruction
|= sizebits
<< 16;
15779 neon_dp_fixup (&inst
);
15783 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15784 struct neon_type_el et
= neon_check_type (2, rs
,
15785 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15786 /* Duplicate ARM register to lanes of vector. */
15787 NEON_ENCODE (ARMREG
, inst
);
15790 case 8: inst
.instruction
|= 0x400000; break;
15791 case 16: inst
.instruction
|= 0x000020; break;
15792 case 32: inst
.instruction
|= 0x000000; break;
15795 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15796 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15797 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15798 inst
.instruction
|= neon_quad (rs
) << 21;
15799 /* The encoding for this instruction is identical for the ARM and Thumb
15800 variants, except for the condition field. */
15801 do_vfp_cond_or_thumb ();
15805 /* VMOV has particularly many variations. It can be one of:
15806 0. VMOV<c><q> <Qd>, <Qm>
15807 1. VMOV<c><q> <Dd>, <Dm>
15808 (Register operations, which are VORR with Rm = Rn.)
15809 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15810 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15812 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15813 (ARM register to scalar.)
15814 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15815 (Two ARM registers to vector.)
15816 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15817 (Scalar to ARM register.)
15818 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15819 (Vector to two ARM registers.)
15820 8. VMOV.F32 <Sd>, <Sm>
15821 9. VMOV.F64 <Dd>, <Dm>
15822 (VFP register moves.)
15823 10. VMOV.F32 <Sd>, #imm
15824 11. VMOV.F64 <Dd>, #imm
15825 (VFP float immediate load.)
15826 12. VMOV <Rd>, <Sm>
15827 (VFP single to ARM reg.)
15828 13. VMOV <Sd>, <Rm>
15829 (ARM reg to VFP single.)
15830 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15831 (Two ARM regs to two VFP singles.)
15832 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15833 (Two VFP singles to two ARM regs.)
15835 These cases can be disambiguated using neon_select_shape, except cases 1/9
15836 and 3/11 which depend on the operand type too.
15838 All the encoded bits are hardcoded by this function.
15840 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15841 Cases 5, 7 may be used with VFPv2 and above.
15843 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15844 can specify a type where it doesn't make sense to, and is ignored). */
15849 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15850 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15852 struct neon_type_el et
;
15853 const char *ldconst
= 0;
15857 case NS_DD
: /* case 1/9. */
15858 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15859 /* It is not an error here if no type is given. */
15861 if (et
.type
== NT_float
&& et
.size
== 64)
15863 do_vfp_nsyn_opcode ("fcpyd");
15866 /* fall through. */
15868 case NS_QQ
: /* case 0/1. */
15870 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15872 /* The architecture manual I have doesn't explicitly state which
15873 value the U bit should have for register->register moves, but
15874 the equivalent VORR instruction has U = 0, so do that. */
15875 inst
.instruction
= 0x0200110;
15876 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15877 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15878 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15879 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15880 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15881 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15882 inst
.instruction
|= neon_quad (rs
) << 6;
15884 neon_dp_fixup (&inst
);
15888 case NS_DI
: /* case 3/11. */
15889 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15891 if (et
.type
== NT_float
&& et
.size
== 64)
15893 /* case 11 (fconstd). */
15894 ldconst
= "fconstd";
15895 goto encode_fconstd
;
15897 /* fall through. */
15899 case NS_QI
: /* case 2/3. */
15900 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15902 inst
.instruction
= 0x0800010;
15903 neon_move_immediate ();
15904 neon_dp_fixup (&inst
);
15907 case NS_SR
: /* case 4. */
15909 unsigned bcdebits
= 0;
15911 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15912 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15914 /* .<size> is optional here, defaulting to .32. */
15915 if (inst
.vectype
.elems
== 0
15916 && inst
.operands
[0].vectype
.type
== NT_invtype
15917 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15919 inst
.vectype
.el
[0].type
= NT_untyped
;
15920 inst
.vectype
.el
[0].size
= 32;
15921 inst
.vectype
.elems
= 1;
15924 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15925 logsize
= neon_logbits (et
.size
);
15927 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15929 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15930 && et
.size
!= 32, _(BAD_FPU
));
15931 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15932 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15936 case 8: bcdebits
= 0x8; break;
15937 case 16: bcdebits
= 0x1; break;
15938 case 32: bcdebits
= 0x0; break;
15942 bcdebits
|= x
<< logsize
;
15944 inst
.instruction
= 0xe000b10;
15945 do_vfp_cond_or_thumb ();
15946 inst
.instruction
|= LOW4 (dn
) << 16;
15947 inst
.instruction
|= HI1 (dn
) << 7;
15948 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15949 inst
.instruction
|= (bcdebits
& 3) << 5;
15950 inst
.instruction
|= (bcdebits
>> 2) << 21;
15954 case NS_DRR
: /* case 5 (fmdrr). */
15955 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15958 inst
.instruction
= 0xc400b10;
15959 do_vfp_cond_or_thumb ();
15960 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15961 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15962 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15963 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15966 case NS_RS
: /* case 6. */
15969 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15970 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15971 unsigned abcdebits
= 0;
15973 /* .<dt> is optional here, defaulting to .32. */
15974 if (inst
.vectype
.elems
== 0
15975 && inst
.operands
[0].vectype
.type
== NT_invtype
15976 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15978 inst
.vectype
.el
[0].type
= NT_untyped
;
15979 inst
.vectype
.el
[0].size
= 32;
15980 inst
.vectype
.elems
= 1;
15983 et
= neon_check_type (2, NS_NULL
,
15984 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15985 logsize
= neon_logbits (et
.size
);
15987 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15989 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15990 && et
.size
!= 32, _(BAD_FPU
));
15991 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15992 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15996 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
15997 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
15998 case 32: abcdebits
= 0x00; break;
16002 abcdebits
|= x
<< logsize
;
16003 inst
.instruction
= 0xe100b10;
16004 do_vfp_cond_or_thumb ();
16005 inst
.instruction
|= LOW4 (dn
) << 16;
16006 inst
.instruction
|= HI1 (dn
) << 7;
16007 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16008 inst
.instruction
|= (abcdebits
& 3) << 5;
16009 inst
.instruction
|= (abcdebits
>> 2) << 21;
16013 case NS_RRD
: /* case 7 (fmrrd). */
16014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16017 inst
.instruction
= 0xc500b10;
16018 do_vfp_cond_or_thumb ();
16019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16020 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16021 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16022 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16025 case NS_FF
: /* case 8 (fcpys). */
16026 do_vfp_nsyn_opcode ("fcpys");
16029 case NS_FI
: /* case 10 (fconsts). */
16030 ldconst
= "fconsts";
16032 if (is_quarter_float (inst
.operands
[1].imm
))
16034 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16035 do_vfp_nsyn_opcode (ldconst
);
16038 first_error (_("immediate out of range"));
16041 case NS_RF
: /* case 12 (fmrs). */
16042 do_vfp_nsyn_opcode ("fmrs");
16045 case NS_FR
: /* case 13 (fmsr). */
16046 do_vfp_nsyn_opcode ("fmsr");
16049 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16050 (one of which is a list), but we have parsed four. Do some fiddling to
16051 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16053 case NS_RRFF
: /* case 14 (fmrrs). */
16054 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16055 _("VFP registers must be adjacent"));
16056 inst
.operands
[2].imm
= 2;
16057 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16058 do_vfp_nsyn_opcode ("fmrrs");
16061 case NS_FFRR
: /* case 15 (fmsrr). */
16062 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16063 _("VFP registers must be adjacent"));
16064 inst
.operands
[1] = inst
.operands
[2];
16065 inst
.operands
[2] = inst
.operands
[3];
16066 inst
.operands
[0].imm
= 2;
16067 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16068 do_vfp_nsyn_opcode ("fmsrr");
16072 /* neon_select_shape has determined that the instruction
16073 shape is wrong and has already set the error message. */
16082 do_neon_rshift_round_imm (void)
16084 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16085 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16086 int imm
= inst
.operands
[2].imm
;
16088 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16091 inst
.operands
[2].present
= 0;
16096 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16097 _("immediate out of range for shift"));
16098 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16103 do_neon_movl (void)
16105 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16106 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16107 unsigned sizebits
= et
.size
>> 3;
16108 inst
.instruction
|= sizebits
<< 19;
16109 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16115 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16116 struct neon_type_el et
= neon_check_type (2, rs
,
16117 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16118 NEON_ENCODE (INTEGER
, inst
);
16119 neon_two_same (neon_quad (rs
), 1, et
.size
);
16123 do_neon_zip_uzp (void)
16125 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16126 struct neon_type_el et
= neon_check_type (2, rs
,
16127 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16128 if (rs
== NS_DD
&& et
.size
== 32)
16130 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16131 inst
.instruction
= N_MNEM_vtrn
;
16135 neon_two_same (neon_quad (rs
), 1, et
.size
);
16139 do_neon_sat_abs_neg (void)
16141 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16142 struct neon_type_el et
= neon_check_type (2, rs
,
16143 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16144 neon_two_same (neon_quad (rs
), 1, et
.size
);
16148 do_neon_pair_long (void)
16150 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16151 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16152 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16153 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16154 neon_two_same (neon_quad (rs
), 1, et
.size
);
16158 do_neon_recip_est (void)
16160 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16161 struct neon_type_el et
= neon_check_type (2, rs
,
16162 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
16163 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16164 neon_two_same (neon_quad (rs
), 1, et
.size
);
16170 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16171 struct neon_type_el et
= neon_check_type (2, rs
,
16172 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16173 neon_two_same (neon_quad (rs
), 1, et
.size
);
16179 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16180 struct neon_type_el et
= neon_check_type (2, rs
,
16181 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16182 neon_two_same (neon_quad (rs
), 1, et
.size
);
16188 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16189 struct neon_type_el et
= neon_check_type (2, rs
,
16190 N_EQK
| N_INT
, N_8
| N_KEY
);
16191 neon_two_same (neon_quad (rs
), 1, et
.size
);
16197 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16198 neon_two_same (neon_quad (rs
), 1, -1);
16202 do_neon_tbl_tbx (void)
16204 unsigned listlenbits
;
16205 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16207 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16209 first_error (_("bad list length for table lookup"));
16213 listlenbits
= inst
.operands
[1].imm
- 1;
16214 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16215 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16216 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16217 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16218 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16219 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16220 inst
.instruction
|= listlenbits
<< 8;
16222 neon_dp_fixup (&inst
);
16226 do_neon_ldm_stm (void)
16228 /* P, U and L bits are part of bitmask. */
16229 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16230 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16232 if (inst
.operands
[1].issingle
)
16234 do_vfp_nsyn_ldm_stm (is_dbmode
);
16238 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16239 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16241 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16242 _("register list must contain at least 1 and at most 16 "
16245 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16246 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16247 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16248 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16250 inst
.instruction
|= offsetbits
;
16252 do_vfp_cond_or_thumb ();
16256 do_neon_ldr_str (void)
16258 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16260 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16261 And is UNPREDICTABLE in thumb mode. */
16263 && inst
.operands
[1].reg
== REG_PC
16264 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16267 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16268 else if (warn_on_deprecated
)
16269 as_tsktsk (_("Use of PC here is deprecated"));
16272 if (inst
.operands
[0].issingle
)
16275 do_vfp_nsyn_opcode ("flds");
16277 do_vfp_nsyn_opcode ("fsts");
16282 do_vfp_nsyn_opcode ("fldd");
16284 do_vfp_nsyn_opcode ("fstd");
16288 /* "interleave" version also handles non-interleaving register VLD1/VST1
16292 do_neon_ld_st_interleave (void)
16294 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16295 N_8
| N_16
| N_32
| N_64
);
16296 unsigned alignbits
= 0;
16298 /* The bits in this table go:
16299 0: register stride of one (0) or two (1)
16300 1,2: register list length, minus one (1, 2, 3, 4).
16301 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16302 We use -1 for invalid entries. */
16303 const int typetable
[] =
16305 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16306 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16307 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16308 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16312 if (et
.type
== NT_invtype
)
16315 if (inst
.operands
[1].immisalign
)
16316 switch (inst
.operands
[1].imm
>> 8)
16318 case 64: alignbits
= 1; break;
16320 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16321 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16322 goto bad_alignment
;
16326 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16327 goto bad_alignment
;
16332 first_error (_("bad alignment"));
16336 inst
.instruction
|= alignbits
<< 4;
16337 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16339 /* Bits [4:6] of the immediate in a list specifier encode register stride
16340 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16341 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16342 up the right value for "type" in a table based on this value and the given
16343 list style, then stick it back. */
16344 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16345 | (((inst
.instruction
>> 8) & 3) << 3);
16347 typebits
= typetable
[idx
];
16349 constraint (typebits
== -1, _("bad list type for instruction"));
16350 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16351 _("bad element type for instruction"));
16353 inst
.instruction
&= ~0xf00;
16354 inst
.instruction
|= typebits
<< 8;
16357 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16358 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16359 otherwise. The variable arguments are a list of pairs of legal (size, align)
16360 values, terminated with -1. */
16363 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
16366 int result
= FAIL
, thissize
, thisalign
;
16368 if (!inst
.operands
[1].immisalign
)
16374 va_start (ap
, do_align
);
16378 thissize
= va_arg (ap
, int);
16379 if (thissize
== -1)
16381 thisalign
= va_arg (ap
, int);
16383 if (size
== thissize
&& align
== thisalign
)
16386 while (result
!= SUCCESS
);
16390 if (result
== SUCCESS
)
16393 first_error (_("unsupported alignment for instruction"));
16399 do_neon_ld_st_lane (void)
16401 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16402 int align_good
, do_align
= 0;
16403 int logsize
= neon_logbits (et
.size
);
16404 int align
= inst
.operands
[1].imm
>> 8;
16405 int n
= (inst
.instruction
>> 8) & 3;
16406 int max_el
= 64 / et
.size
;
16408 if (et
.type
== NT_invtype
)
16411 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16412 _("bad list length"));
16413 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16414 _("scalar index out of range"));
16415 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16417 _("stride of 2 unavailable when element size is 8"));
16421 case 0: /* VLD1 / VST1. */
16422 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16424 if (align_good
== FAIL
)
16428 unsigned alignbits
= 0;
16431 case 16: alignbits
= 0x1; break;
16432 case 32: alignbits
= 0x3; break;
16435 inst
.instruction
|= alignbits
<< 4;
16439 case 1: /* VLD2 / VST2. */
16440 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16442 if (align_good
== FAIL
)
16445 inst
.instruction
|= 1 << 4;
16448 case 2: /* VLD3 / VST3. */
16449 constraint (inst
.operands
[1].immisalign
,
16450 _("can't use alignment with this instruction"));
16453 case 3: /* VLD4 / VST4. */
16454 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16455 16, 64, 32, 64, 32, 128, -1);
16456 if (align_good
== FAIL
)
16460 unsigned alignbits
= 0;
16463 case 8: alignbits
= 0x1; break;
16464 case 16: alignbits
= 0x1; break;
16465 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16468 inst
.instruction
|= alignbits
<< 4;
16475 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16476 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16477 inst
.instruction
|= 1 << (4 + logsize
);
16479 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16480 inst
.instruction
|= logsize
<< 10;
16483 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16486 do_neon_ld_dup (void)
16488 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16489 int align_good
, do_align
= 0;
16491 if (et
.type
== NT_invtype
)
16494 switch ((inst
.instruction
>> 8) & 3)
16496 case 0: /* VLD1. */
16497 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16498 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16499 &do_align
, 16, 16, 32, 32, -1);
16500 if (align_good
== FAIL
)
16502 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16505 case 2: inst
.instruction
|= 1 << 5; break;
16506 default: first_error (_("bad list length")); return;
16508 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16511 case 1: /* VLD2. */
16512 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16513 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16514 if (align_good
== FAIL
)
16516 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16517 _("bad list length"));
16518 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16519 inst
.instruction
|= 1 << 5;
16520 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16523 case 2: /* VLD3. */
16524 constraint (inst
.operands
[1].immisalign
,
16525 _("can't use alignment with this instruction"));
16526 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16527 _("bad list length"));
16528 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16529 inst
.instruction
|= 1 << 5;
16530 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16533 case 3: /* VLD4. */
16535 int align
= inst
.operands
[1].imm
>> 8;
16536 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16537 16, 64, 32, 64, 32, 128, -1);
16538 if (align_good
== FAIL
)
16540 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16541 _("bad list length"));
16542 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16543 inst
.instruction
|= 1 << 5;
16544 if (et
.size
== 32 && align
== 128)
16545 inst
.instruction
|= 0x3 << 6;
16547 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16554 inst
.instruction
|= do_align
<< 4;
16557 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16558 apart from bits [11:4]. */
16561 do_neon_ldx_stx (void)
16563 if (inst
.operands
[1].isreg
)
16564 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16566 switch (NEON_LANE (inst
.operands
[0].imm
))
16568 case NEON_INTERLEAVE_LANES
:
16569 NEON_ENCODE (INTERLV
, inst
);
16570 do_neon_ld_st_interleave ();
16573 case NEON_ALL_LANES
:
16574 NEON_ENCODE (DUP
, inst
);
16575 if (inst
.instruction
== N_INV
)
16577 first_error ("only loads support such operands");
16584 NEON_ENCODE (LANE
, inst
);
16585 do_neon_ld_st_lane ();
16588 /* L bit comes from bit mask. */
16589 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16590 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16591 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16593 if (inst
.operands
[1].postind
)
16595 int postreg
= inst
.operands
[1].imm
& 0xf;
16596 constraint (!inst
.operands
[1].immisreg
,
16597 _("post-index must be a register"));
16598 constraint (postreg
== 0xd || postreg
== 0xf,
16599 _("bad register for post-index"));
16600 inst
.instruction
|= postreg
;
16604 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16605 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16606 || inst
.reloc
.exp
.X_add_number
!= 0,
16609 if (inst
.operands
[1].writeback
)
16611 inst
.instruction
|= 0xd;
16614 inst
.instruction
|= 0xf;
16618 inst
.instruction
|= 0xf9000000;
16620 inst
.instruction
|= 0xf4000000;
16625 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16627 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16628 D register operands. */
16629 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16630 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16633 NEON_ENCODE (FPV8
, inst
);
16636 do_vfp_sp_dyadic ();
16638 do_vfp_dp_rd_rn_rm ();
16641 inst
.instruction
|= 0x100;
16643 inst
.instruction
|= 0xf0000000;
16649 set_it_insn_type (OUTSIDE_IT_INSN
);
16651 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16652 first_error (_("invalid instruction shape"));
16658 set_it_insn_type (OUTSIDE_IT_INSN
);
16660 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16663 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16666 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16670 do_vrint_1 (enum neon_cvt_mode mode
)
16672 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16673 struct neon_type_el et
;
16678 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16679 D register operands. */
16680 if (neon_shape_class
[rs
] == SC_DOUBLE
)
16681 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16684 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16685 if (et
.type
!= NT_invtype
)
16687 /* VFP encodings. */
16688 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16689 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16690 set_it_insn_type (OUTSIDE_IT_INSN
);
16692 NEON_ENCODE (FPV8
, inst
);
16694 do_vfp_sp_monadic ();
16696 do_vfp_dp_rd_rm ();
16700 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16701 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16702 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16703 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16704 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16705 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16706 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16710 inst
.instruction
|= (rs
== NS_DD
) << 8;
16711 do_vfp_cond_or_thumb ();
16715 /* Neon encodings (or something broken...). */
16717 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16719 if (et
.type
== NT_invtype
)
16722 set_it_insn_type (OUTSIDE_IT_INSN
);
16723 NEON_ENCODE (FLOAT
, inst
);
16725 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16728 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16729 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16730 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16731 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16732 inst
.instruction
|= neon_quad (rs
) << 6;
16735 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16736 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16737 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16738 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16739 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16740 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16741 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16746 inst
.instruction
|= 0xfc000000;
16748 inst
.instruction
|= 0xf0000000;
16755 do_vrint_1 (neon_cvt_mode_x
);
16761 do_vrint_1 (neon_cvt_mode_z
);
16767 do_vrint_1 (neon_cvt_mode_r
);
16773 do_vrint_1 (neon_cvt_mode_a
);
16779 do_vrint_1 (neon_cvt_mode_n
);
16785 do_vrint_1 (neon_cvt_mode_p
);
16791 do_vrint_1 (neon_cvt_mode_m
);
16794 /* Crypto v1 instructions. */
16796 do_crypto_2op_1 (unsigned elttype
, int op
)
16798 set_it_insn_type (OUTSIDE_IT_INSN
);
16800 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16806 NEON_ENCODE (INTEGER
, inst
);
16807 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16808 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16809 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16810 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16812 inst
.instruction
|= op
<< 6;
16815 inst
.instruction
|= 0xfc000000;
16817 inst
.instruction
|= 0xf0000000;
16821 do_crypto_3op_1 (int u
, int op
)
16823 set_it_insn_type (OUTSIDE_IT_INSN
);
16825 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16826 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16831 NEON_ENCODE (INTEGER
, inst
);
16832 neon_three_same (1, u
, 8 << op
);
16838 do_crypto_2op_1 (N_8
, 0);
16844 do_crypto_2op_1 (N_8
, 1);
16850 do_crypto_2op_1 (N_8
, 2);
16856 do_crypto_2op_1 (N_8
, 3);
16862 do_crypto_3op_1 (0, 0);
16868 do_crypto_3op_1 (0, 1);
16874 do_crypto_3op_1 (0, 2);
16880 do_crypto_3op_1 (0, 3);
16886 do_crypto_3op_1 (1, 0);
16892 do_crypto_3op_1 (1, 1);
16896 do_sha256su1 (void)
16898 do_crypto_3op_1 (1, 2);
16904 do_crypto_2op_1 (N_32
, -1);
16910 do_crypto_2op_1 (N_32
, 0);
16914 do_sha256su0 (void)
16916 do_crypto_2op_1 (N_32
, 1);
16920 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16922 unsigned int Rd
= inst
.operands
[0].reg
;
16923 unsigned int Rn
= inst
.operands
[1].reg
;
16924 unsigned int Rm
= inst
.operands
[2].reg
;
16926 set_it_insn_type (OUTSIDE_IT_INSN
);
16927 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16928 inst
.instruction
|= LOW4 (Rn
) << 16;
16929 inst
.instruction
|= LOW4 (Rm
);
16930 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16931 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16933 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16934 as_warn (UNPRED_REG ("r15"));
16935 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16936 as_warn (UNPRED_REG ("r13"));
16976 /* Overall per-instruction processing. */
16978 /* We need to be able to fix up arbitrary expressions in some statements.
16979 This is so that we can handle symbols that are an arbitrary distance from
16980 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16981 which returns part of an address in a form which will be valid for
16982 a data instruction. We do this by pushing the expression into a symbol
16983 in the expr_section, and creating a fix for that. */
16986 fix_new_arm (fragS
* frag
,
17000 /* Create an absolute valued symbol, so we have something to
17001 refer to in the object file. Unfortunately for us, gas's
17002 generic expression parsing will already have folded out
17003 any use of .set foo/.type foo %function that may have
17004 been used to set type information of the target location,
17005 that's being specified symbolically. We have to presume
17006 the user knows what they are doing. */
17010 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17012 symbol
= symbol_find_or_make (name
);
17013 S_SET_SEGMENT (symbol
, absolute_section
);
17014 symbol_set_frag (symbol
, &zero_address_frag
);
17015 S_SET_VALUE (symbol
, exp
->X_add_number
);
17016 exp
->X_op
= O_symbol
;
17017 exp
->X_add_symbol
= symbol
;
17018 exp
->X_add_number
= 0;
17024 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17025 (enum bfd_reloc_code_real
) reloc
);
17029 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17030 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17034 /* Mark whether the fix is to a THUMB instruction, or an ARM
17036 new_fix
->tc_fix_data
= thumb_mode
;
17039 /* Create a frg for an instruction requiring relaxation. */
17041 output_relax_insn (void)
17047 /* The size of the instruction is unknown, so tie the debug info to the
17048 start of the instruction. */
17049 dwarf2_emit_insn (0);
17051 switch (inst
.reloc
.exp
.X_op
)
17054 sym
= inst
.reloc
.exp
.X_add_symbol
;
17055 offset
= inst
.reloc
.exp
.X_add_number
;
17059 offset
= inst
.reloc
.exp
.X_add_number
;
17062 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17066 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17067 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17068 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17071 /* Write a 32-bit thumb instruction to buf. */
17073 put_thumb32_insn (char * buf
, unsigned long insn
)
17075 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17076 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17080 output_inst (const char * str
)
17086 as_bad ("%s -- `%s'", inst
.error
, str
);
17091 output_relax_insn ();
17094 if (inst
.size
== 0)
17097 to
= frag_more (inst
.size
);
17098 /* PR 9814: Record the thumb mode into the current frag so that we know
17099 what type of NOP padding to use, if necessary. We override any previous
17100 setting so that if the mode has changed then the NOPS that we use will
17101 match the encoding of the last instruction in the frag. */
17102 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17104 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17106 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17107 put_thumb32_insn (to
, inst
.instruction
);
17109 else if (inst
.size
> INSN_SIZE
)
17111 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17112 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17113 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17116 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17118 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17119 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17120 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17123 dwarf2_emit_insn (inst
.size
);
17127 output_it_inst (int cond
, int mask
, char * to
)
17129 unsigned long instruction
= 0xbf00;
17132 instruction
|= mask
;
17133 instruction
|= cond
<< 4;
17137 to
= frag_more (2);
17139 dwarf2_emit_insn (2);
17143 md_number_to_chars (to
, instruction
, 2);
17148 /* Tag values used in struct asm_opcode's tag field. */
17151 OT_unconditional
, /* Instruction cannot be conditionalized.
17152 The ARM condition field is still 0xE. */
17153 OT_unconditionalF
, /* Instruction cannot be conditionalized
17154 and carries 0xF in its ARM condition field. */
17155 OT_csuffix
, /* Instruction takes a conditional suffix. */
17156 OT_csuffixF
, /* Some forms of the instruction take a conditional
17157 suffix, others place 0xF where the condition field
17159 OT_cinfix3
, /* Instruction takes a conditional infix,
17160 beginning at character index 3. (In
17161 unified mode, it becomes a suffix.) */
17162 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17163 tsts, cmps, cmns, and teqs. */
17164 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17165 character index 3, even in unified mode. Used for
17166 legacy instructions where suffix and infix forms
17167 may be ambiguous. */
17168 OT_csuf_or_in3
, /* Instruction takes either a conditional
17169 suffix or an infix at character index 3. */
17170 OT_odd_infix_unc
, /* This is the unconditional variant of an
17171 instruction that takes a conditional infix
17172 at an unusual position. In unified mode,
17173 this variant will accept a suffix. */
17174 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17175 are the conditional variants of instructions that
17176 take conditional infixes in unusual positions.
17177 The infix appears at character index
17178 (tag - OT_odd_infix_0). These are not accepted
17179 in unified mode. */
17182 /* Subroutine of md_assemble, responsible for looking up the primary
17183 opcode from the mnemonic the user wrote. STR points to the
17184 beginning of the mnemonic.
17186 This is not simply a hash table lookup, because of conditional
17187 variants. Most instructions have conditional variants, which are
17188 expressed with a _conditional affix_ to the mnemonic. If we were
17189 to encode each conditional variant as a literal string in the opcode
17190 table, it would have approximately 20,000 entries.
17192 Most mnemonics take this affix as a suffix, and in unified syntax,
17193 'most' is upgraded to 'all'. However, in the divided syntax, some
17194 instructions take the affix as an infix, notably the s-variants of
17195 the arithmetic instructions. Of those instructions, all but six
17196 have the infix appear after the third character of the mnemonic.
17198 Accordingly, the algorithm for looking up primary opcodes given
17201 1. Look up the identifier in the opcode table.
17202 If we find a match, go to step U.
17204 2. Look up the last two characters of the identifier in the
17205 conditions table. If we find a match, look up the first N-2
17206 characters of the identifier in the opcode table. If we
17207 find a match, go to step CE.
17209 3. Look up the fourth and fifth characters of the identifier in
17210 the conditions table. If we find a match, extract those
17211 characters from the identifier, and look up the remaining
17212 characters in the opcode table. If we find a match, go
17217 U. Examine the tag field of the opcode structure, in case this is
17218 one of the six instructions with its conditional infix in an
17219 unusual place. If it is, the tag tells us where to find the
17220 infix; look it up in the conditions table and set inst.cond
17221 accordingly. Otherwise, this is an unconditional instruction.
17222 Again set inst.cond accordingly. Return the opcode structure.
17224 CE. Examine the tag field to make sure this is an instruction that
17225 should receive a conditional suffix. If it is not, fail.
17226 Otherwise, set inst.cond from the suffix we already looked up,
17227 and return the opcode structure.
17229 CM. Examine the tag field to make sure this is an instruction that
17230 should receive a conditional infix after the third character.
17231 If it is not, fail. Otherwise, undo the edits to the current
17232 line of input and proceed as for case CE. */
17234 static const struct asm_opcode
*
17235 opcode_lookup (char **str
)
17239 const struct asm_opcode
*opcode
;
17240 const struct asm_cond
*cond
;
17243 /* Scan up to the end of the mnemonic, which must end in white space,
17244 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17245 for (base
= end
= *str
; *end
!= '\0'; end
++)
17246 if (*end
== ' ' || *end
== '.')
17252 /* Handle a possible width suffix and/or Neon type suffix. */
17257 /* The .w and .n suffixes are only valid if the unified syntax is in
17259 if (unified_syntax
&& end
[1] == 'w')
17261 else if (unified_syntax
&& end
[1] == 'n')
17266 inst
.vectype
.elems
= 0;
17268 *str
= end
+ offset
;
17270 if (end
[offset
] == '.')
17272 /* See if we have a Neon type suffix (possible in either unified or
17273 non-unified ARM syntax mode). */
17274 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17277 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17283 /* Look for unaffixed or special-case affixed mnemonic. */
17284 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17289 if (opcode
->tag
< OT_odd_infix_0
)
17291 inst
.cond
= COND_ALWAYS
;
17295 if (warn_on_deprecated
&& unified_syntax
)
17296 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17297 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17298 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17301 inst
.cond
= cond
->value
;
17305 /* Cannot have a conditional suffix on a mnemonic of less than two
17307 if (end
- base
< 3)
17310 /* Look for suffixed mnemonic. */
17312 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17313 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17315 if (opcode
&& cond
)
17318 switch (opcode
->tag
)
17320 case OT_cinfix3_legacy
:
17321 /* Ignore conditional suffixes matched on infix only mnemonics. */
17325 case OT_cinfix3_deprecated
:
17326 case OT_odd_infix_unc
:
17327 if (!unified_syntax
)
17329 /* else fall through */
17333 case OT_csuf_or_in3
:
17334 inst
.cond
= cond
->value
;
17337 case OT_unconditional
:
17338 case OT_unconditionalF
:
17340 inst
.cond
= cond
->value
;
17343 /* Delayed diagnostic. */
17344 inst
.error
= BAD_COND
;
17345 inst
.cond
= COND_ALWAYS
;
17354 /* Cannot have a usual-position infix on a mnemonic of less than
17355 six characters (five would be a suffix). */
17356 if (end
- base
< 6)
17359 /* Look for infixed mnemonic in the usual position. */
17361 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17365 memcpy (save
, affix
, 2);
17366 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17367 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17369 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17370 memcpy (affix
, save
, 2);
17373 && (opcode
->tag
== OT_cinfix3
17374 || opcode
->tag
== OT_cinfix3_deprecated
17375 || opcode
->tag
== OT_csuf_or_in3
17376 || opcode
->tag
== OT_cinfix3_legacy
))
17379 if (warn_on_deprecated
&& unified_syntax
17380 && (opcode
->tag
== OT_cinfix3
17381 || opcode
->tag
== OT_cinfix3_deprecated
))
17382 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17384 inst
.cond
= cond
->value
;
17391 /* This function generates an initial IT instruction, leaving its block
17392 virtually open for the new instructions. Eventually,
17393 the mask will be updated by now_it_add_mask () each time
17394 a new instruction needs to be included in the IT block.
17395 Finally, the block is closed with close_automatic_it_block ().
17396 The block closure can be requested either from md_assemble (),
17397 a tencode (), or due to a label hook. */
17400 new_automatic_it_block (int cond
)
17402 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17403 now_it
.mask
= 0x18;
17405 now_it
.block_length
= 1;
17406 mapping_state (MAP_THUMB
);
17407 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17408 now_it
.warn_deprecated
= FALSE
;
17409 now_it
.insn_cond
= TRUE
;
17412 /* Close an automatic IT block.
17413 See comments in new_automatic_it_block (). */
17416 close_automatic_it_block (void)
17418 now_it
.mask
= 0x10;
17419 now_it
.block_length
= 0;
17422 /* Update the mask of the current automatically-generated IT
17423 instruction. See comments in new_automatic_it_block (). */
17426 now_it_add_mask (int cond
)
17428 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17429 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17430 | ((bitvalue) << (nbit)))
17431 const int resulting_bit
= (cond
& 1);
17433 now_it
.mask
&= 0xf;
17434 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17436 (5 - now_it
.block_length
));
17437 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17439 ((5 - now_it
.block_length
) - 1) );
17440 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17443 #undef SET_BIT_VALUE
17446 /* The IT blocks handling machinery is accessed through the these functions:
17447 it_fsm_pre_encode () from md_assemble ()
17448 set_it_insn_type () optional, from the tencode functions
17449 set_it_insn_type_last () ditto
17450 in_it_block () ditto
17451 it_fsm_post_encode () from md_assemble ()
17452 force_automatic_it_block_close () from label habdling functions
17455 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17456 initializing the IT insn type with a generic initial value depending
17457 on the inst.condition.
17458 2) During the tencode function, two things may happen:
17459 a) The tencode function overrides the IT insn type by
17460 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17461 b) The tencode function queries the IT block state by
17462 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17464 Both set_it_insn_type and in_it_block run the internal FSM state
17465 handling function (handle_it_state), because: a) setting the IT insn
17466 type may incur in an invalid state (exiting the function),
17467 and b) querying the state requires the FSM to be updated.
17468 Specifically we want to avoid creating an IT block for conditional
17469 branches, so it_fsm_pre_encode is actually a guess and we can't
17470 determine whether an IT block is required until the tencode () routine
17471 has decided what type of instruction this actually it.
17472 Because of this, if set_it_insn_type and in_it_block have to be used,
17473 set_it_insn_type has to be called first.
17475 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17476 determines the insn IT type depending on the inst.cond code.
17477 When a tencode () routine encodes an instruction that can be
17478 either outside an IT block, or, in the case of being inside, has to be
17479 the last one, set_it_insn_type_last () will determine the proper
17480 IT instruction type based on the inst.cond code. Otherwise,
17481 set_it_insn_type can be called for overriding that logic or
17482 for covering other cases.
17484 Calling handle_it_state () may not transition the IT block state to
17485 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17486 still queried. Instead, if the FSM determines that the state should
17487 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17488 after the tencode () function: that's what it_fsm_post_encode () does.
17490 Since in_it_block () calls the state handling function to get an
17491 updated state, an error may occur (due to invalid insns combination).
17492 In that case, inst.error is set.
17493 Therefore, inst.error has to be checked after the execution of
17494 the tencode () routine.
17496 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17497 any pending state change (if any) that didn't take place in
17498 handle_it_state () as explained above. */
17501 it_fsm_pre_encode (void)
17503 if (inst
.cond
!= COND_ALWAYS
)
17504 inst
.it_insn_type
= INSIDE_IT_INSN
;
17506 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17508 now_it
.state_handled
= 0;
17511 /* IT state FSM handling function. */
17514 handle_it_state (void)
17516 now_it
.state_handled
= 1;
17517 now_it
.insn_cond
= FALSE
;
17519 switch (now_it
.state
)
17521 case OUTSIDE_IT_BLOCK
:
17522 switch (inst
.it_insn_type
)
17524 case OUTSIDE_IT_INSN
:
17527 case INSIDE_IT_INSN
:
17528 case INSIDE_IT_LAST_INSN
:
17529 if (thumb_mode
== 0)
17532 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17533 as_tsktsk (_("Warning: conditional outside an IT block"\
17538 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17539 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17541 /* Automatically generate the IT instruction. */
17542 new_automatic_it_block (inst
.cond
);
17543 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17544 close_automatic_it_block ();
17548 inst
.error
= BAD_OUT_IT
;
17554 case IF_INSIDE_IT_LAST_INSN
:
17555 case NEUTRAL_IT_INSN
:
17559 now_it
.state
= MANUAL_IT_BLOCK
;
17560 now_it
.block_length
= 0;
17565 case AUTOMATIC_IT_BLOCK
:
17566 /* Three things may happen now:
17567 a) We should increment current it block size;
17568 b) We should close current it block (closing insn or 4 insns);
17569 c) We should close current it block and start a new one (due
17570 to incompatible conditions or
17571 4 insns-length block reached). */
17573 switch (inst
.it_insn_type
)
17575 case OUTSIDE_IT_INSN
:
17576 /* The closure of the block shall happen immediatelly,
17577 so any in_it_block () call reports the block as closed. */
17578 force_automatic_it_block_close ();
17581 case INSIDE_IT_INSN
:
17582 case INSIDE_IT_LAST_INSN
:
17583 case IF_INSIDE_IT_LAST_INSN
:
17584 now_it
.block_length
++;
17586 if (now_it
.block_length
> 4
17587 || !now_it_compatible (inst
.cond
))
17589 force_automatic_it_block_close ();
17590 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17591 new_automatic_it_block (inst
.cond
);
17595 now_it
.insn_cond
= TRUE
;
17596 now_it_add_mask (inst
.cond
);
17599 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17600 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17601 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17602 close_automatic_it_block ();
17605 case NEUTRAL_IT_INSN
:
17606 now_it
.block_length
++;
17607 now_it
.insn_cond
= TRUE
;
17609 if (now_it
.block_length
> 4)
17610 force_automatic_it_block_close ();
17612 now_it_add_mask (now_it
.cc
& 1);
17616 close_automatic_it_block ();
17617 now_it
.state
= MANUAL_IT_BLOCK
;
17622 case MANUAL_IT_BLOCK
:
17624 /* Check conditional suffixes. */
17625 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17628 now_it
.mask
&= 0x1f;
17629 is_last
= (now_it
.mask
== 0x10);
17630 now_it
.insn_cond
= TRUE
;
17632 switch (inst
.it_insn_type
)
17634 case OUTSIDE_IT_INSN
:
17635 inst
.error
= BAD_NOT_IT
;
17638 case INSIDE_IT_INSN
:
17639 if (cond
!= inst
.cond
)
17641 inst
.error
= BAD_IT_COND
;
17646 case INSIDE_IT_LAST_INSN
:
17647 case IF_INSIDE_IT_LAST_INSN
:
17648 if (cond
!= inst
.cond
)
17650 inst
.error
= BAD_IT_COND
;
17655 inst
.error
= BAD_BRANCH
;
17660 case NEUTRAL_IT_INSN
:
17661 /* The BKPT instruction is unconditional even in an IT block. */
17665 inst
.error
= BAD_IT_IT
;
17675 struct depr_insn_mask
17677 unsigned long pattern
;
17678 unsigned long mask
;
17679 const char* description
;
17682 /* List of 16-bit instruction patterns deprecated in an IT block in
17684 static const struct depr_insn_mask depr_it_insns
[] = {
17685 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17686 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17687 { 0xa000, 0xb800, N_("ADR") },
17688 { 0x4800, 0xf800, N_("Literal loads") },
17689 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17690 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17691 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17692 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17693 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17698 it_fsm_post_encode (void)
17702 if (!now_it
.state_handled
)
17703 handle_it_state ();
17705 if (now_it
.insn_cond
17706 && !now_it
.warn_deprecated
17707 && warn_on_deprecated
17708 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17710 if (inst
.instruction
>= 0x10000)
17712 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17713 "deprecated in ARMv8"));
17714 now_it
.warn_deprecated
= TRUE
;
17718 const struct depr_insn_mask
*p
= depr_it_insns
;
17720 while (p
->mask
!= 0)
17722 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17724 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17725 "of the following class are deprecated in ARMv8: "
17726 "%s"), p
->description
);
17727 now_it
.warn_deprecated
= TRUE
;
17735 if (now_it
.block_length
> 1)
17737 as_tsktsk (_("IT blocks containing more than one conditional "
17738 "instruction are deprecated in ARMv8"));
17739 now_it
.warn_deprecated
= TRUE
;
17743 is_last
= (now_it
.mask
== 0x10);
17746 now_it
.state
= OUTSIDE_IT_BLOCK
;
17752 force_automatic_it_block_close (void)
17754 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17756 close_automatic_it_block ();
17757 now_it
.state
= OUTSIDE_IT_BLOCK
;
17765 if (!now_it
.state_handled
)
17766 handle_it_state ();
17768 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17772 md_assemble (char *str
)
17775 const struct asm_opcode
* opcode
;
17777 /* Align the previous label if needed. */
17778 if (last_label_seen
!= NULL
)
17780 symbol_set_frag (last_label_seen
, frag_now
);
17781 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17782 S_SET_SEGMENT (last_label_seen
, now_seg
);
17785 memset (&inst
, '\0', sizeof (inst
));
17786 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17788 opcode
= opcode_lookup (&p
);
17791 /* It wasn't an instruction, but it might be a register alias of
17792 the form alias .req reg, or a Neon .dn/.qn directive. */
17793 if (! create_register_alias (str
, p
)
17794 && ! create_neon_reg_alias (str
, p
))
17795 as_bad (_("bad instruction `%s'"), str
);
17800 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17801 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17803 /* The value which unconditional instructions should have in place of the
17804 condition field. */
17805 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17809 arm_feature_set variant
;
17811 variant
= cpu_variant
;
17812 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17813 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17814 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17815 /* Check that this instruction is supported for this CPU. */
17816 if (!opcode
->tvariant
17817 || (thumb_mode
== 1
17818 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17820 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
17823 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17824 && opcode
->tencode
!= do_t_branch
)
17826 as_bad (_("Thumb does not support conditional execution"));
17830 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17832 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17833 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17834 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17836 /* Two things are addressed here.
17837 1) Implicit require narrow instructions on Thumb-1.
17838 This avoids relaxation accidentally introducing Thumb-2
17840 2) Reject wide instructions in non Thumb-2 cores. */
17841 if (inst
.size_req
== 0)
17843 else if (inst
.size_req
== 4)
17845 as_bad (_("selected processor does not support `%s' in Thumb-2 mode"), str
);
17851 inst
.instruction
= opcode
->tvalue
;
17853 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17855 /* Prepare the it_insn_type for those encodings that don't set
17857 it_fsm_pre_encode ();
17859 opcode
->tencode ();
17861 it_fsm_post_encode ();
17864 if (!(inst
.error
|| inst
.relax
))
17866 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17867 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17868 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17870 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17875 /* Something has gone badly wrong if we try to relax a fixed size
17877 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17879 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17880 *opcode
->tvariant
);
17881 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17882 set those bits when Thumb-2 32-bit instructions are seen. ie.
17883 anything other than bl/blx and v6-M instructions.
17884 The impact of relaxable instructions will be considered later after we
17885 finish all relaxation. */
17886 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17887 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17888 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17889 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17892 check_neon_suffixes
;
17896 mapping_state (MAP_THUMB
);
17899 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17903 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17904 is_bx
= (opcode
->aencode
== do_bx
);
17906 /* Check that this instruction is supported for this CPU. */
17907 if (!(is_bx
&& fix_v4bx
)
17908 && !(opcode
->avariant
&&
17909 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17911 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
17916 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17920 inst
.instruction
= opcode
->avalue
;
17921 if (opcode
->tag
== OT_unconditionalF
)
17922 inst
.instruction
|= 0xFU
<< 28;
17924 inst
.instruction
|= inst
.cond
<< 28;
17925 inst
.size
= INSN_SIZE
;
17926 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17928 it_fsm_pre_encode ();
17929 opcode
->aencode ();
17930 it_fsm_post_encode ();
17932 /* Arm mode bx is marked as both v4T and v5 because it's still required
17933 on a hypothetical non-thumb v5 core. */
17935 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17937 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17938 *opcode
->avariant
);
17940 check_neon_suffixes
;
17944 mapping_state (MAP_ARM
);
17949 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17957 check_it_blocks_finished (void)
17962 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17963 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17964 == MANUAL_IT_BLOCK
)
17966 as_warn (_("section '%s' finished with an open IT block."),
17970 if (now_it
.state
== MANUAL_IT_BLOCK
)
17971 as_warn (_("file finished with an open IT block."));
17975 /* Various frobbings of labels and their addresses. */
17978 arm_start_line_hook (void)
17980 last_label_seen
= NULL
;
17984 arm_frob_label (symbolS
* sym
)
17986 last_label_seen
= sym
;
17988 ARM_SET_THUMB (sym
, thumb_mode
);
17990 #if defined OBJ_COFF || defined OBJ_ELF
17991 ARM_SET_INTERWORK (sym
, support_interwork
);
17994 force_automatic_it_block_close ();
17996 /* Note - do not allow local symbols (.Lxxx) to be labelled
17997 as Thumb functions. This is because these labels, whilst
17998 they exist inside Thumb code, are not the entry points for
17999 possible ARM->Thumb calls. Also, these labels can be used
18000 as part of a computed goto or switch statement. eg gcc
18001 can generate code that looks like this:
18003 ldr r2, [pc, .Laaa]
18013 The first instruction loads the address of the jump table.
18014 The second instruction converts a table index into a byte offset.
18015 The third instruction gets the jump address out of the table.
18016 The fourth instruction performs the jump.
18018 If the address stored at .Laaa is that of a symbol which has the
18019 Thumb_Func bit set, then the linker will arrange for this address
18020 to have the bottom bit set, which in turn would mean that the
18021 address computation performed by the third instruction would end
18022 up with the bottom bit set. Since the ARM is capable of unaligned
18023 word loads, the instruction would then load the incorrect address
18024 out of the jump table, and chaos would ensue. */
18025 if (label_is_thumb_function_name
18026 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18027 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18029 /* When the address of a Thumb function is taken the bottom
18030 bit of that address should be set. This will allow
18031 interworking between Arm and Thumb functions to work
18034 THUMB_SET_FUNC (sym
, 1);
18036 label_is_thumb_function_name
= FALSE
;
18039 dwarf2_emit_label (sym
);
18043 arm_data_in_code (void)
18045 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18047 *input_line_pointer
= '/';
18048 input_line_pointer
+= 5;
18049 *input_line_pointer
= 0;
18057 arm_canonicalize_symbol_name (char * name
)
18061 if (thumb_mode
&& (len
= strlen (name
)) > 5
18062 && streq (name
+ len
- 5, "/data"))
18063 *(name
+ len
- 5) = 0;
18068 /* Table of all register names defined by default. The user can
18069 define additional names with .req. Note that all register names
18070 should appear in both upper and lowercase variants. Some registers
18071 also have mixed-case names. */
18073 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18074 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18075 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18076 #define REGSET(p,t) \
18077 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18078 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18079 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18080 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18081 #define REGSETH(p,t) \
18082 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18083 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18084 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18085 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18086 #define REGSET2(p,t) \
18087 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18088 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18089 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18090 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18091 #define SPLRBANK(base,bank,t) \
18092 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18093 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18094 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18095 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18096 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18097 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18099 static const struct reg_entry reg_names
[] =
18101 /* ARM integer registers. */
18102 REGSET(r
, RN
), REGSET(R
, RN
),
18104 /* ATPCS synonyms. */
18105 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18106 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18107 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18109 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18110 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18111 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18113 /* Well-known aliases. */
18114 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18115 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18117 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18118 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18120 /* Coprocessor numbers. */
18121 REGSET(p
, CP
), REGSET(P
, CP
),
18123 /* Coprocessor register numbers. The "cr" variants are for backward
18125 REGSET(c
, CN
), REGSET(C
, CN
),
18126 REGSET(cr
, CN
), REGSET(CR
, CN
),
18128 /* ARM banked registers. */
18129 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18130 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18131 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18132 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18133 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18134 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18135 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18137 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18138 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18139 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18140 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18141 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18142 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18143 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18144 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18146 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18147 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18148 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18149 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18150 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18151 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18152 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18153 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18154 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18156 /* FPA registers. */
18157 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18158 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18160 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18161 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18163 /* VFP SP registers. */
18164 REGSET(s
,VFS
), REGSET(S
,VFS
),
18165 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18167 /* VFP DP Registers. */
18168 REGSET(d
,VFD
), REGSET(D
,VFD
),
18169 /* Extra Neon DP registers. */
18170 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18172 /* Neon QP registers. */
18173 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18175 /* VFP control registers. */
18176 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18177 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18178 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18179 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18180 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18181 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18183 /* Maverick DSP coprocessor registers. */
18184 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18185 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18187 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18188 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18189 REGDEF(dspsc
,0,DSPSC
),
18191 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18192 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18193 REGDEF(DSPSC
,0,DSPSC
),
18195 /* iWMMXt data registers - p0, c0-15. */
18196 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18198 /* iWMMXt control registers - p1, c0-3. */
18199 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18200 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18201 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18202 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18204 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18205 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18206 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18207 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18208 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18210 /* XScale accumulator registers. */
18211 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18217 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18218 within psr_required_here. */
18219 static const struct asm_psr psrs
[] =
18221 /* Backward compatibility notation. Note that "all" is no longer
18222 truly all possible PSR bits. */
18223 {"all", PSR_c
| PSR_f
},
18227 /* Individual flags. */
18233 /* Combinations of flags. */
18234 {"fs", PSR_f
| PSR_s
},
18235 {"fx", PSR_f
| PSR_x
},
18236 {"fc", PSR_f
| PSR_c
},
18237 {"sf", PSR_s
| PSR_f
},
18238 {"sx", PSR_s
| PSR_x
},
18239 {"sc", PSR_s
| PSR_c
},
18240 {"xf", PSR_x
| PSR_f
},
18241 {"xs", PSR_x
| PSR_s
},
18242 {"xc", PSR_x
| PSR_c
},
18243 {"cf", PSR_c
| PSR_f
},
18244 {"cs", PSR_c
| PSR_s
},
18245 {"cx", PSR_c
| PSR_x
},
18246 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18247 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18248 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18249 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18250 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18251 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18252 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18253 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18254 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18255 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18256 {"scf", PSR_s
| PSR_c
| PSR_f
},
18257 {"scx", PSR_s
| PSR_c
| PSR_x
},
18258 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18259 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18260 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18261 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18262 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18263 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18264 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18265 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18266 {"csf", PSR_c
| PSR_s
| PSR_f
},
18267 {"csx", PSR_c
| PSR_s
| PSR_x
},
18268 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18269 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18270 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18271 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18272 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18273 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18274 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18275 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18276 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18277 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18278 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18279 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18280 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18281 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18282 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18283 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18284 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18285 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18286 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18287 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18288 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18289 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18290 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18291 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18292 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18293 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18296 /* Table of V7M psr names. */
18297 static const struct asm_psr v7m_psrs
[] =
18299 {"apsr", 0 }, {"APSR", 0 },
18300 {"iapsr", 1 }, {"IAPSR", 1 },
18301 {"eapsr", 2 }, {"EAPSR", 2 },
18302 {"psr", 3 }, {"PSR", 3 },
18303 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18304 {"ipsr", 5 }, {"IPSR", 5 },
18305 {"epsr", 6 }, {"EPSR", 6 },
18306 {"iepsr", 7 }, {"IEPSR", 7 },
18307 {"msp", 8 }, {"MSP", 8 },
18308 {"psp", 9 }, {"PSP", 9 },
18309 {"primask", 16}, {"PRIMASK", 16},
18310 {"basepri", 17}, {"BASEPRI", 17},
18311 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18312 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18313 {"faultmask", 19}, {"FAULTMASK", 19},
18314 {"control", 20}, {"CONTROL", 20}
18317 /* Table of all shift-in-operand names. */
18318 static const struct asm_shift_name shift_names
[] =
18320 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18321 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18322 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18323 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18324 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18325 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18328 /* Table of all explicit relocation names. */
18330 static struct reloc_entry reloc_names
[] =
18332 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18333 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18334 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18335 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18336 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18337 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18338 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18339 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18340 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18341 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18342 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18343 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18344 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18345 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18346 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18347 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18348 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18349 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18353 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18354 static const struct asm_cond conds
[] =
18358 {"cs", 0x2}, {"hs", 0x2},
18359 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18373 #define UL_BARRIER(L,U,CODE,FEAT) \
18374 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18375 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18377 static struct asm_barrier_opt barrier_opt_names
[] =
18379 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18380 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18381 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18382 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18383 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18384 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18385 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18386 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18387 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18388 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18389 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18390 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18391 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18392 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18393 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18394 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18399 /* Table of ARM-format instructions. */
18401 /* Macros for gluing together operand strings. N.B. In all cases
18402 other than OPS0, the trailing OP_stop comes from default
18403 zero-initialization of the unspecified elements of the array. */
18404 #define OPS0() { OP_stop, }
18405 #define OPS1(a) { OP_##a, }
18406 #define OPS2(a,b) { OP_##a,OP_##b, }
18407 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18408 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18409 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18410 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18412 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18413 This is useful when mixing operands for ARM and THUMB, i.e. using the
18414 MIX_ARM_THUMB_OPERANDS macro.
18415 In order to use these macros, prefix the number of operands with _
18417 #define OPS_1(a) { a, }
18418 #define OPS_2(a,b) { a,b, }
18419 #define OPS_3(a,b,c) { a,b,c, }
18420 #define OPS_4(a,b,c,d) { a,b,c,d, }
18421 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18422 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18424 /* These macros abstract out the exact format of the mnemonic table and
18425 save some repeated characters. */
18427 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18428 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18429 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18430 THUMB_VARIANT, do_##ae, do_##te }
18432 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18433 a T_MNEM_xyz enumerator. */
18434 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18435 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18436 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18437 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18439 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18440 infix after the third character. */
18441 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18442 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18443 THUMB_VARIANT, do_##ae, do_##te }
18444 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18445 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18446 THUMB_VARIANT, do_##ae, do_##te }
18447 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18448 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18449 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18450 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18451 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18452 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18453 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18454 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18456 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18457 field is still 0xE. Many of the Thumb variants can be executed
18458 conditionally, so this is checked separately. */
18459 #define TUE(mnem, op, top, nops, ops, ae, te) \
18460 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18461 THUMB_VARIANT, do_##ae, do_##te }
18463 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18464 Used by mnemonics that have very minimal differences in the encoding for
18465 ARM and Thumb variants and can be handled in a common function. */
18466 #define TUEc(mnem, op, top, nops, ops, en) \
18467 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18468 THUMB_VARIANT, do_##en, do_##en }
18470 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18471 condition code field. */
18472 #define TUF(mnem, op, top, nops, ops, ae, te) \
18473 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18474 THUMB_VARIANT, do_##ae, do_##te }
18476 /* ARM-only variants of all the above. */
18477 #define CE(mnem, op, nops, ops, ae) \
18478 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18480 #define C3(mnem, op, nops, ops, ae) \
18481 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18483 /* Legacy mnemonics that always have conditional infix after the third
18485 #define CL(mnem, op, nops, ops, ae) \
18486 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18487 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18489 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18490 #define cCE(mnem, op, nops, ops, ae) \
18491 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18493 /* Legacy coprocessor instructions where conditional infix and conditional
18494 suffix are ambiguous. For consistency this includes all FPA instructions,
18495 not just the potentially ambiguous ones. */
18496 #define cCL(mnem, op, nops, ops, ae) \
18497 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18498 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18500 /* Coprocessor, takes either a suffix or a position-3 infix
18501 (for an FPA corner case). */
18502 #define C3E(mnem, op, nops, ops, ae) \
18503 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18504 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18506 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18507 { m1 #m2 m3, OPS##nops ops, \
18508 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18509 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18511 #define CM(m1, m2, op, nops, ops, ae) \
18512 xCM_ (m1, , m2, op, nops, ops, ae), \
18513 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18514 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18515 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18516 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18517 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18518 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18519 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18520 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18521 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18522 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18523 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18524 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18525 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18526 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18527 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18528 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18529 xCM_ (m1, le, m2, op, nops, ops, ae), \
18530 xCM_ (m1, al, m2, op, nops, ops, ae)
18532 #define UE(mnem, op, nops, ops, ae) \
18533 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18535 #define UF(mnem, op, nops, ops, ae) \
18536 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18538 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18539 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18540 use the same encoding function for each. */
18541 #define NUF(mnem, op, nops, ops, enc) \
18542 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18543 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18545 /* Neon data processing, version which indirects through neon_enc_tab for
18546 the various overloaded versions of opcodes. */
18547 #define nUF(mnem, op, nops, ops, enc) \
18548 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18549 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18551 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18553 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18554 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18555 THUMB_VARIANT, do_##enc, do_##enc }
18557 #define NCE(mnem, op, nops, ops, enc) \
18558 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18560 #define NCEF(mnem, op, nops, ops, enc) \
18561 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18563 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18564 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18565 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18566 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18568 #define nCE(mnem, op, nops, ops, enc) \
18569 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18571 #define nCEF(mnem, op, nops, ops, enc) \
18572 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18576 static const struct asm_opcode insns
[] =
18578 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18579 #define THUMB_VARIANT & arm_ext_v4t
18580 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18581 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18582 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18583 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18584 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18585 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18586 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18587 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18588 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18589 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18590 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18591 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18592 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18593 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18594 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18595 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18597 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18598 for setting PSR flag bits. They are obsolete in V6 and do not
18599 have Thumb equivalents. */
18600 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18601 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18602 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18603 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18604 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18605 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18606 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18607 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18608 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18610 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18611 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18612 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18613 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18615 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18616 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18617 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18619 OP_ADDRGLDR
),ldst
, t_ldst
),
18620 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18622 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18623 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18624 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18625 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18626 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18627 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18629 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18630 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18631 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18632 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18635 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18636 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18637 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18638 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18640 /* Thumb-compatibility pseudo ops. */
18641 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18642 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18643 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18644 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18645 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18646 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18647 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18648 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18649 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18650 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18651 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18652 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18654 /* These may simplify to neg. */
18655 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18656 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18658 #undef THUMB_VARIANT
18659 #define THUMB_VARIANT & arm_ext_v6
18661 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18663 /* V1 instructions with no Thumb analogue prior to V6T2. */
18664 #undef THUMB_VARIANT
18665 #define THUMB_VARIANT & arm_ext_v6t2
18667 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18668 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18669 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18671 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18672 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18673 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18674 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18676 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18677 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18679 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18680 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18682 /* V1 instructions with no Thumb analogue at all. */
18683 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18684 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18686 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18687 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18688 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18689 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18690 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18691 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18692 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18693 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18696 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18697 #undef THUMB_VARIANT
18698 #define THUMB_VARIANT & arm_ext_v4t
18700 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18701 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18703 #undef THUMB_VARIANT
18704 #define THUMB_VARIANT & arm_ext_v6t2
18706 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18707 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18709 /* Generic coprocessor instructions. */
18710 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18711 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18712 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18713 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18714 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18715 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18716 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18719 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18721 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18722 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18725 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18726 #undef THUMB_VARIANT
18727 #define THUMB_VARIANT & arm_ext_msr
18729 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18730 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18733 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18734 #undef THUMB_VARIANT
18735 #define THUMB_VARIANT & arm_ext_v6t2
18737 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18738 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18739 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18740 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18741 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18742 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18743 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18744 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18747 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18748 #undef THUMB_VARIANT
18749 #define THUMB_VARIANT & arm_ext_v4t
18751 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18752 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18753 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18754 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18755 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18756 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18759 #define ARM_VARIANT & arm_ext_v4t_5
18761 /* ARM Architecture 4T. */
18762 /* Note: bx (and blx) are required on V5, even if the processor does
18763 not support Thumb. */
18764 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18767 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18768 #undef THUMB_VARIANT
18769 #define THUMB_VARIANT & arm_ext_v5t
18771 /* Note: blx has 2 variants; the .value coded here is for
18772 BLX(2). Only this variant has conditional execution. */
18773 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18774 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18776 #undef THUMB_VARIANT
18777 #define THUMB_VARIANT & arm_ext_v6t2
18779 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18780 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18781 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18782 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18783 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18784 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18785 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18786 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18789 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18790 #undef THUMB_VARIANT
18791 #define THUMB_VARIANT & arm_ext_v5exp
18793 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18794 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18795 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18796 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18798 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18799 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18801 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18802 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18803 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18804 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18806 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18807 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18808 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18809 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18811 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18812 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18814 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18815 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18816 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18817 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18820 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18821 #undef THUMB_VARIANT
18822 #define THUMB_VARIANT & arm_ext_v6t2
18824 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18825 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18827 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18828 ADDRGLDRS
), ldrd
, t_ldstd
),
18830 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18831 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18834 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18836 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18839 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18840 #undef THUMB_VARIANT
18841 #define THUMB_VARIANT & arm_ext_v6
18843 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18844 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18845 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18846 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18847 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18848 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18849 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18850 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18851 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18852 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18854 #undef THUMB_VARIANT
18855 #define THUMB_VARIANT & arm_ext_v6t2
18857 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18858 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18860 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18861 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18863 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18864 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18866 /* ARM V6 not included in V7M. */
18867 #undef THUMB_VARIANT
18868 #define THUMB_VARIANT & arm_ext_v6_notm
18869 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18870 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18871 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18872 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18873 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18874 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18875 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18876 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18877 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18878 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18879 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18880 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18881 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18882 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18883 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18884 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18885 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18886 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18887 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18889 /* ARM V6 not included in V7M (eg. integer SIMD). */
18890 #undef THUMB_VARIANT
18891 #define THUMB_VARIANT & arm_ext_v6_dsp
18892 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18893 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18894 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18895 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18896 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18897 /* Old name for QASX. */
18898 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18899 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18900 /* Old name for QSAX. */
18901 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18902 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18903 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18904 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18905 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18906 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18907 /* Old name for SASX. */
18908 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18909 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18910 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18911 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18912 /* Old name for SHASX. */
18913 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18914 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18915 /* Old name for SHSAX. */
18916 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18917 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18918 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18919 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18920 /* Old name for SSAX. */
18921 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18922 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18923 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18924 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18925 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18926 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18927 /* Old name for UASX. */
18928 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18929 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18930 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18931 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18932 /* Old name for UHASX. */
18933 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18934 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18935 /* Old name for UHSAX. */
18936 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18937 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18938 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18939 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18940 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18941 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18942 /* Old name for UQASX. */
18943 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18944 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18945 /* Old name for UQSAX. */
18946 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18947 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18948 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18949 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18950 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18951 /* Old name for USAX. */
18952 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18953 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18954 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18955 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18956 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18957 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18958 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18959 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18960 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18961 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18962 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18963 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18964 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18965 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18966 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18967 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18968 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18969 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18970 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18971 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18972 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18973 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18974 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18975 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18976 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18977 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18978 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18979 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18980 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18981 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18982 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18983 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18984 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18985 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18988 #define ARM_VARIANT & arm_ext_v6k
18989 #undef THUMB_VARIANT
18990 #define THUMB_VARIANT & arm_ext_v6k
18992 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
18993 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
18994 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
18995 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
18997 #undef THUMB_VARIANT
18998 #define THUMB_VARIANT & arm_ext_v6_notm
18999 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19001 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19002 RRnpcb
), strexd
, t_strexd
),
19004 #undef THUMB_VARIANT
19005 #define THUMB_VARIANT & arm_ext_v6t2
19006 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19008 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19010 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19012 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19014 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19017 #define ARM_VARIANT & arm_ext_sec
19018 #undef THUMB_VARIANT
19019 #define THUMB_VARIANT & arm_ext_sec
19021 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19024 #define ARM_VARIANT & arm_ext_virt
19025 #undef THUMB_VARIANT
19026 #define THUMB_VARIANT & arm_ext_virt
19028 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19029 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19032 #define ARM_VARIANT & arm_ext_pan
19033 #undef THUMB_VARIANT
19034 #define THUMB_VARIANT & arm_ext_pan
19036 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19039 #define ARM_VARIANT & arm_ext_v6t2
19040 #undef THUMB_VARIANT
19041 #define THUMB_VARIANT & arm_ext_v6t2
19043 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19044 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19045 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19046 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19048 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19049 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19050 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19051 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19053 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19054 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19055 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19056 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19058 /* Thumb-only instructions. */
19060 #define ARM_VARIANT NULL
19061 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19062 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19064 /* ARM does not really have an IT instruction, so always allow it.
19065 The opcode is copied from Thumb in order to allow warnings in
19066 -mimplicit-it=[never | arm] modes. */
19068 #define ARM_VARIANT & arm_ext_v1
19070 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19071 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19072 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19073 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19074 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19075 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19076 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19077 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19078 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19079 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19080 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19081 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19082 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19083 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19084 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19085 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19086 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19087 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19089 /* Thumb2 only instructions. */
19091 #define ARM_VARIANT NULL
19093 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19094 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19095 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19096 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19097 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19098 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19100 /* Hardware division instructions. */
19102 #define ARM_VARIANT & arm_ext_adiv
19103 #undef THUMB_VARIANT
19104 #define THUMB_VARIANT & arm_ext_div
19106 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19107 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19109 /* ARM V6M/V7 instructions. */
19111 #define ARM_VARIANT & arm_ext_barrier
19112 #undef THUMB_VARIANT
19113 #define THUMB_VARIANT & arm_ext_barrier
19115 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19116 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19117 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19119 /* ARM V7 instructions. */
19121 #define ARM_VARIANT & arm_ext_v7
19122 #undef THUMB_VARIANT
19123 #define THUMB_VARIANT & arm_ext_v7
19125 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19126 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19129 #define ARM_VARIANT & arm_ext_mp
19130 #undef THUMB_VARIANT
19131 #define THUMB_VARIANT & arm_ext_mp
19133 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19135 /* AArchv8 instructions. */
19137 #define ARM_VARIANT & arm_ext_v8
19138 #undef THUMB_VARIANT
19139 #define THUMB_VARIANT & arm_ext_v8
19141 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19142 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19143 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19144 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19146 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19147 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19148 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19150 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19152 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19154 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19156 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19157 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19158 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19159 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19160 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19161 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19163 /* ARMv8 T32 only. */
19165 #define ARM_VARIANT NULL
19166 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19167 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19168 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19170 /* FP for ARMv8. */
19172 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19173 #undef THUMB_VARIANT
19174 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19176 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19177 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19178 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19179 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19180 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19181 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19182 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19183 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19184 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19185 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19186 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19187 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19188 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19189 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19190 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19191 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19192 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19194 /* Crypto v1 extensions. */
19196 #define ARM_VARIANT & fpu_crypto_ext_armv8
19197 #undef THUMB_VARIANT
19198 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19200 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19201 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19202 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19203 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19204 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19205 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19206 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19207 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19208 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19209 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19210 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19211 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19212 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19213 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19216 #define ARM_VARIANT & crc_ext_armv8
19217 #undef THUMB_VARIANT
19218 #define THUMB_VARIANT & crc_ext_armv8
19219 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19220 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19221 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19222 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19223 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19224 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19227 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19228 #undef THUMB_VARIANT
19229 #define THUMB_VARIANT NULL
19231 cCE("wfs", e200110
, 1, (RR
), rd
),
19232 cCE("rfs", e300110
, 1, (RR
), rd
),
19233 cCE("wfc", e400110
, 1, (RR
), rd
),
19234 cCE("rfc", e500110
, 1, (RR
), rd
),
19236 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19237 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19238 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19239 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19241 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19242 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19243 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19244 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19246 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19247 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19248 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19249 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19250 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19251 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19252 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19253 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19254 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19255 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19256 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19257 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19259 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19260 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19261 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19262 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19263 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19264 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19265 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19266 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19267 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19268 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19269 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19270 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19272 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19273 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19274 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19275 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19276 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19277 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19278 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19279 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19280 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19281 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19282 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19283 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19285 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19286 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19287 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19288 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19289 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19290 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19291 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19292 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19293 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19294 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19295 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19296 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19298 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19299 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19300 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19301 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19302 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19303 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19304 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19305 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19306 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19307 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19308 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19309 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19311 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19312 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19313 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19314 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19315 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19316 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19317 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19318 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19319 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19320 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19321 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19322 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19324 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19325 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19326 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19327 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19328 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19329 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19330 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19331 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19332 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19333 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19334 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19335 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19337 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19338 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19339 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19340 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19341 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19342 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19343 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19344 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19345 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19346 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19347 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19348 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19350 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19351 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19352 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19353 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19354 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19355 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19356 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19357 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19358 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19359 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19360 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19361 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19363 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19364 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19365 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19366 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19367 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19368 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19369 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19370 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19371 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19372 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19373 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19374 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19376 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19377 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19378 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19379 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19380 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19381 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19382 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19383 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19384 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19385 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19386 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19387 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19389 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19390 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19391 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19392 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19393 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19394 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19395 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19396 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19397 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19398 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19399 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19400 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19402 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19403 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19404 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19405 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19406 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19407 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19408 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19409 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19410 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19411 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19412 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19413 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19415 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19416 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19417 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19418 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19419 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19420 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19421 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19422 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19423 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19424 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19425 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19426 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19428 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19429 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19430 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19431 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19432 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19433 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19434 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19435 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19436 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19437 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19438 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19439 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19441 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19442 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19443 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19444 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19445 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19446 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19447 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19448 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19449 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19450 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19451 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19452 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19454 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19455 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19456 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19457 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19458 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19459 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19460 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19461 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19462 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19463 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19464 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19465 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19467 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19468 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19469 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19470 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19471 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19472 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19473 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19474 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19475 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19476 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19477 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19478 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19480 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19481 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19482 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19483 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19484 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19485 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19486 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19487 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19488 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19489 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19490 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19491 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19493 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19494 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19495 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19496 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19497 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19498 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19499 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19500 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19501 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19502 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19503 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19504 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19506 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19507 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19508 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19509 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19510 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19511 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19512 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19513 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19514 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19515 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19516 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19517 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19519 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19520 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19521 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19522 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19523 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19524 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19525 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19526 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19527 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19528 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19529 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19530 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19532 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19533 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19534 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19535 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19536 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19537 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19538 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19539 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19540 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19541 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19542 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19543 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19545 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19546 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19547 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19548 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19549 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19550 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19551 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19552 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19553 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19554 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19555 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19556 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19558 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19559 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19560 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19561 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19562 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19563 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19564 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19565 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19566 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19567 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19568 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19569 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19571 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19572 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19573 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19574 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19575 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19576 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19577 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19578 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19579 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19580 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19581 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19582 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19584 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19585 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19586 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19587 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19588 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19589 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19590 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19591 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19592 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19593 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19594 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19595 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19597 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19598 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19599 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19600 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19601 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19602 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19603 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19604 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19605 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19606 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19607 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19608 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19610 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19611 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19612 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19613 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19614 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19615 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19616 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19617 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19618 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19619 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19620 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19621 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19623 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19624 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19625 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19626 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19628 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19629 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19630 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19631 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19632 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19633 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19634 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19635 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19636 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19637 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19638 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19639 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19641 /* The implementation of the FIX instruction is broken on some
19642 assemblers, in that it accepts a precision specifier as well as a
19643 rounding specifier, despite the fact that this is meaningless.
19644 To be more compatible, we accept it as well, though of course it
19645 does not set any bits. */
19646 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19647 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19648 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19649 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19650 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19651 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19652 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19653 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19654 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19655 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19656 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19657 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19658 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19660 /* Instructions that were new with the real FPA, call them V2. */
19662 #define ARM_VARIANT & fpu_fpa_ext_v2
19664 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19665 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19666 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19667 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19668 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19669 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19672 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19674 /* Moves and type conversions. */
19675 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19676 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19677 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19678 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19679 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19680 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19681 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19682 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19683 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19684 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19685 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19686 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19687 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19688 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19690 /* Memory operations. */
19691 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19692 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19693 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19694 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19695 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19696 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19697 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19698 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19699 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19700 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19701 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19702 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19703 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19704 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19705 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19706 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19707 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19708 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19710 /* Monadic operations. */
19711 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19712 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19713 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19715 /* Dyadic operations. */
19716 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19717 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19718 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19719 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19720 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19721 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19722 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19723 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19724 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19727 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19728 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19729 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19730 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19732 /* Double precision load/store are still present on single precision
19733 implementations. */
19734 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19735 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19736 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19737 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19738 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19739 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19740 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19741 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19742 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19743 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19746 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19748 /* Moves and type conversions. */
19749 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19750 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19751 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19752 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19753 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19754 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19755 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19756 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19757 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19758 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19759 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19760 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19761 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19763 /* Monadic operations. */
19764 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19765 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19766 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19768 /* Dyadic operations. */
19769 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19770 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19771 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19772 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19773 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19774 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19775 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19776 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19777 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19780 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19781 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19782 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19783 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19786 #define ARM_VARIANT & fpu_vfp_ext_v2
19788 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19789 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19790 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19791 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19793 /* Instructions which may belong to either the Neon or VFP instruction sets.
19794 Individual encoder functions perform additional architecture checks. */
19796 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19797 #undef THUMB_VARIANT
19798 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19800 /* These mnemonics are unique to VFP. */
19801 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19802 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19803 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19804 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19805 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19806 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19807 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
19808 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19809 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19810 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19812 /* Mnemonics shared by Neon and VFP. */
19813 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19814 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19815 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19817 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19818 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19820 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19821 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19823 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19824 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19825 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19826 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19827 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19828 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19829 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19830 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19832 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19833 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19834 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19835 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19838 /* NOTE: All VMOV encoding is special-cased! */
19839 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19840 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19842 #undef THUMB_VARIANT
19843 #define THUMB_VARIANT & fpu_neon_ext_v1
19845 #define ARM_VARIANT & fpu_neon_ext_v1
19847 /* Data processing with three registers of the same length. */
19848 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19849 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19850 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19851 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19852 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19853 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19854 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19855 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19856 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19857 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19858 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19859 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19860 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19861 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19862 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19863 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19864 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19865 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19866 /* If not immediate, fall back to neon_dyadic_i64_su.
19867 shl_imm should accept I8 I16 I32 I64,
19868 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19869 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19870 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19871 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19872 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19873 /* Logic ops, types optional & ignored. */
19874 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19875 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19876 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19877 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19878 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19879 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19880 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19881 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19882 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19883 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19884 /* Bitfield ops, untyped. */
19885 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19886 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19887 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19888 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19889 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19890 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19891 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19892 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19893 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19894 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19895 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19896 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19897 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19898 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19899 back to neon_dyadic_if_su. */
19900 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19901 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19902 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19903 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19904 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19905 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19906 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19907 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19908 /* Comparison. Type I8 I16 I32 F32. */
19909 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19910 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19911 /* As above, D registers only. */
19912 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19913 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19914 /* Int and float variants, signedness unimportant. */
19915 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19916 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19917 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19918 /* Add/sub take types I8 I16 I32 I64 F32. */
19919 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19920 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19921 /* vtst takes sizes 8, 16, 32. */
19922 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19923 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19924 /* VMUL takes I8 I16 I32 F32 P8. */
19925 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19926 /* VQD{R}MULH takes S16 S32. */
19927 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19928 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19929 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19930 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19931 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19932 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19933 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19934 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19935 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19936 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19937 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19938 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19939 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19940 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19941 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19942 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19943 /* ARM v8.1 extension. */
19944 nUF(vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19945 nUF(vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19946 nUF(vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19947 nUF(vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19949 /* Two address, int/float. Types S8 S16 S32 F32. */
19950 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19951 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19953 /* Data processing with two registers and a shift amount. */
19954 /* Right shifts, and variants with rounding.
19955 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19956 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19957 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19958 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19959 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19960 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19961 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19962 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19963 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19964 /* Shift and insert. Sizes accepted 8 16 32 64. */
19965 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19966 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19967 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19968 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19969 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19970 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19971 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19972 /* Right shift immediate, saturating & narrowing, with rounding variants.
19973 Types accepted S16 S32 S64 U16 U32 U64. */
19974 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19975 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19976 /* As above, unsigned. Types accepted S16 S32 S64. */
19977 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19978 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19979 /* Right shift narrowing. Types accepted I16 I32 I64. */
19980 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19981 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19982 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19983 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19984 /* CVT with optional immediate for fixed-point variant. */
19985 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19987 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19988 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19990 /* Data processing, three registers of different lengths. */
19991 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19992 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
19993 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19994 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19995 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19996 /* If not scalar, fall back to neon_dyadic_long.
19997 Vector types as above, scalar types S16 S32 U16 U32. */
19998 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19999 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20000 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20001 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20002 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20003 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20004 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20005 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20006 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20007 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20008 /* Saturating doubling multiplies. Types S16 S32. */
20009 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20010 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20011 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20012 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20013 S16 S32 U16 U32. */
20014 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20016 /* Extract. Size 8. */
20017 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20018 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20020 /* Two registers, miscellaneous. */
20021 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20022 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20023 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20024 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20025 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20026 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20027 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20028 /* Vector replicate. Sizes 8 16 32. */
20029 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20030 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20031 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20032 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20033 /* VMOVN. Types I16 I32 I64. */
20034 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20035 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20036 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20037 /* VQMOVUN. Types S16 S32 S64. */
20038 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20039 /* VZIP / VUZP. Sizes 8 16 32. */
20040 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20041 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20042 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20043 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20044 /* VQABS / VQNEG. Types S8 S16 S32. */
20045 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20046 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20047 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20048 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20049 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20050 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20051 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20052 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20053 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20054 /* Reciprocal estimates. Types U32 F32. */
20055 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20056 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20057 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20058 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20059 /* VCLS. Types S8 S16 S32. */
20060 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20061 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20062 /* VCLZ. Types I8 I16 I32. */
20063 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20064 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20065 /* VCNT. Size 8. */
20066 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20067 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20068 /* Two address, untyped. */
20069 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20070 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20071 /* VTRN. Sizes 8 16 32. */
20072 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20073 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20075 /* Table lookup. Size 8. */
20076 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20077 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20079 #undef THUMB_VARIANT
20080 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20082 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20084 /* Neon element/structure load/store. */
20085 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20086 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20087 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20088 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20089 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20090 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20091 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20092 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20094 #undef THUMB_VARIANT
20095 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20097 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20098 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20099 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20100 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20101 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20102 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20103 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20104 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20105 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20106 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20108 #undef THUMB_VARIANT
20109 #define THUMB_VARIANT & fpu_vfp_ext_v3
20111 #define ARM_VARIANT & fpu_vfp_ext_v3
20113 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20114 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20115 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20116 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20117 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20118 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20119 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20120 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20121 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20124 #define ARM_VARIANT & fpu_vfp_ext_fma
20125 #undef THUMB_VARIANT
20126 #define THUMB_VARIANT & fpu_vfp_ext_fma
20127 /* Mnemonics shared by Neon and VFP. These are included in the
20128 VFP FMA variant; NEON and VFP FMA always includes the NEON
20129 FMA instructions. */
20130 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20131 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20132 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20133 the v form should always be used. */
20134 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20135 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20136 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20137 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20138 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20139 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20141 #undef THUMB_VARIANT
20143 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20145 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20146 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20147 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20148 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20149 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20150 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20151 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20152 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20155 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20157 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20158 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20159 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20160 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20161 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20162 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20163 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20164 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20165 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20166 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20167 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20168 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20169 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20170 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20171 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20172 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20173 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20174 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20175 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20176 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20177 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20178 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20179 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20180 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20181 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20182 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20183 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20184 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20185 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20186 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20187 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20188 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20189 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20190 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20191 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20192 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20193 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20194 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20195 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20196 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20197 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20198 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20199 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20200 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20201 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20202 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20203 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20204 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20205 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20206 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20207 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20208 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20209 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20210 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20211 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20212 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20213 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20214 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20215 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20216 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20217 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20218 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20219 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20220 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20221 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20222 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20223 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20224 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20225 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20226 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20227 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20228 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20229 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20230 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20231 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20232 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20233 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20234 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20235 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20236 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20237 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20238 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20239 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20240 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20241 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20242 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20243 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20244 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20245 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20246 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20247 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20248 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20249 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20250 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20251 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20252 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20253 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20254 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20255 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20256 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20257 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20258 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20259 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20260 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20261 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20262 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20263 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20264 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20265 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20266 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20267 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20268 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20269 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20270 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20271 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20272 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20273 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20274 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20275 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20276 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20277 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20278 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20279 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20280 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20281 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20282 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20283 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20284 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20285 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20286 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20287 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20288 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20289 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20290 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20291 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20292 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20293 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20294 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20295 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20296 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20297 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20298 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20299 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20300 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20301 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20302 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20303 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20304 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20305 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20306 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20307 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20308 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20309 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20310 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20311 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20312 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20313 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20314 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20315 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20316 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20317 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20318 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20321 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20323 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20324 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20325 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20326 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20327 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20328 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20329 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20330 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20331 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20332 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20333 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20334 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20335 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20336 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20337 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20338 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20339 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20340 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20341 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20342 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20343 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20344 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20345 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20346 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20347 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20348 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20349 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20350 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20351 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20352 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20353 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20354 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20355 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20356 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20357 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20358 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20359 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20360 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20361 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20362 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20363 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20364 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20365 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20366 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20367 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20368 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20369 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20370 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20371 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20372 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20373 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20374 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20375 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20376 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20377 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20378 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20379 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20382 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20384 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20385 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20386 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20387 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20388 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20389 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20390 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20391 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20392 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20393 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20394 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20395 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20396 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20397 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20398 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20399 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20400 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20401 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20402 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20403 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20404 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20405 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20406 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20407 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20408 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20409 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20410 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20411 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20412 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20413 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20414 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20415 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20416 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20417 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20418 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20419 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20420 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20421 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20422 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20423 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20424 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20425 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20426 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20427 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20428 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20429 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20430 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20431 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20432 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20433 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20434 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20435 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20436 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20437 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20438 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20439 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20440 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20441 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20442 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20443 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20444 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20445 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20446 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20447 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20448 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20449 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20450 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20451 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20452 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20453 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20454 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20455 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20456 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20457 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20458 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20459 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20462 #undef THUMB_VARIANT
20488 /* MD interface: bits in the object file. */
20490 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20491 for use in the a.out file, and stores them in the array pointed to by buf.
20492 This knows about the endian-ness of the target machine and does
20493 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20494 2 (short) and 4 (long) Floating numbers are put out as a series of
20495 LITTLENUMS (shorts, here at least). */
20498 md_number_to_chars (char * buf
, valueT val
, int n
)
20500 if (target_big_endian
)
20501 number_to_chars_bigendian (buf
, val
, n
);
20503 number_to_chars_littleendian (buf
, val
, n
);
20507 md_chars_to_number (char * buf
, int n
)
20510 unsigned char * where
= (unsigned char *) buf
;
20512 if (target_big_endian
)
20517 result
|= (*where
++ & 255);
20525 result
|= (where
[n
] & 255);
20532 /* MD interface: Sections. */
20534 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20535 that an rs_machine_dependent frag may reach. */
20538 arm_frag_max_var (fragS
*fragp
)
20540 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20541 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20543 Note that we generate relaxable instructions even for cases that don't
20544 really need it, like an immediate that's a trivial constant. So we're
20545 overestimating the instruction size for some of those cases. Rather
20546 than putting more intelligence here, it would probably be better to
20547 avoid generating a relaxation frag in the first place when it can be
20548 determined up front that a short instruction will suffice. */
20550 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20554 /* Estimate the size of a frag before relaxing. Assume everything fits in
20558 md_estimate_size_before_relax (fragS
* fragp
,
20559 segT segtype ATTRIBUTE_UNUSED
)
20565 /* Convert a machine dependent frag. */
20568 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20570 unsigned long insn
;
20571 unsigned long old_op
;
20579 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20581 old_op
= bfd_get_16(abfd
, buf
);
20582 if (fragp
->fr_symbol
)
20584 exp
.X_op
= O_symbol
;
20585 exp
.X_add_symbol
= fragp
->fr_symbol
;
20589 exp
.X_op
= O_constant
;
20591 exp
.X_add_number
= fragp
->fr_offset
;
20592 opcode
= fragp
->fr_subtype
;
20595 case T_MNEM_ldr_pc
:
20596 case T_MNEM_ldr_pc2
:
20597 case T_MNEM_ldr_sp
:
20598 case T_MNEM_str_sp
:
20605 if (fragp
->fr_var
== 4)
20607 insn
= THUMB_OP32 (opcode
);
20608 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20610 insn
|= (old_op
& 0x700) << 4;
20614 insn
|= (old_op
& 7) << 12;
20615 insn
|= (old_op
& 0x38) << 13;
20617 insn
|= 0x00000c00;
20618 put_thumb32_insn (buf
, insn
);
20619 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20623 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20625 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20628 if (fragp
->fr_var
== 4)
20630 insn
= THUMB_OP32 (opcode
);
20631 insn
|= (old_op
& 0xf0) << 4;
20632 put_thumb32_insn (buf
, insn
);
20633 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20637 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20638 exp
.X_add_number
-= 4;
20646 if (fragp
->fr_var
== 4)
20648 int r0off
= (opcode
== T_MNEM_mov
20649 || opcode
== T_MNEM_movs
) ? 0 : 8;
20650 insn
= THUMB_OP32 (opcode
);
20651 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20652 insn
|= (old_op
& 0x700) << r0off
;
20653 put_thumb32_insn (buf
, insn
);
20654 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20658 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20663 if (fragp
->fr_var
== 4)
20665 insn
= THUMB_OP32(opcode
);
20666 put_thumb32_insn (buf
, insn
);
20667 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20670 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20674 if (fragp
->fr_var
== 4)
20676 insn
= THUMB_OP32(opcode
);
20677 insn
|= (old_op
& 0xf00) << 14;
20678 put_thumb32_insn (buf
, insn
);
20679 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20682 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20685 case T_MNEM_add_sp
:
20686 case T_MNEM_add_pc
:
20687 case T_MNEM_inc_sp
:
20688 case T_MNEM_dec_sp
:
20689 if (fragp
->fr_var
== 4)
20691 /* ??? Choose between add and addw. */
20692 insn
= THUMB_OP32 (opcode
);
20693 insn
|= (old_op
& 0xf0) << 4;
20694 put_thumb32_insn (buf
, insn
);
20695 if (opcode
== T_MNEM_add_pc
)
20696 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20698 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20701 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20709 if (fragp
->fr_var
== 4)
20711 insn
= THUMB_OP32 (opcode
);
20712 insn
|= (old_op
& 0xf0) << 4;
20713 insn
|= (old_op
& 0xf) << 16;
20714 put_thumb32_insn (buf
, insn
);
20715 if (insn
& (1 << 20))
20716 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20718 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20721 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20727 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20728 (enum bfd_reloc_code_real
) reloc_type
);
20729 fixp
->fx_file
= fragp
->fr_file
;
20730 fixp
->fx_line
= fragp
->fr_line
;
20731 fragp
->fr_fix
+= fragp
->fr_var
;
20733 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20734 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
20735 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
20736 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
20739 /* Return the size of a relaxable immediate operand instruction.
20740 SHIFT and SIZE specify the form of the allowable immediate. */
20742 relax_immediate (fragS
*fragp
, int size
, int shift
)
20748 /* ??? Should be able to do better than this. */
20749 if (fragp
->fr_symbol
)
20752 low
= (1 << shift
) - 1;
20753 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20754 offset
= fragp
->fr_offset
;
20755 /* Force misaligned offsets to 32-bit variant. */
20758 if (offset
& ~mask
)
20763 /* Get the address of a symbol during relaxation. */
20765 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20771 sym
= fragp
->fr_symbol
;
20772 sym_frag
= symbol_get_frag (sym
);
20773 know (S_GET_SEGMENT (sym
) != absolute_section
20774 || sym_frag
== &zero_address_frag
);
20775 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20777 /* If frag has yet to be reached on this pass, assume it will
20778 move by STRETCH just as we did. If this is not so, it will
20779 be because some frag between grows, and that will force
20783 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20787 /* Adjust stretch for any alignment frag. Note that if have
20788 been expanding the earlier code, the symbol may be
20789 defined in what appears to be an earlier frag. FIXME:
20790 This doesn't handle the fr_subtype field, which specifies
20791 a maximum number of bytes to skip when doing an
20793 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20795 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20798 stretch
= - ((- stretch
)
20799 & ~ ((1 << (int) f
->fr_offset
) - 1));
20801 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20813 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20816 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20821 /* Assume worst case for symbols not known to be in the same section. */
20822 if (fragp
->fr_symbol
== NULL
20823 || !S_IS_DEFINED (fragp
->fr_symbol
)
20824 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20825 || S_IS_WEAK (fragp
->fr_symbol
))
20828 val
= relaxed_symbol_addr (fragp
, stretch
);
20829 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20830 addr
= (addr
+ 4) & ~3;
20831 /* Force misaligned targets to 32-bit variant. */
20835 if (val
< 0 || val
> 1020)
20840 /* Return the size of a relaxable add/sub immediate instruction. */
20842 relax_addsub (fragS
*fragp
, asection
*sec
)
20847 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20848 op
= bfd_get_16(sec
->owner
, buf
);
20849 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20850 return relax_immediate (fragp
, 8, 0);
20852 return relax_immediate (fragp
, 3, 0);
20855 /* Return TRUE iff the definition of symbol S could be pre-empted
20856 (overridden) at link or load time. */
20858 symbol_preemptible (symbolS
*s
)
20860 /* Weak symbols can always be pre-empted. */
20864 /* Non-global symbols cannot be pre-empted. */
20865 if (! S_IS_EXTERNAL (s
))
20869 /* In ELF, a global symbol can be marked protected, or private. In that
20870 case it can't be pre-empted (other definitions in the same link unit
20871 would violate the ODR). */
20872 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20876 /* Other global symbols might be pre-empted. */
20880 /* Return the size of a relaxable branch instruction. BITS is the
20881 size of the offset field in the narrow instruction. */
20884 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20890 /* Assume worst case for symbols not known to be in the same section. */
20891 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20892 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20893 || S_IS_WEAK (fragp
->fr_symbol
))
20897 /* A branch to a function in ARM state will require interworking. */
20898 if (S_IS_DEFINED (fragp
->fr_symbol
)
20899 && ARM_IS_FUNC (fragp
->fr_symbol
))
20903 if (symbol_preemptible (fragp
->fr_symbol
))
20906 val
= relaxed_symbol_addr (fragp
, stretch
);
20907 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20910 /* Offset is a signed value *2 */
20912 if (val
>= limit
|| val
< -limit
)
20918 /* Relax a machine dependent frag. This returns the amount by which
20919 the current size of the frag should change. */
20922 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20927 oldsize
= fragp
->fr_var
;
20928 switch (fragp
->fr_subtype
)
20930 case T_MNEM_ldr_pc2
:
20931 newsize
= relax_adr (fragp
, sec
, stretch
);
20933 case T_MNEM_ldr_pc
:
20934 case T_MNEM_ldr_sp
:
20935 case T_MNEM_str_sp
:
20936 newsize
= relax_immediate (fragp
, 8, 2);
20940 newsize
= relax_immediate (fragp
, 5, 2);
20944 newsize
= relax_immediate (fragp
, 5, 1);
20948 newsize
= relax_immediate (fragp
, 5, 0);
20951 newsize
= relax_adr (fragp
, sec
, stretch
);
20957 newsize
= relax_immediate (fragp
, 8, 0);
20960 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20963 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20965 case T_MNEM_add_sp
:
20966 case T_MNEM_add_pc
:
20967 newsize
= relax_immediate (fragp
, 8, 2);
20969 case T_MNEM_inc_sp
:
20970 case T_MNEM_dec_sp
:
20971 newsize
= relax_immediate (fragp
, 7, 2);
20977 newsize
= relax_addsub (fragp
, sec
);
20983 fragp
->fr_var
= newsize
;
20984 /* Freeze wide instructions that are at or before the same location as
20985 in the previous pass. This avoids infinite loops.
20986 Don't freeze them unconditionally because targets may be artificially
20987 misaligned by the expansion of preceding frags. */
20988 if (stretch
<= 0 && newsize
> 2)
20990 md_convert_frag (sec
->owner
, sec
, fragp
);
20994 return newsize
- oldsize
;
20997 /* Round up a section size to the appropriate boundary. */
21000 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21003 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21004 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21006 /* For a.out, force the section size to be aligned. If we don't do
21007 this, BFD will align it for us, but it will not write out the
21008 final bytes of the section. This may be a bug in BFD, but it is
21009 easier to fix it here since that is how the other a.out targets
21013 align
= bfd_get_section_alignment (stdoutput
, segment
);
21014 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21021 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21022 of an rs_align_code fragment. */
21025 arm_handle_align (fragS
* fragP
)
21027 static char const arm_noop
[2][2][4] =
21030 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21031 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21034 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21035 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21038 static char const thumb_noop
[2][2][2] =
21041 {0xc0, 0x46}, /* LE */
21042 {0x46, 0xc0}, /* BE */
21045 {0x00, 0xbf}, /* LE */
21046 {0xbf, 0x00} /* BE */
21049 static char const wide_thumb_noop
[2][4] =
21050 { /* Wide Thumb-2 */
21051 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21052 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21055 unsigned bytes
, fix
, noop_size
;
21058 const char *narrow_noop
= NULL
;
21063 if (fragP
->fr_type
!= rs_align_code
)
21066 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21067 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21070 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21071 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21073 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21075 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21077 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21078 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21080 narrow_noop
= thumb_noop
[1][target_big_endian
];
21081 noop
= wide_thumb_noop
[target_big_endian
];
21084 noop
= thumb_noop
[0][target_big_endian
];
21092 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21093 ? selected_cpu
: arm_arch_none
,
21095 [target_big_endian
];
21102 fragP
->fr_var
= noop_size
;
21104 if (bytes
& (noop_size
- 1))
21106 fix
= bytes
& (noop_size
- 1);
21108 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21110 memset (p
, 0, fix
);
21117 if (bytes
& noop_size
)
21119 /* Insert a narrow noop. */
21120 memcpy (p
, narrow_noop
, noop_size
);
21122 bytes
-= noop_size
;
21126 /* Use wide noops for the remainder */
21130 while (bytes
>= noop_size
)
21132 memcpy (p
, noop
, noop_size
);
21134 bytes
-= noop_size
;
21138 fragP
->fr_fix
+= fix
;
21141 /* Called from md_do_align. Used to create an alignment
21142 frag in a code section. */
21145 arm_frag_align_code (int n
, int max
)
21149 /* We assume that there will never be a requirement
21150 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21151 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21156 _("alignments greater than %d bytes not supported in .text sections."),
21157 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21158 as_fatal ("%s", err_msg
);
21161 p
= frag_var (rs_align_code
,
21162 MAX_MEM_FOR_RS_ALIGN_CODE
,
21164 (relax_substateT
) max
,
21171 /* Perform target specific initialisation of a frag.
21172 Note - despite the name this initialisation is not done when the frag
21173 is created, but only when its type is assigned. A frag can be created
21174 and used a long time before its type is set, so beware of assuming that
21175 this initialisationis performed first. */
21179 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21181 /* Record whether this frag is in an ARM or a THUMB area. */
21182 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21185 #else /* OBJ_ELF is defined. */
21187 arm_init_frag (fragS
* fragP
, int max_chars
)
21189 int frag_thumb_mode
;
21191 /* If the current ARM vs THUMB mode has not already
21192 been recorded into this frag then do so now. */
21193 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21194 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21196 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21198 /* Record a mapping symbol for alignment frags. We will delete this
21199 later if the alignment ends up empty. */
21200 switch (fragP
->fr_type
)
21203 case rs_align_test
:
21205 mapping_state_2 (MAP_DATA
, max_chars
);
21207 case rs_align_code
:
21208 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21215 /* When we change sections we need to issue a new mapping symbol. */
21218 arm_elf_change_section (void)
21220 /* Link an unlinked unwind index table section to the .text section. */
21221 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21222 && elf_linked_to_section (now_seg
) == NULL
)
21223 elf_linked_to_section (now_seg
) = text_section
;
21227 arm_elf_section_type (const char * str
, size_t len
)
21229 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21230 return SHT_ARM_EXIDX
;
21235 /* Code to deal with unwinding tables. */
21237 static void add_unwind_adjustsp (offsetT
);
21239 /* Generate any deferred unwind frame offset. */
21242 flush_pending_unwind (void)
21246 offset
= unwind
.pending_offset
;
21247 unwind
.pending_offset
= 0;
21249 add_unwind_adjustsp (offset
);
21252 /* Add an opcode to this list for this function. Two-byte opcodes should
21253 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21257 add_unwind_opcode (valueT op
, int length
)
21259 /* Add any deferred stack adjustment. */
21260 if (unwind
.pending_offset
)
21261 flush_pending_unwind ();
21263 unwind
.sp_restored
= 0;
21265 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21267 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21268 if (unwind
.opcodes
)
21269 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
21270 unwind
.opcode_alloc
);
21272 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
21277 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21279 unwind
.opcode_count
++;
21283 /* Add unwind opcodes to adjust the stack pointer. */
21286 add_unwind_adjustsp (offsetT offset
)
21290 if (offset
> 0x200)
21292 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21297 /* Long form: 0xb2, uleb128. */
21298 /* This might not fit in a word so add the individual bytes,
21299 remembering the list is built in reverse order. */
21300 o
= (valueT
) ((offset
- 0x204) >> 2);
21302 add_unwind_opcode (0, 1);
21304 /* Calculate the uleb128 encoding of the offset. */
21308 bytes
[n
] = o
& 0x7f;
21314 /* Add the insn. */
21316 add_unwind_opcode (bytes
[n
- 1], 1);
21317 add_unwind_opcode (0xb2, 1);
21319 else if (offset
> 0x100)
21321 /* Two short opcodes. */
21322 add_unwind_opcode (0x3f, 1);
21323 op
= (offset
- 0x104) >> 2;
21324 add_unwind_opcode (op
, 1);
21326 else if (offset
> 0)
21328 /* Short opcode. */
21329 op
= (offset
- 4) >> 2;
21330 add_unwind_opcode (op
, 1);
21332 else if (offset
< 0)
21335 while (offset
> 0x100)
21337 add_unwind_opcode (0x7f, 1);
21340 op
= ((offset
- 4) >> 2) | 0x40;
21341 add_unwind_opcode (op
, 1);
21345 /* Finish the list of unwind opcodes for this function. */
21347 finish_unwind_opcodes (void)
21351 if (unwind
.fp_used
)
21353 /* Adjust sp as necessary. */
21354 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21355 flush_pending_unwind ();
21357 /* After restoring sp from the frame pointer. */
21358 op
= 0x90 | unwind
.fp_reg
;
21359 add_unwind_opcode (op
, 1);
21362 flush_pending_unwind ();
21366 /* Start an exception table entry. If idx is nonzero this is an index table
21370 start_unwind_section (const segT text_seg
, int idx
)
21372 const char * text_name
;
21373 const char * prefix
;
21374 const char * prefix_once
;
21375 const char * group_name
;
21379 size_t sec_name_len
;
21386 prefix
= ELF_STRING_ARM_unwind
;
21387 prefix_once
= ELF_STRING_ARM_unwind_once
;
21388 type
= SHT_ARM_EXIDX
;
21392 prefix
= ELF_STRING_ARM_unwind_info
;
21393 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21394 type
= SHT_PROGBITS
;
21397 text_name
= segment_name (text_seg
);
21398 if (streq (text_name
, ".text"))
21401 if (strncmp (text_name
, ".gnu.linkonce.t.",
21402 strlen (".gnu.linkonce.t.")) == 0)
21404 prefix
= prefix_once
;
21405 text_name
+= strlen (".gnu.linkonce.t.");
21408 prefix_len
= strlen (prefix
);
21409 text_len
= strlen (text_name
);
21410 sec_name_len
= prefix_len
+ text_len
;
21411 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21412 memcpy (sec_name
, prefix
, prefix_len
);
21413 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21414 sec_name
[prefix_len
+ text_len
] = '\0';
21420 /* Handle COMDAT group. */
21421 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21423 group_name
= elf_group_name (text_seg
);
21424 if (group_name
== NULL
)
21426 as_bad (_("Group section `%s' has no group signature"),
21427 segment_name (text_seg
));
21428 ignore_rest_of_line ();
21431 flags
|= SHF_GROUP
;
21435 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21437 /* Set the section link for index tables. */
21439 elf_linked_to_section (now_seg
) = text_seg
;
21443 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21444 personality routine data. Returns zero, or the index table value for
21445 an inline entry. */
21448 create_unwind_entry (int have_data
)
21453 /* The current word of data. */
21455 /* The number of bytes left in this word. */
21458 finish_unwind_opcodes ();
21460 /* Remember the current text section. */
21461 unwind
.saved_seg
= now_seg
;
21462 unwind
.saved_subseg
= now_subseg
;
21464 start_unwind_section (now_seg
, 0);
21466 if (unwind
.personality_routine
== NULL
)
21468 if (unwind
.personality_index
== -2)
21471 as_bad (_("handlerdata in cantunwind frame"));
21472 return 1; /* EXIDX_CANTUNWIND. */
21475 /* Use a default personality routine if none is specified. */
21476 if (unwind
.personality_index
== -1)
21478 if (unwind
.opcode_count
> 3)
21479 unwind
.personality_index
= 1;
21481 unwind
.personality_index
= 0;
21484 /* Space for the personality routine entry. */
21485 if (unwind
.personality_index
== 0)
21487 if (unwind
.opcode_count
> 3)
21488 as_bad (_("too many unwind opcodes for personality routine 0"));
21492 /* All the data is inline in the index table. */
21495 while (unwind
.opcode_count
> 0)
21497 unwind
.opcode_count
--;
21498 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21502 /* Pad with "finish" opcodes. */
21504 data
= (data
<< 8) | 0xb0;
21511 /* We get two opcodes "free" in the first word. */
21512 size
= unwind
.opcode_count
- 2;
21516 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21517 if (unwind
.personality_index
!= -1)
21519 as_bad (_("attempt to recreate an unwind entry"));
21523 /* An extra byte is required for the opcode count. */
21524 size
= unwind
.opcode_count
+ 1;
21527 size
= (size
+ 3) >> 2;
21529 as_bad (_("too many unwind opcodes"));
21531 frag_align (2, 0, 0);
21532 record_alignment (now_seg
, 2);
21533 unwind
.table_entry
= expr_build_dot ();
21535 /* Allocate the table entry. */
21536 ptr
= frag_more ((size
<< 2) + 4);
21537 /* PR 13449: Zero the table entries in case some of them are not used. */
21538 memset (ptr
, 0, (size
<< 2) + 4);
21539 where
= frag_now_fix () - ((size
<< 2) + 4);
21541 switch (unwind
.personality_index
)
21544 /* ??? Should this be a PLT generating relocation? */
21545 /* Custom personality routine. */
21546 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21547 BFD_RELOC_ARM_PREL31
);
21552 /* Set the first byte to the number of additional words. */
21553 data
= size
> 0 ? size
- 1 : 0;
21557 /* ABI defined personality routines. */
21559 /* Three opcodes bytes are packed into the first word. */
21566 /* The size and first two opcode bytes go in the first word. */
21567 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21572 /* Should never happen. */
21576 /* Pack the opcodes into words (MSB first), reversing the list at the same
21578 while (unwind
.opcode_count
> 0)
21582 md_number_to_chars (ptr
, data
, 4);
21587 unwind
.opcode_count
--;
21589 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21592 /* Finish off the last word. */
21595 /* Pad with "finish" opcodes. */
21597 data
= (data
<< 8) | 0xb0;
21599 md_number_to_chars (ptr
, data
, 4);
21604 /* Add an empty descriptor if there is no user-specified data. */
21605 ptr
= frag_more (4);
21606 md_number_to_chars (ptr
, 0, 4);
21613 /* Initialize the DWARF-2 unwind information for this procedure. */
21616 tc_arm_frame_initial_instructions (void)
21618 cfi_add_CFA_def_cfa (REG_SP
, 0);
21620 #endif /* OBJ_ELF */
21622 /* Convert REGNAME to a DWARF-2 register number. */
21625 tc_arm_regname_to_dw2regnum (char *regname
)
21627 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21631 /* PR 16694: Allow VFP registers as well. */
21632 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21636 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21645 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21649 exp
.X_op
= O_secrel
;
21650 exp
.X_add_symbol
= symbol
;
21651 exp
.X_add_number
= 0;
21652 emit_expr (&exp
, size
);
21656 /* MD interface: Symbol and relocation handling. */
21658 /* Return the address within the segment that a PC-relative fixup is
21659 relative to. For ARM, PC-relative fixups applied to instructions
21660 are generally relative to the location of the fixup plus 8 bytes.
21661 Thumb branches are offset by 4, and Thumb loads relative to PC
21662 require special handling. */
21665 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21667 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21669 /* If this is pc-relative and we are going to emit a relocation
21670 then we just want to put out any pipeline compensation that the linker
21671 will need. Otherwise we want to use the calculated base.
21672 For WinCE we skip the bias for externals as well, since this
21673 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21675 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21676 || (arm_force_relocation (fixP
)
21678 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21684 switch (fixP
->fx_r_type
)
21686 /* PC relative addressing on the Thumb is slightly odd as the
21687 bottom two bits of the PC are forced to zero for the
21688 calculation. This happens *after* application of the
21689 pipeline offset. However, Thumb adrl already adjusts for
21690 this, so we need not do it again. */
21691 case BFD_RELOC_ARM_THUMB_ADD
:
21694 case BFD_RELOC_ARM_THUMB_OFFSET
:
21695 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21696 case BFD_RELOC_ARM_T32_ADD_PC12
:
21697 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21698 return (base
+ 4) & ~3;
21700 /* Thumb branches are simply offset by +4. */
21701 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21702 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21703 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21704 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21705 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21708 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21710 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21711 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21712 && ARM_IS_FUNC (fixP
->fx_addsy
)
21713 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21714 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21717 /* BLX is like branches above, but forces the low two bits of PC to
21719 case BFD_RELOC_THUMB_PCREL_BLX
:
21721 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21722 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21723 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21724 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21725 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21726 return (base
+ 4) & ~3;
21728 /* ARM mode branches are offset by +8. However, the Windows CE
21729 loader expects the relocation not to take this into account. */
21730 case BFD_RELOC_ARM_PCREL_BLX
:
21732 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21733 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21734 && ARM_IS_FUNC (fixP
->fx_addsy
)
21735 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21736 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21739 case BFD_RELOC_ARM_PCREL_CALL
:
21741 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21742 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21743 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21744 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21745 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21748 case BFD_RELOC_ARM_PCREL_BRANCH
:
21749 case BFD_RELOC_ARM_PCREL_JUMP
:
21750 case BFD_RELOC_ARM_PLT32
:
21752 /* When handling fixups immediately, because we have already
21753 discovered the value of a symbol, or the address of the frag involved
21754 we must account for the offset by +8, as the OS loader will never see the reloc.
21755 see fixup_segment() in write.c
21756 The S_IS_EXTERNAL test handles the case of global symbols.
21757 Those need the calculated base, not just the pipe compensation the linker will need. */
21759 && fixP
->fx_addsy
!= NULL
21760 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21761 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21769 /* ARM mode loads relative to PC are also offset by +8. Unlike
21770 branches, the Windows CE loader *does* expect the relocation
21771 to take this into account. */
21772 case BFD_RELOC_ARM_OFFSET_IMM
:
21773 case BFD_RELOC_ARM_OFFSET_IMM8
:
21774 case BFD_RELOC_ARM_HWLITERAL
:
21775 case BFD_RELOC_ARM_LITERAL
:
21776 case BFD_RELOC_ARM_CP_OFF_IMM
:
21780 /* Other PC-relative relocations are un-offset. */
21786 static bfd_boolean flag_warn_syms
= TRUE
;
21789 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
21791 /* PR 18347 - Warn if the user attempts to create a symbol with the same
21792 name as an ARM instruction. Whilst strictly speaking it is allowed, it
21793 does mean that the resulting code might be very confusing to the reader.
21794 Also this warning can be triggered if the user omits an operand before
21795 an immediate address, eg:
21799 GAS treats this as an assignment of the value of the symbol foo to a
21800 symbol LDR, and so (without this code) it will not issue any kind of
21801 warning or error message.
21803 Note - ARM instructions are case-insensitive but the strings in the hash
21804 table are all stored in lower case, so we must first ensure that name is
21806 if (flag_warn_syms
&& arm_ops_hsh
)
21808 char * nbuf
= strdup (name
);
21811 for (p
= nbuf
; *p
; p
++)
21813 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
21815 static struct hash_control
* already_warned
= NULL
;
21817 if (already_warned
== NULL
)
21818 already_warned
= hash_new ();
21819 /* Only warn about the symbol once. To keep the code
21820 simple we let hash_insert do the lookup for us. */
21821 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
21822 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
21831 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21832 Otherwise we have no need to default values of symbols. */
21835 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21838 if (name
[0] == '_' && name
[1] == 'G'
21839 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21843 if (symbol_find (name
))
21844 as_bad (_("GOT already in the symbol table"));
21846 GOT_symbol
= symbol_new (name
, undefined_section
,
21847 (valueT
) 0, & zero_address_frag
);
21857 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21858 computed as two separate immediate values, added together. We
21859 already know that this value cannot be computed by just one ARM
21862 static unsigned int
21863 validate_immediate_twopart (unsigned int val
,
21864 unsigned int * highpart
)
21869 for (i
= 0; i
< 32; i
+= 2)
21870 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21876 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21878 else if (a
& 0xff0000)
21880 if (a
& 0xff000000)
21882 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21886 gas_assert (a
& 0xff000000);
21887 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21890 return (a
& 0xff) | (i
<< 7);
21897 validate_offset_imm (unsigned int val
, int hwse
)
21899 if ((hwse
&& val
> 255) || val
> 4095)
21904 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21905 negative immediate constant by altering the instruction. A bit of
21910 by inverting the second operand, and
21913 by negating the second operand. */
21916 negate_data_op (unsigned long * instruction
,
21917 unsigned long value
)
21920 unsigned long negated
, inverted
;
21922 negated
= encode_arm_immediate (-value
);
21923 inverted
= encode_arm_immediate (~value
);
21925 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21928 /* First negates. */
21929 case OPCODE_SUB
: /* ADD <-> SUB */
21930 new_inst
= OPCODE_ADD
;
21935 new_inst
= OPCODE_SUB
;
21939 case OPCODE_CMP
: /* CMP <-> CMN */
21940 new_inst
= OPCODE_CMN
;
21945 new_inst
= OPCODE_CMP
;
21949 /* Now Inverted ops. */
21950 case OPCODE_MOV
: /* MOV <-> MVN */
21951 new_inst
= OPCODE_MVN
;
21956 new_inst
= OPCODE_MOV
;
21960 case OPCODE_AND
: /* AND <-> BIC */
21961 new_inst
= OPCODE_BIC
;
21966 new_inst
= OPCODE_AND
;
21970 case OPCODE_ADC
: /* ADC <-> SBC */
21971 new_inst
= OPCODE_SBC
;
21976 new_inst
= OPCODE_ADC
;
21980 /* We cannot do anything. */
21985 if (value
== (unsigned) FAIL
)
21988 *instruction
&= OPCODE_MASK
;
21989 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
21993 /* Like negate_data_op, but for Thumb-2. */
21995 static unsigned int
21996 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22000 unsigned int negated
, inverted
;
22002 negated
= encode_thumb32_immediate (-value
);
22003 inverted
= encode_thumb32_immediate (~value
);
22005 rd
= (*instruction
>> 8) & 0xf;
22006 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22009 /* ADD <-> SUB. Includes CMP <-> CMN. */
22010 case T2_OPCODE_SUB
:
22011 new_inst
= T2_OPCODE_ADD
;
22015 case T2_OPCODE_ADD
:
22016 new_inst
= T2_OPCODE_SUB
;
22020 /* ORR <-> ORN. Includes MOV <-> MVN. */
22021 case T2_OPCODE_ORR
:
22022 new_inst
= T2_OPCODE_ORN
;
22026 case T2_OPCODE_ORN
:
22027 new_inst
= T2_OPCODE_ORR
;
22031 /* AND <-> BIC. TST has no inverted equivalent. */
22032 case T2_OPCODE_AND
:
22033 new_inst
= T2_OPCODE_BIC
;
22040 case T2_OPCODE_BIC
:
22041 new_inst
= T2_OPCODE_AND
;
22046 case T2_OPCODE_ADC
:
22047 new_inst
= T2_OPCODE_SBC
;
22051 case T2_OPCODE_SBC
:
22052 new_inst
= T2_OPCODE_ADC
;
22056 /* We cannot do anything. */
22061 if (value
== (unsigned int)FAIL
)
22064 *instruction
&= T2_OPCODE_MASK
;
22065 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22069 /* Read a 32-bit thumb instruction from buf. */
22070 static unsigned long
22071 get_thumb32_insn (char * buf
)
22073 unsigned long insn
;
22074 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22075 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22081 /* We usually want to set the low bit on the address of thumb function
22082 symbols. In particular .word foo - . should have the low bit set.
22083 Generic code tries to fold the difference of two symbols to
22084 a constant. Prevent this and force a relocation when the first symbols
22085 is a thumb function. */
22088 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22090 if (op
== O_subtract
22091 && l
->X_op
== O_symbol
22092 && r
->X_op
== O_symbol
22093 && THUMB_IS_FUNC (l
->X_add_symbol
))
22095 l
->X_op
= O_subtract
;
22096 l
->X_op_symbol
= r
->X_add_symbol
;
22097 l
->X_add_number
-= r
->X_add_number
;
22101 /* Process as normal. */
22105 /* Encode Thumb2 unconditional branches and calls. The encoding
22106 for the 2 are identical for the immediate values. */
22109 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22111 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22114 addressT S
, I1
, I2
, lo
, hi
;
22116 S
= (value
>> 24) & 0x01;
22117 I1
= (value
>> 23) & 0x01;
22118 I2
= (value
>> 22) & 0x01;
22119 hi
= (value
>> 12) & 0x3ff;
22120 lo
= (value
>> 1) & 0x7ff;
22121 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22122 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22123 newval
|= (S
<< 10) | hi
;
22124 newval2
&= ~T2I1I2MASK
;
22125 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22126 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22127 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22131 md_apply_fix (fixS
* fixP
,
22135 offsetT value
= * valP
;
22137 unsigned int newimm
;
22138 unsigned long temp
;
22140 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22142 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22144 /* Note whether this will delete the relocation. */
22146 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22149 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22150 consistency with the behaviour on 32-bit hosts. Remember value
22152 value
&= 0xffffffff;
22153 value
^= 0x80000000;
22154 value
-= 0x80000000;
22157 fixP
->fx_addnumber
= value
;
22159 /* Same treatment for fixP->fx_offset. */
22160 fixP
->fx_offset
&= 0xffffffff;
22161 fixP
->fx_offset
^= 0x80000000;
22162 fixP
->fx_offset
-= 0x80000000;
22164 switch (fixP
->fx_r_type
)
22166 case BFD_RELOC_NONE
:
22167 /* This will need to go in the object file. */
22171 case BFD_RELOC_ARM_IMMEDIATE
:
22172 /* We claim that this fixup has been processed here,
22173 even if in fact we generate an error because we do
22174 not have a reloc for it, so tc_gen_reloc will reject it. */
22177 if (fixP
->fx_addsy
)
22179 const char *msg
= 0;
22181 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22182 msg
= _("undefined symbol %s used as an immediate value");
22183 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22184 msg
= _("symbol %s is in a different section");
22185 else if (S_IS_WEAK (fixP
->fx_addsy
))
22186 msg
= _("symbol %s is weak and may be overridden later");
22190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22191 msg
, S_GET_NAME (fixP
->fx_addsy
));
22196 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22198 /* If the offset is negative, we should use encoding A2 for ADR. */
22199 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22200 newimm
= negate_data_op (&temp
, value
);
22203 newimm
= encode_arm_immediate (value
);
22205 /* If the instruction will fail, see if we can fix things up by
22206 changing the opcode. */
22207 if (newimm
== (unsigned int) FAIL
)
22208 newimm
= negate_data_op (&temp
, value
);
22211 if (newimm
== (unsigned int) FAIL
)
22213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22214 _("invalid constant (%lx) after fixup"),
22215 (unsigned long) value
);
22219 newimm
|= (temp
& 0xfffff000);
22220 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22223 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22225 unsigned int highpart
= 0;
22226 unsigned int newinsn
= 0xe1a00000; /* nop. */
22228 if (fixP
->fx_addsy
)
22230 const char *msg
= 0;
22232 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22233 msg
= _("undefined symbol %s used as an immediate value");
22234 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22235 msg
= _("symbol %s is in a different section");
22236 else if (S_IS_WEAK (fixP
->fx_addsy
))
22237 msg
= _("symbol %s is weak and may be overridden later");
22241 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22242 msg
, S_GET_NAME (fixP
->fx_addsy
));
22247 newimm
= encode_arm_immediate (value
);
22248 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22250 /* If the instruction will fail, see if we can fix things up by
22251 changing the opcode. */
22252 if (newimm
== (unsigned int) FAIL
22253 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22255 /* No ? OK - try using two ADD instructions to generate
22257 newimm
= validate_immediate_twopart (value
, & highpart
);
22259 /* Yes - then make sure that the second instruction is
22261 if (newimm
!= (unsigned int) FAIL
)
22263 /* Still No ? Try using a negated value. */
22264 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22265 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22266 /* Otherwise - give up. */
22269 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22270 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22275 /* Replace the first operand in the 2nd instruction (which
22276 is the PC) with the destination register. We have
22277 already added in the PC in the first instruction and we
22278 do not want to do it again. */
22279 newinsn
&= ~ 0xf0000;
22280 newinsn
|= ((newinsn
& 0x0f000) << 4);
22283 newimm
|= (temp
& 0xfffff000);
22284 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22286 highpart
|= (newinsn
& 0xfffff000);
22287 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22291 case BFD_RELOC_ARM_OFFSET_IMM
:
22292 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22295 case BFD_RELOC_ARM_LITERAL
:
22301 if (validate_offset_imm (value
, 0) == FAIL
)
22303 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22305 _("invalid literal constant: pool needs to be closer"));
22307 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22308 _("bad immediate value for offset (%ld)"),
22313 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22315 newval
&= 0xfffff000;
22318 newval
&= 0xff7ff000;
22319 newval
|= value
| (sign
? INDEX_UP
: 0);
22321 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22324 case BFD_RELOC_ARM_OFFSET_IMM8
:
22325 case BFD_RELOC_ARM_HWLITERAL
:
22331 if (validate_offset_imm (value
, 1) == FAIL
)
22333 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22335 _("invalid literal constant: pool needs to be closer"));
22337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22338 _("bad immediate value for 8-bit offset (%ld)"),
22343 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22345 newval
&= 0xfffff0f0;
22348 newval
&= 0xff7ff0f0;
22349 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22351 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22354 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22355 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22357 _("bad immediate value for offset (%ld)"), (long) value
);
22360 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22362 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22365 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22366 /* This is a complicated relocation used for all varieties of Thumb32
22367 load/store instruction with immediate offset:
22369 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22370 *4, optional writeback(W)
22371 (doubleword load/store)
22373 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22374 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22375 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22376 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22377 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22379 Uppercase letters indicate bits that are already encoded at
22380 this point. Lowercase letters are our problem. For the
22381 second block of instructions, the secondary opcode nybble
22382 (bits 8..11) is present, and bit 23 is zero, even if this is
22383 a PC-relative operation. */
22384 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22386 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22388 if ((newval
& 0xf0000000) == 0xe0000000)
22390 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22392 newval
|= (1 << 23);
22395 if (value
% 4 != 0)
22397 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22398 _("offset not a multiple of 4"));
22404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22405 _("offset out of range"));
22410 else if ((newval
& 0x000f0000) == 0x000f0000)
22412 /* PC-relative, 12-bit offset. */
22414 newval
|= (1 << 23);
22419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22420 _("offset out of range"));
22425 else if ((newval
& 0x00000100) == 0x00000100)
22427 /* Writeback: 8-bit, +/- offset. */
22429 newval
|= (1 << 9);
22434 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22435 _("offset out of range"));
22440 else if ((newval
& 0x00000f00) == 0x00000e00)
22442 /* T-instruction: positive 8-bit offset. */
22443 if (value
< 0 || value
> 0xff)
22445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22446 _("offset out of range"));
22454 /* Positive 12-bit or negative 8-bit offset. */
22458 newval
|= (1 << 23);
22468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22469 _("offset out of range"));
22476 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22477 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22480 case BFD_RELOC_ARM_SHIFT_IMM
:
22481 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22482 if (((unsigned long) value
) > 32
22484 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22487 _("shift expression is too large"));
22492 /* Shifts of zero must be done as lsl. */
22494 else if (value
== 32)
22496 newval
&= 0xfffff07f;
22497 newval
|= (value
& 0x1f) << 7;
22498 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22501 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22502 case BFD_RELOC_ARM_T32_ADD_IMM
:
22503 case BFD_RELOC_ARM_T32_IMM12
:
22504 case BFD_RELOC_ARM_T32_ADD_PC12
:
22505 /* We claim that this fixup has been processed here,
22506 even if in fact we generate an error because we do
22507 not have a reloc for it, so tc_gen_reloc will reject it. */
22511 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22514 _("undefined symbol %s used as an immediate value"),
22515 S_GET_NAME (fixP
->fx_addsy
));
22519 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22521 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22524 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22525 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22527 newimm
= encode_thumb32_immediate (value
);
22528 if (newimm
== (unsigned int) FAIL
)
22529 newimm
= thumb32_negate_data_op (&newval
, value
);
22531 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22532 && newimm
== (unsigned int) FAIL
)
22534 /* Turn add/sum into addw/subw. */
22535 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22536 newval
= (newval
& 0xfeffffff) | 0x02000000;
22537 /* No flat 12-bit imm encoding for addsw/subsw. */
22538 if ((newval
& 0x00100000) == 0)
22540 /* 12 bit immediate for addw/subw. */
22544 newval
^= 0x00a00000;
22547 newimm
= (unsigned int) FAIL
;
22553 if (newimm
== (unsigned int)FAIL
)
22555 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22556 _("invalid constant (%lx) after fixup"),
22557 (unsigned long) value
);
22561 newval
|= (newimm
& 0x800) << 15;
22562 newval
|= (newimm
& 0x700) << 4;
22563 newval
|= (newimm
& 0x0ff);
22565 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22566 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22569 case BFD_RELOC_ARM_SMC
:
22570 if (((unsigned long) value
) > 0xffff)
22571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22572 _("invalid smc expression"));
22573 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22574 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22575 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22578 case BFD_RELOC_ARM_HVC
:
22579 if (((unsigned long) value
) > 0xffff)
22580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22581 _("invalid hvc expression"));
22582 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22583 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22584 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22587 case BFD_RELOC_ARM_SWI
:
22588 if (fixP
->tc_fix_data
!= 0)
22590 if (((unsigned long) value
) > 0xff)
22591 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22592 _("invalid swi expression"));
22593 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22595 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22599 if (((unsigned long) value
) > 0x00ffffff)
22600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22601 _("invalid swi expression"));
22602 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22604 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22608 case BFD_RELOC_ARM_MULTI
:
22609 if (((unsigned long) value
) > 0xffff)
22610 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22611 _("invalid expression in load/store multiple"));
22612 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22613 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22617 case BFD_RELOC_ARM_PCREL_CALL
:
22619 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22621 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22622 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22623 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22624 /* Flip the bl to blx. This is a simple flip
22625 bit here because we generate PCREL_CALL for
22626 unconditional bls. */
22628 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22629 newval
= newval
| 0x10000000;
22630 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22636 goto arm_branch_common
;
22638 case BFD_RELOC_ARM_PCREL_JUMP
:
22639 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22641 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22642 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22643 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22645 /* This would map to a bl<cond>, b<cond>,
22646 b<always> to a Thumb function. We
22647 need to force a relocation for this particular
22649 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22653 case BFD_RELOC_ARM_PLT32
:
22655 case BFD_RELOC_ARM_PCREL_BRANCH
:
22657 goto arm_branch_common
;
22659 case BFD_RELOC_ARM_PCREL_BLX
:
22662 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22664 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22665 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22666 && ARM_IS_FUNC (fixP
->fx_addsy
))
22668 /* Flip the blx to a bl and warn. */
22669 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22670 newval
= 0xeb000000;
22671 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22672 _("blx to '%s' an ARM ISA state function changed to bl"),
22674 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22680 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22681 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22685 /* We are going to store value (shifted right by two) in the
22686 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22687 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22688 also be be clear. */
22690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22691 _("misaligned branch destination"));
22692 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22693 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22696 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22698 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22699 newval
|= (value
>> 2) & 0x00ffffff;
22700 /* Set the H bit on BLX instructions. */
22704 newval
|= 0x01000000;
22706 newval
&= ~0x01000000;
22708 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22712 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22713 /* CBZ can only branch forward. */
22715 /* Attempts to use CBZ to branch to the next instruction
22716 (which, strictly speaking, are prohibited) will be turned into
22719 FIXME: It may be better to remove the instruction completely and
22720 perform relaxation. */
22723 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22724 newval
= 0xbf00; /* NOP encoding T1 */
22725 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22730 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22732 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22734 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22735 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22736 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22741 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22742 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22743 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22745 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22747 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22748 newval
|= (value
& 0x1ff) >> 1;
22749 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22753 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22754 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22757 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22759 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22760 newval
|= (value
& 0xfff) >> 1;
22761 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22765 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22767 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22768 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22769 && ARM_IS_FUNC (fixP
->fx_addsy
)
22770 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22772 /* Force a relocation for a branch 20 bits wide. */
22775 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22777 _("conditional branch out of range"));
22779 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22782 addressT S
, J1
, J2
, lo
, hi
;
22784 S
= (value
& 0x00100000) >> 20;
22785 J2
= (value
& 0x00080000) >> 19;
22786 J1
= (value
& 0x00040000) >> 18;
22787 hi
= (value
& 0x0003f000) >> 12;
22788 lo
= (value
& 0x00000ffe) >> 1;
22790 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22791 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22792 newval
|= (S
<< 10) | hi
;
22793 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22794 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22795 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22799 case BFD_RELOC_THUMB_PCREL_BLX
:
22800 /* If there is a blx from a thumb state function to
22801 another thumb function flip this to a bl and warn
22805 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22806 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22807 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22809 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22810 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22811 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22813 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22814 newval
= newval
| 0x1000;
22815 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22816 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22821 goto thumb_bl_common
;
22823 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22824 /* A bl from Thumb state ISA to an internal ARM state function
22825 is converted to a blx. */
22827 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22828 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22829 && ARM_IS_FUNC (fixP
->fx_addsy
)
22830 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22832 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22833 newval
= newval
& ~0x1000;
22834 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22835 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22841 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22842 /* For a BLX instruction, make sure that the relocation is rounded up
22843 to a word boundary. This follows the semantics of the instruction
22844 which specifies that bit 1 of the target address will come from bit
22845 1 of the base address. */
22846 value
= (value
+ 3) & ~ 3;
22849 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22850 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22851 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22854 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22856 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22858 else if ((value
& ~0x1ffffff)
22859 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22861 _("Thumb2 branch out of range"));
22864 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22865 encode_thumb2_b_bl_offset (buf
, value
);
22869 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22870 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22873 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22874 encode_thumb2_b_bl_offset (buf
, value
);
22879 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22884 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22885 md_number_to_chars (buf
, value
, 2);
22889 case BFD_RELOC_ARM_TLS_CALL
:
22890 case BFD_RELOC_ARM_THM_TLS_CALL
:
22891 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22892 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22893 case BFD_RELOC_ARM_TLS_GOTDESC
:
22894 case BFD_RELOC_ARM_TLS_GD32
:
22895 case BFD_RELOC_ARM_TLS_LE32
:
22896 case BFD_RELOC_ARM_TLS_IE32
:
22897 case BFD_RELOC_ARM_TLS_LDM32
:
22898 case BFD_RELOC_ARM_TLS_LDO32
:
22899 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22902 case BFD_RELOC_ARM_GOT32
:
22903 case BFD_RELOC_ARM_GOTOFF
:
22906 case BFD_RELOC_ARM_GOT_PREL
:
22907 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22908 md_number_to_chars (buf
, value
, 4);
22911 case BFD_RELOC_ARM_TARGET2
:
22912 /* TARGET2 is not partial-inplace, so we need to write the
22913 addend here for REL targets, because it won't be written out
22914 during reloc processing later. */
22915 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22916 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22920 case BFD_RELOC_RVA
:
22922 case BFD_RELOC_ARM_TARGET1
:
22923 case BFD_RELOC_ARM_ROSEGREL32
:
22924 case BFD_RELOC_ARM_SBREL32
:
22925 case BFD_RELOC_32_PCREL
:
22927 case BFD_RELOC_32_SECREL
:
22929 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22931 /* For WinCE we only do this for pcrel fixups. */
22932 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22934 md_number_to_chars (buf
, value
, 4);
22938 case BFD_RELOC_ARM_PREL31
:
22939 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22941 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22942 if ((value
^ (value
>> 1)) & 0x40000000)
22944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22945 _("rel31 relocation overflow"));
22947 newval
|= value
& 0x7fffffff;
22948 md_number_to_chars (buf
, newval
, 4);
22953 case BFD_RELOC_ARM_CP_OFF_IMM
:
22954 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22955 if (value
< -1023 || value
> 1023 || (value
& 3))
22956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22957 _("co-processor offset out of range"));
22962 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22963 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22964 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22966 newval
= get_thumb32_insn (buf
);
22968 newval
&= 0xffffff00;
22971 newval
&= 0xff7fff00;
22972 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22974 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22975 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22976 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22978 put_thumb32_insn (buf
, newval
);
22981 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22982 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22983 if (value
< -255 || value
> 255)
22984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22985 _("co-processor offset out of range"));
22987 goto cp_off_common
;
22989 case BFD_RELOC_ARM_THUMB_OFFSET
:
22990 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22991 /* Exactly what ranges, and where the offset is inserted depends
22992 on the type of instruction, we can establish this from the
22994 switch (newval
>> 12)
22996 case 4: /* PC load. */
22997 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22998 forced to zero for these loads; md_pcrel_from has already
22999 compensated for this. */
23001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23002 _("invalid offset, target not word aligned (0x%08lX)"),
23003 (((unsigned long) fixP
->fx_frag
->fr_address
23004 + (unsigned long) fixP
->fx_where
) & ~3)
23005 + (unsigned long) value
);
23007 if (value
& ~0x3fc)
23008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23009 _("invalid offset, value too big (0x%08lX)"),
23012 newval
|= value
>> 2;
23015 case 9: /* SP load/store. */
23016 if (value
& ~0x3fc)
23017 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23018 _("invalid offset, value too big (0x%08lX)"),
23020 newval
|= value
>> 2;
23023 case 6: /* Word load/store. */
23025 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23026 _("invalid offset, value too big (0x%08lX)"),
23028 newval
|= value
<< 4; /* 6 - 2. */
23031 case 7: /* Byte load/store. */
23033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23034 _("invalid offset, value too big (0x%08lX)"),
23036 newval
|= value
<< 6;
23039 case 8: /* Halfword load/store. */
23041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23042 _("invalid offset, value too big (0x%08lX)"),
23044 newval
|= value
<< 5; /* 6 - 1. */
23048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23049 "Unable to process relocation for thumb opcode: %lx",
23050 (unsigned long) newval
);
23053 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23056 case BFD_RELOC_ARM_THUMB_ADD
:
23057 /* This is a complicated relocation, since we use it for all of
23058 the following immediate relocations:
23062 9bit ADD/SUB SP word-aligned
23063 10bit ADD PC/SP word-aligned
23065 The type of instruction being processed is encoded in the
23072 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23074 int rd
= (newval
>> 4) & 0xf;
23075 int rs
= newval
& 0xf;
23076 int subtract
= !!(newval
& 0x8000);
23078 /* Check for HI regs, only very restricted cases allowed:
23079 Adjusting SP, and using PC or SP to get an address. */
23080 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23081 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23083 _("invalid Hi register with immediate"));
23085 /* If value is negative, choose the opposite instruction. */
23089 subtract
= !subtract
;
23091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23092 _("immediate value out of range"));
23097 if (value
& ~0x1fc)
23098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23099 _("invalid immediate for stack address calculation"));
23100 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23101 newval
|= value
>> 2;
23103 else if (rs
== REG_PC
|| rs
== REG_SP
)
23105 /* PR gas/18541. If the addition is for a defined symbol
23106 within range of an ADR instruction then accept it. */
23109 && fixP
->fx_addsy
!= NULL
)
23113 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23114 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23115 || S_IS_WEAK (fixP
->fx_addsy
))
23117 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23118 _("address calculation needs a strongly defined nearby symbol"));
23122 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23124 /* Round up to the next 4-byte boundary. */
23129 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23134 _("symbol too far away"));
23144 if (subtract
|| value
& ~0x3fc)
23145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23146 _("invalid immediate for address calculation (value = 0x%08lX)"),
23147 (unsigned long) (subtract
? - value
: value
));
23148 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23150 newval
|= value
>> 2;
23155 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23156 _("immediate value out of range"));
23157 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23158 newval
|= (rd
<< 8) | value
;
23163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23164 _("immediate value out of range"));
23165 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23166 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23169 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23172 case BFD_RELOC_ARM_THUMB_IMM
:
23173 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23174 if (value
< 0 || value
> 255)
23175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23176 _("invalid immediate: %ld is out of range"),
23179 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23182 case BFD_RELOC_ARM_THUMB_SHIFT
:
23183 /* 5bit shift value (0..32). LSL cannot take 32. */
23184 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23185 temp
= newval
& 0xf800;
23186 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23187 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23188 _("invalid shift value: %ld"), (long) value
);
23189 /* Shifts of zero must be encoded as LSL. */
23191 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23192 /* Shifts of 32 are encoded as zero. */
23193 else if (value
== 32)
23195 newval
|= value
<< 6;
23196 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23199 case BFD_RELOC_VTABLE_INHERIT
:
23200 case BFD_RELOC_VTABLE_ENTRY
:
23204 case BFD_RELOC_ARM_MOVW
:
23205 case BFD_RELOC_ARM_MOVT
:
23206 case BFD_RELOC_ARM_THUMB_MOVW
:
23207 case BFD_RELOC_ARM_THUMB_MOVT
:
23208 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23210 /* REL format relocations are limited to a 16-bit addend. */
23211 if (!fixP
->fx_done
)
23213 if (value
< -0x8000 || value
> 0x7fff)
23214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23215 _("offset out of range"));
23217 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23218 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23223 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23224 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23226 newval
= get_thumb32_insn (buf
);
23227 newval
&= 0xfbf08f00;
23228 newval
|= (value
& 0xf000) << 4;
23229 newval
|= (value
& 0x0800) << 15;
23230 newval
|= (value
& 0x0700) << 4;
23231 newval
|= (value
& 0x00ff);
23232 put_thumb32_insn (buf
, newval
);
23236 newval
= md_chars_to_number (buf
, 4);
23237 newval
&= 0xfff0f000;
23238 newval
|= value
& 0x0fff;
23239 newval
|= (value
& 0xf000) << 4;
23240 md_number_to_chars (buf
, newval
, 4);
23245 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23246 case BFD_RELOC_ARM_ALU_PC_G0
:
23247 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23248 case BFD_RELOC_ARM_ALU_PC_G1
:
23249 case BFD_RELOC_ARM_ALU_PC_G2
:
23250 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23251 case BFD_RELOC_ARM_ALU_SB_G0
:
23252 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23253 case BFD_RELOC_ARM_ALU_SB_G1
:
23254 case BFD_RELOC_ARM_ALU_SB_G2
:
23255 gas_assert (!fixP
->fx_done
);
23256 if (!seg
->use_rela_p
)
23259 bfd_vma encoded_addend
;
23260 bfd_vma addend_abs
= abs (value
);
23262 /* Check that the absolute value of the addend can be
23263 expressed as an 8-bit constant plus a rotation. */
23264 encoded_addend
= encode_arm_immediate (addend_abs
);
23265 if (encoded_addend
== (unsigned int) FAIL
)
23266 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23267 _("the offset 0x%08lX is not representable"),
23268 (unsigned long) addend_abs
);
23270 /* Extract the instruction. */
23271 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23273 /* If the addend is positive, use an ADD instruction.
23274 Otherwise use a SUB. Take care not to destroy the S bit. */
23275 insn
&= 0xff1fffff;
23281 /* Place the encoded addend into the first 12 bits of the
23283 insn
&= 0xfffff000;
23284 insn
|= encoded_addend
;
23286 /* Update the instruction. */
23287 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23291 case BFD_RELOC_ARM_LDR_PC_G0
:
23292 case BFD_RELOC_ARM_LDR_PC_G1
:
23293 case BFD_RELOC_ARM_LDR_PC_G2
:
23294 case BFD_RELOC_ARM_LDR_SB_G0
:
23295 case BFD_RELOC_ARM_LDR_SB_G1
:
23296 case BFD_RELOC_ARM_LDR_SB_G2
:
23297 gas_assert (!fixP
->fx_done
);
23298 if (!seg
->use_rela_p
)
23301 bfd_vma addend_abs
= abs (value
);
23303 /* Check that the absolute value of the addend can be
23304 encoded in 12 bits. */
23305 if (addend_abs
>= 0x1000)
23306 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23307 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23308 (unsigned long) addend_abs
);
23310 /* Extract the instruction. */
23311 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23313 /* If the addend is negative, clear bit 23 of the instruction.
23314 Otherwise set it. */
23316 insn
&= ~(1 << 23);
23320 /* Place the absolute value of the addend into the first 12 bits
23321 of the instruction. */
23322 insn
&= 0xfffff000;
23323 insn
|= addend_abs
;
23325 /* Update the instruction. */
23326 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23330 case BFD_RELOC_ARM_LDRS_PC_G0
:
23331 case BFD_RELOC_ARM_LDRS_PC_G1
:
23332 case BFD_RELOC_ARM_LDRS_PC_G2
:
23333 case BFD_RELOC_ARM_LDRS_SB_G0
:
23334 case BFD_RELOC_ARM_LDRS_SB_G1
:
23335 case BFD_RELOC_ARM_LDRS_SB_G2
:
23336 gas_assert (!fixP
->fx_done
);
23337 if (!seg
->use_rela_p
)
23340 bfd_vma addend_abs
= abs (value
);
23342 /* Check that the absolute value of the addend can be
23343 encoded in 8 bits. */
23344 if (addend_abs
>= 0x100)
23345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23346 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23347 (unsigned long) addend_abs
);
23349 /* Extract the instruction. */
23350 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23352 /* If the addend is negative, clear bit 23 of the instruction.
23353 Otherwise set it. */
23355 insn
&= ~(1 << 23);
23359 /* Place the first four bits of the absolute value of the addend
23360 into the first 4 bits of the instruction, and the remaining
23361 four into bits 8 .. 11. */
23362 insn
&= 0xfffff0f0;
23363 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23365 /* Update the instruction. */
23366 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23370 case BFD_RELOC_ARM_LDC_PC_G0
:
23371 case BFD_RELOC_ARM_LDC_PC_G1
:
23372 case BFD_RELOC_ARM_LDC_PC_G2
:
23373 case BFD_RELOC_ARM_LDC_SB_G0
:
23374 case BFD_RELOC_ARM_LDC_SB_G1
:
23375 case BFD_RELOC_ARM_LDC_SB_G2
:
23376 gas_assert (!fixP
->fx_done
);
23377 if (!seg
->use_rela_p
)
23380 bfd_vma addend_abs
= abs (value
);
23382 /* Check that the absolute value of the addend is a multiple of
23383 four and, when divided by four, fits in 8 bits. */
23384 if (addend_abs
& 0x3)
23385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23386 _("bad offset 0x%08lX (must be word-aligned)"),
23387 (unsigned long) addend_abs
);
23389 if ((addend_abs
>> 2) > 0xff)
23390 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23391 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23392 (unsigned long) addend_abs
);
23394 /* Extract the instruction. */
23395 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23397 /* If the addend is negative, clear bit 23 of the instruction.
23398 Otherwise set it. */
23400 insn
&= ~(1 << 23);
23404 /* Place the addend (divided by four) into the first eight
23405 bits of the instruction. */
23406 insn
&= 0xfffffff0;
23407 insn
|= addend_abs
>> 2;
23409 /* Update the instruction. */
23410 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23414 case BFD_RELOC_ARM_V4BX
:
23415 /* This will need to go in the object file. */
23419 case BFD_RELOC_UNUSED
:
23421 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23422 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
23426 /* Translate internal representation of relocation info to BFD target
23430 tc_gen_reloc (asection
*section
, fixS
*fixp
)
23433 bfd_reloc_code_real_type code
;
23435 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
23437 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
23438 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
23439 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
23441 if (fixp
->fx_pcrel
)
23443 if (section
->use_rela_p
)
23444 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
23446 fixp
->fx_offset
= reloc
->address
;
23448 reloc
->addend
= fixp
->fx_offset
;
23450 switch (fixp
->fx_r_type
)
23453 if (fixp
->fx_pcrel
)
23455 code
= BFD_RELOC_8_PCREL
;
23460 if (fixp
->fx_pcrel
)
23462 code
= BFD_RELOC_16_PCREL
;
23467 if (fixp
->fx_pcrel
)
23469 code
= BFD_RELOC_32_PCREL
;
23473 case BFD_RELOC_ARM_MOVW
:
23474 if (fixp
->fx_pcrel
)
23476 code
= BFD_RELOC_ARM_MOVW_PCREL
;
23480 case BFD_RELOC_ARM_MOVT
:
23481 if (fixp
->fx_pcrel
)
23483 code
= BFD_RELOC_ARM_MOVT_PCREL
;
23487 case BFD_RELOC_ARM_THUMB_MOVW
:
23488 if (fixp
->fx_pcrel
)
23490 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
23494 case BFD_RELOC_ARM_THUMB_MOVT
:
23495 if (fixp
->fx_pcrel
)
23497 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
23501 case BFD_RELOC_NONE
:
23502 case BFD_RELOC_ARM_PCREL_BRANCH
:
23503 case BFD_RELOC_ARM_PCREL_BLX
:
23504 case BFD_RELOC_RVA
:
23505 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
23506 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
23507 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
23508 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23509 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23510 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23511 case BFD_RELOC_VTABLE_ENTRY
:
23512 case BFD_RELOC_VTABLE_INHERIT
:
23514 case BFD_RELOC_32_SECREL
:
23516 code
= fixp
->fx_r_type
;
23519 case BFD_RELOC_THUMB_PCREL_BLX
:
23521 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23522 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23525 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23528 case BFD_RELOC_ARM_LITERAL
:
23529 case BFD_RELOC_ARM_HWLITERAL
:
23530 /* If this is called then the a literal has
23531 been referenced across a section boundary. */
23532 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23533 _("literal referenced across section boundary"));
23537 case BFD_RELOC_ARM_TLS_CALL
:
23538 case BFD_RELOC_ARM_THM_TLS_CALL
:
23539 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23540 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23541 case BFD_RELOC_ARM_GOT32
:
23542 case BFD_RELOC_ARM_GOTOFF
:
23543 case BFD_RELOC_ARM_GOT_PREL
:
23544 case BFD_RELOC_ARM_PLT32
:
23545 case BFD_RELOC_ARM_TARGET1
:
23546 case BFD_RELOC_ARM_ROSEGREL32
:
23547 case BFD_RELOC_ARM_SBREL32
:
23548 case BFD_RELOC_ARM_PREL31
:
23549 case BFD_RELOC_ARM_TARGET2
:
23550 case BFD_RELOC_ARM_TLS_LDO32
:
23551 case BFD_RELOC_ARM_PCREL_CALL
:
23552 case BFD_RELOC_ARM_PCREL_JUMP
:
23553 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23554 case BFD_RELOC_ARM_ALU_PC_G0
:
23555 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23556 case BFD_RELOC_ARM_ALU_PC_G1
:
23557 case BFD_RELOC_ARM_ALU_PC_G2
:
23558 case BFD_RELOC_ARM_LDR_PC_G0
:
23559 case BFD_RELOC_ARM_LDR_PC_G1
:
23560 case BFD_RELOC_ARM_LDR_PC_G2
:
23561 case BFD_RELOC_ARM_LDRS_PC_G0
:
23562 case BFD_RELOC_ARM_LDRS_PC_G1
:
23563 case BFD_RELOC_ARM_LDRS_PC_G2
:
23564 case BFD_RELOC_ARM_LDC_PC_G0
:
23565 case BFD_RELOC_ARM_LDC_PC_G1
:
23566 case BFD_RELOC_ARM_LDC_PC_G2
:
23567 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23568 case BFD_RELOC_ARM_ALU_SB_G0
:
23569 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23570 case BFD_RELOC_ARM_ALU_SB_G1
:
23571 case BFD_RELOC_ARM_ALU_SB_G2
:
23572 case BFD_RELOC_ARM_LDR_SB_G0
:
23573 case BFD_RELOC_ARM_LDR_SB_G1
:
23574 case BFD_RELOC_ARM_LDR_SB_G2
:
23575 case BFD_RELOC_ARM_LDRS_SB_G0
:
23576 case BFD_RELOC_ARM_LDRS_SB_G1
:
23577 case BFD_RELOC_ARM_LDRS_SB_G2
:
23578 case BFD_RELOC_ARM_LDC_SB_G0
:
23579 case BFD_RELOC_ARM_LDC_SB_G1
:
23580 case BFD_RELOC_ARM_LDC_SB_G2
:
23581 case BFD_RELOC_ARM_V4BX
:
23582 code
= fixp
->fx_r_type
;
23585 case BFD_RELOC_ARM_TLS_GOTDESC
:
23586 case BFD_RELOC_ARM_TLS_GD32
:
23587 case BFD_RELOC_ARM_TLS_LE32
:
23588 case BFD_RELOC_ARM_TLS_IE32
:
23589 case BFD_RELOC_ARM_TLS_LDM32
:
23590 /* BFD will include the symbol's address in the addend.
23591 But we don't want that, so subtract it out again here. */
23592 if (!S_IS_COMMON (fixp
->fx_addsy
))
23593 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23594 code
= fixp
->fx_r_type
;
23598 case BFD_RELOC_ARM_IMMEDIATE
:
23599 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23600 _("internal relocation (type: IMMEDIATE) not fixed up"));
23603 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23604 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23605 _("ADRL used for a symbol not defined in the same file"));
23608 case BFD_RELOC_ARM_OFFSET_IMM
:
23609 if (section
->use_rela_p
)
23611 code
= fixp
->fx_r_type
;
23615 if (fixp
->fx_addsy
!= NULL
23616 && !S_IS_DEFINED (fixp
->fx_addsy
)
23617 && S_IS_LOCAL (fixp
->fx_addsy
))
23619 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23620 _("undefined local label `%s'"),
23621 S_GET_NAME (fixp
->fx_addsy
));
23625 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23626 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23633 switch (fixp
->fx_r_type
)
23635 case BFD_RELOC_NONE
: type
= "NONE"; break;
23636 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23637 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23638 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23639 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23640 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23641 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23642 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23643 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23644 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23645 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23646 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23647 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23648 default: type
= _("<unknown>"); break;
23650 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23651 _("cannot represent %s relocation in this object file format"),
23658 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23660 && fixp
->fx_addsy
== GOT_symbol
)
23662 code
= BFD_RELOC_ARM_GOTPC
;
23663 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23667 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23669 if (reloc
->howto
== NULL
)
23671 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23672 _("cannot represent %s relocation in this object file format"),
23673 bfd_get_reloc_code_name (code
));
23677 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23678 vtable entry to be used in the relocation's section offset. */
23679 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23680 reloc
->address
= fixp
->fx_offset
;
23685 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23688 cons_fix_new_arm (fragS
* frag
,
23692 bfd_reloc_code_real_type reloc
)
23697 FIXME: @@ Should look at CPU word size. */
23701 reloc
= BFD_RELOC_8
;
23704 reloc
= BFD_RELOC_16
;
23708 reloc
= BFD_RELOC_32
;
23711 reloc
= BFD_RELOC_64
;
23716 if (exp
->X_op
== O_secrel
)
23718 exp
->X_op
= O_symbol
;
23719 reloc
= BFD_RELOC_32_SECREL
;
23723 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23726 #if defined (OBJ_COFF)
23728 arm_validate_fix (fixS
* fixP
)
23730 /* If the destination of the branch is a defined symbol which does not have
23731 the THUMB_FUNC attribute, then we must be calling a function which has
23732 the (interfacearm) attribute. We look for the Thumb entry point to that
23733 function and change the branch to refer to that function instead. */
23734 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23735 && fixP
->fx_addsy
!= NULL
23736 && S_IS_DEFINED (fixP
->fx_addsy
)
23737 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23739 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23746 arm_force_relocation (struct fix
* fixp
)
23748 #if defined (OBJ_COFF) && defined (TE_PE)
23749 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23753 /* In case we have a call or a branch to a function in ARM ISA mode from
23754 a thumb function or vice-versa force the relocation. These relocations
23755 are cleared off for some cores that might have blx and simple transformations
23759 switch (fixp
->fx_r_type
)
23761 case BFD_RELOC_ARM_PCREL_JUMP
:
23762 case BFD_RELOC_ARM_PCREL_CALL
:
23763 case BFD_RELOC_THUMB_PCREL_BLX
:
23764 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23768 case BFD_RELOC_ARM_PCREL_BLX
:
23769 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23770 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23771 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23772 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23781 /* Resolve these relocations even if the symbol is extern or weak.
23782 Technically this is probably wrong due to symbol preemption.
23783 In practice these relocations do not have enough range to be useful
23784 at dynamic link time, and some code (e.g. in the Linux kernel)
23785 expects these references to be resolved. */
23786 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23787 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23788 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23789 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23790 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23791 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23792 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23793 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23794 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23795 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23796 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23797 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23798 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23799 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23802 /* Always leave these relocations for the linker. */
23803 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23804 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23805 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23808 /* Always generate relocations against function symbols. */
23809 if (fixp
->fx_r_type
== BFD_RELOC_32
23811 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23814 return generic_force_reloc (fixp
);
23817 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23818 /* Relocations against function names must be left unadjusted,
23819 so that the linker can use this information to generate interworking
23820 stubs. The MIPS version of this function
23821 also prevents relocations that are mips-16 specific, but I do not
23822 know why it does this.
23825 There is one other problem that ought to be addressed here, but
23826 which currently is not: Taking the address of a label (rather
23827 than a function) and then later jumping to that address. Such
23828 addresses also ought to have their bottom bit set (assuming that
23829 they reside in Thumb code), but at the moment they will not. */
23832 arm_fix_adjustable (fixS
* fixP
)
23834 if (fixP
->fx_addsy
== NULL
)
23837 /* Preserve relocations against symbols with function type. */
23838 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23841 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23842 && fixP
->fx_subsy
== NULL
)
23845 /* We need the symbol name for the VTABLE entries. */
23846 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23847 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23850 /* Don't allow symbols to be discarded on GOT related relocs. */
23851 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23852 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23853 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23854 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23855 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23856 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23857 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23858 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23859 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23860 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23861 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23862 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23863 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23864 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23867 /* Similarly for group relocations. */
23868 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23869 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23870 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23873 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23874 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23875 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23876 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23877 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23878 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23879 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23880 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23881 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23886 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23891 elf32_arm_target_format (void)
23894 return (target_big_endian
23895 ? "elf32-bigarm-symbian"
23896 : "elf32-littlearm-symbian");
23897 #elif defined (TE_VXWORKS)
23898 return (target_big_endian
23899 ? "elf32-bigarm-vxworks"
23900 : "elf32-littlearm-vxworks");
23901 #elif defined (TE_NACL)
23902 return (target_big_endian
23903 ? "elf32-bigarm-nacl"
23904 : "elf32-littlearm-nacl");
23906 if (target_big_endian
)
23907 return "elf32-bigarm";
23909 return "elf32-littlearm";
23914 armelf_frob_symbol (symbolS
* symp
,
23917 elf_frob_symbol (symp
, puntp
);
23921 /* MD interface: Finalization. */
23926 literal_pool
* pool
;
23928 /* Ensure that all the IT blocks are properly closed. */
23929 check_it_blocks_finished ();
23931 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23933 /* Put it at the end of the relevant section. */
23934 subseg_set (pool
->section
, pool
->sub_section
);
23936 arm_elf_change_section ();
23943 /* Remove any excess mapping symbols generated for alignment frags in
23944 SEC. We may have created a mapping symbol before a zero byte
23945 alignment; remove it if there's a mapping symbol after the
23948 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23949 void *dummy ATTRIBUTE_UNUSED
)
23951 segment_info_type
*seginfo
= seg_info (sec
);
23954 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23957 for (fragp
= seginfo
->frchainP
->frch_root
;
23959 fragp
= fragp
->fr_next
)
23961 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23962 fragS
*next
= fragp
->fr_next
;
23964 /* Variable-sized frags have been converted to fixed size by
23965 this point. But if this was variable-sized to start with,
23966 there will be a fixed-size frag after it. So don't handle
23968 if (sym
== NULL
|| next
== NULL
)
23971 if (S_GET_VALUE (sym
) < next
->fr_address
)
23972 /* Not at the end of this frag. */
23974 know (S_GET_VALUE (sym
) == next
->fr_address
);
23978 if (next
->tc_frag_data
.first_map
!= NULL
)
23980 /* Next frag starts with a mapping symbol. Discard this
23982 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23986 if (next
->fr_next
== NULL
)
23988 /* This mapping symbol is at the end of the section. Discard
23990 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23991 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23995 /* As long as we have empty frags without any mapping symbols,
23997 /* If the next frag is non-empty and does not start with a
23998 mapping symbol, then this mapping symbol is required. */
23999 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24002 next
= next
->fr_next
;
24004 while (next
!= NULL
);
24009 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24013 arm_adjust_symtab (void)
24018 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24020 if (ARM_IS_THUMB (sym
))
24022 if (THUMB_IS_FUNC (sym
))
24024 /* Mark the symbol as a Thumb function. */
24025 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24026 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24027 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24029 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24030 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24032 as_bad (_("%s: unexpected function type: %d"),
24033 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24035 else switch (S_GET_STORAGE_CLASS (sym
))
24038 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24041 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24044 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24052 if (ARM_IS_INTERWORK (sym
))
24053 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24060 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24062 if (ARM_IS_THUMB (sym
))
24064 elf_symbol_type
* elf_sym
;
24066 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24067 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24069 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24070 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24072 /* If it's a .thumb_func, declare it as so,
24073 otherwise tag label as .code 16. */
24074 if (THUMB_IS_FUNC (sym
))
24075 elf_sym
->internal_elf_sym
.st_target_internal
24076 = ST_BRANCH_TO_THUMB
;
24077 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24078 elf_sym
->internal_elf_sym
.st_info
=
24079 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24084 /* Remove any overlapping mapping symbols generated by alignment frags. */
24085 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24086 /* Now do generic ELF adjustments. */
24087 elf_adjust_symtab ();
24091 /* MD interface: Initialization. */
24094 set_constant_flonums (void)
24098 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24099 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24103 /* Auto-select Thumb mode if it's the only available instruction set for the
24104 given architecture. */
24107 autoselect_thumb_from_cpu_variant (void)
24109 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24110 opcode_select (16);
24119 if ( (arm_ops_hsh
= hash_new ()) == NULL
24120 || (arm_cond_hsh
= hash_new ()) == NULL
24121 || (arm_shift_hsh
= hash_new ()) == NULL
24122 || (arm_psr_hsh
= hash_new ()) == NULL
24123 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24124 || (arm_reg_hsh
= hash_new ()) == NULL
24125 || (arm_reloc_hsh
= hash_new ()) == NULL
24126 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24127 as_fatal (_("virtual memory exhausted"));
24129 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24130 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24131 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24132 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24133 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24134 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24135 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24136 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24137 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24138 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24139 (void *) (v7m_psrs
+ i
));
24140 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24141 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24143 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24145 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24146 (void *) (barrier_opt_names
+ i
));
24148 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24150 struct reloc_entry
* entry
= reloc_names
+ i
;
24152 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24153 /* This makes encode_branch() use the EABI versions of this relocation. */
24154 entry
->reloc
= BFD_RELOC_UNUSED
;
24156 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24160 set_constant_flonums ();
24162 /* Set the cpu variant based on the command-line options. We prefer
24163 -mcpu= over -march= if both are set (as for GCC); and we prefer
24164 -mfpu= over any other way of setting the floating point unit.
24165 Use of legacy options with new options are faulted. */
24168 if (mcpu_cpu_opt
|| march_cpu_opt
)
24169 as_bad (_("use of old and new-style options to set CPU type"));
24171 mcpu_cpu_opt
= legacy_cpu
;
24173 else if (!mcpu_cpu_opt
)
24174 mcpu_cpu_opt
= march_cpu_opt
;
24179 as_bad (_("use of old and new-style options to set FPU type"));
24181 mfpu_opt
= legacy_fpu
;
24183 else if (!mfpu_opt
)
24185 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24186 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24187 /* Some environments specify a default FPU. If they don't, infer it
24188 from the processor. */
24190 mfpu_opt
= mcpu_fpu_opt
;
24192 mfpu_opt
= march_fpu_opt
;
24194 mfpu_opt
= &fpu_default
;
24200 if (mcpu_cpu_opt
!= NULL
)
24201 mfpu_opt
= &fpu_default
;
24202 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24203 mfpu_opt
= &fpu_arch_vfp_v2
;
24205 mfpu_opt
= &fpu_arch_fpa
;
24211 mcpu_cpu_opt
= &cpu_default
;
24212 selected_cpu
= cpu_default
;
24214 else if (no_cpu_selected ())
24215 selected_cpu
= cpu_default
;
24218 selected_cpu
= *mcpu_cpu_opt
;
24220 mcpu_cpu_opt
= &arm_arch_any
;
24223 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24225 autoselect_thumb_from_cpu_variant ();
24227 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24229 #if defined OBJ_COFF || defined OBJ_ELF
24231 unsigned int flags
= 0;
24233 #if defined OBJ_ELF
24234 flags
= meabi_flags
;
24236 switch (meabi_flags
)
24238 case EF_ARM_EABI_UNKNOWN
:
24240 /* Set the flags in the private structure. */
24241 if (uses_apcs_26
) flags
|= F_APCS26
;
24242 if (support_interwork
) flags
|= F_INTERWORK
;
24243 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24244 if (pic_code
) flags
|= F_PIC
;
24245 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24246 flags
|= F_SOFT_FLOAT
;
24248 switch (mfloat_abi_opt
)
24250 case ARM_FLOAT_ABI_SOFT
:
24251 case ARM_FLOAT_ABI_SOFTFP
:
24252 flags
|= F_SOFT_FLOAT
;
24255 case ARM_FLOAT_ABI_HARD
:
24256 if (flags
& F_SOFT_FLOAT
)
24257 as_bad (_("hard-float conflicts with specified fpu"));
24261 /* Using pure-endian doubles (even if soft-float). */
24262 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24263 flags
|= F_VFP_FLOAT
;
24265 #if defined OBJ_ELF
24266 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24267 flags
|= EF_ARM_MAVERICK_FLOAT
;
24270 case EF_ARM_EABI_VER4
:
24271 case EF_ARM_EABI_VER5
:
24272 /* No additional flags to set. */
24279 bfd_set_private_flags (stdoutput
, flags
);
24281 /* We have run out flags in the COFF header to encode the
24282 status of ATPCS support, so instead we create a dummy,
24283 empty, debug section called .arm.atpcs. */
24288 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24292 bfd_set_section_flags
24293 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24294 bfd_set_section_size (stdoutput
, sec
, 0);
24295 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24301 /* Record the CPU type as well. */
24302 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24303 mach
= bfd_mach_arm_iWMMXt2
;
24304 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24305 mach
= bfd_mach_arm_iWMMXt
;
24306 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24307 mach
= bfd_mach_arm_XScale
;
24308 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24309 mach
= bfd_mach_arm_ep9312
;
24310 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24311 mach
= bfd_mach_arm_5TE
;
24312 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24314 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24315 mach
= bfd_mach_arm_5T
;
24317 mach
= bfd_mach_arm_5
;
24319 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24321 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24322 mach
= bfd_mach_arm_4T
;
24324 mach
= bfd_mach_arm_4
;
24326 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24327 mach
= bfd_mach_arm_3M
;
24328 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24329 mach
= bfd_mach_arm_3
;
24330 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24331 mach
= bfd_mach_arm_2a
;
24332 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24333 mach
= bfd_mach_arm_2
;
24335 mach
= bfd_mach_arm_unknown
;
24337 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24340 /* Command line processing. */
24343 Invocation line includes a switch not recognized by the base assembler.
24344 See if it's a processor-specific option.
24346 This routine is somewhat complicated by the need for backwards
24347 compatibility (since older releases of gcc can't be changed).
24348 The new options try to make the interface as compatible as
24351 New options (supported) are:
24353 -mcpu=<cpu name> Assemble for selected processor
24354 -march=<architecture name> Assemble for selected architecture
24355 -mfpu=<fpu architecture> Assemble for selected FPU.
24356 -EB/-mbig-endian Big-endian
24357 -EL/-mlittle-endian Little-endian
24358 -k Generate PIC code
24359 -mthumb Start in Thumb mode
24360 -mthumb-interwork Code supports ARM/Thumb interworking
24362 -m[no-]warn-deprecated Warn about deprecated features
24363 -m[no-]warn-syms Warn when symbols match instructions
24365 For now we will also provide support for:
24367 -mapcs-32 32-bit Program counter
24368 -mapcs-26 26-bit Program counter
24369 -macps-float Floats passed in FP registers
24370 -mapcs-reentrant Reentrant code
24372 (sometime these will probably be replaced with -mapcs=<list of options>
24373 and -matpcs=<list of options>)
24375 The remaining options are only supported for back-wards compatibility.
24376 Cpu variants, the arm part is optional:
24377 -m[arm]1 Currently not supported.
24378 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24379 -m[arm]3 Arm 3 processor
24380 -m[arm]6[xx], Arm 6 processors
24381 -m[arm]7[xx][t][[d]m] Arm 7 processors
24382 -m[arm]8[10] Arm 8 processors
24383 -m[arm]9[20][tdmi] Arm 9 processors
24384 -mstrongarm[110[0]] StrongARM processors
24385 -mxscale XScale processors
24386 -m[arm]v[2345[t[e]]] Arm architectures
24387 -mall All (except the ARM1)
24389 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24390 -mfpe-old (No float load/store multiples)
24391 -mvfpxd VFP Single precision
24393 -mno-fpu Disable all floating point instructions
24395 The following CPU names are recognized:
24396 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24397 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24398 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24399 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24400 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24401 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24402 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24406 const char * md_shortopts
= "m:k";
24408 #ifdef ARM_BI_ENDIAN
24409 #define OPTION_EB (OPTION_MD_BASE + 0)
24410 #define OPTION_EL (OPTION_MD_BASE + 1)
24412 #if TARGET_BYTES_BIG_ENDIAN
24413 #define OPTION_EB (OPTION_MD_BASE + 0)
24415 #define OPTION_EL (OPTION_MD_BASE + 1)
24418 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24420 struct option md_longopts
[] =
24423 {"EB", no_argument
, NULL
, OPTION_EB
},
24426 {"EL", no_argument
, NULL
, OPTION_EL
},
24428 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
24429 {NULL
, no_argument
, NULL
, 0}
24433 size_t md_longopts_size
= sizeof (md_longopts
);
24435 struct arm_option_table
24437 char *option
; /* Option name to match. */
24438 char *help
; /* Help information. */
24439 int *var
; /* Variable to change. */
24440 int value
; /* What to change it to. */
24441 char *deprecated
; /* If non-null, print this message. */
24444 struct arm_option_table arm_opts
[] =
24446 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
24447 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
24448 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24449 &support_interwork
, 1, NULL
},
24450 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
24451 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
24452 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
24454 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
24455 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
24456 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
24457 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
24460 /* These are recognized by the assembler, but have no affect on code. */
24461 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
24462 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
24464 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
24465 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24466 &warn_on_deprecated
, 0, NULL
},
24467 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
24468 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
24469 {NULL
, NULL
, NULL
, 0, NULL
}
24472 struct arm_legacy_option_table
24474 char *option
; /* Option name to match. */
24475 const arm_feature_set
**var
; /* Variable to change. */
24476 const arm_feature_set value
; /* What to change it to. */
24477 char *deprecated
; /* If non-null, print this message. */
24480 const struct arm_legacy_option_table arm_legacy_opts
[] =
24482 /* DON'T add any new processors to this list -- we want the whole list
24483 to go away... Add them to the processors table instead. */
24484 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24485 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
24486 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24487 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
24488 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24489 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
24490 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24491 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
24492 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24493 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
24494 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24495 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
24496 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24497 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
24498 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24499 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
24500 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24501 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
24502 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24503 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
24504 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24505 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
24506 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24507 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
24508 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24509 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
24510 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24511 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
24512 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24513 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
24514 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24515 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
24516 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24517 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
24518 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24519 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
24520 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24521 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
24522 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24523 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
24524 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24525 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
24526 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24527 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
24528 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24529 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
24530 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24531 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24532 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24533 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24534 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24535 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24536 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24537 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24538 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24539 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24540 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24541 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24542 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24543 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24544 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24545 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24546 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24547 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24548 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24549 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24550 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24551 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24552 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24553 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24554 N_("use -mcpu=strongarm110")},
24555 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24556 N_("use -mcpu=strongarm1100")},
24557 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24558 N_("use -mcpu=strongarm1110")},
24559 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24560 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24561 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24563 /* Architecture variants -- don't add any more to this list either. */
24564 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24565 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24566 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24567 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24568 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24569 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24570 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24571 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24572 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24573 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24574 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24575 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24576 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24577 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24578 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24579 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24580 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24581 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24583 /* Floating point variants -- don't add any more to this list either. */
24584 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24585 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24586 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24587 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24588 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24590 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24593 struct arm_cpu_option_table
24597 const arm_feature_set value
;
24598 /* For some CPUs we assume an FPU unless the user explicitly sets
24600 const arm_feature_set default_fpu
;
24601 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24603 const char *canonical_name
;
24606 /* This list should, at a minimum, contain all the cpu names
24607 recognized by GCC. */
24608 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24609 static const struct arm_cpu_option_table arm_cpus
[] =
24611 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24612 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24613 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24614 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24615 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24616 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24617 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24618 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24619 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24620 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24621 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24622 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24623 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24624 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24625 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24626 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24627 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24628 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24629 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24630 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24631 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24632 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24633 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24634 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24635 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24636 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24637 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24638 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24639 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24640 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24641 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24642 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24643 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24644 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24645 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24646 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24647 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24648 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24649 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24650 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24651 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24652 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24653 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24654 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24655 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24656 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24657 /* For V5 or later processors we default to using VFP; but the user
24658 should really set the FPU type explicitly. */
24659 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24660 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24661 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24662 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24663 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24664 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24665 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24666 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24667 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24668 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24669 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24670 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24671 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24672 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24673 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24674 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24675 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24676 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24677 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24678 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24680 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24681 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24682 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24683 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24684 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24685 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24686 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24687 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24688 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24690 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24691 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24692 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24693 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24694 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24695 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
24696 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
24697 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24698 FPU_NONE
, "Cortex-A5"),
24699 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24701 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24702 ARM_FEATURE_COPROC (FPU_VFP_V3
24703 | FPU_NEON_EXT_V1
),
24705 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24706 ARM_FEATURE_COPROC (FPU_VFP_V3
24707 | FPU_NEON_EXT_V1
),
24709 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24711 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24713 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24715 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24717 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24719 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24721 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24723 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24724 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24726 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24727 FPU_NONE
, "Cortex-R5"),
24728 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24729 FPU_ARCH_VFP_V3D16
,
24731 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
24732 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24733 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24734 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24735 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24736 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24737 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24740 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24744 /* ??? XSCALE is really an architecture. */
24745 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24746 /* ??? iwmmxt is not a processor. */
24747 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24748 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24749 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24751 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24752 FPU_ARCH_MAVERICK
, "ARM920T"),
24753 /* Marvell processors. */
24754 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24756 FPU_ARCH_VFP_V3D16
, NULL
),
24757 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A
| ARM_EXT_MP
24759 FPU_ARCH_NEON_VFP_V4
, NULL
),
24760 /* APM X-Gene family. */
24761 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24763 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24766 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24770 struct arm_arch_option_table
24774 const arm_feature_set value
;
24775 const arm_feature_set default_fpu
;
24778 /* This list should, at a minimum, contain all the architecture names
24779 recognized by GCC. */
24780 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24781 static const struct arm_arch_option_table arm_archs
[] =
24783 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24784 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24785 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24786 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24787 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24788 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24789 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24790 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24791 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24792 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24793 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24794 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24795 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24796 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24797 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24798 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24799 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24800 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24801 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24802 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24803 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24804 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
24805 kept to preserve existing behaviour. */
24806 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24807 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
24808 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24809 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24810 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24811 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
24812 kept to preserve existing behaviour. */
24813 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24814 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
24815 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24816 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24817 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24818 /* The official spelling of the ARMv7 profile variants is the dashed form.
24819 Accept the non-dashed form for compatibility with old toolchains. */
24820 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24821 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24822 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24823 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24824 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24825 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24826 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24827 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24828 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24829 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
24830 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
24831 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24832 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24833 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24834 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24836 #undef ARM_ARCH_OPT
24838 /* ISA extensions in the co-processor and main instruction set space. */
24839 struct arm_option_extension_value_table
24843 const arm_feature_set merge_value
;
24844 const arm_feature_set clear_value
;
24845 const arm_feature_set allowed_archs
;
24848 /* The following table must be in alphabetical order with a NULL last entry.
24850 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24851 static const struct arm_option_extension_value_table arm_extensions
[] =
24853 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
24854 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24855 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24856 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
24857 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24858 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
24859 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24860 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24861 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
24862 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24863 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
24864 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
24865 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
24866 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
24867 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
24868 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
24869 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24870 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
24871 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
24872 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24873 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
24874 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24875 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24876 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
24877 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
24878 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
24879 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
24880 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24881 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24882 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
24883 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
24884 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
24886 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
24887 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
24888 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8
,
24889 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
24890 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
24891 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
24892 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
24893 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24897 /* ISA floating-point and Advanced SIMD extensions. */
24898 struct arm_option_fpu_value_table
24901 const arm_feature_set value
;
24904 /* This list should, at a minimum, contain all the fpu names
24905 recognized by GCC. */
24906 static const struct arm_option_fpu_value_table arm_fpus
[] =
24908 {"softfpa", FPU_NONE
},
24909 {"fpe", FPU_ARCH_FPE
},
24910 {"fpe2", FPU_ARCH_FPE
},
24911 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24912 {"fpa", FPU_ARCH_FPA
},
24913 {"fpa10", FPU_ARCH_FPA
},
24914 {"fpa11", FPU_ARCH_FPA
},
24915 {"arm7500fe", FPU_ARCH_FPA
},
24916 {"softvfp", FPU_ARCH_VFP
},
24917 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24918 {"vfp", FPU_ARCH_VFP_V2
},
24919 {"vfp9", FPU_ARCH_VFP_V2
},
24920 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24921 {"vfp10", FPU_ARCH_VFP_V2
},
24922 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24923 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24924 {"vfpv2", FPU_ARCH_VFP_V2
},
24925 {"vfpv3", FPU_ARCH_VFP_V3
},
24926 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24927 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24928 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24929 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24930 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24931 {"arm1020t", FPU_ARCH_VFP_V1
},
24932 {"arm1020e", FPU_ARCH_VFP_V2
},
24933 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24934 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24935 {"maverick", FPU_ARCH_MAVERICK
},
24936 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24937 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24938 {"vfpv4", FPU_ARCH_VFP_V4
},
24939 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24940 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24941 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
24942 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
24943 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24944 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24945 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24946 {"crypto-neon-fp-armv8",
24947 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24948 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
24949 {"crypto-neon-fp-armv8.1",
24950 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
24951 {NULL
, ARM_ARCH_NONE
}
24954 struct arm_option_value_table
24960 static const struct arm_option_value_table arm_float_abis
[] =
24962 {"hard", ARM_FLOAT_ABI_HARD
},
24963 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24964 {"soft", ARM_FLOAT_ABI_SOFT
},
24969 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24970 static const struct arm_option_value_table arm_eabis
[] =
24972 {"gnu", EF_ARM_EABI_UNKNOWN
},
24973 {"4", EF_ARM_EABI_VER4
},
24974 {"5", EF_ARM_EABI_VER5
},
24979 struct arm_long_option_table
24981 char * option
; /* Substring to match. */
24982 char * help
; /* Help information. */
24983 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24984 char * deprecated
; /* If non-null, print this message. */
24988 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24990 arm_feature_set
*ext_set
= (arm_feature_set
*)
24991 xmalloc (sizeof (arm_feature_set
));
24993 /* We insist on extensions being specified in alphabetical order, and with
24994 extensions being added before being removed. We achieve this by having
24995 the global ARM_EXTENSIONS table in alphabetical order, and using the
24996 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24997 or removing it (0) and only allowing it to change in the order
24999 const struct arm_option_extension_value_table
* opt
= NULL
;
25000 int adding_value
= -1;
25002 /* Copy the feature set, so that we can modify it. */
25003 *ext_set
= **opt_p
;
25006 while (str
!= NULL
&& *str
!= 0)
25013 as_bad (_("invalid architectural extension"));
25018 ext
= strchr (str
, '+');
25023 len
= strlen (str
);
25025 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25027 if (adding_value
!= 0)
25030 opt
= arm_extensions
;
25038 if (adding_value
== -1)
25041 opt
= arm_extensions
;
25043 else if (adding_value
!= 1)
25045 as_bad (_("must specify extensions to add before specifying "
25046 "those to remove"));
25053 as_bad (_("missing architectural extension"));
25057 gas_assert (adding_value
!= -1);
25058 gas_assert (opt
!= NULL
);
25060 /* Scan over the options table trying to find an exact match. */
25061 for (; opt
->name
!= NULL
; opt
++)
25062 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25064 /* Check we can apply the extension to this architecture. */
25065 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25067 as_bad (_("extension does not apply to the base architecture"));
25071 /* Add or remove the extension. */
25073 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25075 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25080 if (opt
->name
== NULL
)
25082 /* Did we fail to find an extension because it wasn't specified in
25083 alphabetical order, or because it does not exist? */
25085 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25086 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25089 if (opt
->name
== NULL
)
25090 as_bad (_("unknown architectural extension `%s'"), str
);
25092 as_bad (_("architectural extensions must be specified in "
25093 "alphabetical order"));
25099 /* We should skip the extension we've just matched the next time
25111 arm_parse_cpu (char *str
)
25113 const struct arm_cpu_option_table
*opt
;
25114 char *ext
= strchr (str
, '+');
25120 len
= strlen (str
);
25124 as_bad (_("missing cpu name `%s'"), str
);
25128 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25129 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25131 mcpu_cpu_opt
= &opt
->value
;
25132 mcpu_fpu_opt
= &opt
->default_fpu
;
25133 if (opt
->canonical_name
)
25135 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25136 strcpy (selected_cpu_name
, opt
->canonical_name
);
25142 if (len
>= sizeof selected_cpu_name
)
25143 len
= (sizeof selected_cpu_name
) - 1;
25145 for (i
= 0; i
< len
; i
++)
25146 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25147 selected_cpu_name
[i
] = 0;
25151 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25156 as_bad (_("unknown cpu `%s'"), str
);
25161 arm_parse_arch (char *str
)
25163 const struct arm_arch_option_table
*opt
;
25164 char *ext
= strchr (str
, '+');
25170 len
= strlen (str
);
25174 as_bad (_("missing architecture name `%s'"), str
);
25178 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25179 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25181 march_cpu_opt
= &opt
->value
;
25182 march_fpu_opt
= &opt
->default_fpu
;
25183 strcpy (selected_cpu_name
, opt
->name
);
25186 return arm_parse_extension (ext
, &march_cpu_opt
);
25191 as_bad (_("unknown architecture `%s'\n"), str
);
25196 arm_parse_fpu (char * str
)
25198 const struct arm_option_fpu_value_table
* opt
;
25200 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25201 if (streq (opt
->name
, str
))
25203 mfpu_opt
= &opt
->value
;
25207 as_bad (_("unknown floating point format `%s'\n"), str
);
25212 arm_parse_float_abi (char * str
)
25214 const struct arm_option_value_table
* opt
;
25216 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25217 if (streq (opt
->name
, str
))
25219 mfloat_abi_opt
= opt
->value
;
25223 as_bad (_("unknown floating point abi `%s'\n"), str
);
25229 arm_parse_eabi (char * str
)
25231 const struct arm_option_value_table
*opt
;
25233 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25234 if (streq (opt
->name
, str
))
25236 meabi_flags
= opt
->value
;
25239 as_bad (_("unknown EABI `%s'\n"), str
);
25245 arm_parse_it_mode (char * str
)
25247 bfd_boolean ret
= TRUE
;
25249 if (streq ("arm", str
))
25250 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25251 else if (streq ("thumb", str
))
25252 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25253 else if (streq ("always", str
))
25254 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25255 else if (streq ("never", str
))
25256 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25259 as_bad (_("unknown implicit IT mode `%s', should be "\
25260 "arm, thumb, always, or never."), str
);
25268 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
25270 codecomposer_syntax
= TRUE
;
25271 arm_comment_chars
[0] = ';';
25272 arm_line_separator_chars
[0] = 0;
25276 struct arm_long_option_table arm_long_opts
[] =
25278 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25279 arm_parse_cpu
, NULL
},
25280 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25281 arm_parse_arch
, NULL
},
25282 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25283 arm_parse_fpu
, NULL
},
25284 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25285 arm_parse_float_abi
, NULL
},
25287 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25288 arm_parse_eabi
, NULL
},
25290 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25291 arm_parse_it_mode
, NULL
},
25292 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25293 arm_ccs_mode
, NULL
},
25294 {NULL
, NULL
, 0, NULL
}
25298 md_parse_option (int c
, char * arg
)
25300 struct arm_option_table
*opt
;
25301 const struct arm_legacy_option_table
*fopt
;
25302 struct arm_long_option_table
*lopt
;
25308 target_big_endian
= 1;
25314 target_big_endian
= 0;
25318 case OPTION_FIX_V4BX
:
25323 /* Listing option. Just ignore these, we don't support additional
25328 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25330 if (c
== opt
->option
[0]
25331 && ((arg
== NULL
&& opt
->option
[1] == 0)
25332 || streq (arg
, opt
->option
+ 1)))
25334 /* If the option is deprecated, tell the user. */
25335 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25336 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25337 arg
? arg
: "", _(opt
->deprecated
));
25339 if (opt
->var
!= NULL
)
25340 *opt
->var
= opt
->value
;
25346 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25348 if (c
== fopt
->option
[0]
25349 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25350 || streq (arg
, fopt
->option
+ 1)))
25352 /* If the option is deprecated, tell the user. */
25353 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25354 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25355 arg
? arg
: "", _(fopt
->deprecated
));
25357 if (fopt
->var
!= NULL
)
25358 *fopt
->var
= &fopt
->value
;
25364 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25366 /* These options are expected to have an argument. */
25367 if (c
== lopt
->option
[0]
25369 && strncmp (arg
, lopt
->option
+ 1,
25370 strlen (lopt
->option
+ 1)) == 0)
25372 /* If the option is deprecated, tell the user. */
25373 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25374 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25375 _(lopt
->deprecated
));
25377 /* Call the sup-option parser. */
25378 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25389 md_show_usage (FILE * fp
)
25391 struct arm_option_table
*opt
;
25392 struct arm_long_option_table
*lopt
;
25394 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25396 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25397 if (opt
->help
!= NULL
)
25398 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25400 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25401 if (lopt
->help
!= NULL
)
25402 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
25406 -EB assemble code for a big-endian cpu\n"));
25411 -EL assemble code for a little-endian cpu\n"));
25415 --fix-v4bx Allow BX in ARMv4 code\n"));
25423 arm_feature_set flags
;
25424 } cpu_arch_ver_table
;
25426 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25427 least features first. */
25428 static const cpu_arch_ver_table cpu_arch_ver
[] =
25434 {4, ARM_ARCH_V5TE
},
25435 {5, ARM_ARCH_V5TEJ
},
25439 {11, ARM_ARCH_V6M
},
25440 {12, ARM_ARCH_V6SM
},
25441 {8, ARM_ARCH_V6T2
},
25442 {10, ARM_ARCH_V7VE
},
25443 {10, ARM_ARCH_V7R
},
25444 {10, ARM_ARCH_V7M
},
25445 {14, ARM_ARCH_V8A
},
25449 /* Set an attribute if it has not already been set by the user. */
25451 aeabi_set_attribute_int (int tag
, int value
)
25454 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25455 || !attributes_set_explicitly
[tag
])
25456 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
25460 aeabi_set_attribute_string (int tag
, const char *value
)
25463 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
25464 || !attributes_set_explicitly
[tag
])
25465 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
25468 /* Set the public EABI object attributes. */
25470 aeabi_set_public_attributes (void)
25475 int fp16_optional
= 0;
25476 arm_feature_set flags
;
25477 arm_feature_set tmp
;
25478 const cpu_arch_ver_table
*p
;
25480 /* Choose the architecture based on the capabilities of the requested cpu
25481 (if any) and/or the instructions actually used. */
25482 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
25483 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
25484 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
25486 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
25487 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
25489 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
25490 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
25492 selected_cpu
= flags
;
25494 /* Allow the user to override the reported architecture. */
25497 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
25498 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
25501 /* We need to make sure that the attributes do not identify us as v6S-M
25502 when the only v6S-M feature in use is the Operating System Extensions. */
25503 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
25504 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
25505 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
25509 for (p
= cpu_arch_ver
; p
->val
; p
++)
25511 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
25514 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
25518 /* The table lookup above finds the last architecture to contribute
25519 a new feature. Unfortunately, Tag13 is a subset of the union of
25520 v6T2 and v7-M, so it is never seen as contributing a new feature.
25521 We can not search for the last entry which is entirely used,
25522 because if no CPU is specified we build up only those flags
25523 actually used. Perhaps we should separate out the specified
25524 and implicit cases. Avoid taking this path for -march=all by
25525 checking for contradictory v7-A / v7-M features. */
25527 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
25528 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
25529 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
25532 /* Tag_CPU_name. */
25533 if (selected_cpu_name
[0])
25537 q
= selected_cpu_name
;
25538 if (strncmp (q
, "armv", 4) == 0)
25543 for (i
= 0; q
[i
]; i
++)
25544 q
[i
] = TOUPPER (q
[i
]);
25546 aeabi_set_attribute_string (Tag_CPU_name
, q
);
25549 /* Tag_CPU_arch. */
25550 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
25552 /* Tag_CPU_arch_profile. */
25553 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
25555 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
25557 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
25562 if (profile
!= '\0')
25563 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
25565 /* Tag_ARM_ISA_use. */
25566 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
25568 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
25570 /* Tag_THUMB_ISA_use. */
25571 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
25573 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
25574 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
25576 /* Tag_VFP_arch. */
25577 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
25578 aeabi_set_attribute_int (Tag_VFP_arch
,
25579 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25581 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
25582 aeabi_set_attribute_int (Tag_VFP_arch
,
25583 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
25585 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
25588 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
25590 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
25592 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
25595 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
25596 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25597 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25598 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25599 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25601 /* Tag_ABI_HardFP_use. */
25602 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25603 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25604 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25606 /* Tag_WMMX_arch. */
25607 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25608 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25609 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25610 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25612 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25613 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25614 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25615 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25617 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25619 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25623 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25628 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25629 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25630 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25634 We set Tag_DIV_use to two when integer divide instructions have been used
25635 in ARM state, or when Thumb integer divide instructions have been used,
25636 but we have no architecture profile set, nor have we any ARM instructions.
25638 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25641 For new architectures we will have to check these tests. */
25642 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25643 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25644 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25645 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25646 || (profile
== '\0'
25647 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25648 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25649 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25651 /* Tag_MP_extension_use. */
25652 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25653 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25655 /* Tag Virtualization_use. */
25656 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25658 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25661 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25664 /* Add the default contents for the .ARM.attributes section. */
25668 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25671 aeabi_set_public_attributes ();
25673 #endif /* OBJ_ELF */
25676 /* Parse a .cpu directive. */
25679 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25681 const struct arm_cpu_option_table
*opt
;
25685 name
= input_line_pointer
;
25686 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25687 input_line_pointer
++;
25688 saved_char
= *input_line_pointer
;
25689 *input_line_pointer
= 0;
25691 /* Skip the first "all" entry. */
25692 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25693 if (streq (opt
->name
, name
))
25695 mcpu_cpu_opt
= &opt
->value
;
25696 selected_cpu
= opt
->value
;
25697 if (opt
->canonical_name
)
25698 strcpy (selected_cpu_name
, opt
->canonical_name
);
25702 for (i
= 0; opt
->name
[i
]; i
++)
25703 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25705 selected_cpu_name
[i
] = 0;
25707 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25708 *input_line_pointer
= saved_char
;
25709 demand_empty_rest_of_line ();
25712 as_bad (_("unknown cpu `%s'"), name
);
25713 *input_line_pointer
= saved_char
;
25714 ignore_rest_of_line ();
25718 /* Parse a .arch directive. */
25721 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25723 const struct arm_arch_option_table
*opt
;
25727 name
= input_line_pointer
;
25728 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25729 input_line_pointer
++;
25730 saved_char
= *input_line_pointer
;
25731 *input_line_pointer
= 0;
25733 /* Skip the first "all" entry. */
25734 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25735 if (streq (opt
->name
, name
))
25737 mcpu_cpu_opt
= &opt
->value
;
25738 selected_cpu
= opt
->value
;
25739 strcpy (selected_cpu_name
, opt
->name
);
25740 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25741 *input_line_pointer
= saved_char
;
25742 demand_empty_rest_of_line ();
25746 as_bad (_("unknown architecture `%s'\n"), name
);
25747 *input_line_pointer
= saved_char
;
25748 ignore_rest_of_line ();
25752 /* Parse a .object_arch directive. */
25755 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25757 const struct arm_arch_option_table
*opt
;
25761 name
= input_line_pointer
;
25762 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25763 input_line_pointer
++;
25764 saved_char
= *input_line_pointer
;
25765 *input_line_pointer
= 0;
25767 /* Skip the first "all" entry. */
25768 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25769 if (streq (opt
->name
, name
))
25771 object_arch
= &opt
->value
;
25772 *input_line_pointer
= saved_char
;
25773 demand_empty_rest_of_line ();
25777 as_bad (_("unknown architecture `%s'\n"), name
);
25778 *input_line_pointer
= saved_char
;
25779 ignore_rest_of_line ();
25782 /* Parse a .arch_extension directive. */
25785 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25787 const struct arm_option_extension_value_table
*opt
;
25790 int adding_value
= 1;
25792 name
= input_line_pointer
;
25793 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25794 input_line_pointer
++;
25795 saved_char
= *input_line_pointer
;
25796 *input_line_pointer
= 0;
25798 if (strlen (name
) >= 2
25799 && strncmp (name
, "no", 2) == 0)
25805 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25806 if (streq (opt
->name
, name
))
25808 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25810 as_bad (_("architectural extension `%s' is not allowed for the "
25811 "current base architecture"), name
);
25816 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
25819 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
25821 mcpu_cpu_opt
= &selected_cpu
;
25822 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25823 *input_line_pointer
= saved_char
;
25824 demand_empty_rest_of_line ();
25828 if (opt
->name
== NULL
)
25829 as_bad (_("unknown architecture extension `%s'\n"), name
);
25831 *input_line_pointer
= saved_char
;
25832 ignore_rest_of_line ();
25835 /* Parse a .fpu directive. */
25838 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25840 const struct arm_option_fpu_value_table
*opt
;
25844 name
= input_line_pointer
;
25845 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25846 input_line_pointer
++;
25847 saved_char
= *input_line_pointer
;
25848 *input_line_pointer
= 0;
25850 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25851 if (streq (opt
->name
, name
))
25853 mfpu_opt
= &opt
->value
;
25854 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25855 *input_line_pointer
= saved_char
;
25856 demand_empty_rest_of_line ();
25860 as_bad (_("unknown floating point format `%s'\n"), name
);
25861 *input_line_pointer
= saved_char
;
25862 ignore_rest_of_line ();
25865 /* Copy symbol information. */
25868 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25870 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25874 /* Given a symbolic attribute NAME, return the proper integer value.
25875 Returns -1 if the attribute is not known. */
25878 arm_convert_symbolic_attribute (const char *name
)
25880 static const struct
25885 attribute_table
[] =
25887 /* When you modify this table you should
25888 also modify the list in doc/c-arm.texi. */
25889 #define T(tag) {#tag, tag}
25890 T (Tag_CPU_raw_name
),
25893 T (Tag_CPU_arch_profile
),
25894 T (Tag_ARM_ISA_use
),
25895 T (Tag_THUMB_ISA_use
),
25899 T (Tag_Advanced_SIMD_arch
),
25900 T (Tag_PCS_config
),
25901 T (Tag_ABI_PCS_R9_use
),
25902 T (Tag_ABI_PCS_RW_data
),
25903 T (Tag_ABI_PCS_RO_data
),
25904 T (Tag_ABI_PCS_GOT_use
),
25905 T (Tag_ABI_PCS_wchar_t
),
25906 T (Tag_ABI_FP_rounding
),
25907 T (Tag_ABI_FP_denormal
),
25908 T (Tag_ABI_FP_exceptions
),
25909 T (Tag_ABI_FP_user_exceptions
),
25910 T (Tag_ABI_FP_number_model
),
25911 T (Tag_ABI_align_needed
),
25912 T (Tag_ABI_align8_needed
),
25913 T (Tag_ABI_align_preserved
),
25914 T (Tag_ABI_align8_preserved
),
25915 T (Tag_ABI_enum_size
),
25916 T (Tag_ABI_HardFP_use
),
25917 T (Tag_ABI_VFP_args
),
25918 T (Tag_ABI_WMMX_args
),
25919 T (Tag_ABI_optimization_goals
),
25920 T (Tag_ABI_FP_optimization_goals
),
25921 T (Tag_compatibility
),
25922 T (Tag_CPU_unaligned_access
),
25923 T (Tag_FP_HP_extension
),
25924 T (Tag_VFP_HP_extension
),
25925 T (Tag_ABI_FP_16bit_format
),
25926 T (Tag_MPextension_use
),
25928 T (Tag_nodefaults
),
25929 T (Tag_also_compatible_with
),
25930 T (Tag_conformance
),
25932 T (Tag_Virtualization_use
),
25933 /* We deliberately do not include Tag_MPextension_use_legacy. */
25941 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25942 if (streq (name
, attribute_table
[i
].name
))
25943 return attribute_table
[i
].tag
;
25949 /* Apply sym value for relocations only in the case that they are for
25950 local symbols in the same segment as the fixup and you have the
25951 respective architectural feature for blx and simple switches. */
25953 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
25956 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25957 /* PR 17444: If the local symbol is in a different section then a reloc
25958 will always be generated for it, so applying the symbol value now
25959 will result in a double offset being stored in the relocation. */
25960 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
25961 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25963 switch (fixP
->fx_r_type
)
25965 case BFD_RELOC_ARM_PCREL_BLX
:
25966 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25967 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25971 case BFD_RELOC_ARM_PCREL_CALL
:
25972 case BFD_RELOC_THUMB_PCREL_BLX
:
25973 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25984 #endif /* OBJ_ELF */