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[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modified by David Taylor (dtaylor@armltd.co.uk)
6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 02111-1307, USA. */
23
24 #include <ctype.h>
25 #include <string.h>
26 #define NO_RELOC 0
27 #include "as.h"
28
29 /* Need TARGET_CPU. */
30 #include "config.h"
31 #include "subsegs.h"
32 #include "obstack.h"
33 #include "symbols.h"
34 #include "listing.h"
35
36 #ifdef OBJ_ELF
37 #include "elf/arm.h"
38 #endif
39
40 /* Types of processor to assemble for. */
41 #define ARM_1 0x00000001
42 #define ARM_2 0x00000002
43 #define ARM_3 0x00000004
44 #define ARM_250 ARM_3
45 #define ARM_6 0x00000008
46 #define ARM_7 ARM_6 /* Same core instruction set. */
47 #define ARM_8 ARM_6 /* Same core instruction set. */
48 #define ARM_9 ARM_6 /* Same core instruction set. */
49 #define ARM_CPU_MASK 0x0000000f
50
51 /* The following bitmasks control CPU extensions (ARM7 onwards): */
52 #define ARM_LONGMUL 0x00000010 /* Allow long multiplies. */
53 #define ARM_HALFWORD 0x00000020 /* Allow half word loads. */
54 #define ARM_THUMB 0x00000040 /* Allow BX instruction. */
55 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
56
57 /* Architectures are the sum of the base and extensions. */
58 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
60 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
61 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
62
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP (ARM_ANY - ARM_1)
66 #define ARM_ALL ARM_2UP /* Not arm1 only. */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7. */
69
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
73 #define FPU_NONE 0
74
75 /* Some useful combinations. */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
78
79 #ifndef CPU_DEFAULT
80 #if defined __thumb__
81 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
82 #else
83 #define CPU_DEFAULT ARM_ALL
84 #endif
85 #endif
86
87 #ifndef FPU_DEFAULT
88 #define FPU_DEFAULT FPU_ALL
89 #endif
90
91 #define streq(a, b) (strcmp (a, b) == 0)
92 #define skip_whitespace(str) while (*(str) == ' ') ++(str)
93
94 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
95 static int target_oabi = 0;
96
97 #if defined OBJ_COFF || defined OBJ_ELF
98 /* Flags stored in private area of BFD structure. */
99 static boolean uses_apcs_26 = false;
100 static boolean support_interwork = false;
101 static boolean uses_apcs_float = false;
102 static boolean pic_code = false;
103 #endif
104
105 /* This array holds the chars that always start a comment. If the
106 pre-processor is disabled, these aren't very useful. */
107 CONST char comment_chars[] = "@";
108
109 /* This array holds the chars that only start a comment at the beginning of
110 a line. If the line seems to have the form '# 123 filename'
111 .line and .file directives will appear in the pre-processed output. */
112 /* Note that input_file.c hand checks for '#' at the beginning of the
113 first line of the input file. This is because the compiler outputs
114 #NO_APP at the beginning of its output. */
115 /* Also note that comments like this one will always work. */
116 CONST char line_comment_chars[] = "#";
117
118 CONST char line_separator_chars[] = ";";
119
120 /* Chars that can be used to separate mant
121 from exp in floating point numbers. */
122 CONST char EXP_CHARS[] = "eE";
123
124 /* Chars that mean this number is a floating point constant. */
125 /* As in 0f12.456 */
126 /* or 0d1.2345e12 */
127
128 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
129
130 /* Prefix characters that indicate the start of an immediate
131 value. */
132 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
133
134 #ifdef OBJ_ELF
135 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
136 symbolS * GOT_symbol;
137 #endif
138
139 /* Size of relocation record. */
140 CONST int md_reloc_size = 8;
141
142 /* 0: assemble for ARM,
143 1: assemble for Thumb,
144 2: assemble for Thumb even though target CPU does not support thumb
145 instructions. */
146 static int thumb_mode = 0;
147
148 typedef struct arm_fix
149 {
150 int thumb_mode;
151 } arm_fix_data;
152
153 struct arm_it
154 {
155 CONST char * error;
156 unsigned long instruction;
157 int suffix;
158 int size;
159 struct
160 {
161 bfd_reloc_code_real_type type;
162 expressionS exp;
163 int pc_rel;
164 } reloc;
165 };
166
167 struct arm_it inst;
168
169 enum asm_shift_index
170 {
171 SHIFT_LSL = 0,
172 SHIFT_LSR,
173 SHIFT_ASR,
174 SHIFT_ROR,
175 SHIFT_RRX
176 };
177
178 struct asm_shift_properties
179 {
180 enum asm_shift_index index;
181 unsigned long bit_field;
182 unsigned int allows_0 : 1;
183 unsigned int allows_32 : 1;
184 };
185
186 static const struct asm_shift_properties shift_properties [] =
187 {
188 { SHIFT_LSL, 0, 1, 0},
189 { SHIFT_LSR, 0x20, 0, 1},
190 { SHIFT_ASR, 0x40, 0, 1},
191 { SHIFT_ROR, 0x60, 0, 0},
192 { SHIFT_RRX, 0x60, 0, 0}
193 };
194
195 struct asm_shift_name
196 {
197 const char * name;
198 const struct asm_shift_properties * properties;
199 };
200
201 static const struct asm_shift_name shift_names [] =
202 {
203 { "asl", shift_properties + SHIFT_LSL },
204 { "lsl", shift_properties + SHIFT_LSL },
205 { "lsr", shift_properties + SHIFT_LSR },
206 { "asr", shift_properties + SHIFT_ASR },
207 { "ror", shift_properties + SHIFT_ROR },
208 { "rrx", shift_properties + SHIFT_RRX },
209 { "ASL", shift_properties + SHIFT_LSL },
210 { "LSL", shift_properties + SHIFT_LSL },
211 { "LSR", shift_properties + SHIFT_LSR },
212 { "ASR", shift_properties + SHIFT_ASR },
213 { "ROR", shift_properties + SHIFT_ROR },
214 { "RRX", shift_properties + SHIFT_RRX }
215 };
216
217 #define NO_SHIFT_RESTRICT 1
218 #define SHIFT_RESTRICT 0
219
220 #define NUM_FLOAT_VALS 8
221
222 CONST char * fp_const[] =
223 {
224 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
225 };
226
227 /* Number of littlenums required to hold an extended precision number. */
228 #define MAX_LITTLENUMS 6
229
230 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
231
232 #define FAIL (-1)
233 #define SUCCESS (0)
234
235 #define SUFF_S 1
236 #define SUFF_D 2
237 #define SUFF_E 3
238 #define SUFF_P 4
239
240 #define CP_T_X 0x00008000
241 #define CP_T_Y 0x00400000
242 #define CP_T_Pre 0x01000000
243 #define CP_T_UD 0x00800000
244 #define CP_T_WB 0x00200000
245
246 #define CONDS_BIT (0x00100000)
247 #define LOAD_BIT (0x00100000)
248 #define TRANS_BIT (0x00200000)
249
250 struct asm_cond
251 {
252 CONST char * template;
253 unsigned long value;
254 };
255
256 /* This is to save a hash look-up in the common case. */
257 #define COND_ALWAYS 0xe0000000
258
259 static CONST struct asm_cond conds[] =
260 {
261 {"eq", 0x00000000},
262 {"ne", 0x10000000},
263 {"cs", 0x20000000}, {"hs", 0x20000000},
264 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
265 {"mi", 0x40000000},
266 {"pl", 0x50000000},
267 {"vs", 0x60000000},
268 {"vc", 0x70000000},
269 {"hi", 0x80000000},
270 {"ls", 0x90000000},
271 {"ge", 0xa0000000},
272 {"lt", 0xb0000000},
273 {"gt", 0xc0000000},
274 {"le", 0xd0000000},
275 {"al", 0xe0000000},
276 {"nv", 0xf0000000}
277 };
278
279 /* Warning: If the top bit of the set_bits is set, then the standard
280 instruction bitmask is ignored, and the new bitmask is taken from
281 the set_bits: */
282 struct asm_flg
283 {
284 CONST char * template; /* Basic flag string. */
285 unsigned long set_bits; /* Bits to set. */
286 };
287
288 static CONST struct asm_flg s_flag[] =
289 {
290 {"s", CONDS_BIT},
291 {NULL, 0}
292 };
293
294 static CONST struct asm_flg ldr_flags[] =
295 {
296 {"b", 0x00400000},
297 {"t", TRANS_BIT},
298 {"bt", 0x00400000 | TRANS_BIT},
299 {"h", 0x801000b0},
300 {"sh", 0x801000f0},
301 {"sb", 0x801000d0},
302 {NULL, 0}
303 };
304
305 static CONST struct asm_flg str_flags[] =
306 {
307 {"b", 0x00400000},
308 {"t", TRANS_BIT},
309 {"bt", 0x00400000 | TRANS_BIT},
310 {"h", 0x800000b0},
311 {NULL, 0}
312 };
313
314 static CONST struct asm_flg byte_flag[] =
315 {
316 {"b", 0x00400000},
317 {NULL, 0}
318 };
319
320 static CONST struct asm_flg cmp_flags[] =
321 {
322 {"s", CONDS_BIT},
323 {"p", 0x0010f000},
324 {NULL, 0}
325 };
326
327 static CONST struct asm_flg ldm_flags[] =
328 {
329 {"ed", 0x01800000},
330 {"fd", 0x00800000},
331 {"ea", 0x01000000},
332 {"fa", 0x08000000},
333 {"ib", 0x01800000},
334 {"ia", 0x00800000},
335 {"db", 0x01000000},
336 {"da", 0x08000000},
337 {NULL, 0}
338 };
339
340 static CONST struct asm_flg stm_flags[] =
341 {
342 {"ed", 0x08000000},
343 {"fd", 0x01000000},
344 {"ea", 0x00800000},
345 {"fa", 0x01800000},
346 {"ib", 0x01800000},
347 {"ia", 0x00800000},
348 {"db", 0x01000000},
349 {"da", 0x08000000},
350 {NULL, 0}
351 };
352
353 static CONST struct asm_flg lfm_flags[] =
354 {
355 {"fd", 0x00800000},
356 {"ea", 0x01000000},
357 {NULL, 0}
358 };
359
360 static CONST struct asm_flg sfm_flags[] =
361 {
362 {"fd", 0x01000000},
363 {"ea", 0x00800000},
364 {NULL, 0}
365 };
366
367 static CONST struct asm_flg round_flags[] =
368 {
369 {"p", 0x00000020},
370 {"m", 0x00000040},
371 {"z", 0x00000060},
372 {NULL, 0}
373 };
374
375 /* The implementation of the FIX instruction is broken on some assemblers,
376 in that it accepts a precision specifier as well as a rounding specifier,
377 despite the fact that this is meaningless. To be more compatible, we
378 accept it as well, though of course it does not set any bits. */
379 static CONST struct asm_flg fix_flags[] =
380 {
381 {"p", 0x00000020},
382 {"m", 0x00000040},
383 {"z", 0x00000060},
384 {"sp", 0x00000020},
385 {"sm", 0x00000040},
386 {"sz", 0x00000060},
387 {"dp", 0x00000020},
388 {"dm", 0x00000040},
389 {"dz", 0x00000060},
390 {"ep", 0x00000020},
391 {"em", 0x00000040},
392 {"ez", 0x00000060},
393 {NULL, 0}
394 };
395
396 static CONST struct asm_flg except_flag[] =
397 {
398 {"e", 0x00400000},
399 {NULL, 0}
400 };
401
402 static CONST struct asm_flg cplong_flag[] =
403 {
404 {"l", 0x00400000},
405 {NULL, 0}
406 };
407
408 struct asm_psr
409 {
410 CONST char * template;
411 boolean cpsr;
412 unsigned long field;
413 };
414
415 /* The bit that distnguishes CPSR and SPSR. */
416 #define SPSR_BIT (1 << 22)
417
418 /* How many bits to shift the PSR_xxx bits up by. */
419 #define PSR_SHIFT 16
420
421 #define PSR_c (1 << 0)
422 #define PSR_x (1 << 1)
423 #define PSR_s (1 << 2)
424 #define PSR_f (1 << 3)
425
426 static CONST struct asm_psr psrs[] =
427 {
428 {"CPSR", true, PSR_c | PSR_f},
429 {"CPSR_all", true, PSR_c | PSR_f},
430 {"SPSR", false, PSR_c | PSR_f},
431 {"SPSR_all", false, PSR_c | PSR_f},
432 {"CPSR_flg", true, PSR_f},
433 {"CPSR_f", true, PSR_f},
434 {"SPSR_flg", false, PSR_f},
435 {"SPSR_f", false, PSR_f},
436 {"CPSR_c", true, PSR_c},
437 {"CPSR_ctl", true, PSR_c},
438 {"SPSR_c", false, PSR_c},
439 {"SPSR_ctl", false, PSR_c},
440 {"CPSR_x", true, PSR_x},
441 {"CPSR_s", true, PSR_s},
442 {"SPSR_x", false, PSR_x},
443 {"SPSR_s", false, PSR_s},
444 /* Combinations of flags. */
445 {"CPSR_fs", true, PSR_f | PSR_s},
446 {"CPSR_fx", true, PSR_f | PSR_x},
447 {"CPSR_fc", true, PSR_f | PSR_c},
448 {"CPSR_sf", true, PSR_s | PSR_f},
449 {"CPSR_sx", true, PSR_s | PSR_x},
450 {"CPSR_sc", true, PSR_s | PSR_c},
451 {"CPSR_xf", true, PSR_x | PSR_f},
452 {"CPSR_xs", true, PSR_x | PSR_s},
453 {"CPSR_xc", true, PSR_x | PSR_c},
454 {"CPSR_cf", true, PSR_c | PSR_f},
455 {"CPSR_cs", true, PSR_c | PSR_s},
456 {"CPSR_cx", true, PSR_c | PSR_x},
457 {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x},
458 {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c},
459 {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s},
460 {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c},
461 {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s},
462 {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x},
463 {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x},
464 {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c},
465 {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f},
466 {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c},
467 {"CPSR_scf", true, PSR_s | PSR_c | PSR_f},
468 {"CPSR_scx", true, PSR_s | PSR_c | PSR_x},
469 {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s},
470 {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c},
471 {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f},
472 {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c},
473 {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f},
474 {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s},
475 {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s},
476 {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x},
477 {"CPSR_csf", true, PSR_c | PSR_s | PSR_f},
478 {"CPSR_csx", true, PSR_c | PSR_s | PSR_x},
479 {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f},
480 {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s},
481 {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c},
482 {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x},
483 {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c},
484 {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s},
485 {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x},
486 {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s},
487 {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c},
488 {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x},
489 {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c},
490 {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f},
491 {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x},
492 {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f},
493 {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c},
494 {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s},
495 {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c},
496 {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f},
497 {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s},
498 {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f},
499 {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x},
500 {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s},
501 {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x},
502 {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f},
503 {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s},
504 {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f},
505 {"SPSR_fs", false, PSR_f | PSR_s},
506 {"SPSR_fx", false, PSR_f | PSR_x},
507 {"SPSR_fc", false, PSR_f | PSR_c},
508 {"SPSR_sf", false, PSR_s | PSR_f},
509 {"SPSR_sx", false, PSR_s | PSR_x},
510 {"SPSR_sc", false, PSR_s | PSR_c},
511 {"SPSR_xf", false, PSR_x | PSR_f},
512 {"SPSR_xs", false, PSR_x | PSR_s},
513 {"SPSR_xc", false, PSR_x | PSR_c},
514 {"SPSR_cf", false, PSR_c | PSR_f},
515 {"SPSR_cs", false, PSR_c | PSR_s},
516 {"SPSR_cx", false, PSR_c | PSR_x},
517 {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x},
518 {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c},
519 {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s},
520 {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c},
521 {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s},
522 {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x},
523 {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x},
524 {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c},
525 {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f},
526 {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c},
527 {"SPSR_scf", false, PSR_s | PSR_c | PSR_f},
528 {"SPSR_scx", false, PSR_s | PSR_c | PSR_x},
529 {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s},
530 {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c},
531 {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f},
532 {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c},
533 {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f},
534 {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s},
535 {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s},
536 {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x},
537 {"SPSR_csf", false, PSR_c | PSR_s | PSR_f},
538 {"SPSR_csx", false, PSR_c | PSR_s | PSR_x},
539 {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f},
540 {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s},
541 {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c},
542 {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x},
543 {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c},
544 {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s},
545 {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x},
546 {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s},
547 {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c},
548 {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x},
549 {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c},
550 {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f},
551 {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x},
552 {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f},
553 {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c},
554 {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s},
555 {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c},
556 {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f},
557 {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s},
558 {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f},
559 {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x},
560 {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s},
561 {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x},
562 {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f},
563 {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s},
564 {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
565 /* For backwards compatability with older toolchain we also
566 support lower case versions of some of these flags. */
567 {"cpsr", true, PSR_c | PSR_f},
568 {"cpsr_all", true, PSR_c | PSR_f},
569 {"spsr", false, PSR_c | PSR_f},
570 {"spsr_all", false, PSR_c | PSR_f},
571 {"cpsr_flg", true, PSR_f},
572 {"cpsr_f", true, PSR_f},
573 {"spsr_flg", false, PSR_f},
574 {"spsr_f", false, PSR_f},
575 {"cpsr_c", true, PSR_c},
576 {"cpsr_ctl", true, PSR_c},
577 {"spsr_c", false, PSR_c},
578 {"spsr_ctl", false, PSR_c}
579 };
580
581 /* Functions called by parser. */
582 /* ARM instructions. */
583 static void do_arit PARAMS ((char *, unsigned long));
584 static void do_cmp PARAMS ((char *, unsigned long));
585 static void do_mov PARAMS ((char *, unsigned long));
586 static void do_ldst PARAMS ((char *, unsigned long));
587 static void do_ldmstm PARAMS ((char *, unsigned long));
588 static void do_branch PARAMS ((char *, unsigned long));
589 static void do_swi PARAMS ((char *, unsigned long));
590 /* Pseudo Op codes. */
591 static void do_adr PARAMS ((char *, unsigned long));
592 static void do_adrl PARAMS ((char *, unsigned long));
593 static void do_nop PARAMS ((char *, unsigned long));
594 /* ARM 2. */
595 static void do_mul PARAMS ((char *, unsigned long));
596 static void do_mla PARAMS ((char *, unsigned long));
597 /* ARM 3. */
598 static void do_swap PARAMS ((char *, unsigned long));
599 /* ARM 6. */
600 static void do_msr PARAMS ((char *, unsigned long));
601 static void do_mrs PARAMS ((char *, unsigned long));
602 /* ARM 7M. */
603 static void do_mull PARAMS ((char *, unsigned long));
604 /* ARM THUMB. */
605 static void do_bx PARAMS ((char *, unsigned long));
606
607 /* Coprocessor Instructions. */
608 static void do_cdp PARAMS ((char *, unsigned long));
609 static void do_lstc PARAMS ((char *, unsigned long));
610 static void do_co_reg PARAMS ((char *, unsigned long));
611 static void do_fp_ctrl PARAMS ((char *, unsigned long));
612 static void do_fp_ldst PARAMS ((char *, unsigned long));
613 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
614 static void do_fp_dyadic PARAMS ((char *, unsigned long));
615 static void do_fp_monadic PARAMS ((char *, unsigned long));
616 static void do_fp_cmp PARAMS ((char *, unsigned long));
617 static void do_fp_from_reg PARAMS ((char *, unsigned long));
618 static void do_fp_to_reg PARAMS ((char *, unsigned long));
619
620 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
621 static int arm_reg_parse PARAMS ((char **));
622 static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
623 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
624 static int add_to_lit_pool PARAMS ((void));
625 static unsigned validate_immediate PARAMS ((unsigned));
626 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
627 static int validate_offset_imm PARAMS ((unsigned int, int));
628 static void opcode_select PARAMS ((int));
629 static void end_of_line PARAMS ((char *));
630 static int reg_required_here PARAMS ((char **, int));
631 static int psr_required_here PARAMS ((char **));
632 static int co_proc_number PARAMS ((char **));
633 static int cp_opc_expr PARAMS ((char **, int, int));
634 static int cp_reg_required_here PARAMS ((char **, int));
635 static int fp_reg_required_here PARAMS ((char **, int));
636 static int cp_address_offset PARAMS ((char **));
637 static int cp_address_required_here PARAMS ((char **));
638 static int my_get_float_expression PARAMS ((char **));
639 static int skip_past_comma PARAMS ((char **));
640 static int walk_no_bignums PARAMS ((symbolS *));
641 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
642 static int data_op2 PARAMS ((char **));
643 static int fp_op2 PARAMS ((char **));
644 static long reg_list PARAMS ((char **));
645 static void thumb_load_store PARAMS ((char *, int, int));
646 static int decode_shift PARAMS ((char **, int));
647 static int ldst_extend PARAMS ((char **, int));
648 static void thumb_add_sub PARAMS ((char *, int));
649 static void insert_reg PARAMS ((int));
650 static void thumb_shift PARAMS ((char *, int));
651 static void thumb_mov_compare PARAMS ((char *, int));
652 static void set_constant_flonums PARAMS ((void));
653 static valueT md_chars_to_number PARAMS ((char *, int));
654 static void insert_reg_alias PARAMS ((char *, int));
655 static void output_inst PARAMS ((void));
656 #ifdef OBJ_ELF
657 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
658 #endif
659
660 /* ARM instructions take 4bytes in the object file, Thumb instructions
661 take 2: */
662 #define INSN_SIZE 4
663
664 /* LONGEST_INST is the longest basic instruction name without conditions or
665 flags. ARM7M has 4 of length 5. */
666
667 #define LONGEST_INST 5
668
669 struct asm_opcode
670 {
671 /* Basic string to match. */
672 CONST char * template;
673
674 /* Basic instruction code. */
675 unsigned long value;
676
677 /* Compulsory suffix that must follow conds. If "", then the
678 instruction is not conditional and must have no suffix. */
679 CONST char * comp_suffix;
680
681 /* Bits to toggle if flag 'n' set. */
682 CONST struct asm_flg * flags;
683
684 /* Which CPU variants this exists for. */
685 unsigned long variants;
686
687 /* Function to call to parse args. */
688 void (* parms) PARAMS ((char *, unsigned long));
689 };
690
691 static CONST struct asm_opcode insns[] =
692 {
693 /* ARM Instructions. */
694 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
695 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
696 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
697 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
698 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
699 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
700 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
701 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
702 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
703 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
704 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
705 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
706 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
707 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
708 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
709 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
710 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
711 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
712 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
713 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
714 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
715 #ifdef TE_WINCE
716 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
717 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
718 #else
719 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
720 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
721 #endif
722
723 /* Pseudo ops. */
724 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
725 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
726 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
727
728 /* ARM 2 multiplies. */
729 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
730 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
731
732 /* ARM 3 - swp instructions. */
733 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
734
735 /* ARM 6 Coprocessor instructions. */
736 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
737 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
738 /* ScottB: our code uses 0x0128f000 for msr.
739 NickC: but this is wrong because the bits 16 through 19 are
740 handled by the PSR_xxx defines above. */
741
742 /* ARM 7M long multiplies - need signed/unsigned flags! */
743 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
744 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
745 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
746 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
747
748 /* ARM THUMB interworking. */
749 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
750
751 /* Floating point instructions. */
752 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
753 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
754 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
755 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
756 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
757 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
758 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
759 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
760 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
761 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
762 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
763 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
764 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
765 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
766 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
767 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
768 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
769 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
770 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
771 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
772 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
773 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
774 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
775 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
776 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
777 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
778 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
779 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
780 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
781 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
782 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
783 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
784 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
785 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
786 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
787 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
788 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
789 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
790 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
791 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
792 be an optional suffix, but part of the instruction. To be compatible,
793 we accept either. */
794 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
795 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
796 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
797 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
798
799 /* Generic copressor instructions. */
800 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
801 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
802 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
803 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
804 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
805 };
806
807 /* Defines for various bits that we will want to toggle. */
808 #define INST_IMMEDIATE 0x02000000
809 #define OFFSET_REG 0x02000000
810 #define HWOFFSET_IMM 0x00400000
811 #define SHIFT_BY_REG 0x00000010
812 #define PRE_INDEX 0x01000000
813 #define INDEX_UP 0x00800000
814 #define WRITE_BACK 0x00200000
815 #define LDM_TYPE_2_OR_3 0x00400000
816
817 #define LITERAL_MASK 0xf000f000
818 #define COND_MASK 0xf0000000
819 #define OPCODE_MASK 0xfe1fffff
820 #define DATA_OP_SHIFT 21
821
822 /* Codes to distinguish the arithmetic instructions. */
823 #define OPCODE_AND 0
824 #define OPCODE_EOR 1
825 #define OPCODE_SUB 2
826 #define OPCODE_RSB 3
827 #define OPCODE_ADD 4
828 #define OPCODE_ADC 5
829 #define OPCODE_SBC 6
830 #define OPCODE_RSC 7
831 #define OPCODE_TST 8
832 #define OPCODE_TEQ 9
833 #define OPCODE_CMP 10
834 #define OPCODE_CMN 11
835 #define OPCODE_ORR 12
836 #define OPCODE_MOV 13
837 #define OPCODE_BIC 14
838 #define OPCODE_MVN 15
839
840 static void do_t_nop PARAMS ((char *));
841 static void do_t_arit PARAMS ((char *));
842 static void do_t_add PARAMS ((char *));
843 static void do_t_asr PARAMS ((char *));
844 static void do_t_branch9 PARAMS ((char *));
845 static void do_t_branch12 PARAMS ((char *));
846 static void do_t_branch23 PARAMS ((char *));
847 static void do_t_bx PARAMS ((char *));
848 static void do_t_compare PARAMS ((char *));
849 static void do_t_ldmstm PARAMS ((char *));
850 static void do_t_ldr PARAMS ((char *));
851 static void do_t_ldrb PARAMS ((char *));
852 static void do_t_ldrh PARAMS ((char *));
853 static void do_t_lds PARAMS ((char *));
854 static void do_t_lsl PARAMS ((char *));
855 static void do_t_lsr PARAMS ((char *));
856 static void do_t_mov PARAMS ((char *));
857 static void do_t_push_pop PARAMS ((char *));
858 static void do_t_str PARAMS ((char *));
859 static void do_t_strb PARAMS ((char *));
860 static void do_t_strh PARAMS ((char *));
861 static void do_t_sub PARAMS ((char *));
862 static void do_t_swi PARAMS ((char *));
863 static void do_t_adr PARAMS ((char *));
864
865 #define T_OPCODE_MUL 0x4340
866 #define T_OPCODE_TST 0x4200
867 #define T_OPCODE_CMN 0x42c0
868 #define T_OPCODE_NEG 0x4240
869 #define T_OPCODE_MVN 0x43c0
870
871 #define T_OPCODE_ADD_R3 0x1800
872 #define T_OPCODE_SUB_R3 0x1a00
873 #define T_OPCODE_ADD_HI 0x4400
874 #define T_OPCODE_ADD_ST 0xb000
875 #define T_OPCODE_SUB_ST 0xb080
876 #define T_OPCODE_ADD_SP 0xa800
877 #define T_OPCODE_ADD_PC 0xa000
878 #define T_OPCODE_ADD_I8 0x3000
879 #define T_OPCODE_SUB_I8 0x3800
880 #define T_OPCODE_ADD_I3 0x1c00
881 #define T_OPCODE_SUB_I3 0x1e00
882
883 #define T_OPCODE_ASR_R 0x4100
884 #define T_OPCODE_LSL_R 0x4080
885 #define T_OPCODE_LSR_R 0x40c0
886 #define T_OPCODE_ASR_I 0x1000
887 #define T_OPCODE_LSL_I 0x0000
888 #define T_OPCODE_LSR_I 0x0800
889
890 #define T_OPCODE_MOV_I8 0x2000
891 #define T_OPCODE_CMP_I8 0x2800
892 #define T_OPCODE_CMP_LR 0x4280
893 #define T_OPCODE_MOV_HR 0x4600
894 #define T_OPCODE_CMP_HR 0x4500
895
896 #define T_OPCODE_LDR_PC 0x4800
897 #define T_OPCODE_LDR_SP 0x9800
898 #define T_OPCODE_STR_SP 0x9000
899 #define T_OPCODE_LDR_IW 0x6800
900 #define T_OPCODE_STR_IW 0x6000
901 #define T_OPCODE_LDR_IH 0x8800
902 #define T_OPCODE_STR_IH 0x8000
903 #define T_OPCODE_LDR_IB 0x7800
904 #define T_OPCODE_STR_IB 0x7000
905 #define T_OPCODE_LDR_RW 0x5800
906 #define T_OPCODE_STR_RW 0x5000
907 #define T_OPCODE_LDR_RH 0x5a00
908 #define T_OPCODE_STR_RH 0x5200
909 #define T_OPCODE_LDR_RB 0x5c00
910 #define T_OPCODE_STR_RB 0x5400
911
912 #define T_OPCODE_PUSH 0xb400
913 #define T_OPCODE_POP 0xbc00
914
915 #define T_OPCODE_BRANCH 0xe7fe
916
917 static int thumb_reg PARAMS ((char ** str, int hi_lo));
918
919 #define THUMB_SIZE 2 /* Size of thumb instruction. */
920 #define THUMB_REG_LO 0x1
921 #define THUMB_REG_HI 0x2
922 #define THUMB_REG_ANY 0x3
923
924 #define THUMB_H1 0x0080
925 #define THUMB_H2 0x0040
926
927 #define THUMB_ASR 0
928 #define THUMB_LSL 1
929 #define THUMB_LSR 2
930
931 #define THUMB_MOVE 0
932 #define THUMB_COMPARE 1
933
934 #define THUMB_LOAD 0
935 #define THUMB_STORE 1
936
937 #define THUMB_PP_PC_LR 0x0100
938
939 /* These three are used for immediate shifts, do not alter. */
940 #define THUMB_WORD 2
941 #define THUMB_HALFWORD 1
942 #define THUMB_BYTE 0
943
944 struct thumb_opcode
945 {
946 /* Basic string to match. */
947 CONST char * template;
948
949 /* Basic instruction code. */
950 unsigned long value;
951
952 int size;
953
954 /* Which CPU variants this exists for. */
955 unsigned long variants;
956
957 /* Function to call to parse args. */
958 void (* parms) PARAMS ((char *));
959 };
960
961 static CONST struct thumb_opcode tinsns[] =
962 {
963 {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
964 {"add", 0x0000, 2, ARM_THUMB, do_t_add},
965 {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
966 {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
967 {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
968 {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
969 {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
970 {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
971 {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
972 {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
973 {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
974 {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
975 {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
976 {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
977 {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
978 {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
979 {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
980 {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
981 {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
982 {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
983 {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
984 {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
985 {"bal", 0xdefe, 2, ARM_THUMB, do_t_branch9},
986 {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
987 {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
988 {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
989 {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
990 {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
991 {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
992 {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
993 {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
994 {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
995 {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
996 {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
997 {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
998 {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
999 {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
1000 {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
1001 {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
1002 {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
1003 {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
1004 {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
1005 {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
1006 {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
1007 {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
1008 {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
1009 {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
1010 {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
1011 {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
1012 {"str", 0x0000, 2, ARM_THUMB, do_t_str},
1013 {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
1014 {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
1015 {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
1016 {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
1017 {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
1018 /* Pseudo ops: */
1019 {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
1020 {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
1021 };
1022
1023 struct reg_entry
1024 {
1025 CONST char * name;
1026 int number;
1027 };
1028
1029 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
1030 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
1031 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
1032
1033 #define REG_PC 15
1034 #define REG_LR 14
1035 #define REG_SP 13
1036
1037 /* These are the standard names. Users can add aliases with .req. */
1038 static CONST struct reg_entry reg_table[] =
1039 {
1040 /* Processor Register Numbers. */
1041 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
1042 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
1043 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
1044 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
1045 /* APCS conventions. */
1046 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
1047 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
1048 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
1049 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
1050 /* ATPCS additions to APCS conventions. */
1051 {"wr", 7}, {"v8", 11},
1052 /* FP Registers. */
1053 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
1054 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
1055 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
1056 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
1057 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
1058 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
1059 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
1060 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
1061 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
1062 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
1063 /* ATPCS additions to float register names. */
1064 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
1065 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
1066 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
1067 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
1068 /* FIXME: At some point we need to add VFP register names. */
1069 /* Array terminator. */
1070 {NULL, 0}
1071 };
1072
1073 #define BAD_ARGS _("Bad arguments to instruction")
1074 #define BAD_PC _("r15 not allowed here")
1075 #define BAD_FLAGS _("Instruction should not have flags")
1076 #define BAD_COND _("Instruction is not conditional")
1077
1078 static struct hash_control * arm_ops_hsh = NULL;
1079 static struct hash_control * arm_tops_hsh = NULL;
1080 static struct hash_control * arm_cond_hsh = NULL;
1081 static struct hash_control * arm_shift_hsh = NULL;
1082 static struct hash_control * arm_reg_hsh = NULL;
1083 static struct hash_control * arm_psr_hsh = NULL;
1084
1085 /* This table describes all the machine specific pseudo-ops the assembler
1086 has to support. The fields are:
1087 pseudo-op name without dot
1088 function to call to execute this pseudo-op
1089 Integer arg to pass to the function. */
1090
1091 static void s_req PARAMS ((int));
1092 static void s_align PARAMS ((int));
1093 static void s_bss PARAMS ((int));
1094 static void s_even PARAMS ((int));
1095 static void s_ltorg PARAMS ((int));
1096 static void s_arm PARAMS ((int));
1097 static void s_thumb PARAMS ((int));
1098 static void s_code PARAMS ((int));
1099 static void s_force_thumb PARAMS ((int));
1100 static void s_thumb_func PARAMS ((int));
1101 static void s_thumb_set PARAMS ((int));
1102 static void arm_s_text PARAMS ((int));
1103 static void arm_s_data PARAMS ((int));
1104 #ifdef OBJ_ELF
1105 static void arm_s_section PARAMS ((int));
1106 static void s_arm_elf_cons PARAMS ((int));
1107 #endif
1108
1109 static int my_get_expression PARAMS ((expressionS *, char **));
1110
1111 CONST pseudo_typeS md_pseudo_table[] =
1112 {
1113 /* Never called becasue '.req' does not start line. */
1114 { "req", s_req, 0 },
1115 { "bss", s_bss, 0 },
1116 { "align", s_align, 0 },
1117 { "arm", s_arm, 0 },
1118 { "thumb", s_thumb, 0 },
1119 { "code", s_code, 0 },
1120 { "force_thumb", s_force_thumb, 0 },
1121 { "thumb_func", s_thumb_func, 0 },
1122 { "thumb_set", s_thumb_set, 0 },
1123 { "even", s_even, 0 },
1124 { "ltorg", s_ltorg, 0 },
1125 { "pool", s_ltorg, 0 },
1126 /* Allow for the effect of section changes. */
1127 { "text", arm_s_text, 0 },
1128 { "data", arm_s_data, 0 },
1129 #ifdef OBJ_ELF
1130 { "section", arm_s_section, 0 },
1131 { "section.s", arm_s_section, 0 },
1132 { "sect", arm_s_section, 0 },
1133 { "sect.s", arm_s_section, 0 },
1134 { "word", s_arm_elf_cons, 4 },
1135 { "long", s_arm_elf_cons, 4 },
1136 #else
1137 { "word", cons, 4},
1138 #endif
1139 { "extend", float_cons, 'x' },
1140 { "ldouble", float_cons, 'x' },
1141 { "packed", float_cons, 'p' },
1142 { 0, 0, 0 }
1143 };
1144
1145 /* Stuff needed to resolve the label ambiguity
1146 As:
1147 ...
1148 label: <insn>
1149 may differ from:
1150 ...
1151 label:
1152 <insn>
1153 */
1154
1155 symbolS * last_label_seen;
1156 static int label_is_thumb_function_name = false;
1157
1158 /* Literal stuff. */
1159
1160 #define MAX_LITERAL_POOL_SIZE 1024
1161
1162 typedef struct literalS
1163 {
1164 struct expressionS exp;
1165 struct arm_it * inst;
1166 } literalT;
1167
1168 literalT literals[MAX_LITERAL_POOL_SIZE];
1169
1170 /* Next free entry in the pool. */
1171 int next_literal_pool_place = 0;
1172
1173 /* Next literal pool number. */
1174 int lit_pool_num = 1;
1175
1176 symbolS * current_poolP = NULL;
1177
1178 static int
1179 add_to_lit_pool ()
1180 {
1181 int lit_count = 0;
1182
1183 if (current_poolP == NULL)
1184 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1185 (valueT) 0, &zero_address_frag);
1186
1187 /* Check if this literal value is already in the pool: */
1188 while (lit_count < next_literal_pool_place)
1189 {
1190 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1191 && inst.reloc.exp.X_op == O_constant
1192 && (literals[lit_count].exp.X_add_number
1193 == inst.reloc.exp.X_add_number)
1194 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1195 break;
1196 lit_count++;
1197 }
1198
1199 if (lit_count == next_literal_pool_place) /* New entry. */
1200 {
1201 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1202 {
1203 inst.error = _("Literal Pool Overflow");
1204 return FAIL;
1205 }
1206
1207 literals[next_literal_pool_place].exp = inst.reloc.exp;
1208 lit_count = next_literal_pool_place++;
1209 }
1210
1211 inst.reloc.exp.X_op = O_symbol;
1212 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1213 inst.reloc.exp.X_add_symbol = current_poolP;
1214
1215 return SUCCESS;
1216 }
1217
1218 /* Can't use symbol_new here, so have to create a symbol and then at
1219 a later date assign it a value. Thats what these functions do. */
1220
1221 static void
1222 symbol_locate (symbolP, name, segment, valu, frag)
1223 symbolS * symbolP;
1224 CONST char * name; /* It is copied, the caller can modify. */
1225 segT segment; /* Segment identifier (SEG_<something>). */
1226 valueT valu; /* Symbol value. */
1227 fragS * frag; /* Associated fragment. */
1228 {
1229 unsigned int name_length;
1230 char * preserved_copy_of_name;
1231
1232 name_length = strlen (name) + 1; /* +1 for \0. */
1233 obstack_grow (&notes, name, name_length);
1234 preserved_copy_of_name = obstack_finish (&notes);
1235 #ifdef STRIP_UNDERSCORE
1236 if (preserved_copy_of_name[0] == '_')
1237 preserved_copy_of_name++;
1238 #endif
1239
1240 #ifdef tc_canonicalize_symbol_name
1241 preserved_copy_of_name =
1242 tc_canonicalize_symbol_name (preserved_copy_of_name);
1243 #endif
1244
1245 S_SET_NAME (symbolP, preserved_copy_of_name);
1246
1247 S_SET_SEGMENT (symbolP, segment);
1248 S_SET_VALUE (symbolP, valu);
1249 symbol_clear_list_pointers(symbolP);
1250
1251 symbol_set_frag (symbolP, frag);
1252
1253 /* Link to end of symbol chain. */
1254 {
1255 extern int symbol_table_frozen;
1256 if (symbol_table_frozen)
1257 abort ();
1258 }
1259
1260 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1261
1262 obj_symbol_new_hook (symbolP);
1263
1264 #ifdef tc_symbol_new_hook
1265 tc_symbol_new_hook (symbolP);
1266 #endif
1267
1268 #ifdef DEBUG_SYMS
1269 verify_symbol_chain (symbol_rootP, symbol_lastP);
1270 #endif /* DEBUG_SYMS */
1271 }
1272
1273 /* Check that an immediate is valid.
1274 If so, convert it to the right format. */
1275
1276 static unsigned int
1277 validate_immediate (val)
1278 unsigned int val;
1279 {
1280 unsigned int a;
1281 unsigned int i;
1282
1283 #define rotate_left(v, n) (v << n | v >> (32 - n))
1284
1285 for (i = 0; i < 32; i += 2)
1286 if ((a = rotate_left (val, i)) <= 0xff)
1287 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
1288
1289 return FAIL;
1290 }
1291
1292 /* Check to see if an immediate can be computed as two seperate immediate
1293 values, added together. We already know that this value cannot be
1294 computed by just one ARM instruction. */
1295
1296 static unsigned int
1297 validate_immediate_twopart (val, highpart)
1298 unsigned int val;
1299 unsigned int * highpart;
1300 {
1301 unsigned int a;
1302 unsigned int i;
1303
1304 for (i = 0; i < 32; i += 2)
1305 if (((a = rotate_left (val, i)) & 0xff) != 0)
1306 {
1307 if (a & 0xff00)
1308 {
1309 if (a & ~ 0xffff)
1310 continue;
1311 * highpart = (a >> 8) | ((i + 24) << 7);
1312 }
1313 else if (a & 0xff0000)
1314 {
1315 if (a & 0xff000000)
1316 continue;
1317 * highpart = (a >> 16) | ((i + 16) << 7);
1318 }
1319 else
1320 {
1321 assert (a & 0xff000000);
1322 * highpart = (a >> 24) | ((i + 8) << 7);
1323 }
1324
1325 return (a & 0xff) | (i << 7);
1326 }
1327
1328 return FAIL;
1329 }
1330
1331 static int
1332 validate_offset_imm (val, hwse)
1333 unsigned int val;
1334 int hwse;
1335 {
1336 if ((hwse && val > 255) || val > 4095)
1337 return FAIL;
1338 return val;
1339 }
1340
1341 static void
1342 s_req (a)
1343 int a ATTRIBUTE_UNUSED;
1344 {
1345 as_bad (_("Invalid syntax for .req directive."));
1346 }
1347
1348 static void
1349 s_bss (ignore)
1350 int ignore ATTRIBUTE_UNUSED;
1351 {
1352 /* We don't support putting frags in the BSS segment, we fake it by
1353 marking in_bss, then looking at s_skip for clues. */
1354 subseg_set (bss_section, 0);
1355 demand_empty_rest_of_line ();
1356 }
1357
1358 static void
1359 s_even (ignore)
1360 int ignore ATTRIBUTE_UNUSED;
1361 {
1362 /* Never make frag if expect extra pass. */
1363 if (!need_pass_2)
1364 frag_align (1, 0, 0);
1365
1366 record_alignment (now_seg, 1);
1367
1368 demand_empty_rest_of_line ();
1369 }
1370
1371 static void
1372 s_ltorg (ignored)
1373 int ignored ATTRIBUTE_UNUSED;
1374 {
1375 int lit_count = 0;
1376 char sym_name[20];
1377
1378 if (current_poolP == NULL)
1379 return;
1380
1381 /* Align pool as you have word accesses.
1382 Only make a frag if we have to. */
1383 if (!need_pass_2)
1384 frag_align (2, 0, 0);
1385
1386 record_alignment (now_seg, 2);
1387
1388 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1389
1390 symbol_locate (current_poolP, sym_name, now_seg,
1391 (valueT) frag_now_fix (), frag_now);
1392 symbol_table_insert (current_poolP);
1393
1394 ARM_SET_THUMB (current_poolP, thumb_mode);
1395
1396 #if defined OBJ_COFF || defined OBJ_ELF
1397 ARM_SET_INTERWORK (current_poolP, support_interwork);
1398 #endif
1399
1400 while (lit_count < next_literal_pool_place)
1401 /* First output the expression in the instruction to the pool. */
1402 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1403
1404 next_literal_pool_place = 0;
1405 current_poolP = NULL;
1406 }
1407
1408 /* Same as s_align_ptwo but align 0 => align 2. */
1409
1410 static void
1411 s_align (unused)
1412 int unused ATTRIBUTE_UNUSED;
1413 {
1414 register int temp;
1415 register long temp_fill;
1416 long max_alignment = 15;
1417
1418 temp = get_absolute_expression ();
1419 if (temp > max_alignment)
1420 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1421 else if (temp < 0)
1422 {
1423 as_bad (_("Alignment negative. 0 assumed."));
1424 temp = 0;
1425 }
1426
1427 if (*input_line_pointer == ',')
1428 {
1429 input_line_pointer++;
1430 temp_fill = get_absolute_expression ();
1431 }
1432 else
1433 temp_fill = 0;
1434
1435 if (!temp)
1436 temp = 2;
1437
1438 /* Only make a frag if we HAVE to. */
1439 if (temp && !need_pass_2)
1440 frag_align (temp, (int) temp_fill, 0);
1441 demand_empty_rest_of_line ();
1442
1443 record_alignment (now_seg, temp);
1444 }
1445
1446 static void
1447 s_force_thumb (ignore)
1448 int ignore ATTRIBUTE_UNUSED;
1449 {
1450 /* If we are not already in thumb mode go into it, EVEN if
1451 the target processor does not support thumb instructions.
1452 This is used by gcc/config/arm/lib1funcs.asm for example
1453 to compile interworking support functions even if the
1454 target processor should not support interworking. */
1455 if (! thumb_mode)
1456 {
1457 thumb_mode = 2;
1458
1459 record_alignment (now_seg, 1);
1460 }
1461
1462 demand_empty_rest_of_line ();
1463 }
1464
1465 static void
1466 s_thumb_func (ignore)
1467 int ignore ATTRIBUTE_UNUSED;
1468 {
1469 if (! thumb_mode)
1470 opcode_select (16);
1471
1472 /* The following label is the name/address of the start of a Thumb function.
1473 We need to know this for the interworking support. */
1474 label_is_thumb_function_name = true;
1475
1476 demand_empty_rest_of_line ();
1477 }
1478
1479 /* Perform a .set directive, but also mark the alias as
1480 being a thumb function. */
1481
1482 static void
1483 s_thumb_set (equiv)
1484 int equiv;
1485 {
1486 /* XXX the following is a duplicate of the code for s_set() in read.c
1487 We cannot just call that code as we need to get at the symbol that
1488 is created. */
1489 register char * name;
1490 register char delim;
1491 register char * end_name;
1492 register symbolS * symbolP;
1493
1494 /* Especial apologies for the random logic:
1495 This just grew, and could be parsed much more simply!
1496 Dean - in haste. */
1497 name = input_line_pointer;
1498 delim = get_symbol_end ();
1499 end_name = input_line_pointer;
1500 *end_name = delim;
1501
1502 SKIP_WHITESPACE ();
1503
1504 if (*input_line_pointer != ',')
1505 {
1506 *end_name = 0;
1507 as_bad (_("Expected comma after name \"%s\""), name);
1508 *end_name = delim;
1509 ignore_rest_of_line ();
1510 return;
1511 }
1512
1513 input_line_pointer++;
1514 *end_name = 0;
1515
1516 if (name[0] == '.' && name[1] == '\0')
1517 {
1518 /* XXX - this should not happen to .thumb_set. */
1519 abort ();
1520 }
1521
1522 if ((symbolP = symbol_find (name)) == NULL
1523 && (symbolP = md_undefined_symbol (name)) == NULL)
1524 {
1525 #ifndef NO_LISTING
1526 /* When doing symbol listings, play games with dummy fragments living
1527 outside the normal fragment chain to record the file and line info
1528 for this symbol. */
1529 if (listing & LISTING_SYMBOLS)
1530 {
1531 extern struct list_info_struct * listing_tail;
1532 fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS));
1533
1534 memset (dummy_frag, 0, sizeof (fragS));
1535 dummy_frag->fr_type = rs_fill;
1536 dummy_frag->line = listing_tail;
1537 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1538 dummy_frag->fr_symbol = symbolP;
1539 }
1540 else
1541 #endif
1542 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1543
1544 #ifdef OBJ_COFF
1545 /* "set" symbols are local unless otherwise specified. */
1546 SF_SET_LOCAL (symbolP);
1547 #endif /* OBJ_COFF */
1548 } /* Make a new symbol. */
1549
1550 symbol_table_insert (symbolP);
1551
1552 * end_name = delim;
1553
1554 if (equiv
1555 && S_IS_DEFINED (symbolP)
1556 && S_GET_SEGMENT (symbolP) != reg_section)
1557 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1558
1559 pseudo_set (symbolP);
1560
1561 demand_empty_rest_of_line ();
1562
1563 /* XXX Now we come to the Thumb specific bit of code. */
1564
1565 THUMB_SET_FUNC (symbolP, 1);
1566 ARM_SET_THUMB (symbolP, 1);
1567 #if defined OBJ_ELF || defined OBJ_COFF
1568 ARM_SET_INTERWORK (symbolP, support_interwork);
1569 #endif
1570 }
1571
1572 /* If we change section we must dump the literal pool first. */
1573
1574 static void
1575 arm_s_text (ignore)
1576 int ignore;
1577 {
1578 if (now_seg != text_section)
1579 s_ltorg (0);
1580
1581 #ifdef OBJ_ELF
1582 obj_elf_text (ignore);
1583 #else
1584 s_text (ignore);
1585 #endif
1586 }
1587
1588 static void
1589 arm_s_data (ignore)
1590 int ignore;
1591 {
1592 if (flag_readonly_data_in_text)
1593 {
1594 if (now_seg != text_section)
1595 s_ltorg (0);
1596 }
1597 else if (now_seg != data_section)
1598 s_ltorg (0);
1599
1600 #ifdef OBJ_ELF
1601 obj_elf_data (ignore);
1602 #else
1603 s_data (ignore);
1604 #endif
1605 }
1606
1607 #ifdef OBJ_ELF
1608 static void
1609 arm_s_section (ignore)
1610 int ignore;
1611 {
1612 s_ltorg (0);
1613
1614 obj_elf_section (ignore);
1615 }
1616 #endif
1617
1618 static void
1619 opcode_select (width)
1620 int width;
1621 {
1622 switch (width)
1623 {
1624 case 16:
1625 if (! thumb_mode)
1626 {
1627 if (! (cpu_variant & ARM_THUMB))
1628 as_bad (_("selected processor does not support THUMB opcodes"));
1629
1630 thumb_mode = 1;
1631 /* No need to force the alignment, since we will have been
1632 coming from ARM mode, which is word-aligned. */
1633 record_alignment (now_seg, 1);
1634 }
1635 break;
1636
1637 case 32:
1638 if (thumb_mode)
1639 {
1640 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1641 as_bad (_("selected processor does not support ARM opcodes"));
1642
1643 thumb_mode = 0;
1644
1645 if (!need_pass_2)
1646 frag_align (2, 0, 0);
1647
1648 record_alignment (now_seg, 1);
1649 }
1650 break;
1651
1652 default:
1653 as_bad (_("invalid instruction size selected (%d)"), width);
1654 }
1655 }
1656
1657 static void
1658 s_arm (ignore)
1659 int ignore ATTRIBUTE_UNUSED;
1660 {
1661 opcode_select (32);
1662 demand_empty_rest_of_line ();
1663 }
1664
1665 static void
1666 s_thumb (ignore)
1667 int ignore ATTRIBUTE_UNUSED;
1668 {
1669 opcode_select (16);
1670 demand_empty_rest_of_line ();
1671 }
1672
1673 static void
1674 s_code (unused)
1675 int unused ATTRIBUTE_UNUSED;
1676 {
1677 register int temp;
1678
1679 temp = get_absolute_expression ();
1680 switch (temp)
1681 {
1682 case 16:
1683 case 32:
1684 opcode_select (temp);
1685 break;
1686
1687 default:
1688 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1689 }
1690 }
1691
1692 static void
1693 end_of_line (str)
1694 char * str;
1695 {
1696 skip_whitespace (str);
1697
1698 if (* str != '\0')
1699 inst.error = _("Garbage following instruction");
1700 }
1701
1702 static int
1703 skip_past_comma (str)
1704 char ** str;
1705 {
1706 char * p = * str, c;
1707 int comma = 0;
1708
1709 while ((c = *p) == ' ' || c == ',')
1710 {
1711 p++;
1712 if (c == ',' && comma++)
1713 return FAIL;
1714 }
1715
1716 if (c == '\0')
1717 return FAIL;
1718
1719 *str = p;
1720 return comma ? SUCCESS : FAIL;
1721 }
1722
1723 /* A standard register must be given at this point.
1724 SHIFT is the place to put it in inst.instruction.
1725 Restores input start point on error.
1726 Returns the reg#, or FAIL. */
1727
1728 static int
1729 reg_required_here (str, shift)
1730 char ** str;
1731 int shift;
1732 {
1733 static char buff [128]; /* XXX */
1734 int reg;
1735 char * start = * str;
1736
1737 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1738 {
1739 if (shift >= 0)
1740 inst.instruction |= reg << shift;
1741 return reg;
1742 }
1743
1744 /* Restore the start point, we may have got a reg of the wrong class. */
1745 *str = start;
1746
1747 /* In the few cases where we might be able to accept something else
1748 this error can be overridden. */
1749 sprintf (buff, _("Register expected, not '%.100s'"), start);
1750 inst.error = buff;
1751
1752 return FAIL;
1753 }
1754
1755 static CONST struct asm_psr *
1756 arm_psr_parse (ccp)
1757 register char ** ccp;
1758 {
1759 char * start = * ccp;
1760 char c;
1761 char * p;
1762 CONST struct asm_psr * psr;
1763
1764 p = start;
1765
1766 /* Skip to the end of the next word in the input stream. */
1767 do
1768 {
1769 c = *p++;
1770 }
1771 while (isalpha (c) || c == '_');
1772
1773 /* Terminate the word. */
1774 *--p = 0;
1775
1776 /* Now locate the word in the psr hash table. */
1777 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
1778
1779 /* Restore the input stream. */
1780 *p = c;
1781
1782 /* If we found a valid match, advance the
1783 stream pointer past the end of the word. */
1784 *ccp = p;
1785
1786 return psr;
1787 }
1788
1789 /* Parse the input looking for a PSR flag. */
1790
1791 static int
1792 psr_required_here (str)
1793 char ** str;
1794 {
1795 char * start = * str;
1796 CONST struct asm_psr * psr;
1797
1798 psr = arm_psr_parse (str);
1799
1800 if (psr)
1801 {
1802 /* If this is the SPSR that is being modified, set the R bit. */
1803 if (! psr->cpsr)
1804 inst.instruction |= SPSR_BIT;
1805
1806 /* Set the psr flags in the MSR instruction. */
1807 inst.instruction |= psr->field << PSR_SHIFT;
1808
1809 return SUCCESS;
1810 }
1811
1812 /* In the few cases where we might be able to accept
1813 something else this error can be overridden. */
1814 inst.error = _("flag for {c}psr instruction expected");
1815
1816 /* Restore the start point. */
1817 *str = start;
1818 return FAIL;
1819 }
1820
1821 static int
1822 co_proc_number (str)
1823 char ** str;
1824 {
1825 int processor, pchar;
1826
1827 skip_whitespace (* str);
1828
1829 /* The data sheet seems to imply that just a number on its own is valid
1830 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1831 accept either. */
1832 if (**str == 'p' || **str == 'P')
1833 (*str)++;
1834
1835 pchar = *(*str)++;
1836 if (pchar >= '0' && pchar <= '9')
1837 {
1838 processor = pchar - '0';
1839 if (**str >= '0' && **str <= '9')
1840 {
1841 processor = processor * 10 + *(*str)++ - '0';
1842 if (processor > 15)
1843 {
1844 inst.error = _("Illegal co-processor number");
1845 return FAIL;
1846 }
1847 }
1848 }
1849 else
1850 {
1851 inst.error = _("Bad or missing co-processor number");
1852 return FAIL;
1853 }
1854
1855 inst.instruction |= processor << 8;
1856 return SUCCESS;
1857 }
1858
1859 static int
1860 cp_opc_expr (str, where, length)
1861 char ** str;
1862 int where;
1863 int length;
1864 {
1865 expressionS expr;
1866
1867 skip_whitespace (* str);
1868
1869 memset (&expr, '\0', sizeof (expr));
1870
1871 if (my_get_expression (&expr, str))
1872 return FAIL;
1873 if (expr.X_op != O_constant)
1874 {
1875 inst.error = _("bad or missing expression");
1876 return FAIL;
1877 }
1878
1879 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1880 {
1881 inst.error = _("immediate co-processor expression too large");
1882 return FAIL;
1883 }
1884
1885 inst.instruction |= expr.X_add_number << where;
1886 return SUCCESS;
1887 }
1888
1889 static int
1890 cp_reg_required_here (str, where)
1891 char ** str;
1892 int where;
1893 {
1894 int reg;
1895 char * start = *str;
1896
1897 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1898 {
1899 reg &= 15;
1900 inst.instruction |= reg << where;
1901 return reg;
1902 }
1903
1904 /* In the few cases where we might be able to accept something else
1905 this error can be overridden. */
1906 inst.error = _("Co-processor register expected");
1907
1908 /* Restore the start point. */
1909 *str = start;
1910 return FAIL;
1911 }
1912
1913 static int
1914 fp_reg_required_here (str, where)
1915 char ** str;
1916 int where;
1917 {
1918 int reg;
1919 char * start = * str;
1920
1921 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1922 {
1923 reg &= 7;
1924 inst.instruction |= reg << where;
1925 return reg;
1926 }
1927
1928 /* In the few cases where we might be able to accept something else
1929 this error can be overridden. */
1930 inst.error = _("Floating point register expected");
1931
1932 /* Restore the start point. */
1933 *str = start;
1934 return FAIL;
1935 }
1936
1937 static int
1938 cp_address_offset (str)
1939 char ** str;
1940 {
1941 int offset;
1942
1943 skip_whitespace (* str);
1944
1945 if (! is_immediate_prefix (**str))
1946 {
1947 inst.error = _("immediate expression expected");
1948 return FAIL;
1949 }
1950
1951 (*str)++;
1952
1953 if (my_get_expression (& inst.reloc.exp, str))
1954 return FAIL;
1955
1956 if (inst.reloc.exp.X_op == O_constant)
1957 {
1958 offset = inst.reloc.exp.X_add_number;
1959
1960 if (offset & 3)
1961 {
1962 inst.error = _("co-processor address must be word aligned");
1963 return FAIL;
1964 }
1965
1966 if (offset > 1023 || offset < -1023)
1967 {
1968 inst.error = _("offset too large");
1969 return FAIL;
1970 }
1971
1972 if (offset >= 0)
1973 inst.instruction |= INDEX_UP;
1974 else
1975 offset = -offset;
1976
1977 inst.instruction |= offset >> 2;
1978 }
1979 else
1980 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1981
1982 return SUCCESS;
1983 }
1984
1985 static int
1986 cp_address_required_here (str)
1987 char ** str;
1988 {
1989 char * p = * str;
1990 int pre_inc = 0;
1991 int write_back = 0;
1992
1993 if (*p == '[')
1994 {
1995 int reg;
1996
1997 p++;
1998 skip_whitespace (p);
1999
2000 if ((reg = reg_required_here (& p, 16)) == FAIL)
2001 return FAIL;
2002
2003 skip_whitespace (p);
2004
2005 if (*p == ']')
2006 {
2007 p++;
2008
2009 if (skip_past_comma (& p) == SUCCESS)
2010 {
2011 /* [Rn], #expr */
2012 write_back = WRITE_BACK;
2013
2014 if (reg == REG_PC)
2015 {
2016 inst.error = _("pc may not be used in post-increment");
2017 return FAIL;
2018 }
2019
2020 if (cp_address_offset (& p) == FAIL)
2021 return FAIL;
2022 }
2023 else
2024 pre_inc = PRE_INDEX | INDEX_UP;
2025 }
2026 else
2027 {
2028 /* '['Rn, #expr']'[!] */
2029
2030 if (skip_past_comma (& p) == FAIL)
2031 {
2032 inst.error = _("pre-indexed expression expected");
2033 return FAIL;
2034 }
2035
2036 pre_inc = PRE_INDEX;
2037
2038 if (cp_address_offset (& p) == FAIL)
2039 return FAIL;
2040
2041 skip_whitespace (p);
2042
2043 if (*p++ != ']')
2044 {
2045 inst.error = _("missing ]");
2046 return FAIL;
2047 }
2048
2049 skip_whitespace (p);
2050
2051 if (*p == '!')
2052 {
2053 if (reg == REG_PC)
2054 {
2055 inst.error = _("pc may not be used with write-back");
2056 return FAIL;
2057 }
2058
2059 p++;
2060 write_back = WRITE_BACK;
2061 }
2062 }
2063 }
2064 else
2065 {
2066 if (my_get_expression (&inst.reloc.exp, &p))
2067 return FAIL;
2068
2069 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
2070 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
2071 inst.reloc.pc_rel = 1;
2072 inst.instruction |= (REG_PC << 16);
2073 pre_inc = PRE_INDEX;
2074 }
2075
2076 inst.instruction |= write_back | pre_inc;
2077 *str = p;
2078 return SUCCESS;
2079 }
2080
2081 static void
2082 do_nop (str, flags)
2083 char * str;
2084 unsigned long flags;
2085 {
2086 /* Do nothing really. */
2087 inst.instruction |= flags; /* This is pointless. */
2088 end_of_line (str);
2089 return;
2090 }
2091
2092 static void
2093 do_mrs (str, flags)
2094 char *str;
2095 unsigned long flags;
2096 {
2097 int skip = 0;
2098
2099 /* Only one syntax. */
2100 skip_whitespace (str);
2101
2102 if (reg_required_here (&str, 12) == FAIL)
2103 {
2104 inst.error = BAD_ARGS;
2105 return;
2106 }
2107
2108 if (skip_past_comma (&str) == FAIL)
2109 {
2110 inst.error = _("comma expected after register name");
2111 return;
2112 }
2113
2114 skip_whitespace (str);
2115
2116 if ( strcmp (str, "CPSR") == 0
2117 || strcmp (str, "SPSR") == 0
2118 /* Lower case versions for backwards compatability. */
2119 || strcmp (str, "cpsr") == 0
2120 || strcmp (str, "spsr") == 0)
2121 skip = 4;
2122
2123 /* This is for backwards compatability with older toolchains. */
2124 else if ( strcmp (str, "cpsr_all") == 0
2125 || strcmp (str, "spsr_all") == 0)
2126 skip = 8;
2127 else
2128 {
2129 inst.error = _("{C|S}PSR expected");
2130 return;
2131 }
2132
2133 if (* str == 's' || * str == 'S')
2134 inst.instruction |= SPSR_BIT;
2135 str += skip;
2136
2137 inst.instruction |= flags;
2138 end_of_line (str);
2139 }
2140
2141 /* Two possible forms:
2142 "{C|S}PSR_<field>, Rm",
2143 "{C|S}PSR_f, #expression". */
2144
2145 static void
2146 do_msr (str, flags)
2147 char * str;
2148 unsigned long flags;
2149 {
2150 skip_whitespace (str);
2151
2152 if (psr_required_here (& str) == FAIL)
2153 return;
2154
2155 if (skip_past_comma (& str) == FAIL)
2156 {
2157 inst.error = _("comma missing after psr flags");
2158 return;
2159 }
2160
2161 skip_whitespace (str);
2162
2163 if (reg_required_here (& str, 0) != FAIL)
2164 {
2165 inst.error = NULL;
2166 inst.instruction |= flags;
2167 end_of_line (str);
2168 return;
2169 }
2170
2171 if (! is_immediate_prefix (* str))
2172 {
2173 inst.error =
2174 _("only a register or immediate value can follow a psr flag");
2175 return;
2176 }
2177
2178 str ++;
2179 inst.error = NULL;
2180
2181 if (my_get_expression (& inst.reloc.exp, & str))
2182 {
2183 inst.error =
2184 _("only a register or immediate value can follow a psr flag");
2185 return;
2186 }
2187
2188 if (inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
2189 {
2190 inst.error = _("can only set flag field with immediate value");
2191 return;
2192 }
2193
2194 flags |= INST_IMMEDIATE;
2195
2196 if (inst.reloc.exp.X_add_symbol)
2197 {
2198 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2199 inst.reloc.pc_rel = 0;
2200 }
2201 else
2202 {
2203 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
2204
2205 if (value == (unsigned) FAIL)
2206 {
2207 inst.error = _("Invalid constant");
2208 return;
2209 }
2210
2211 inst.instruction |= value;
2212 }
2213
2214 inst.error = NULL;
2215 inst.instruction |= flags;
2216 end_of_line (str);
2217 }
2218
2219 /* Long Multiply Parser
2220 UMULL RdLo, RdHi, Rm, Rs
2221 SMULL RdLo, RdHi, Rm, Rs
2222 UMLAL RdLo, RdHi, Rm, Rs
2223 SMLAL RdLo, RdHi, Rm, Rs. */
2224
2225 static void
2226 do_mull (str, flags)
2227 char * str;
2228 unsigned long flags;
2229 {
2230 int rdlo, rdhi, rm, rs;
2231
2232 /* Only one format "rdlo, rdhi, rm, rs". */
2233 skip_whitespace (str);
2234
2235 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
2236 {
2237 inst.error = BAD_ARGS;
2238 return;
2239 }
2240
2241 if (skip_past_comma (&str) == FAIL
2242 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2243 {
2244 inst.error = BAD_ARGS;
2245 return;
2246 }
2247
2248 if (skip_past_comma (&str) == FAIL
2249 || (rm = reg_required_here (&str, 0)) == FAIL)
2250 {
2251 inst.error = BAD_ARGS;
2252 return;
2253 }
2254
2255 /* rdhi, rdlo and rm must all be different. */
2256 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2257 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2258
2259 if (skip_past_comma (&str) == FAIL
2260 || (rs = reg_required_here (&str, 8)) == FAIL)
2261 {
2262 inst.error = BAD_ARGS;
2263 return;
2264 }
2265
2266 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2267 {
2268 inst.error = BAD_PC;
2269 return;
2270 }
2271
2272 inst.instruction |= flags;
2273 end_of_line (str);
2274 return;
2275 }
2276
2277 static void
2278 do_mul (str, flags)
2279 char * str;
2280 unsigned long flags;
2281 {
2282 int rd, rm;
2283
2284 /* Only one format "rd, rm, rs". */
2285 skip_whitespace (str);
2286
2287 if ((rd = reg_required_here (&str, 16)) == FAIL)
2288 {
2289 inst.error = BAD_ARGS;
2290 return;
2291 }
2292
2293 if (rd == REG_PC)
2294 {
2295 inst.error = BAD_PC;
2296 return;
2297 }
2298
2299 if (skip_past_comma (&str) == FAIL
2300 || (rm = reg_required_here (&str, 0)) == FAIL)
2301 {
2302 inst.error = BAD_ARGS;
2303 return;
2304 }
2305
2306 if (rm == REG_PC)
2307 {
2308 inst.error = BAD_PC;
2309 return;
2310 }
2311
2312 if (rm == rd)
2313 as_tsktsk (_("rd and rm should be different in mul"));
2314
2315 if (skip_past_comma (&str) == FAIL
2316 || (rm = reg_required_here (&str, 8)) == FAIL)
2317 {
2318 inst.error = BAD_ARGS;
2319 return;
2320 }
2321
2322 if (rm == REG_PC)
2323 {
2324 inst.error = BAD_PC;
2325 return;
2326 }
2327
2328 inst.instruction |= flags;
2329 end_of_line (str);
2330 return;
2331 }
2332
2333 static void
2334 do_mla (str, flags)
2335 char * str;
2336 unsigned long flags;
2337 {
2338 int rd, rm;
2339
2340 /* Only one format "rd, rm, rs, rn". */
2341 skip_whitespace (str);
2342
2343 if ((rd = reg_required_here (&str, 16)) == FAIL)
2344 {
2345 inst.error = BAD_ARGS;
2346 return;
2347 }
2348
2349 if (rd == REG_PC)
2350 {
2351 inst.error = BAD_PC;
2352 return;
2353 }
2354
2355 if (skip_past_comma (&str) == FAIL
2356 || (rm = reg_required_here (&str, 0)) == FAIL)
2357 {
2358 inst.error = BAD_ARGS;
2359 return;
2360 }
2361
2362 if (rm == REG_PC)
2363 {
2364 inst.error = BAD_PC;
2365 return;
2366 }
2367
2368 if (rm == rd)
2369 as_tsktsk (_("rd and rm should be different in mla"));
2370
2371 if (skip_past_comma (&str) == FAIL
2372 || (rd = reg_required_here (&str, 8)) == FAIL
2373 || skip_past_comma (&str) == FAIL
2374 || (rm = reg_required_here (&str, 12)) == FAIL)
2375 {
2376 inst.error = BAD_ARGS;
2377 return;
2378 }
2379
2380 if (rd == REG_PC || rm == REG_PC)
2381 {
2382 inst.error = BAD_PC;
2383 return;
2384 }
2385
2386 inst.instruction |= flags;
2387 end_of_line (str);
2388 return;
2389 }
2390
2391 /* Returns the index into fp_values of a floating point number,
2392 or -1 if not in the table. */
2393
2394 static int
2395 my_get_float_expression (str)
2396 char ** str;
2397 {
2398 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2399 char * save_in;
2400 expressionS exp;
2401 int i;
2402 int j;
2403
2404 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2405
2406 /* Look for a raw floating point number. */
2407 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2408 && is_end_of_line[(unsigned char) *save_in])
2409 {
2410 for (i = 0; i < NUM_FLOAT_VALS; i++)
2411 {
2412 for (j = 0; j < MAX_LITTLENUMS; j++)
2413 {
2414 if (words[j] != fp_values[i][j])
2415 break;
2416 }
2417
2418 if (j == MAX_LITTLENUMS)
2419 {
2420 *str = save_in;
2421 return i;
2422 }
2423 }
2424 }
2425
2426 /* Try and parse a more complex expression, this will probably fail
2427 unless the code uses a floating point prefix (eg "0f"). */
2428 save_in = input_line_pointer;
2429 input_line_pointer = *str;
2430 if (expression (&exp) == absolute_section
2431 && exp.X_op == O_big
2432 && exp.X_add_number < 0)
2433 {
2434 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2435 Ditto for 15. */
2436 if (gen_to_words (words, 5, (long) 15) == 0)
2437 {
2438 for (i = 0; i < NUM_FLOAT_VALS; i++)
2439 {
2440 for (j = 0; j < MAX_LITTLENUMS; j++)
2441 {
2442 if (words[j] != fp_values[i][j])
2443 break;
2444 }
2445
2446 if (j == MAX_LITTLENUMS)
2447 {
2448 *str = input_line_pointer;
2449 input_line_pointer = save_in;
2450 return i;
2451 }
2452 }
2453 }
2454 }
2455
2456 *str = input_line_pointer;
2457 input_line_pointer = save_in;
2458 return -1;
2459 }
2460
2461 /* Return true if anything in the expression is a bignum. */
2462
2463 static int
2464 walk_no_bignums (sp)
2465 symbolS * sp;
2466 {
2467 if (symbol_get_value_expression (sp)->X_op == O_big)
2468 return 1;
2469
2470 if (symbol_get_value_expression (sp)->X_add_symbol)
2471 {
2472 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2473 || (symbol_get_value_expression (sp)->X_op_symbol
2474 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2475 }
2476
2477 return 0;
2478 }
2479
2480 static int
2481 my_get_expression (ep, str)
2482 expressionS * ep;
2483 char ** str;
2484 {
2485 char * save_in;
2486 segT seg;
2487
2488 save_in = input_line_pointer;
2489 input_line_pointer = *str;
2490 seg = expression (ep);
2491
2492 #ifdef OBJ_AOUT
2493 if (seg != absolute_section
2494 && seg != text_section
2495 && seg != data_section
2496 && seg != bss_section
2497 && seg != undefined_section)
2498 {
2499 inst.error = _("bad_segment");
2500 *str = input_line_pointer;
2501 input_line_pointer = save_in;
2502 return 1;
2503 }
2504 #endif
2505
2506 /* Get rid of any bignums now, so that we don't generate an error for which
2507 we can't establish a line number later on. Big numbers are never valid
2508 in instructions, which is where this routine is always called. */
2509 if (ep->X_op == O_big
2510 || (ep->X_add_symbol
2511 && (walk_no_bignums (ep->X_add_symbol)
2512 || (ep->X_op_symbol
2513 && walk_no_bignums (ep->X_op_symbol)))))
2514 {
2515 inst.error = _("Invalid constant");
2516 *str = input_line_pointer;
2517 input_line_pointer = save_in;
2518 return 1;
2519 }
2520
2521 *str = input_line_pointer;
2522 input_line_pointer = save_in;
2523 return 0;
2524 }
2525
2526 /* UNRESTRICT should be one if <shift> <register> is permitted for this
2527 instruction. */
2528
2529 static int
2530 decode_shift (str, unrestrict)
2531 char ** str;
2532 int unrestrict;
2533 {
2534 struct asm_shift_name * shift;
2535 char * p;
2536 char c;
2537
2538 skip_whitespace (* str);
2539
2540 for (p = * str; isalpha (* p); p ++)
2541 ;
2542
2543 if (p == * str)
2544 {
2545 inst.error = _("Shift expression expected");
2546 return FAIL;
2547 }
2548
2549 c = * p;
2550 * p = '\0';
2551 shift = (struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
2552 * p = c;
2553
2554 if (shift == NULL)
2555 {
2556 inst.error = _("Shift expression expected");
2557 return FAIL;
2558 }
2559
2560 assert (shift->properties->index == shift_properties[shift->properties->index].index);
2561
2562 if (shift->properties->index == SHIFT_RRX)
2563 {
2564 * str = p;
2565 inst.instruction |= shift->properties->bit_field;
2566 return SUCCESS;
2567 }
2568
2569 skip_whitespace (p);
2570
2571 if (unrestrict && reg_required_here (& p, 8) != FAIL)
2572 {
2573 inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
2574 * str = p;
2575 return SUCCESS;
2576 }
2577 else if (! is_immediate_prefix (* p))
2578 {
2579 inst.error = (unrestrict
2580 ? _("shift requires register or #expression")
2581 : _("shift requires #expression"));
2582 * str = p;
2583 return FAIL;
2584 }
2585
2586 inst.error = NULL;
2587 p ++;
2588
2589 if (my_get_expression (& inst.reloc.exp, & p))
2590 return FAIL;
2591
2592 /* Validate some simple #expressions. */
2593 if (inst.reloc.exp.X_op == O_constant)
2594 {
2595 unsigned num = inst.reloc.exp.X_add_number;
2596
2597 /* Reject operations greater than 32. */
2598 if (num > 32
2599 /* Reject a shift of 0 unless the mode allows it. */
2600 || (num == 0 && shift->properties->allows_0 == 0)
2601 /* Reject a shift of 32 unless the mode allows it. */
2602 || (num == 32 && shift->properties->allows_32 == 0)
2603 )
2604 {
2605 /* As a special case we allow ROR #0, but we issue a message
2606 reminding the programmer that this is actually an RRX. */
2607 if (num == 0 && shift->properties->index == SHIFT_ROR)
2608 as_tsktsk (_("ROR #0 is actually RRX"));
2609 else
2610 {
2611 inst.error = _("Invalid immediate shift");
2612 return FAIL;
2613 }
2614 }
2615
2616 /* Shifts of 32 are encoded as 0, for those shifts that
2617 support it. */
2618 if (num == 32)
2619 num = 0;
2620
2621 inst.instruction |= (num << 7) | shift->properties->bit_field;
2622 }
2623 else
2624 {
2625 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2626 inst.reloc.pc_rel = 0;
2627 inst.instruction |= shift->properties->bit_field;
2628 }
2629
2630 * str = p;
2631 return SUCCESS;
2632 }
2633
2634 /* Do those data_ops which can take a negative immediate constant
2635 by altering the instuction. A bit of a hack really.
2636 MOV <-> MVN
2637 AND <-> BIC
2638 ADC <-> SBC
2639 by inverting the second operand, and
2640 ADD <-> SUB
2641 CMP <-> CMN
2642 by negating the second operand. */
2643
2644 static int
2645 negate_data_op (instruction, value)
2646 unsigned long * instruction;
2647 unsigned long value;
2648 {
2649 int op, new_inst;
2650 unsigned long negated, inverted;
2651
2652 negated = validate_immediate (-value);
2653 inverted = validate_immediate (~value);
2654
2655 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2656 switch (op)
2657 {
2658 /* First negates. */
2659 case OPCODE_SUB: /* ADD <-> SUB */
2660 new_inst = OPCODE_ADD;
2661 value = negated;
2662 break;
2663
2664 case OPCODE_ADD:
2665 new_inst = OPCODE_SUB;
2666 value = negated;
2667 break;
2668
2669 case OPCODE_CMP: /* CMP <-> CMN */
2670 new_inst = OPCODE_CMN;
2671 value = negated;
2672 break;
2673
2674 case OPCODE_CMN:
2675 new_inst = OPCODE_CMP;
2676 value = negated;
2677 break;
2678
2679 /* Now Inverted ops. */
2680 case OPCODE_MOV: /* MOV <-> MVN */
2681 new_inst = OPCODE_MVN;
2682 value = inverted;
2683 break;
2684
2685 case OPCODE_MVN:
2686 new_inst = OPCODE_MOV;
2687 value = inverted;
2688 break;
2689
2690 case OPCODE_AND: /* AND <-> BIC */
2691 new_inst = OPCODE_BIC;
2692 value = inverted;
2693 break;
2694
2695 case OPCODE_BIC:
2696 new_inst = OPCODE_AND;
2697 value = inverted;
2698 break;
2699
2700 case OPCODE_ADC: /* ADC <-> SBC */
2701 new_inst = OPCODE_SBC;
2702 value = inverted;
2703 break;
2704
2705 case OPCODE_SBC:
2706 new_inst = OPCODE_ADC;
2707 value = inverted;
2708 break;
2709
2710 /* We cannot do anything. */
2711 default:
2712 return FAIL;
2713 }
2714
2715 if (value == (unsigned) FAIL)
2716 return FAIL;
2717
2718 *instruction &= OPCODE_MASK;
2719 *instruction |= new_inst << DATA_OP_SHIFT;
2720 return value;
2721 }
2722
2723 static int
2724 data_op2 (str)
2725 char ** str;
2726 {
2727 int value;
2728 expressionS expr;
2729
2730 skip_whitespace (* str);
2731
2732 if (reg_required_here (str, 0) != FAIL)
2733 {
2734 if (skip_past_comma (str) == SUCCESS)
2735 /* Shift operation on register. */
2736 return decode_shift (str, NO_SHIFT_RESTRICT);
2737
2738 return SUCCESS;
2739 }
2740 else
2741 {
2742 /* Immediate expression. */
2743 if (is_immediate_prefix (**str))
2744 {
2745 (*str)++;
2746 inst.error = NULL;
2747
2748 if (my_get_expression (&inst.reloc.exp, str))
2749 return FAIL;
2750
2751 if (inst.reloc.exp.X_add_symbol)
2752 {
2753 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2754 inst.reloc.pc_rel = 0;
2755 }
2756 else
2757 {
2758 if (skip_past_comma (str) == SUCCESS)
2759 {
2760 /* #x, y -- ie explicit rotation by Y. */
2761 if (my_get_expression (&expr, str))
2762 return FAIL;
2763
2764 if (expr.X_op != O_constant)
2765 {
2766 inst.error = _("Constant expression expected");
2767 return FAIL;
2768 }
2769
2770 /* Rotate must be a multiple of 2. */
2771 if (((unsigned) expr.X_add_number) > 30
2772 || (expr.X_add_number & 1) != 0
2773 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2774 {
2775 inst.error = _("Invalid constant");
2776 return FAIL;
2777 }
2778 inst.instruction |= INST_IMMEDIATE;
2779 inst.instruction |= inst.reloc.exp.X_add_number;
2780 inst.instruction |= expr.X_add_number << 7;
2781 return SUCCESS;
2782 }
2783
2784 /* Implicit rotation, select a suitable one. */
2785 value = validate_immediate (inst.reloc.exp.X_add_number);
2786
2787 if (value == FAIL)
2788 {
2789 /* Can't be done. Perhaps the code reads something like
2790 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
2791 if ((value = negate_data_op (&inst.instruction,
2792 inst.reloc.exp.X_add_number))
2793 == FAIL)
2794 {
2795 inst.error = _("Invalid constant");
2796 return FAIL;
2797 }
2798 }
2799
2800 inst.instruction |= value;
2801 }
2802
2803 inst.instruction |= INST_IMMEDIATE;
2804 return SUCCESS;
2805 }
2806
2807 (*str)++;
2808 inst.error = _("Register or shift expression expected");
2809 return FAIL;
2810 }
2811 }
2812
2813 static int
2814 fp_op2 (str)
2815 char ** str;
2816 {
2817 skip_whitespace (* str);
2818
2819 if (fp_reg_required_here (str, 0) != FAIL)
2820 return SUCCESS;
2821 else
2822 {
2823 /* Immediate expression. */
2824 if (*((*str)++) == '#')
2825 {
2826 int i;
2827
2828 inst.error = NULL;
2829
2830 skip_whitespace (* str);
2831
2832 /* First try and match exact strings, this is to guarantee
2833 that some formats will work even for cross assembly. */
2834
2835 for (i = 0; fp_const[i]; i++)
2836 {
2837 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2838 {
2839 char *start = *str;
2840
2841 *str += strlen (fp_const[i]);
2842 if (is_end_of_line[(unsigned char) **str])
2843 {
2844 inst.instruction |= i + 8;
2845 return SUCCESS;
2846 }
2847 *str = start;
2848 }
2849 }
2850
2851 /* Just because we didn't get a match doesn't mean that the
2852 constant isn't valid, just that it is in a format that we
2853 don't automatically recognize. Try parsing it with
2854 the standard expression routines. */
2855 if ((i = my_get_float_expression (str)) >= 0)
2856 {
2857 inst.instruction |= i + 8;
2858 return SUCCESS;
2859 }
2860
2861 inst.error = _("Invalid floating point immediate expression");
2862 return FAIL;
2863 }
2864 inst.error =
2865 _("Floating point register or immediate expression expected");
2866 return FAIL;
2867 }
2868 }
2869
2870 static void
2871 do_arit (str, flags)
2872 char * str;
2873 unsigned long flags;
2874 {
2875 skip_whitespace (str);
2876
2877 if (reg_required_here (&str, 12) == FAIL
2878 || skip_past_comma (&str) == FAIL
2879 || reg_required_here (&str, 16) == FAIL
2880 || skip_past_comma (&str) == FAIL
2881 || data_op2 (&str) == FAIL)
2882 {
2883 if (!inst.error)
2884 inst.error = BAD_ARGS;
2885 return;
2886 }
2887
2888 inst.instruction |= flags;
2889 end_of_line (str);
2890 return;
2891 }
2892
2893 static void
2894 do_adr (str, flags)
2895 char * str;
2896 unsigned long flags;
2897 {
2898 /* This is a pseudo-op of the form "adr rd, label" to be converted
2899 into a relative address of the form "add rd, pc, #label-.-8". */
2900 skip_whitespace (str);
2901
2902 if (reg_required_here (&str, 12) == FAIL
2903 || skip_past_comma (&str) == FAIL
2904 || my_get_expression (&inst.reloc.exp, &str))
2905 {
2906 if (!inst.error)
2907 inst.error = BAD_ARGS;
2908 return;
2909 }
2910
2911 /* Frag hacking will turn this into a sub instruction if the offset turns
2912 out to be negative. */
2913 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2914 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
2915 inst.reloc.pc_rel = 1;
2916 inst.instruction |= flags;
2917
2918 end_of_line (str);
2919 }
2920
2921 static void
2922 do_adrl (str, flags)
2923 char * str;
2924 unsigned long flags;
2925 {
2926 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2927 into a relative address of the form:
2928 add rd, pc, #low(label-.-8)"
2929 add rd, rd, #high(label-.-8)" */
2930
2931 skip_whitespace (str);
2932
2933 if (reg_required_here (& str, 12) == FAIL
2934 || skip_past_comma (& str) == FAIL
2935 || my_get_expression (& inst.reloc.exp, & str))
2936 {
2937 if (!inst.error)
2938 inst.error = BAD_ARGS;
2939 return;
2940 }
2941
2942 end_of_line (str);
2943
2944 /* Frag hacking will turn this into a sub instruction if the offset turns
2945 out to be negative. */
2946 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2947 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2948 inst.reloc.pc_rel = 1;
2949 inst.instruction |= flags;
2950 inst.size = INSN_SIZE * 2;
2951
2952 return;
2953 }
2954
2955 static void
2956 do_cmp (str, flags)
2957 char * str;
2958 unsigned long flags;
2959 {
2960 skip_whitespace (str);
2961
2962 if (reg_required_here (&str, 16) == FAIL)
2963 {
2964 if (!inst.error)
2965 inst.error = BAD_ARGS;
2966 return;
2967 }
2968
2969 if (skip_past_comma (&str) == FAIL
2970 || data_op2 (&str) == FAIL)
2971 {
2972 if (!inst.error)
2973 inst.error = BAD_ARGS;
2974 return;
2975 }
2976
2977 inst.instruction |= flags;
2978 if ((flags & 0x0000f000) == 0)
2979 inst.instruction |= CONDS_BIT;
2980
2981 end_of_line (str);
2982 return;
2983 }
2984
2985 static void
2986 do_mov (str, flags)
2987 char * str;
2988 unsigned long flags;
2989 {
2990 skip_whitespace (str);
2991
2992 if (reg_required_here (&str, 12) == FAIL)
2993 {
2994 if (!inst.error)
2995 inst.error = BAD_ARGS;
2996 return;
2997 }
2998
2999 if (skip_past_comma (&str) == FAIL
3000 || data_op2 (&str) == FAIL)
3001 {
3002 if (!inst.error)
3003 inst.error = BAD_ARGS;
3004 return;
3005 }
3006
3007 inst.instruction |= flags;
3008 end_of_line (str);
3009 return;
3010 }
3011
3012 static int
3013 ldst_extend (str, hwse)
3014 char ** str;
3015 int hwse;
3016 {
3017 int add = INDEX_UP;
3018
3019 switch (**str)
3020 {
3021 case '#':
3022 case '$':
3023 (*str)++;
3024 if (my_get_expression (& inst.reloc.exp, str))
3025 return FAIL;
3026
3027 if (inst.reloc.exp.X_op == O_constant)
3028 {
3029 int value = inst.reloc.exp.X_add_number;
3030
3031 if ((hwse && (value < -255 || value > 255))
3032 || (value < -4095 || value > 4095))
3033 {
3034 inst.error = _("address offset too large");
3035 return FAIL;
3036 }
3037
3038 if (value < 0)
3039 {
3040 value = -value;
3041 add = 0;
3042 }
3043
3044 /* Halfword and signextension instructions have the
3045 immediate value split across bits 11..8 and bits 3..0. */
3046 if (hwse)
3047 inst.instruction |= (add | HWOFFSET_IMM
3048 | ((value >> 4) << 8) | (value & 0xF));
3049 else
3050 inst.instruction |= add | value;
3051 }
3052 else
3053 {
3054 if (hwse)
3055 {
3056 inst.instruction |= HWOFFSET_IMM;
3057 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3058 }
3059 else
3060 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3061 inst.reloc.pc_rel = 0;
3062 }
3063 return SUCCESS;
3064
3065 case '-':
3066 add = 0;
3067 /* Fall through. */
3068
3069 case '+':
3070 (*str)++;
3071 /* Fall through. */
3072
3073 default:
3074 if (reg_required_here (str, 0) == FAIL)
3075 return FAIL;
3076
3077 if (hwse)
3078 inst.instruction |= add;
3079 else
3080 {
3081 inst.instruction |= add | OFFSET_REG;
3082 if (skip_past_comma (str) == SUCCESS)
3083 return decode_shift (str, SHIFT_RESTRICT);
3084 }
3085
3086 return SUCCESS;
3087 }
3088 }
3089
3090 static void
3091 do_ldst (str, flags)
3092 char *str;
3093 unsigned long flags;
3094 {
3095 int halfword = 0;
3096 int pre_inc = 0;
3097 int conflict_reg;
3098 int value;
3099
3100 /* This is not ideal, but it is the simplest way of dealing with the
3101 ARM7T halfword instructions (since they use a different
3102 encoding, but the same mnemonic): */
3103 halfword = (flags & 0x80000000) != 0;
3104 if (halfword)
3105 {
3106 /* This is actually a load/store of a halfword, or a
3107 signed-extension load. */
3108 if ((cpu_variant & ARM_HALFWORD) == 0)
3109 {
3110 inst.error
3111 = _("Processor does not support halfwords or signed bytes");
3112 return;
3113 }
3114
3115 inst.instruction = ((inst.instruction & COND_MASK)
3116 | (flags & ~COND_MASK));
3117
3118 flags = 0;
3119 }
3120
3121 skip_whitespace (str);
3122
3123 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
3124 {
3125 if (!inst.error)
3126 inst.error = BAD_ARGS;
3127 return;
3128 }
3129
3130 if (skip_past_comma (& str) == FAIL)
3131 {
3132 inst.error = _("Address expected");
3133 return;
3134 }
3135
3136 if (*str == '[')
3137 {
3138 int reg;
3139
3140 str++;
3141
3142 skip_whitespace (str);
3143
3144 if ((reg = reg_required_here (&str, 16)) == FAIL)
3145 return;
3146
3147 /* Conflicts can occur on stores as well as loads. */
3148 conflict_reg = (conflict_reg == reg);
3149
3150 skip_whitespace (str);
3151
3152 if (*str == ']')
3153 {
3154 str ++;
3155
3156 if (skip_past_comma (&str) == SUCCESS)
3157 {
3158 /* [Rn],... (post inc) */
3159 if (ldst_extend (&str, halfword) == FAIL)
3160 return;
3161 if (conflict_reg)
3162 as_warn (_("%s register same as write-back base"),
3163 ((inst.instruction & LOAD_BIT)
3164 ? _("destination") : _("source")));
3165 }
3166 else
3167 {
3168 /* [Rn] */
3169 if (halfword)
3170 inst.instruction |= HWOFFSET_IMM;
3171
3172 skip_whitespace (str);
3173
3174 if (*str == '!')
3175 {
3176 if (conflict_reg)
3177 as_warn (_("%s register same as write-back base"),
3178 ((inst.instruction & LOAD_BIT)
3179 ? _("destination") : _("source")));
3180 str++;
3181 inst.instruction |= WRITE_BACK;
3182 }
3183
3184 flags |= INDEX_UP;
3185 if (! (flags & TRANS_BIT))
3186 pre_inc = 1;
3187 }
3188 }
3189 else
3190 {
3191 /* [Rn,...] */
3192 if (skip_past_comma (&str) == FAIL)
3193 {
3194 inst.error = _("pre-indexed expression expected");
3195 return;
3196 }
3197
3198 pre_inc = 1;
3199 if (ldst_extend (&str, halfword) == FAIL)
3200 return;
3201
3202 skip_whitespace (str);
3203
3204 if (*str++ != ']')
3205 {
3206 inst.error = _("missing ]");
3207 return;
3208 }
3209
3210 skip_whitespace (str);
3211
3212 if (*str == '!')
3213 {
3214 if (conflict_reg)
3215 as_warn (_("%s register same as write-back base"),
3216 ((inst.instruction & LOAD_BIT)
3217 ? _("destination") : _("source")));
3218 str++;
3219 inst.instruction |= WRITE_BACK;
3220 }
3221 }
3222 }
3223 else if (*str == '=')
3224 {
3225 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
3226 str++;
3227
3228 skip_whitespace (str);
3229
3230 if (my_get_expression (&inst.reloc.exp, &str))
3231 return;
3232
3233 if (inst.reloc.exp.X_op != O_constant
3234 && inst.reloc.exp.X_op != O_symbol)
3235 {
3236 inst.error = _("Constant expression expected");
3237 return;
3238 }
3239
3240 if (inst.reloc.exp.X_op == O_constant
3241 && (value = validate_immediate (inst.reloc.exp.X_add_number)) != FAIL)
3242 {
3243 /* This can be done with a mov instruction. */
3244 inst.instruction &= LITERAL_MASK;
3245 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
3246 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
3247 end_of_line (str);
3248 return;
3249 }
3250 else
3251 {
3252 /* Insert into literal pool. */
3253 if (add_to_lit_pool () == FAIL)
3254 {
3255 if (!inst.error)
3256 inst.error = _("literal pool insertion failed");
3257 return;
3258 }
3259
3260 /* Change the instruction exp to point to the pool. */
3261 if (halfword)
3262 {
3263 inst.instruction |= HWOFFSET_IMM;
3264 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
3265 }
3266 else
3267 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
3268 inst.reloc.pc_rel = 1;
3269 inst.instruction |= (REG_PC << 16);
3270 pre_inc = 1;
3271 }
3272 }
3273 else
3274 {
3275 if (my_get_expression (&inst.reloc.exp, &str))
3276 return;
3277
3278 if (halfword)
3279 {
3280 inst.instruction |= HWOFFSET_IMM;
3281 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3282 }
3283 else
3284 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3285 #ifndef TE_WINCE
3286 /* PC rel adjust. */
3287 inst.reloc.exp.X_add_number -= 8;
3288 #endif
3289 inst.reloc.pc_rel = 1;
3290 inst.instruction |= (REG_PC << 16);
3291 pre_inc = 1;
3292 }
3293
3294 if (pre_inc && (flags & TRANS_BIT))
3295 inst.error = _("Pre-increment instruction with translate");
3296
3297 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3298 end_of_line (str);
3299 return;
3300 }
3301
3302 static long
3303 reg_list (strp)
3304 char ** strp;
3305 {
3306 char * str = * strp;
3307 long range = 0;
3308 int another_range;
3309
3310 /* We come back here if we get ranges concatenated by '+' or '|'. */
3311 do
3312 {
3313 another_range = 0;
3314
3315 if (*str == '{')
3316 {
3317 int in_range = 0;
3318 int cur_reg = -1;
3319
3320 str++;
3321 do
3322 {
3323 int reg;
3324
3325 skip_whitespace (str);
3326
3327 if ((reg = reg_required_here (& str, -1)) == FAIL)
3328 return FAIL;
3329
3330 if (in_range)
3331 {
3332 int i;
3333
3334 if (reg <= cur_reg)
3335 {
3336 inst.error = _("Bad range in register list");
3337 return FAIL;
3338 }
3339
3340 for (i = cur_reg + 1; i < reg; i++)
3341 {
3342 if (range & (1 << i))
3343 as_tsktsk
3344 (_("Warning: Duplicated register (r%d) in register list"),
3345 i);
3346 else
3347 range |= 1 << i;
3348 }
3349 in_range = 0;
3350 }
3351
3352 if (range & (1 << reg))
3353 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3354 reg);
3355 else if (reg <= cur_reg)
3356 as_tsktsk (_("Warning: Register range not in ascending order"));
3357
3358 range |= 1 << reg;
3359 cur_reg = reg;
3360 }
3361 while (skip_past_comma (&str) != FAIL
3362 || (in_range = 1, *str++ == '-'));
3363 str--;
3364 skip_whitespace (str);
3365
3366 if (*str++ != '}')
3367 {
3368 inst.error = _("Missing `}'");
3369 return FAIL;
3370 }
3371 }
3372 else
3373 {
3374 expressionS expr;
3375
3376 if (my_get_expression (&expr, &str))
3377 return FAIL;
3378
3379 if (expr.X_op == O_constant)
3380 {
3381 if (expr.X_add_number
3382 != (expr.X_add_number & 0x0000ffff))
3383 {
3384 inst.error = _("invalid register mask");
3385 return FAIL;
3386 }
3387
3388 if ((range & expr.X_add_number) != 0)
3389 {
3390 int regno = range & expr.X_add_number;
3391
3392 regno &= -regno;
3393 regno = (1 << regno) - 1;
3394 as_tsktsk
3395 (_("Warning: Duplicated register (r%d) in register list"),
3396 regno);
3397 }
3398
3399 range |= expr.X_add_number;
3400 }
3401 else
3402 {
3403 if (inst.reloc.type != 0)
3404 {
3405 inst.error = _("expression too complex");
3406 return FAIL;
3407 }
3408
3409 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3410 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3411 inst.reloc.pc_rel = 0;
3412 }
3413 }
3414
3415 skip_whitespace (str);
3416
3417 if (*str == '|' || *str == '+')
3418 {
3419 str++;
3420 another_range = 1;
3421 }
3422 }
3423 while (another_range);
3424
3425 *strp = str;
3426 return range;
3427 }
3428
3429 static void
3430 do_ldmstm (str, flags)
3431 char * str;
3432 unsigned long flags;
3433 {
3434 int base_reg;
3435 long range;
3436
3437 skip_whitespace (str);
3438
3439 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3440 return;
3441
3442 if (base_reg == REG_PC)
3443 {
3444 inst.error = _("r15 not allowed as base register");
3445 return;
3446 }
3447
3448 skip_whitespace (str);
3449
3450 if (*str == '!')
3451 {
3452 flags |= WRITE_BACK;
3453 str++;
3454 }
3455
3456 if (skip_past_comma (&str) == FAIL
3457 || (range = reg_list (&str)) == FAIL)
3458 {
3459 if (! inst.error)
3460 inst.error = BAD_ARGS;
3461 return;
3462 }
3463
3464 if (*str == '^')
3465 {
3466 str++;
3467 flags |= LDM_TYPE_2_OR_3;
3468 }
3469
3470 inst.instruction |= flags | range;
3471 end_of_line (str);
3472 return;
3473 }
3474
3475 static void
3476 do_swi (str, flags)
3477 char * str;
3478 unsigned long flags;
3479 {
3480 skip_whitespace (str);
3481
3482 /* Allow optional leading '#'. */
3483 if (is_immediate_prefix (*str))
3484 str++;
3485
3486 if (my_get_expression (& inst.reloc.exp, & str))
3487 return;
3488
3489 inst.reloc.type = BFD_RELOC_ARM_SWI;
3490 inst.reloc.pc_rel = 0;
3491 inst.instruction |= flags;
3492
3493 end_of_line (str);
3494
3495 return;
3496 }
3497
3498 static void
3499 do_swap (str, flags)
3500 char * str;
3501 unsigned long flags;
3502 {
3503 int reg;
3504
3505 skip_whitespace (str);
3506
3507 if ((reg = reg_required_here (&str, 12)) == FAIL)
3508 return;
3509
3510 if (reg == REG_PC)
3511 {
3512 inst.error = _("r15 not allowed in swap");
3513 return;
3514 }
3515
3516 if (skip_past_comma (&str) == FAIL
3517 || (reg = reg_required_here (&str, 0)) == FAIL)
3518 {
3519 if (!inst.error)
3520 inst.error = BAD_ARGS;
3521 return;
3522 }
3523
3524 if (reg == REG_PC)
3525 {
3526 inst.error = _("r15 not allowed in swap");
3527 return;
3528 }
3529
3530 if (skip_past_comma (&str) == FAIL
3531 || *str++ != '[')
3532 {
3533 inst.error = BAD_ARGS;
3534 return;
3535 }
3536
3537 skip_whitespace (str);
3538
3539 if ((reg = reg_required_here (&str, 16)) == FAIL)
3540 return;
3541
3542 if (reg == REG_PC)
3543 {
3544 inst.error = BAD_PC;
3545 return;
3546 }
3547
3548 skip_whitespace (str);
3549
3550 if (*str++ != ']')
3551 {
3552 inst.error = _("missing ]");
3553 return;
3554 }
3555
3556 inst.instruction |= flags;
3557 end_of_line (str);
3558 return;
3559 }
3560
3561 static void
3562 do_branch (str, flags)
3563 char * str;
3564 unsigned long flags ATTRIBUTE_UNUSED;
3565 {
3566 if (my_get_expression (&inst.reloc.exp, &str))
3567 return;
3568
3569 #ifdef OBJ_ELF
3570 {
3571 char * save_in;
3572
3573 /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
3574 required for the instruction. */
3575
3576 /* arm_parse_reloc () works on input_line_pointer.
3577 We actually want to parse the operands to the branch instruction
3578 passed in 'str'. Save the input pointer and restore it later. */
3579 save_in = input_line_pointer;
3580 input_line_pointer = str;
3581 if (inst.reloc.exp.X_op == O_symbol
3582 && *str == '('
3583 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3584 {
3585 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3586 inst.reloc.pc_rel = 0;
3587 /* Modify str to point to after parsed operands, otherwise
3588 end_of_line() will complain about the (PLT) left in str. */
3589 str = input_line_pointer;
3590 }
3591 else
3592 {
3593 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3594 inst.reloc.pc_rel = 1;
3595 }
3596 input_line_pointer = save_in;
3597 }
3598 #else
3599 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3600 inst.reloc.pc_rel = 1;
3601 #endif /* OBJ_ELF */
3602
3603 end_of_line (str);
3604 return;
3605 }
3606
3607 static void
3608 do_bx (str, flags)
3609 char * str;
3610 unsigned long flags ATTRIBUTE_UNUSED;
3611 {
3612 int reg;
3613
3614 skip_whitespace (str);
3615
3616 if ((reg = reg_required_here (&str, 0)) == FAIL)
3617 {
3618 inst.error = BAD_ARGS;
3619 return;
3620 }
3621
3622 /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
3623 if (reg == REG_PC)
3624 as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
3625
3626 end_of_line (str);
3627 }
3628
3629 static void
3630 do_cdp (str, flags)
3631 char * str;
3632 unsigned long flags ATTRIBUTE_UNUSED;
3633 {
3634 /* Co-processor data operation.
3635 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3636 skip_whitespace (str);
3637
3638 if (co_proc_number (&str) == FAIL)
3639 {
3640 if (!inst.error)
3641 inst.error = BAD_ARGS;
3642 return;
3643 }
3644
3645 if (skip_past_comma (&str) == FAIL
3646 || cp_opc_expr (&str, 20,4) == FAIL)
3647 {
3648 if (!inst.error)
3649 inst.error = BAD_ARGS;
3650 return;
3651 }
3652
3653 if (skip_past_comma (&str) == FAIL
3654 || cp_reg_required_here (&str, 12) == FAIL)
3655 {
3656 if (!inst.error)
3657 inst.error = BAD_ARGS;
3658 return;
3659 }
3660
3661 if (skip_past_comma (&str) == FAIL
3662 || cp_reg_required_here (&str, 16) == FAIL)
3663 {
3664 if (!inst.error)
3665 inst.error = BAD_ARGS;
3666 return;
3667 }
3668
3669 if (skip_past_comma (&str) == FAIL
3670 || cp_reg_required_here (&str, 0) == FAIL)
3671 {
3672 if (!inst.error)
3673 inst.error = BAD_ARGS;
3674 return;
3675 }
3676
3677 if (skip_past_comma (&str) == SUCCESS)
3678 {
3679 if (cp_opc_expr (&str, 5, 3) == FAIL)
3680 {
3681 if (!inst.error)
3682 inst.error = BAD_ARGS;
3683 return;
3684 }
3685 }
3686
3687 end_of_line (str);
3688 return;
3689 }
3690
3691 static void
3692 do_lstc (str, flags)
3693 char * str;
3694 unsigned long flags;
3695 {
3696 /* Co-processor register load/store.
3697 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3698
3699 skip_whitespace (str);
3700
3701 if (co_proc_number (&str) == FAIL)
3702 {
3703 if (!inst.error)
3704 inst.error = BAD_ARGS;
3705 return;
3706 }
3707
3708 if (skip_past_comma (&str) == FAIL
3709 || cp_reg_required_here (&str, 12) == FAIL)
3710 {
3711 if (!inst.error)
3712 inst.error = BAD_ARGS;
3713 return;
3714 }
3715
3716 if (skip_past_comma (&str) == FAIL
3717 || cp_address_required_here (&str) == FAIL)
3718 {
3719 if (! inst.error)
3720 inst.error = BAD_ARGS;
3721 return;
3722 }
3723
3724 inst.instruction |= flags;
3725 end_of_line (str);
3726 return;
3727 }
3728
3729 static void
3730 do_co_reg (str, flags)
3731 char * str;
3732 unsigned long flags;
3733 {
3734 /* Co-processor register transfer.
3735 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3736
3737 skip_whitespace (str);
3738
3739 if (co_proc_number (&str) == FAIL)
3740 {
3741 if (!inst.error)
3742 inst.error = BAD_ARGS;
3743 return;
3744 }
3745
3746 if (skip_past_comma (&str) == FAIL
3747 || cp_opc_expr (&str, 21, 3) == FAIL)
3748 {
3749 if (!inst.error)
3750 inst.error = BAD_ARGS;
3751 return;
3752 }
3753
3754 if (skip_past_comma (&str) == FAIL
3755 || reg_required_here (&str, 12) == FAIL)
3756 {
3757 if (!inst.error)
3758 inst.error = BAD_ARGS;
3759 return;
3760 }
3761
3762 if (skip_past_comma (&str) == FAIL
3763 || cp_reg_required_here (&str, 16) == FAIL)
3764 {
3765 if (!inst.error)
3766 inst.error = BAD_ARGS;
3767 return;
3768 }
3769
3770 if (skip_past_comma (&str) == FAIL
3771 || cp_reg_required_here (&str, 0) == FAIL)
3772 {
3773 if (!inst.error)
3774 inst.error = BAD_ARGS;
3775 return;
3776 }
3777
3778 if (skip_past_comma (&str) == SUCCESS)
3779 {
3780 if (cp_opc_expr (&str, 5, 3) == FAIL)
3781 {
3782 if (!inst.error)
3783 inst.error = BAD_ARGS;
3784 return;
3785 }
3786 }
3787 if (flags)
3788 {
3789 inst.error = BAD_COND;
3790 }
3791
3792 end_of_line (str);
3793 return;
3794 }
3795
3796 static void
3797 do_fp_ctrl (str, flags)
3798 char * str;
3799 unsigned long flags ATTRIBUTE_UNUSED;
3800 {
3801 /* FP control registers.
3802 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3803
3804 skip_whitespace (str);
3805
3806 if (reg_required_here (&str, 12) == FAIL)
3807 {
3808 if (!inst.error)
3809 inst.error = BAD_ARGS;
3810 return;
3811 }
3812
3813 end_of_line (str);
3814 return;
3815 }
3816
3817 static void
3818 do_fp_ldst (str, flags)
3819 char * str;
3820 unsigned long flags ATTRIBUTE_UNUSED;
3821 {
3822 skip_whitespace (str);
3823
3824 switch (inst.suffix)
3825 {
3826 case SUFF_S:
3827 break;
3828 case SUFF_D:
3829 inst.instruction |= CP_T_X;
3830 break;
3831 case SUFF_E:
3832 inst.instruction |= CP_T_Y;
3833 break;
3834 case SUFF_P:
3835 inst.instruction |= CP_T_X | CP_T_Y;
3836 break;
3837 default:
3838 abort ();
3839 }
3840
3841 if (fp_reg_required_here (&str, 12) == FAIL)
3842 {
3843 if (!inst.error)
3844 inst.error = BAD_ARGS;
3845 return;
3846 }
3847
3848 if (skip_past_comma (&str) == FAIL
3849 || cp_address_required_here (&str) == FAIL)
3850 {
3851 if (!inst.error)
3852 inst.error = BAD_ARGS;
3853 return;
3854 }
3855
3856 end_of_line (str);
3857 }
3858
3859 static void
3860 do_fp_ldmstm (str, flags)
3861 char * str;
3862 unsigned long flags;
3863 {
3864 int num_regs;
3865
3866 skip_whitespace (str);
3867
3868 if (fp_reg_required_here (&str, 12) == FAIL)
3869 {
3870 if (! inst.error)
3871 inst.error = BAD_ARGS;
3872 return;
3873 }
3874
3875 /* Get Number of registers to transfer. */
3876 if (skip_past_comma (&str) == FAIL
3877 || my_get_expression (&inst.reloc.exp, &str))
3878 {
3879 if (! inst.error)
3880 inst.error = _("constant expression expected");
3881 return;
3882 }
3883
3884 if (inst.reloc.exp.X_op != O_constant)
3885 {
3886 inst.error = _("Constant value required for number of registers");
3887 return;
3888 }
3889
3890 num_regs = inst.reloc.exp.X_add_number;
3891
3892 if (num_regs < 1 || num_regs > 4)
3893 {
3894 inst.error = _("number of registers must be in the range [1:4]");
3895 return;
3896 }
3897
3898 switch (num_regs)
3899 {
3900 case 1:
3901 inst.instruction |= CP_T_X;
3902 break;
3903 case 2:
3904 inst.instruction |= CP_T_Y;
3905 break;
3906 case 3:
3907 inst.instruction |= CP_T_Y | CP_T_X;
3908 break;
3909 case 4:
3910 break;
3911 default:
3912 abort ();
3913 }
3914
3915 if (flags)
3916 {
3917 int reg;
3918 int write_back;
3919 int offset;
3920
3921 /* The instruction specified "ea" or "fd", so we can only accept
3922 [Rn]{!}. The instruction does not really support stacking or
3923 unstacking, so we have to emulate these by setting appropriate
3924 bits and offsets. */
3925 if (skip_past_comma (&str) == FAIL
3926 || *str != '[')
3927 {
3928 if (! inst.error)
3929 inst.error = BAD_ARGS;
3930 return;
3931 }
3932
3933 str++;
3934 skip_whitespace (str);
3935
3936 if ((reg = reg_required_here (&str, 16)) == FAIL)
3937 return;
3938
3939 skip_whitespace (str);
3940
3941 if (*str != ']')
3942 {
3943 inst.error = BAD_ARGS;
3944 return;
3945 }
3946
3947 str++;
3948 if (*str == '!')
3949 {
3950 write_back = 1;
3951 str++;
3952 if (reg == REG_PC)
3953 {
3954 inst.error =
3955 _("R15 not allowed as base register with write-back");
3956 return;
3957 }
3958 }
3959 else
3960 write_back = 0;
3961
3962 if (flags & CP_T_Pre)
3963 {
3964 /* Pre-decrement. */
3965 offset = 3 * num_regs;
3966 if (write_back)
3967 flags |= CP_T_WB;
3968 }
3969 else
3970 {
3971 /* Post-increment. */
3972 if (write_back)
3973 {
3974 flags |= CP_T_WB;
3975 offset = 3 * num_regs;
3976 }
3977 else
3978 {
3979 /* No write-back, so convert this into a standard pre-increment
3980 instruction -- aesthetically more pleasing. */
3981 flags = CP_T_Pre | CP_T_UD;
3982 offset = 0;
3983 }
3984 }
3985
3986 inst.instruction |= flags | offset;
3987 }
3988 else if (skip_past_comma (&str) == FAIL
3989 || cp_address_required_here (&str) == FAIL)
3990 {
3991 if (! inst.error)
3992 inst.error = BAD_ARGS;
3993 return;
3994 }
3995
3996 end_of_line (str);
3997 }
3998
3999 static void
4000 do_fp_dyadic (str, flags)
4001 char * str;
4002 unsigned long flags;
4003 {
4004 skip_whitespace (str);
4005
4006 switch (inst.suffix)
4007 {
4008 case SUFF_S:
4009 break;
4010 case SUFF_D:
4011 inst.instruction |= 0x00000080;
4012 break;
4013 case SUFF_E:
4014 inst.instruction |= 0x00080000;
4015 break;
4016 default:
4017 abort ();
4018 }
4019
4020 if (fp_reg_required_here (&str, 12) == FAIL)
4021 {
4022 if (! inst.error)
4023 inst.error = BAD_ARGS;
4024 return;
4025 }
4026
4027 if (skip_past_comma (&str) == FAIL
4028 || fp_reg_required_here (&str, 16) == FAIL)
4029 {
4030 if (! inst.error)
4031 inst.error = BAD_ARGS;
4032 return;
4033 }
4034
4035 if (skip_past_comma (&str) == FAIL
4036 || fp_op2 (&str) == FAIL)
4037 {
4038 if (! inst.error)
4039 inst.error = BAD_ARGS;
4040 return;
4041 }
4042
4043 inst.instruction |= flags;
4044 end_of_line (str);
4045 return;
4046 }
4047
4048 static void
4049 do_fp_monadic (str, flags)
4050 char * str;
4051 unsigned long flags;
4052 {
4053 skip_whitespace (str);
4054
4055 switch (inst.suffix)
4056 {
4057 case SUFF_S:
4058 break;
4059 case SUFF_D:
4060 inst.instruction |= 0x00000080;
4061 break;
4062 case SUFF_E:
4063 inst.instruction |= 0x00080000;
4064 break;
4065 default:
4066 abort ();
4067 }
4068
4069 if (fp_reg_required_here (&str, 12) == FAIL)
4070 {
4071 if (! inst.error)
4072 inst.error = BAD_ARGS;
4073 return;
4074 }
4075
4076 if (skip_past_comma (&str) == FAIL
4077 || fp_op2 (&str) == FAIL)
4078 {
4079 if (! inst.error)
4080 inst.error = BAD_ARGS;
4081 return;
4082 }
4083
4084 inst.instruction |= flags;
4085 end_of_line (str);
4086 return;
4087 }
4088
4089 static void
4090 do_fp_cmp (str, flags)
4091 char * str;
4092 unsigned long flags;
4093 {
4094 skip_whitespace (str);
4095
4096 if (fp_reg_required_here (&str, 16) == FAIL)
4097 {
4098 if (! inst.error)
4099 inst.error = BAD_ARGS;
4100 return;
4101 }
4102
4103 if (skip_past_comma (&str) == FAIL
4104 || fp_op2 (&str) == FAIL)
4105 {
4106 if (! inst.error)
4107 inst.error = BAD_ARGS;
4108 return;
4109 }
4110
4111 inst.instruction |= flags;
4112 end_of_line (str);
4113 return;
4114 }
4115
4116 static void
4117 do_fp_from_reg (str, flags)
4118 char * str;
4119 unsigned long flags;
4120 {
4121 skip_whitespace (str);
4122
4123 switch (inst.suffix)
4124 {
4125 case SUFF_S:
4126 break;
4127 case SUFF_D:
4128 inst.instruction |= 0x00000080;
4129 break;
4130 case SUFF_E:
4131 inst.instruction |= 0x00080000;
4132 break;
4133 default:
4134 abort ();
4135 }
4136
4137 if (fp_reg_required_here (&str, 16) == FAIL)
4138 {
4139 if (! inst.error)
4140 inst.error = BAD_ARGS;
4141 return;
4142 }
4143
4144 if (skip_past_comma (&str) == FAIL
4145 || reg_required_here (&str, 12) == FAIL)
4146 {
4147 if (! inst.error)
4148 inst.error = BAD_ARGS;
4149 return;
4150 }
4151
4152 inst.instruction |= flags;
4153 end_of_line (str);
4154 return;
4155 }
4156
4157 static void
4158 do_fp_to_reg (str, flags)
4159 char * str;
4160 unsigned long flags;
4161 {
4162 skip_whitespace (str);
4163
4164 if (reg_required_here (&str, 12) == FAIL)
4165 return;
4166
4167 if (skip_past_comma (&str) == FAIL
4168 || fp_reg_required_here (&str, 0) == FAIL)
4169 {
4170 if (! inst.error)
4171 inst.error = BAD_ARGS;
4172 return;
4173 }
4174
4175 inst.instruction |= flags;
4176 end_of_line (str);
4177 return;
4178 }
4179
4180 /* Thumb specific routines. */
4181
4182 /* Parse and validate that a register is of the right form, this saves
4183 repeated checking of this information in many similar cases.
4184 Unlike the 32-bit case we do not insert the register into the opcode
4185 here, since the position is often unknown until the full instruction
4186 has been parsed. */
4187
4188 static int
4189 thumb_reg (strp, hi_lo)
4190 char ** strp;
4191 int hi_lo;
4192 {
4193 int reg;
4194
4195 if ((reg = reg_required_here (strp, -1)) == FAIL)
4196 return FAIL;
4197
4198 switch (hi_lo)
4199 {
4200 case THUMB_REG_LO:
4201 if (reg > 7)
4202 {
4203 inst.error = _("lo register required");
4204 return FAIL;
4205 }
4206 break;
4207
4208 case THUMB_REG_HI:
4209 if (reg < 8)
4210 {
4211 inst.error = _("hi register required");
4212 return FAIL;
4213 }
4214 break;
4215
4216 default:
4217 break;
4218 }
4219
4220 return reg;
4221 }
4222
4223 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
4224 was SUB. */
4225
4226 static void
4227 thumb_add_sub (str, subtract)
4228 char * str;
4229 int subtract;
4230 {
4231 int Rd, Rs, Rn = FAIL;
4232
4233 skip_whitespace (str);
4234
4235 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4236 || skip_past_comma (&str) == FAIL)
4237 {
4238 if (! inst.error)
4239 inst.error = BAD_ARGS;
4240 return;
4241 }
4242
4243 if (is_immediate_prefix (*str))
4244 {
4245 Rs = Rd;
4246 str++;
4247 if (my_get_expression (&inst.reloc.exp, &str))
4248 return;
4249 }
4250 else
4251 {
4252 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4253 return;
4254
4255 if (skip_past_comma (&str) == FAIL)
4256 {
4257 /* Two operand format, shuffle the registers
4258 and pretend there are 3. */
4259 Rn = Rs;
4260 Rs = Rd;
4261 }
4262 else if (is_immediate_prefix (*str))
4263 {
4264 str++;
4265 if (my_get_expression (&inst.reloc.exp, &str))
4266 return;
4267 }
4268 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4269 return;
4270 }
4271
4272 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4273 for the latter case, EXPR contains the immediate that was found. */
4274 if (Rn != FAIL)
4275 {
4276 /* All register format. */
4277 if (Rd > 7 || Rs > 7 || Rn > 7)
4278 {
4279 if (Rs != Rd)
4280 {
4281 inst.error = _("dest and source1 must be the same register");
4282 return;
4283 }
4284
4285 /* Can't do this for SUB. */
4286 if (subtract)
4287 {
4288 inst.error = _("subtract valid only on lo regs");
4289 return;
4290 }
4291
4292 inst.instruction = (T_OPCODE_ADD_HI
4293 | (Rd > 7 ? THUMB_H1 : 0)
4294 | (Rn > 7 ? THUMB_H2 : 0));
4295 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4296 }
4297 else
4298 {
4299 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4300 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4301 }
4302 }
4303 else
4304 {
4305 /* Immediate expression, now things start to get nasty. */
4306
4307 /* First deal with HI regs, only very restricted cases allowed:
4308 Adjusting SP, and using PC or SP to get an address. */
4309 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4310 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4311 {
4312 inst.error = _("invalid Hi register with immediate");
4313 return;
4314 }
4315
4316 if (inst.reloc.exp.X_op != O_constant)
4317 {
4318 /* Value isn't known yet, all we can do is store all the fragments
4319 we know about in the instruction and let the reloc hacking
4320 work it all out. */
4321 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4322 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4323 }
4324 else
4325 {
4326 int offset = inst.reloc.exp.X_add_number;
4327
4328 if (subtract)
4329 offset = -offset;
4330
4331 if (offset < 0)
4332 {
4333 offset = -offset;
4334 subtract = 1;
4335
4336 /* Quick check, in case offset is MIN_INT. */
4337 if (offset < 0)
4338 {
4339 inst.error = _("immediate value out of range");
4340 return;
4341 }
4342 }
4343 else
4344 subtract = 0;
4345
4346 if (Rd == REG_SP)
4347 {
4348 if (offset & ~0x1fc)
4349 {
4350 inst.error = _("invalid immediate value for stack adjust");
4351 return;
4352 }
4353 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4354 inst.instruction |= offset >> 2;
4355 }
4356 else if (Rs == REG_PC || Rs == REG_SP)
4357 {
4358 if (subtract
4359 || (offset & ~0x3fc))
4360 {
4361 inst.error = _("invalid immediate for address calculation");
4362 return;
4363 }
4364 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4365 : T_OPCODE_ADD_SP);
4366 inst.instruction |= (Rd << 8) | (offset >> 2);
4367 }
4368 else if (Rs == Rd)
4369 {
4370 if (offset & ~0xff)
4371 {
4372 inst.error = _("immediate value out of range");
4373 return;
4374 }
4375 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4376 inst.instruction |= (Rd << 8) | offset;
4377 }
4378 else
4379 {
4380 if (offset & ~0x7)
4381 {
4382 inst.error = _("immediate value out of range");
4383 return;
4384 }
4385 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4386 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4387 }
4388 }
4389 }
4390
4391 end_of_line (str);
4392 }
4393
4394 static void
4395 thumb_shift (str, shift)
4396 char * str;
4397 int shift;
4398 {
4399 int Rd, Rs, Rn = FAIL;
4400
4401 skip_whitespace (str);
4402
4403 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4404 || skip_past_comma (&str) == FAIL)
4405 {
4406 if (! inst.error)
4407 inst.error = BAD_ARGS;
4408 return;
4409 }
4410
4411 if (is_immediate_prefix (*str))
4412 {
4413 /* Two operand immediate format, set Rs to Rd. */
4414 Rs = Rd;
4415 str ++;
4416 if (my_get_expression (&inst.reloc.exp, &str))
4417 return;
4418 }
4419 else
4420 {
4421 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4422 return;
4423
4424 if (skip_past_comma (&str) == FAIL)
4425 {
4426 /* Two operand format, shuffle the registers
4427 and pretend there are 3. */
4428 Rn = Rs;
4429 Rs = Rd;
4430 }
4431 else if (is_immediate_prefix (*str))
4432 {
4433 str++;
4434 if (my_get_expression (&inst.reloc.exp, &str))
4435 return;
4436 }
4437 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4438 return;
4439 }
4440
4441 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4442 for the latter case, EXPR contains the immediate that was found. */
4443
4444 if (Rn != FAIL)
4445 {
4446 if (Rs != Rd)
4447 {
4448 inst.error = _("source1 and dest must be same register");
4449 return;
4450 }
4451
4452 switch (shift)
4453 {
4454 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4455 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4456 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4457 }
4458
4459 inst.instruction |= Rd | (Rn << 3);
4460 }
4461 else
4462 {
4463 switch (shift)
4464 {
4465 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4466 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4467 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4468 }
4469
4470 if (inst.reloc.exp.X_op != O_constant)
4471 {
4472 /* Value isn't known yet, create a dummy reloc and let reloc
4473 hacking fix it up. */
4474 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4475 }
4476 else
4477 {
4478 unsigned shift_value = inst.reloc.exp.X_add_number;
4479
4480 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4481 {
4482 inst.error = _("Invalid immediate for shift");
4483 return;
4484 }
4485
4486 /* Shifts of zero are handled by converting to LSL. */
4487 if (shift_value == 0)
4488 inst.instruction = T_OPCODE_LSL_I;
4489
4490 /* Shifts of 32 are encoded as a shift of zero. */
4491 if (shift_value == 32)
4492 shift_value = 0;
4493
4494 inst.instruction |= shift_value << 6;
4495 }
4496
4497 inst.instruction |= Rd | (Rs << 3);
4498 }
4499
4500 end_of_line (str);
4501 }
4502
4503 static void
4504 thumb_mov_compare (str, move)
4505 char * str;
4506 int move;
4507 {
4508 int Rd, Rs = FAIL;
4509
4510 skip_whitespace (str);
4511
4512 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4513 || skip_past_comma (&str) == FAIL)
4514 {
4515 if (! inst.error)
4516 inst.error = BAD_ARGS;
4517 return;
4518 }
4519
4520 if (is_immediate_prefix (*str))
4521 {
4522 str++;
4523 if (my_get_expression (&inst.reloc.exp, &str))
4524 return;
4525 }
4526 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4527 return;
4528
4529 if (Rs != FAIL)
4530 {
4531 if (Rs < 8 && Rd < 8)
4532 {
4533 if (move == THUMB_MOVE)
4534 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4535 since a MOV instruction produces unpredictable results. */
4536 inst.instruction = T_OPCODE_ADD_I3;
4537 else
4538 inst.instruction = T_OPCODE_CMP_LR;
4539 inst.instruction |= Rd | (Rs << 3);
4540 }
4541 else
4542 {
4543 if (move == THUMB_MOVE)
4544 inst.instruction = T_OPCODE_MOV_HR;
4545 else
4546 inst.instruction = T_OPCODE_CMP_HR;
4547
4548 if (Rd > 7)
4549 inst.instruction |= THUMB_H1;
4550
4551 if (Rs > 7)
4552 inst.instruction |= THUMB_H2;
4553
4554 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4555 }
4556 }
4557 else
4558 {
4559 if (Rd > 7)
4560 {
4561 inst.error = _("only lo regs allowed with immediate");
4562 return;
4563 }
4564
4565 if (move == THUMB_MOVE)
4566 inst.instruction = T_OPCODE_MOV_I8;
4567 else
4568 inst.instruction = T_OPCODE_CMP_I8;
4569
4570 inst.instruction |= Rd << 8;
4571
4572 if (inst.reloc.exp.X_op != O_constant)
4573 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4574 else
4575 {
4576 unsigned value = inst.reloc.exp.X_add_number;
4577
4578 if (value > 255)
4579 {
4580 inst.error = _("invalid immediate");
4581 return;
4582 }
4583
4584 inst.instruction |= value;
4585 }
4586 }
4587
4588 end_of_line (str);
4589 }
4590
4591 static void
4592 thumb_load_store (str, load_store, size)
4593 char * str;
4594 int load_store;
4595 int size;
4596 {
4597 int Rd, Rb, Ro = FAIL;
4598
4599 skip_whitespace (str);
4600
4601 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4602 || skip_past_comma (&str) == FAIL)
4603 {
4604 if (! inst.error)
4605 inst.error = BAD_ARGS;
4606 return;
4607 }
4608
4609 if (*str == '[')
4610 {
4611 str++;
4612 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4613 return;
4614
4615 if (skip_past_comma (&str) != FAIL)
4616 {
4617 if (is_immediate_prefix (*str))
4618 {
4619 str++;
4620 if (my_get_expression (&inst.reloc.exp, &str))
4621 return;
4622 }
4623 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4624 return;
4625 }
4626 else
4627 {
4628 inst.reloc.exp.X_op = O_constant;
4629 inst.reloc.exp.X_add_number = 0;
4630 }
4631
4632 if (*str != ']')
4633 {
4634 inst.error = _("expected ']'");
4635 return;
4636 }
4637 str++;
4638 }
4639 else if (*str == '=')
4640 {
4641 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
4642 str++;
4643
4644 skip_whitespace (str);
4645
4646 if (my_get_expression (& inst.reloc.exp, & str))
4647 return;
4648
4649 end_of_line (str);
4650
4651 if ( inst.reloc.exp.X_op != O_constant
4652 && inst.reloc.exp.X_op != O_symbol)
4653 {
4654 inst.error = "Constant expression expected";
4655 return;
4656 }
4657
4658 if (inst.reloc.exp.X_op == O_constant
4659 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4660 {
4661 /* This can be done with a mov instruction. */
4662
4663 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4664 inst.instruction |= inst.reloc.exp.X_add_number;
4665 return;
4666 }
4667
4668 /* Insert into literal pool. */
4669 if (add_to_lit_pool () == FAIL)
4670 {
4671 if (!inst.error)
4672 inst.error = "literal pool insertion failed";
4673 return;
4674 }
4675
4676 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4677 inst.reloc.pc_rel = 1;
4678 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4679 /* Adjust ARM pipeline offset to Thumb. */
4680 inst.reloc.exp.X_add_number += 4;
4681
4682 return;
4683 }
4684 else
4685 {
4686 if (my_get_expression (&inst.reloc.exp, &str))
4687 return;
4688
4689 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4690 inst.reloc.pc_rel = 1;
4691 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */
4692 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4693 end_of_line (str);
4694 return;
4695 }
4696
4697 if (Rb == REG_PC || Rb == REG_SP)
4698 {
4699 if (size != THUMB_WORD)
4700 {
4701 inst.error = _("byte or halfword not valid for base register");
4702 return;
4703 }
4704 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4705 {
4706 inst.error = _("R15 based store not allowed");
4707 return;
4708 }
4709 else if (Ro != FAIL)
4710 {
4711 inst.error = _("Invalid base register for register offset");
4712 return;
4713 }
4714
4715 if (Rb == REG_PC)
4716 inst.instruction = T_OPCODE_LDR_PC;
4717 else if (load_store == THUMB_LOAD)
4718 inst.instruction = T_OPCODE_LDR_SP;
4719 else
4720 inst.instruction = T_OPCODE_STR_SP;
4721
4722 inst.instruction |= Rd << 8;
4723 if (inst.reloc.exp.X_op == O_constant)
4724 {
4725 unsigned offset = inst.reloc.exp.X_add_number;
4726
4727 if (offset & ~0x3fc)
4728 {
4729 inst.error = _("invalid offset");
4730 return;
4731 }
4732
4733 inst.instruction |= offset >> 2;
4734 }
4735 else
4736 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4737 }
4738 else if (Rb > 7)
4739 {
4740 inst.error = _("invalid base register in load/store");
4741 return;
4742 }
4743 else if (Ro == FAIL)
4744 {
4745 /* Immediate offset. */
4746 if (size == THUMB_WORD)
4747 inst.instruction = (load_store == THUMB_LOAD
4748 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4749 else if (size == THUMB_HALFWORD)
4750 inst.instruction = (load_store == THUMB_LOAD
4751 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4752 else
4753 inst.instruction = (load_store == THUMB_LOAD
4754 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4755
4756 inst.instruction |= Rd | (Rb << 3);
4757
4758 if (inst.reloc.exp.X_op == O_constant)
4759 {
4760 unsigned offset = inst.reloc.exp.X_add_number;
4761
4762 if (offset & ~(0x1f << size))
4763 {
4764 inst.error = _("Invalid offset");
4765 return;
4766 }
4767 inst.instruction |= (offset >> size) << 6;
4768 }
4769 else
4770 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4771 }
4772 else
4773 {
4774 /* Register offset. */
4775 if (size == THUMB_WORD)
4776 inst.instruction = (load_store == THUMB_LOAD
4777 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4778 else if (size == THUMB_HALFWORD)
4779 inst.instruction = (load_store == THUMB_LOAD
4780 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4781 else
4782 inst.instruction = (load_store == THUMB_LOAD
4783 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4784
4785 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4786 }
4787
4788 end_of_line (str);
4789 }
4790
4791 static void
4792 do_t_nop (str)
4793 char * str;
4794 {
4795 /* Do nothing. */
4796 end_of_line (str);
4797 return;
4798 }
4799
4800 /* Handle the Format 4 instructions that do not have equivalents in other
4801 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4802 BIC and MVN. */
4803
4804 static void
4805 do_t_arit (str)
4806 char * str;
4807 {
4808 int Rd, Rs, Rn;
4809
4810 skip_whitespace (str);
4811
4812 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4813 || skip_past_comma (&str) == FAIL
4814 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4815 {
4816 inst.error = BAD_ARGS;
4817 return;
4818 }
4819
4820 if (skip_past_comma (&str) != FAIL)
4821 {
4822 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4823 (It isn't allowed for CMP either, but that isn't handled by this
4824 function.) */
4825 if (inst.instruction == T_OPCODE_TST
4826 || inst.instruction == T_OPCODE_CMN
4827 || inst.instruction == T_OPCODE_NEG
4828 || inst.instruction == T_OPCODE_MVN)
4829 {
4830 inst.error = BAD_ARGS;
4831 return;
4832 }
4833
4834 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4835 return;
4836
4837 if (Rs != Rd)
4838 {
4839 inst.error = _("dest and source1 one must be the same register");
4840 return;
4841 }
4842 Rs = Rn;
4843 }
4844
4845 if (inst.instruction == T_OPCODE_MUL
4846 && Rs == Rd)
4847 as_tsktsk (_("Rs and Rd must be different in MUL"));
4848
4849 inst.instruction |= Rd | (Rs << 3);
4850 end_of_line (str);
4851 }
4852
4853 static void
4854 do_t_add (str)
4855 char * str;
4856 {
4857 thumb_add_sub (str, 0);
4858 }
4859
4860 static void
4861 do_t_asr (str)
4862 char * str;
4863 {
4864 thumb_shift (str, THUMB_ASR);
4865 }
4866
4867 static void
4868 do_t_branch9 (str)
4869 char * str;
4870 {
4871 if (my_get_expression (&inst.reloc.exp, &str))
4872 return;
4873 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4874 inst.reloc.pc_rel = 1;
4875 end_of_line (str);
4876 }
4877
4878 static void
4879 do_t_branch12 (str)
4880 char * str;
4881 {
4882 if (my_get_expression (&inst.reloc.exp, &str))
4883 return;
4884 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4885 inst.reloc.pc_rel = 1;
4886 end_of_line (str);
4887 }
4888
4889 /* Find the real, Thumb encoded start of a Thumb function. */
4890
4891 static symbolS *
4892 find_real_start (symbolP)
4893 symbolS * symbolP;
4894 {
4895 char * real_start;
4896 const char * name = S_GET_NAME (symbolP);
4897 symbolS * new_target;
4898
4899 /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
4900 #define STUB_NAME ".real_start_of"
4901
4902 if (name == NULL)
4903 abort ();
4904
4905 /* Names that start with '.' are local labels, not function entry points.
4906 The compiler may generate BL instructions to these labels because it
4907 needs to perform a branch to a far away location. */
4908 if (name[0] == '.')
4909 return symbolP;
4910
4911 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4912 sprintf (real_start, "%s%s", STUB_NAME, name);
4913
4914 new_target = symbol_find (real_start);
4915
4916 if (new_target == NULL)
4917 {
4918 as_warn ("Failed to find real start of function: %s\n", name);
4919 new_target = symbolP;
4920 }
4921
4922 free (real_start);
4923
4924 return new_target;
4925 }
4926
4927 static void
4928 do_t_branch23 (str)
4929 char * str;
4930 {
4931 if (my_get_expression (& inst.reloc.exp, & str))
4932 return;
4933
4934 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4935 inst.reloc.pc_rel = 1;
4936 end_of_line (str);
4937
4938 /* If the destination of the branch is a defined symbol which does not have
4939 the THUMB_FUNC attribute, then we must be calling a function which has
4940 the (interfacearm) attribute. We look for the Thumb entry point to that
4941 function and change the branch to refer to that function instead. */
4942 if ( inst.reloc.exp.X_op == O_symbol
4943 && inst.reloc.exp.X_add_symbol != NULL
4944 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4945 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4946 inst.reloc.exp.X_add_symbol =
4947 find_real_start (inst.reloc.exp.X_add_symbol);
4948 }
4949
4950 static void
4951 do_t_bx (str)
4952 char * str;
4953 {
4954 int reg;
4955
4956 skip_whitespace (str);
4957
4958 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4959 return;
4960
4961 /* This sets THUMB_H2 from the top bit of reg. */
4962 inst.instruction |= reg << 3;
4963
4964 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4965 should cause the alignment to be checked once it is known. This is
4966 because BX PC only works if the instruction is word aligned. */
4967
4968 end_of_line (str);
4969 }
4970
4971 static void
4972 do_t_compare (str)
4973 char * str;
4974 {
4975 thumb_mov_compare (str, THUMB_COMPARE);
4976 }
4977
4978 static void
4979 do_t_ldmstm (str)
4980 char * str;
4981 {
4982 int Rb;
4983 long range;
4984
4985 skip_whitespace (str);
4986
4987 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4988 return;
4989
4990 if (*str != '!')
4991 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4992 else
4993 str++;
4994
4995 if (skip_past_comma (&str) == FAIL
4996 || (range = reg_list (&str)) == FAIL)
4997 {
4998 if (! inst.error)
4999 inst.error = BAD_ARGS;
5000 return;
5001 }
5002
5003 if (inst.reloc.type != BFD_RELOC_NONE)
5004 {
5005 /* This really doesn't seem worth it. */
5006 inst.reloc.type = BFD_RELOC_NONE;
5007 inst.error = _("Expression too complex");
5008 return;
5009 }
5010
5011 if (range & ~0xff)
5012 {
5013 inst.error = _("only lo-regs valid in load/store multiple");
5014 return;
5015 }
5016
5017 inst.instruction |= (Rb << 8) | range;
5018 end_of_line (str);
5019 }
5020
5021 static void
5022 do_t_ldr (str)
5023 char * str;
5024 {
5025 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
5026 }
5027
5028 static void
5029 do_t_ldrb (str)
5030 char * str;
5031 {
5032 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
5033 }
5034
5035 static void
5036 do_t_ldrh (str)
5037 char * str;
5038 {
5039 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
5040 }
5041
5042 static void
5043 do_t_lds (str)
5044 char * str;
5045 {
5046 int Rd, Rb, Ro;
5047
5048 skip_whitespace (str);
5049
5050 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5051 || skip_past_comma (&str) == FAIL
5052 || *str++ != '['
5053 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5054 || skip_past_comma (&str) == FAIL
5055 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5056 || *str++ != ']')
5057 {
5058 if (! inst.error)
5059 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
5060 return;
5061 }
5062
5063 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
5064 end_of_line (str);
5065 }
5066
5067 static void
5068 do_t_lsl (str)
5069 char * str;
5070 {
5071 thumb_shift (str, THUMB_LSL);
5072 }
5073
5074 static void
5075 do_t_lsr (str)
5076 char * str;
5077 {
5078 thumb_shift (str, THUMB_LSR);
5079 }
5080
5081 static void
5082 do_t_mov (str)
5083 char * str;
5084 {
5085 thumb_mov_compare (str, THUMB_MOVE);
5086 }
5087
5088 static void
5089 do_t_push_pop (str)
5090 char * str;
5091 {
5092 long range;
5093
5094 skip_whitespace (str);
5095
5096 if ((range = reg_list (&str)) == FAIL)
5097 {
5098 if (! inst.error)
5099 inst.error = BAD_ARGS;
5100 return;
5101 }
5102
5103 if (inst.reloc.type != BFD_RELOC_NONE)
5104 {
5105 /* This really doesn't seem worth it. */
5106 inst.reloc.type = BFD_RELOC_NONE;
5107 inst.error = _("Expression too complex");
5108 return;
5109 }
5110
5111 if (range & ~0xff)
5112 {
5113 if ((inst.instruction == T_OPCODE_PUSH
5114 && (range & ~0xff) == 1 << REG_LR)
5115 || (inst.instruction == T_OPCODE_POP
5116 && (range & ~0xff) == 1 << REG_PC))
5117 {
5118 inst.instruction |= THUMB_PP_PC_LR;
5119 range &= 0xff;
5120 }
5121 else
5122 {
5123 inst.error = _("invalid register list to push/pop instruction");
5124 return;
5125 }
5126 }
5127
5128 inst.instruction |= range;
5129 end_of_line (str);
5130 }
5131
5132 static void
5133 do_t_str (str)
5134 char * str;
5135 {
5136 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
5137 }
5138
5139 static void
5140 do_t_strb (str)
5141 char * str;
5142 {
5143 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
5144 }
5145
5146 static void
5147 do_t_strh (str)
5148 char * str;
5149 {
5150 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
5151 }
5152
5153 static void
5154 do_t_sub (str)
5155 char * str;
5156 {
5157 thumb_add_sub (str, 1);
5158 }
5159
5160 static void
5161 do_t_swi (str)
5162 char * str;
5163 {
5164 skip_whitespace (str);
5165
5166 if (my_get_expression (&inst.reloc.exp, &str))
5167 return;
5168
5169 inst.reloc.type = BFD_RELOC_ARM_SWI;
5170 end_of_line (str);
5171 return;
5172 }
5173
5174 static void
5175 do_t_adr (str)
5176 char * str;
5177 {
5178 int reg;
5179
5180 /* This is a pseudo-op of the form "adr rd, label" to be converted
5181 into a relative address of the form "add rd, pc, #label-.-4". */
5182 skip_whitespace (str);
5183
5184 /* Store Rd in temporary location inside instruction. */
5185 if ((reg = reg_required_here (&str, 4)) == FAIL
5186 || (reg > 7) /* For Thumb reg must be r0..r7. */
5187 || skip_past_comma (&str) == FAIL
5188 || my_get_expression (&inst.reloc.exp, &str))
5189 {
5190 if (!inst.error)
5191 inst.error = BAD_ARGS;
5192 return;
5193 }
5194
5195 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5196 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
5197 inst.reloc.pc_rel = 1;
5198 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
5199
5200 end_of_line (str);
5201 }
5202
5203 static void
5204 insert_reg (entry)
5205 int entry;
5206 {
5207 int len = strlen (reg_table[entry].name) + 2;
5208 char * buf = (char *) xmalloc (len);
5209 char * buf2 = (char *) xmalloc (len);
5210 int i = 0;
5211
5212 #ifdef REGISTER_PREFIX
5213 buf[i++] = REGISTER_PREFIX;
5214 #endif
5215
5216 strcpy (buf + i, reg_table[entry].name);
5217
5218 for (i = 0; buf[i]; i++)
5219 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
5220
5221 buf2[i] = '\0';
5222
5223 hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]);
5224 hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]);
5225 }
5226
5227 static void
5228 insert_reg_alias (str, regnum)
5229 char *str;
5230 int regnum;
5231 {
5232 struct reg_entry *new =
5233 (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
5234 char *name = xmalloc (strlen (str) + 1);
5235 strcpy (name, str);
5236
5237 new->name = name;
5238 new->number = regnum;
5239
5240 hash_insert (arm_reg_hsh, name, (PTR) new);
5241 }
5242
5243 static void
5244 set_constant_flonums ()
5245 {
5246 int i;
5247
5248 for (i = 0; i < NUM_FLOAT_VALS; i++)
5249 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
5250 abort ();
5251 }
5252
5253 void
5254 md_begin ()
5255 {
5256 unsigned mach;
5257 unsigned int i;
5258
5259 if ( (arm_ops_hsh = hash_new ()) == NULL
5260 || (arm_tops_hsh = hash_new ()) == NULL
5261 || (arm_cond_hsh = hash_new ()) == NULL
5262 || (arm_shift_hsh = hash_new ()) == NULL
5263 || (arm_reg_hsh = hash_new ()) == NULL
5264 || (arm_psr_hsh = hash_new ()) == NULL)
5265 as_fatal (_("Virtual memory exhausted"));
5266
5267 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
5268 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
5269 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
5270 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
5271 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5272 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
5273 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5274 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
5275 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5276 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
5277
5278 for (i = 0; reg_table[i].name; i++)
5279 insert_reg (i);
5280
5281 set_constant_flonums ();
5282
5283 #if defined OBJ_COFF || defined OBJ_ELF
5284 {
5285 unsigned int flags = 0;
5286
5287 /* Set the flags in the private structure. */
5288 if (uses_apcs_26) flags |= F_APCS26;
5289 if (support_interwork) flags |= F_INTERWORK;
5290 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5291 if (pic_code) flags |= F_PIC;
5292 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
5293
5294 bfd_set_private_flags (stdoutput, flags);
5295 }
5296 #endif
5297
5298 /* Record the CPU type as well. */
5299 switch (cpu_variant & ARM_CPU_MASK)
5300 {
5301 case ARM_2:
5302 mach = bfd_mach_arm_2;
5303 break;
5304
5305 case ARM_3: /* Also ARM_250. */
5306 mach = bfd_mach_arm_2a;
5307 break;
5308
5309 default:
5310 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
5311 mach = bfd_mach_arm_4;
5312 break;
5313
5314 case ARM_7: /* Also ARM_6. */
5315 mach = bfd_mach_arm_3;
5316 break;
5317 }
5318
5319 /* Catch special cases. */
5320 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5321 {
5322 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5323 mach = bfd_mach_arm_5T;
5324 else if (cpu_variant & ARM_EXT_V5)
5325 mach = bfd_mach_arm_5;
5326 else if (cpu_variant & ARM_THUMB)
5327 mach = bfd_mach_arm_4T;
5328 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5329 mach = bfd_mach_arm_4;
5330 else if (cpu_variant & ARM_LONGMUL)
5331 mach = bfd_mach_arm_3M;
5332 }
5333
5334 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5335 }
5336
5337 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5338 for use in the a.out file, and stores them in the array pointed to by buf.
5339 This knows about the endian-ness of the target machine and does
5340 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5341 2 (short) and 4 (long) Floating numbers are put out as a series of
5342 LITTLENUMS (shorts, here at least). */
5343
5344 void
5345 md_number_to_chars (buf, val, n)
5346 char * buf;
5347 valueT val;
5348 int n;
5349 {
5350 if (target_big_endian)
5351 number_to_chars_bigendian (buf, val, n);
5352 else
5353 number_to_chars_littleendian (buf, val, n);
5354 }
5355
5356 static valueT
5357 md_chars_to_number (buf, n)
5358 char * buf;
5359 int n;
5360 {
5361 valueT result = 0;
5362 unsigned char * where = (unsigned char *) buf;
5363
5364 if (target_big_endian)
5365 {
5366 while (n--)
5367 {
5368 result <<= 8;
5369 result |= (*where++ & 255);
5370 }
5371 }
5372 else
5373 {
5374 while (n--)
5375 {
5376 result <<= 8;
5377 result |= (where[n] & 255);
5378 }
5379 }
5380
5381 return result;
5382 }
5383
5384 /* Turn a string in input_line_pointer into a floating point constant
5385 of type TYPE, and store the appropriate bytes in *LITP. The number
5386 of LITTLENUMS emitted is stored in *SIZEP. An error message is
5387 returned, or NULL on OK.
5388
5389 Note that fp constants aren't represent in the normal way on the ARM.
5390 In big endian mode, things are as expected. However, in little endian
5391 mode fp constants are big-endian word-wise, and little-endian byte-wise
5392 within the words. For example, (double) 1.1 in big endian mode is
5393 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5394 the byte sequence 99 99 f1 3f 9a 99 99 99.
5395
5396 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5397
5398 char *
5399 md_atof (type, litP, sizeP)
5400 char type;
5401 char * litP;
5402 int * sizeP;
5403 {
5404 int prec;
5405 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5406 char *t;
5407 int i;
5408
5409 switch (type)
5410 {
5411 case 'f':
5412 case 'F':
5413 case 's':
5414 case 'S':
5415 prec = 2;
5416 break;
5417
5418 case 'd':
5419 case 'D':
5420 case 'r':
5421 case 'R':
5422 prec = 4;
5423 break;
5424
5425 case 'x':
5426 case 'X':
5427 prec = 6;
5428 break;
5429
5430 case 'p':
5431 case 'P':
5432 prec = 6;
5433 break;
5434
5435 default:
5436 *sizeP = 0;
5437 return _("Bad call to MD_ATOF()");
5438 }
5439
5440 t = atof_ieee (input_line_pointer, type, words);
5441 if (t)
5442 input_line_pointer = t;
5443 *sizeP = prec * 2;
5444
5445 if (target_big_endian)
5446 {
5447 for (i = 0; i < prec; i++)
5448 {
5449 md_number_to_chars (litP, (valueT) words[i], 2);
5450 litP += 2;
5451 }
5452 }
5453 else
5454 {
5455 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5456 8 byte float the order is 1 0 3 2. */
5457 for (i = 0; i < prec; i += 2)
5458 {
5459 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5460 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5461 litP += 4;
5462 }
5463 }
5464
5465 return 0;
5466 }
5467
5468 /* The knowledge of the PC's pipeline offset is built into the insns
5469 themselves. */
5470
5471 long
5472 md_pcrel_from (fixP)
5473 fixS * fixP;
5474 {
5475 if (fixP->fx_addsy
5476 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5477 && fixP->fx_subsy == NULL)
5478 return 0;
5479
5480 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5481 {
5482 /* PC relative addressing on the Thumb is slightly odd
5483 as the bottom two bits of the PC are forced to zero
5484 for the calculation. */
5485 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5486 }
5487
5488 #ifdef TE_WINCE
5489 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5490 so we un-adjust here to compensate for the accomodation. */
5491 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
5492 #else
5493 return fixP->fx_where + fixP->fx_frag->fr_address;
5494 #endif
5495 }
5496
5497 /* Round up a section size to the appropriate boundary. */
5498
5499 valueT
5500 md_section_align (segment, size)
5501 segT segment ATTRIBUTE_UNUSED;
5502 valueT size;
5503 {
5504 #ifdef OBJ_ELF
5505 return size;
5506 #else
5507 /* Round all sects to multiple of 4. */
5508 return (size + 3) & ~3;
5509 #endif
5510 }
5511
5512 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5513 Otherwise we have no need to default values of symbols. */
5514
5515 symbolS *
5516 md_undefined_symbol (name)
5517 char * name ATTRIBUTE_UNUSED;
5518 {
5519 #ifdef OBJ_ELF
5520 if (name[0] == '_' && name[1] == 'G'
5521 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5522 {
5523 if (!GOT_symbol)
5524 {
5525 if (symbol_find (name))
5526 as_bad ("GOT already in the symbol table");
5527
5528 GOT_symbol = symbol_new (name, undefined_section,
5529 (valueT) 0, & zero_address_frag);
5530 }
5531
5532 return GOT_symbol;
5533 }
5534 #endif
5535
5536 return 0;
5537 }
5538
5539 /* arm_reg_parse () := if it looks like a register, return its token and
5540 advance the pointer. */
5541
5542 static int
5543 arm_reg_parse (ccp)
5544 register char ** ccp;
5545 {
5546 char * start = * ccp;
5547 char c;
5548 char * p;
5549 struct reg_entry * reg;
5550
5551 #ifdef REGISTER_PREFIX
5552 if (*start != REGISTER_PREFIX)
5553 return FAIL;
5554 p = start + 1;
5555 #else
5556 p = start;
5557 #ifdef OPTIONAL_REGISTER_PREFIX
5558 if (*p == OPTIONAL_REGISTER_PREFIX)
5559 p++, start++;
5560 #endif
5561 #endif
5562 if (!isalpha (*p) || !is_name_beginner (*p))
5563 return FAIL;
5564
5565 c = *p++;
5566 while (isalpha (c) || isdigit (c) || c == '_')
5567 c = *p++;
5568
5569 *--p = 0;
5570 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5571 *p = c;
5572
5573 if (reg)
5574 {
5575 *ccp = p;
5576 return reg->number;
5577 }
5578
5579 return FAIL;
5580 }
5581
5582 int
5583 md_apply_fix3 (fixP, val, seg)
5584 fixS * fixP;
5585 valueT * val;
5586 segT seg;
5587 {
5588 offsetT value = * val;
5589 offsetT newval;
5590 unsigned int newimm;
5591 unsigned long temp;
5592 int sign;
5593 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5594 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5595
5596 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5597
5598 /* Note whether this will delete the relocation. */
5599 #if 0
5600 /* Patch from REarnshaw to JDavis (disabled for the moment, since it
5601 doesn't work fully.) */
5602 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5603 && !fixP->fx_pcrel)
5604 #else
5605 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5606 #endif
5607 fixP->fx_done = 1;
5608
5609 /* If this symbol is in a different section then we need to leave it for
5610 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5611 so we have to undo it's effects here. */
5612 if (fixP->fx_pcrel)
5613 {
5614 if (fixP->fx_addsy != NULL
5615 && S_IS_DEFINED (fixP->fx_addsy)
5616 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5617 {
5618 if (target_oabi
5619 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
5620 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
5621 ))
5622 value = 0;
5623 else
5624 value += md_pcrel_from (fixP);
5625 }
5626 }
5627
5628 /* Remember value for emit_reloc. */
5629 fixP->fx_addnumber = value;
5630
5631 switch (fixP->fx_r_type)
5632 {
5633 case BFD_RELOC_ARM_IMMEDIATE:
5634 newimm = validate_immediate (value);
5635 temp = md_chars_to_number (buf, INSN_SIZE);
5636
5637 /* If the instruction will fail, see if we can fix things up by
5638 changing the opcode. */
5639 if (newimm == (unsigned int) FAIL
5640 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5641 {
5642 as_bad_where (fixP->fx_file, fixP->fx_line,
5643 _("invalid constant (%lx) after fixup"),
5644 (unsigned long) value);
5645 break;
5646 }
5647
5648 newimm |= (temp & 0xfffff000);
5649 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5650 break;
5651
5652 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5653 {
5654 unsigned int highpart = 0;
5655 unsigned int newinsn = 0xe1a00000; /* nop. */
5656 newimm = validate_immediate (value);
5657 temp = md_chars_to_number (buf, INSN_SIZE);
5658
5659 /* If the instruction will fail, see if we can fix things up by
5660 changing the opcode. */
5661 if (newimm == (unsigned int) FAIL
5662 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5663 {
5664 /* No ? OK - try using two ADD instructions to generate
5665 the value. */
5666 newimm = validate_immediate_twopart (value, & highpart);
5667
5668 /* Yes - then make sure that the second instruction is
5669 also an add. */
5670 if (newimm != (unsigned int) FAIL)
5671 newinsn = temp;
5672 /* Still No ? Try using a negated value. */
5673 else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
5674 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5675 /* Otherwise - give up. */
5676 else
5677 {
5678 as_bad_where (fixP->fx_file, fixP->fx_line,
5679 _("Unable to compute ADRL instructions for PC offset of 0x%x"),
5680 value);
5681 break;
5682 }
5683
5684 /* Replace the first operand in the 2nd instruction (which
5685 is the PC) with the destination register. We have
5686 already added in the PC in the first instruction and we
5687 do not want to do it again. */
5688 newinsn &= ~0xf0000;
5689 newinsn |= ((newinsn & 0x0f000) << 4);
5690 }
5691
5692 newimm |= (temp & 0xfffff000);
5693 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5694
5695 highpart |= (newinsn & 0xfffff000);
5696 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5697 }
5698 break;
5699
5700 case BFD_RELOC_ARM_OFFSET_IMM:
5701 sign = value >= 0;
5702
5703 if (value < 0)
5704 value = -value;
5705
5706 if (validate_offset_imm (value, 0) == FAIL)
5707 {
5708 as_bad_where (fixP->fx_file, fixP->fx_line,
5709 _("bad immediate value for offset (%ld)"),
5710 (long) value);
5711 break;
5712 }
5713
5714 newval = md_chars_to_number (buf, INSN_SIZE);
5715 newval &= 0xff7ff000;
5716 newval |= value | (sign ? INDEX_UP : 0);
5717 md_number_to_chars (buf, newval, INSN_SIZE);
5718 break;
5719
5720 case BFD_RELOC_ARM_OFFSET_IMM8:
5721 case BFD_RELOC_ARM_HWLITERAL:
5722 sign = value >= 0;
5723
5724 if (value < 0)
5725 value = -value;
5726
5727 if (validate_offset_imm (value, 1) == FAIL)
5728 {
5729 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5730 as_bad_where (fixP->fx_file, fixP->fx_line,
5731 _("invalid literal constant: pool needs to be closer"));
5732 else
5733 as_bad (_("bad immediate value for half-word offset (%ld)"),
5734 (long) value);
5735 break;
5736 }
5737
5738 newval = md_chars_to_number (buf, INSN_SIZE);
5739 newval &= 0xff7ff0f0;
5740 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5741 md_number_to_chars (buf, newval, INSN_SIZE);
5742 break;
5743
5744 case BFD_RELOC_ARM_LITERAL:
5745 sign = value >= 0;
5746
5747 if (value < 0)
5748 value = -value;
5749
5750 if (validate_offset_imm (value, 0) == FAIL)
5751 {
5752 as_bad_where (fixP->fx_file, fixP->fx_line,
5753 _("invalid literal constant: pool needs to be closer"));
5754 break;
5755 }
5756
5757 newval = md_chars_to_number (buf, INSN_SIZE);
5758 newval &= 0xff7ff000;
5759 newval |= value | (sign ? INDEX_UP : 0);
5760 md_number_to_chars (buf, newval, INSN_SIZE);
5761 break;
5762
5763 case BFD_RELOC_ARM_SHIFT_IMM:
5764 newval = md_chars_to_number (buf, INSN_SIZE);
5765 if (((unsigned long) value) > 32
5766 || (value == 32
5767 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5768 {
5769 as_bad_where (fixP->fx_file, fixP->fx_line,
5770 _("shift expression is too large"));
5771 break;
5772 }
5773
5774 if (value == 0)
5775 /* Shifts of zero must be done as lsl. */
5776 newval &= ~0x60;
5777 else if (value == 32)
5778 value = 0;
5779 newval &= 0xfffff07f;
5780 newval |= (value & 0x1f) << 7;
5781 md_number_to_chars (buf, newval, INSN_SIZE);
5782 break;
5783
5784 case BFD_RELOC_ARM_SWI:
5785 if (arm_data->thumb_mode)
5786 {
5787 if (((unsigned long) value) > 0xff)
5788 as_bad_where (fixP->fx_file, fixP->fx_line,
5789 _("Invalid swi expression"));
5790 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5791 newval |= value;
5792 md_number_to_chars (buf, newval, THUMB_SIZE);
5793 }
5794 else
5795 {
5796 if (((unsigned long) value) > 0x00ffffff)
5797 as_bad_where (fixP->fx_file, fixP->fx_line,
5798 _("Invalid swi expression"));
5799 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5800 newval |= value;
5801 md_number_to_chars (buf, newval, INSN_SIZE);
5802 }
5803 break;
5804
5805 case BFD_RELOC_ARM_MULTI:
5806 if (((unsigned long) value) > 0xffff)
5807 as_bad_where (fixP->fx_file, fixP->fx_line,
5808 _("Invalid expression in load/store multiple"));
5809 newval = value | md_chars_to_number (buf, INSN_SIZE);
5810 md_number_to_chars (buf, newval, INSN_SIZE);
5811 break;
5812
5813 case BFD_RELOC_ARM_PCREL_BRANCH:
5814 newval = md_chars_to_number (buf, INSN_SIZE);
5815
5816 /* Sign-extend a 24-bit number. */
5817 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
5818
5819 #ifdef OBJ_ELF
5820 if (! target_oabi)
5821 value = fixP->fx_offset;
5822 #endif
5823
5824 /* We are going to store value (shifted right by two) in the
5825 instruction, in a 24 bit, signed field. Thus we need to check
5826 that none of the top 8 bits of the shifted value (top 7 bits of
5827 the unshifted, unsigned value) are set, or that they are all set. */
5828 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
5829 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
5830 {
5831 #ifdef OBJ_ELF
5832 /* Normally we would be stuck at this point, since we cannot store
5833 the absolute address that is the destination of the branch in the
5834 24 bits of the branch instruction. If however, we happen to know
5835 that the destination of the branch is in the same section as the
5836 branch instruciton itself, then we can compute the relocation for
5837 ourselves and not have to bother the linker with it.
5838
5839 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5840 because I have not worked out how to do this for OBJ_COFF or
5841 target_oabi. */
5842 if (! target_oabi
5843 && fixP->fx_addsy != NULL
5844 && S_IS_DEFINED (fixP->fx_addsy)
5845 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
5846 {
5847 /* Get pc relative value to go into the branch. */
5848 value = * val;
5849
5850 /* Permit a backward branch provided that enough bits
5851 are set. Allow a forwards branch, provided that
5852 enough bits are clear. */
5853 if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
5854 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
5855 fixP->fx_done = 1;
5856 }
5857
5858 if (! fixP->fx_done)
5859 #endif
5860 as_bad_where (fixP->fx_file, fixP->fx_line,
5861 _("gas can't handle same-section branch dest >= 0x04000000"));
5862 }
5863
5864 value >>= 2;
5865 value += SEXT24 (newval);
5866
5867 if ( (value & ~ ((offsetT) 0xffffff)) != 0
5868 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
5869 as_bad_where (fixP->fx_file, fixP->fx_line,
5870 _("out of range branch"));
5871
5872 newval = (value & 0x00ffffff) | (newval & 0xff000000);
5873 md_number_to_chars (buf, newval, INSN_SIZE);
5874 break;
5875
5876 case BFD_RELOC_ARM_PCREL_BLX:
5877 {
5878 offsetT hbit;
5879 newval = md_chars_to_number (buf, INSN_SIZE);
5880
5881 #ifdef OBJ_ELF
5882 if (! target_oabi)
5883 value = fixP->fx_offset;
5884 #endif
5885 hbit = (value >> 1) & 1;
5886 value = (value >> 2) & 0x00ffffff;
5887 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5888 newval = value | (newval & 0xfe000000) | (hbit << 24);
5889 md_number_to_chars (buf, newval, INSN_SIZE);
5890 }
5891 break;
5892
5893 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
5894 newval = md_chars_to_number (buf, THUMB_SIZE);
5895 {
5896 addressT diff = (newval & 0xff) << 1;
5897 if (diff & 0x100)
5898 diff |= ~0xff;
5899
5900 value += diff;
5901 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5902 as_bad_where (fixP->fx_file, fixP->fx_line,
5903 _("Branch out of range"));
5904 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5905 }
5906 md_number_to_chars (buf, newval, THUMB_SIZE);
5907 break;
5908
5909 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
5910 newval = md_chars_to_number (buf, THUMB_SIZE);
5911 {
5912 addressT diff = (newval & 0x7ff) << 1;
5913 if (diff & 0x800)
5914 diff |= ~0x7ff;
5915
5916 value += diff;
5917 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5918 as_bad_where (fixP->fx_file, fixP->fx_line,
5919 _("Branch out of range"));
5920 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5921 }
5922 md_number_to_chars (buf, newval, THUMB_SIZE);
5923 break;
5924
5925 case BFD_RELOC_THUMB_PCREL_BLX:
5926 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5927 {
5928 offsetT newval2;
5929 addressT diff;
5930
5931 newval = md_chars_to_number (buf, THUMB_SIZE);
5932 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5933 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5934 if (diff & 0x400000)
5935 diff |= ~0x3fffff;
5936 #ifdef OBJ_ELF
5937 value = fixP->fx_offset;
5938 #endif
5939 value += diff;
5940 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5941 as_bad_where (fixP->fx_file, fixP->fx_line,
5942 _("Branch with link out of range"));
5943
5944 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5945 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5946 md_number_to_chars (buf, newval, THUMB_SIZE);
5947 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5948 }
5949 break;
5950
5951 case BFD_RELOC_8:
5952 if (fixP->fx_done || fixP->fx_pcrel)
5953 md_number_to_chars (buf, value, 1);
5954 #ifdef OBJ_ELF
5955 else if (!target_oabi)
5956 {
5957 value = fixP->fx_offset;
5958 md_number_to_chars (buf, value, 1);
5959 }
5960 #endif
5961 break;
5962
5963 case BFD_RELOC_16:
5964 if (fixP->fx_done || fixP->fx_pcrel)
5965 md_number_to_chars (buf, value, 2);
5966 #ifdef OBJ_ELF
5967 else if (!target_oabi)
5968 {
5969 value = fixP->fx_offset;
5970 md_number_to_chars (buf, value, 2);
5971 }
5972 #endif
5973 break;
5974
5975 #ifdef OBJ_ELF
5976 case BFD_RELOC_ARM_GOT32:
5977 case BFD_RELOC_ARM_GOTOFF:
5978 md_number_to_chars (buf, 0, 4);
5979 break;
5980 #endif
5981
5982 case BFD_RELOC_RVA:
5983 case BFD_RELOC_32:
5984 if (fixP->fx_done || fixP->fx_pcrel)
5985 md_number_to_chars (buf, value, 4);
5986 #ifdef OBJ_ELF
5987 else if (!target_oabi)
5988 {
5989 value = fixP->fx_offset;
5990 md_number_to_chars (buf, value, 4);
5991 }
5992 #endif
5993 break;
5994
5995 #ifdef OBJ_ELF
5996 case BFD_RELOC_ARM_PLT32:
5997 /* It appears the instruction is fully prepared at this point. */
5998 break;
5999 #endif
6000
6001 case BFD_RELOC_ARM_GOTPC:
6002 md_number_to_chars (buf, value, 4);
6003 break;
6004
6005 case BFD_RELOC_ARM_CP_OFF_IMM:
6006 sign = value >= 0;
6007 if (value < -1023 || value > 1023 || (value & 3))
6008 as_bad_where (fixP->fx_file, fixP->fx_line,
6009 _("Illegal value for co-processor offset"));
6010 if (value < 0)
6011 value = -value;
6012 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
6013 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
6014 md_number_to_chars (buf, newval, INSN_SIZE);
6015 break;
6016
6017 case BFD_RELOC_ARM_THUMB_OFFSET:
6018 newval = md_chars_to_number (buf, THUMB_SIZE);
6019 /* Exactly what ranges, and where the offset is inserted depends
6020 on the type of instruction, we can establish this from the
6021 top 4 bits. */
6022 switch (newval >> 12)
6023 {
6024 case 4: /* PC load. */
6025 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
6026 forced to zero for these loads, so we will need to round
6027 up the offset if the instruction address is not word
6028 aligned (since the final address produced must be, and
6029 we can only describe word-aligned immediate offsets). */
6030
6031 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
6032 as_bad_where (fixP->fx_file, fixP->fx_line,
6033 _("Invalid offset, target not word aligned (0x%08X)"),
6034 (unsigned int) (fixP->fx_frag->fr_address
6035 + fixP->fx_where + value));
6036
6037 if ((value + 2) & ~0x3fe)
6038 as_bad_where (fixP->fx_file, fixP->fx_line,
6039 _("Invalid offset, value too big (0x%08X)"), value);
6040
6041 /* Round up, since pc will be rounded down. */
6042 newval |= (value + 2) >> 2;
6043 break;
6044
6045 case 9: /* SP load/store. */
6046 if (value & ~0x3fc)
6047 as_bad_where (fixP->fx_file, fixP->fx_line,
6048 _("Invalid offset, value too big (0x%08X)"), value);
6049 newval |= value >> 2;
6050 break;
6051
6052 case 6: /* Word load/store. */
6053 if (value & ~0x7c)
6054 as_bad_where (fixP->fx_file, fixP->fx_line,
6055 _("Invalid offset, value too big (0x%08X)"), value);
6056 newval |= value << 4; /* 6 - 2. */
6057 break;
6058
6059 case 7: /* Byte load/store. */
6060 if (value & ~0x1f)
6061 as_bad_where (fixP->fx_file, fixP->fx_line,
6062 _("Invalid offset, value too big (0x%08X)"), value);
6063 newval |= value << 6;
6064 break;
6065
6066 case 8: /* Halfword load/store. */
6067 if (value & ~0x3e)
6068 as_bad_where (fixP->fx_file, fixP->fx_line,
6069 _("Invalid offset, value too big (0x%08X)"), value);
6070 newval |= value << 5; /* 6 - 1. */
6071 break;
6072
6073 default:
6074 as_bad_where (fixP->fx_file, fixP->fx_line,
6075 "Unable to process relocation for thumb opcode: %lx",
6076 (unsigned long) newval);
6077 break;
6078 }
6079 md_number_to_chars (buf, newval, THUMB_SIZE);
6080 break;
6081
6082 case BFD_RELOC_ARM_THUMB_ADD:
6083 /* This is a complicated relocation, since we use it for all of
6084 the following immediate relocations:
6085
6086 3bit ADD/SUB
6087 8bit ADD/SUB
6088 9bit ADD/SUB SP word-aligned
6089 10bit ADD PC/SP word-aligned
6090
6091 The type of instruction being processed is encoded in the
6092 instruction field:
6093
6094 0x8000 SUB
6095 0x00F0 Rd
6096 0x000F Rs
6097 */
6098 newval = md_chars_to_number (buf, THUMB_SIZE);
6099 {
6100 int rd = (newval >> 4) & 0xf;
6101 int rs = newval & 0xf;
6102 int subtract = newval & 0x8000;
6103
6104 if (rd == REG_SP)
6105 {
6106 if (value & ~0x1fc)
6107 as_bad_where (fixP->fx_file, fixP->fx_line,
6108 _("Invalid immediate for stack address calculation"));
6109 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
6110 newval |= value >> 2;
6111 }
6112 else if (rs == REG_PC || rs == REG_SP)
6113 {
6114 if (subtract ||
6115 value & ~0x3fc)
6116 as_bad_where (fixP->fx_file, fixP->fx_line,
6117 _("Invalid immediate for address calculation (value = 0x%08lX)"),
6118 (unsigned long) value);
6119 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
6120 newval |= rd << 8;
6121 newval |= value >> 2;
6122 }
6123 else if (rs == rd)
6124 {
6125 if (value & ~0xff)
6126 as_bad_where (fixP->fx_file, fixP->fx_line,
6127 _("Invalid 8bit immediate"));
6128 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
6129 newval |= (rd << 8) | value;
6130 }
6131 else
6132 {
6133 if (value & ~0x7)
6134 as_bad_where (fixP->fx_file, fixP->fx_line,
6135 _("Invalid 3bit immediate"));
6136 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
6137 newval |= rd | (rs << 3) | (value << 6);
6138 }
6139 }
6140 md_number_to_chars (buf, newval, THUMB_SIZE);
6141 break;
6142
6143 case BFD_RELOC_ARM_THUMB_IMM:
6144 newval = md_chars_to_number (buf, THUMB_SIZE);
6145 switch (newval >> 11)
6146 {
6147 case 0x04: /* 8bit immediate MOV. */
6148 case 0x05: /* 8bit immediate CMP. */
6149 if (value < 0 || value > 255)
6150 as_bad_where (fixP->fx_file, fixP->fx_line,
6151 _("Invalid immediate: %ld is too large"),
6152 (long) value);
6153 newval |= value;
6154 break;
6155
6156 default:
6157 abort ();
6158 }
6159 md_number_to_chars (buf, newval, THUMB_SIZE);
6160 break;
6161
6162 case BFD_RELOC_ARM_THUMB_SHIFT:
6163 /* 5bit shift value (0..31). */
6164 if (value < 0 || value > 31)
6165 as_bad_where (fixP->fx_file, fixP->fx_line,
6166 _("Illegal Thumb shift value: %ld"), (long) value);
6167 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
6168 newval |= value << 6;
6169 md_number_to_chars (buf, newval, THUMB_SIZE);
6170 break;
6171
6172 case BFD_RELOC_VTABLE_INHERIT:
6173 case BFD_RELOC_VTABLE_ENTRY:
6174 fixP->fx_done = 0;
6175 return 1;
6176
6177 case BFD_RELOC_NONE:
6178 default:
6179 as_bad_where (fixP->fx_file, fixP->fx_line,
6180 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
6181 }
6182
6183 return 1;
6184 }
6185
6186 /* Translate internal representation of relocation info to BFD target
6187 format. */
6188
6189 arelent *
6190 tc_gen_reloc (section, fixp)
6191 asection * section ATTRIBUTE_UNUSED;
6192 fixS * fixp;
6193 {
6194 arelent * reloc;
6195 bfd_reloc_code_real_type code;
6196
6197 reloc = (arelent *) xmalloc (sizeof (arelent));
6198
6199 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6200 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6201 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6202
6203 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
6204 #ifndef OBJ_ELF
6205 if (fixp->fx_pcrel == 0)
6206 reloc->addend = fixp->fx_offset;
6207 else
6208 reloc->addend = fixp->fx_offset = reloc->address;
6209 #else /* OBJ_ELF */
6210 reloc->addend = fixp->fx_offset;
6211 #endif
6212
6213 switch (fixp->fx_r_type)
6214 {
6215 case BFD_RELOC_8:
6216 if (fixp->fx_pcrel)
6217 {
6218 code = BFD_RELOC_8_PCREL;
6219 break;
6220 }
6221
6222 case BFD_RELOC_16:
6223 if (fixp->fx_pcrel)
6224 {
6225 code = BFD_RELOC_16_PCREL;
6226 break;
6227 }
6228
6229 case BFD_RELOC_32:
6230 if (fixp->fx_pcrel)
6231 {
6232 code = BFD_RELOC_32_PCREL;
6233 break;
6234 }
6235
6236 case BFD_RELOC_ARM_PCREL_BRANCH:
6237 case BFD_RELOC_ARM_PCREL_BLX:
6238 case BFD_RELOC_RVA:
6239 case BFD_RELOC_THUMB_PCREL_BRANCH9:
6240 case BFD_RELOC_THUMB_PCREL_BRANCH12:
6241 case BFD_RELOC_THUMB_PCREL_BRANCH23:
6242 case BFD_RELOC_THUMB_PCREL_BLX:
6243 case BFD_RELOC_VTABLE_ENTRY:
6244 case BFD_RELOC_VTABLE_INHERIT:
6245 code = fixp->fx_r_type;
6246 break;
6247
6248 case BFD_RELOC_ARM_LITERAL:
6249 case BFD_RELOC_ARM_HWLITERAL:
6250 /* If this is called then the a literal has been referenced across
6251 a section boundary - possibly due to an implicit dump. */
6252 as_bad_where (fixp->fx_file, fixp->fx_line,
6253 _("Literal referenced across section boundary (Implicit dump?)"));
6254 return NULL;
6255
6256 #ifdef OBJ_ELF
6257 case BFD_RELOC_ARM_GOT32:
6258 case BFD_RELOC_ARM_GOTOFF:
6259 case BFD_RELOC_ARM_PLT32:
6260 code = fixp->fx_r_type;
6261 break;
6262 #endif
6263
6264 case BFD_RELOC_ARM_IMMEDIATE:
6265 as_bad_where (fixp->fx_file, fixp->fx_line,
6266 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
6267 fixp->fx_r_type);
6268 return NULL;
6269
6270 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6271 as_bad_where (fixp->fx_file, fixp->fx_line,
6272 _("ADRL used for a symbol not defined in the same file"),
6273 fixp->fx_r_type);
6274 return NULL;
6275
6276 case BFD_RELOC_ARM_OFFSET_IMM:
6277 as_bad_where (fixp->fx_file, fixp->fx_line,
6278 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6279 fixp->fx_r_type);
6280 return NULL;
6281
6282 default:
6283 {
6284 char * type;
6285
6286 switch (fixp->fx_r_type)
6287 {
6288 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
6289 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
6290 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
6291 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
6292 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
6293 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
6294 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
6295 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
6296 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
6297 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
6298 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
6299 default: type = _("<unknown>"); break;
6300 }
6301 as_bad_where (fixp->fx_file, fixp->fx_line,
6302 _("Can not represent %s relocation in this object file format (%d)"),
6303 type, fixp->fx_pcrel);
6304 return NULL;
6305 }
6306 }
6307
6308 #ifdef OBJ_ELF
6309 if (code == BFD_RELOC_32_PCREL
6310 && GOT_symbol
6311 && fixp->fx_addsy == GOT_symbol)
6312 {
6313 code = BFD_RELOC_ARM_GOTPC;
6314 reloc->addend = fixp->fx_offset = reloc->address;
6315 }
6316 #endif
6317
6318 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6319
6320 if (reloc->howto == NULL)
6321 {
6322 as_bad_where (fixp->fx_file, fixp->fx_line,
6323 _("Can not represent %s relocation in this object file format"),
6324 bfd_get_reloc_code_name (code));
6325 return NULL;
6326 }
6327
6328 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6329 vtable entry to be used in the relocation's section offset. */
6330 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6331 reloc->address = fixp->fx_offset;
6332
6333 return reloc;
6334 }
6335
6336 int
6337 md_estimate_size_before_relax (fragP, segtype)
6338 fragS * fragP ATTRIBUTE_UNUSED;
6339 segT segtype ATTRIBUTE_UNUSED;
6340 {
6341 as_fatal (_("md_estimate_size_before_relax\n"));
6342 return 1;
6343 }
6344
6345 static void
6346 output_inst PARAMS ((void))
6347 {
6348 char * to = NULL;
6349
6350 if (inst.error)
6351 {
6352 as_bad (inst.error);
6353 return;
6354 }
6355
6356 to = frag_more (inst.size);
6357
6358 if (thumb_mode && (inst.size > THUMB_SIZE))
6359 {
6360 assert (inst.size == (2 * THUMB_SIZE));
6361 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6362 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6363 }
6364 else if (inst.size > INSN_SIZE)
6365 {
6366 assert (inst.size == (2 * INSN_SIZE));
6367 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6368 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6369 }
6370 else
6371 md_number_to_chars (to, inst.instruction, inst.size);
6372
6373 if (inst.reloc.type != BFD_RELOC_NONE)
6374 fix_new_arm (frag_now, to - frag_now->fr_literal,
6375 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6376 inst.reloc.type);
6377
6378 return;
6379 }
6380
6381 void
6382 md_assemble (str)
6383 char * str;
6384 {
6385 char c;
6386 char * p;
6387 char * q;
6388 char * start;
6389
6390 /* Align the instruction.
6391 This may not be the right thing to do but ... */
6392 #if 0
6393 arm_align (2, 0);
6394 #endif
6395 listing_prev_line (); /* Defined in listing.h. */
6396
6397 /* Align the previous label if needed. */
6398 if (last_label_seen != NULL)
6399 {
6400 symbol_set_frag (last_label_seen, frag_now);
6401 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6402 S_SET_SEGMENT (last_label_seen, now_seg);
6403 }
6404
6405 memset (&inst, '\0', sizeof (inst));
6406 inst.reloc.type = BFD_RELOC_NONE;
6407
6408 skip_whitespace (str);
6409
6410 /* Scan up to the end of the op-code, which must end in white space or
6411 end of string. */
6412 for (start = p = str; *p != '\0'; p++)
6413 if (*p == ' ')
6414 break;
6415
6416 if (p == str)
6417 {
6418 as_bad (_("No operator -- statement `%s'\n"), str);
6419 return;
6420 }
6421
6422 if (thumb_mode)
6423 {
6424 CONST struct thumb_opcode * opcode;
6425
6426 c = *p;
6427 *p = '\0';
6428 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6429 *p = c;
6430
6431 if (opcode)
6432 {
6433 /* Check that this instruction is supported for this CPU. */
6434 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
6435 {
6436 as_bad (_("selected processor does not support this opcode"));
6437 return;
6438 }
6439
6440 inst.instruction = opcode->value;
6441 inst.size = opcode->size;
6442 (*opcode->parms) (p);
6443 output_inst ();
6444 return;
6445 }
6446 }
6447 else
6448 {
6449 CONST struct asm_opcode * opcode;
6450 unsigned long cond_code;
6451
6452 inst.size = INSN_SIZE;
6453 /* P now points to the end of the opcode, probably white space, but we
6454 have to break the opcode up in case it contains condionals and flags;
6455 keep trying with progressively smaller basic instructions until one
6456 matches, or we run out of opcode. */
6457 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6458
6459 for (; q != str; q--)
6460 {
6461 c = *q;
6462 *q = '\0';
6463
6464 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6465 *q = c;
6466
6467 if (opcode && opcode->template)
6468 {
6469 unsigned long flag_bits = 0;
6470 char * r;
6471
6472 /* Check that this instruction is supported for this CPU. */
6473 if ((opcode->variants & cpu_variant) == 0)
6474 goto try_shorter;
6475
6476 inst.instruction = opcode->value;
6477 if (q == p) /* Just a simple opcode. */
6478 {
6479 if (opcode->comp_suffix)
6480 {
6481 if (*opcode->comp_suffix != '\0')
6482 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6483 str, opcode->comp_suffix);
6484 else
6485 /* Not a conditional instruction. */
6486 (*opcode->parms) (q, 0);
6487 }
6488 else
6489 {
6490 /* A conditional instruction with default condition. */
6491 inst.instruction |= COND_ALWAYS;
6492 (*opcode->parms) (q, 0);
6493 }
6494 output_inst ();
6495 return;
6496 }
6497
6498 /* Not just a simple opcode. Check if extra is a
6499 conditional. */
6500 r = q;
6501 if (p - r >= 2)
6502 {
6503 CONST struct asm_cond *cond;
6504 char d = *(r + 2);
6505
6506 *(r + 2) = '\0';
6507 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6508 *(r + 2) = d;
6509 if (cond)
6510 {
6511 if (cond->value == 0xf0000000)
6512 as_tsktsk (
6513 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6514
6515 cond_code = cond->value;
6516 r += 2;
6517 }
6518 else
6519 cond_code = COND_ALWAYS;
6520 }
6521 else
6522 cond_code = COND_ALWAYS;
6523
6524 /* Apply the conditional, or complain it's not allowed. */
6525 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
6526 {
6527 /* Instruction isn't conditional. */
6528 if (cond_code != COND_ALWAYS)
6529 {
6530 as_bad (_("Opcode `%s' is unconditional\n"), str);
6531 return;
6532 }
6533 }
6534 else
6535 /* Instruction is conditional: set the condition into it. */
6536 inst.instruction |= cond_code;
6537
6538 /* If there is a compulsory suffix, it should come here
6539 before any optional flags. */
6540 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
6541 {
6542 CONST char *s = opcode->comp_suffix;
6543
6544 while (*s)
6545 {
6546 inst.suffix++;
6547 if (*r == *s)
6548 break;
6549 s++;
6550 }
6551
6552 if (*s == '\0')
6553 {
6554 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
6555 str, opcode->comp_suffix);
6556 return;
6557 }
6558
6559 r++;
6560 }
6561
6562 /* The remainder, if any should now be flags for the instruction;
6563 Scan these checking each one found with the opcode. */
6564 if (r != p)
6565 {
6566 char d;
6567 CONST struct asm_flg *flag = opcode->flags;
6568
6569 if (flag)
6570 {
6571 int flagno;
6572
6573 d = *p;
6574 *p = '\0';
6575
6576 for (flagno = 0; flag[flagno].template; flagno++)
6577 {
6578 if (streq (r, flag[flagno].template))
6579 {
6580 flag_bits |= flag[flagno].set_bits;
6581 break;
6582 }
6583 }
6584
6585 *p = d;
6586 if (! flag[flagno].template)
6587 goto try_shorter;
6588 }
6589 else
6590 goto try_shorter;
6591 }
6592
6593 (*opcode->parms) (p, flag_bits);
6594 output_inst ();
6595 return;
6596 }
6597
6598 try_shorter:
6599 ;
6600 }
6601 }
6602
6603 /* It wasn't an instruction, but it might be a register alias of the form
6604 alias .req reg. */
6605 q = p;
6606 skip_whitespace (q);
6607
6608 c = *p;
6609 *p = '\0';
6610
6611 if (*q && !strncmp (q, ".req ", 4))
6612 {
6613 int reg;
6614 char * copy_of_str = str;
6615 char * r;
6616
6617 q += 4;
6618 skip_whitespace (q);
6619
6620 for (r = q; *r != '\0'; r++)
6621 if (*r == ' ')
6622 break;
6623
6624 if (r != q)
6625 {
6626 int regnum;
6627 char d = *r;
6628
6629 *r = '\0';
6630 regnum = arm_reg_parse (& q);
6631 *r = d;
6632
6633 reg = arm_reg_parse (& str);
6634
6635 if (reg == FAIL)
6636 {
6637 if (regnum != FAIL)
6638 insert_reg_alias (str, regnum);
6639 else
6640 as_warn (_("register '%s' does not exist\n"), q);
6641 }
6642 else if (regnum != FAIL)
6643 {
6644 if (reg != regnum)
6645 as_warn (_("ignoring redefinition of register alias '%s'"),
6646 copy_of_str);
6647
6648 /* Do not warn about redefinitions to the same alias. */
6649 }
6650 else
6651 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6652 copy_of_str, q);
6653 }
6654 else
6655 as_warn (_("ignoring incomplete .req pseuso op"));
6656
6657 *p = c;
6658 return;
6659 }
6660
6661 *p = c;
6662 as_bad (_("bad instruction `%s'"), start);
6663 }
6664
6665 /* md_parse_option
6666 Invocation line includes a switch not recognized by the base assembler.
6667 See if it's a processor-specific option. These are:
6668 Cpu variants, the arm part is optional:
6669 -m[arm]1 Currently not supported.
6670 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6671 -m[arm]3 Arm 3 processor
6672 -m[arm]6[xx], Arm 6 processors
6673 -m[arm]7[xx][t][[d]m] Arm 7 processors
6674 -m[arm]8[10] Arm 8 processors
6675 -m[arm]9[20][tdmi] Arm 9 processors
6676 -mstrongarm[110[0]] StrongARM processors
6677 -m[arm]v[2345[t]] Arm architectures
6678 -mall All (except the ARM1)
6679 FP variants:
6680 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6681 -mfpe-old (No float load/store multiples)
6682 -mno-fpu Disable all floating point instructions
6683 Run-time endian selection:
6684 -EB big endian cpu
6685 -EL little endian cpu
6686 ARM Procedure Calling Standard:
6687 -mapcs-32 32 bit APCS
6688 -mapcs-26 26 bit APCS
6689 -mapcs-float Pass floats in float regs
6690 -mapcs-reentrant Position independent code
6691 -mthumb-interwork Code supports Arm/Thumb interworking
6692 -moabi Old ELF ABI */
6693
6694 CONST char * md_shortopts = "m:k";
6695
6696 struct option md_longopts[] =
6697 {
6698 #ifdef ARM_BI_ENDIAN
6699 #define OPTION_EB (OPTION_MD_BASE + 0)
6700 {"EB", no_argument, NULL, OPTION_EB},
6701 #define OPTION_EL (OPTION_MD_BASE + 1)
6702 {"EL", no_argument, NULL, OPTION_EL},
6703 #ifdef OBJ_ELF
6704 #define OPTION_OABI (OPTION_MD_BASE +2)
6705 {"oabi", no_argument, NULL, OPTION_OABI},
6706 #endif
6707 #endif
6708 {NULL, no_argument, NULL, 0}
6709 };
6710
6711 size_t md_longopts_size = sizeof (md_longopts);
6712
6713 int
6714 md_parse_option (c, arg)
6715 int c;
6716 char * arg;
6717 {
6718 char * str = arg;
6719
6720 switch (c)
6721 {
6722 #ifdef ARM_BI_ENDIAN
6723 case OPTION_EB:
6724 target_big_endian = 1;
6725 break;
6726 case OPTION_EL:
6727 target_big_endian = 0;
6728 break;
6729 #endif
6730
6731 case 'm':
6732 switch (*str)
6733 {
6734 case 'f':
6735 if (streq (str, "fpa10"))
6736 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6737 else if (streq (str, "fpa11"))
6738 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6739 else if (streq (str, "fpe-old"))
6740 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6741 else
6742 goto bad;
6743 break;
6744
6745 case 'n':
6746 if (streq (str, "no-fpu"))
6747 cpu_variant &= ~FPU_ALL;
6748 break;
6749
6750 #ifdef OBJ_ELF
6751 case 'o':
6752 if (streq (str, "oabi"))
6753 target_oabi = true;
6754 break;
6755 #endif
6756
6757 case 't':
6758 /* Limit assembler to generating only Thumb instructions: */
6759 if (streq (str, "thumb"))
6760 {
6761 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6762 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6763 thumb_mode = 1;
6764 }
6765 else if (streq (str, "thumb-interwork"))
6766 {
6767 if ((cpu_variant & ARM_THUMB) == 0)
6768 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
6769 #if defined OBJ_COFF || defined OBJ_ELF
6770 support_interwork = true;
6771 #endif
6772 }
6773 else
6774 goto bad;
6775 break;
6776
6777 default:
6778 if (streq (str, "all"))
6779 {
6780 cpu_variant = ARM_ALL | FPU_ALL;
6781 return 1;
6782 }
6783 #if defined OBJ_COFF || defined OBJ_ELF
6784 if (! strncmp (str, "apcs-", 5))
6785 {
6786 /* GCC passes on all command line options starting "-mapcs-..."
6787 to us, so we must parse them here. */
6788
6789 str += 5;
6790
6791 if (streq (str, "32"))
6792 {
6793 uses_apcs_26 = false;
6794 return 1;
6795 }
6796 else if (streq (str, "26"))
6797 {
6798 uses_apcs_26 = true;
6799 return 1;
6800 }
6801 else if (streq (str, "frame"))
6802 {
6803 /* Stack frames are being generated - does not affect
6804 linkage of code. */
6805 return 1;
6806 }
6807 else if (streq (str, "stack-check"))
6808 {
6809 /* Stack checking is being performed - does not affect
6810 linkage, but does require that the functions
6811 __rt_stkovf_split_small and __rt_stkovf_split_big be
6812 present in the final link. */
6813
6814 return 1;
6815 }
6816 else if (streq (str, "float"))
6817 {
6818 /* Floating point arguments are being passed in the floating
6819 point registers. This does affect linking, since this
6820 version of the APCS is incompatible with the version that
6821 passes floating points in the integer registers. */
6822
6823 uses_apcs_float = true;
6824 return 1;
6825 }
6826 else if (streq (str, "reentrant"))
6827 {
6828 /* Reentrant code has been generated. This does affect
6829 linking, since there is no point in linking reentrant/
6830 position independent code with absolute position code. */
6831 pic_code = true;
6832 return 1;
6833 }
6834
6835 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6836 return 0;
6837 }
6838 #endif
6839 /* Strip off optional "arm". */
6840 if (! strncmp (str, "arm", 3))
6841 str += 3;
6842
6843 switch (*str)
6844 {
6845 case '1':
6846 if (streq (str, "1"))
6847 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6848 else
6849 goto bad;
6850 break;
6851
6852 case '2':
6853 if (streq (str, "2"))
6854 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6855 else if (streq (str, "250"))
6856 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6857 else
6858 goto bad;
6859 break;
6860
6861 case '3':
6862 if (streq (str, "3"))
6863 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6864 else
6865 goto bad;
6866 break;
6867
6868 case '6':
6869 switch (strtol (str, NULL, 10))
6870 {
6871 case 6:
6872 case 60:
6873 case 600:
6874 case 610:
6875 case 620:
6876 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6877 break;
6878 default:
6879 goto bad;
6880 }
6881 break;
6882
6883 case '7':
6884 /* Eat the processor name. */
6885 switch (strtol (str, & str, 10))
6886 {
6887 case 7:
6888 case 70:
6889 case 700:
6890 case 710:
6891 case 720:
6892 case 7100:
6893 case 7500:
6894 break;
6895 default:
6896 goto bad;
6897 }
6898 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6899 for (; *str; str++)
6900 {
6901 switch (*str)
6902 {
6903 case 't':
6904 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6905 break;
6906
6907 case 'm':
6908 cpu_variant |= ARM_LONGMUL;
6909 break;
6910
6911 case 'f': /* fe => fp enabled cpu. */
6912 if (str[1] == 'e')
6913 ++ str;
6914 else
6915 goto bad;
6916
6917 case 'c': /* Left over from 710c processor name. */
6918 case 'd': /* Debug. */
6919 case 'i': /* Embedded ICE. */
6920 /* Included for completeness in ARM processor naming. */
6921 break;
6922
6923 default:
6924 goto bad;
6925 }
6926 }
6927 break;
6928
6929 case '8':
6930 if (streq (str, "8") || streq (str, "810"))
6931 cpu_variant = (cpu_variant & ~ARM_ANY)
6932 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6933 else
6934 goto bad;
6935 break;
6936
6937 case '9':
6938 if (streq (str, "9"))
6939 cpu_variant = (cpu_variant & ~ARM_ANY)
6940 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6941 else if (streq (str, "920"))
6942 cpu_variant = (cpu_variant & ~ARM_ANY)
6943 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6944 else if (streq (str, "920t"))
6945 cpu_variant = (cpu_variant & ~ARM_ANY)
6946 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6947 else if (streq (str, "9tdmi"))
6948 cpu_variant = (cpu_variant & ~ARM_ANY)
6949 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6950 else
6951 goto bad;
6952 break;
6953
6954 case 's':
6955 if (streq (str, "strongarm")
6956 || streq (str, "strongarm110")
6957 || streq (str, "strongarm1100"))
6958 cpu_variant = (cpu_variant & ~ARM_ANY)
6959 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6960 else
6961 goto bad;
6962 break;
6963
6964 case 'v':
6965 /* Select variant based on architecture rather than
6966 processor. */
6967 switch (*++str)
6968 {
6969 case '2':
6970 switch (*++str)
6971 {
6972 case 'a':
6973 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6974 break;
6975 case 0:
6976 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6977 break;
6978 default:
6979 as_bad (_("Invalid architecture variant -m%s"), arg);
6980 break;
6981 }
6982 break;
6983
6984 case '3':
6985 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6986
6987 switch (*++str)
6988 {
6989 case 'm': cpu_variant |= ARM_LONGMUL; break;
6990 case 0: break;
6991 default:
6992 as_bad (_("Invalid architecture variant -m%s"), arg);
6993 break;
6994 }
6995 break;
6996
6997 case '4':
6998 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
6999
7000 switch (*++str)
7001 {
7002 case 't': cpu_variant |= ARM_THUMB; break;
7003 case 0: break;
7004 default:
7005 as_bad (_("Invalid architecture variant -m%s"), arg);
7006 break;
7007 }
7008 break;
7009
7010 case '5':
7011 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
7012 switch (*++str)
7013 {
7014 case 't': cpu_variant |= ARM_THUMB; break;
7015 case 0: break;
7016 default:
7017 as_bad (_("Invalid architecture variant -m%s"), arg);
7018 break;
7019 }
7020 break;
7021
7022 default:
7023 as_bad (_("Invalid architecture variant -m%s"), arg);
7024 break;
7025 }
7026 break;
7027
7028 default:
7029 bad:
7030 as_bad (_("Invalid processor variant -m%s"), arg);
7031 return 0;
7032 }
7033 }
7034 break;
7035
7036 #if defined OBJ_ELF || defined OBJ_COFF
7037 case 'k':
7038 pic_code = 1;
7039 break;
7040 #endif
7041
7042 default:
7043 return 0;
7044 }
7045
7046 return 1;
7047 }
7048
7049 void
7050 md_show_usage (fp)
7051 FILE * fp;
7052 {
7053 fprintf (fp, _("\
7054 ARM Specific Assembler Options:\n\
7055 -m[arm][<processor name>] select processor variant\n\
7056 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
7057 -mthumb only allow Thumb instructions\n\
7058 -mthumb-interwork mark the assembled code as supporting interworking\n\
7059 -mall allow any instruction\n\
7060 -mfpa10, -mfpa11 select floating point architecture\n\
7061 -mfpe-old don't allow floating-point multiple instructions\n\
7062 -mno-fpu don't allow any floating-point instructions.\n\
7063 -k generate PIC code.\n"));
7064 #if defined OBJ_COFF || defined OBJ_ELF
7065 fprintf (fp, _("\
7066 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
7067 -mapcs-float floating point args are passed in FP regs\n\
7068 -mapcs-reentrant the code is position independent/reentrant\n"));
7069 #endif
7070 #ifdef OBJ_ELF
7071 fprintf (fp, _("\
7072 -moabi support the old ELF ABI\n"));
7073 #endif
7074 #ifdef ARM_BI_ENDIAN
7075 fprintf (fp, _("\
7076 -EB assemble code for a big endian cpu\n\
7077 -EL assemble code for a little endian cpu\n"));
7078 #endif
7079 }
7080
7081 /* We need to be able to fix up arbitrary expressions in some statements.
7082 This is so that we can handle symbols that are an arbitrary distance from
7083 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7084 which returns part of an address in a form which will be valid for
7085 a data instruction. We do this by pushing the expression into a symbol
7086 in the expr_section, and creating a fix for that. */
7087
7088 static void
7089 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
7090 fragS * frag;
7091 int where;
7092 short int size;
7093 expressionS * exp;
7094 int pc_rel;
7095 int reloc;
7096 {
7097 fixS * new_fix;
7098 arm_fix_data * arm_data;
7099
7100 switch (exp->X_op)
7101 {
7102 case O_constant:
7103 case O_symbol:
7104 case O_add:
7105 case O_subtract:
7106 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7107 break;
7108
7109 default:
7110 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7111 pc_rel, reloc);
7112 break;
7113 }
7114
7115 /* Mark whether the fix is to a THUMB instruction, or an ARM
7116 instruction. */
7117 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
7118 new_fix->tc_fix_data = (PTR) arm_data;
7119 arm_data->thumb_mode = thumb_mode;
7120
7121 return;
7122 }
7123
7124 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7125
7126 void
7127 cons_fix_new_arm (frag, where, size, exp)
7128 fragS * frag;
7129 int where;
7130 int size;
7131 expressionS * exp;
7132 {
7133 bfd_reloc_code_real_type type;
7134 int pcrel = 0;
7135
7136 /* Pick a reloc.
7137 FIXME: @@ Should look at CPU word size. */
7138 switch (size)
7139 {
7140 case 1:
7141 type = BFD_RELOC_8;
7142 break;
7143 case 2:
7144 type = BFD_RELOC_16;
7145 break;
7146 case 4:
7147 default:
7148 type = BFD_RELOC_32;
7149 break;
7150 case 8:
7151 type = BFD_RELOC_64;
7152 break;
7153 }
7154
7155 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
7156 }
7157
7158 /* A good place to do this, although this was probably not intended
7159 for this kind of use. We need to dump the literal pool before
7160 references are made to a null symbol pointer. */
7161
7162 void
7163 arm_cleanup ()
7164 {
7165 if (current_poolP == NULL)
7166 return;
7167
7168 /* Put it at the end of text section. */
7169 subseg_set (text_section, 0);
7170 s_ltorg (0);
7171 listing_prev_line ();
7172 }
7173
7174 void
7175 arm_start_line_hook ()
7176 {
7177 last_label_seen = NULL;
7178 }
7179
7180 void
7181 arm_frob_label (sym)
7182 symbolS * sym;
7183 {
7184 last_label_seen = sym;
7185
7186 ARM_SET_THUMB (sym, thumb_mode);
7187
7188 #if defined OBJ_COFF || defined OBJ_ELF
7189 ARM_SET_INTERWORK (sym, support_interwork);
7190 #endif
7191
7192 if (label_is_thumb_function_name)
7193 {
7194 /* When the address of a Thumb function is taken the bottom
7195 bit of that address should be set. This will allow
7196 interworking between Arm and Thumb functions to work
7197 correctly. */
7198
7199 THUMB_SET_FUNC (sym, 1);
7200
7201 label_is_thumb_function_name = false;
7202 }
7203 }
7204
7205 /* Adjust the symbol table. This marks Thumb symbols as distinct from
7206 ARM ones. */
7207
7208 void
7209 arm_adjust_symtab ()
7210 {
7211 #ifdef OBJ_COFF
7212 symbolS * sym;
7213
7214 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
7215 {
7216 if (ARM_IS_THUMB (sym))
7217 {
7218 if (THUMB_IS_FUNC (sym))
7219 {
7220 /* Mark the symbol as a Thumb function. */
7221 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
7222 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
7223 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
7224
7225 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
7226 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
7227 else
7228 as_bad (_("%s: unexpected function type: %d"),
7229 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
7230 }
7231 else switch (S_GET_STORAGE_CLASS (sym))
7232 {
7233 case C_EXT:
7234 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
7235 break;
7236 case C_STAT:
7237 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
7238 break;
7239 case C_LABEL:
7240 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
7241 break;
7242 default:
7243 /* Do nothing. */
7244 break;
7245 }
7246 }
7247
7248 if (ARM_IS_INTERWORK (sym))
7249 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
7250 }
7251 #endif
7252 #ifdef OBJ_ELF
7253 symbolS *sym;
7254 char bind;
7255
7256 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
7257 {
7258 if (ARM_IS_THUMB (sym))
7259 {
7260 elf_symbol_type *elf_sym;
7261
7262 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
7263 bind = ELF_ST_BIND (elf_sym);
7264
7265 /* If it's a .thumb_func, declare it as so,
7266 otherwise tag label as .code 16. */
7267 if (THUMB_IS_FUNC (sym))
7268 elf_sym->internal_elf_sym.st_info =
7269 ELF_ST_INFO (bind, STT_ARM_TFUNC);
7270 else
7271 elf_sym->internal_elf_sym.st_info =
7272 ELF_ST_INFO (bind, STT_ARM_16BIT);
7273 }
7274 }
7275 #endif
7276 }
7277
7278 int
7279 arm_data_in_code ()
7280 {
7281 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7282 {
7283 *input_line_pointer = '/';
7284 input_line_pointer += 5;
7285 *input_line_pointer = 0;
7286 return 1;
7287 }
7288
7289 return 0;
7290 }
7291
7292 char *
7293 arm_canonicalize_symbol_name (name)
7294 char *name;
7295 {
7296 int len;
7297
7298 if (thumb_mode && (len = strlen (name)) > 5
7299 && streq (name + len - 5, "/data"))
7300 *(name + len - 5) = 0;
7301
7302 return name;
7303 }
7304
7305 boolean
7306 arm_validate_fix (fixP)
7307 fixS *fixP;
7308 {
7309 /* If the destination of the branch is a defined symbol which does not have
7310 the THUMB_FUNC attribute, then we must be calling a function which has
7311 the (interfacearm) attribute. We look for the Thumb entry point to that
7312 function and change the branch to refer to that function instead. */
7313 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
7314 && fixP->fx_addsy != NULL
7315 && S_IS_DEFINED (fixP->fx_addsy)
7316 && ! THUMB_IS_FUNC (fixP->fx_addsy))
7317 {
7318 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
7319 return true;
7320 }
7321
7322 return false;
7323 }
7324
7325 #ifdef OBJ_ELF
7326 /* Relocations against Thumb function names must be left unadjusted,
7327 so that the linker can use this information to correctly set the
7328 bottom bit of their addresses. The MIPS version of this function
7329 also prevents relocations that are mips-16 specific, but I do not
7330 know why it does this.
7331
7332 FIXME:
7333 There is one other problem that ought to be addressed here, but
7334 which currently is not: Taking the address of a label (rather
7335 than a function) and then later jumping to that address. Such
7336 addresses also ought to have their bottom bit set (assuming that
7337 they reside in Thumb code), but at the moment they will not. */
7338
7339 boolean
7340 arm_fix_adjustable (fixP)
7341 fixS *fixP;
7342 {
7343 if (fixP->fx_addsy == NULL)
7344 return 1;
7345
7346 /* Prevent all adjustments to global symbols. */
7347 if (S_IS_EXTERN (fixP->fx_addsy))
7348 return 0;
7349
7350 if (S_IS_WEAK (fixP->fx_addsy))
7351 return 0;
7352
7353 if (THUMB_IS_FUNC (fixP->fx_addsy)
7354 && fixP->fx_subsy == NULL)
7355 return 0;
7356
7357 /* We need the symbol name for the VTABLE entries. */
7358 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7359 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7360 return 0;
7361
7362 return 1;
7363 }
7364
7365 const char *
7366 elf32_arm_target_format ()
7367 {
7368 if (target_big_endian)
7369 {
7370 if (target_oabi)
7371 return "elf32-bigarm-oabi";
7372 else
7373 return "elf32-bigarm";
7374 }
7375 else
7376 {
7377 if (target_oabi)
7378 return "elf32-littlearm-oabi";
7379 else
7380 return "elf32-littlearm";
7381 }
7382 }
7383
7384 void
7385 armelf_frob_symbol (symp, puntp)
7386 symbolS * symp;
7387 int * puntp;
7388 {
7389 elf_frob_symbol (symp, puntp);
7390 }
7391
7392 int
7393 arm_force_relocation (fixp)
7394 struct fix * fixp;
7395 {
7396 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7397 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7398 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
7399 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
7400 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
7401 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
7402 return 1;
7403
7404 return 0;
7405 }
7406
7407 static bfd_reloc_code_real_type
7408 arm_parse_reloc ()
7409 {
7410 char id [16];
7411 char * ip;
7412 unsigned int i;
7413 static struct
7414 {
7415 char * str;
7416 int len;
7417 bfd_reloc_code_real_type reloc;
7418 }
7419 reloc_map[] =
7420 {
7421 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
7422 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7423 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7424 /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
7425 branch instructions generated by GCC for PLT relocs. */
7426 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7427 { NULL, 0, BFD_RELOC_UNUSED }
7428 #undef MAP
7429 };
7430
7431 for (i = 0, ip = input_line_pointer;
7432 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7433 i++, ip++)
7434 id[i] = tolower (*ip);
7435
7436 for (i = 0; reloc_map[i].str; i++)
7437 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7438 break;
7439
7440 input_line_pointer += reloc_map[i].len;
7441
7442 return reloc_map[i].reloc;
7443 }
7444
7445 static void
7446 s_arm_elf_cons (nbytes)
7447 int nbytes;
7448 {
7449 expressionS exp;
7450
7451 #ifdef md_flush_pending_output
7452 md_flush_pending_output ();
7453 #endif
7454
7455 if (is_it_end_of_statement ())
7456 {
7457 demand_empty_rest_of_line ();
7458 return;
7459 }
7460
7461 #ifdef md_cons_align
7462 md_cons_align (nbytes);
7463 #endif
7464
7465 do
7466 {
7467 bfd_reloc_code_real_type reloc;
7468
7469 expression (& exp);
7470
7471 if (exp.X_op == O_symbol
7472 && *input_line_pointer == '('
7473 && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED)
7474 {
7475 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
7476 int size = bfd_get_reloc_size (howto);
7477
7478 if (size > nbytes)
7479 as_bad ("%s relocations do not fit in %d bytes",
7480 howto->name, nbytes);
7481 else
7482 {
7483 register char *p = frag_more ((int) nbytes);
7484 int offset = nbytes - size;
7485
7486 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7487 &exp, 0, reloc);
7488 }
7489 }
7490 else
7491 emit_expr (&exp, (unsigned int) nbytes);
7492 }
7493 while (*input_line_pointer++ == ',');
7494
7495 /* Put terminator back into stream. */
7496 input_line_pointer --;
7497 demand_empty_rest_of_line ();
7498 }
7499
7500 #endif /* OBJ_ELF */
GDB Binutils - Deliverables
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