1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
158 static const arm_feature_set
*object_arch
= NULL
;
160 /* Constants for known architecture features. */
161 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
162 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
163 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
164 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
165 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
166 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
167 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
168 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
191 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
192 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
193 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
194 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
195 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
196 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
197 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
198 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_arch_any
= ARM_ANY
;
201 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
202 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
203 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
205 static const arm_feature_set arm_cext_iwmmxt2
=
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
207 static const arm_feature_set arm_cext_iwmmxt
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
209 static const arm_feature_set arm_cext_xscale
=
210 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
211 static const arm_feature_set arm_cext_maverick
=
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
213 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
214 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
215 static const arm_feature_set fpu_vfp_ext_v1xd
=
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
217 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
218 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
220 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
221 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
222 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
224 static int mfloat_abi_opt
= -1;
225 /* Record user cpu selection for object attributes. */
226 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
227 /* Must be long enough to hold any of the names in arm_cpus. */
228 static char selected_cpu_name
[16];
231 static int meabi_flags
= EABI_DEFAULT
;
233 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
239 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
244 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
245 symbolS
* GOT_symbol
;
248 /* 0: assemble for ARM,
249 1: assemble for Thumb,
250 2: assemble for Thumb even though target CPU does not support thumb
252 static int thumb_mode
= 0;
254 /* If unified_syntax is true, we are processing the new unified
255 ARM/Thumb syntax. Important differences from the old ARM mode:
257 - Immediate operands do not require a # prefix.
258 - Conditional affixes always appear at the end of the
259 instruction. (For backward compatibility, those instructions
260 that formerly had them in the middle, continue to accept them
262 - The IT instruction may appear, and if it does is validated
263 against subsequent conditional affixes. It does not generate
266 Important differences from the old Thumb mode:
268 - Immediate operands do not require a # prefix.
269 - Most of the V6T2 instructions are only available in unified mode.
270 - The .N and .W suffixes are recognized and honored (it is an error
271 if they cannot be honored).
272 - All instructions set the flags if and only if they have an 's' affix.
273 - Conditional affixes may be used. They are validated against
274 preceding IT instructions. Unlike ARM mode, you cannot use a
275 conditional affix except in the scope of an IT instruction. */
277 static bfd_boolean unified_syntax
= FALSE
;
292 enum neon_el_type type
;
296 #define NEON_MAX_TYPE_ELS 4
300 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
307 unsigned long instruction
;
311 /* "uncond_value" is set to the value in place of the conditional field in
312 unconditional versions of the instruction, or -1 if nothing is
315 struct neon_type vectype
;
316 /* Set to the opcode if the instruction needs relaxation.
317 Zero if the instruction is not relaxed. */
321 bfd_reloc_code_real_type type
;
330 struct neon_type_el vectype
;
331 unsigned present
: 1; /* Operand present. */
332 unsigned isreg
: 1; /* Operand was a register. */
333 unsigned immisreg
: 1; /* .imm field is a second register. */
334 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
335 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
336 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
338 instructions. This allows us to disambiguate ARM <-> vector insns. */
339 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
340 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
341 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
342 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
343 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
344 unsigned writeback
: 1; /* Operand has trailing ! */
345 unsigned preind
: 1; /* Preindexed address. */
346 unsigned postind
: 1; /* Postindexed address. */
347 unsigned negative
: 1; /* Index register was negated. */
348 unsigned shifted
: 1; /* Shift applied to operation. */
349 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
353 static struct arm_it inst
;
355 #define NUM_FLOAT_VALS 8
357 const char * fp_const
[] =
359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
362 /* Number of littlenums required to hold an extended precision number. */
363 #define MAX_LITTLENUMS 6
365 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
375 #define CP_T_X 0x00008000
376 #define CP_T_Y 0x00400000
378 #define CONDS_BIT 0x00100000
379 #define LOAD_BIT 0x00100000
381 #define DOUBLE_LOAD_FLAG 0x00000001
385 const char * template;
389 #define COND_ALWAYS 0xE
393 const char *template;
397 struct asm_barrier_opt
399 const char *template;
403 /* The bit that distinguishes CPSR and SPSR. */
404 #define SPSR_BIT (1 << 22)
406 /* The individual PSR flag bits. */
407 #define PSR_c (1 << 16)
408 #define PSR_x (1 << 17)
409 #define PSR_s (1 << 18)
410 #define PSR_f (1 << 19)
415 bfd_reloc_code_real_type reloc
;
420 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
421 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
426 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
429 /* Bits for DEFINED field in neon_typed_alias. */
430 #define NTA_HASTYPE 1
431 #define NTA_HASINDEX 2
433 struct neon_typed_alias
435 unsigned char defined
;
437 struct neon_type_el eltype
;
440 /* ARM register categories. This includes coprocessor numbers and various
441 architecture extensions' registers. */
467 /* Structure for a hash table entry for a register.
468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
469 information which states whether a vector type or index is specified (for a
470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
474 unsigned char number
;
476 unsigned char builtin
;
477 struct neon_typed_alias
*neon
;
480 /* Diagnostics used when we don't get a register of the expected type. */
481 const char *const reg_expected_msgs
[] =
483 N_("ARM register expected"),
484 N_("bad or missing co-processor number"),
485 N_("co-processor register expected"),
486 N_("FPA register expected"),
487 N_("VFP single precision register expected"),
488 N_("VFP/Neon double precision register expected"),
489 N_("Neon quad precision register expected"),
490 N_("VFP single or double precision register expected"),
491 N_("Neon double or quad precision register expected"),
492 N_("VFP single, double or Neon quad precision register expected"),
493 N_("VFP system register expected"),
494 N_("Maverick MVF register expected"),
495 N_("Maverick MVD register expected"),
496 N_("Maverick MVFX register expected"),
497 N_("Maverick MVDX register expected"),
498 N_("Maverick MVAX register expected"),
499 N_("Maverick DSPSC register expected"),
500 N_("iWMMXt data register expected"),
501 N_("iWMMXt control register expected"),
502 N_("iWMMXt scalar register expected"),
503 N_("XScale accumulator register expected"),
506 /* Some well known registers that we refer to directly elsewhere. */
511 /* ARM instructions take 4bytes in the object file, Thumb instructions
517 /* Basic string to match. */
518 const char *template;
520 /* Parameters to instruction. */
521 unsigned char operands
[8];
523 /* Conditional tag - see opcode_lookup. */
524 unsigned int tag
: 4;
526 /* Basic instruction code. */
527 unsigned int avalue
: 28;
529 /* Thumb-format instruction code. */
532 /* Which architecture variant provides this instruction. */
533 const arm_feature_set
*avariant
;
534 const arm_feature_set
*tvariant
;
536 /* Function to call to encode instruction in ARM format. */
537 void (* aencode
) (void);
539 /* Function to call to encode instruction in Thumb format. */
540 void (* tencode
) (void);
543 /* Defines for various bits that we will want to toggle. */
544 #define INST_IMMEDIATE 0x02000000
545 #define OFFSET_REG 0x02000000
546 #define HWOFFSET_IMM 0x00400000
547 #define SHIFT_BY_REG 0x00000010
548 #define PRE_INDEX 0x01000000
549 #define INDEX_UP 0x00800000
550 #define WRITE_BACK 0x00200000
551 #define LDM_TYPE_2_OR_3 0x00400000
552 #define CPSI_MMOD 0x00020000
554 #define LITERAL_MASK 0xf000f000
555 #define OPCODE_MASK 0xfe1fffff
556 #define V4_STR_BIT 0x00000020
558 #define T2_SUBS_PC_LR 0xf3de8f00
560 #define DATA_OP_SHIFT 21
562 #define T2_OPCODE_MASK 0xfe1fffff
563 #define T2_DATA_OP_SHIFT 21
565 /* Codes to distinguish the arithmetic instructions. */
576 #define OPCODE_CMP 10
577 #define OPCODE_CMN 11
578 #define OPCODE_ORR 12
579 #define OPCODE_MOV 13
580 #define OPCODE_BIC 14
581 #define OPCODE_MVN 15
583 #define T2_OPCODE_AND 0
584 #define T2_OPCODE_BIC 1
585 #define T2_OPCODE_ORR 2
586 #define T2_OPCODE_ORN 3
587 #define T2_OPCODE_EOR 4
588 #define T2_OPCODE_ADD 8
589 #define T2_OPCODE_ADC 10
590 #define T2_OPCODE_SBC 11
591 #define T2_OPCODE_SUB 13
592 #define T2_OPCODE_RSB 14
594 #define T_OPCODE_MUL 0x4340
595 #define T_OPCODE_TST 0x4200
596 #define T_OPCODE_CMN 0x42c0
597 #define T_OPCODE_NEG 0x4240
598 #define T_OPCODE_MVN 0x43c0
600 #define T_OPCODE_ADD_R3 0x1800
601 #define T_OPCODE_SUB_R3 0x1a00
602 #define T_OPCODE_ADD_HI 0x4400
603 #define T_OPCODE_ADD_ST 0xb000
604 #define T_OPCODE_SUB_ST 0xb080
605 #define T_OPCODE_ADD_SP 0xa800
606 #define T_OPCODE_ADD_PC 0xa000
607 #define T_OPCODE_ADD_I8 0x3000
608 #define T_OPCODE_SUB_I8 0x3800
609 #define T_OPCODE_ADD_I3 0x1c00
610 #define T_OPCODE_SUB_I3 0x1e00
612 #define T_OPCODE_ASR_R 0x4100
613 #define T_OPCODE_LSL_R 0x4080
614 #define T_OPCODE_LSR_R 0x40c0
615 #define T_OPCODE_ROR_R 0x41c0
616 #define T_OPCODE_ASR_I 0x1000
617 #define T_OPCODE_LSL_I 0x0000
618 #define T_OPCODE_LSR_I 0x0800
620 #define T_OPCODE_MOV_I8 0x2000
621 #define T_OPCODE_CMP_I8 0x2800
622 #define T_OPCODE_CMP_LR 0x4280
623 #define T_OPCODE_MOV_HR 0x4600
624 #define T_OPCODE_CMP_HR 0x4500
626 #define T_OPCODE_LDR_PC 0x4800
627 #define T_OPCODE_LDR_SP 0x9800
628 #define T_OPCODE_STR_SP 0x9000
629 #define T_OPCODE_LDR_IW 0x6800
630 #define T_OPCODE_STR_IW 0x6000
631 #define T_OPCODE_LDR_IH 0x8800
632 #define T_OPCODE_STR_IH 0x8000
633 #define T_OPCODE_LDR_IB 0x7800
634 #define T_OPCODE_STR_IB 0x7000
635 #define T_OPCODE_LDR_RW 0x5800
636 #define T_OPCODE_STR_RW 0x5000
637 #define T_OPCODE_LDR_RH 0x5a00
638 #define T_OPCODE_STR_RH 0x5200
639 #define T_OPCODE_LDR_RB 0x5c00
640 #define T_OPCODE_STR_RB 0x5400
642 #define T_OPCODE_PUSH 0xb400
643 #define T_OPCODE_POP 0xbc00
645 #define T_OPCODE_BRANCH 0xe000
647 #define THUMB_SIZE 2 /* Size of thumb instruction. */
648 #define THUMB_PP_PC_LR 0x0100
649 #define THUMB_LOAD_BIT 0x0800
650 #define THUMB2_LOAD_BIT 0x00100000
652 #define BAD_ARGS _("bad arguments to instruction")
653 #define BAD_PC _("r15 not allowed here")
654 #define BAD_COND _("instruction cannot be conditional")
655 #define BAD_OVERLAP _("registers may not be the same")
656 #define BAD_HIREG _("lo register required")
657 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
658 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
659 #define BAD_BRANCH _("branch must be last instruction in IT block")
660 #define BAD_NOT_IT _("instruction not allowed in IT block")
661 #define BAD_FPU _("selected FPU does not support instruction")
663 static struct hash_control
*arm_ops_hsh
;
664 static struct hash_control
*arm_cond_hsh
;
665 static struct hash_control
*arm_shift_hsh
;
666 static struct hash_control
*arm_psr_hsh
;
667 static struct hash_control
*arm_v7m_psr_hsh
;
668 static struct hash_control
*arm_reg_hsh
;
669 static struct hash_control
*arm_reloc_hsh
;
670 static struct hash_control
*arm_barrier_opt_hsh
;
672 /* Stuff needed to resolve the label ambiguity
681 symbolS
* last_label_seen
;
682 static int label_is_thumb_function_name
= FALSE
;
684 /* Literal pool structure. Held on a per-section
685 and per-sub-section basis. */
687 #define MAX_LITERAL_POOL_SIZE 1024
688 typedef struct literal_pool
690 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
691 unsigned int next_free_entry
;
696 struct literal_pool
* next
;
699 /* Pointer to a linked list of literal pools. */
700 literal_pool
* list_of_pools
= NULL
;
702 /* State variables for IT block handling. */
703 static bfd_boolean current_it_mask
= 0;
704 static int current_cc
;
708 /* This array holds the chars that always start a comment. If the
709 pre-processor is disabled, these aren't very useful. */
710 const char comment_chars
[] = "@";
712 /* This array holds the chars that only start a comment at the beginning of
713 a line. If the line seems to have the form '# 123 filename'
714 .line and .file directives will appear in the pre-processed output. */
715 /* Note that input_file.c hand checks for '#' at the beginning of the
716 first line of the input file. This is because the compiler outputs
717 #NO_APP at the beginning of its output. */
718 /* Also note that comments like this one will always work. */
719 const char line_comment_chars
[] = "#";
721 const char line_separator_chars
[] = ";";
723 /* Chars that can be used to separate mant
724 from exp in floating point numbers. */
725 const char EXP_CHARS
[] = "eE";
727 /* Chars that mean this number is a floating point constant. */
731 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
733 /* Prefix characters that indicate the start of an immediate
735 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
737 /* Separator character handling. */
739 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
742 skip_past_char (char ** str
, char c
)
752 #define skip_past_comma(str) skip_past_char (str, ',')
754 /* Arithmetic expressions (possibly involving symbols). */
756 /* Return TRUE if anything in the expression is a bignum. */
759 walk_no_bignums (symbolS
* sp
)
761 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
764 if (symbol_get_value_expression (sp
)->X_add_symbol
)
766 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
767 || (symbol_get_value_expression (sp
)->X_op_symbol
768 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
774 static int in_my_get_expression
= 0;
776 /* Third argument to my_get_expression. */
777 #define GE_NO_PREFIX 0
778 #define GE_IMM_PREFIX 1
779 #define GE_OPT_PREFIX 2
780 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
781 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
782 #define GE_OPT_PREFIX_BIG 3
785 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
790 /* In unified syntax, all prefixes are optional. */
792 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
797 case GE_NO_PREFIX
: break;
799 if (!is_immediate_prefix (**str
))
801 inst
.error
= _("immediate expression requires a # prefix");
807 case GE_OPT_PREFIX_BIG
:
808 if (is_immediate_prefix (**str
))
814 memset (ep
, 0, sizeof (expressionS
));
816 save_in
= input_line_pointer
;
817 input_line_pointer
= *str
;
818 in_my_get_expression
= 1;
819 seg
= expression (ep
);
820 in_my_get_expression
= 0;
822 if (ep
->X_op
== O_illegal
)
824 /* We found a bad expression in md_operand(). */
825 *str
= input_line_pointer
;
826 input_line_pointer
= save_in
;
827 if (inst
.error
== NULL
)
828 inst
.error
= _("bad expression");
833 if (seg
!= absolute_section
834 && seg
!= text_section
835 && seg
!= data_section
836 && seg
!= bss_section
837 && seg
!= undefined_section
)
839 inst
.error
= _("bad segment");
840 *str
= input_line_pointer
;
841 input_line_pointer
= save_in
;
846 /* Get rid of any bignums now, so that we don't generate an error for which
847 we can't establish a line number later on. Big numbers are never valid
848 in instructions, which is where this routine is always called. */
849 if (prefix_mode
!= GE_OPT_PREFIX_BIG
850 && (ep
->X_op
== O_big
852 && (walk_no_bignums (ep
->X_add_symbol
)
854 && walk_no_bignums (ep
->X_op_symbol
))))))
856 inst
.error
= _("invalid constant");
857 *str
= input_line_pointer
;
858 input_line_pointer
= save_in
;
862 *str
= input_line_pointer
;
863 input_line_pointer
= save_in
;
867 /* Turn a string in input_line_pointer into a floating point constant
868 of type TYPE, and store the appropriate bytes in *LITP. The number
869 of LITTLENUMS emitted is stored in *SIZEP. An error message is
870 returned, or NULL on OK.
872 Note that fp constants aren't represent in the normal way on the ARM.
873 In big endian mode, things are as expected. However, in little endian
874 mode fp constants are big-endian word-wise, and little-endian byte-wise
875 within the words. For example, (double) 1.1 in big endian mode is
876 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
877 the byte sequence 99 99 f1 3f 9a 99 99 99.
879 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
882 md_atof (int type
, char * litP
, int * sizeP
)
885 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
917 return _("Unrecognized or unsupported floating point constant");
920 t
= atof_ieee (input_line_pointer
, type
, words
);
922 input_line_pointer
= t
;
923 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
925 if (target_big_endian
)
927 for (i
= 0; i
< prec
; i
++)
929 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
930 litP
+= sizeof (LITTLENUM_TYPE
);
935 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
936 for (i
= prec
- 1; i
>= 0; i
--)
938 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
939 litP
+= sizeof (LITTLENUM_TYPE
);
942 /* For a 4 byte float the order of elements in `words' is 1 0.
943 For an 8 byte float the order is 1 0 3 2. */
944 for (i
= 0; i
< prec
; i
+= 2)
946 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
947 sizeof (LITTLENUM_TYPE
));
948 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
949 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
950 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
957 /* We handle all bad expressions here, so that we can report the faulty
958 instruction in the error message. */
960 md_operand (expressionS
* expr
)
962 if (in_my_get_expression
)
963 expr
->X_op
= O_illegal
;
966 /* Immediate values. */
968 /* Generic immediate-value read function for use in directives.
969 Accepts anything that 'expression' can fold to a constant.
970 *val receives the number. */
973 immediate_for_directive (int *val
)
976 exp
.X_op
= O_illegal
;
978 if (is_immediate_prefix (*input_line_pointer
))
980 input_line_pointer
++;
984 if (exp
.X_op
!= O_constant
)
986 as_bad (_("expected #constant"));
987 ignore_rest_of_line ();
990 *val
= exp
.X_add_number
;
995 /* Register parsing. */
997 /* Generic register parser. CCP points to what should be the
998 beginning of a register name. If it is indeed a valid register
999 name, advance CCP over it and return the reg_entry structure;
1000 otherwise return NULL. Does not issue diagnostics. */
1002 static struct reg_entry
*
1003 arm_reg_parse_multi (char **ccp
)
1007 struct reg_entry
*reg
;
1009 #ifdef REGISTER_PREFIX
1010 if (*start
!= REGISTER_PREFIX
)
1014 #ifdef OPTIONAL_REGISTER_PREFIX
1015 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1020 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1025 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1027 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1037 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1038 enum arm_reg_type type
)
1040 /* Alternative syntaxes are accepted for a few register classes. */
1047 /* Generic coprocessor register names are allowed for these. */
1048 if (reg
&& reg
->type
== REG_TYPE_CN
)
1053 /* For backward compatibility, a bare number is valid here. */
1055 unsigned long processor
= strtoul (start
, ccp
, 10);
1056 if (*ccp
!= start
&& processor
<= 15)
1060 case REG_TYPE_MMXWC
:
1061 /* WC includes WCG. ??? I'm not sure this is true for all
1062 instructions that take WC registers. */
1063 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1074 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1075 return value is the register number or FAIL. */
1078 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1081 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1084 /* Do not allow a scalar (reg+index) to parse as a register. */
1085 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1088 if (reg
&& reg
->type
== type
)
1091 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1098 /* Parse a Neon type specifier. *STR should point at the leading '.'
1099 character. Does no verification at this stage that the type fits the opcode
1106 Can all be legally parsed by this function.
1108 Fills in neon_type struct pointer with parsed information, and updates STR
1109 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1110 type, FAIL if not. */
1113 parse_neon_type (struct neon_type
*type
, char **str
)
1120 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1122 enum neon_el_type thistype
= NT_untyped
;
1123 unsigned thissize
= -1u;
1130 /* Just a size without an explicit type. */
1134 switch (TOLOWER (*ptr
))
1136 case 'i': thistype
= NT_integer
; break;
1137 case 'f': thistype
= NT_float
; break;
1138 case 'p': thistype
= NT_poly
; break;
1139 case 's': thistype
= NT_signed
; break;
1140 case 'u': thistype
= NT_unsigned
; break;
1142 thistype
= NT_float
;
1147 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1153 /* .f is an abbreviation for .f32. */
1154 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1159 thissize
= strtoul (ptr
, &ptr
, 10);
1161 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1164 as_bad (_("bad size %d in type specifier"), thissize
);
1172 type
->el
[type
->elems
].type
= thistype
;
1173 type
->el
[type
->elems
].size
= thissize
;
1178 /* Empty/missing type is not a successful parse. */
1179 if (type
->elems
== 0)
1187 /* Errors may be set multiple times during parsing or bit encoding
1188 (particularly in the Neon bits), but usually the earliest error which is set
1189 will be the most meaningful. Avoid overwriting it with later (cascading)
1190 errors by calling this function. */
1193 first_error (const char *err
)
1199 /* Parse a single type, e.g. ".s32", leading period included. */
1201 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1204 struct neon_type optype
;
1208 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1210 if (optype
.elems
== 1)
1211 *vectype
= optype
.el
[0];
1214 first_error (_("only one type should be specified for operand"));
1220 first_error (_("vector type expected"));
1232 /* Special meanings for indices (which have a range of 0-7), which will fit into
1235 #define NEON_ALL_LANES 15
1236 #define NEON_INTERLEAVE_LANES 14
1238 /* Parse either a register or a scalar, with an optional type. Return the
1239 register number, and optionally fill in the actual type of the register
1240 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1241 type/index information in *TYPEINFO. */
1244 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1245 enum arm_reg_type
*rtype
,
1246 struct neon_typed_alias
*typeinfo
)
1249 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1250 struct neon_typed_alias atype
;
1251 struct neon_type_el parsetype
;
1255 atype
.eltype
.type
= NT_invtype
;
1256 atype
.eltype
.size
= -1;
1258 /* Try alternate syntax for some types of register. Note these are mutually
1259 exclusive with the Neon syntax extensions. */
1262 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1270 /* Undo polymorphism when a set of register types may be accepted. */
1271 if ((type
== REG_TYPE_NDQ
1272 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1273 || (type
== REG_TYPE_VFSD
1274 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1275 || (type
== REG_TYPE_NSDQ
1276 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1277 || reg
->type
== REG_TYPE_NQ
))
1278 || (type
== REG_TYPE_MMXWC
1279 && (reg
->type
== REG_TYPE_MMXWCG
)))
1282 if (type
!= reg
->type
)
1288 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1290 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1292 first_error (_("can't redefine type for operand"));
1295 atype
.defined
|= NTA_HASTYPE
;
1296 atype
.eltype
= parsetype
;
1299 if (skip_past_char (&str
, '[') == SUCCESS
)
1301 if (type
!= REG_TYPE_VFD
)
1303 first_error (_("only D registers may be indexed"));
1307 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1309 first_error (_("can't change index for operand"));
1313 atype
.defined
|= NTA_HASINDEX
;
1315 if (skip_past_char (&str
, ']') == SUCCESS
)
1316 atype
.index
= NEON_ALL_LANES
;
1321 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1323 if (exp
.X_op
!= O_constant
)
1325 first_error (_("constant expression required"));
1329 if (skip_past_char (&str
, ']') == FAIL
)
1332 atype
.index
= exp
.X_add_number
;
1347 /* Like arm_reg_parse, but allow allow the following extra features:
1348 - If RTYPE is non-zero, return the (possibly restricted) type of the
1349 register (e.g. Neon double or quad reg when either has been requested).
1350 - If this is a Neon vector type with additional type information, fill
1351 in the struct pointed to by VECTYPE (if non-NULL).
1352 This function will fault on encountering a scalar. */
1355 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1356 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1358 struct neon_typed_alias atype
;
1360 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1365 /* Do not allow a scalar (reg+index) to parse as a register. */
1366 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1368 first_error (_("register operand expected, but got scalar"));
1373 *vectype
= atype
.eltype
;
1380 #define NEON_SCALAR_REG(X) ((X) >> 4)
1381 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1383 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1384 have enough information to be able to do a good job bounds-checking. So, we
1385 just do easy checks here, and do further checks later. */
1388 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1392 struct neon_typed_alias atype
;
1394 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1396 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1399 if (atype
.index
== NEON_ALL_LANES
)
1401 first_error (_("scalar must have an index"));
1404 else if (atype
.index
>= 64 / elsize
)
1406 first_error (_("scalar index out of range"));
1411 *type
= atype
.eltype
;
1415 return reg
* 16 + atype
.index
;
1418 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1420 parse_reg_list (char ** strp
)
1422 char * str
= * strp
;
1426 /* We come back here if we get ranges concatenated by '+' or '|'. */
1441 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1443 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1453 first_error (_("bad range in register list"));
1457 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1459 if (range
& (1 << i
))
1461 (_("Warning: duplicated register (r%d) in register list"),
1469 if (range
& (1 << reg
))
1470 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1472 else if (reg
<= cur_reg
)
1473 as_tsktsk (_("Warning: register range not in ascending order"));
1478 while (skip_past_comma (&str
) != FAIL
1479 || (in_range
= 1, *str
++ == '-'));
1484 first_error (_("missing `}'"));
1492 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1495 if (expr
.X_op
== O_constant
)
1497 if (expr
.X_add_number
1498 != (expr
.X_add_number
& 0x0000ffff))
1500 inst
.error
= _("invalid register mask");
1504 if ((range
& expr
.X_add_number
) != 0)
1506 int regno
= range
& expr
.X_add_number
;
1509 regno
= (1 << regno
) - 1;
1511 (_("Warning: duplicated register (r%d) in register list"),
1515 range
|= expr
.X_add_number
;
1519 if (inst
.reloc
.type
!= 0)
1521 inst
.error
= _("expression too complex");
1525 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1526 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1527 inst
.reloc
.pc_rel
= 0;
1531 if (*str
== '|' || *str
== '+')
1537 while (another_range
);
1543 /* Types of registers in a list. */
1552 /* Parse a VFP register list. If the string is invalid return FAIL.
1553 Otherwise return the number of registers, and set PBASE to the first
1554 register. Parses registers of type ETYPE.
1555 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1556 - Q registers can be used to specify pairs of D registers
1557 - { } can be omitted from around a singleton register list
1558 FIXME: This is not implemented, as it would require backtracking in
1561 This could be done (the meaning isn't really ambiguous), but doesn't
1562 fit in well with the current parsing framework.
1563 - 32 D registers may be used (also true for VFPv3).
1564 FIXME: Types are ignored in these register lists, which is probably a
1568 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1573 enum arm_reg_type regtype
= 0;
1577 unsigned long mask
= 0;
1582 inst
.error
= _("expecting {");
1591 regtype
= REG_TYPE_VFS
;
1596 regtype
= REG_TYPE_VFD
;
1599 case REGLIST_NEON_D
:
1600 regtype
= REG_TYPE_NDQ
;
1604 if (etype
!= REGLIST_VFP_S
)
1606 /* VFPv3 allows 32 D registers. */
1607 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1611 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1614 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1621 base_reg
= max_regs
;
1625 int setmask
= 1, addregs
= 1;
1627 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1629 if (new_base
== FAIL
)
1631 first_error (_(reg_expected_msgs
[regtype
]));
1635 if (new_base
>= max_regs
)
1637 first_error (_("register out of range in list"));
1641 /* Note: a value of 2 * n is returned for the register Q<n>. */
1642 if (regtype
== REG_TYPE_NQ
)
1648 if (new_base
< base_reg
)
1649 base_reg
= new_base
;
1651 if (mask
& (setmask
<< new_base
))
1653 first_error (_("invalid register list"));
1657 if ((mask
>> new_base
) != 0 && ! warned
)
1659 as_tsktsk (_("register list not in ascending order"));
1663 mask
|= setmask
<< new_base
;
1666 if (*str
== '-') /* We have the start of a range expression */
1672 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1675 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1679 if (high_range
>= max_regs
)
1681 first_error (_("register out of range in list"));
1685 if (regtype
== REG_TYPE_NQ
)
1686 high_range
= high_range
+ 1;
1688 if (high_range
<= new_base
)
1690 inst
.error
= _("register range not in ascending order");
1694 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1696 if (mask
& (setmask
<< new_base
))
1698 inst
.error
= _("invalid register list");
1702 mask
|= setmask
<< new_base
;
1707 while (skip_past_comma (&str
) != FAIL
);
1711 /* Sanity check -- should have raised a parse error above. */
1712 if (count
== 0 || count
> max_regs
)
1717 /* Final test -- the registers must be consecutive. */
1719 for (i
= 0; i
< count
; i
++)
1721 if ((mask
& (1u << i
)) == 0)
1723 inst
.error
= _("non-contiguous register range");
1733 /* True if two alias types are the same. */
1736 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1744 if (a
->defined
!= b
->defined
)
1747 if ((a
->defined
& NTA_HASTYPE
) != 0
1748 && (a
->eltype
.type
!= b
->eltype
.type
1749 || a
->eltype
.size
!= b
->eltype
.size
))
1752 if ((a
->defined
& NTA_HASINDEX
) != 0
1753 && (a
->index
!= b
->index
))
1759 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1760 The base register is put in *PBASE.
1761 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1763 The register stride (minus one) is put in bit 4 of the return value.
1764 Bits [6:5] encode the list length (minus one).
1765 The type of the list elements is put in *ELTYPE, if non-NULL. */
1767 #define NEON_LANE(X) ((X) & 0xf)
1768 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1769 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1772 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1773 struct neon_type_el
*eltype
)
1780 int leading_brace
= 0;
1781 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1783 const char *const incr_error
= "register stride must be 1 or 2";
1784 const char *const type_error
= "mismatched element/structure types in list";
1785 struct neon_typed_alias firsttype
;
1787 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1792 struct neon_typed_alias atype
;
1793 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1797 first_error (_(reg_expected_msgs
[rtype
]));
1804 if (rtype
== REG_TYPE_NQ
)
1811 else if (reg_incr
== -1)
1813 reg_incr
= getreg
- base_reg
;
1814 if (reg_incr
< 1 || reg_incr
> 2)
1816 first_error (_(incr_error
));
1820 else if (getreg
!= base_reg
+ reg_incr
* count
)
1822 first_error (_(incr_error
));
1826 if (!neon_alias_types_same (&atype
, &firsttype
))
1828 first_error (_(type_error
));
1832 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1836 struct neon_typed_alias htype
;
1837 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1839 lane
= NEON_INTERLEAVE_LANES
;
1840 else if (lane
!= NEON_INTERLEAVE_LANES
)
1842 first_error (_(type_error
));
1847 else if (reg_incr
!= 1)
1849 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1853 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1856 first_error (_(reg_expected_msgs
[rtype
]));
1859 if (!neon_alias_types_same (&htype
, &firsttype
))
1861 first_error (_(type_error
));
1864 count
+= hireg
+ dregs
- getreg
;
1868 /* If we're using Q registers, we can't use [] or [n] syntax. */
1869 if (rtype
== REG_TYPE_NQ
)
1875 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1879 else if (lane
!= atype
.index
)
1881 first_error (_(type_error
));
1885 else if (lane
== -1)
1886 lane
= NEON_INTERLEAVE_LANES
;
1887 else if (lane
!= NEON_INTERLEAVE_LANES
)
1889 first_error (_(type_error
));
1894 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1896 /* No lane set by [x]. We must be interleaving structures. */
1898 lane
= NEON_INTERLEAVE_LANES
;
1901 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1902 || (count
> 1 && reg_incr
== -1))
1904 first_error (_("error parsing element/structure list"));
1908 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1910 first_error (_("expected }"));
1918 *eltype
= firsttype
.eltype
;
1923 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1926 /* Parse an explicit relocation suffix on an expression. This is
1927 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1928 arm_reloc_hsh contains no entries, so this function can only
1929 succeed if there is no () after the word. Returns -1 on error,
1930 BFD_RELOC_UNUSED if there wasn't any suffix. */
1932 parse_reloc (char **str
)
1934 struct reloc_entry
*r
;
1938 return BFD_RELOC_UNUSED
;
1943 while (*q
&& *q
!= ')' && *q
!= ',')
1948 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1955 /* Directives: register aliases. */
1957 static struct reg_entry
*
1958 insert_reg_alias (char *str
, int number
, int type
)
1960 struct reg_entry
*new;
1963 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1966 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1968 /* Only warn about a redefinition if it's not defined as the
1970 else if (new->number
!= number
|| new->type
!= type
)
1971 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1976 name
= xstrdup (str
);
1977 new = xmalloc (sizeof (struct reg_entry
));
1980 new->number
= number
;
1982 new->builtin
= FALSE
;
1985 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1992 insert_neon_reg_alias (char *str
, int number
, int type
,
1993 struct neon_typed_alias
*atype
)
1995 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1999 first_error (_("attempt to redefine typed alias"));
2005 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2006 *reg
->neon
= *atype
;
2010 /* Look for the .req directive. This is of the form:
2012 new_register_name .req existing_register_name
2014 If we find one, or if it looks sufficiently like one that we want to
2015 handle any error here, return TRUE. Otherwise return FALSE. */
2018 create_register_alias (char * newname
, char *p
)
2020 struct reg_entry
*old
;
2021 char *oldname
, *nbuf
;
2024 /* The input scrubber ensures that whitespace after the mnemonic is
2025 collapsed to single spaces. */
2027 if (strncmp (oldname
, " .req ", 6) != 0)
2031 if (*oldname
== '\0')
2034 old
= hash_find (arm_reg_hsh
, oldname
);
2037 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2041 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2042 the desired alias name, and p points to its end. If not, then
2043 the desired alias name is in the global original_case_string. */
2044 #ifdef TC_CASE_SENSITIVE
2047 newname
= original_case_string
;
2048 nlen
= strlen (newname
);
2051 nbuf
= alloca (nlen
+ 1);
2052 memcpy (nbuf
, newname
, nlen
);
2055 /* Create aliases under the new name as stated; an all-lowercase
2056 version of the new name; and an all-uppercase version of the new
2058 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2060 for (p
= nbuf
; *p
; p
++)
2063 if (strncmp (nbuf
, newname
, nlen
))
2065 /* If this attempt to create an additional alias fails, do not bother
2066 trying to create the all-lower case alias. We will fail and issue
2067 a second, duplicate error message. This situation arises when the
2068 programmer does something like:
2071 The second .req creates the "Foo" alias but then fails to create
2072 the artificial FOO alias because it has already been created by the
2074 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2078 for (p
= nbuf
; *p
; p
++)
2081 if (strncmp (nbuf
, newname
, nlen
))
2082 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2088 /* Create a Neon typed/indexed register alias using directives, e.g.:
2093 These typed registers can be used instead of the types specified after the
2094 Neon mnemonic, so long as all operands given have types. Types can also be
2095 specified directly, e.g.:
2096 vadd d0.s32, d1.s32, d2.s32 */
2099 create_neon_reg_alias (char *newname
, char *p
)
2101 enum arm_reg_type basetype
;
2102 struct reg_entry
*basereg
;
2103 struct reg_entry mybasereg
;
2104 struct neon_type ntype
;
2105 struct neon_typed_alias typeinfo
;
2106 char *namebuf
, *nameend
;
2109 typeinfo
.defined
= 0;
2110 typeinfo
.eltype
.type
= NT_invtype
;
2111 typeinfo
.eltype
.size
= -1;
2112 typeinfo
.index
= -1;
2116 if (strncmp (p
, " .dn ", 5) == 0)
2117 basetype
= REG_TYPE_VFD
;
2118 else if (strncmp (p
, " .qn ", 5) == 0)
2119 basetype
= REG_TYPE_NQ
;
2128 basereg
= arm_reg_parse_multi (&p
);
2130 if (basereg
&& basereg
->type
!= basetype
)
2132 as_bad (_("bad type for register"));
2136 if (basereg
== NULL
)
2139 /* Try parsing as an integer. */
2140 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2141 if (exp
.X_op
!= O_constant
)
2143 as_bad (_("expression must be constant"));
2146 basereg
= &mybasereg
;
2147 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2153 typeinfo
= *basereg
->neon
;
2155 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2157 /* We got a type. */
2158 if (typeinfo
.defined
& NTA_HASTYPE
)
2160 as_bad (_("can't redefine the type of a register alias"));
2164 typeinfo
.defined
|= NTA_HASTYPE
;
2165 if (ntype
.elems
!= 1)
2167 as_bad (_("you must specify a single type only"));
2170 typeinfo
.eltype
= ntype
.el
[0];
2173 if (skip_past_char (&p
, '[') == SUCCESS
)
2176 /* We got a scalar index. */
2178 if (typeinfo
.defined
& NTA_HASINDEX
)
2180 as_bad (_("can't redefine the index of a scalar alias"));
2184 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2186 if (exp
.X_op
!= O_constant
)
2188 as_bad (_("scalar index must be constant"));
2192 typeinfo
.defined
|= NTA_HASINDEX
;
2193 typeinfo
.index
= exp
.X_add_number
;
2195 if (skip_past_char (&p
, ']') == FAIL
)
2197 as_bad (_("expecting ]"));
2202 namelen
= nameend
- newname
;
2203 namebuf
= alloca (namelen
+ 1);
2204 strncpy (namebuf
, newname
, namelen
);
2205 namebuf
[namelen
] = '\0';
2207 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2208 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2210 /* Insert name in all uppercase. */
2211 for (p
= namebuf
; *p
; p
++)
2214 if (strncmp (namebuf
, newname
, namelen
))
2215 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2216 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2218 /* Insert name in all lowercase. */
2219 for (p
= namebuf
; *p
; p
++)
2222 if (strncmp (namebuf
, newname
, namelen
))
2223 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2224 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2229 /* Should never be called, as .req goes between the alias and the
2230 register name, not at the beginning of the line. */
2232 s_req (int a ATTRIBUTE_UNUSED
)
2234 as_bad (_("invalid syntax for .req directive"));
2238 s_dn (int a ATTRIBUTE_UNUSED
)
2240 as_bad (_("invalid syntax for .dn directive"));
2244 s_qn (int a ATTRIBUTE_UNUSED
)
2246 as_bad (_("invalid syntax for .qn directive"));
2249 /* The .unreq directive deletes an alias which was previously defined
2250 by .req. For example:
2256 s_unreq (int a ATTRIBUTE_UNUSED
)
2261 name
= input_line_pointer
;
2263 while (*input_line_pointer
!= 0
2264 && *input_line_pointer
!= ' '
2265 && *input_line_pointer
!= '\n')
2266 ++input_line_pointer
;
2268 saved_char
= *input_line_pointer
;
2269 *input_line_pointer
= 0;
2272 as_bad (_("invalid syntax for .unreq directive"));
2275 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2278 as_bad (_("unknown register alias '%s'"), name
);
2279 else if (reg
->builtin
)
2280 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2287 hash_delete (arm_reg_hsh
, name
);
2288 free ((char *) reg
->name
);
2293 /* Also locate the all upper case and all lower case versions.
2294 Do not complain if we cannot find one or the other as it
2295 was probably deleted above. */
2297 nbuf
= strdup (name
);
2298 for (p
= nbuf
; *p
; p
++)
2300 reg
= hash_find (arm_reg_hsh
, nbuf
);
2303 hash_delete (arm_reg_hsh
, nbuf
);
2304 free ((char *) reg
->name
);
2310 for (p
= nbuf
; *p
; p
++)
2312 reg
= hash_find (arm_reg_hsh
, nbuf
);
2315 hash_delete (arm_reg_hsh
, nbuf
);
2316 free ((char *) reg
->name
);
2326 *input_line_pointer
= saved_char
;
2327 demand_empty_rest_of_line ();
2330 /* Directives: Instruction set selection. */
2333 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2334 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2335 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2336 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2338 static enum mstate mapstate
= MAP_UNDEFINED
;
2341 mapping_state (enum mstate state
)
2344 const char * symname
;
2347 if (mapstate
== state
)
2348 /* The mapping symbol has already been emitted.
2349 There is nothing else to do. */
2358 type
= BSF_NO_FLAGS
;
2362 type
= BSF_NO_FLAGS
;
2366 type
= BSF_NO_FLAGS
;
2374 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2376 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2377 symbol_table_insert (symbolP
);
2378 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2383 THUMB_SET_FUNC (symbolP
, 0);
2384 ARM_SET_THUMB (symbolP
, 0);
2385 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2389 THUMB_SET_FUNC (symbolP
, 1);
2390 ARM_SET_THUMB (symbolP
, 1);
2391 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2400 #define mapping_state(x) /* nothing */
2403 /* Find the real, Thumb encoded start of a Thumb function. */
2406 find_real_start (symbolS
* symbolP
)
2409 const char * name
= S_GET_NAME (symbolP
);
2410 symbolS
* new_target
;
2412 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2413 #define STUB_NAME ".real_start_of"
2418 /* The compiler may generate BL instructions to local labels because
2419 it needs to perform a branch to a far away location. These labels
2420 do not have a corresponding ".real_start_of" label. We check
2421 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2422 the ".real_start_of" convention for nonlocal branches. */
2423 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2426 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2427 new_target
= symbol_find (real_start
);
2429 if (new_target
== NULL
)
2431 as_warn (_("Failed to find real start of function: %s\n"), name
);
2432 new_target
= symbolP
;
2439 opcode_select (int width
)
2446 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2447 as_bad (_("selected processor does not support THUMB opcodes"));
2450 /* No need to force the alignment, since we will have been
2451 coming from ARM mode, which is word-aligned. */
2452 record_alignment (now_seg
, 1);
2454 mapping_state (MAP_THUMB
);
2460 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2461 as_bad (_("selected processor does not support ARM opcodes"));
2466 frag_align (2, 0, 0);
2468 record_alignment (now_seg
, 1);
2470 mapping_state (MAP_ARM
);
2474 as_bad (_("invalid instruction size selected (%d)"), width
);
2479 s_arm (int ignore ATTRIBUTE_UNUSED
)
2482 demand_empty_rest_of_line ();
2486 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2489 demand_empty_rest_of_line ();
2493 s_code (int unused ATTRIBUTE_UNUSED
)
2497 temp
= get_absolute_expression ();
2502 opcode_select (temp
);
2506 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2511 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2513 /* If we are not already in thumb mode go into it, EVEN if
2514 the target processor does not support thumb instructions.
2515 This is used by gcc/config/arm/lib1funcs.asm for example
2516 to compile interworking support functions even if the
2517 target processor should not support interworking. */
2521 record_alignment (now_seg
, 1);
2524 demand_empty_rest_of_line ();
2528 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2532 /* The following label is the name/address of the start of a Thumb function.
2533 We need to know this for the interworking support. */
2534 label_is_thumb_function_name
= TRUE
;
2537 /* Perform a .set directive, but also mark the alias as
2538 being a thumb function. */
2541 s_thumb_set (int equiv
)
2543 /* XXX the following is a duplicate of the code for s_set() in read.c
2544 We cannot just call that code as we need to get at the symbol that
2551 /* Especial apologies for the random logic:
2552 This just grew, and could be parsed much more simply!
2554 name
= input_line_pointer
;
2555 delim
= get_symbol_end ();
2556 end_name
= input_line_pointer
;
2559 if (*input_line_pointer
!= ',')
2562 as_bad (_("expected comma after name \"%s\""), name
);
2564 ignore_rest_of_line ();
2568 input_line_pointer
++;
2571 if (name
[0] == '.' && name
[1] == '\0')
2573 /* XXX - this should not happen to .thumb_set. */
2577 if ((symbolP
= symbol_find (name
)) == NULL
2578 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2581 /* When doing symbol listings, play games with dummy fragments living
2582 outside the normal fragment chain to record the file and line info
2584 if (listing
& LISTING_SYMBOLS
)
2586 extern struct list_info_struct
* listing_tail
;
2587 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2589 memset (dummy_frag
, 0, sizeof (fragS
));
2590 dummy_frag
->fr_type
= rs_fill
;
2591 dummy_frag
->line
= listing_tail
;
2592 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2593 dummy_frag
->fr_symbol
= symbolP
;
2597 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2600 /* "set" symbols are local unless otherwise specified. */
2601 SF_SET_LOCAL (symbolP
);
2602 #endif /* OBJ_COFF */
2603 } /* Make a new symbol. */
2605 symbol_table_insert (symbolP
);
2610 && S_IS_DEFINED (symbolP
)
2611 && S_GET_SEGMENT (symbolP
) != reg_section
)
2612 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2614 pseudo_set (symbolP
);
2616 demand_empty_rest_of_line ();
2618 /* XXX Now we come to the Thumb specific bit of code. */
2620 THUMB_SET_FUNC (symbolP
, 1);
2621 ARM_SET_THUMB (symbolP
, 1);
2622 #if defined OBJ_ELF || defined OBJ_COFF
2623 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2627 /* Directives: Mode selection. */
2629 /* .syntax [unified|divided] - choose the new unified syntax
2630 (same for Arm and Thumb encoding, modulo slight differences in what
2631 can be represented) or the old divergent syntax for each mode. */
2633 s_syntax (int unused ATTRIBUTE_UNUSED
)
2637 name
= input_line_pointer
;
2638 delim
= get_symbol_end ();
2640 if (!strcasecmp (name
, "unified"))
2641 unified_syntax
= TRUE
;
2642 else if (!strcasecmp (name
, "divided"))
2643 unified_syntax
= FALSE
;
2646 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2649 *input_line_pointer
= delim
;
2650 demand_empty_rest_of_line ();
2653 /* Directives: sectioning and alignment. */
2655 /* Same as s_align_ptwo but align 0 => align 2. */
2658 s_align (int unused ATTRIBUTE_UNUSED
)
2663 long max_alignment
= 15;
2665 temp
= get_absolute_expression ();
2666 if (temp
> max_alignment
)
2667 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2670 as_bad (_("alignment negative. 0 assumed."));
2674 if (*input_line_pointer
== ',')
2676 input_line_pointer
++;
2677 temp_fill
= get_absolute_expression ();
2689 /* Only make a frag if we HAVE to. */
2690 if (temp
&& !need_pass_2
)
2692 if (!fill_p
&& subseg_text_p (now_seg
))
2693 frag_align_code (temp
, 0);
2695 frag_align (temp
, (int) temp_fill
, 0);
2697 demand_empty_rest_of_line ();
2699 record_alignment (now_seg
, temp
);
2703 s_bss (int ignore ATTRIBUTE_UNUSED
)
2705 /* We don't support putting frags in the BSS segment, we fake it by
2706 marking in_bss, then looking at s_skip for clues. */
2707 subseg_set (bss_section
, 0);
2708 demand_empty_rest_of_line ();
2709 mapping_state (MAP_DATA
);
2713 s_even (int ignore ATTRIBUTE_UNUSED
)
2715 /* Never make frag if expect extra pass. */
2717 frag_align (1, 0, 0);
2719 record_alignment (now_seg
, 1);
2721 demand_empty_rest_of_line ();
2724 /* Directives: Literal pools. */
2726 static literal_pool
*
2727 find_literal_pool (void)
2729 literal_pool
* pool
;
2731 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2733 if (pool
->section
== now_seg
2734 && pool
->sub_section
== now_subseg
)
2741 static literal_pool
*
2742 find_or_make_literal_pool (void)
2744 /* Next literal pool ID number. */
2745 static unsigned int latest_pool_num
= 1;
2746 literal_pool
* pool
;
2748 pool
= find_literal_pool ();
2752 /* Create a new pool. */
2753 pool
= xmalloc (sizeof (* pool
));
2757 pool
->next_free_entry
= 0;
2758 pool
->section
= now_seg
;
2759 pool
->sub_section
= now_subseg
;
2760 pool
->next
= list_of_pools
;
2761 pool
->symbol
= NULL
;
2763 /* Add it to the list. */
2764 list_of_pools
= pool
;
2767 /* New pools, and emptied pools, will have a NULL symbol. */
2768 if (pool
->symbol
== NULL
)
2770 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2771 (valueT
) 0, &zero_address_frag
);
2772 pool
->id
= latest_pool_num
++;
2779 /* Add the literal in the global 'inst'
2780 structure to the relevant literal pool. */
2783 add_to_lit_pool (void)
2785 literal_pool
* pool
;
2788 pool
= find_or_make_literal_pool ();
2790 /* Check if this literal value is already in the pool. */
2791 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2793 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2794 && (inst
.reloc
.exp
.X_op
== O_constant
)
2795 && (pool
->literals
[entry
].X_add_number
2796 == inst
.reloc
.exp
.X_add_number
)
2797 && (pool
->literals
[entry
].X_unsigned
2798 == inst
.reloc
.exp
.X_unsigned
))
2801 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2802 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2803 && (pool
->literals
[entry
].X_add_number
2804 == inst
.reloc
.exp
.X_add_number
)
2805 && (pool
->literals
[entry
].X_add_symbol
2806 == inst
.reloc
.exp
.X_add_symbol
)
2807 && (pool
->literals
[entry
].X_op_symbol
2808 == inst
.reloc
.exp
.X_op_symbol
))
2812 /* Do we need to create a new entry? */
2813 if (entry
== pool
->next_free_entry
)
2815 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2817 inst
.error
= _("literal pool overflow");
2821 pool
->literals
[entry
] = inst
.reloc
.exp
;
2822 pool
->next_free_entry
+= 1;
2825 inst
.reloc
.exp
.X_op
= O_symbol
;
2826 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2827 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2832 /* Can't use symbol_new here, so have to create a symbol and then at
2833 a later date assign it a value. Thats what these functions do. */
2836 symbol_locate (symbolS
* symbolP
,
2837 const char * name
, /* It is copied, the caller can modify. */
2838 segT segment
, /* Segment identifier (SEG_<something>). */
2839 valueT valu
, /* Symbol value. */
2840 fragS
* frag
) /* Associated fragment. */
2842 unsigned int name_length
;
2843 char * preserved_copy_of_name
;
2845 name_length
= strlen (name
) + 1; /* +1 for \0. */
2846 obstack_grow (¬es
, name
, name_length
);
2847 preserved_copy_of_name
= obstack_finish (¬es
);
2849 #ifdef tc_canonicalize_symbol_name
2850 preserved_copy_of_name
=
2851 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2854 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2856 S_SET_SEGMENT (symbolP
, segment
);
2857 S_SET_VALUE (symbolP
, valu
);
2858 symbol_clear_list_pointers (symbolP
);
2860 symbol_set_frag (symbolP
, frag
);
2862 /* Link to end of symbol chain. */
2864 extern int symbol_table_frozen
;
2866 if (symbol_table_frozen
)
2870 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2872 obj_symbol_new_hook (symbolP
);
2874 #ifdef tc_symbol_new_hook
2875 tc_symbol_new_hook (symbolP
);
2879 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2880 #endif /* DEBUG_SYMS */
2885 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2888 literal_pool
* pool
;
2891 pool
= find_literal_pool ();
2893 || pool
->symbol
== NULL
2894 || pool
->next_free_entry
== 0)
2897 mapping_state (MAP_DATA
);
2899 /* Align pool as you have word accesses.
2900 Only make a frag if we have to. */
2902 frag_align (2, 0, 0);
2904 record_alignment (now_seg
, 2);
2906 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2908 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2909 (valueT
) frag_now_fix (), frag_now
);
2910 symbol_table_insert (pool
->symbol
);
2912 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2914 #if defined OBJ_COFF || defined OBJ_ELF
2915 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2918 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2919 /* First output the expression in the instruction to the pool. */
2920 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2922 /* Mark the pool as empty. */
2923 pool
->next_free_entry
= 0;
2924 pool
->symbol
= NULL
;
2928 /* Forward declarations for functions below, in the MD interface
2930 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2931 static valueT
create_unwind_entry (int);
2932 static void start_unwind_section (const segT
, int);
2933 static void add_unwind_opcode (valueT
, int);
2934 static void flush_pending_unwind (void);
2936 /* Directives: Data. */
2939 s_arm_elf_cons (int nbytes
)
2943 #ifdef md_flush_pending_output
2944 md_flush_pending_output ();
2947 if (is_it_end_of_statement ())
2949 demand_empty_rest_of_line ();
2953 #ifdef md_cons_align
2954 md_cons_align (nbytes
);
2957 mapping_state (MAP_DATA
);
2961 char *base
= input_line_pointer
;
2965 if (exp
.X_op
!= O_symbol
)
2966 emit_expr (&exp
, (unsigned int) nbytes
);
2969 char *before_reloc
= input_line_pointer
;
2970 reloc
= parse_reloc (&input_line_pointer
);
2973 as_bad (_("unrecognized relocation suffix"));
2974 ignore_rest_of_line ();
2977 else if (reloc
== BFD_RELOC_UNUSED
)
2978 emit_expr (&exp
, (unsigned int) nbytes
);
2981 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2982 int size
= bfd_get_reloc_size (howto
);
2984 if (reloc
== BFD_RELOC_ARM_PLT32
)
2986 as_bad (_("(plt) is only valid on branch targets"));
2987 reloc
= BFD_RELOC_UNUSED
;
2992 as_bad (_("%s relocations do not fit in %d bytes"),
2993 howto
->name
, nbytes
);
2996 /* We've parsed an expression stopping at O_symbol.
2997 But there may be more expression left now that we
2998 have parsed the relocation marker. Parse it again.
2999 XXX Surely there is a cleaner way to do this. */
3000 char *p
= input_line_pointer
;
3002 char *save_buf
= alloca (input_line_pointer
- base
);
3003 memcpy (save_buf
, base
, input_line_pointer
- base
);
3004 memmove (base
+ (input_line_pointer
- before_reloc
),
3005 base
, before_reloc
- base
);
3007 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3009 memcpy (base
, save_buf
, p
- base
);
3011 offset
= nbytes
- size
;
3012 p
= frag_more ((int) nbytes
);
3013 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3014 size
, &exp
, 0, reloc
);
3019 while (*input_line_pointer
++ == ',');
3021 /* Put terminator back into stream. */
3022 input_line_pointer
--;
3023 demand_empty_rest_of_line ();
3027 /* Parse a .rel31 directive. */
3030 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3037 if (*input_line_pointer
== '1')
3038 highbit
= 0x80000000;
3039 else if (*input_line_pointer
!= '0')
3040 as_bad (_("expected 0 or 1"));
3042 input_line_pointer
++;
3043 if (*input_line_pointer
!= ',')
3044 as_bad (_("missing comma"));
3045 input_line_pointer
++;
3047 #ifdef md_flush_pending_output
3048 md_flush_pending_output ();
3051 #ifdef md_cons_align
3055 mapping_state (MAP_DATA
);
3060 md_number_to_chars (p
, highbit
, 4);
3061 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3062 BFD_RELOC_ARM_PREL31
);
3064 demand_empty_rest_of_line ();
3067 /* Directives: AEABI stack-unwind tables. */
3069 /* Parse an unwind_fnstart directive. Simply records the current location. */
3072 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3074 demand_empty_rest_of_line ();
3075 /* Mark the start of the function. */
3076 unwind
.proc_start
= expr_build_dot ();
3078 /* Reset the rest of the unwind info. */
3079 unwind
.opcode_count
= 0;
3080 unwind
.table_entry
= NULL
;
3081 unwind
.personality_routine
= NULL
;
3082 unwind
.personality_index
= -1;
3083 unwind
.frame_size
= 0;
3084 unwind
.fp_offset
= 0;
3087 unwind
.sp_restored
= 0;
3091 /* Parse a handlerdata directive. Creates the exception handling table entry
3092 for the function. */
3095 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3097 demand_empty_rest_of_line ();
3098 if (unwind
.table_entry
)
3099 as_bad (_("duplicate .handlerdata directive"));
3101 create_unwind_entry (1);
3104 /* Parse an unwind_fnend directive. Generates the index table entry. */
3107 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3113 demand_empty_rest_of_line ();
3115 /* Add eh table entry. */
3116 if (unwind
.table_entry
== NULL
)
3117 val
= create_unwind_entry (0);
3121 /* Add index table entry. This is two words. */
3122 start_unwind_section (unwind
.saved_seg
, 1);
3123 frag_align (2, 0, 0);
3124 record_alignment (now_seg
, 2);
3126 ptr
= frag_more (8);
3127 where
= frag_now_fix () - 8;
3129 /* Self relative offset of the function start. */
3130 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3131 BFD_RELOC_ARM_PREL31
);
3133 /* Indicate dependency on EHABI-defined personality routines to the
3134 linker, if it hasn't been done already. */
3135 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3136 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3138 static const char *const name
[] =
3140 "__aeabi_unwind_cpp_pr0",
3141 "__aeabi_unwind_cpp_pr1",
3142 "__aeabi_unwind_cpp_pr2"
3144 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3145 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3146 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3147 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3148 = marked_pr_dependency
;
3152 /* Inline exception table entry. */
3153 md_number_to_chars (ptr
+ 4, val
, 4);
3155 /* Self relative offset of the table entry. */
3156 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3157 BFD_RELOC_ARM_PREL31
);
3159 /* Restore the original section. */
3160 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3164 /* Parse an unwind_cantunwind directive. */
3167 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3169 demand_empty_rest_of_line ();
3170 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3171 as_bad (_("personality routine specified for cantunwind frame"));
3173 unwind
.personality_index
= -2;
3177 /* Parse a personalityindex directive. */
3180 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3184 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3185 as_bad (_("duplicate .personalityindex directive"));
3189 if (exp
.X_op
!= O_constant
3190 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3192 as_bad (_("bad personality routine number"));
3193 ignore_rest_of_line ();
3197 unwind
.personality_index
= exp
.X_add_number
;
3199 demand_empty_rest_of_line ();
3203 /* Parse a personality directive. */
3206 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3210 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3211 as_bad (_("duplicate .personality directive"));
3213 name
= input_line_pointer
;
3214 c
= get_symbol_end ();
3215 p
= input_line_pointer
;
3216 unwind
.personality_routine
= symbol_find_or_make (name
);
3218 demand_empty_rest_of_line ();
3222 /* Parse a directive saving core registers. */
3225 s_arm_unwind_save_core (void)
3231 range
= parse_reg_list (&input_line_pointer
);
3234 as_bad (_("expected register list"));
3235 ignore_rest_of_line ();
3239 demand_empty_rest_of_line ();
3241 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3242 into .unwind_save {..., sp...}. We aren't bothered about the value of
3243 ip because it is clobbered by calls. */
3244 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3245 && (range
& 0x3000) == 0x1000)
3247 unwind
.opcode_count
--;
3248 unwind
.sp_restored
= 0;
3249 range
= (range
| 0x2000) & ~0x1000;
3250 unwind
.pending_offset
= 0;
3256 /* See if we can use the short opcodes. These pop a block of up to 8
3257 registers starting with r4, plus maybe r14. */
3258 for (n
= 0; n
< 8; n
++)
3260 /* Break at the first non-saved register. */
3261 if ((range
& (1 << (n
+ 4))) == 0)
3264 /* See if there are any other bits set. */
3265 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3267 /* Use the long form. */
3268 op
= 0x8000 | ((range
>> 4) & 0xfff);
3269 add_unwind_opcode (op
, 2);
3273 /* Use the short form. */
3275 op
= 0xa8; /* Pop r14. */
3277 op
= 0xa0; /* Do not pop r14. */
3279 add_unwind_opcode (op
, 1);
3286 op
= 0xb100 | (range
& 0xf);
3287 add_unwind_opcode (op
, 2);
3290 /* Record the number of bytes pushed. */
3291 for (n
= 0; n
< 16; n
++)
3293 if (range
& (1 << n
))
3294 unwind
.frame_size
+= 4;
3299 /* Parse a directive saving FPA registers. */
3302 s_arm_unwind_save_fpa (int reg
)
3308 /* Get Number of registers to transfer. */
3309 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3312 exp
.X_op
= O_illegal
;
3314 if (exp
.X_op
!= O_constant
)
3316 as_bad (_("expected , <constant>"));
3317 ignore_rest_of_line ();
3321 num_regs
= exp
.X_add_number
;
3323 if (num_regs
< 1 || num_regs
> 4)
3325 as_bad (_("number of registers must be in the range [1:4]"));
3326 ignore_rest_of_line ();
3330 demand_empty_rest_of_line ();
3335 op
= 0xb4 | (num_regs
- 1);
3336 add_unwind_opcode (op
, 1);
3341 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3342 add_unwind_opcode (op
, 2);
3344 unwind
.frame_size
+= num_regs
* 12;
3348 /* Parse a directive saving VFP registers for ARMv6 and above. */
3351 s_arm_unwind_save_vfp_armv6 (void)
3356 int num_vfpv3_regs
= 0;
3357 int num_regs_below_16
;
3359 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3362 as_bad (_("expected register list"));
3363 ignore_rest_of_line ();
3367 demand_empty_rest_of_line ();
3369 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3370 than FSTMX/FLDMX-style ones). */
3372 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3374 num_vfpv3_regs
= count
;
3375 else if (start
+ count
> 16)
3376 num_vfpv3_regs
= start
+ count
- 16;
3378 if (num_vfpv3_regs
> 0)
3380 int start_offset
= start
> 16 ? start
- 16 : 0;
3381 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3382 add_unwind_opcode (op
, 2);
3385 /* Generate opcode for registers numbered in the range 0 .. 15. */
3386 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3387 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3388 if (num_regs_below_16
> 0)
3390 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3391 add_unwind_opcode (op
, 2);
3394 unwind
.frame_size
+= count
* 8;
3398 /* Parse a directive saving VFP registers for pre-ARMv6. */
3401 s_arm_unwind_save_vfp (void)
3407 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3410 as_bad (_("expected register list"));
3411 ignore_rest_of_line ();
3415 demand_empty_rest_of_line ();
3420 op
= 0xb8 | (count
- 1);
3421 add_unwind_opcode (op
, 1);
3426 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3427 add_unwind_opcode (op
, 2);
3429 unwind
.frame_size
+= count
* 8 + 4;
3433 /* Parse a directive saving iWMMXt data registers. */
3436 s_arm_unwind_save_mmxwr (void)
3444 if (*input_line_pointer
== '{')
3445 input_line_pointer
++;
3449 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3453 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3458 as_tsktsk (_("register list not in ascending order"));
3461 if (*input_line_pointer
== '-')
3463 input_line_pointer
++;
3464 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3467 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3470 else if (reg
>= hi_reg
)
3472 as_bad (_("bad register range"));
3475 for (; reg
< hi_reg
; reg
++)
3479 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3481 if (*input_line_pointer
== '}')
3482 input_line_pointer
++;
3484 demand_empty_rest_of_line ();
3486 /* Generate any deferred opcodes because we're going to be looking at
3488 flush_pending_unwind ();
3490 for (i
= 0; i
< 16; i
++)
3492 if (mask
& (1 << i
))
3493 unwind
.frame_size
+= 8;
3496 /* Attempt to combine with a previous opcode. We do this because gcc
3497 likes to output separate unwind directives for a single block of
3499 if (unwind
.opcode_count
> 0)
3501 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3502 if ((i
& 0xf8) == 0xc0)
3505 /* Only merge if the blocks are contiguous. */
3508 if ((mask
& 0xfe00) == (1 << 9))
3510 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3511 unwind
.opcode_count
--;
3514 else if (i
== 6 && unwind
.opcode_count
>= 2)
3516 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3520 op
= 0xffff << (reg
- 1);
3522 && ((mask
& op
) == (1u << (reg
- 1))))
3524 op
= (1 << (reg
+ i
+ 1)) - 1;
3525 op
&= ~((1 << reg
) - 1);
3527 unwind
.opcode_count
-= 2;
3534 /* We want to generate opcodes in the order the registers have been
3535 saved, ie. descending order. */
3536 for (reg
= 15; reg
>= -1; reg
--)
3538 /* Save registers in blocks. */
3540 || !(mask
& (1 << reg
)))
3542 /* We found an unsaved reg. Generate opcodes to save the
3549 op
= 0xc0 | (hi_reg
- 10);
3550 add_unwind_opcode (op
, 1);
3555 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3556 add_unwind_opcode (op
, 2);
3565 ignore_rest_of_line ();
3569 s_arm_unwind_save_mmxwcg (void)
3576 if (*input_line_pointer
== '{')
3577 input_line_pointer
++;
3581 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3585 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3591 as_tsktsk (_("register list not in ascending order"));
3594 if (*input_line_pointer
== '-')
3596 input_line_pointer
++;
3597 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3600 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3603 else if (reg
>= hi_reg
)
3605 as_bad (_("bad register range"));
3608 for (; reg
< hi_reg
; reg
++)
3612 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3614 if (*input_line_pointer
== '}')
3615 input_line_pointer
++;
3617 demand_empty_rest_of_line ();
3619 /* Generate any deferred opcodes because we're going to be looking at
3621 flush_pending_unwind ();
3623 for (reg
= 0; reg
< 16; reg
++)
3625 if (mask
& (1 << reg
))
3626 unwind
.frame_size
+= 4;
3629 add_unwind_opcode (op
, 2);
3632 ignore_rest_of_line ();
3636 /* Parse an unwind_save directive.
3637 If the argument is non-zero, this is a .vsave directive. */
3640 s_arm_unwind_save (int arch_v6
)
3643 struct reg_entry
*reg
;
3644 bfd_boolean had_brace
= FALSE
;
3646 /* Figure out what sort of save we have. */
3647 peek
= input_line_pointer
;
3655 reg
= arm_reg_parse_multi (&peek
);
3659 as_bad (_("register expected"));
3660 ignore_rest_of_line ();
3669 as_bad (_("FPA .unwind_save does not take a register list"));
3670 ignore_rest_of_line ();
3673 s_arm_unwind_save_fpa (reg
->number
);
3676 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3679 s_arm_unwind_save_vfp_armv6 ();
3681 s_arm_unwind_save_vfp ();
3683 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3684 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3687 as_bad (_(".unwind_save does not support this kind of register"));
3688 ignore_rest_of_line ();
3693 /* Parse an unwind_movsp directive. */
3696 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3702 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3705 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3706 ignore_rest_of_line ();
3710 /* Optional constant. */
3711 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3713 if (immediate_for_directive (&offset
) == FAIL
)
3719 demand_empty_rest_of_line ();
3721 if (reg
== REG_SP
|| reg
== REG_PC
)
3723 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3727 if (unwind
.fp_reg
!= REG_SP
)
3728 as_bad (_("unexpected .unwind_movsp directive"));
3730 /* Generate opcode to restore the value. */
3732 add_unwind_opcode (op
, 1);
3734 /* Record the information for later. */
3735 unwind
.fp_reg
= reg
;
3736 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3737 unwind
.sp_restored
= 1;
3740 /* Parse an unwind_pad directive. */
3743 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3747 if (immediate_for_directive (&offset
) == FAIL
)
3752 as_bad (_("stack increment must be multiple of 4"));
3753 ignore_rest_of_line ();
3757 /* Don't generate any opcodes, just record the details for later. */
3758 unwind
.frame_size
+= offset
;
3759 unwind
.pending_offset
+= offset
;
3761 demand_empty_rest_of_line ();
3764 /* Parse an unwind_setfp directive. */
3767 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3773 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3774 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3777 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3779 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3781 as_bad (_("expected <reg>, <reg>"));
3782 ignore_rest_of_line ();
3786 /* Optional constant. */
3787 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3789 if (immediate_for_directive (&offset
) == FAIL
)
3795 demand_empty_rest_of_line ();
3797 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3799 as_bad (_("register must be either sp or set by a previous"
3800 "unwind_movsp directive"));
3804 /* Don't generate any opcodes, just record the information for later. */
3805 unwind
.fp_reg
= fp_reg
;
3808 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3810 unwind
.fp_offset
-= offset
;
3813 /* Parse an unwind_raw directive. */
3816 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3819 /* This is an arbitrary limit. */
3820 unsigned char op
[16];
3824 if (exp
.X_op
== O_constant
3825 && skip_past_comma (&input_line_pointer
) != FAIL
)
3827 unwind
.frame_size
+= exp
.X_add_number
;
3831 exp
.X_op
= O_illegal
;
3833 if (exp
.X_op
!= O_constant
)
3835 as_bad (_("expected <offset>, <opcode>"));
3836 ignore_rest_of_line ();
3842 /* Parse the opcode. */
3847 as_bad (_("unwind opcode too long"));
3848 ignore_rest_of_line ();
3850 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3852 as_bad (_("invalid unwind opcode"));
3853 ignore_rest_of_line ();
3856 op
[count
++] = exp
.X_add_number
;
3858 /* Parse the next byte. */
3859 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3865 /* Add the opcode bytes in reverse order. */
3867 add_unwind_opcode (op
[count
], 1);
3869 demand_empty_rest_of_line ();
3873 /* Parse a .eabi_attribute directive. */
3876 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3878 s_vendor_attribute (OBJ_ATTR_PROC
);
3880 #endif /* OBJ_ELF */
3882 static void s_arm_arch (int);
3883 static void s_arm_object_arch (int);
3884 static void s_arm_cpu (int);
3885 static void s_arm_fpu (int);
3890 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3897 if (exp
.X_op
== O_symbol
)
3898 exp
.X_op
= O_secrel
;
3900 emit_expr (&exp
, 4);
3902 while (*input_line_pointer
++ == ',');
3904 input_line_pointer
--;
3905 demand_empty_rest_of_line ();
3909 /* This table describes all the machine specific pseudo-ops the assembler
3910 has to support. The fields are:
3911 pseudo-op name without dot
3912 function to call to execute this pseudo-op
3913 Integer arg to pass to the function. */
3915 const pseudo_typeS md_pseudo_table
[] =
3917 /* Never called because '.req' does not start a line. */
3918 { "req", s_req
, 0 },
3919 /* Following two are likewise never called. */
3922 { "unreq", s_unreq
, 0 },
3923 { "bss", s_bss
, 0 },
3924 { "align", s_align
, 0 },
3925 { "arm", s_arm
, 0 },
3926 { "thumb", s_thumb
, 0 },
3927 { "code", s_code
, 0 },
3928 { "force_thumb", s_force_thumb
, 0 },
3929 { "thumb_func", s_thumb_func
, 0 },
3930 { "thumb_set", s_thumb_set
, 0 },
3931 { "even", s_even
, 0 },
3932 { "ltorg", s_ltorg
, 0 },
3933 { "pool", s_ltorg
, 0 },
3934 { "syntax", s_syntax
, 0 },
3935 { "cpu", s_arm_cpu
, 0 },
3936 { "arch", s_arm_arch
, 0 },
3937 { "object_arch", s_arm_object_arch
, 0 },
3938 { "fpu", s_arm_fpu
, 0 },
3940 { "word", s_arm_elf_cons
, 4 },
3941 { "long", s_arm_elf_cons
, 4 },
3942 { "rel31", s_arm_rel31
, 0 },
3943 { "fnstart", s_arm_unwind_fnstart
, 0 },
3944 { "fnend", s_arm_unwind_fnend
, 0 },
3945 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3946 { "personality", s_arm_unwind_personality
, 0 },
3947 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3948 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3949 { "save", s_arm_unwind_save
, 0 },
3950 { "vsave", s_arm_unwind_save
, 1 },
3951 { "movsp", s_arm_unwind_movsp
, 0 },
3952 { "pad", s_arm_unwind_pad
, 0 },
3953 { "setfp", s_arm_unwind_setfp
, 0 },
3954 { "unwind_raw", s_arm_unwind_raw
, 0 },
3955 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3959 /* These are used for dwarf. */
3963 /* These are used for dwarf2. */
3964 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3965 { "loc", dwarf2_directive_loc
, 0 },
3966 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3968 { "extend", float_cons
, 'x' },
3969 { "ldouble", float_cons
, 'x' },
3970 { "packed", float_cons
, 'p' },
3972 {"secrel32", pe_directive_secrel
, 0},
3977 /* Parser functions used exclusively in instruction operands. */
3979 /* Generic immediate-value read function for use in insn parsing.
3980 STR points to the beginning of the immediate (the leading #);
3981 VAL receives the value; if the value is outside [MIN, MAX]
3982 issue an error. PREFIX_OPT is true if the immediate prefix is
3986 parse_immediate (char **str
, int *val
, int min
, int max
,
3987 bfd_boolean prefix_opt
)
3990 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3991 if (exp
.X_op
!= O_constant
)
3993 inst
.error
= _("constant expression required");
3997 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
3999 inst
.error
= _("immediate value out of range");
4003 *val
= exp
.X_add_number
;
4007 /* Less-generic immediate-value read function with the possibility of loading a
4008 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4009 instructions. Puts the result directly in inst.operands[i]. */
4012 parse_big_immediate (char **str
, int i
)
4017 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4019 if (exp
.X_op
== O_constant
)
4021 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4022 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4023 O_constant. We have to be careful not to break compilation for
4024 32-bit X_add_number, though. */
4025 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4027 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4028 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4029 inst
.operands
[i
].regisimm
= 1;
4032 else if (exp
.X_op
== O_big
4033 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4034 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4036 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4037 /* Bignums have their least significant bits in
4038 generic_bignum[0]. Make sure we put 32 bits in imm and
4039 32 bits in reg, in a (hopefully) portable way. */
4040 assert (parts
!= 0);
4041 inst
.operands
[i
].imm
= 0;
4042 for (j
= 0; j
< parts
; j
++, idx
++)
4043 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4044 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4045 inst
.operands
[i
].reg
= 0;
4046 for (j
= 0; j
< parts
; j
++, idx
++)
4047 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4048 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4049 inst
.operands
[i
].regisimm
= 1;
4059 /* Returns the pseudo-register number of an FPA immediate constant,
4060 or FAIL if there isn't a valid constant here. */
4063 parse_fpa_immediate (char ** str
)
4065 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4071 /* First try and match exact strings, this is to guarantee
4072 that some formats will work even for cross assembly. */
4074 for (i
= 0; fp_const
[i
]; i
++)
4076 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4080 *str
+= strlen (fp_const
[i
]);
4081 if (is_end_of_line
[(unsigned char) **str
])
4087 /* Just because we didn't get a match doesn't mean that the constant
4088 isn't valid, just that it is in a format that we don't
4089 automatically recognize. Try parsing it with the standard
4090 expression routines. */
4092 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4094 /* Look for a raw floating point number. */
4095 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4096 && is_end_of_line
[(unsigned char) *save_in
])
4098 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4100 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4102 if (words
[j
] != fp_values
[i
][j
])
4106 if (j
== MAX_LITTLENUMS
)
4114 /* Try and parse a more complex expression, this will probably fail
4115 unless the code uses a floating point prefix (eg "0f"). */
4116 save_in
= input_line_pointer
;
4117 input_line_pointer
= *str
;
4118 if (expression (&exp
) == absolute_section
4119 && exp
.X_op
== O_big
4120 && exp
.X_add_number
< 0)
4122 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4124 if (gen_to_words (words
, 5, (long) 15) == 0)
4126 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4128 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4130 if (words
[j
] != fp_values
[i
][j
])
4134 if (j
== MAX_LITTLENUMS
)
4136 *str
= input_line_pointer
;
4137 input_line_pointer
= save_in
;
4144 *str
= input_line_pointer
;
4145 input_line_pointer
= save_in
;
4146 inst
.error
= _("invalid FPA immediate expression");
4150 /* Returns 1 if a number has "quarter-precision" float format
4151 0baBbbbbbc defgh000 00000000 00000000. */
4154 is_quarter_float (unsigned imm
)
4156 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4157 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4160 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4161 0baBbbbbbc defgh000 00000000 00000000.
4162 The zero and minus-zero cases need special handling, since they can't be
4163 encoded in the "quarter-precision" float format, but can nonetheless be
4164 loaded as integer constants. */
4167 parse_qfloat_immediate (char **ccp
, int *immed
)
4171 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4172 int found_fpchar
= 0;
4174 skip_past_char (&str
, '#');
4176 /* We must not accidentally parse an integer as a floating-point number. Make
4177 sure that the value we parse is not an integer by checking for special
4178 characters '.' or 'e'.
4179 FIXME: This is a horrible hack, but doing better is tricky because type
4180 information isn't in a very usable state at parse time. */
4182 skip_whitespace (fpnum
);
4184 if (strncmp (fpnum
, "0x", 2) == 0)
4188 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4189 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4199 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4201 unsigned fpword
= 0;
4204 /* Our FP word must be 32 bits (single-precision FP). */
4205 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4207 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4211 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4224 /* Shift operands. */
4227 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4230 struct asm_shift_name
4233 enum shift_kind kind
;
4236 /* Third argument to parse_shift. */
4237 enum parse_shift_mode
4239 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4240 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4241 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4242 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4243 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4246 /* Parse a <shift> specifier on an ARM data processing instruction.
4247 This has three forms:
4249 (LSL|LSR|ASL|ASR|ROR) Rs
4250 (LSL|LSR|ASL|ASR|ROR) #imm
4253 Note that ASL is assimilated to LSL in the instruction encoding, and
4254 RRX to ROR #0 (which cannot be written as such). */
4257 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4259 const struct asm_shift_name
*shift_name
;
4260 enum shift_kind shift
;
4265 for (p
= *str
; ISALPHA (*p
); p
++)
4270 inst
.error
= _("shift expression expected");
4274 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4276 if (shift_name
== NULL
)
4278 inst
.error
= _("shift expression expected");
4282 shift
= shift_name
->kind
;
4286 case NO_SHIFT_RESTRICT
:
4287 case SHIFT_IMMEDIATE
: break;
4289 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4290 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4292 inst
.error
= _("'LSL' or 'ASR' required");
4297 case SHIFT_LSL_IMMEDIATE
:
4298 if (shift
!= SHIFT_LSL
)
4300 inst
.error
= _("'LSL' required");
4305 case SHIFT_ASR_IMMEDIATE
:
4306 if (shift
!= SHIFT_ASR
)
4308 inst
.error
= _("'ASR' required");
4316 if (shift
!= SHIFT_RRX
)
4318 /* Whitespace can appear here if the next thing is a bare digit. */
4319 skip_whitespace (p
);
4321 if (mode
== NO_SHIFT_RESTRICT
4322 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4324 inst
.operands
[i
].imm
= reg
;
4325 inst
.operands
[i
].immisreg
= 1;
4327 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4330 inst
.operands
[i
].shift_kind
= shift
;
4331 inst
.operands
[i
].shifted
= 1;
4336 /* Parse a <shifter_operand> for an ARM data processing instruction:
4339 #<immediate>, <rotate>
4343 where <shift> is defined by parse_shift above, and <rotate> is a
4344 multiple of 2 between 0 and 30. Validation of immediate operands
4345 is deferred to md_apply_fix. */
4348 parse_shifter_operand (char **str
, int i
)
4353 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4355 inst
.operands
[i
].reg
= value
;
4356 inst
.operands
[i
].isreg
= 1;
4358 /* parse_shift will override this if appropriate */
4359 inst
.reloc
.exp
.X_op
= O_constant
;
4360 inst
.reloc
.exp
.X_add_number
= 0;
4362 if (skip_past_comma (str
) == FAIL
)
4365 /* Shift operation on register. */
4366 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4369 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4372 if (skip_past_comma (str
) == SUCCESS
)
4374 /* #x, y -- ie explicit rotation by Y. */
4375 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4378 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4380 inst
.error
= _("constant expression expected");
4384 value
= expr
.X_add_number
;
4385 if (value
< 0 || value
> 30 || value
% 2 != 0)
4387 inst
.error
= _("invalid rotation");
4390 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4392 inst
.error
= _("invalid constant");
4396 /* Convert to decoded value. md_apply_fix will put it back. */
4397 inst
.reloc
.exp
.X_add_number
4398 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4399 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4402 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4403 inst
.reloc
.pc_rel
= 0;
4407 /* Group relocation information. Each entry in the table contains the
4408 textual name of the relocation as may appear in assembler source
4409 and must end with a colon.
4410 Along with this textual name are the relocation codes to be used if
4411 the corresponding instruction is an ALU instruction (ADD or SUB only),
4412 an LDR, an LDRS, or an LDC. */
4414 struct group_reloc_table_entry
4425 /* Varieties of non-ALU group relocation. */
4432 static struct group_reloc_table_entry group_reloc_table
[] =
4433 { /* Program counter relative: */
4435 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4440 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4441 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4442 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4443 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4445 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4450 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4451 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4452 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4453 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4455 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4456 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4457 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4458 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4459 /* Section base relative */
4461 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4466 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4467 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4468 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4469 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4471 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4476 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4477 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4478 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4479 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4481 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4482 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4483 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4484 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4486 /* Given the address of a pointer pointing to the textual name of a group
4487 relocation as may appear in assembler source, attempt to find its details
4488 in group_reloc_table. The pointer will be updated to the character after
4489 the trailing colon. On failure, FAIL will be returned; SUCCESS
4490 otherwise. On success, *entry will be updated to point at the relevant
4491 group_reloc_table entry. */
4494 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4497 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4499 int length
= strlen (group_reloc_table
[i
].name
);
4501 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4502 && (*str
)[length
] == ':')
4504 *out
= &group_reloc_table
[i
];
4505 *str
+= (length
+ 1);
4513 /* Parse a <shifter_operand> for an ARM data processing instruction
4514 (as for parse_shifter_operand) where group relocations are allowed:
4517 #<immediate>, <rotate>
4518 #:<group_reloc>:<expression>
4522 where <group_reloc> is one of the strings defined in group_reloc_table.
4523 The hashes are optional.
4525 Everything else is as for parse_shifter_operand. */
4527 static parse_operand_result
4528 parse_shifter_operand_group_reloc (char **str
, int i
)
4530 /* Determine if we have the sequence of characters #: or just :
4531 coming next. If we do, then we check for a group relocation.
4532 If we don't, punt the whole lot to parse_shifter_operand. */
4534 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4535 || (*str
)[0] == ':')
4537 struct group_reloc_table_entry
*entry
;
4539 if ((*str
)[0] == '#')
4544 /* Try to parse a group relocation. Anything else is an error. */
4545 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4547 inst
.error
= _("unknown group relocation");
4548 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4551 /* We now have the group relocation table entry corresponding to
4552 the name in the assembler source. Next, we parse the expression. */
4553 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4554 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4556 /* Record the relocation type (always the ALU variant here). */
4557 inst
.reloc
.type
= entry
->alu_code
;
4558 assert (inst
.reloc
.type
!= 0);
4560 return PARSE_OPERAND_SUCCESS
;
4563 return parse_shifter_operand (str
, i
) == SUCCESS
4564 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4566 /* Never reached. */
4569 /* Parse all forms of an ARM address expression. Information is written
4570 to inst.operands[i] and/or inst.reloc.
4572 Preindexed addressing (.preind=1):
4574 [Rn, #offset] .reg=Rn .reloc.exp=offset
4575 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4576 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4577 .shift_kind=shift .reloc.exp=shift_imm
4579 These three may have a trailing ! which causes .writeback to be set also.
4581 Postindexed addressing (.postind=1, .writeback=1):
4583 [Rn], #offset .reg=Rn .reloc.exp=offset
4584 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4585 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4586 .shift_kind=shift .reloc.exp=shift_imm
4588 Unindexed addressing (.preind=0, .postind=0):
4590 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4594 [Rn]{!} shorthand for [Rn,#0]{!}
4595 =immediate .isreg=0 .reloc.exp=immediate
4596 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4598 It is the caller's responsibility to check for addressing modes not
4599 supported by the instruction, and to set inst.reloc.type. */
4601 static parse_operand_result
4602 parse_address_main (char **str
, int i
, int group_relocations
,
4603 group_reloc_type group_type
)
4608 if (skip_past_char (&p
, '[') == FAIL
)
4610 if (skip_past_char (&p
, '=') == FAIL
)
4612 /* bare address - translate to PC-relative offset */
4613 inst
.reloc
.pc_rel
= 1;
4614 inst
.operands
[i
].reg
= REG_PC
;
4615 inst
.operands
[i
].isreg
= 1;
4616 inst
.operands
[i
].preind
= 1;
4618 /* else a load-constant pseudo op, no special treatment needed here */
4620 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4621 return PARSE_OPERAND_FAIL
;
4624 return PARSE_OPERAND_SUCCESS
;
4627 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4629 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4630 return PARSE_OPERAND_FAIL
;
4632 inst
.operands
[i
].reg
= reg
;
4633 inst
.operands
[i
].isreg
= 1;
4635 if (skip_past_comma (&p
) == SUCCESS
)
4637 inst
.operands
[i
].preind
= 1;
4640 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4642 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4644 inst
.operands
[i
].imm
= reg
;
4645 inst
.operands
[i
].immisreg
= 1;
4647 if (skip_past_comma (&p
) == SUCCESS
)
4648 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4649 return PARSE_OPERAND_FAIL
;
4651 else if (skip_past_char (&p
, ':') == SUCCESS
)
4653 /* FIXME: '@' should be used here, but it's filtered out by generic
4654 code before we get to see it here. This may be subject to
4657 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4658 if (exp
.X_op
!= O_constant
)
4660 inst
.error
= _("alignment must be constant");
4661 return PARSE_OPERAND_FAIL
;
4663 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4664 inst
.operands
[i
].immisalign
= 1;
4665 /* Alignments are not pre-indexes. */
4666 inst
.operands
[i
].preind
= 0;
4670 if (inst
.operands
[i
].negative
)
4672 inst
.operands
[i
].negative
= 0;
4676 if (group_relocations
4677 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4679 struct group_reloc_table_entry
*entry
;
4681 /* Skip over the #: or : sequence. */
4687 /* Try to parse a group relocation. Anything else is an
4689 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4691 inst
.error
= _("unknown group relocation");
4692 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4695 /* We now have the group relocation table entry corresponding to
4696 the name in the assembler source. Next, we parse the
4698 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4699 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4701 /* Record the relocation type. */
4705 inst
.reloc
.type
= entry
->ldr_code
;
4709 inst
.reloc
.type
= entry
->ldrs_code
;
4713 inst
.reloc
.type
= entry
->ldc_code
;
4720 if (inst
.reloc
.type
== 0)
4722 inst
.error
= _("this group relocation is not allowed on this instruction");
4723 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4727 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4728 return PARSE_OPERAND_FAIL
;
4732 if (skip_past_char (&p
, ']') == FAIL
)
4734 inst
.error
= _("']' expected");
4735 return PARSE_OPERAND_FAIL
;
4738 if (skip_past_char (&p
, '!') == SUCCESS
)
4739 inst
.operands
[i
].writeback
= 1;
4741 else if (skip_past_comma (&p
) == SUCCESS
)
4743 if (skip_past_char (&p
, '{') == SUCCESS
)
4745 /* [Rn], {expr} - unindexed, with option */
4746 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4747 0, 255, TRUE
) == FAIL
)
4748 return PARSE_OPERAND_FAIL
;
4750 if (skip_past_char (&p
, '}') == FAIL
)
4752 inst
.error
= _("'}' expected at end of 'option' field");
4753 return PARSE_OPERAND_FAIL
;
4755 if (inst
.operands
[i
].preind
)
4757 inst
.error
= _("cannot combine index with option");
4758 return PARSE_OPERAND_FAIL
;
4761 return PARSE_OPERAND_SUCCESS
;
4765 inst
.operands
[i
].postind
= 1;
4766 inst
.operands
[i
].writeback
= 1;
4768 if (inst
.operands
[i
].preind
)
4770 inst
.error
= _("cannot combine pre- and post-indexing");
4771 return PARSE_OPERAND_FAIL
;
4775 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4777 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4779 /* We might be using the immediate for alignment already. If we
4780 are, OR the register number into the low-order bits. */
4781 if (inst
.operands
[i
].immisalign
)
4782 inst
.operands
[i
].imm
|= reg
;
4784 inst
.operands
[i
].imm
= reg
;
4785 inst
.operands
[i
].immisreg
= 1;
4787 if (skip_past_comma (&p
) == SUCCESS
)
4788 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4789 return PARSE_OPERAND_FAIL
;
4793 if (inst
.operands
[i
].negative
)
4795 inst
.operands
[i
].negative
= 0;
4798 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4799 return PARSE_OPERAND_FAIL
;
4804 /* If at this point neither .preind nor .postind is set, we have a
4805 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4806 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4808 inst
.operands
[i
].preind
= 1;
4809 inst
.reloc
.exp
.X_op
= O_constant
;
4810 inst
.reloc
.exp
.X_add_number
= 0;
4813 return PARSE_OPERAND_SUCCESS
;
4817 parse_address (char **str
, int i
)
4819 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4823 static parse_operand_result
4824 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4826 return parse_address_main (str
, i
, 1, type
);
4829 /* Parse an operand for a MOVW or MOVT instruction. */
4831 parse_half (char **str
)
4836 skip_past_char (&p
, '#');
4837 if (strncasecmp (p
, ":lower16:", 9) == 0)
4838 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4839 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4840 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4842 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4845 skip_whitespace (p
);
4848 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4851 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4853 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4855 inst
.error
= _("constant expression expected");
4858 if (inst
.reloc
.exp
.X_add_number
< 0
4859 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4861 inst
.error
= _("immediate value out of range");
4869 /* Miscellaneous. */
4871 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4872 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4874 parse_psr (char **str
)
4877 unsigned long psr_field
;
4878 const struct asm_psr
*psr
;
4881 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4882 feature for ease of use and backwards compatibility. */
4884 if (strncasecmp (p
, "SPSR", 4) == 0)
4885 psr_field
= SPSR_BIT
;
4886 else if (strncasecmp (p
, "CPSR", 4) == 0)
4893 while (ISALNUM (*p
) || *p
== '_');
4895 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4906 /* A suffix follows. */
4912 while (ISALNUM (*p
) || *p
== '_');
4914 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4918 psr_field
|= psr
->field
;
4923 goto error
; /* Garbage after "[CS]PSR". */
4925 psr_field
|= (PSR_c
| PSR_f
);
4931 inst
.error
= _("flag for {c}psr instruction expected");
4935 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4936 value suitable for splatting into the AIF field of the instruction. */
4939 parse_cps_flags (char **str
)
4948 case '\0': case ',':
4951 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4952 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4953 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4956 inst
.error
= _("unrecognized CPS flag");
4961 if (saw_a_flag
== 0)
4963 inst
.error
= _("missing CPS flags");
4971 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4972 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4975 parse_endian_specifier (char **str
)
4980 if (strncasecmp (s
, "BE", 2))
4982 else if (strncasecmp (s
, "LE", 2))
4986 inst
.error
= _("valid endian specifiers are be or le");
4990 if (ISALNUM (s
[2]) || s
[2] == '_')
4992 inst
.error
= _("valid endian specifiers are be or le");
4997 return little_endian
;
5000 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5001 value suitable for poking into the rotate field of an sxt or sxta
5002 instruction, or FAIL on error. */
5005 parse_ror (char **str
)
5010 if (strncasecmp (s
, "ROR", 3) == 0)
5014 inst
.error
= _("missing rotation field after comma");
5018 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5023 case 0: *str
= s
; return 0x0;
5024 case 8: *str
= s
; return 0x1;
5025 case 16: *str
= s
; return 0x2;
5026 case 24: *str
= s
; return 0x3;
5029 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5034 /* Parse a conditional code (from conds[] below). The value returned is in the
5035 range 0 .. 14, or FAIL. */
5037 parse_cond (char **str
)
5040 const struct asm_cond
*c
;
5043 while (ISALPHA (*q
))
5046 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5049 inst
.error
= _("condition required");
5057 /* Parse an option for a barrier instruction. Returns the encoding for the
5060 parse_barrier (char **str
)
5063 const struct asm_barrier_opt
*o
;
5066 while (ISALPHA (*q
))
5069 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5077 /* Parse the operands of a table branch instruction. Similar to a memory
5080 parse_tb (char **str
)
5085 if (skip_past_char (&p
, '[') == FAIL
)
5087 inst
.error
= _("'[' expected");
5091 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5093 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5096 inst
.operands
[0].reg
= reg
;
5098 if (skip_past_comma (&p
) == FAIL
)
5100 inst
.error
= _("',' expected");
5104 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5106 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5109 inst
.operands
[0].imm
= reg
;
5111 if (skip_past_comma (&p
) == SUCCESS
)
5113 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5115 if (inst
.reloc
.exp
.X_add_number
!= 1)
5117 inst
.error
= _("invalid shift");
5120 inst
.operands
[0].shifted
= 1;
5123 if (skip_past_char (&p
, ']') == FAIL
)
5125 inst
.error
= _("']' expected");
5132 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5133 information on the types the operands can take and how they are encoded.
5134 Up to four operands may be read; this function handles setting the
5135 ".present" field for each read operand itself.
5136 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5137 else returns FAIL. */
5140 parse_neon_mov (char **str
, int *which_operand
)
5142 int i
= *which_operand
, val
;
5143 enum arm_reg_type rtype
;
5145 struct neon_type_el optype
;
5147 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5149 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5150 inst
.operands
[i
].reg
= val
;
5151 inst
.operands
[i
].isscalar
= 1;
5152 inst
.operands
[i
].vectype
= optype
;
5153 inst
.operands
[i
++].present
= 1;
5155 if (skip_past_comma (&ptr
) == FAIL
)
5158 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5161 inst
.operands
[i
].reg
= val
;
5162 inst
.operands
[i
].isreg
= 1;
5163 inst
.operands
[i
].present
= 1;
5165 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5168 /* Cases 0, 1, 2, 3, 5 (D only). */
5169 if (skip_past_comma (&ptr
) == FAIL
)
5172 inst
.operands
[i
].reg
= val
;
5173 inst
.operands
[i
].isreg
= 1;
5174 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5175 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5176 inst
.operands
[i
].isvec
= 1;
5177 inst
.operands
[i
].vectype
= optype
;
5178 inst
.operands
[i
++].present
= 1;
5180 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5182 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5183 Case 13: VMOV <Sd>, <Rm> */
5184 inst
.operands
[i
].reg
= val
;
5185 inst
.operands
[i
].isreg
= 1;
5186 inst
.operands
[i
].present
= 1;
5188 if (rtype
== REG_TYPE_NQ
)
5190 first_error (_("can't use Neon quad register here"));
5193 else if (rtype
!= REG_TYPE_VFS
)
5196 if (skip_past_comma (&ptr
) == FAIL
)
5198 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5200 inst
.operands
[i
].reg
= val
;
5201 inst
.operands
[i
].isreg
= 1;
5202 inst
.operands
[i
].present
= 1;
5205 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5206 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5207 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5208 Case 10: VMOV.F32 <Sd>, #<imm>
5209 Case 11: VMOV.F64 <Dd>, #<imm> */
5210 inst
.operands
[i
].immisfloat
= 1;
5211 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5212 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5213 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5215 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5218 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5219 Case 1: VMOV<c><q> <Dd>, <Dm>
5220 Case 8: VMOV.F32 <Sd>, <Sm>
5221 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5223 inst
.operands
[i
].reg
= val
;
5224 inst
.operands
[i
].isreg
= 1;
5225 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5226 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5227 inst
.operands
[i
].isvec
= 1;
5228 inst
.operands
[i
].vectype
= optype
;
5229 inst
.operands
[i
].present
= 1;
5231 if (skip_past_comma (&ptr
) == SUCCESS
)
5236 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5239 inst
.operands
[i
].reg
= val
;
5240 inst
.operands
[i
].isreg
= 1;
5241 inst
.operands
[i
++].present
= 1;
5243 if (skip_past_comma (&ptr
) == FAIL
)
5246 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5249 inst
.operands
[i
].reg
= val
;
5250 inst
.operands
[i
].isreg
= 1;
5251 inst
.operands
[i
++].present
= 1;
5256 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5260 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5263 inst
.operands
[i
].reg
= val
;
5264 inst
.operands
[i
].isreg
= 1;
5265 inst
.operands
[i
++].present
= 1;
5267 if (skip_past_comma (&ptr
) == FAIL
)
5270 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5272 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5273 inst
.operands
[i
].reg
= val
;
5274 inst
.operands
[i
].isscalar
= 1;
5275 inst
.operands
[i
].present
= 1;
5276 inst
.operands
[i
].vectype
= optype
;
5278 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5280 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5281 inst
.operands
[i
].reg
= val
;
5282 inst
.operands
[i
].isreg
= 1;
5283 inst
.operands
[i
++].present
= 1;
5285 if (skip_past_comma (&ptr
) == FAIL
)
5288 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5291 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5295 inst
.operands
[i
].reg
= val
;
5296 inst
.operands
[i
].isreg
= 1;
5297 inst
.operands
[i
].isvec
= 1;
5298 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5299 inst
.operands
[i
].vectype
= optype
;
5300 inst
.operands
[i
].present
= 1;
5302 if (rtype
== REG_TYPE_VFS
)
5306 if (skip_past_comma (&ptr
) == FAIL
)
5308 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5311 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5314 inst
.operands
[i
].reg
= val
;
5315 inst
.operands
[i
].isreg
= 1;
5316 inst
.operands
[i
].isvec
= 1;
5317 inst
.operands
[i
].issingle
= 1;
5318 inst
.operands
[i
].vectype
= optype
;
5319 inst
.operands
[i
].present
= 1;
5322 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5326 inst
.operands
[i
].reg
= val
;
5327 inst
.operands
[i
].isreg
= 1;
5328 inst
.operands
[i
].isvec
= 1;
5329 inst
.operands
[i
].issingle
= 1;
5330 inst
.operands
[i
].vectype
= optype
;
5331 inst
.operands
[i
++].present
= 1;
5336 first_error (_("parse error"));
5340 /* Successfully parsed the operands. Update args. */
5346 first_error (_("expected comma"));
5350 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5354 /* Matcher codes for parse_operands. */
5355 enum operand_parse_code
5357 OP_stop
, /* end of line */
5359 OP_RR
, /* ARM register */
5360 OP_RRnpc
, /* ARM register, not r15 */
5361 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5362 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5363 OP_RCP
, /* Coprocessor number */
5364 OP_RCN
, /* Coprocessor register */
5365 OP_RF
, /* FPA register */
5366 OP_RVS
, /* VFP single precision register */
5367 OP_RVD
, /* VFP double precision register (0..15) */
5368 OP_RND
, /* Neon double precision register (0..31) */
5369 OP_RNQ
, /* Neon quad precision register */
5370 OP_RVSD
, /* VFP single or double precision register */
5371 OP_RNDQ
, /* Neon double or quad precision register */
5372 OP_RNSDQ
, /* Neon single, double or quad precision register */
5373 OP_RNSC
, /* Neon scalar D[X] */
5374 OP_RVC
, /* VFP control register */
5375 OP_RMF
, /* Maverick F register */
5376 OP_RMD
, /* Maverick D register */
5377 OP_RMFX
, /* Maverick FX register */
5378 OP_RMDX
, /* Maverick DX register */
5379 OP_RMAX
, /* Maverick AX register */
5380 OP_RMDS
, /* Maverick DSPSC register */
5381 OP_RIWR
, /* iWMMXt wR register */
5382 OP_RIWC
, /* iWMMXt wC register */
5383 OP_RIWG
, /* iWMMXt wCG register */
5384 OP_RXA
, /* XScale accumulator register */
5386 OP_REGLST
, /* ARM register list */
5387 OP_VRSLST
, /* VFP single-precision register list */
5388 OP_VRDLST
, /* VFP double-precision register list */
5389 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5390 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5391 OP_NSTRLST
, /* Neon element/structure list */
5393 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5394 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5395 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5396 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5397 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5398 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5399 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5400 OP_VMOV
, /* Neon VMOV operands. */
5401 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5402 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5403 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5405 OP_I0
, /* immediate zero */
5406 OP_I7
, /* immediate value 0 .. 7 */
5407 OP_I15
, /* 0 .. 15 */
5408 OP_I16
, /* 1 .. 16 */
5409 OP_I16z
, /* 0 .. 16 */
5410 OP_I31
, /* 0 .. 31 */
5411 OP_I31w
, /* 0 .. 31, optional trailing ! */
5412 OP_I32
, /* 1 .. 32 */
5413 OP_I32z
, /* 0 .. 32 */
5414 OP_I63
, /* 0 .. 63 */
5415 OP_I63s
, /* -64 .. 63 */
5416 OP_I64
, /* 1 .. 64 */
5417 OP_I64z
, /* 0 .. 64 */
5418 OP_I255
, /* 0 .. 255 */
5420 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5421 OP_I7b
, /* 0 .. 7 */
5422 OP_I15b
, /* 0 .. 15 */
5423 OP_I31b
, /* 0 .. 31 */
5425 OP_SH
, /* shifter operand */
5426 OP_SHG
, /* shifter operand with possible group relocation */
5427 OP_ADDR
, /* Memory address expression (any mode) */
5428 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5429 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5430 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5431 OP_EXP
, /* arbitrary expression */
5432 OP_EXPi
, /* same, with optional immediate prefix */
5433 OP_EXPr
, /* same, with optional relocation suffix */
5434 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5436 OP_CPSF
, /* CPS flags */
5437 OP_ENDI
, /* Endianness specifier */
5438 OP_PSR
, /* CPSR/SPSR mask for msr */
5439 OP_COND
, /* conditional code */
5440 OP_TB
, /* Table branch. */
5442 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5443 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5445 OP_RRnpc_I0
, /* ARM register or literal 0 */
5446 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5447 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5448 OP_RF_IF
, /* FPA register or immediate */
5449 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5450 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5452 /* Optional operands. */
5453 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5454 OP_oI31b
, /* 0 .. 31 */
5455 OP_oI32b
, /* 1 .. 32 */
5456 OP_oIffffb
, /* 0 .. 65535 */
5457 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5459 OP_oRR
, /* ARM register */
5460 OP_oRRnpc
, /* ARM register, not the PC */
5461 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5462 OP_oRND
, /* Optional Neon double precision register */
5463 OP_oRNQ
, /* Optional Neon quad precision register */
5464 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5465 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5466 OP_oSHll
, /* LSL immediate */
5467 OP_oSHar
, /* ASR immediate */
5468 OP_oSHllar
, /* LSL or ASR immediate */
5469 OP_oROR
, /* ROR 0/8/16/24 */
5470 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5472 OP_FIRST_OPTIONAL
= OP_oI7b
5475 /* Generic instruction operand parser. This does no encoding and no
5476 semantic validation; it merely squirrels values away in the inst
5477 structure. Returns SUCCESS or FAIL depending on whether the
5478 specified grammar matched. */
5480 parse_operands (char *str
, const unsigned char *pattern
)
5482 unsigned const char *upat
= pattern
;
5483 char *backtrack_pos
= 0;
5484 const char *backtrack_error
= 0;
5485 int i
, val
, backtrack_index
= 0;
5486 enum arm_reg_type rtype
;
5487 parse_operand_result result
;
5489 #define po_char_or_fail(chr) do { \
5490 if (skip_past_char (&str, chr) == FAIL) \
5494 #define po_reg_or_fail(regtype) do { \
5495 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5496 &inst.operands[i].vectype); \
5499 first_error (_(reg_expected_msgs[regtype])); \
5502 inst.operands[i].reg = val; \
5503 inst.operands[i].isreg = 1; \
5504 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5505 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5506 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5507 || rtype == REG_TYPE_VFD \
5508 || rtype == REG_TYPE_NQ); \
5511 #define po_reg_or_goto(regtype, label) do { \
5512 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5513 &inst.operands[i].vectype); \
5517 inst.operands[i].reg = val; \
5518 inst.operands[i].isreg = 1; \
5519 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5520 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5521 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5522 || rtype == REG_TYPE_VFD \
5523 || rtype == REG_TYPE_NQ); \
5526 #define po_imm_or_fail(min, max, popt) do { \
5527 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5529 inst.operands[i].imm = val; \
5532 #define po_scalar_or_goto(elsz, label) do { \
5533 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5536 inst.operands[i].reg = val; \
5537 inst.operands[i].isscalar = 1; \
5540 #define po_misc_or_fail(expr) do { \
5545 #define po_misc_or_fail_no_backtrack(expr) do { \
5547 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5548 backtrack_pos = 0; \
5549 if (result != PARSE_OPERAND_SUCCESS) \
5553 skip_whitespace (str
);
5555 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5557 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5559 /* Remember where we are in case we need to backtrack. */
5560 assert (!backtrack_pos
);
5561 backtrack_pos
= str
;
5562 backtrack_error
= inst
.error
;
5563 backtrack_index
= i
;
5566 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5567 po_char_or_fail (',');
5575 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5576 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5577 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5578 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5579 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5580 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5582 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5584 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5586 /* Also accept generic coprocessor regs for unknown registers. */
5588 po_reg_or_fail (REG_TYPE_CN
);
5590 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5591 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5592 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5593 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5594 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5595 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5596 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5597 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5598 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5599 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5601 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5603 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5604 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5606 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5608 /* Neon scalar. Using an element size of 8 means that some invalid
5609 scalars are accepted here, so deal with those in later code. */
5610 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5612 /* WARNING: We can expand to two operands here. This has the potential
5613 to totally confuse the backtracking mechanism! It will be OK at
5614 least as long as we don't try to use optional args as well,
5618 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5619 inst
.operands
[i
].present
= 1;
5621 skip_past_comma (&str
);
5622 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5625 /* Optional register operand was omitted. Unfortunately, it's in
5626 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5627 here (this is a bit grotty). */
5628 inst
.operands
[i
] = inst
.operands
[i
-1];
5629 inst
.operands
[i
-1].present
= 0;
5632 /* There's a possibility of getting a 64-bit immediate here, so
5633 we need special handling. */
5634 if (parse_big_immediate (&str
, i
) == FAIL
)
5636 inst
.error
= _("immediate value is out of range");
5644 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5647 po_imm_or_fail (0, 0, TRUE
);
5652 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5657 po_scalar_or_goto (8, try_rr
);
5660 po_reg_or_fail (REG_TYPE_RN
);
5666 po_scalar_or_goto (8, try_nsdq
);
5669 po_reg_or_fail (REG_TYPE_NSDQ
);
5675 po_scalar_or_goto (8, try_ndq
);
5678 po_reg_or_fail (REG_TYPE_NDQ
);
5684 po_scalar_or_goto (8, try_vfd
);
5687 po_reg_or_fail (REG_TYPE_VFD
);
5692 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5693 not careful then bad things might happen. */
5694 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5699 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5702 /* There's a possibility of getting a 64-bit immediate here, so
5703 we need special handling. */
5704 if (parse_big_immediate (&str
, i
) == FAIL
)
5706 inst
.error
= _("immediate value is out of range");
5714 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5717 po_imm_or_fail (0, 63, TRUE
);
5722 po_char_or_fail ('[');
5723 po_reg_or_fail (REG_TYPE_RN
);
5724 po_char_or_fail (']');
5729 po_reg_or_fail (REG_TYPE_RN
);
5730 if (skip_past_char (&str
, '!') == SUCCESS
)
5731 inst
.operands
[i
].writeback
= 1;
5735 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5736 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5737 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5738 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5739 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5740 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5741 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5742 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5743 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5744 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5745 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5746 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5748 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5750 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5751 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5753 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5754 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5755 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5757 /* Immediate variants */
5759 po_char_or_fail ('{');
5760 po_imm_or_fail (0, 255, TRUE
);
5761 po_char_or_fail ('}');
5765 /* The expression parser chokes on a trailing !, so we have
5766 to find it first and zap it. */
5769 while (*s
&& *s
!= ',')
5774 inst
.operands
[i
].writeback
= 1;
5776 po_imm_or_fail (0, 31, TRUE
);
5784 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5789 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5794 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5796 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5798 val
= parse_reloc (&str
);
5801 inst
.error
= _("unrecognized relocation suffix");
5804 else if (val
!= BFD_RELOC_UNUSED
)
5806 inst
.operands
[i
].imm
= val
;
5807 inst
.operands
[i
].hasreloc
= 1;
5812 /* Operand for MOVW or MOVT. */
5814 po_misc_or_fail (parse_half (&str
));
5817 /* Register or expression */
5818 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5819 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5821 /* Register or immediate */
5822 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5823 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5825 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5827 if (!is_immediate_prefix (*str
))
5830 val
= parse_fpa_immediate (&str
);
5833 /* FPA immediates are encoded as registers 8-15.
5834 parse_fpa_immediate has already applied the offset. */
5835 inst
.operands
[i
].reg
= val
;
5836 inst
.operands
[i
].isreg
= 1;
5839 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5840 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5842 /* Two kinds of register */
5845 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5847 || (rege
->type
!= REG_TYPE_MMXWR
5848 && rege
->type
!= REG_TYPE_MMXWC
5849 && rege
->type
!= REG_TYPE_MMXWCG
))
5851 inst
.error
= _("iWMMXt data or control register expected");
5854 inst
.operands
[i
].reg
= rege
->number
;
5855 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5861 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5863 || (rege
->type
!= REG_TYPE_MMXWC
5864 && rege
->type
!= REG_TYPE_MMXWCG
))
5866 inst
.error
= _("iWMMXt control register expected");
5869 inst
.operands
[i
].reg
= rege
->number
;
5870 inst
.operands
[i
].isreg
= 1;
5875 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5876 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5877 case OP_oROR
: val
= parse_ror (&str
); break;
5878 case OP_PSR
: val
= parse_psr (&str
); break;
5879 case OP_COND
: val
= parse_cond (&str
); break;
5880 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5883 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5884 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5887 val
= parse_psr (&str
);
5891 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5894 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5896 if (strncasecmp (str
, "APSR_", 5) == 0)
5903 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5904 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5905 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5906 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5907 default: found
= 16;
5911 inst
.operands
[i
].isvec
= 1;
5918 po_misc_or_fail (parse_tb (&str
));
5921 /* Register lists */
5923 val
= parse_reg_list (&str
);
5926 inst
.operands
[1].writeback
= 1;
5932 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5936 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5940 /* Allow Q registers too. */
5941 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5946 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5948 inst
.operands
[i
].issingle
= 1;
5953 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5958 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5959 &inst
.operands
[i
].vectype
);
5962 /* Addressing modes */
5964 po_misc_or_fail (parse_address (&str
, i
));
5968 po_misc_or_fail_no_backtrack (
5969 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5973 po_misc_or_fail_no_backtrack (
5974 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5978 po_misc_or_fail_no_backtrack (
5979 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5983 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5987 po_misc_or_fail_no_backtrack (
5988 parse_shifter_operand_group_reloc (&str
, i
));
5992 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5996 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6000 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6004 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6007 /* Various value-based sanity checks and shared operations. We
6008 do not signal immediate failures for the register constraints;
6009 this allows a syntax error to take precedence. */
6018 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6019 inst
.error
= BAD_PC
;
6037 inst
.operands
[i
].imm
= val
;
6044 /* If we get here, this operand was successfully parsed. */
6045 inst
.operands
[i
].present
= 1;
6049 inst
.error
= BAD_ARGS
;
6054 /* The parse routine should already have set inst.error, but set a
6055 default here just in case. */
6057 inst
.error
= _("syntax error");
6061 /* Do not backtrack over a trailing optional argument that
6062 absorbed some text. We will only fail again, with the
6063 'garbage following instruction' error message, which is
6064 probably less helpful than the current one. */
6065 if (backtrack_index
== i
&& backtrack_pos
!= str
6066 && upat
[i
+1] == OP_stop
)
6069 inst
.error
= _("syntax error");
6073 /* Try again, skipping the optional argument at backtrack_pos. */
6074 str
= backtrack_pos
;
6075 inst
.error
= backtrack_error
;
6076 inst
.operands
[backtrack_index
].present
= 0;
6077 i
= backtrack_index
;
6081 /* Check that we have parsed all the arguments. */
6082 if (*str
!= '\0' && !inst
.error
)
6083 inst
.error
= _("garbage following instruction");
6085 return inst
.error
? FAIL
: SUCCESS
;
6088 #undef po_char_or_fail
6089 #undef po_reg_or_fail
6090 #undef po_reg_or_goto
6091 #undef po_imm_or_fail
6092 #undef po_scalar_or_fail
6094 /* Shorthand macro for instruction encoding functions issuing errors. */
6095 #define constraint(expr, err) do { \
6103 /* Functions for operand encoding. ARM, then Thumb. */
6105 #define rotate_left(v, n) (v << n | v >> (32 - n))
6107 /* If VAL can be encoded in the immediate field of an ARM instruction,
6108 return the encoded form. Otherwise, return FAIL. */
6111 encode_arm_immediate (unsigned int val
)
6115 for (i
= 0; i
< 32; i
+= 2)
6116 if ((a
= rotate_left (val
, i
)) <= 0xff)
6117 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6122 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6123 return the encoded form. Otherwise, return FAIL. */
6125 encode_thumb32_immediate (unsigned int val
)
6132 for (i
= 1; i
<= 24; i
++)
6135 if ((val
& ~(0xff << i
)) == 0)
6136 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6140 if (val
== ((a
<< 16) | a
))
6142 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6146 if (val
== ((a
<< 16) | a
))
6147 return 0x200 | (a
>> 8);
6151 /* Encode a VFP SP or DP register number into inst.instruction. */
6154 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6156 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6159 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6162 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6165 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6170 first_error (_("D register out of range for selected VFP version"));
6178 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6182 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6186 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6190 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6194 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6198 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6206 /* Encode a <shift> in an ARM-format instruction. The immediate,
6207 if any, is handled by md_apply_fix. */
6209 encode_arm_shift (int i
)
6211 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6212 inst
.instruction
|= SHIFT_ROR
<< 5;
6215 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6216 if (inst
.operands
[i
].immisreg
)
6218 inst
.instruction
|= SHIFT_BY_REG
;
6219 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6222 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6227 encode_arm_shifter_operand (int i
)
6229 if (inst
.operands
[i
].isreg
)
6231 inst
.instruction
|= inst
.operands
[i
].reg
;
6232 encode_arm_shift (i
);
6235 inst
.instruction
|= INST_IMMEDIATE
;
6238 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6240 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6242 assert (inst
.operands
[i
].isreg
);
6243 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6245 if (inst
.operands
[i
].preind
)
6249 inst
.error
= _("instruction does not accept preindexed addressing");
6252 inst
.instruction
|= PRE_INDEX
;
6253 if (inst
.operands
[i
].writeback
)
6254 inst
.instruction
|= WRITE_BACK
;
6257 else if (inst
.operands
[i
].postind
)
6259 assert (inst
.operands
[i
].writeback
);
6261 inst
.instruction
|= WRITE_BACK
;
6263 else /* unindexed - only for coprocessor */
6265 inst
.error
= _("instruction does not accept unindexed addressing");
6269 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6270 && (((inst
.instruction
& 0x000f0000) >> 16)
6271 == ((inst
.instruction
& 0x0000f000) >> 12)))
6272 as_warn ((inst
.instruction
& LOAD_BIT
)
6273 ? _("destination register same as write-back base")
6274 : _("source register same as write-back base"));
6277 /* inst.operands[i] was set up by parse_address. Encode it into an
6278 ARM-format mode 2 load or store instruction. If is_t is true,
6279 reject forms that cannot be used with a T instruction (i.e. not
6282 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6284 encode_arm_addr_mode_common (i
, is_t
);
6286 if (inst
.operands
[i
].immisreg
)
6288 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6289 inst
.instruction
|= inst
.operands
[i
].imm
;
6290 if (!inst
.operands
[i
].negative
)
6291 inst
.instruction
|= INDEX_UP
;
6292 if (inst
.operands
[i
].shifted
)
6294 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6295 inst
.instruction
|= SHIFT_ROR
<< 5;
6298 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6299 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6303 else /* immediate offset in inst.reloc */
6305 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6306 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6310 /* inst.operands[i] was set up by parse_address. Encode it into an
6311 ARM-format mode 3 load or store instruction. Reject forms that
6312 cannot be used with such instructions. If is_t is true, reject
6313 forms that cannot be used with a T instruction (i.e. not
6316 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6318 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6320 inst
.error
= _("instruction does not accept scaled register index");
6324 encode_arm_addr_mode_common (i
, is_t
);
6326 if (inst
.operands
[i
].immisreg
)
6328 inst
.instruction
|= inst
.operands
[i
].imm
;
6329 if (!inst
.operands
[i
].negative
)
6330 inst
.instruction
|= INDEX_UP
;
6332 else /* immediate offset in inst.reloc */
6334 inst
.instruction
|= HWOFFSET_IMM
;
6335 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6336 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6340 /* inst.operands[i] was set up by parse_address. Encode it into an
6341 ARM-format instruction. Reject all forms which cannot be encoded
6342 into a coprocessor load/store instruction. If wb_ok is false,
6343 reject use of writeback; if unind_ok is false, reject use of
6344 unindexed addressing. If reloc_override is not 0, use it instead
6345 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6346 (in which case it is preserved). */
6349 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6351 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6353 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6355 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6357 assert (!inst
.operands
[i
].writeback
);
6360 inst
.error
= _("instruction does not support unindexed addressing");
6363 inst
.instruction
|= inst
.operands
[i
].imm
;
6364 inst
.instruction
|= INDEX_UP
;
6368 if (inst
.operands
[i
].preind
)
6369 inst
.instruction
|= PRE_INDEX
;
6371 if (inst
.operands
[i
].writeback
)
6373 if (inst
.operands
[i
].reg
== REG_PC
)
6375 inst
.error
= _("pc may not be used with write-back");
6380 inst
.error
= _("instruction does not support writeback");
6383 inst
.instruction
|= WRITE_BACK
;
6387 inst
.reloc
.type
= reloc_override
;
6388 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6389 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6390 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6393 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6395 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6401 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6402 Determine whether it can be performed with a move instruction; if
6403 it can, convert inst.instruction to that move instruction and
6404 return 1; if it can't, convert inst.instruction to a literal-pool
6405 load and return 0. If this is not a valid thing to do in the
6406 current context, set inst.error and return 1.
6408 inst.operands[i] describes the destination register. */
6411 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6416 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6420 if ((inst
.instruction
& tbit
) == 0)
6422 inst
.error
= _("invalid pseudo operation");
6425 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6427 inst
.error
= _("constant expression expected");
6430 if (inst
.reloc
.exp
.X_op
== O_constant
)
6434 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6436 /* This can be done with a mov(1) instruction. */
6437 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6438 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6444 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6447 /* This can be done with a mov instruction. */
6448 inst
.instruction
&= LITERAL_MASK
;
6449 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6450 inst
.instruction
|= value
& 0xfff;
6454 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6457 /* This can be done with a mvn instruction. */
6458 inst
.instruction
&= LITERAL_MASK
;
6459 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6460 inst
.instruction
|= value
& 0xfff;
6466 if (add_to_lit_pool () == FAIL
)
6468 inst
.error
= _("literal pool insertion failed");
6471 inst
.operands
[1].reg
= REG_PC
;
6472 inst
.operands
[1].isreg
= 1;
6473 inst
.operands
[1].preind
= 1;
6474 inst
.reloc
.pc_rel
= 1;
6475 inst
.reloc
.type
= (thumb_p
6476 ? BFD_RELOC_ARM_THUMB_OFFSET
6478 ? BFD_RELOC_ARM_HWLITERAL
6479 : BFD_RELOC_ARM_LITERAL
));
6483 /* Functions for instruction encoding, sorted by sub-architecture.
6484 First some generics; their names are taken from the conventional
6485 bit positions for register arguments in ARM format instructions. */
6495 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6502 inst
.instruction
|= inst
.operands
[1].reg
;
6508 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6509 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6515 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6516 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6522 unsigned Rn
= inst
.operands
[2].reg
;
6523 /* Enforce restrictions on SWP instruction. */
6524 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6525 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6526 _("Rn must not overlap other operands"));
6527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6528 inst
.instruction
|= inst
.operands
[1].reg
;
6529 inst
.instruction
|= Rn
<< 16;
6535 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6536 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6537 inst
.instruction
|= inst
.operands
[2].reg
;
6543 inst
.instruction
|= inst
.operands
[0].reg
;
6544 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6545 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6551 inst
.instruction
|= inst
.operands
[0].imm
;
6557 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6558 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6561 /* ARM instructions, in alphabetical order by function name (except
6562 that wrapper functions appear immediately after the function they
6565 /* This is a pseudo-op of the form "adr rd, label" to be converted
6566 into a relative address of the form "add rd, pc, #label-.-8". */
6571 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6573 /* Frag hacking will turn this into a sub instruction if the offset turns
6574 out to be negative. */
6575 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6576 inst
.reloc
.pc_rel
= 1;
6577 inst
.reloc
.exp
.X_add_number
-= 8;
6580 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6581 into a relative address of the form:
6582 add rd, pc, #low(label-.-8)"
6583 add rd, rd, #high(label-.-8)" */
6588 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6590 /* Frag hacking will turn this into a sub instruction if the offset turns
6591 out to be negative. */
6592 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6593 inst
.reloc
.pc_rel
= 1;
6594 inst
.size
= INSN_SIZE
* 2;
6595 inst
.reloc
.exp
.X_add_number
-= 8;
6601 if (!inst
.operands
[1].present
)
6602 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6603 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6604 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6605 encode_arm_shifter_operand (2);
6611 if (inst
.operands
[0].present
)
6613 constraint ((inst
.instruction
& 0xf0) != 0x40
6614 && inst
.operands
[0].imm
!= 0xf,
6615 _("bad barrier type"));
6616 inst
.instruction
|= inst
.operands
[0].imm
;
6619 inst
.instruction
|= 0xf;
6625 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6626 constraint (msb
> 32, _("bit-field extends past end of register"));
6627 /* The instruction encoding stores the LSB and MSB,
6628 not the LSB and width. */
6629 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6630 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6631 inst
.instruction
|= (msb
- 1) << 16;
6639 /* #0 in second position is alternative syntax for bfc, which is
6640 the same instruction but with REG_PC in the Rm field. */
6641 if (!inst
.operands
[1].isreg
)
6642 inst
.operands
[1].reg
= REG_PC
;
6644 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6645 constraint (msb
> 32, _("bit-field extends past end of register"));
6646 /* The instruction encoding stores the LSB and MSB,
6647 not the LSB and width. */
6648 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6649 inst
.instruction
|= inst
.operands
[1].reg
;
6650 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6651 inst
.instruction
|= (msb
- 1) << 16;
6657 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6658 _("bit-field extends past end of register"));
6659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6660 inst
.instruction
|= inst
.operands
[1].reg
;
6661 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6662 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6665 /* ARM V5 breakpoint instruction (argument parse)
6666 BKPT <16 bit unsigned immediate>
6667 Instruction is not conditional.
6668 The bit pattern given in insns[] has the COND_ALWAYS condition,
6669 and it is an error if the caller tried to override that. */
6674 /* Top 12 of 16 bits to bits 19:8. */
6675 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6677 /* Bottom 4 of 16 bits to bits 3:0. */
6678 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6682 encode_branch (int default_reloc
)
6684 if (inst
.operands
[0].hasreloc
)
6686 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6687 _("the only suffix valid here is '(plt)'"));
6688 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6692 inst
.reloc
.type
= default_reloc
;
6694 inst
.reloc
.pc_rel
= 1;
6701 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6702 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6705 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6712 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6714 if (inst
.cond
== COND_ALWAYS
)
6715 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6717 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6721 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6724 /* ARM V5 branch-link-exchange instruction (argument parse)
6725 BLX <target_addr> ie BLX(1)
6726 BLX{<condition>} <Rm> ie BLX(2)
6727 Unfortunately, there are two different opcodes for this mnemonic.
6728 So, the insns[].value is not used, and the code here zaps values
6729 into inst.instruction.
6730 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6735 if (inst
.operands
[0].isreg
)
6737 /* Arg is a register; the opcode provided by insns[] is correct.
6738 It is not illegal to do "blx pc", just useless. */
6739 if (inst
.operands
[0].reg
== REG_PC
)
6740 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6742 inst
.instruction
|= inst
.operands
[0].reg
;
6746 /* Arg is an address; this instruction cannot be executed
6747 conditionally, and the opcode must be adjusted. */
6748 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6749 inst
.instruction
= 0xfa000000;
6751 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6752 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6755 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6762 if (inst
.operands
[0].reg
== REG_PC
)
6763 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6765 inst
.instruction
|= inst
.operands
[0].reg
;
6769 /* ARM v5TEJ. Jump to Jazelle code. */
6774 if (inst
.operands
[0].reg
== REG_PC
)
6775 as_tsktsk (_("use of r15 in bxj is not really useful"));
6777 inst
.instruction
|= inst
.operands
[0].reg
;
6780 /* Co-processor data operation:
6781 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6782 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6786 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6787 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6788 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6789 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6790 inst
.instruction
|= inst
.operands
[4].reg
;
6791 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6797 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6798 encode_arm_shifter_operand (1);
6801 /* Transfer between coprocessor and ARM registers.
6802 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6807 No special properties. */
6812 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6813 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6814 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6815 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6816 inst
.instruction
|= inst
.operands
[4].reg
;
6817 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6820 /* Transfer between coprocessor register and pair of ARM registers.
6821 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6826 Two XScale instructions are special cases of these:
6828 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6829 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6831 Result unpredictable if Rd or Rn is R15. */
6836 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6837 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6838 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6839 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6840 inst
.instruction
|= inst
.operands
[4].reg
;
6846 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6847 if (inst
.operands
[1].present
)
6849 inst
.instruction
|= CPSI_MMOD
;
6850 inst
.instruction
|= inst
.operands
[1].imm
;
6857 inst
.instruction
|= inst
.operands
[0].imm
;
6863 /* There is no IT instruction in ARM mode. We
6864 process it but do not generate code for it. */
6871 int base_reg
= inst
.operands
[0].reg
;
6872 int range
= inst
.operands
[1].imm
;
6874 inst
.instruction
|= base_reg
<< 16;
6875 inst
.instruction
|= range
;
6877 if (inst
.operands
[1].writeback
)
6878 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6880 if (inst
.operands
[0].writeback
)
6882 inst
.instruction
|= WRITE_BACK
;
6883 /* Check for unpredictable uses of writeback. */
6884 if (inst
.instruction
& LOAD_BIT
)
6886 /* Not allowed in LDM type 2. */
6887 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6888 && ((range
& (1 << REG_PC
)) == 0))
6889 as_warn (_("writeback of base register is UNPREDICTABLE"));
6890 /* Only allowed if base reg not in list for other types. */
6891 else if (range
& (1 << base_reg
))
6892 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6896 /* Not allowed for type 2. */
6897 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6898 as_warn (_("writeback of base register is UNPREDICTABLE"));
6899 /* Only allowed if base reg not in list, or first in list. */
6900 else if ((range
& (1 << base_reg
))
6901 && (range
& ((1 << base_reg
) - 1)))
6902 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6907 /* ARMv5TE load-consecutive (argument parse)
6916 constraint (inst
.operands
[0].reg
% 2 != 0,
6917 _("first destination register must be even"));
6918 constraint (inst
.operands
[1].present
6919 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6920 _("can only load two consecutive registers"));
6921 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6922 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6924 if (!inst
.operands
[1].present
)
6925 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6927 if (inst
.instruction
& LOAD_BIT
)
6929 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6930 register and the first register written; we have to diagnose
6931 overlap between the base and the second register written here. */
6933 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6934 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6935 as_warn (_("base register written back, and overlaps "
6936 "second destination register"));
6938 /* For an index-register load, the index register must not overlap the
6939 destination (even if not write-back). */
6940 else if (inst
.operands
[2].immisreg
6941 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6942 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6943 as_warn (_("index register overlaps destination register"));
6946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6947 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6953 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6954 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6955 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6956 || inst
.operands
[1].negative
6957 /* This can arise if the programmer has written
6959 or if they have mistakenly used a register name as the last
6962 It is very difficult to distinguish between these two cases
6963 because "rX" might actually be a label. ie the register
6964 name has been occluded by a symbol of the same name. So we
6965 just generate a general 'bad addressing mode' type error
6966 message and leave it up to the programmer to discover the
6967 true cause and fix their mistake. */
6968 || (inst
.operands
[1].reg
== REG_PC
),
6971 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6972 || inst
.reloc
.exp
.X_add_number
!= 0,
6973 _("offset must be zero in ARM encoding"));
6975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6976 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6977 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6983 constraint (inst
.operands
[0].reg
% 2 != 0,
6984 _("even register required"));
6985 constraint (inst
.operands
[1].present
6986 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6987 _("can only load two consecutive registers"));
6988 /* If op 1 were present and equal to PC, this function wouldn't
6989 have been called in the first place. */
6990 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6993 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6999 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7000 if (!inst
.operands
[1].isreg
)
7001 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7003 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7009 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7011 if (inst
.operands
[1].preind
)
7013 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7014 || inst
.reloc
.exp
.X_add_number
!= 0,
7015 _("this instruction requires a post-indexed address"));
7017 inst
.operands
[1].preind
= 0;
7018 inst
.operands
[1].postind
= 1;
7019 inst
.operands
[1].writeback
= 1;
7021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7022 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7025 /* Halfword and signed-byte load/store operations. */
7030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7031 if (!inst
.operands
[1].isreg
)
7032 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7034 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7040 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7042 if (inst
.operands
[1].preind
)
7044 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7045 || inst
.reloc
.exp
.X_add_number
!= 0,
7046 _("this instruction requires a post-indexed address"));
7048 inst
.operands
[1].preind
= 0;
7049 inst
.operands
[1].postind
= 1;
7050 inst
.operands
[1].writeback
= 1;
7052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7053 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7056 /* Co-processor register load/store.
7057 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7061 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7062 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7063 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7069 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7070 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7071 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7072 && !(inst
.instruction
& 0x00400000))
7073 as_tsktsk (_("Rd and Rm should be different in mla"));
7075 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7076 inst
.instruction
|= inst
.operands
[1].reg
;
7077 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7078 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7085 encode_arm_shifter_operand (1);
7088 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7095 top
= (inst
.instruction
& 0x00400000) != 0;
7096 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7097 _(":lower16: not allowed this instruction"));
7098 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7099 _(":upper16: not allowed instruction"));
7100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7101 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7103 imm
= inst
.reloc
.exp
.X_add_number
;
7104 /* The value is in two pieces: 0:11, 16:19. */
7105 inst
.instruction
|= (imm
& 0x00000fff);
7106 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7110 static void do_vfp_nsyn_opcode (const char *);
7113 do_vfp_nsyn_mrs (void)
7115 if (inst
.operands
[0].isvec
)
7117 if (inst
.operands
[1].reg
!= 1)
7118 first_error (_("operand 1 must be FPSCR"));
7119 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7120 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7121 do_vfp_nsyn_opcode ("fmstat");
7123 else if (inst
.operands
[1].isvec
)
7124 do_vfp_nsyn_opcode ("fmrx");
7132 do_vfp_nsyn_msr (void)
7134 if (inst
.operands
[0].isvec
)
7135 do_vfp_nsyn_opcode ("fmxr");
7145 if (do_vfp_nsyn_mrs () == SUCCESS
)
7148 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7149 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7151 _("'CPSR' or 'SPSR' expected"));
7152 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7153 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7156 /* Two possible forms:
7157 "{C|S}PSR_<field>, Rm",
7158 "{C|S}PSR_f, #expression". */
7163 if (do_vfp_nsyn_msr () == SUCCESS
)
7166 inst
.instruction
|= inst
.operands
[0].imm
;
7167 if (inst
.operands
[1].isreg
)
7168 inst
.instruction
|= inst
.operands
[1].reg
;
7171 inst
.instruction
|= INST_IMMEDIATE
;
7172 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7173 inst
.reloc
.pc_rel
= 0;
7180 if (!inst
.operands
[2].present
)
7181 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7182 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7183 inst
.instruction
|= inst
.operands
[1].reg
;
7184 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7186 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7187 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7188 as_tsktsk (_("Rd and Rm should be different in mul"));
7191 /* Long Multiply Parser
7192 UMULL RdLo, RdHi, Rm, Rs
7193 SMULL RdLo, RdHi, Rm, Rs
7194 UMLAL RdLo, RdHi, Rm, Rs
7195 SMLAL RdLo, RdHi, Rm, Rs. */
7200 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7201 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7202 inst
.instruction
|= inst
.operands
[2].reg
;
7203 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7205 /* rdhi and rdlo must be different. */
7206 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7207 as_tsktsk (_("rdhi and rdlo must be different"));
7209 /* rdhi, rdlo and rm must all be different before armv6. */
7210 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7211 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7212 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7213 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7219 if (inst
.operands
[0].present
)
7221 /* Architectural NOP hints are CPSR sets with no bits selected. */
7222 inst
.instruction
&= 0xf0000000;
7223 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7227 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7228 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7229 Condition defaults to COND_ALWAYS.
7230 Error if Rd, Rn or Rm are R15. */
7235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7236 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7237 inst
.instruction
|= inst
.operands
[2].reg
;
7238 if (inst
.operands
[3].present
)
7239 encode_arm_shift (3);
7242 /* ARM V6 PKHTB (Argument Parse). */
7247 if (!inst
.operands
[3].present
)
7249 /* If the shift specifier is omitted, turn the instruction
7250 into pkhbt rd, rm, rn. */
7251 inst
.instruction
&= 0xfff00010;
7252 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7253 inst
.instruction
|= inst
.operands
[1].reg
;
7254 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7258 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7259 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7260 inst
.instruction
|= inst
.operands
[2].reg
;
7261 encode_arm_shift (3);
7265 /* ARMv5TE: Preload-Cache
7269 Syntactically, like LDR with B=1, W=0, L=1. */
7274 constraint (!inst
.operands
[0].isreg
,
7275 _("'[' expected after PLD mnemonic"));
7276 constraint (inst
.operands
[0].postind
,
7277 _("post-indexed expression used in preload instruction"));
7278 constraint (inst
.operands
[0].writeback
,
7279 _("writeback used in preload instruction"));
7280 constraint (!inst
.operands
[0].preind
,
7281 _("unindexed addressing used in preload instruction"));
7282 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7285 /* ARMv7: PLI <addr_mode> */
7289 constraint (!inst
.operands
[0].isreg
,
7290 _("'[' expected after PLI mnemonic"));
7291 constraint (inst
.operands
[0].postind
,
7292 _("post-indexed expression used in preload instruction"));
7293 constraint (inst
.operands
[0].writeback
,
7294 _("writeback used in preload instruction"));
7295 constraint (!inst
.operands
[0].preind
,
7296 _("unindexed addressing used in preload instruction"));
7297 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7298 inst
.instruction
&= ~PRE_INDEX
;
7304 inst
.operands
[1] = inst
.operands
[0];
7305 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7306 inst
.operands
[0].isreg
= 1;
7307 inst
.operands
[0].writeback
= 1;
7308 inst
.operands
[0].reg
= REG_SP
;
7312 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7313 word at the specified address and the following word
7315 Unconditionally executed.
7316 Error if Rn is R15. */
7321 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7322 if (inst
.operands
[0].writeback
)
7323 inst
.instruction
|= WRITE_BACK
;
7326 /* ARM V6 ssat (argument parse). */
7331 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7332 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7333 inst
.instruction
|= inst
.operands
[2].reg
;
7335 if (inst
.operands
[3].present
)
7336 encode_arm_shift (3);
7339 /* ARM V6 usat (argument parse). */
7344 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7345 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7346 inst
.instruction
|= inst
.operands
[2].reg
;
7348 if (inst
.operands
[3].present
)
7349 encode_arm_shift (3);
7352 /* ARM V6 ssat16 (argument parse). */
7357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7358 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7359 inst
.instruction
|= inst
.operands
[2].reg
;
7365 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7366 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7367 inst
.instruction
|= inst
.operands
[2].reg
;
7370 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7371 preserving the other bits.
7373 setend <endian_specifier>, where <endian_specifier> is either
7379 if (inst
.operands
[0].imm
)
7380 inst
.instruction
|= 0x200;
7386 unsigned int Rm
= (inst
.operands
[1].present
7387 ? inst
.operands
[1].reg
7388 : inst
.operands
[0].reg
);
7390 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7391 inst
.instruction
|= Rm
;
7392 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7394 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7395 inst
.instruction
|= SHIFT_BY_REG
;
7398 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7404 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7405 inst
.reloc
.pc_rel
= 0;
7411 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7412 inst
.reloc
.pc_rel
= 0;
7415 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7416 SMLAxy{cond} Rd,Rm,Rs,Rn
7417 SMLAWy{cond} Rd,Rm,Rs,Rn
7418 Error if any register is R15. */
7423 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7424 inst
.instruction
|= inst
.operands
[1].reg
;
7425 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7426 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7429 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7430 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7431 Error if any register is R15.
7432 Warning if Rdlo == Rdhi. */
7437 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7438 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7439 inst
.instruction
|= inst
.operands
[2].reg
;
7440 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7442 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7443 as_tsktsk (_("rdhi and rdlo must be different"));
7446 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7447 SMULxy{cond} Rd,Rm,Rs
7448 Error if any register is R15. */
7453 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7454 inst
.instruction
|= inst
.operands
[1].reg
;
7455 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7458 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7459 the same for both ARM and Thumb-2. */
7466 if (inst
.operands
[0].present
)
7468 reg
= inst
.operands
[0].reg
;
7469 constraint (reg
!= 13, _("SRS base register must be r13"));
7474 inst
.instruction
|= reg
<< 16;
7475 inst
.instruction
|= inst
.operands
[1].imm
;
7476 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7477 inst
.instruction
|= WRITE_BACK
;
7480 /* ARM V6 strex (argument parse). */
7485 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7486 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7487 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7488 || inst
.operands
[2].negative
7489 /* See comment in do_ldrex(). */
7490 || (inst
.operands
[2].reg
== REG_PC
),
7493 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7494 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7496 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7497 || inst
.reloc
.exp
.X_add_number
!= 0,
7498 _("offset must be zero in ARM encoding"));
7500 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7501 inst
.instruction
|= inst
.operands
[1].reg
;
7502 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7503 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7509 constraint (inst
.operands
[1].reg
% 2 != 0,
7510 _("even register required"));
7511 constraint (inst
.operands
[2].present
7512 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7513 _("can only store two consecutive registers"));
7514 /* If op 2 were present and equal to PC, this function wouldn't
7515 have been called in the first place. */
7516 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7518 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7519 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7520 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7524 inst
.instruction
|= inst
.operands
[1].reg
;
7525 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7528 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7529 extends it to 32-bits, and adds the result to a value in another
7530 register. You can specify a rotation by 0, 8, 16, or 24 bits
7531 before extracting the 16-bit value.
7532 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7533 Condition defaults to COND_ALWAYS.
7534 Error if any register uses R15. */
7539 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7540 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7541 inst
.instruction
|= inst
.operands
[2].reg
;
7542 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7547 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7548 Condition defaults to COND_ALWAYS.
7549 Error if any register uses R15. */
7554 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7555 inst
.instruction
|= inst
.operands
[1].reg
;
7556 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7559 /* VFP instructions. In a logical order: SP variant first, monad
7560 before dyad, arithmetic then move then load/store. */
7563 do_vfp_sp_monadic (void)
7565 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7566 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7570 do_vfp_sp_dyadic (void)
7572 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7573 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7574 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7578 do_vfp_sp_compare_z (void)
7580 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7584 do_vfp_dp_sp_cvt (void)
7586 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7587 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7591 do_vfp_sp_dp_cvt (void)
7593 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7594 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7598 do_vfp_reg_from_sp (void)
7600 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7601 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7605 do_vfp_reg2_from_sp2 (void)
7607 constraint (inst
.operands
[2].imm
!= 2,
7608 _("only two consecutive VFP SP registers allowed here"));
7609 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7610 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7611 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7615 do_vfp_sp_from_reg (void)
7617 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7618 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7622 do_vfp_sp2_from_reg2 (void)
7624 constraint (inst
.operands
[0].imm
!= 2,
7625 _("only two consecutive VFP SP registers allowed here"));
7626 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7627 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7628 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7632 do_vfp_sp_ldst (void)
7634 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7635 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7639 do_vfp_dp_ldst (void)
7641 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7642 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7647 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7649 if (inst
.operands
[0].writeback
)
7650 inst
.instruction
|= WRITE_BACK
;
7652 constraint (ldstm_type
!= VFP_LDSTMIA
,
7653 _("this addressing mode requires base-register writeback"));
7654 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7655 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7656 inst
.instruction
|= inst
.operands
[1].imm
;
7660 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7664 if (inst
.operands
[0].writeback
)
7665 inst
.instruction
|= WRITE_BACK
;
7667 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7668 _("this addressing mode requires base-register writeback"));
7670 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7671 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7673 count
= inst
.operands
[1].imm
<< 1;
7674 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7677 inst
.instruction
|= count
;
7681 do_vfp_sp_ldstmia (void)
7683 vfp_sp_ldstm (VFP_LDSTMIA
);
7687 do_vfp_sp_ldstmdb (void)
7689 vfp_sp_ldstm (VFP_LDSTMDB
);
7693 do_vfp_dp_ldstmia (void)
7695 vfp_dp_ldstm (VFP_LDSTMIA
);
7699 do_vfp_dp_ldstmdb (void)
7701 vfp_dp_ldstm (VFP_LDSTMDB
);
7705 do_vfp_xp_ldstmia (void)
7707 vfp_dp_ldstm (VFP_LDSTMIAX
);
7711 do_vfp_xp_ldstmdb (void)
7713 vfp_dp_ldstm (VFP_LDSTMDBX
);
7717 do_vfp_dp_rd_rm (void)
7719 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7720 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7724 do_vfp_dp_rn_rd (void)
7726 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7727 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7731 do_vfp_dp_rd_rn (void)
7733 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7734 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7738 do_vfp_dp_rd_rn_rm (void)
7740 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7741 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7742 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7748 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7752 do_vfp_dp_rm_rd_rn (void)
7754 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7755 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7756 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7759 /* VFPv3 instructions. */
7761 do_vfp_sp_const (void)
7763 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7764 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7765 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7769 do_vfp_dp_const (void)
7771 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7772 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7773 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7777 vfp_conv (int srcsize
)
7779 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7780 inst
.instruction
|= (immbits
& 1) << 5;
7781 inst
.instruction
|= (immbits
>> 1);
7785 do_vfp_sp_conv_16 (void)
7787 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7792 do_vfp_dp_conv_16 (void)
7794 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7799 do_vfp_sp_conv_32 (void)
7801 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7806 do_vfp_dp_conv_32 (void)
7808 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7812 /* FPA instructions. Also in a logical order. */
7817 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7818 inst
.instruction
|= inst
.operands
[1].reg
;
7822 do_fpa_ldmstm (void)
7824 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7825 switch (inst
.operands
[1].imm
)
7827 case 1: inst
.instruction
|= CP_T_X
; break;
7828 case 2: inst
.instruction
|= CP_T_Y
; break;
7829 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7834 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7836 /* The instruction specified "ea" or "fd", so we can only accept
7837 [Rn]{!}. The instruction does not really support stacking or
7838 unstacking, so we have to emulate these by setting appropriate
7839 bits and offsets. */
7840 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7841 || inst
.reloc
.exp
.X_add_number
!= 0,
7842 _("this instruction does not support indexing"));
7844 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7845 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7847 if (!(inst
.instruction
& INDEX_UP
))
7848 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7850 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7852 inst
.operands
[2].preind
= 0;
7853 inst
.operands
[2].postind
= 1;
7857 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7860 /* iWMMXt instructions: strictly in alphabetical order. */
7863 do_iwmmxt_tandorc (void)
7865 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7869 do_iwmmxt_textrc (void)
7871 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7872 inst
.instruction
|= inst
.operands
[1].imm
;
7876 do_iwmmxt_textrm (void)
7878 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7879 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7880 inst
.instruction
|= inst
.operands
[2].imm
;
7884 do_iwmmxt_tinsr (void)
7886 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7887 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7888 inst
.instruction
|= inst
.operands
[2].imm
;
7892 do_iwmmxt_tmia (void)
7894 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7895 inst
.instruction
|= inst
.operands
[1].reg
;
7896 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7900 do_iwmmxt_waligni (void)
7902 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7903 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7904 inst
.instruction
|= inst
.operands
[2].reg
;
7905 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7909 do_iwmmxt_wmerge (void)
7911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7912 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7913 inst
.instruction
|= inst
.operands
[2].reg
;
7914 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7918 do_iwmmxt_wmov (void)
7920 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7922 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7923 inst
.instruction
|= inst
.operands
[1].reg
;
7927 do_iwmmxt_wldstbh (void)
7930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7932 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7934 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7935 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7939 do_iwmmxt_wldstw (void)
7941 /* RIWR_RIWC clears .isreg for a control register. */
7942 if (!inst
.operands
[0].isreg
)
7944 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7945 inst
.instruction
|= 0xf0000000;
7948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7949 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7953 do_iwmmxt_wldstd (void)
7955 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7956 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7957 && inst
.operands
[1].immisreg
)
7959 inst
.instruction
&= ~0x1a000ff;
7960 inst
.instruction
|= (0xf << 28);
7961 if (inst
.operands
[1].preind
)
7962 inst
.instruction
|= PRE_INDEX
;
7963 if (!inst
.operands
[1].negative
)
7964 inst
.instruction
|= INDEX_UP
;
7965 if (inst
.operands
[1].writeback
)
7966 inst
.instruction
|= WRITE_BACK
;
7967 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7968 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
7969 inst
.instruction
|= inst
.operands
[1].imm
;
7972 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7976 do_iwmmxt_wshufh (void)
7978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7979 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7980 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7981 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7985 do_iwmmxt_wzero (void)
7987 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7988 inst
.instruction
|= inst
.operands
[0].reg
;
7989 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7990 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7994 do_iwmmxt_wrwrwr_or_imm5 (void)
7996 if (inst
.operands
[2].isreg
)
7999 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8000 _("immediate operand requires iWMMXt2"));
8002 if (inst
.operands
[2].imm
== 0)
8004 switch ((inst
.instruction
>> 20) & 0xf)
8010 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8011 inst
.operands
[2].imm
= 16;
8012 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8018 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8019 inst
.operands
[2].imm
= 32;
8020 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8027 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8029 wrn
= (inst
.instruction
>> 16) & 0xf;
8030 inst
.instruction
&= 0xff0fff0f;
8031 inst
.instruction
|= wrn
;
8032 /* Bail out here; the instruction is now assembled. */
8037 /* Map 32 -> 0, etc. */
8038 inst
.operands
[2].imm
&= 0x1f;
8039 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8043 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8044 operations first, then control, shift, and load/store. */
8046 /* Insns like "foo X,Y,Z". */
8049 do_mav_triple (void)
8051 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8052 inst
.instruction
|= inst
.operands
[1].reg
;
8053 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8056 /* Insns like "foo W,X,Y,Z".
8057 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8062 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8063 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8064 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8065 inst
.instruction
|= inst
.operands
[3].reg
;
8068 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8072 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8075 /* Maverick shift immediate instructions.
8076 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8077 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8082 int imm
= inst
.operands
[2].imm
;
8084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8085 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8087 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8088 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8089 Bit 4 should be 0. */
8090 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8092 inst
.instruction
|= imm
;
8095 /* XScale instructions. Also sorted arithmetic before move. */
8097 /* Xscale multiply-accumulate (argument parse)
8100 MIAxycc acc0,Rm,Rs. */
8105 inst
.instruction
|= inst
.operands
[1].reg
;
8106 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8109 /* Xscale move-accumulator-register (argument parse)
8111 MARcc acc0,RdLo,RdHi. */
8116 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8117 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8120 /* Xscale move-register-accumulator (argument parse)
8122 MRAcc RdLo,RdHi,acc0. */
8127 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8128 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8129 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8132 /* Encoding functions relevant only to Thumb. */
8134 /* inst.operands[i] is a shifted-register operand; encode
8135 it into inst.instruction in the format used by Thumb32. */
8138 encode_thumb32_shifted_operand (int i
)
8140 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8141 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8143 constraint (inst
.operands
[i
].immisreg
,
8144 _("shift by register not allowed in thumb mode"));
8145 inst
.instruction
|= inst
.operands
[i
].reg
;
8146 if (shift
== SHIFT_RRX
)
8147 inst
.instruction
|= SHIFT_ROR
<< 4;
8150 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8151 _("expression too complex"));
8153 constraint (value
> 32
8154 || (value
== 32 && (shift
== SHIFT_LSL
8155 || shift
== SHIFT_ROR
)),
8156 _("shift expression is too large"));
8160 else if (value
== 32)
8163 inst
.instruction
|= shift
<< 4;
8164 inst
.instruction
|= (value
& 0x1c) << 10;
8165 inst
.instruction
|= (value
& 0x03) << 6;
8170 /* inst.operands[i] was set up by parse_address. Encode it into a
8171 Thumb32 format load or store instruction. Reject forms that cannot
8172 be used with such instructions. If is_t is true, reject forms that
8173 cannot be used with a T instruction; if is_d is true, reject forms
8174 that cannot be used with a D instruction. */
8177 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8179 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8181 constraint (!inst
.operands
[i
].isreg
,
8182 _("Instruction does not support =N addresses"));
8184 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8185 if (inst
.operands
[i
].immisreg
)
8187 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8188 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8189 constraint (inst
.operands
[i
].negative
,
8190 _("Thumb does not support negative register indexing"));
8191 constraint (inst
.operands
[i
].postind
,
8192 _("Thumb does not support register post-indexing"));
8193 constraint (inst
.operands
[i
].writeback
,
8194 _("Thumb does not support register indexing with writeback"));
8195 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8196 _("Thumb supports only LSL in shifted register indexing"));
8198 inst
.instruction
|= inst
.operands
[i
].imm
;
8199 if (inst
.operands
[i
].shifted
)
8201 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8202 _("expression too complex"));
8203 constraint (inst
.reloc
.exp
.X_add_number
< 0
8204 || inst
.reloc
.exp
.X_add_number
> 3,
8205 _("shift out of range"));
8206 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8208 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8210 else if (inst
.operands
[i
].preind
)
8212 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8213 _("cannot use writeback with PC-relative addressing"));
8214 constraint (is_t
&& inst
.operands
[i
].writeback
,
8215 _("cannot use writeback with this instruction"));
8219 inst
.instruction
|= 0x01000000;
8220 if (inst
.operands
[i
].writeback
)
8221 inst
.instruction
|= 0x00200000;
8225 inst
.instruction
|= 0x00000c00;
8226 if (inst
.operands
[i
].writeback
)
8227 inst
.instruction
|= 0x00000100;
8229 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8231 else if (inst
.operands
[i
].postind
)
8233 assert (inst
.operands
[i
].writeback
);
8234 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8235 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8238 inst
.instruction
|= 0x00200000;
8240 inst
.instruction
|= 0x00000900;
8241 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8243 else /* unindexed - only for coprocessor */
8244 inst
.error
= _("instruction does not accept unindexed addressing");
8247 /* Table of Thumb instructions which exist in both 16- and 32-bit
8248 encodings (the latter only in post-V6T2 cores). The index is the
8249 value used in the insns table below. When there is more than one
8250 possible 16-bit encoding for the instruction, this table always
8252 Also contains several pseudo-instructions used during relaxation. */
8253 #define T16_32_TAB \
8254 X(adc, 4140, eb400000), \
8255 X(adcs, 4140, eb500000), \
8256 X(add, 1c00, eb000000), \
8257 X(adds, 1c00, eb100000), \
8258 X(addi, 0000, f1000000), \
8259 X(addis, 0000, f1100000), \
8260 X(add_pc,000f, f20f0000), \
8261 X(add_sp,000d, f10d0000), \
8262 X(adr, 000f, f20f0000), \
8263 X(and, 4000, ea000000), \
8264 X(ands, 4000, ea100000), \
8265 X(asr, 1000, fa40f000), \
8266 X(asrs, 1000, fa50f000), \
8267 X(b, e000, f000b000), \
8268 X(bcond, d000, f0008000), \
8269 X(bic, 4380, ea200000), \
8270 X(bics, 4380, ea300000), \
8271 X(cmn, 42c0, eb100f00), \
8272 X(cmp, 2800, ebb00f00), \
8273 X(cpsie, b660, f3af8400), \
8274 X(cpsid, b670, f3af8600), \
8275 X(cpy, 4600, ea4f0000), \
8276 X(dec_sp,80dd, f1ad0d00), \
8277 X(eor, 4040, ea800000), \
8278 X(eors, 4040, ea900000), \
8279 X(inc_sp,00dd, f10d0d00), \
8280 X(ldmia, c800, e8900000), \
8281 X(ldr, 6800, f8500000), \
8282 X(ldrb, 7800, f8100000), \
8283 X(ldrh, 8800, f8300000), \
8284 X(ldrsb, 5600, f9100000), \
8285 X(ldrsh, 5e00, f9300000), \
8286 X(ldr_pc,4800, f85f0000), \
8287 X(ldr_pc2,4800, f85f0000), \
8288 X(ldr_sp,9800, f85d0000), \
8289 X(lsl, 0000, fa00f000), \
8290 X(lsls, 0000, fa10f000), \
8291 X(lsr, 0800, fa20f000), \
8292 X(lsrs, 0800, fa30f000), \
8293 X(mov, 2000, ea4f0000), \
8294 X(movs, 2000, ea5f0000), \
8295 X(mul, 4340, fb00f000), \
8296 X(muls, 4340, ffffffff), /* no 32b muls */ \
8297 X(mvn, 43c0, ea6f0000), \
8298 X(mvns, 43c0, ea7f0000), \
8299 X(neg, 4240, f1c00000), /* rsb #0 */ \
8300 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8301 X(orr, 4300, ea400000), \
8302 X(orrs, 4300, ea500000), \
8303 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8304 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8305 X(rev, ba00, fa90f080), \
8306 X(rev16, ba40, fa90f090), \
8307 X(revsh, bac0, fa90f0b0), \
8308 X(ror, 41c0, fa60f000), \
8309 X(rors, 41c0, fa70f000), \
8310 X(sbc, 4180, eb600000), \
8311 X(sbcs, 4180, eb700000), \
8312 X(stmia, c000, e8800000), \
8313 X(str, 6000, f8400000), \
8314 X(strb, 7000, f8000000), \
8315 X(strh, 8000, f8200000), \
8316 X(str_sp,9000, f84d0000), \
8317 X(sub, 1e00, eba00000), \
8318 X(subs, 1e00, ebb00000), \
8319 X(subi, 8000, f1a00000), \
8320 X(subis, 8000, f1b00000), \
8321 X(sxtb, b240, fa4ff080), \
8322 X(sxth, b200, fa0ff080), \
8323 X(tst, 4200, ea100f00), \
8324 X(uxtb, b2c0, fa5ff080), \
8325 X(uxth, b280, fa1ff080), \
8326 X(nop, bf00, f3af8000), \
8327 X(yield, bf10, f3af8001), \
8328 X(wfe, bf20, f3af8002), \
8329 X(wfi, bf30, f3af8003), \
8330 X(sev, bf40, f3af9004), /* typo, 8004? */
8332 /* To catch errors in encoding functions, the codes are all offset by
8333 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8334 as 16-bit instructions. */
8335 #define X(a,b,c) T_MNEM_##a
8336 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8339 #define X(a,b,c) 0x##b
8340 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8341 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8344 #define X(a,b,c) 0x##c
8345 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8346 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8347 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8351 /* Thumb instruction encoders, in alphabetical order. */
8355 do_t_add_sub_w (void)
8359 Rd
= inst
.operands
[0].reg
;
8360 Rn
= inst
.operands
[1].reg
;
8362 constraint (Rd
== 15, _("PC not allowed as destination"));
8363 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8364 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8367 /* Parse an add or subtract instruction. We get here with inst.instruction
8368 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8375 Rd
= inst
.operands
[0].reg
;
8376 Rs
= (inst
.operands
[1].present
8377 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8378 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8386 flags
= (inst
.instruction
== T_MNEM_adds
8387 || inst
.instruction
== T_MNEM_subs
);
8389 narrow
= (current_it_mask
== 0);
8391 narrow
= (current_it_mask
!= 0);
8392 if (!inst
.operands
[2].isreg
)
8396 add
= (inst
.instruction
== T_MNEM_add
8397 || inst
.instruction
== T_MNEM_adds
);
8399 if (inst
.size_req
!= 4)
8401 /* Attempt to use a narrow opcode, with relaxation if
8403 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8404 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8405 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8406 opcode
= T_MNEM_add_sp
;
8407 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8408 opcode
= T_MNEM_add_pc
;
8409 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8412 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8414 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8418 inst
.instruction
= THUMB_OP16(opcode
);
8419 inst
.instruction
|= (Rd
<< 4) | Rs
;
8420 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8421 if (inst
.size_req
!= 2)
8422 inst
.relax
= opcode
;
8425 constraint (inst
.size_req
== 2, BAD_HIREG
);
8427 if (inst
.size_req
== 4
8428 || (inst
.size_req
!= 2 && !opcode
))
8432 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8433 _("only SUBS PC, LR, #const allowed"));
8434 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8435 _("expression too complex"));
8436 constraint (inst
.reloc
.exp
.X_add_number
< 0
8437 || inst
.reloc
.exp
.X_add_number
> 0xff,
8438 _("immediate value out of range"));
8439 inst
.instruction
= T2_SUBS_PC_LR
8440 | inst
.reloc
.exp
.X_add_number
;
8441 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8444 else if (Rs
== REG_PC
)
8446 /* Always use addw/subw. */
8447 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8448 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8452 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8453 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8456 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8458 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8460 inst
.instruction
|= Rd
<< 8;
8461 inst
.instruction
|= Rs
<< 16;
8466 Rn
= inst
.operands
[2].reg
;
8467 /* See if we can do this with a 16-bit instruction. */
8468 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8470 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8475 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8476 || inst
.instruction
== T_MNEM_add
)
8479 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8483 if (inst
.instruction
== T_MNEM_add
)
8487 inst
.instruction
= T_OPCODE_ADD_HI
;
8488 inst
.instruction
|= (Rd
& 8) << 4;
8489 inst
.instruction
|= (Rd
& 7);
8490 inst
.instruction
|= Rn
<< 3;
8493 /* ... because addition is commutative! */
8496 inst
.instruction
= T_OPCODE_ADD_HI
;
8497 inst
.instruction
|= (Rd
& 8) << 4;
8498 inst
.instruction
|= (Rd
& 7);
8499 inst
.instruction
|= Rs
<< 3;
8504 /* If we get here, it can't be done in 16 bits. */
8505 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8506 _("shift must be constant"));
8507 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8508 inst
.instruction
|= Rd
<< 8;
8509 inst
.instruction
|= Rs
<< 16;
8510 encode_thumb32_shifted_operand (2);
8515 constraint (inst
.instruction
== T_MNEM_adds
8516 || inst
.instruction
== T_MNEM_subs
,
8519 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8521 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8522 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8525 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8527 inst
.instruction
|= (Rd
<< 4) | Rs
;
8528 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8532 Rn
= inst
.operands
[2].reg
;
8533 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8535 /* We now have Rd, Rs, and Rn set to registers. */
8536 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8538 /* Can't do this for SUB. */
8539 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8540 inst
.instruction
= T_OPCODE_ADD_HI
;
8541 inst
.instruction
|= (Rd
& 8) << 4;
8542 inst
.instruction
|= (Rd
& 7);
8544 inst
.instruction
|= Rn
<< 3;
8546 inst
.instruction
|= Rs
<< 3;
8548 constraint (1, _("dest must overlap one source register"));
8552 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8553 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8554 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8562 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8564 /* Defer to section relaxation. */
8565 inst
.relax
= inst
.instruction
;
8566 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8567 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8569 else if (unified_syntax
&& inst
.size_req
!= 2)
8571 /* Generate a 32-bit opcode. */
8572 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8573 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8574 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8575 inst
.reloc
.pc_rel
= 1;
8579 /* Generate a 16-bit opcode. */
8580 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8581 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8582 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8583 inst
.reloc
.pc_rel
= 1;
8585 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8589 /* Arithmetic instructions for which there is just one 16-bit
8590 instruction encoding, and it allows only two low registers.
8591 For maximal compatibility with ARM syntax, we allow three register
8592 operands even when Thumb-32 instructions are not available, as long
8593 as the first two are identical. For instance, both "sbc r0,r1" and
8594 "sbc r0,r0,r1" are allowed. */
8600 Rd
= inst
.operands
[0].reg
;
8601 Rs
= (inst
.operands
[1].present
8602 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8603 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8604 Rn
= inst
.operands
[2].reg
;
8608 if (!inst
.operands
[2].isreg
)
8610 /* For an immediate, we always generate a 32-bit opcode;
8611 section relaxation will shrink it later if possible. */
8612 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8613 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8614 inst
.instruction
|= Rd
<< 8;
8615 inst
.instruction
|= Rs
<< 16;
8616 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8622 /* See if we can do this with a 16-bit instruction. */
8623 if (THUMB_SETS_FLAGS (inst
.instruction
))
8624 narrow
= current_it_mask
== 0;
8626 narrow
= current_it_mask
!= 0;
8628 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8630 if (inst
.operands
[2].shifted
)
8632 if (inst
.size_req
== 4)
8638 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8639 inst
.instruction
|= Rd
;
8640 inst
.instruction
|= Rn
<< 3;
8644 /* If we get here, it can't be done in 16 bits. */
8645 constraint (inst
.operands
[2].shifted
8646 && inst
.operands
[2].immisreg
,
8647 _("shift must be constant"));
8648 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8649 inst
.instruction
|= Rd
<< 8;
8650 inst
.instruction
|= Rs
<< 16;
8651 encode_thumb32_shifted_operand (2);
8656 /* On its face this is a lie - the instruction does set the
8657 flags. However, the only supported mnemonic in this mode
8659 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8661 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8662 _("unshifted register required"));
8663 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8664 constraint (Rd
!= Rs
,
8665 _("dest and source1 must be the same register"));
8667 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8668 inst
.instruction
|= Rd
;
8669 inst
.instruction
|= Rn
<< 3;
8673 /* Similarly, but for instructions where the arithmetic operation is
8674 commutative, so we can allow either of them to be different from
8675 the destination operand in a 16-bit instruction. For instance, all
8676 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8683 Rd
= inst
.operands
[0].reg
;
8684 Rs
= (inst
.operands
[1].present
8685 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8686 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8687 Rn
= inst
.operands
[2].reg
;
8691 if (!inst
.operands
[2].isreg
)
8693 /* For an immediate, we always generate a 32-bit opcode;
8694 section relaxation will shrink it later if possible. */
8695 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8696 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8697 inst
.instruction
|= Rd
<< 8;
8698 inst
.instruction
|= Rs
<< 16;
8699 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8705 /* See if we can do this with a 16-bit instruction. */
8706 if (THUMB_SETS_FLAGS (inst
.instruction
))
8707 narrow
= current_it_mask
== 0;
8709 narrow
= current_it_mask
!= 0;
8711 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8713 if (inst
.operands
[2].shifted
)
8715 if (inst
.size_req
== 4)
8722 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8723 inst
.instruction
|= Rd
;
8724 inst
.instruction
|= Rn
<< 3;
8729 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8730 inst
.instruction
|= Rd
;
8731 inst
.instruction
|= Rs
<< 3;
8736 /* If we get here, it can't be done in 16 bits. */
8737 constraint (inst
.operands
[2].shifted
8738 && inst
.operands
[2].immisreg
,
8739 _("shift must be constant"));
8740 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8741 inst
.instruction
|= Rd
<< 8;
8742 inst
.instruction
|= Rs
<< 16;
8743 encode_thumb32_shifted_operand (2);
8748 /* On its face this is a lie - the instruction does set the
8749 flags. However, the only supported mnemonic in this mode
8751 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8753 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8754 _("unshifted register required"));
8755 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8757 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8758 inst
.instruction
|= Rd
;
8761 inst
.instruction
|= Rn
<< 3;
8763 inst
.instruction
|= Rs
<< 3;
8765 constraint (1, _("dest must overlap one source register"));
8772 if (inst
.operands
[0].present
)
8774 constraint ((inst
.instruction
& 0xf0) != 0x40
8775 && inst
.operands
[0].imm
!= 0xf,
8776 _("bad barrier type"));
8777 inst
.instruction
|= inst
.operands
[0].imm
;
8780 inst
.instruction
|= 0xf;
8786 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8787 constraint (msb
> 32, _("bit-field extends past end of register"));
8788 /* The instruction encoding stores the LSB and MSB,
8789 not the LSB and width. */
8790 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8791 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8792 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8793 inst
.instruction
|= msb
- 1;
8801 /* #0 in second position is alternative syntax for bfc, which is
8802 the same instruction but with REG_PC in the Rm field. */
8803 if (!inst
.operands
[1].isreg
)
8804 inst
.operands
[1].reg
= REG_PC
;
8806 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8807 constraint (msb
> 32, _("bit-field extends past end of register"));
8808 /* The instruction encoding stores the LSB and MSB,
8809 not the LSB and width. */
8810 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8811 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8812 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8813 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8814 inst
.instruction
|= msb
- 1;
8820 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8821 _("bit-field extends past end of register"));
8822 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8823 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8824 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8825 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8826 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8829 /* ARM V5 Thumb BLX (argument parse)
8830 BLX <target_addr> which is BLX(1)
8831 BLX <Rm> which is BLX(2)
8832 Unfortunately, there are two different opcodes for this mnemonic.
8833 So, the insns[].value is not used, and the code here zaps values
8834 into inst.instruction.
8836 ??? How to take advantage of the additional two bits of displacement
8837 available in Thumb32 mode? Need new relocation? */
8842 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8843 if (inst
.operands
[0].isreg
)
8844 /* We have a register, so this is BLX(2). */
8845 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8848 /* No register. This must be BLX(1). */
8849 inst
.instruction
= 0xf000e800;
8851 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8852 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8855 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8856 inst
.reloc
.pc_rel
= 1;
8866 if (current_it_mask
)
8868 /* Conditional branches inside IT blocks are encoded as unconditional
8871 /* A branch must be the last instruction in an IT block. */
8872 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8877 if (cond
!= COND_ALWAYS
)
8878 opcode
= T_MNEM_bcond
;
8880 opcode
= inst
.instruction
;
8882 if (unified_syntax
&& inst
.size_req
== 4)
8884 inst
.instruction
= THUMB_OP32(opcode
);
8885 if (cond
== COND_ALWAYS
)
8886 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8889 assert (cond
!= 0xF);
8890 inst
.instruction
|= cond
<< 22;
8891 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8896 inst
.instruction
= THUMB_OP16(opcode
);
8897 if (cond
== COND_ALWAYS
)
8898 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8901 inst
.instruction
|= cond
<< 8;
8902 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8904 /* Allow section relaxation. */
8905 if (unified_syntax
&& inst
.size_req
!= 2)
8906 inst
.relax
= opcode
;
8909 inst
.reloc
.pc_rel
= 1;
8915 constraint (inst
.cond
!= COND_ALWAYS
,
8916 _("instruction is always unconditional"));
8917 if (inst
.operands
[0].present
)
8919 constraint (inst
.operands
[0].imm
> 255,
8920 _("immediate value out of range"));
8921 inst
.instruction
|= inst
.operands
[0].imm
;
8926 do_t_branch23 (void)
8928 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8929 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8930 inst
.reloc
.pc_rel
= 1;
8932 /* If the destination of the branch is a defined symbol which does not have
8933 the THUMB_FUNC attribute, then we must be calling a function which has
8934 the (interfacearm) attribute. We look for the Thumb entry point to that
8935 function and change the branch to refer to that function instead. */
8936 if ( inst
.reloc
.exp
.X_op
== O_symbol
8937 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8938 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8939 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8940 inst
.reloc
.exp
.X_add_symbol
=
8941 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8947 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8948 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8949 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8950 should cause the alignment to be checked once it is known. This is
8951 because BX PC only works if the instruction is word aligned. */
8957 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8958 if (inst
.operands
[0].reg
== REG_PC
)
8959 as_tsktsk (_("use of r15 in bxj is not really useful"));
8961 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8967 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8968 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8969 inst
.instruction
|= inst
.operands
[1].reg
;
8975 constraint (current_it_mask
, BAD_NOT_IT
);
8976 inst
.instruction
|= inst
.operands
[0].imm
;
8982 constraint (current_it_mask
, BAD_NOT_IT
);
8984 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8985 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8987 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8988 inst
.instruction
= 0xf3af8000;
8989 inst
.instruction
|= imod
<< 9;
8990 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8991 if (inst
.operands
[1].present
)
8992 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8996 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8997 && (inst
.operands
[0].imm
& 4),
8998 _("selected processor does not support 'A' form "
8999 "of this instruction"));
9000 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9001 _("Thumb does not support the 2-argument "
9002 "form of this instruction"));
9003 inst
.instruction
|= inst
.operands
[0].imm
;
9007 /* THUMB CPY instruction (argument parse). */
9012 if (inst
.size_req
== 4)
9014 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9015 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9016 inst
.instruction
|= inst
.operands
[1].reg
;
9020 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9021 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9022 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9029 constraint (current_it_mask
, BAD_NOT_IT
);
9030 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9031 inst
.instruction
|= inst
.operands
[0].reg
;
9032 inst
.reloc
.pc_rel
= 1;
9033 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9039 inst
.instruction
|= inst
.operands
[0].imm
;
9045 if (!inst
.operands
[1].present
)
9046 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9047 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9048 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9049 inst
.instruction
|= inst
.operands
[2].reg
;
9055 if (unified_syntax
&& inst
.size_req
== 4)
9056 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9058 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9064 unsigned int cond
= inst
.operands
[0].imm
;
9066 constraint (current_it_mask
, BAD_NOT_IT
);
9067 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9070 /* If the condition is a negative condition, invert the mask. */
9071 if ((cond
& 0x1) == 0x0)
9073 unsigned int mask
= inst
.instruction
& 0x000f;
9075 if ((mask
& 0x7) == 0)
9076 /* no conversion needed */;
9077 else if ((mask
& 0x3) == 0)
9079 else if ((mask
& 0x1) == 0)
9084 inst
.instruction
&= 0xfff0;
9085 inst
.instruction
|= mask
;
9088 inst
.instruction
|= cond
<< 4;
9091 /* Helper function used for both push/pop and ldm/stm. */
9093 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9097 load
= (inst
.instruction
& (1 << 20)) != 0;
9099 if (mask
& (1 << 13))
9100 inst
.error
= _("SP not allowed in register list");
9103 if (mask
& (1 << 14)
9104 && mask
& (1 << 15))
9105 inst
.error
= _("LR and PC should not both be in register list");
9107 if ((mask
& (1 << base
)) != 0
9109 as_warn (_("base register should not be in register list "
9110 "when written back"));
9114 if (mask
& (1 << 15))
9115 inst
.error
= _("PC not allowed in register list");
9117 if (mask
& (1 << base
))
9118 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9121 if ((mask
& (mask
- 1)) == 0)
9123 /* Single register transfers implemented as str/ldr. */
9126 if (inst
.instruction
& (1 << 23))
9127 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9129 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9133 if (inst
.instruction
& (1 << 23))
9134 inst
.instruction
= 0x00800000; /* ia -> [base] */
9136 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9139 inst
.instruction
|= 0xf8400000;
9141 inst
.instruction
|= 0x00100000;
9143 mask
= ffs (mask
) - 1;
9147 inst
.instruction
|= WRITE_BACK
;
9149 inst
.instruction
|= mask
;
9150 inst
.instruction
|= base
<< 16;
9156 /* This really doesn't seem worth it. */
9157 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9158 _("expression too complex"));
9159 constraint (inst
.operands
[1].writeback
,
9160 _("Thumb load/store multiple does not support {reglist}^"));
9168 /* See if we can use a 16-bit instruction. */
9169 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9170 && inst
.size_req
!= 4
9171 && !(inst
.operands
[1].imm
& ~0xff))
9173 mask
= 1 << inst
.operands
[0].reg
;
9175 if (inst
.operands
[0].reg
<= 7
9176 && (inst
.instruction
== T_MNEM_stmia
9177 ? inst
.operands
[0].writeback
9178 : (inst
.operands
[0].writeback
9179 == !(inst
.operands
[1].imm
& mask
))))
9181 if (inst
.instruction
== T_MNEM_stmia
9182 && (inst
.operands
[1].imm
& mask
)
9183 && (inst
.operands
[1].imm
& (mask
- 1)))
9184 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9185 inst
.operands
[0].reg
);
9187 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9188 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9189 inst
.instruction
|= inst
.operands
[1].imm
;
9192 else if (inst
.operands
[0] .reg
== REG_SP
9193 && inst
.operands
[0].writeback
)
9195 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9196 ? T_MNEM_push
: T_MNEM_pop
);
9197 inst
.instruction
|= inst
.operands
[1].imm
;
9204 if (inst
.instruction
< 0xffff)
9205 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9207 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9208 inst
.operands
[0].writeback
);
9213 constraint (inst
.operands
[0].reg
> 7
9214 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9215 constraint (inst
.instruction
!= T_MNEM_ldmia
9216 && inst
.instruction
!= T_MNEM_stmia
,
9217 _("Thumb-2 instruction only valid in unified syntax"));
9218 if (inst
.instruction
== T_MNEM_stmia
)
9220 if (!inst
.operands
[0].writeback
)
9221 as_warn (_("this instruction will write back the base register"));
9222 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9223 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9224 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9225 inst
.operands
[0].reg
);
9229 if (!inst
.operands
[0].writeback
9230 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9231 as_warn (_("this instruction will write back the base register"));
9232 else if (inst
.operands
[0].writeback
9233 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9234 as_warn (_("this instruction will not write back the base register"));
9237 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9238 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9239 inst
.instruction
|= inst
.operands
[1].imm
;
9246 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9247 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9248 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9249 || inst
.operands
[1].negative
,
9252 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9253 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9254 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9260 if (!inst
.operands
[1].present
)
9262 constraint (inst
.operands
[0].reg
== REG_LR
,
9263 _("r14 not allowed as first register "
9264 "when second register is omitted"));
9265 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9267 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9270 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9271 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9272 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9278 unsigned long opcode
;
9281 opcode
= inst
.instruction
;
9284 if (!inst
.operands
[1].isreg
)
9286 if (opcode
<= 0xffff)
9287 inst
.instruction
= THUMB_OP32 (opcode
);
9288 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9291 if (inst
.operands
[1].isreg
9292 && !inst
.operands
[1].writeback
9293 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9294 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9296 && inst
.size_req
!= 4)
9298 /* Insn may have a 16-bit form. */
9299 Rn
= inst
.operands
[1].reg
;
9300 if (inst
.operands
[1].immisreg
)
9302 inst
.instruction
= THUMB_OP16 (opcode
);
9304 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9307 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9308 && opcode
!= T_MNEM_ldrsb
)
9309 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9310 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9317 if (inst
.reloc
.pc_rel
)
9318 opcode
= T_MNEM_ldr_pc2
;
9320 opcode
= T_MNEM_ldr_pc
;
9324 if (opcode
== T_MNEM_ldr
)
9325 opcode
= T_MNEM_ldr_sp
;
9327 opcode
= T_MNEM_str_sp
;
9329 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9333 inst
.instruction
= inst
.operands
[0].reg
;
9334 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9336 inst
.instruction
|= THUMB_OP16 (opcode
);
9337 if (inst
.size_req
== 2)
9338 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9340 inst
.relax
= opcode
;
9344 /* Definitely a 32-bit variant. */
9345 inst
.instruction
= THUMB_OP32 (opcode
);
9346 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9347 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9351 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9353 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9355 /* Only [Rn,Rm] is acceptable. */
9356 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9357 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9358 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9359 || inst
.operands
[1].negative
,
9360 _("Thumb does not support this addressing mode"));
9361 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9365 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9366 if (!inst
.operands
[1].isreg
)
9367 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9370 constraint (!inst
.operands
[1].preind
9371 || inst
.operands
[1].shifted
9372 || inst
.operands
[1].writeback
,
9373 _("Thumb does not support this addressing mode"));
9374 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9376 constraint (inst
.instruction
& 0x0600,
9377 _("byte or halfword not valid for base register"));
9378 constraint (inst
.operands
[1].reg
== REG_PC
9379 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9380 _("r15 based store not allowed"));
9381 constraint (inst
.operands
[1].immisreg
,
9382 _("invalid base register for register offset"));
9384 if (inst
.operands
[1].reg
== REG_PC
)
9385 inst
.instruction
= T_OPCODE_LDR_PC
;
9386 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9387 inst
.instruction
= T_OPCODE_LDR_SP
;
9389 inst
.instruction
= T_OPCODE_STR_SP
;
9391 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9392 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9396 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9397 if (!inst
.operands
[1].immisreg
)
9399 /* Immediate offset. */
9400 inst
.instruction
|= inst
.operands
[0].reg
;
9401 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9402 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9406 /* Register offset. */
9407 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9408 constraint (inst
.operands
[1].negative
,
9409 _("Thumb does not support this addressing mode"));
9412 switch (inst
.instruction
)
9414 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9415 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9416 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9417 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9418 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9419 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9420 case 0x5600 /* ldrsb */:
9421 case 0x5e00 /* ldrsh */: break;
9425 inst
.instruction
|= inst
.operands
[0].reg
;
9426 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9427 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9433 if (!inst
.operands
[1].present
)
9435 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9436 constraint (inst
.operands
[0].reg
== REG_LR
,
9437 _("r14 not allowed here"));
9439 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9440 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9441 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9448 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9454 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9455 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9456 inst
.instruction
|= inst
.operands
[2].reg
;
9457 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9463 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9464 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9465 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9466 inst
.instruction
|= inst
.operands
[3].reg
;
9474 int r0off
= (inst
.instruction
== T_MNEM_mov
9475 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9476 unsigned long opcode
;
9478 bfd_boolean low_regs
;
9480 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9481 opcode
= inst
.instruction
;
9482 if (current_it_mask
)
9483 narrow
= opcode
!= T_MNEM_movs
;
9485 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9486 if (inst
.size_req
== 4
9487 || inst
.operands
[1].shifted
)
9490 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9491 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9492 && !inst
.operands
[1].shifted
9493 && inst
.operands
[0].reg
== REG_PC
9494 && inst
.operands
[1].reg
== REG_LR
)
9496 inst
.instruction
= T2_SUBS_PC_LR
;
9500 if (!inst
.operands
[1].isreg
)
9502 /* Immediate operand. */
9503 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9505 if (low_regs
&& narrow
)
9507 inst
.instruction
= THUMB_OP16 (opcode
);
9508 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9509 if (inst
.size_req
== 2)
9510 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9512 inst
.relax
= opcode
;
9516 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9517 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9518 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9519 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9522 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9523 && (inst
.instruction
== T_MNEM_mov
9524 || inst
.instruction
== T_MNEM_movs
))
9526 /* Register shifts are encoded as separate shift instructions. */
9527 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9529 if (current_it_mask
)
9534 if (inst
.size_req
== 4)
9537 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9540 if (inst
.operands
[0].reg
!= inst
.operands
[1].reg
)
9543 switch (inst
.operands
[1].shift_kind
)
9546 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9549 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9552 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9555 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9561 inst
.instruction
= opcode
;
9564 inst
.instruction
|= inst
.operands
[0].reg
;
9565 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9570 inst
.instruction
|= CONDS_BIT
;
9572 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9573 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9574 inst
.instruction
|= inst
.operands
[1].imm
;
9579 /* Some mov with immediate shift have narrow variants.
9580 Register shifts are handled above. */
9581 if (low_regs
&& inst
.operands
[1].shifted
9582 && (inst
.instruction
== T_MNEM_mov
9583 || inst
.instruction
== T_MNEM_movs
))
9585 if (current_it_mask
)
9586 narrow
= (inst
.instruction
== T_MNEM_mov
);
9588 narrow
= (inst
.instruction
== T_MNEM_movs
);
9593 switch (inst
.operands
[1].shift_kind
)
9595 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9596 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9597 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9598 default: narrow
= FALSE
; break;
9604 inst
.instruction
|= inst
.operands
[0].reg
;
9605 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9606 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9610 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9611 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9612 encode_thumb32_shifted_operand (1);
9616 switch (inst
.instruction
)
9619 inst
.instruction
= T_OPCODE_MOV_HR
;
9620 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9621 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9622 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9626 /* We know we have low registers at this point.
9627 Generate ADD Rd, Rs, #0. */
9628 inst
.instruction
= T_OPCODE_ADD_I3
;
9629 inst
.instruction
|= inst
.operands
[0].reg
;
9630 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9636 inst
.instruction
= T_OPCODE_CMP_LR
;
9637 inst
.instruction
|= inst
.operands
[0].reg
;
9638 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9642 inst
.instruction
= T_OPCODE_CMP_HR
;
9643 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9644 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9645 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9652 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9653 if (inst
.operands
[1].isreg
)
9655 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9657 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9658 since a MOV instruction produces unpredictable results. */
9659 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9660 inst
.instruction
= T_OPCODE_ADD_I3
;
9662 inst
.instruction
= T_OPCODE_CMP_LR
;
9664 inst
.instruction
|= inst
.operands
[0].reg
;
9665 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9669 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9670 inst
.instruction
= T_OPCODE_MOV_HR
;
9672 inst
.instruction
= T_OPCODE_CMP_HR
;
9678 constraint (inst
.operands
[0].reg
> 7,
9679 _("only lo regs allowed with immediate"));
9680 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9681 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9691 top
= (inst
.instruction
& 0x00800000) != 0;
9692 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9694 constraint (top
, _(":lower16: not allowed this instruction"));
9695 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9697 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9699 constraint (!top
, _(":upper16: not allowed this instruction"));
9700 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9703 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9704 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9706 imm
= inst
.reloc
.exp
.X_add_number
;
9707 inst
.instruction
|= (imm
& 0xf000) << 4;
9708 inst
.instruction
|= (imm
& 0x0800) << 15;
9709 inst
.instruction
|= (imm
& 0x0700) << 4;
9710 inst
.instruction
|= (imm
& 0x00ff);
9719 int r0off
= (inst
.instruction
== T_MNEM_mvn
9720 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9723 if (inst
.size_req
== 4
9724 || inst
.instruction
> 0xffff
9725 || inst
.operands
[1].shifted
9726 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9728 else if (inst
.instruction
== T_MNEM_cmn
)
9730 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9731 narrow
= (current_it_mask
== 0);
9733 narrow
= (current_it_mask
!= 0);
9735 if (!inst
.operands
[1].isreg
)
9737 /* For an immediate, we always generate a 32-bit opcode;
9738 section relaxation will shrink it later if possible. */
9739 if (inst
.instruction
< 0xffff)
9740 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9741 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9742 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9743 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9747 /* See if we can do this with a 16-bit instruction. */
9750 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9751 inst
.instruction
|= inst
.operands
[0].reg
;
9752 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9756 constraint (inst
.operands
[1].shifted
9757 && inst
.operands
[1].immisreg
,
9758 _("shift must be constant"));
9759 if (inst
.instruction
< 0xffff)
9760 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9761 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9762 encode_thumb32_shifted_operand (1);
9768 constraint (inst
.instruction
> 0xffff
9769 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9770 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9771 _("unshifted register required"));
9772 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9775 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9776 inst
.instruction
|= inst
.operands
[0].reg
;
9777 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9786 if (do_vfp_nsyn_mrs () == SUCCESS
)
9789 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9792 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9793 _("selected processor does not support "
9794 "requested special purpose register"));
9798 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9799 _("selected processor does not support "
9800 "requested special purpose register %x"));
9801 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9802 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9803 _("'CPSR' or 'SPSR' expected"));
9806 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9807 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9808 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9816 if (do_vfp_nsyn_msr () == SUCCESS
)
9819 constraint (!inst
.operands
[1].isreg
,
9820 _("Thumb encoding does not support an immediate here"));
9821 flags
= inst
.operands
[0].imm
;
9824 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9825 _("selected processor does not support "
9826 "requested special purpose register"));
9830 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9831 _("selected processor does not support "
9832 "requested special purpose register"));
9835 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9836 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9837 inst
.instruction
|= (flags
& 0xff);
9838 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9844 if (!inst
.operands
[2].present
)
9845 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9847 /* There is no 32-bit MULS and no 16-bit MUL. */
9848 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9850 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9851 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9852 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9853 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9857 constraint (!unified_syntax
9858 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9859 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9862 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9863 inst
.instruction
|= inst
.operands
[0].reg
;
9865 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9866 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9867 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9868 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9870 constraint (1, _("dest must overlap one source register"));
9877 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9878 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9879 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9880 inst
.instruction
|= inst
.operands
[3].reg
;
9882 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9883 as_tsktsk (_("rdhi and rdlo must be different"));
9891 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9893 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9894 inst
.instruction
|= inst
.operands
[0].imm
;
9898 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9899 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9904 constraint (inst
.operands
[0].present
,
9905 _("Thumb does not support NOP with hints"));
9906 inst
.instruction
= 0x46c0;
9917 if (THUMB_SETS_FLAGS (inst
.instruction
))
9918 narrow
= (current_it_mask
== 0);
9920 narrow
= (current_it_mask
!= 0);
9921 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9923 if (inst
.size_req
== 4)
9928 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9929 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9930 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9934 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9935 inst
.instruction
|= inst
.operands
[0].reg
;
9936 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9941 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9943 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9945 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9946 inst
.instruction
|= inst
.operands
[0].reg
;
9947 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9954 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9956 inst
.instruction
|= inst
.operands
[2].reg
;
9957 if (inst
.operands
[3].present
)
9959 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9960 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9961 _("expression too complex"));
9962 inst
.instruction
|= (val
& 0x1c) << 10;
9963 inst
.instruction
|= (val
& 0x03) << 6;
9970 if (!inst
.operands
[3].present
)
9971 inst
.instruction
&= ~0x00000020;
9978 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9982 do_t_push_pop (void)
9986 constraint (inst
.operands
[0].writeback
,
9987 _("push/pop do not support {reglist}^"));
9988 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9989 _("expression too complex"));
9991 mask
= inst
.operands
[0].imm
;
9992 if ((mask
& ~0xff) == 0)
9993 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
9994 else if ((inst
.instruction
== T_MNEM_push
9995 && (mask
& ~0xff) == 1 << REG_LR
)
9996 || (inst
.instruction
== T_MNEM_pop
9997 && (mask
& ~0xff) == 1 << REG_PC
))
9999 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10000 inst
.instruction
|= THUMB_PP_PC_LR
;
10001 inst
.instruction
|= mask
& 0xff;
10003 else if (unified_syntax
)
10005 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10006 encode_thumb2_ldmstm (13, mask
, TRUE
);
10010 inst
.error
= _("invalid register list to push/pop instruction");
10018 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10019 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10025 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10026 && inst
.size_req
!= 4)
10028 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10029 inst
.instruction
|= inst
.operands
[0].reg
;
10030 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10032 else if (unified_syntax
)
10034 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10035 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10036 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10037 inst
.instruction
|= inst
.operands
[1].reg
;
10040 inst
.error
= BAD_HIREG
;
10048 Rd
= inst
.operands
[0].reg
;
10049 Rs
= (inst
.operands
[1].present
10050 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10051 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10053 inst
.instruction
|= Rd
<< 8;
10054 inst
.instruction
|= Rs
<< 16;
10055 if (!inst
.operands
[2].isreg
)
10057 bfd_boolean narrow
;
10059 if ((inst
.instruction
& 0x00100000) != 0)
10060 narrow
= (current_it_mask
== 0);
10062 narrow
= (current_it_mask
!= 0);
10064 if (Rd
> 7 || Rs
> 7)
10067 if (inst
.size_req
== 4 || !unified_syntax
)
10070 if (inst
.reloc
.exp
.X_op
!= O_constant
10071 || inst
.reloc
.exp
.X_add_number
!= 0)
10074 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10075 relaxation, but it doesn't seem worth the hassle. */
10078 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10079 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10080 inst
.instruction
|= Rs
<< 3;
10081 inst
.instruction
|= Rd
;
10085 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10086 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10090 encode_thumb32_shifted_operand (2);
10096 constraint (current_it_mask
, BAD_NOT_IT
);
10097 if (inst
.operands
[0].imm
)
10098 inst
.instruction
|= 0x8;
10104 if (!inst
.operands
[1].present
)
10105 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10107 if (unified_syntax
)
10109 bfd_boolean narrow
;
10112 switch (inst
.instruction
)
10115 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10117 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10119 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10121 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10125 if (THUMB_SETS_FLAGS (inst
.instruction
))
10126 narrow
= (current_it_mask
== 0);
10128 narrow
= (current_it_mask
!= 0);
10129 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10131 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10133 if (inst
.operands
[2].isreg
10134 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10135 || inst
.operands
[2].reg
> 7))
10137 if (inst
.size_req
== 4)
10142 if (inst
.operands
[2].isreg
)
10144 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10145 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10146 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10147 inst
.instruction
|= inst
.operands
[2].reg
;
10151 inst
.operands
[1].shifted
= 1;
10152 inst
.operands
[1].shift_kind
= shift_kind
;
10153 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10154 ? T_MNEM_movs
: T_MNEM_mov
);
10155 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10156 encode_thumb32_shifted_operand (1);
10157 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10158 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10163 if (inst
.operands
[2].isreg
)
10165 switch (shift_kind
)
10167 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10168 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10169 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10170 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10174 inst
.instruction
|= inst
.operands
[0].reg
;
10175 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10179 switch (shift_kind
)
10181 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10182 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10183 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10186 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10187 inst
.instruction
|= inst
.operands
[0].reg
;
10188 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10194 constraint (inst
.operands
[0].reg
> 7
10195 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10196 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10198 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10200 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10201 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10202 _("source1 and dest must be same register"));
10204 switch (inst
.instruction
)
10206 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10207 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10208 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10209 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10213 inst
.instruction
|= inst
.operands
[0].reg
;
10214 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10218 switch (inst
.instruction
)
10220 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10221 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10222 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10223 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10226 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10227 inst
.instruction
|= inst
.operands
[0].reg
;
10228 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10236 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10237 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10238 inst
.instruction
|= inst
.operands
[2].reg
;
10244 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10245 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10246 _("expression too complex"));
10247 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10248 inst
.instruction
|= (value
& 0xf000) >> 12;
10249 inst
.instruction
|= (value
& 0x0ff0);
10250 inst
.instruction
|= (value
& 0x000f) << 16;
10256 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10257 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10258 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10260 if (inst
.operands
[3].present
)
10262 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10263 _("expression too complex"));
10265 if (inst
.reloc
.exp
.X_add_number
!= 0)
10267 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10268 inst
.instruction
|= 0x00200000; /* sh bit */
10269 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10270 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10272 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10279 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10280 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10281 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10287 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10288 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10289 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10290 || inst
.operands
[2].negative
,
10293 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10294 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10295 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10296 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10302 if (!inst
.operands
[2].present
)
10303 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10305 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10306 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10307 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10308 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10311 inst
.instruction
|= inst
.operands
[0].reg
;
10312 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10313 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10314 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10320 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10321 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10322 inst
.instruction
|= inst
.operands
[2].reg
;
10323 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10329 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10330 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10331 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10333 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10334 inst
.instruction
|= inst
.operands
[0].reg
;
10335 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10337 else if (unified_syntax
)
10339 if (inst
.instruction
<= 0xffff)
10340 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10341 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10342 inst
.instruction
|= inst
.operands
[1].reg
;
10343 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10347 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10348 _("Thumb encoding does not support rotation"));
10349 constraint (1, BAD_HIREG
);
10356 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10364 half
= (inst
.instruction
& 0x10) != 0;
10365 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10366 constraint (inst
.operands
[0].immisreg
,
10367 _("instruction requires register index"));
10368 constraint (inst
.operands
[0].imm
== 15,
10369 _("PC is not a valid index register"));
10370 constraint (!half
&& inst
.operands
[0].shifted
,
10371 _("instruction does not allow shifted index"));
10372 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10378 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10379 inst
.instruction
|= inst
.operands
[1].imm
;
10380 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10382 if (inst
.operands
[3].present
)
10384 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10385 _("expression too complex"));
10386 if (inst
.reloc
.exp
.X_add_number
!= 0)
10388 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10389 inst
.instruction
|= 0x00200000; /* sh bit */
10391 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10392 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10394 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10401 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10402 inst
.instruction
|= inst
.operands
[1].imm
;
10403 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10406 /* Neon instruction encoder helpers. */
10408 /* Encodings for the different types for various Neon opcodes. */
10410 /* An "invalid" code for the following tables. */
10413 struct neon_tab_entry
10416 unsigned float_or_poly
;
10417 unsigned scalar_or_imm
;
10420 /* Map overloaded Neon opcodes to their respective encodings. */
10421 #define NEON_ENC_TAB \
10422 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10423 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10424 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10425 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10426 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10427 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10428 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10429 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10430 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10431 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10432 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10433 /* Register variants of the following two instructions are encoded as
10434 vcge / vcgt with the operands reversed. */ \
10435 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10436 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10437 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10438 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10439 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10440 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10441 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10442 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10443 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10444 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10445 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10446 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10447 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10448 X(vshl, 0x0000400, N_INV, 0x0800510), \
10449 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10450 X(vand, 0x0000110, N_INV, 0x0800030), \
10451 X(vbic, 0x0100110, N_INV, 0x0800030), \
10452 X(veor, 0x1000110, N_INV, N_INV), \
10453 X(vorn, 0x0300110, N_INV, 0x0800010), \
10454 X(vorr, 0x0200110, N_INV, 0x0800010), \
10455 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10456 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10457 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10458 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10459 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10460 X(vst1, 0x0000000, 0x0800000, N_INV), \
10461 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10462 X(vst2, 0x0000100, 0x0800100, N_INV), \
10463 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10464 X(vst3, 0x0000200, 0x0800200, N_INV), \
10465 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10466 X(vst4, 0x0000300, 0x0800300, N_INV), \
10467 X(vmovn, 0x1b20200, N_INV, N_INV), \
10468 X(vtrn, 0x1b20080, N_INV, N_INV), \
10469 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10470 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10471 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10472 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10473 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10474 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10475 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10476 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10477 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10481 #define X(OPC,I,F,S) N_MNEM_##OPC
10486 static const struct neon_tab_entry neon_enc_tab
[] =
10488 #define X(OPC,I,F,S) { (I), (F), (S) }
10493 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10494 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10495 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10496 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10497 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10498 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10499 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10500 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10501 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10502 #define NEON_ENC_SINGLE(X) \
10503 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10504 #define NEON_ENC_DOUBLE(X) \
10505 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10507 /* Define shapes for instruction operands. The following mnemonic characters
10508 are used in this table:
10510 F - VFP S<n> register
10511 D - Neon D<n> register
10512 Q - Neon Q<n> register
10516 L - D<n> register list
10518 This table is used to generate various data:
10519 - enumerations of the form NS_DDR to be used as arguments to
10521 - a table classifying shapes into single, double, quad, mixed.
10522 - a table used to drive neon_select_shape. */
10524 #define NEON_SHAPE_DEF \
10525 X(3, (D, D, D), DOUBLE), \
10526 X(3, (Q, Q, Q), QUAD), \
10527 X(3, (D, D, I), DOUBLE), \
10528 X(3, (Q, Q, I), QUAD), \
10529 X(3, (D, D, S), DOUBLE), \
10530 X(3, (Q, Q, S), QUAD), \
10531 X(2, (D, D), DOUBLE), \
10532 X(2, (Q, Q), QUAD), \
10533 X(2, (D, S), DOUBLE), \
10534 X(2, (Q, S), QUAD), \
10535 X(2, (D, R), DOUBLE), \
10536 X(2, (Q, R), QUAD), \
10537 X(2, (D, I), DOUBLE), \
10538 X(2, (Q, I), QUAD), \
10539 X(3, (D, L, D), DOUBLE), \
10540 X(2, (D, Q), MIXED), \
10541 X(2, (Q, D), MIXED), \
10542 X(3, (D, Q, I), MIXED), \
10543 X(3, (Q, D, I), MIXED), \
10544 X(3, (Q, D, D), MIXED), \
10545 X(3, (D, Q, Q), MIXED), \
10546 X(3, (Q, Q, D), MIXED), \
10547 X(3, (Q, D, S), MIXED), \
10548 X(3, (D, Q, S), MIXED), \
10549 X(4, (D, D, D, I), DOUBLE), \
10550 X(4, (Q, Q, Q, I), QUAD), \
10551 X(2, (F, F), SINGLE), \
10552 X(3, (F, F, F), SINGLE), \
10553 X(2, (F, I), SINGLE), \
10554 X(2, (F, D), MIXED), \
10555 X(2, (D, F), MIXED), \
10556 X(3, (F, F, I), MIXED), \
10557 X(4, (R, R, F, F), SINGLE), \
10558 X(4, (F, F, R, R), SINGLE), \
10559 X(3, (D, R, R), DOUBLE), \
10560 X(3, (R, R, D), DOUBLE), \
10561 X(2, (S, R), SINGLE), \
10562 X(2, (R, S), SINGLE), \
10563 X(2, (F, R), SINGLE), \
10564 X(2, (R, F), SINGLE)
10566 #define S2(A,B) NS_##A##B
10567 #define S3(A,B,C) NS_##A##B##C
10568 #define S4(A,B,C,D) NS_##A##B##C##D
10570 #define X(N, L, C) S##N L
10583 enum neon_shape_class
10591 #define X(N, L, C) SC_##C
10593 static enum neon_shape_class neon_shape_class
[] =
10611 /* Register widths of above. */
10612 static unsigned neon_shape_el_size
[] =
10623 struct neon_shape_info
10626 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10629 #define S2(A,B) { SE_##A, SE_##B }
10630 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10631 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10633 #define X(N, L, C) { N, S##N L }
10635 static struct neon_shape_info neon_shape_tab
[] =
10645 /* Bit masks used in type checking given instructions.
10646 'N_EQK' means the type must be the same as (or based on in some way) the key
10647 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10648 set, various other bits can be set as well in order to modify the meaning of
10649 the type constraint. */
10651 enum neon_type_mask
10673 N_KEY
= 0x100000, /* key element (main type specifier). */
10674 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10675 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10676 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10677 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10678 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10679 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10680 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10681 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10682 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10684 N_MAX_NONSPECIAL
= N_F64
10687 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10689 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10690 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10691 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10692 #define N_SUF_32 (N_SU_32 | N_F32)
10693 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10694 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10696 /* Pass this as the first type argument to neon_check_type to ignore types
10698 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10700 /* Select a "shape" for the current instruction (describing register types or
10701 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10702 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10703 function of operand parsing, so this function doesn't need to be called.
10704 Shapes should be listed in order of decreasing length. */
10706 static enum neon_shape
10707 neon_select_shape (enum neon_shape shape
, ...)
10710 enum neon_shape first_shape
= shape
;
10712 /* Fix missing optional operands. FIXME: we don't know at this point how
10713 many arguments we should have, so this makes the assumption that we have
10714 > 1. This is true of all current Neon opcodes, I think, but may not be
10715 true in the future. */
10716 if (!inst
.operands
[1].present
)
10717 inst
.operands
[1] = inst
.operands
[0];
10719 va_start (ap
, shape
);
10721 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10726 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10728 if (!inst
.operands
[j
].present
)
10734 switch (neon_shape_tab
[shape
].el
[j
])
10737 if (!(inst
.operands
[j
].isreg
10738 && inst
.operands
[j
].isvec
10739 && inst
.operands
[j
].issingle
10740 && !inst
.operands
[j
].isquad
))
10745 if (!(inst
.operands
[j
].isreg
10746 && inst
.operands
[j
].isvec
10747 && !inst
.operands
[j
].isquad
10748 && !inst
.operands
[j
].issingle
))
10753 if (!(inst
.operands
[j
].isreg
10754 && !inst
.operands
[j
].isvec
))
10759 if (!(inst
.operands
[j
].isreg
10760 && inst
.operands
[j
].isvec
10761 && inst
.operands
[j
].isquad
10762 && !inst
.operands
[j
].issingle
))
10767 if (!(!inst
.operands
[j
].isreg
10768 && !inst
.operands
[j
].isscalar
))
10773 if (!(!inst
.operands
[j
].isreg
10774 && inst
.operands
[j
].isscalar
))
10788 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10789 first_error (_("invalid instruction shape"));
10794 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10795 means the Q bit should be set). */
10798 neon_quad (enum neon_shape shape
)
10800 return neon_shape_class
[shape
] == SC_QUAD
;
10804 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10807 /* Allow modification to be made to types which are constrained to be
10808 based on the key element, based on bits set alongside N_EQK. */
10809 if ((typebits
& N_EQK
) != 0)
10811 if ((typebits
& N_HLF
) != 0)
10813 else if ((typebits
& N_DBL
) != 0)
10815 if ((typebits
& N_SGN
) != 0)
10816 *g_type
= NT_signed
;
10817 else if ((typebits
& N_UNS
) != 0)
10818 *g_type
= NT_unsigned
;
10819 else if ((typebits
& N_INT
) != 0)
10820 *g_type
= NT_integer
;
10821 else if ((typebits
& N_FLT
) != 0)
10822 *g_type
= NT_float
;
10823 else if ((typebits
& N_SIZ
) != 0)
10824 *g_type
= NT_untyped
;
10828 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10829 operand type, i.e. the single type specified in a Neon instruction when it
10830 is the only one given. */
10832 static struct neon_type_el
10833 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10835 struct neon_type_el dest
= *key
;
10837 assert ((thisarg
& N_EQK
) != 0);
10839 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10844 /* Convert Neon type and size into compact bitmask representation. */
10846 static enum neon_type_mask
10847 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10854 case 8: return N_8
;
10855 case 16: return N_16
;
10856 case 32: return N_32
;
10857 case 64: return N_64
;
10865 case 8: return N_I8
;
10866 case 16: return N_I16
;
10867 case 32: return N_I32
;
10868 case 64: return N_I64
;
10876 case 32: return N_F32
;
10877 case 64: return N_F64
;
10885 case 8: return N_P8
;
10886 case 16: return N_P16
;
10894 case 8: return N_S8
;
10895 case 16: return N_S16
;
10896 case 32: return N_S32
;
10897 case 64: return N_S64
;
10905 case 8: return N_U8
;
10906 case 16: return N_U16
;
10907 case 32: return N_U32
;
10908 case 64: return N_U64
;
10919 /* Convert compact Neon bitmask type representation to a type and size. Only
10920 handles the case where a single bit is set in the mask. */
10923 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10924 enum neon_type_mask mask
)
10926 if ((mask
& N_EQK
) != 0)
10929 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10931 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10933 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10935 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10940 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10942 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10943 *type
= NT_unsigned
;
10944 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10945 *type
= NT_integer
;
10946 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10947 *type
= NT_untyped
;
10948 else if ((mask
& (N_P8
| N_P16
)) != 0)
10950 else if ((mask
& (N_F32
| N_F64
)) != 0)
10958 /* Modify a bitmask of allowed types. This is only needed for type
10962 modify_types_allowed (unsigned allowed
, unsigned mods
)
10965 enum neon_el_type type
;
10971 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10973 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10975 neon_modify_type_size (mods
, &type
, &size
);
10976 destmask
|= type_chk_of_el_type (type
, size
);
10983 /* Check type and return type classification.
10984 The manual states (paraphrase): If one datatype is given, it indicates the
10986 - the second operand, if there is one
10987 - the operand, if there is no second operand
10988 - the result, if there are no operands.
10989 This isn't quite good enough though, so we use a concept of a "key" datatype
10990 which is set on a per-instruction basis, which is the one which matters when
10991 only one data type is written.
10992 Note: this function has side-effects (e.g. filling in missing operands). All
10993 Neon instructions should call it before performing bit encoding. */
10995 static struct neon_type_el
10996 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10999 unsigned i
, pass
, key_el
= 0;
11000 unsigned types
[NEON_MAX_TYPE_ELS
];
11001 enum neon_el_type k_type
= NT_invtype
;
11002 unsigned k_size
= -1u;
11003 struct neon_type_el badtype
= {NT_invtype
, -1};
11004 unsigned key_allowed
= 0;
11006 /* Optional registers in Neon instructions are always (not) in operand 1.
11007 Fill in the missing operand here, if it was omitted. */
11008 if (els
> 1 && !inst
.operands
[1].present
)
11009 inst
.operands
[1] = inst
.operands
[0];
11011 /* Suck up all the varargs. */
11013 for (i
= 0; i
< els
; i
++)
11015 unsigned thisarg
= va_arg (ap
, unsigned);
11016 if (thisarg
== N_IGNORE_TYPE
)
11021 types
[i
] = thisarg
;
11022 if ((thisarg
& N_KEY
) != 0)
11027 if (inst
.vectype
.elems
> 0)
11028 for (i
= 0; i
< els
; i
++)
11029 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11031 first_error (_("types specified in both the mnemonic and operands"));
11035 /* Duplicate inst.vectype elements here as necessary.
11036 FIXME: No idea if this is exactly the same as the ARM assembler,
11037 particularly when an insn takes one register and one non-register
11039 if (inst
.vectype
.elems
== 1 && els
> 1)
11042 inst
.vectype
.elems
= els
;
11043 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11044 for (j
= 0; j
< els
; j
++)
11046 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11049 else if (inst
.vectype
.elems
== 0 && els
> 0)
11052 /* No types were given after the mnemonic, so look for types specified
11053 after each operand. We allow some flexibility here; as long as the
11054 "key" operand has a type, we can infer the others. */
11055 for (j
= 0; j
< els
; j
++)
11056 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11057 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11059 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11061 for (j
= 0; j
< els
; j
++)
11062 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11063 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11068 first_error (_("operand types can't be inferred"));
11072 else if (inst
.vectype
.elems
!= els
)
11074 first_error (_("type specifier has the wrong number of parts"));
11078 for (pass
= 0; pass
< 2; pass
++)
11080 for (i
= 0; i
< els
; i
++)
11082 unsigned thisarg
= types
[i
];
11083 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11084 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11085 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11086 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11088 /* Decay more-specific signed & unsigned types to sign-insensitive
11089 integer types if sign-specific variants are unavailable. */
11090 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11091 && (types_allowed
& N_SU_ALL
) == 0)
11092 g_type
= NT_integer
;
11094 /* If only untyped args are allowed, decay any more specific types to
11095 them. Some instructions only care about signs for some element
11096 sizes, so handle that properly. */
11097 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11098 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11099 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11100 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11101 g_type
= NT_untyped
;
11105 if ((thisarg
& N_KEY
) != 0)
11109 key_allowed
= thisarg
& ~N_KEY
;
11114 if ((thisarg
& N_VFP
) != 0)
11116 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11117 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11119 /* In VFP mode, operands must match register widths. If we
11120 have a key operand, use its width, else use the width of
11121 the current operand. */
11127 if (regwidth
!= match
)
11129 first_error (_("operand size must match register width"));
11134 if ((thisarg
& N_EQK
) == 0)
11136 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11138 if ((given_type
& types_allowed
) == 0)
11140 first_error (_("bad type in Neon instruction"));
11146 enum neon_el_type mod_k_type
= k_type
;
11147 unsigned mod_k_size
= k_size
;
11148 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11149 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11151 first_error (_("inconsistent types in Neon instruction"));
11159 return inst
.vectype
.el
[key_el
];
11162 /* Neon-style VFP instruction forwarding. */
11164 /* Thumb VFP instructions have 0xE in the condition field. */
11167 do_vfp_cond_or_thumb (void)
11170 inst
.instruction
|= 0xe0000000;
11172 inst
.instruction
|= inst
.cond
<< 28;
11175 /* Look up and encode a simple mnemonic, for use as a helper function for the
11176 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11177 etc. It is assumed that operand parsing has already been done, and that the
11178 operands are in the form expected by the given opcode (this isn't necessarily
11179 the same as the form in which they were parsed, hence some massaging must
11180 take place before this function is called).
11181 Checks current arch version against that in the looked-up opcode. */
11184 do_vfp_nsyn_opcode (const char *opname
)
11186 const struct asm_opcode
*opcode
;
11188 opcode
= hash_find (arm_ops_hsh
, opname
);
11193 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11194 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11199 inst
.instruction
= opcode
->tvalue
;
11200 opcode
->tencode ();
11204 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11205 opcode
->aencode ();
11210 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11212 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11217 do_vfp_nsyn_opcode ("fadds");
11219 do_vfp_nsyn_opcode ("fsubs");
11224 do_vfp_nsyn_opcode ("faddd");
11226 do_vfp_nsyn_opcode ("fsubd");
11230 /* Check operand types to see if this is a VFP instruction, and if so call
11234 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11236 enum neon_shape rs
;
11237 struct neon_type_el et
;
11242 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11243 et
= neon_check_type (2, rs
,
11244 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11248 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11249 et
= neon_check_type (3, rs
,
11250 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11257 if (et
.type
!= NT_invtype
)
11269 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11271 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11276 do_vfp_nsyn_opcode ("fmacs");
11278 do_vfp_nsyn_opcode ("fmscs");
11283 do_vfp_nsyn_opcode ("fmacd");
11285 do_vfp_nsyn_opcode ("fmscd");
11290 do_vfp_nsyn_mul (enum neon_shape rs
)
11293 do_vfp_nsyn_opcode ("fmuls");
11295 do_vfp_nsyn_opcode ("fmuld");
11299 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11301 int is_neg
= (inst
.instruction
& 0x80) != 0;
11302 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11307 do_vfp_nsyn_opcode ("fnegs");
11309 do_vfp_nsyn_opcode ("fabss");
11314 do_vfp_nsyn_opcode ("fnegd");
11316 do_vfp_nsyn_opcode ("fabsd");
11320 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11321 insns belong to Neon, and are handled elsewhere. */
11324 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11326 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11330 do_vfp_nsyn_opcode ("fldmdbs");
11332 do_vfp_nsyn_opcode ("fldmias");
11337 do_vfp_nsyn_opcode ("fstmdbs");
11339 do_vfp_nsyn_opcode ("fstmias");
11344 do_vfp_nsyn_sqrt (void)
11346 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11347 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11350 do_vfp_nsyn_opcode ("fsqrts");
11352 do_vfp_nsyn_opcode ("fsqrtd");
11356 do_vfp_nsyn_div (void)
11358 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11359 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11360 N_F32
| N_F64
| N_KEY
| N_VFP
);
11363 do_vfp_nsyn_opcode ("fdivs");
11365 do_vfp_nsyn_opcode ("fdivd");
11369 do_vfp_nsyn_nmul (void)
11371 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11372 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11373 N_F32
| N_F64
| N_KEY
| N_VFP
);
11377 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11378 do_vfp_sp_dyadic ();
11382 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11383 do_vfp_dp_rd_rn_rm ();
11385 do_vfp_cond_or_thumb ();
11389 do_vfp_nsyn_cmp (void)
11391 if (inst
.operands
[1].isreg
)
11393 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11394 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11398 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11399 do_vfp_sp_monadic ();
11403 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11404 do_vfp_dp_rd_rm ();
11409 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11410 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11412 switch (inst
.instruction
& 0x0fffffff)
11415 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11418 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11426 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11427 do_vfp_sp_compare_z ();
11431 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11435 do_vfp_cond_or_thumb ();
11439 nsyn_insert_sp (void)
11441 inst
.operands
[1] = inst
.operands
[0];
11442 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11443 inst
.operands
[0].reg
= 13;
11444 inst
.operands
[0].isreg
= 1;
11445 inst
.operands
[0].writeback
= 1;
11446 inst
.operands
[0].present
= 1;
11450 do_vfp_nsyn_push (void)
11453 if (inst
.operands
[1].issingle
)
11454 do_vfp_nsyn_opcode ("fstmdbs");
11456 do_vfp_nsyn_opcode ("fstmdbd");
11460 do_vfp_nsyn_pop (void)
11463 if (inst
.operands
[1].issingle
)
11464 do_vfp_nsyn_opcode ("fldmias");
11466 do_vfp_nsyn_opcode ("fldmiad");
11469 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11470 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11473 neon_dp_fixup (unsigned i
)
11477 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11491 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11495 neon_logbits (unsigned x
)
11497 return ffs (x
) - 4;
11500 #define LOW4(R) ((R) & 0xf)
11501 #define HI1(R) (((R) >> 4) & 1)
11503 /* Encode insns with bit pattern:
11505 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11506 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11508 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11509 different meaning for some instruction. */
11512 neon_three_same (int isquad
, int ubit
, int size
)
11514 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11515 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11516 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11517 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11518 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11519 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11520 inst
.instruction
|= (isquad
!= 0) << 6;
11521 inst
.instruction
|= (ubit
!= 0) << 24;
11523 inst
.instruction
|= neon_logbits (size
) << 20;
11525 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11528 /* Encode instructions of the form:
11530 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11531 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11533 Don't write size if SIZE == -1. */
11536 neon_two_same (int qbit
, int ubit
, int size
)
11538 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11539 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11540 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11541 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11542 inst
.instruction
|= (qbit
!= 0) << 6;
11543 inst
.instruction
|= (ubit
!= 0) << 24;
11546 inst
.instruction
|= neon_logbits (size
) << 18;
11548 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11551 /* Neon instruction encoders, in approximate order of appearance. */
11554 do_neon_dyadic_i_su (void)
11556 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11557 struct neon_type_el et
= neon_check_type (3, rs
,
11558 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11559 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11563 do_neon_dyadic_i64_su (void)
11565 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11566 struct neon_type_el et
= neon_check_type (3, rs
,
11567 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11568 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11572 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11575 unsigned size
= et
.size
>> 3;
11576 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11577 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11578 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11579 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11580 inst
.instruction
|= (isquad
!= 0) << 6;
11581 inst
.instruction
|= immbits
<< 16;
11582 inst
.instruction
|= (size
>> 3) << 7;
11583 inst
.instruction
|= (size
& 0x7) << 19;
11585 inst
.instruction
|= (uval
!= 0) << 24;
11587 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11591 do_neon_shl_imm (void)
11593 if (!inst
.operands
[2].isreg
)
11595 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11596 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11597 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11598 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11602 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11603 struct neon_type_el et
= neon_check_type (3, rs
,
11604 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11607 /* VSHL/VQSHL 3-register variants have syntax such as:
11609 whereas other 3-register operations encoded by neon_three_same have
11612 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11614 tmp
= inst
.operands
[2].reg
;
11615 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11616 inst
.operands
[1].reg
= tmp
;
11617 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11618 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11623 do_neon_qshl_imm (void)
11625 if (!inst
.operands
[2].isreg
)
11627 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11628 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11630 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11631 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11632 inst
.operands
[2].imm
);
11636 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11637 struct neon_type_el et
= neon_check_type (3, rs
,
11638 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11641 /* See note in do_neon_shl_imm. */
11642 tmp
= inst
.operands
[2].reg
;
11643 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11644 inst
.operands
[1].reg
= tmp
;
11645 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11646 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11651 do_neon_rshl (void)
11653 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11654 struct neon_type_el et
= neon_check_type (3, rs
,
11655 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11658 tmp
= inst
.operands
[2].reg
;
11659 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11660 inst
.operands
[1].reg
= tmp
;
11661 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11665 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11667 /* Handle .I8 pseudo-instructions. */
11670 /* Unfortunately, this will make everything apart from zero out-of-range.
11671 FIXME is this the intended semantics? There doesn't seem much point in
11672 accepting .I8 if so. */
11673 immediate
|= immediate
<< 8;
11679 if (immediate
== (immediate
& 0x000000ff))
11681 *immbits
= immediate
;
11684 else if (immediate
== (immediate
& 0x0000ff00))
11686 *immbits
= immediate
>> 8;
11689 else if (immediate
== (immediate
& 0x00ff0000))
11691 *immbits
= immediate
>> 16;
11694 else if (immediate
== (immediate
& 0xff000000))
11696 *immbits
= immediate
>> 24;
11699 if ((immediate
& 0xffff) != (immediate
>> 16))
11700 goto bad_immediate
;
11701 immediate
&= 0xffff;
11704 if (immediate
== (immediate
& 0x000000ff))
11706 *immbits
= immediate
;
11709 else if (immediate
== (immediate
& 0x0000ff00))
11711 *immbits
= immediate
>> 8;
11716 first_error (_("immediate value out of range"));
11720 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11724 neon_bits_same_in_bytes (unsigned imm
)
11726 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11727 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11728 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11729 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11732 /* For immediate of above form, return 0bABCD. */
11735 neon_squash_bits (unsigned imm
)
11737 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11738 | ((imm
& 0x01000000) >> 21);
11741 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11744 neon_qfloat_bits (unsigned imm
)
11746 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11749 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11750 the instruction. *OP is passed as the initial value of the op field, and
11751 may be set to a different value depending on the constant (i.e.
11752 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11753 MVN). If the immediate looks like a repeated pattern then also
11754 try smaller element sizes. */
11757 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
11758 unsigned *immbits
, int *op
, int size
,
11759 enum neon_el_type type
)
11761 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11763 if (type
== NT_float
&& !float_p
)
11766 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11768 if (size
!= 32 || *op
== 1)
11770 *immbits
= neon_qfloat_bits (immlo
);
11776 if (neon_bits_same_in_bytes (immhi
)
11777 && neon_bits_same_in_bytes (immlo
))
11781 *immbits
= (neon_squash_bits (immhi
) << 4)
11782 | neon_squash_bits (immlo
);
11787 if (immhi
!= immlo
)
11793 if (immlo
== (immlo
& 0x000000ff))
11798 else if (immlo
== (immlo
& 0x0000ff00))
11800 *immbits
= immlo
>> 8;
11803 else if (immlo
== (immlo
& 0x00ff0000))
11805 *immbits
= immlo
>> 16;
11808 else if (immlo
== (immlo
& 0xff000000))
11810 *immbits
= immlo
>> 24;
11813 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11815 *immbits
= (immlo
>> 8) & 0xff;
11818 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11820 *immbits
= (immlo
>> 16) & 0xff;
11824 if ((immlo
& 0xffff) != (immlo
>> 16))
11831 if (immlo
== (immlo
& 0x000000ff))
11836 else if (immlo
== (immlo
& 0x0000ff00))
11838 *immbits
= immlo
>> 8;
11842 if ((immlo
& 0xff) != (immlo
>> 8))
11847 if (immlo
== (immlo
& 0x000000ff))
11849 /* Don't allow MVN with 8-bit immediate. */
11859 /* Write immediate bits [7:0] to the following locations:
11861 |28/24|23 19|18 16|15 4|3 0|
11862 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11864 This function is used by VMOV/VMVN/VORR/VBIC. */
11867 neon_write_immbits (unsigned immbits
)
11869 inst
.instruction
|= immbits
& 0xf;
11870 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11871 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11874 /* Invert low-order SIZE bits of XHI:XLO. */
11877 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11879 unsigned immlo
= xlo
? *xlo
: 0;
11880 unsigned immhi
= xhi
? *xhi
: 0;
11885 immlo
= (~immlo
) & 0xff;
11889 immlo
= (~immlo
) & 0xffff;
11893 immhi
= (~immhi
) & 0xffffffff;
11894 /* fall through. */
11897 immlo
= (~immlo
) & 0xffffffff;
11912 do_neon_logic (void)
11914 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11916 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11917 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11918 /* U bit and size field were set as part of the bitmask. */
11919 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11920 neon_three_same (neon_quad (rs
), 0, -1);
11924 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11925 struct neon_type_el et
= neon_check_type (2, rs
,
11926 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11927 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11931 if (et
.type
== NT_invtype
)
11934 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11936 immbits
= inst
.operands
[1].imm
;
11939 /* .i64 is a pseudo-op, so the immediate must be a repeating
11941 if (immbits
!= (inst
.operands
[1].regisimm
?
11942 inst
.operands
[1].reg
: 0))
11944 /* Set immbits to an invalid constant. */
11945 immbits
= 0xdeadbeef;
11952 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11956 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11960 /* Pseudo-instruction for VBIC. */
11961 neon_invert_size (&immbits
, 0, et
.size
);
11962 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11966 /* Pseudo-instruction for VORR. */
11967 neon_invert_size (&immbits
, 0, et
.size
);
11968 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11978 inst
.instruction
|= neon_quad (rs
) << 6;
11979 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11980 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11981 inst
.instruction
|= cmode
<< 8;
11982 neon_write_immbits (immbits
);
11984 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11989 do_neon_bitfield (void)
11991 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11992 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11993 neon_three_same (neon_quad (rs
), 0, -1);
11997 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12000 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12001 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12003 if (et
.type
== NT_float
)
12005 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12006 neon_three_same (neon_quad (rs
), 0, -1);
12010 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12011 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12016 do_neon_dyadic_if_su (void)
12018 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12022 do_neon_dyadic_if_su_d (void)
12024 /* This version only allow D registers, but that constraint is enforced during
12025 operand parsing so we don't need to do anything extra here. */
12026 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12030 do_neon_dyadic_if_i_d (void)
12032 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12033 affected if we specify unsigned args. */
12034 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12037 enum vfp_or_neon_is_neon_bits
12040 NEON_CHECK_ARCH
= 2
12043 /* Call this function if an instruction which may have belonged to the VFP or
12044 Neon instruction sets, but turned out to be a Neon instruction (due to the
12045 operand types involved, etc.). We have to check and/or fix-up a couple of
12048 - Make sure the user hasn't attempted to make a Neon instruction
12050 - Alter the value in the condition code field if necessary.
12051 - Make sure that the arch supports Neon instructions.
12053 Which of these operations take place depends on bits from enum
12054 vfp_or_neon_is_neon_bits.
12056 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12057 current instruction's condition is COND_ALWAYS, the condition field is
12058 changed to inst.uncond_value. This is necessary because instructions shared
12059 between VFP and Neon may be conditional for the VFP variants only, and the
12060 unconditional Neon version must have, e.g., 0xF in the condition field. */
12063 vfp_or_neon_is_neon (unsigned check
)
12065 /* Conditions are always legal in Thumb mode (IT blocks). */
12066 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12068 if (inst
.cond
!= COND_ALWAYS
)
12070 first_error (_(BAD_COND
));
12073 if (inst
.uncond_value
!= -1)
12074 inst
.instruction
|= inst
.uncond_value
<< 28;
12077 if ((check
& NEON_CHECK_ARCH
)
12078 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12080 first_error (_(BAD_FPU
));
12088 do_neon_addsub_if_i (void)
12090 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12093 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12096 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12097 affected if we specify unsigned args. */
12098 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12101 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12103 V<op> A,B (A is operand 0, B is operand 2)
12108 so handle that case specially. */
12111 neon_exchange_operands (void)
12113 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12114 if (inst
.operands
[1].present
)
12116 /* Swap operands[1] and operands[2]. */
12117 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12118 inst
.operands
[1] = inst
.operands
[2];
12119 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12123 inst
.operands
[1] = inst
.operands
[2];
12124 inst
.operands
[2] = inst
.operands
[0];
12129 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12131 if (inst
.operands
[2].isreg
)
12134 neon_exchange_operands ();
12135 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12139 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12140 struct neon_type_el et
= neon_check_type (2, rs
,
12141 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12143 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12144 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12145 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12146 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12147 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12148 inst
.instruction
|= neon_quad (rs
) << 6;
12149 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12150 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12152 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12159 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12163 do_neon_cmp_inv (void)
12165 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12171 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12174 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12175 scalars, which are encoded in 5 bits, M : Rm.
12176 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12177 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12181 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12183 unsigned regno
= NEON_SCALAR_REG (scalar
);
12184 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12189 if (regno
> 7 || elno
> 3)
12191 return regno
| (elno
<< 3);
12194 if (regno
> 15 || elno
> 1)
12196 return regno
| (elno
<< 4);
12200 first_error (_("scalar out of range for multiply instruction"));
12206 /* Encode multiply / multiply-accumulate scalar instructions. */
12209 neon_mul_mac (struct neon_type_el et
, int ubit
)
12213 /* Give a more helpful error message if we have an invalid type. */
12214 if (et
.type
== NT_invtype
)
12217 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12218 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12219 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12220 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12221 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12222 inst
.instruction
|= LOW4 (scalar
);
12223 inst
.instruction
|= HI1 (scalar
) << 5;
12224 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12225 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12226 inst
.instruction
|= (ubit
!= 0) << 24;
12228 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12232 do_neon_mac_maybe_scalar (void)
12234 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12237 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12240 if (inst
.operands
[2].isscalar
)
12242 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12243 struct neon_type_el et
= neon_check_type (3, rs
,
12244 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12245 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12246 neon_mul_mac (et
, neon_quad (rs
));
12250 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12251 affected if we specify unsigned args. */
12252 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12259 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12260 struct neon_type_el et
= neon_check_type (3, rs
,
12261 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12262 neon_three_same (neon_quad (rs
), 0, et
.size
);
12265 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12266 same types as the MAC equivalents. The polynomial type for this instruction
12267 is encoded the same as the integer type. */
12272 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12275 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12278 if (inst
.operands
[2].isscalar
)
12279 do_neon_mac_maybe_scalar ();
12281 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12285 do_neon_qdmulh (void)
12287 if (inst
.operands
[2].isscalar
)
12289 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12290 struct neon_type_el et
= neon_check_type (3, rs
,
12291 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12292 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12293 neon_mul_mac (et
, neon_quad (rs
));
12297 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12298 struct neon_type_el et
= neon_check_type (3, rs
,
12299 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12300 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12301 /* The U bit (rounding) comes from bit mask. */
12302 neon_three_same (neon_quad (rs
), 0, et
.size
);
12307 do_neon_fcmp_absolute (void)
12309 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12310 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12311 /* Size field comes from bit mask. */
12312 neon_three_same (neon_quad (rs
), 1, -1);
12316 do_neon_fcmp_absolute_inv (void)
12318 neon_exchange_operands ();
12319 do_neon_fcmp_absolute ();
12323 do_neon_step (void)
12325 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12326 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12327 neon_three_same (neon_quad (rs
), 0, -1);
12331 do_neon_abs_neg (void)
12333 enum neon_shape rs
;
12334 struct neon_type_el et
;
12336 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12339 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12342 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12343 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12345 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12346 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12347 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12348 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12349 inst
.instruction
|= neon_quad (rs
) << 6;
12350 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12351 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12353 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12359 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12360 struct neon_type_el et
= neon_check_type (2, rs
,
12361 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12362 int imm
= inst
.operands
[2].imm
;
12363 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12364 _("immediate out of range for insert"));
12365 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12371 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12372 struct neon_type_el et
= neon_check_type (2, rs
,
12373 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12374 int imm
= inst
.operands
[2].imm
;
12375 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12376 _("immediate out of range for insert"));
12377 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12381 do_neon_qshlu_imm (void)
12383 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12384 struct neon_type_el et
= neon_check_type (2, rs
,
12385 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12386 int imm
= inst
.operands
[2].imm
;
12387 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12388 _("immediate out of range for shift"));
12389 /* Only encodes the 'U present' variant of the instruction.
12390 In this case, signed types have OP (bit 8) set to 0.
12391 Unsigned types have OP set to 1. */
12392 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12393 /* The rest of the bits are the same as other immediate shifts. */
12394 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12398 do_neon_qmovn (void)
12400 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12401 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12402 /* Saturating move where operands can be signed or unsigned, and the
12403 destination has the same signedness. */
12404 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12405 if (et
.type
== NT_unsigned
)
12406 inst
.instruction
|= 0xc0;
12408 inst
.instruction
|= 0x80;
12409 neon_two_same (0, 1, et
.size
/ 2);
12413 do_neon_qmovun (void)
12415 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12416 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12417 /* Saturating move with unsigned results. Operands must be signed. */
12418 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12419 neon_two_same (0, 1, et
.size
/ 2);
12423 do_neon_rshift_sat_narrow (void)
12425 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12426 or unsigned. If operands are unsigned, results must also be unsigned. */
12427 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12428 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12429 int imm
= inst
.operands
[2].imm
;
12430 /* This gets the bounds check, size encoding and immediate bits calculation
12434 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12435 VQMOVN.I<size> <Dd>, <Qm>. */
12438 inst
.operands
[2].present
= 0;
12439 inst
.instruction
= N_MNEM_vqmovn
;
12444 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12445 _("immediate out of range"));
12446 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12450 do_neon_rshift_sat_narrow_u (void)
12452 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12453 or unsigned. If operands are unsigned, results must also be unsigned. */
12454 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12455 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12456 int imm
= inst
.operands
[2].imm
;
12457 /* This gets the bounds check, size encoding and immediate bits calculation
12461 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12462 VQMOVUN.I<size> <Dd>, <Qm>. */
12465 inst
.operands
[2].present
= 0;
12466 inst
.instruction
= N_MNEM_vqmovun
;
12471 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12472 _("immediate out of range"));
12473 /* FIXME: The manual is kind of unclear about what value U should have in
12474 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12476 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12480 do_neon_movn (void)
12482 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12483 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12484 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12485 neon_two_same (0, 1, et
.size
/ 2);
12489 do_neon_rshift_narrow (void)
12491 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12492 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12493 int imm
= inst
.operands
[2].imm
;
12494 /* This gets the bounds check, size encoding and immediate bits calculation
12498 /* If immediate is zero then we are a pseudo-instruction for
12499 VMOVN.I<size> <Dd>, <Qm> */
12502 inst
.operands
[2].present
= 0;
12503 inst
.instruction
= N_MNEM_vmovn
;
12508 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12509 _("immediate out of range for narrowing operation"));
12510 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12514 do_neon_shll (void)
12516 /* FIXME: Type checking when lengthening. */
12517 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12518 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12519 unsigned imm
= inst
.operands
[2].imm
;
12521 if (imm
== et
.size
)
12523 /* Maximum shift variant. */
12524 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12525 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12526 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12527 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12528 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12529 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12531 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12535 /* A more-specific type check for non-max versions. */
12536 et
= neon_check_type (2, NS_QDI
,
12537 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12538 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12539 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12543 /* Check the various types for the VCVT instruction, and return which version
12544 the current instruction is. */
12547 neon_cvt_flavour (enum neon_shape rs
)
12549 #define CVT_VAR(C,X,Y) \
12550 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12551 if (et.type != NT_invtype) \
12553 inst.error = NULL; \
12556 struct neon_type_el et
;
12557 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12558 || rs
== NS_FF
) ? N_VFP
: 0;
12559 /* The instruction versions which take an immediate take one register
12560 argument, which is extended to the width of the full register. Thus the
12561 "source" and "destination" registers must have the same width. Hack that
12562 here by making the size equal to the key (wider, in this case) operand. */
12563 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12565 CVT_VAR (0, N_S32
, N_F32
);
12566 CVT_VAR (1, N_U32
, N_F32
);
12567 CVT_VAR (2, N_F32
, N_S32
);
12568 CVT_VAR (3, N_F32
, N_U32
);
12572 /* VFP instructions. */
12573 CVT_VAR (4, N_F32
, N_F64
);
12574 CVT_VAR (5, N_F64
, N_F32
);
12575 CVT_VAR (6, N_S32
, N_F64
| key
);
12576 CVT_VAR (7, N_U32
, N_F64
| key
);
12577 CVT_VAR (8, N_F64
| key
, N_S32
);
12578 CVT_VAR (9, N_F64
| key
, N_U32
);
12579 /* VFP instructions with bitshift. */
12580 CVT_VAR (10, N_F32
| key
, N_S16
);
12581 CVT_VAR (11, N_F32
| key
, N_U16
);
12582 CVT_VAR (12, N_F64
| key
, N_S16
);
12583 CVT_VAR (13, N_F64
| key
, N_U16
);
12584 CVT_VAR (14, N_S16
, N_F32
| key
);
12585 CVT_VAR (15, N_U16
, N_F32
| key
);
12586 CVT_VAR (16, N_S16
, N_F64
| key
);
12587 CVT_VAR (17, N_U16
, N_F64
| key
);
12593 /* Neon-syntax VFP conversions. */
12596 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12598 const char *opname
= 0;
12600 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12602 /* Conversions with immediate bitshift. */
12603 const char *enc
[] =
12625 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12627 opname
= enc
[flavour
];
12628 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12629 _("operands 0 and 1 must be the same register"));
12630 inst
.operands
[1] = inst
.operands
[2];
12631 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12636 /* Conversions without bitshift. */
12637 const char *enc
[] =
12651 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12652 opname
= enc
[flavour
];
12656 do_vfp_nsyn_opcode (opname
);
12660 do_vfp_nsyn_cvtz (void)
12662 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12663 int flavour
= neon_cvt_flavour (rs
);
12664 const char *enc
[] =
12676 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12677 do_vfp_nsyn_opcode (enc
[flavour
]);
12683 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12684 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12685 int flavour
= neon_cvt_flavour (rs
);
12687 /* VFP rather than Neon conversions. */
12690 do_vfp_nsyn_cvt (rs
, flavour
);
12699 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12702 /* Fixed-point conversion with #0 immediate is encoded as an
12703 integer conversion. */
12704 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12706 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12707 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12708 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12710 inst
.instruction
|= enctab
[flavour
];
12711 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12712 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12713 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12714 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12715 inst
.instruction
|= neon_quad (rs
) << 6;
12716 inst
.instruction
|= 1 << 21;
12717 inst
.instruction
|= immbits
<< 16;
12719 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12727 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12729 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12731 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12735 inst
.instruction
|= enctab
[flavour
];
12737 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12738 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12739 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12740 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12741 inst
.instruction
|= neon_quad (rs
) << 6;
12742 inst
.instruction
|= 2 << 18;
12744 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12749 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12750 do_vfp_nsyn_cvt (rs
, flavour
);
12755 neon_move_immediate (void)
12757 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12758 struct neon_type_el et
= neon_check_type (2, rs
,
12759 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12760 unsigned immlo
, immhi
= 0, immbits
;
12761 int op
, cmode
, float_p
;
12763 constraint (et
.type
== NT_invtype
,
12764 _("operand size must be specified for immediate VMOV"));
12766 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12767 op
= (inst
.instruction
& (1 << 5)) != 0;
12769 immlo
= inst
.operands
[1].imm
;
12770 if (inst
.operands
[1].regisimm
)
12771 immhi
= inst
.operands
[1].reg
;
12773 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12774 _("immediate has bits set outside the operand size"));
12776 float_p
= inst
.operands
[1].immisfloat
;
12778 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
12779 et
.size
, et
.type
)) == FAIL
)
12781 /* Invert relevant bits only. */
12782 neon_invert_size (&immlo
, &immhi
, et
.size
);
12783 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12784 with one or the other; those cases are caught by
12785 neon_cmode_for_move_imm. */
12787 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
12788 &op
, et
.size
, et
.type
)) == FAIL
)
12790 first_error (_("immediate out of range"));
12795 inst
.instruction
&= ~(1 << 5);
12796 inst
.instruction
|= op
<< 5;
12798 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12799 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12800 inst
.instruction
|= neon_quad (rs
) << 6;
12801 inst
.instruction
|= cmode
<< 8;
12803 neon_write_immbits (immbits
);
12809 if (inst
.operands
[1].isreg
)
12811 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12813 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12814 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12815 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12816 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12817 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12818 inst
.instruction
|= neon_quad (rs
) << 6;
12822 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12823 neon_move_immediate ();
12826 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12829 /* Encode instructions of form:
12831 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12832 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
12835 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12837 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12838 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12839 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12840 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12841 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12842 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12843 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12844 inst
.instruction
|= neon_logbits (size
) << 20;
12846 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12850 do_neon_dyadic_long (void)
12852 /* FIXME: Type checking for lengthening op. */
12853 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12854 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12855 neon_mixed_length (et
, et
.size
);
12859 do_neon_abal (void)
12861 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12862 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12863 neon_mixed_length (et
, et
.size
);
12867 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12869 if (inst
.operands
[2].isscalar
)
12871 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12872 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12873 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12874 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12878 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12879 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12880 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12881 neon_mixed_length (et
, et
.size
);
12886 do_neon_mac_maybe_scalar_long (void)
12888 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12892 do_neon_dyadic_wide (void)
12894 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12895 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12896 neon_mixed_length (et
, et
.size
);
12900 do_neon_dyadic_narrow (void)
12902 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12903 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12904 /* Operand sign is unimportant, and the U bit is part of the opcode,
12905 so force the operand type to integer. */
12906 et
.type
= NT_integer
;
12907 neon_mixed_length (et
, et
.size
/ 2);
12911 do_neon_mul_sat_scalar_long (void)
12913 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12917 do_neon_vmull (void)
12919 if (inst
.operands
[2].isscalar
)
12920 do_neon_mac_maybe_scalar_long ();
12923 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12924 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12925 if (et
.type
== NT_poly
)
12926 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12928 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12929 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12930 zero. Should be OK as-is. */
12931 neon_mixed_length (et
, et
.size
);
12938 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12939 struct neon_type_el et
= neon_check_type (3, rs
,
12940 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12941 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12942 constraint (imm
>= (neon_quad (rs
) ? 16 : 8), _("shift out of range"));
12943 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12944 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12945 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12946 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12947 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12948 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12949 inst
.instruction
|= neon_quad (rs
) << 6;
12950 inst
.instruction
|= imm
<< 8;
12952 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12958 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12959 struct neon_type_el et
= neon_check_type (2, rs
,
12960 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12961 unsigned op
= (inst
.instruction
>> 7) & 3;
12962 /* N (width of reversed regions) is encoded as part of the bitmask. We
12963 extract it here to check the elements to be reversed are smaller.
12964 Otherwise we'd get a reserved instruction. */
12965 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12966 assert (elsize
!= 0);
12967 constraint (et
.size
>= elsize
,
12968 _("elements must be smaller than reversal region"));
12969 neon_two_same (neon_quad (rs
), 1, et
.size
);
12975 if (inst
.operands
[1].isscalar
)
12977 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12978 struct neon_type_el et
= neon_check_type (2, rs
,
12979 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12980 unsigned sizebits
= et
.size
>> 3;
12981 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12982 int logsize
= neon_logbits (et
.size
);
12983 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12985 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12988 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12989 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12990 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12991 inst
.instruction
|= LOW4 (dm
);
12992 inst
.instruction
|= HI1 (dm
) << 5;
12993 inst
.instruction
|= neon_quad (rs
) << 6;
12994 inst
.instruction
|= x
<< 17;
12995 inst
.instruction
|= sizebits
<< 16;
12997 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13001 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13002 struct neon_type_el et
= neon_check_type (2, rs
,
13003 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13004 /* Duplicate ARM register to lanes of vector. */
13005 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13008 case 8: inst
.instruction
|= 0x400000; break;
13009 case 16: inst
.instruction
|= 0x000020; break;
13010 case 32: inst
.instruction
|= 0x000000; break;
13013 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13014 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13015 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13016 inst
.instruction
|= neon_quad (rs
) << 21;
13017 /* The encoding for this instruction is identical for the ARM and Thumb
13018 variants, except for the condition field. */
13019 do_vfp_cond_or_thumb ();
13023 /* VMOV has particularly many variations. It can be one of:
13024 0. VMOV<c><q> <Qd>, <Qm>
13025 1. VMOV<c><q> <Dd>, <Dm>
13026 (Register operations, which are VORR with Rm = Rn.)
13027 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13028 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13030 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13031 (ARM register to scalar.)
13032 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13033 (Two ARM registers to vector.)
13034 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13035 (Scalar to ARM register.)
13036 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13037 (Vector to two ARM registers.)
13038 8. VMOV.F32 <Sd>, <Sm>
13039 9. VMOV.F64 <Dd>, <Dm>
13040 (VFP register moves.)
13041 10. VMOV.F32 <Sd>, #imm
13042 11. VMOV.F64 <Dd>, #imm
13043 (VFP float immediate load.)
13044 12. VMOV <Rd>, <Sm>
13045 (VFP single to ARM reg.)
13046 13. VMOV <Sd>, <Rm>
13047 (ARM reg to VFP single.)
13048 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13049 (Two ARM regs to two VFP singles.)
13050 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13051 (Two VFP singles to two ARM regs.)
13053 These cases can be disambiguated using neon_select_shape, except cases 1/9
13054 and 3/11 which depend on the operand type too.
13056 All the encoded bits are hardcoded by this function.
13058 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13059 Cases 5, 7 may be used with VFPv2 and above.
13061 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13062 can specify a type where it doesn't make sense to, and is ignored). */
13067 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13068 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13070 struct neon_type_el et
;
13071 const char *ldconst
= 0;
13075 case NS_DD
: /* case 1/9. */
13076 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13077 /* It is not an error here if no type is given. */
13079 if (et
.type
== NT_float
&& et
.size
== 64)
13081 do_vfp_nsyn_opcode ("fcpyd");
13084 /* fall through. */
13086 case NS_QQ
: /* case 0/1. */
13088 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13090 /* The architecture manual I have doesn't explicitly state which
13091 value the U bit should have for register->register moves, but
13092 the equivalent VORR instruction has U = 0, so do that. */
13093 inst
.instruction
= 0x0200110;
13094 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13095 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13096 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13097 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13098 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13099 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13100 inst
.instruction
|= neon_quad (rs
) << 6;
13102 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13106 case NS_DI
: /* case 3/11. */
13107 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13109 if (et
.type
== NT_float
&& et
.size
== 64)
13111 /* case 11 (fconstd). */
13112 ldconst
= "fconstd";
13113 goto encode_fconstd
;
13115 /* fall through. */
13117 case NS_QI
: /* case 2/3. */
13118 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13120 inst
.instruction
= 0x0800010;
13121 neon_move_immediate ();
13122 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13125 case NS_SR
: /* case 4. */
13127 unsigned bcdebits
= 0;
13128 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13129 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13130 int logsize
= neon_logbits (et
.size
);
13131 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13132 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13134 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13136 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13137 && et
.size
!= 32, _(BAD_FPU
));
13138 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13139 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13143 case 8: bcdebits
= 0x8; break;
13144 case 16: bcdebits
= 0x1; break;
13145 case 32: bcdebits
= 0x0; break;
13149 bcdebits
|= x
<< logsize
;
13151 inst
.instruction
= 0xe000b10;
13152 do_vfp_cond_or_thumb ();
13153 inst
.instruction
|= LOW4 (dn
) << 16;
13154 inst
.instruction
|= HI1 (dn
) << 7;
13155 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13156 inst
.instruction
|= (bcdebits
& 3) << 5;
13157 inst
.instruction
|= (bcdebits
>> 2) << 21;
13161 case NS_DRR
: /* case 5 (fmdrr). */
13162 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13165 inst
.instruction
= 0xc400b10;
13166 do_vfp_cond_or_thumb ();
13167 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13168 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13169 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13170 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13173 case NS_RS
: /* case 6. */
13175 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13176 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13177 unsigned logsize
= neon_logbits (et
.size
);
13178 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13179 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13180 unsigned abcdebits
= 0;
13182 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13184 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13185 && et
.size
!= 32, _(BAD_FPU
));
13186 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13187 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13191 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13192 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13193 case 32: abcdebits
= 0x00; break;
13197 abcdebits
|= x
<< logsize
;
13198 inst
.instruction
= 0xe100b10;
13199 do_vfp_cond_or_thumb ();
13200 inst
.instruction
|= LOW4 (dn
) << 16;
13201 inst
.instruction
|= HI1 (dn
) << 7;
13202 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13203 inst
.instruction
|= (abcdebits
& 3) << 5;
13204 inst
.instruction
|= (abcdebits
>> 2) << 21;
13208 case NS_RRD
: /* case 7 (fmrrd). */
13209 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13212 inst
.instruction
= 0xc500b10;
13213 do_vfp_cond_or_thumb ();
13214 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13215 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13216 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13217 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13220 case NS_FF
: /* case 8 (fcpys). */
13221 do_vfp_nsyn_opcode ("fcpys");
13224 case NS_FI
: /* case 10 (fconsts). */
13225 ldconst
= "fconsts";
13227 if (is_quarter_float (inst
.operands
[1].imm
))
13229 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13230 do_vfp_nsyn_opcode (ldconst
);
13233 first_error (_("immediate out of range"));
13236 case NS_RF
: /* case 12 (fmrs). */
13237 do_vfp_nsyn_opcode ("fmrs");
13240 case NS_FR
: /* case 13 (fmsr). */
13241 do_vfp_nsyn_opcode ("fmsr");
13244 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13245 (one of which is a list), but we have parsed four. Do some fiddling to
13246 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13248 case NS_RRFF
: /* case 14 (fmrrs). */
13249 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13250 _("VFP registers must be adjacent"));
13251 inst
.operands
[2].imm
= 2;
13252 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13253 do_vfp_nsyn_opcode ("fmrrs");
13256 case NS_FFRR
: /* case 15 (fmsrr). */
13257 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13258 _("VFP registers must be adjacent"));
13259 inst
.operands
[1] = inst
.operands
[2];
13260 inst
.operands
[2] = inst
.operands
[3];
13261 inst
.operands
[0].imm
= 2;
13262 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13263 do_vfp_nsyn_opcode ("fmsrr");
13272 do_neon_rshift_round_imm (void)
13274 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13275 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13276 int imm
= inst
.operands
[2].imm
;
13278 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13281 inst
.operands
[2].present
= 0;
13286 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13287 _("immediate out of range for shift"));
13288 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13293 do_neon_movl (void)
13295 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13296 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13297 unsigned sizebits
= et
.size
>> 3;
13298 inst
.instruction
|= sizebits
<< 19;
13299 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13305 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13306 struct neon_type_el et
= neon_check_type (2, rs
,
13307 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13308 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13309 neon_two_same (neon_quad (rs
), 1, et
.size
);
13313 do_neon_zip_uzp (void)
13315 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13316 struct neon_type_el et
= neon_check_type (2, rs
,
13317 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13318 if (rs
== NS_DD
&& et
.size
== 32)
13320 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13321 inst
.instruction
= N_MNEM_vtrn
;
13325 neon_two_same (neon_quad (rs
), 1, et
.size
);
13329 do_neon_sat_abs_neg (void)
13331 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13332 struct neon_type_el et
= neon_check_type (2, rs
,
13333 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13334 neon_two_same (neon_quad (rs
), 1, et
.size
);
13338 do_neon_pair_long (void)
13340 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13341 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13342 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13343 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13344 neon_two_same (neon_quad (rs
), 1, et
.size
);
13348 do_neon_recip_est (void)
13350 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13351 struct neon_type_el et
= neon_check_type (2, rs
,
13352 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13353 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13354 neon_two_same (neon_quad (rs
), 1, et
.size
);
13360 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13361 struct neon_type_el et
= neon_check_type (2, rs
,
13362 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13363 neon_two_same (neon_quad (rs
), 1, et
.size
);
13369 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13370 struct neon_type_el et
= neon_check_type (2, rs
,
13371 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13372 neon_two_same (neon_quad (rs
), 1, et
.size
);
13378 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13379 struct neon_type_el et
= neon_check_type (2, rs
,
13380 N_EQK
| N_INT
, N_8
| N_KEY
);
13381 neon_two_same (neon_quad (rs
), 1, et
.size
);
13387 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13388 neon_two_same (neon_quad (rs
), 1, -1);
13392 do_neon_tbl_tbx (void)
13394 unsigned listlenbits
;
13395 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13397 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13399 first_error (_("bad list length for table lookup"));
13403 listlenbits
= inst
.operands
[1].imm
- 1;
13404 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13405 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13406 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13407 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13408 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13409 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13410 inst
.instruction
|= listlenbits
<< 8;
13412 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13416 do_neon_ldm_stm (void)
13418 /* P, U and L bits are part of bitmask. */
13419 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13420 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13422 if (inst
.operands
[1].issingle
)
13424 do_vfp_nsyn_ldm_stm (is_dbmode
);
13428 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13429 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13431 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13432 _("register list must contain at least 1 and at most 16 "
13435 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13436 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13437 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13438 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13440 inst
.instruction
|= offsetbits
;
13442 do_vfp_cond_or_thumb ();
13446 do_neon_ldr_str (void)
13448 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13450 if (inst
.operands
[0].issingle
)
13453 do_vfp_nsyn_opcode ("flds");
13455 do_vfp_nsyn_opcode ("fsts");
13460 do_vfp_nsyn_opcode ("fldd");
13462 do_vfp_nsyn_opcode ("fstd");
13466 /* "interleave" version also handles non-interleaving register VLD1/VST1
13470 do_neon_ld_st_interleave (void)
13472 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13473 N_8
| N_16
| N_32
| N_64
);
13474 unsigned alignbits
= 0;
13476 /* The bits in this table go:
13477 0: register stride of one (0) or two (1)
13478 1,2: register list length, minus one (1, 2, 3, 4).
13479 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13480 We use -1 for invalid entries. */
13481 const int typetable
[] =
13483 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13484 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13485 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13486 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13490 if (et
.type
== NT_invtype
)
13493 if (inst
.operands
[1].immisalign
)
13494 switch (inst
.operands
[1].imm
>> 8)
13496 case 64: alignbits
= 1; break;
13498 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13499 goto bad_alignment
;
13503 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13504 goto bad_alignment
;
13509 first_error (_("bad alignment"));
13513 inst
.instruction
|= alignbits
<< 4;
13514 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13516 /* Bits [4:6] of the immediate in a list specifier encode register stride
13517 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13518 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13519 up the right value for "type" in a table based on this value and the given
13520 list style, then stick it back. */
13521 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13522 | (((inst
.instruction
>> 8) & 3) << 3);
13524 typebits
= typetable
[idx
];
13526 constraint (typebits
== -1, _("bad list type for instruction"));
13528 inst
.instruction
&= ~0xf00;
13529 inst
.instruction
|= typebits
<< 8;
13532 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13533 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13534 otherwise. The variable arguments are a list of pairs of legal (size, align)
13535 values, terminated with -1. */
13538 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13541 int result
= FAIL
, thissize
, thisalign
;
13543 if (!inst
.operands
[1].immisalign
)
13549 va_start (ap
, do_align
);
13553 thissize
= va_arg (ap
, int);
13554 if (thissize
== -1)
13556 thisalign
= va_arg (ap
, int);
13558 if (size
== thissize
&& align
== thisalign
)
13561 while (result
!= SUCCESS
);
13565 if (result
== SUCCESS
)
13568 first_error (_("unsupported alignment for instruction"));
13574 do_neon_ld_st_lane (void)
13576 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13577 int align_good
, do_align
= 0;
13578 int logsize
= neon_logbits (et
.size
);
13579 int align
= inst
.operands
[1].imm
>> 8;
13580 int n
= (inst
.instruction
>> 8) & 3;
13581 int max_el
= 64 / et
.size
;
13583 if (et
.type
== NT_invtype
)
13586 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13587 _("bad list length"));
13588 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13589 _("scalar index out of range"));
13590 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13592 _("stride of 2 unavailable when element size is 8"));
13596 case 0: /* VLD1 / VST1. */
13597 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13599 if (align_good
== FAIL
)
13603 unsigned alignbits
= 0;
13606 case 16: alignbits
= 0x1; break;
13607 case 32: alignbits
= 0x3; break;
13610 inst
.instruction
|= alignbits
<< 4;
13614 case 1: /* VLD2 / VST2. */
13615 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13617 if (align_good
== FAIL
)
13620 inst
.instruction
|= 1 << 4;
13623 case 2: /* VLD3 / VST3. */
13624 constraint (inst
.operands
[1].immisalign
,
13625 _("can't use alignment with this instruction"));
13628 case 3: /* VLD4 / VST4. */
13629 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13630 16, 64, 32, 64, 32, 128, -1);
13631 if (align_good
== FAIL
)
13635 unsigned alignbits
= 0;
13638 case 8: alignbits
= 0x1; break;
13639 case 16: alignbits
= 0x1; break;
13640 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13643 inst
.instruction
|= alignbits
<< 4;
13650 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13651 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13652 inst
.instruction
|= 1 << (4 + logsize
);
13654 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13655 inst
.instruction
|= logsize
<< 10;
13658 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13661 do_neon_ld_dup (void)
13663 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13664 int align_good
, do_align
= 0;
13666 if (et
.type
== NT_invtype
)
13669 switch ((inst
.instruction
>> 8) & 3)
13671 case 0: /* VLD1. */
13672 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13673 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13674 &do_align
, 16, 16, 32, 32, -1);
13675 if (align_good
== FAIL
)
13677 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13680 case 2: inst
.instruction
|= 1 << 5; break;
13681 default: first_error (_("bad list length")); return;
13683 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13686 case 1: /* VLD2. */
13687 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13688 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13689 if (align_good
== FAIL
)
13691 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13692 _("bad list length"));
13693 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13694 inst
.instruction
|= 1 << 5;
13695 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13698 case 2: /* VLD3. */
13699 constraint (inst
.operands
[1].immisalign
,
13700 _("can't use alignment with this instruction"));
13701 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13702 _("bad list length"));
13703 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13704 inst
.instruction
|= 1 << 5;
13705 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13708 case 3: /* VLD4. */
13710 int align
= inst
.operands
[1].imm
>> 8;
13711 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13712 16, 64, 32, 64, 32, 128, -1);
13713 if (align_good
== FAIL
)
13715 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13716 _("bad list length"));
13717 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13718 inst
.instruction
|= 1 << 5;
13719 if (et
.size
== 32 && align
== 128)
13720 inst
.instruction
|= 0x3 << 6;
13722 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13729 inst
.instruction
|= do_align
<< 4;
13732 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13733 apart from bits [11:4]. */
13736 do_neon_ldx_stx (void)
13738 switch (NEON_LANE (inst
.operands
[0].imm
))
13740 case NEON_INTERLEAVE_LANES
:
13741 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13742 do_neon_ld_st_interleave ();
13745 case NEON_ALL_LANES
:
13746 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13751 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13752 do_neon_ld_st_lane ();
13755 /* L bit comes from bit mask. */
13756 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13757 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13758 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13760 if (inst
.operands
[1].postind
)
13762 int postreg
= inst
.operands
[1].imm
& 0xf;
13763 constraint (!inst
.operands
[1].immisreg
,
13764 _("post-index must be a register"));
13765 constraint (postreg
== 0xd || postreg
== 0xf,
13766 _("bad register for post-index"));
13767 inst
.instruction
|= postreg
;
13769 else if (inst
.operands
[1].writeback
)
13771 inst
.instruction
|= 0xd;
13774 inst
.instruction
|= 0xf;
13777 inst
.instruction
|= 0xf9000000;
13779 inst
.instruction
|= 0xf4000000;
13782 /* Overall per-instruction processing. */
13784 /* We need to be able to fix up arbitrary expressions in some statements.
13785 This is so that we can handle symbols that are an arbitrary distance from
13786 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13787 which returns part of an address in a form which will be valid for
13788 a data instruction. We do this by pushing the expression into a symbol
13789 in the expr_section, and creating a fix for that. */
13792 fix_new_arm (fragS
* frag
,
13807 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13811 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13816 /* Mark whether the fix is to a THUMB instruction, or an ARM
13818 new_fix
->tc_fix_data
= thumb_mode
;
13821 /* Create a frg for an instruction requiring relaxation. */
13823 output_relax_insn (void)
13829 /* The size of the instruction is unknown, so tie the debug info to the
13830 start of the instruction. */
13831 dwarf2_emit_insn (0);
13833 switch (inst
.reloc
.exp
.X_op
)
13836 sym
= inst
.reloc
.exp
.X_add_symbol
;
13837 offset
= inst
.reloc
.exp
.X_add_number
;
13841 offset
= inst
.reloc
.exp
.X_add_number
;
13844 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13848 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13849 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13850 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13853 /* Write a 32-bit thumb instruction to buf. */
13855 put_thumb32_insn (char * buf
, unsigned long insn
)
13857 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13858 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13862 output_inst (const char * str
)
13868 as_bad ("%s -- `%s'", inst
.error
, str
);
13873 output_relax_insn ();
13876 if (inst
.size
== 0)
13879 to
= frag_more (inst
.size
);
13881 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13883 assert (inst
.size
== (2 * THUMB_SIZE
));
13884 put_thumb32_insn (to
, inst
.instruction
);
13886 else if (inst
.size
> INSN_SIZE
)
13888 assert (inst
.size
== (2 * INSN_SIZE
));
13889 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13890 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13893 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13895 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13896 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13897 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13900 dwarf2_emit_insn (inst
.size
);
13903 /* Tag values used in struct asm_opcode's tag field. */
13906 OT_unconditional
, /* Instruction cannot be conditionalized.
13907 The ARM condition field is still 0xE. */
13908 OT_unconditionalF
, /* Instruction cannot be conditionalized
13909 and carries 0xF in its ARM condition field. */
13910 OT_csuffix
, /* Instruction takes a conditional suffix. */
13911 OT_csuffixF
, /* Some forms of the instruction take a conditional
13912 suffix, others place 0xF where the condition field
13914 OT_cinfix3
, /* Instruction takes a conditional infix,
13915 beginning at character index 3. (In
13916 unified mode, it becomes a suffix.) */
13917 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13918 tsts, cmps, cmns, and teqs. */
13919 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13920 character index 3, even in unified mode. Used for
13921 legacy instructions where suffix and infix forms
13922 may be ambiguous. */
13923 OT_csuf_or_in3
, /* Instruction takes either a conditional
13924 suffix or an infix at character index 3. */
13925 OT_odd_infix_unc
, /* This is the unconditional variant of an
13926 instruction that takes a conditional infix
13927 at an unusual position. In unified mode,
13928 this variant will accept a suffix. */
13929 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13930 are the conditional variants of instructions that
13931 take conditional infixes in unusual positions.
13932 The infix appears at character index
13933 (tag - OT_odd_infix_0). These are not accepted
13934 in unified mode. */
13937 /* Subroutine of md_assemble, responsible for looking up the primary
13938 opcode from the mnemonic the user wrote. STR points to the
13939 beginning of the mnemonic.
13941 This is not simply a hash table lookup, because of conditional
13942 variants. Most instructions have conditional variants, which are
13943 expressed with a _conditional affix_ to the mnemonic. If we were
13944 to encode each conditional variant as a literal string in the opcode
13945 table, it would have approximately 20,000 entries.
13947 Most mnemonics take this affix as a suffix, and in unified syntax,
13948 'most' is upgraded to 'all'. However, in the divided syntax, some
13949 instructions take the affix as an infix, notably the s-variants of
13950 the arithmetic instructions. Of those instructions, all but six
13951 have the infix appear after the third character of the mnemonic.
13953 Accordingly, the algorithm for looking up primary opcodes given
13956 1. Look up the identifier in the opcode table.
13957 If we find a match, go to step U.
13959 2. Look up the last two characters of the identifier in the
13960 conditions table. If we find a match, look up the first N-2
13961 characters of the identifier in the opcode table. If we
13962 find a match, go to step CE.
13964 3. Look up the fourth and fifth characters of the identifier in
13965 the conditions table. If we find a match, extract those
13966 characters from the identifier, and look up the remaining
13967 characters in the opcode table. If we find a match, go
13972 U. Examine the tag field of the opcode structure, in case this is
13973 one of the six instructions with its conditional infix in an
13974 unusual place. If it is, the tag tells us where to find the
13975 infix; look it up in the conditions table and set inst.cond
13976 accordingly. Otherwise, this is an unconditional instruction.
13977 Again set inst.cond accordingly. Return the opcode structure.
13979 CE. Examine the tag field to make sure this is an instruction that
13980 should receive a conditional suffix. If it is not, fail.
13981 Otherwise, set inst.cond from the suffix we already looked up,
13982 and return the opcode structure.
13984 CM. Examine the tag field to make sure this is an instruction that
13985 should receive a conditional infix after the third character.
13986 If it is not, fail. Otherwise, undo the edits to the current
13987 line of input and proceed as for case CE. */
13989 static const struct asm_opcode
*
13990 opcode_lookup (char **str
)
13994 const struct asm_opcode
*opcode
;
13995 const struct asm_cond
*cond
;
13997 bfd_boolean neon_supported
;
13999 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14001 /* Scan up to the end of the mnemonic, which must end in white space,
14002 '.' (in unified mode, or for Neon instructions), or end of string. */
14003 for (base
= end
= *str
; *end
!= '\0'; end
++)
14004 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14010 /* Handle a possible width suffix and/or Neon type suffix. */
14015 /* The .w and .n suffixes are only valid if the unified syntax is in
14017 if (unified_syntax
&& end
[1] == 'w')
14019 else if (unified_syntax
&& end
[1] == 'n')
14024 inst
.vectype
.elems
= 0;
14026 *str
= end
+ offset
;
14028 if (end
[offset
] == '.')
14030 /* See if we have a Neon type suffix (possible in either unified or
14031 non-unified ARM syntax mode). */
14032 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14035 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14041 /* Look for unaffixed or special-case affixed mnemonic. */
14042 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14046 if (opcode
->tag
< OT_odd_infix_0
)
14048 inst
.cond
= COND_ALWAYS
;
14052 if (unified_syntax
)
14053 as_warn (_("conditional infixes are deprecated in unified syntax"));
14054 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14055 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14058 inst
.cond
= cond
->value
;
14062 /* Cannot have a conditional suffix on a mnemonic of less than two
14064 if (end
- base
< 3)
14067 /* Look for suffixed mnemonic. */
14069 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14070 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14071 if (opcode
&& cond
)
14074 switch (opcode
->tag
)
14076 case OT_cinfix3_legacy
:
14077 /* Ignore conditional suffixes matched on infix only mnemonics. */
14081 case OT_cinfix3_deprecated
:
14082 case OT_odd_infix_unc
:
14083 if (!unified_syntax
)
14085 /* else fall through */
14089 case OT_csuf_or_in3
:
14090 inst
.cond
= cond
->value
;
14093 case OT_unconditional
:
14094 case OT_unconditionalF
:
14097 inst
.cond
= cond
->value
;
14101 /* delayed diagnostic */
14102 inst
.error
= BAD_COND
;
14103 inst
.cond
= COND_ALWAYS
;
14112 /* Cannot have a usual-position infix on a mnemonic of less than
14113 six characters (five would be a suffix). */
14114 if (end
- base
< 6)
14117 /* Look for infixed mnemonic in the usual position. */
14119 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14123 memcpy (save
, affix
, 2);
14124 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14125 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14126 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14127 memcpy (affix
, save
, 2);
14130 && (opcode
->tag
== OT_cinfix3
14131 || opcode
->tag
== OT_cinfix3_deprecated
14132 || opcode
->tag
== OT_csuf_or_in3
14133 || opcode
->tag
== OT_cinfix3_legacy
))
14137 && (opcode
->tag
== OT_cinfix3
14138 || opcode
->tag
== OT_cinfix3_deprecated
))
14139 as_warn (_("conditional infixes are deprecated in unified syntax"));
14141 inst
.cond
= cond
->value
;
14149 md_assemble (char *str
)
14152 const struct asm_opcode
* opcode
;
14154 /* Align the previous label if needed. */
14155 if (last_label_seen
!= NULL
)
14157 symbol_set_frag (last_label_seen
, frag_now
);
14158 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14159 S_SET_SEGMENT (last_label_seen
, now_seg
);
14162 memset (&inst
, '\0', sizeof (inst
));
14163 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14165 opcode
= opcode_lookup (&p
);
14168 /* It wasn't an instruction, but it might be a register alias of
14169 the form alias .req reg, or a Neon .dn/.qn directive. */
14170 if (!create_register_alias (str
, p
)
14171 && !create_neon_reg_alias (str
, p
))
14172 as_bad (_("bad instruction `%s'"), str
);
14177 if (opcode
->tag
== OT_cinfix3_deprecated
)
14178 as_warn (_("s suffix on comparison instruction is deprecated"));
14180 /* The value which unconditional instructions should have in place of the
14181 condition field. */
14182 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14186 arm_feature_set variant
;
14188 variant
= cpu_variant
;
14189 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14190 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14191 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14192 /* Check that this instruction is supported for this CPU. */
14193 if (!opcode
->tvariant
14194 || (thumb_mode
== 1
14195 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14197 as_bad (_("selected processor does not support `%s'"), str
);
14200 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14201 && opcode
->tencode
!= do_t_branch
)
14203 as_bad (_("Thumb does not support conditional execution"));
14207 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14209 /* Implicit require narrow instructions on Thumb-1. This avoids
14210 relaxation accidentally introducing Thumb-2 instructions. */
14211 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
)
14215 /* Check conditional suffixes. */
14216 if (current_it_mask
)
14219 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14220 current_it_mask
<<= 1;
14221 current_it_mask
&= 0x1f;
14222 /* The BKPT instruction is unconditional even in an IT block. */
14224 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14226 as_bad (_("incorrect condition in IT block"));
14230 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14232 as_bad (_("thumb conditional instruction not in IT block"));
14236 mapping_state (MAP_THUMB
);
14237 inst
.instruction
= opcode
->tvalue
;
14239 if (!parse_operands (p
, opcode
->operands
))
14240 opcode
->tencode ();
14242 /* Clear current_it_mask at the end of an IT block. */
14243 if (current_it_mask
== 0x10)
14244 current_it_mask
= 0;
14246 if (!(inst
.error
|| inst
.relax
))
14248 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14249 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14250 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14252 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14257 /* Something has gone badly wrong if we try to relax a fixed size
14259 assert (inst
.size_req
== 0 || !inst
.relax
);
14261 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14262 *opcode
->tvariant
);
14263 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14264 set those bits when Thumb-2 32-bit instructions are seen. ie.
14265 anything other than bl/blx.
14266 This is overly pessimistic for relaxable instructions. */
14267 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14269 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14272 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14274 /* Check that this instruction is supported for this CPU. */
14275 if (!opcode
->avariant
||
14276 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
14278 as_bad (_("selected processor does not support `%s'"), str
);
14283 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14287 mapping_state (MAP_ARM
);
14288 inst
.instruction
= opcode
->avalue
;
14289 if (opcode
->tag
== OT_unconditionalF
)
14290 inst
.instruction
|= 0xF << 28;
14292 inst
.instruction
|= inst
.cond
<< 28;
14293 inst
.size
= INSN_SIZE
;
14294 if (!parse_operands (p
, opcode
->operands
))
14295 opcode
->aencode ();
14296 /* Arm mode bx is marked as both v4T and v5 because it's still required
14297 on a hypothetical non-thumb v5 core. */
14298 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
14299 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
14300 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14302 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14303 *opcode
->avariant
);
14307 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14314 /* Various frobbings of labels and their addresses. */
14317 arm_start_line_hook (void)
14319 last_label_seen
= NULL
;
14323 arm_frob_label (symbolS
* sym
)
14325 last_label_seen
= sym
;
14327 ARM_SET_THUMB (sym
, thumb_mode
);
14329 #if defined OBJ_COFF || defined OBJ_ELF
14330 ARM_SET_INTERWORK (sym
, support_interwork
);
14333 /* Note - do not allow local symbols (.Lxxx) to be labelled
14334 as Thumb functions. This is because these labels, whilst
14335 they exist inside Thumb code, are not the entry points for
14336 possible ARM->Thumb calls. Also, these labels can be used
14337 as part of a computed goto or switch statement. eg gcc
14338 can generate code that looks like this:
14340 ldr r2, [pc, .Laaa]
14350 The first instruction loads the address of the jump table.
14351 The second instruction converts a table index into a byte offset.
14352 The third instruction gets the jump address out of the table.
14353 The fourth instruction performs the jump.
14355 If the address stored at .Laaa is that of a symbol which has the
14356 Thumb_Func bit set, then the linker will arrange for this address
14357 to have the bottom bit set, which in turn would mean that the
14358 address computation performed by the third instruction would end
14359 up with the bottom bit set. Since the ARM is capable of unaligned
14360 word loads, the instruction would then load the incorrect address
14361 out of the jump table, and chaos would ensue. */
14362 if (label_is_thumb_function_name
14363 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14364 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14366 /* When the address of a Thumb function is taken the bottom
14367 bit of that address should be set. This will allow
14368 interworking between Arm and Thumb functions to work
14371 THUMB_SET_FUNC (sym
, 1);
14373 label_is_thumb_function_name
= FALSE
;
14376 dwarf2_emit_label (sym
);
14380 arm_data_in_code (void)
14382 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14384 *input_line_pointer
= '/';
14385 input_line_pointer
+= 5;
14386 *input_line_pointer
= 0;
14394 arm_canonicalize_symbol_name (char * name
)
14398 if (thumb_mode
&& (len
= strlen (name
)) > 5
14399 && streq (name
+ len
- 5, "/data"))
14400 *(name
+ len
- 5) = 0;
14405 /* Table of all register names defined by default. The user can
14406 define additional names with .req. Note that all register names
14407 should appear in both upper and lowercase variants. Some registers
14408 also have mixed-case names. */
14410 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14411 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14412 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14413 #define REGSET(p,t) \
14414 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14415 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14416 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14417 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14418 #define REGSETH(p,t) \
14419 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14420 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14421 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14422 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14423 #define REGSET2(p,t) \
14424 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14425 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14426 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14427 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14429 static const struct reg_entry reg_names
[] =
14431 /* ARM integer registers. */
14432 REGSET(r
, RN
), REGSET(R
, RN
),
14434 /* ATPCS synonyms. */
14435 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14436 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14437 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14439 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14440 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14441 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14443 /* Well-known aliases. */
14444 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14445 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14447 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14448 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14450 /* Coprocessor numbers. */
14451 REGSET(p
, CP
), REGSET(P
, CP
),
14453 /* Coprocessor register numbers. The "cr" variants are for backward
14455 REGSET(c
, CN
), REGSET(C
, CN
),
14456 REGSET(cr
, CN
), REGSET(CR
, CN
),
14458 /* FPA registers. */
14459 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14460 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14462 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14463 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14465 /* VFP SP registers. */
14466 REGSET(s
,VFS
), REGSET(S
,VFS
),
14467 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14469 /* VFP DP Registers. */
14470 REGSET(d
,VFD
), REGSET(D
,VFD
),
14471 /* Extra Neon DP registers. */
14472 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14474 /* Neon QP registers. */
14475 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14477 /* VFP control registers. */
14478 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14479 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14480 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
14481 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
14482 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
14483 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
14485 /* Maverick DSP coprocessor registers. */
14486 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14487 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14489 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14490 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14491 REGDEF(dspsc
,0,DSPSC
),
14493 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14494 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14495 REGDEF(DSPSC
,0,DSPSC
),
14497 /* iWMMXt data registers - p0, c0-15. */
14498 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14500 /* iWMMXt control registers - p1, c0-3. */
14501 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14502 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14503 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14504 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14506 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14507 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14508 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14509 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14510 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14512 /* XScale accumulator registers. */
14513 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14519 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14520 within psr_required_here. */
14521 static const struct asm_psr psrs
[] =
14523 /* Backward compatibility notation. Note that "all" is no longer
14524 truly all possible PSR bits. */
14525 {"all", PSR_c
| PSR_f
},
14529 /* Individual flags. */
14534 /* Combinations of flags. */
14535 {"fs", PSR_f
| PSR_s
},
14536 {"fx", PSR_f
| PSR_x
},
14537 {"fc", PSR_f
| PSR_c
},
14538 {"sf", PSR_s
| PSR_f
},
14539 {"sx", PSR_s
| PSR_x
},
14540 {"sc", PSR_s
| PSR_c
},
14541 {"xf", PSR_x
| PSR_f
},
14542 {"xs", PSR_x
| PSR_s
},
14543 {"xc", PSR_x
| PSR_c
},
14544 {"cf", PSR_c
| PSR_f
},
14545 {"cs", PSR_c
| PSR_s
},
14546 {"cx", PSR_c
| PSR_x
},
14547 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14548 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14549 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14550 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14551 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14552 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14553 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14554 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14555 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14556 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14557 {"scf", PSR_s
| PSR_c
| PSR_f
},
14558 {"scx", PSR_s
| PSR_c
| PSR_x
},
14559 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14560 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14561 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14562 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14563 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14564 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14565 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14566 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14567 {"csf", PSR_c
| PSR_s
| PSR_f
},
14568 {"csx", PSR_c
| PSR_s
| PSR_x
},
14569 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14570 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14571 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14572 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14573 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14574 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14575 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14576 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14577 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14578 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14579 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14580 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14581 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14582 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14583 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14584 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14585 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14586 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14587 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14588 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14589 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14590 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14591 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14592 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14593 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14594 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14597 /* Table of V7M psr names. */
14598 static const struct asm_psr v7m_psrs
[] =
14600 {"apsr", 0 }, {"APSR", 0 },
14601 {"iapsr", 1 }, {"IAPSR", 1 },
14602 {"eapsr", 2 }, {"EAPSR", 2 },
14603 {"psr", 3 }, {"PSR", 3 },
14604 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14605 {"ipsr", 5 }, {"IPSR", 5 },
14606 {"epsr", 6 }, {"EPSR", 6 },
14607 {"iepsr", 7 }, {"IEPSR", 7 },
14608 {"msp", 8 }, {"MSP", 8 },
14609 {"psp", 9 }, {"PSP", 9 },
14610 {"primask", 16}, {"PRIMASK", 16},
14611 {"basepri", 17}, {"BASEPRI", 17},
14612 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14613 {"faultmask", 19}, {"FAULTMASK", 19},
14614 {"control", 20}, {"CONTROL", 20}
14617 /* Table of all shift-in-operand names. */
14618 static const struct asm_shift_name shift_names
[] =
14620 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14621 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14622 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14623 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14624 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14625 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14628 /* Table of all explicit relocation names. */
14630 static struct reloc_entry reloc_names
[] =
14632 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14633 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14634 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14635 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14636 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14637 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14638 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14639 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14640 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14641 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14642 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14646 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14647 static const struct asm_cond conds
[] =
14651 {"cs", 0x2}, {"hs", 0x2},
14652 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14666 static struct asm_barrier_opt barrier_opt_names
[] =
14674 /* Table of ARM-format instructions. */
14676 /* Macros for gluing together operand strings. N.B. In all cases
14677 other than OPS0, the trailing OP_stop comes from default
14678 zero-initialization of the unspecified elements of the array. */
14679 #define OPS0() { OP_stop, }
14680 #define OPS1(a) { OP_##a, }
14681 #define OPS2(a,b) { OP_##a,OP_##b, }
14682 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14683 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14684 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14685 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14687 /* These macros abstract out the exact format of the mnemonic table and
14688 save some repeated characters. */
14690 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14691 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14692 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14693 THUMB_VARIANT, do_##ae, do_##te }
14695 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14696 a T_MNEM_xyz enumerator. */
14697 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14698 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14699 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14700 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14702 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14703 infix after the third character. */
14704 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14705 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14706 THUMB_VARIANT, do_##ae, do_##te }
14707 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14708 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14709 THUMB_VARIANT, do_##ae, do_##te }
14710 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14711 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14712 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14713 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14714 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14715 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14716 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14717 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14719 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14720 appear in the condition table. */
14721 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14722 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14723 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14725 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14726 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14727 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14728 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14729 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14730 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14731 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14732 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14733 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14734 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14735 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14736 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14737 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14738 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14739 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14740 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14741 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14742 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14743 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14744 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14746 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14747 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14748 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14749 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14751 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14752 field is still 0xE. Many of the Thumb variants can be executed
14753 conditionally, so this is checked separately. */
14754 #define TUE(mnem, op, top, nops, ops, ae, te) \
14755 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14756 THUMB_VARIANT, do_##ae, do_##te }
14758 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14759 condition code field. */
14760 #define TUF(mnem, op, top, nops, ops, ae, te) \
14761 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14762 THUMB_VARIANT, do_##ae, do_##te }
14764 /* ARM-only variants of all the above. */
14765 #define CE(mnem, op, nops, ops, ae) \
14766 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14768 #define C3(mnem, op, nops, ops, ae) \
14769 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14771 /* Legacy mnemonics that always have conditional infix after the third
14773 #define CL(mnem, op, nops, ops, ae) \
14774 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14775 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14777 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14778 #define cCE(mnem, op, nops, ops, ae) \
14779 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14781 /* Legacy coprocessor instructions where conditional infix and conditional
14782 suffix are ambiguous. For consistency this includes all FPA instructions,
14783 not just the potentially ambiguous ones. */
14784 #define cCL(mnem, op, nops, ops, ae) \
14785 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14786 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14788 /* Coprocessor, takes either a suffix or a position-3 infix
14789 (for an FPA corner case). */
14790 #define C3E(mnem, op, nops, ops, ae) \
14791 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14792 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14794 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14795 { #m1 #m2 #m3, OPS##nops ops, \
14796 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14797 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14799 #define CM(m1, m2, op, nops, ops, ae) \
14800 xCM_(m1, , m2, op, nops, ops, ae), \
14801 xCM_(m1, eq, m2, op, nops, ops, ae), \
14802 xCM_(m1, ne, m2, op, nops, ops, ae), \
14803 xCM_(m1, cs, m2, op, nops, ops, ae), \
14804 xCM_(m1, hs, m2, op, nops, ops, ae), \
14805 xCM_(m1, cc, m2, op, nops, ops, ae), \
14806 xCM_(m1, ul, m2, op, nops, ops, ae), \
14807 xCM_(m1, lo, m2, op, nops, ops, ae), \
14808 xCM_(m1, mi, m2, op, nops, ops, ae), \
14809 xCM_(m1, pl, m2, op, nops, ops, ae), \
14810 xCM_(m1, vs, m2, op, nops, ops, ae), \
14811 xCM_(m1, vc, m2, op, nops, ops, ae), \
14812 xCM_(m1, hi, m2, op, nops, ops, ae), \
14813 xCM_(m1, ls, m2, op, nops, ops, ae), \
14814 xCM_(m1, ge, m2, op, nops, ops, ae), \
14815 xCM_(m1, lt, m2, op, nops, ops, ae), \
14816 xCM_(m1, gt, m2, op, nops, ops, ae), \
14817 xCM_(m1, le, m2, op, nops, ops, ae), \
14818 xCM_(m1, al, m2, op, nops, ops, ae)
14820 #define UE(mnem, op, nops, ops, ae) \
14821 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14823 #define UF(mnem, op, nops, ops, ae) \
14824 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14826 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14827 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14828 use the same encoding function for each. */
14829 #define NUF(mnem, op, nops, ops, enc) \
14830 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14831 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14833 /* Neon data processing, version which indirects through neon_enc_tab for
14834 the various overloaded versions of opcodes. */
14835 #define nUF(mnem, op, nops, ops, enc) \
14836 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14837 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14839 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14841 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14842 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14843 THUMB_VARIANT, do_##enc, do_##enc }
14845 #define NCE(mnem, op, nops, ops, enc) \
14846 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14848 #define NCEF(mnem, op, nops, ops, enc) \
14849 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14851 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14852 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14853 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14854 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14856 #define nCE(mnem, op, nops, ops, enc) \
14857 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14859 #define nCEF(mnem, op, nops, ops, enc) \
14860 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14864 /* Thumb-only, unconditional. */
14865 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14867 static const struct asm_opcode insns
[] =
14869 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14870 #define THUMB_VARIANT &arm_ext_v4t
14871 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14872 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14873 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14874 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14875 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14876 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14877 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14878 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14879 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14880 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14881 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14882 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14883 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14884 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14885 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14886 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14888 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14889 for setting PSR flag bits. They are obsolete in V6 and do not
14890 have Thumb equivalents. */
14891 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14892 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14893 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14894 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14895 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14896 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14897 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14898 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14899 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14901 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14902 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14903 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14904 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14906 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14907 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14908 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14909 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14911 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14912 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14913 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14914 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14915 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14916 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14918 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14919 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14920 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14921 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14924 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14925 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14926 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14928 /* Thumb-compatibility pseudo ops. */
14929 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14930 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14931 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14932 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14933 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14934 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14935 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14936 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14937 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14938 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14939 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14940 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14942 /* These may simplify to neg. */
14943 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14944 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14946 #undef THUMB_VARIANT
14947 #define THUMB_VARIANT &arm_ext_v6
14948 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14950 /* V1 instructions with no Thumb analogue prior to V6T2. */
14951 #undef THUMB_VARIANT
14952 #define THUMB_VARIANT &arm_ext_v6t2
14953 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14954 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14955 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14957 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14958 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14959 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14960 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14962 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14963 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14965 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14966 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14968 /* V1 instructions with no Thumb analogue at all. */
14969 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14970 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14972 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14973 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14974 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14975 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14976 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14977 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14978 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14979 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14982 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14983 #undef THUMB_VARIANT
14984 #define THUMB_VARIANT &arm_ext_v4t
14985 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14986 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14988 #undef THUMB_VARIANT
14989 #define THUMB_VARIANT &arm_ext_v6t2
14990 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14991 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14993 /* Generic coprocessor instructions. */
14994 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14995 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14996 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14997 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14998 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14999 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15000 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15003 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15004 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15005 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15008 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15009 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15010 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15013 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15014 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15015 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15016 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15017 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15018 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15019 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15020 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15021 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15024 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15025 #undef THUMB_VARIANT
15026 #define THUMB_VARIANT &arm_ext_v4t
15027 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15028 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15029 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15030 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15031 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15032 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15035 #define ARM_VARIANT &arm_ext_v4t_5
15036 /* ARM Architecture 4T. */
15037 /* Note: bx (and blx) are required on V5, even if the processor does
15038 not support Thumb. */
15039 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15042 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15043 #undef THUMB_VARIANT
15044 #define THUMB_VARIANT &arm_ext_v5t
15045 /* Note: blx has 2 variants; the .value coded here is for
15046 BLX(2). Only this variant has conditional execution. */
15047 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15048 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15050 #undef THUMB_VARIANT
15051 #define THUMB_VARIANT &arm_ext_v6t2
15052 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15053 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15054 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15055 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15056 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15057 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15058 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15059 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15062 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15063 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15064 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15065 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15066 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15068 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15069 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15071 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15072 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15073 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15074 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15076 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15077 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15078 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15079 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15081 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15082 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15084 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15085 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15086 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15087 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15090 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15091 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15092 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15093 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15095 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15096 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15099 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15100 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15103 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15104 #undef THUMB_VARIANT
15105 #define THUMB_VARIANT &arm_ext_v6
15106 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15107 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15108 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15109 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15110 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15111 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15112 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15113 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15114 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15115 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15117 #undef THUMB_VARIANT
15118 #define THUMB_VARIANT &arm_ext_v6t2
15119 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15120 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15121 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15122 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15124 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15125 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15127 /* ARM V6 not included in V7M (eg. integer SIMD). */
15128 #undef THUMB_VARIANT
15129 #define THUMB_VARIANT &arm_ext_v6_notm
15130 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15131 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15132 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15133 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15134 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15135 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15136 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15137 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15138 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15139 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15140 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15141 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15142 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15143 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15144 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15145 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15146 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15147 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15148 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15149 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15150 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15151 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15152 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15153 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15154 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15155 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15156 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15157 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15158 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15159 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15160 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15161 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15162 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15163 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15164 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15165 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15166 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15167 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15168 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15169 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15170 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15171 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15172 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15173 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15174 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15175 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15176 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15177 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15178 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15179 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15180 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15181 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15182 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15183 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15184 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15185 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15186 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15187 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15188 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15189 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15190 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15191 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15192 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15193 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15194 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15195 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15196 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15197 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15198 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15199 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15200 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15201 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15202 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15203 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15204 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15205 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15206 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15207 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15208 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15209 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15210 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15211 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15212 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15215 #define ARM_VARIANT &arm_ext_v6k
15216 #undef THUMB_VARIANT
15217 #define THUMB_VARIANT &arm_ext_v6k
15218 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15219 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15220 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15221 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15223 #undef THUMB_VARIANT
15224 #define THUMB_VARIANT &arm_ext_v6_notm
15225 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15226 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15228 #undef THUMB_VARIANT
15229 #define THUMB_VARIANT &arm_ext_v6t2
15230 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15231 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15232 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15233 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15234 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15237 #define ARM_VARIANT &arm_ext_v6z
15238 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15241 #define ARM_VARIANT &arm_ext_v6t2
15242 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15243 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15244 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15245 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15247 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15248 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15249 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15250 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15252 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15253 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15254 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15255 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15257 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15258 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15259 /* ARM does not really have an IT instruction, so always allow it. */
15261 #define ARM_VARIANT &arm_ext_v1
15262 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15263 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15264 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15265 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15266 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15267 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15268 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15269 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15270 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15271 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15272 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15273 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15274 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15275 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15276 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15278 /* Thumb2 only instructions. */
15280 #define ARM_VARIANT NULL
15282 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15283 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15284 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15285 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15287 /* Thumb-2 hardware division instructions (R and M profiles only). */
15288 #undef THUMB_VARIANT
15289 #define THUMB_VARIANT &arm_ext_div
15290 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15291 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15293 /* ARM V7 instructions. */
15295 #define ARM_VARIANT &arm_ext_v7
15296 #undef THUMB_VARIANT
15297 #define THUMB_VARIANT &arm_ext_v7
15298 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15299 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15300 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15301 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15302 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15305 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15306 cCE(wfs
, e200110
, 1, (RR
), rd
),
15307 cCE(rfs
, e300110
, 1, (RR
), rd
),
15308 cCE(wfc
, e400110
, 1, (RR
), rd
),
15309 cCE(rfc
, e500110
, 1, (RR
), rd
),
15311 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15312 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15313 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15314 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15316 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15317 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15318 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15319 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15321 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15322 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15323 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15324 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15325 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15326 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15327 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15328 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15329 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15330 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15331 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15332 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15334 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15335 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15336 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15337 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15338 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15339 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15340 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15341 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15342 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15343 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15344 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15345 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15347 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15348 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15349 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15350 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15351 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15352 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15353 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15354 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15355 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15356 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15357 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15358 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15360 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15361 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15362 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15363 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15364 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15365 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15366 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15367 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15368 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15369 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15370 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15371 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15373 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15374 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15375 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15376 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15377 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15378 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15379 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15380 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15381 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15382 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15383 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15384 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15386 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15387 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15388 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15389 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15390 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15391 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15392 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15393 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15394 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15395 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15396 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15397 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15399 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15400 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15401 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15402 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15403 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15404 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15405 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15406 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15407 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15408 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15409 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15410 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15412 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15413 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15414 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15415 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15416 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15417 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15418 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15419 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15420 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15421 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15422 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15423 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15425 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15426 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15427 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15428 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15429 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15430 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15431 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15432 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15433 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15434 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15435 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15436 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15438 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15439 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15440 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15441 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15442 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15443 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15444 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15445 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15446 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15447 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15448 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15449 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15451 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15452 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15453 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15454 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15455 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15456 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15457 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15458 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15459 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15460 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15461 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15462 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15464 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15465 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15466 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15467 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15468 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15469 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15470 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15471 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15472 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15473 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15474 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15475 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15477 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15478 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15479 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15480 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15481 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15482 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15483 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15484 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15485 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15486 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15487 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15488 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15490 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15491 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15492 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15493 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15494 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15495 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15496 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15497 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15498 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15499 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15500 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15501 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15503 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15504 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15505 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15506 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15507 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15508 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15509 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15510 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15511 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15512 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15513 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15514 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15516 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15517 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15518 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15519 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15520 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15521 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15522 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15523 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15524 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15525 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15526 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15527 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15529 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15530 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15531 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15532 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15533 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15534 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15535 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15536 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15537 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15538 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15539 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15540 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15542 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15543 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15544 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15545 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15546 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15547 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15548 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15549 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15550 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15551 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15552 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15553 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15555 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15556 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15557 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15558 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15559 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15560 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15561 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15562 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15563 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15564 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15565 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15566 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15568 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15569 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15570 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15571 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15572 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15573 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15574 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15575 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15576 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15577 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15578 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15579 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15581 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15582 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15583 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15584 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15585 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15586 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15587 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15588 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15589 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15590 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15591 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15592 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15594 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15595 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15596 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15597 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15598 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15599 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15600 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15601 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15602 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15603 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15604 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15605 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15607 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15608 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15609 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15610 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15611 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15612 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15613 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15614 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15615 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15616 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15617 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15618 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15620 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15621 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15622 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15623 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15624 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15625 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15626 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15627 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15628 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15629 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15630 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15631 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15633 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15634 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15635 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15636 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15637 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15638 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15639 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15640 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15641 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15642 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15643 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15644 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15646 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15647 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15648 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15649 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15650 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15651 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15652 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15653 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15654 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15655 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15656 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15657 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15659 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15660 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15661 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15662 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15663 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15664 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15665 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15666 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15667 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15668 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15669 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15670 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15672 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15673 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15674 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15675 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15676 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15677 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15678 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15679 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15680 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15681 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15682 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15683 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15685 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15686 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15687 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15688 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15689 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15690 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15691 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15692 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15693 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15694 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15695 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15696 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15698 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15699 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15700 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15701 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15703 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15704 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15705 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15706 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15707 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15708 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15709 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15710 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15711 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15712 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15713 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15714 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15716 /* The implementation of the FIX instruction is broken on some
15717 assemblers, in that it accepts a precision specifier as well as a
15718 rounding specifier, despite the fact that this is meaningless.
15719 To be more compatible, we accept it as well, though of course it
15720 does not set any bits. */
15721 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15722 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15723 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15724 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15725 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15726 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15727 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15728 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15729 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15730 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15731 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15732 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15733 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15735 /* Instructions that were new with the real FPA, call them V2. */
15737 #define ARM_VARIANT &fpu_fpa_ext_v2
15738 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15739 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15740 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15741 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15742 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15743 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15746 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15747 /* Moves and type conversions. */
15748 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15749 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15750 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15751 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15752 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15753 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15754 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15755 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15756 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15757 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15758 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15759 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15761 /* Memory operations. */
15762 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15763 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15764 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15765 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15766 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15767 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15768 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15769 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15770 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15771 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15772 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15773 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15774 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15775 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15776 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15777 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15778 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15779 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15781 /* Monadic operations. */
15782 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15783 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15784 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15786 /* Dyadic operations. */
15787 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15788 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15789 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15790 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15791 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15792 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15793 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15794 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15795 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15798 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15799 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15800 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15801 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15804 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15805 /* Moves and type conversions. */
15806 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15807 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15808 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15809 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15810 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15811 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15812 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15813 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15814 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15815 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15816 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15817 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15818 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15820 /* Memory operations. */
15821 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15822 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15823 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15824 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15825 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15826 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15827 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15828 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15829 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15830 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15832 /* Monadic operations. */
15833 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15834 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15835 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15837 /* Dyadic operations. */
15838 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15839 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15840 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15841 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15842 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15843 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15844 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15845 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15846 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15849 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15850 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15851 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15852 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15855 #define ARM_VARIANT &fpu_vfp_ext_v2
15856 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15857 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15858 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15859 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15861 /* Instructions which may belong to either the Neon or VFP instruction sets.
15862 Individual encoder functions perform additional architecture checks. */
15864 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15865 #undef THUMB_VARIANT
15866 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15867 /* These mnemonics are unique to VFP. */
15868 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15869 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15870 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15871 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15872 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15873 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15874 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15875 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15876 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15877 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15879 /* Mnemonics shared by Neon and VFP. */
15880 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15881 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15882 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15884 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15885 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15887 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15888 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15890 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15891 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15892 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15893 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15894 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15895 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15896 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15897 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15899 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15901 /* NOTE: All VMOV encoding is special-cased! */
15902 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15903 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15905 #undef THUMB_VARIANT
15906 #define THUMB_VARIANT &fpu_neon_ext_v1
15908 #define ARM_VARIANT &fpu_neon_ext_v1
15909 /* Data processing with three registers of the same length. */
15910 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15911 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15912 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15913 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15914 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15915 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15916 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15917 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15918 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15919 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15920 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15921 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15922 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15923 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15924 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15925 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15926 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15927 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15928 /* If not immediate, fall back to neon_dyadic_i64_su.
15929 shl_imm should accept I8 I16 I32 I64,
15930 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15931 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15932 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15933 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15934 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15935 /* Logic ops, types optional & ignored. */
15936 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15937 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15938 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15939 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15940 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15941 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15942 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15943 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15944 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15945 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15946 /* Bitfield ops, untyped. */
15947 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15948 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15949 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15950 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15951 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15952 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15953 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15954 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15955 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15956 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15957 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15958 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15959 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15960 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15961 back to neon_dyadic_if_su. */
15962 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15963 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15964 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15965 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15966 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15967 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15968 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15969 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15970 /* Comparison. Type I8 I16 I32 F32. */
15971 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15972 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15973 /* As above, D registers only. */
15974 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15975 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15976 /* Int and float variants, signedness unimportant. */
15977 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15978 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15979 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15980 /* Add/sub take types I8 I16 I32 I64 F32. */
15981 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15982 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15983 /* vtst takes sizes 8, 16, 32. */
15984 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15985 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15986 /* VMUL takes I8 I16 I32 F32 P8. */
15987 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15988 /* VQD{R}MULH takes S16 S32. */
15989 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15990 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15991 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15992 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15993 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15994 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15995 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15996 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15997 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15998 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15999 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16000 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16001 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16002 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16003 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16004 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16006 /* Two address, int/float. Types S8 S16 S32 F32. */
16007 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16008 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16010 /* Data processing with two registers and a shift amount. */
16011 /* Right shifts, and variants with rounding.
16012 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16013 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16014 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16015 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16016 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16017 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16018 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16019 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16020 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16021 /* Shift and insert. Sizes accepted 8 16 32 64. */
16022 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16023 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16024 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16025 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16026 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16027 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16028 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16029 /* Right shift immediate, saturating & narrowing, with rounding variants.
16030 Types accepted S16 S32 S64 U16 U32 U64. */
16031 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16032 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16033 /* As above, unsigned. Types accepted S16 S32 S64. */
16034 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16035 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16036 /* Right shift narrowing. Types accepted I16 I32 I64. */
16037 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16038 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16039 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16040 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16041 /* CVT with optional immediate for fixed-point variant. */
16042 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16044 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16045 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16047 /* Data processing, three registers of different lengths. */
16048 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16049 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16050 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16051 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16052 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16053 /* If not scalar, fall back to neon_dyadic_long.
16054 Vector types as above, scalar types S16 S32 U16 U32. */
16055 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16056 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16057 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16058 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16059 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16060 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16061 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16062 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16063 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16064 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16065 /* Saturating doubling multiplies. Types S16 S32. */
16066 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16067 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16068 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16069 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16070 S16 S32 U16 U32. */
16071 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16073 /* Extract. Size 8. */
16074 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16075 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16077 /* Two registers, miscellaneous. */
16078 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16079 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16080 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16081 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16082 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16083 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16084 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16085 /* Vector replicate. Sizes 8 16 32. */
16086 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16087 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16088 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16089 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16090 /* VMOVN. Types I16 I32 I64. */
16091 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16092 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16093 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16094 /* VQMOVUN. Types S16 S32 S64. */
16095 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16096 /* VZIP / VUZP. Sizes 8 16 32. */
16097 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16098 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16099 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16100 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16101 /* VQABS / VQNEG. Types S8 S16 S32. */
16102 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16103 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16104 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16105 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16106 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16107 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16108 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16109 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16110 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16111 /* Reciprocal estimates. Types U32 F32. */
16112 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16113 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16114 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16115 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16116 /* VCLS. Types S8 S16 S32. */
16117 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16118 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16119 /* VCLZ. Types I8 I16 I32. */
16120 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16121 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16122 /* VCNT. Size 8. */
16123 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16124 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16125 /* Two address, untyped. */
16126 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16127 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16128 /* VTRN. Sizes 8 16 32. */
16129 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16130 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16132 /* Table lookup. Size 8. */
16133 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16134 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16136 #undef THUMB_VARIANT
16137 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16139 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16140 /* Neon element/structure load/store. */
16141 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16142 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16143 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16144 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16145 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16146 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16147 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16148 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16150 #undef THUMB_VARIANT
16151 #define THUMB_VARIANT &fpu_vfp_ext_v3
16153 #define ARM_VARIANT &fpu_vfp_ext_v3
16154 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16155 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16156 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16157 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16158 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16159 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16160 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16161 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16162 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16163 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16164 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16165 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16166 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16167 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16168 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16169 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16170 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16171 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16173 #undef THUMB_VARIANT
16175 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16176 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16177 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16178 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16179 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16180 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16181 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16182 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16183 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16186 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16187 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16188 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16189 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16190 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16191 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16192 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16193 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16194 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16195 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16196 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16197 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16198 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16199 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16200 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16201 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16202 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16203 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16204 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16205 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16206 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16207 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16208 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16209 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16210 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16211 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16212 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16213 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16214 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16215 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16216 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16217 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16218 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16219 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16220 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16221 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16222 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16223 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16224 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16225 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16226 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16227 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16228 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16229 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16230 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16231 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16232 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16233 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16234 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16235 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16236 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16237 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16238 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16239 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16240 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16241 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16242 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16243 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16244 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16245 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16246 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16247 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16248 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16249 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16250 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16251 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16252 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16253 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16254 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16255 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16256 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16257 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16258 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16259 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16260 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16261 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16262 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16263 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16264 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16265 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16266 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16267 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16268 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16269 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16270 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16271 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16272 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16273 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16274 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16275 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16276 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16277 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16278 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16279 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16280 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16281 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16282 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16283 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16284 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16285 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16286 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16287 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16288 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16289 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16290 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16291 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16292 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16293 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16294 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16295 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16296 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16297 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16298 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16299 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16300 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16301 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16302 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16303 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16304 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16305 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16306 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16307 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16308 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16309 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16310 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16311 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16312 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16313 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16314 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16315 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16316 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16317 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16318 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16319 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16320 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16321 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16322 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16323 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16324 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16325 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16326 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16327 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16328 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16329 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16330 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16331 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16332 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16333 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16334 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16335 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16336 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16337 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16338 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16339 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16340 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16341 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16342 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16343 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16344 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16345 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16346 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16347 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16348 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16351 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16352 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16353 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16354 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16355 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16356 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16357 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16358 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16359 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16360 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16361 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16362 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16363 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16364 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16365 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16366 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16367 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16368 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16369 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16370 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16371 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16372 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16373 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16374 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16375 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16376 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16377 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16378 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16379 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16380 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16381 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16382 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16383 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16384 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16385 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16386 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16387 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16388 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16389 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16390 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16391 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16392 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16393 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16394 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16395 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16396 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16397 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16398 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16399 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16400 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16401 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16402 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16403 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16404 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16405 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16406 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16407 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16408 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16411 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16412 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16413 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16414 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16415 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16416 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16417 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16418 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16419 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16420 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16421 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16422 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16423 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16424 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16425 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16426 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16427 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16428 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16429 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16430 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16431 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16432 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16433 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16434 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16435 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16436 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16437 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16438 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16439 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16440 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16441 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16442 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16443 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16444 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16445 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16446 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16447 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16448 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16449 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16450 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16451 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16452 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16453 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16454 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16455 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16456 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16457 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16458 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16459 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16460 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16461 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16462 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16463 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16464 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16465 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16466 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16467 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16468 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16469 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16470 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16471 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16472 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16473 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16474 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16475 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16476 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16477 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16478 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16479 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16480 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16481 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16482 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16483 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16484 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16485 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16486 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16487 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16490 #undef THUMB_VARIANT
16517 /* MD interface: bits in the object file. */
16519 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16520 for use in the a.out file, and stores them in the array pointed to by buf.
16521 This knows about the endian-ness of the target machine and does
16522 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16523 2 (short) and 4 (long) Floating numbers are put out as a series of
16524 LITTLENUMS (shorts, here at least). */
16527 md_number_to_chars (char * buf
, valueT val
, int n
)
16529 if (target_big_endian
)
16530 number_to_chars_bigendian (buf
, val
, n
);
16532 number_to_chars_littleendian (buf
, val
, n
);
16536 md_chars_to_number (char * buf
, int n
)
16539 unsigned char * where
= (unsigned char *) buf
;
16541 if (target_big_endian
)
16546 result
|= (*where
++ & 255);
16554 result
|= (where
[n
] & 255);
16561 /* MD interface: Sections. */
16563 /* Estimate the size of a frag before relaxing. Assume everything fits in
16567 md_estimate_size_before_relax (fragS
* fragp
,
16568 segT segtype ATTRIBUTE_UNUSED
)
16574 /* Convert a machine dependent frag. */
16577 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16579 unsigned long insn
;
16580 unsigned long old_op
;
16588 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16590 old_op
= bfd_get_16(abfd
, buf
);
16591 if (fragp
->fr_symbol
)
16593 exp
.X_op
= O_symbol
;
16594 exp
.X_add_symbol
= fragp
->fr_symbol
;
16598 exp
.X_op
= O_constant
;
16600 exp
.X_add_number
= fragp
->fr_offset
;
16601 opcode
= fragp
->fr_subtype
;
16604 case T_MNEM_ldr_pc
:
16605 case T_MNEM_ldr_pc2
:
16606 case T_MNEM_ldr_sp
:
16607 case T_MNEM_str_sp
:
16614 if (fragp
->fr_var
== 4)
16616 insn
= THUMB_OP32 (opcode
);
16617 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16619 insn
|= (old_op
& 0x700) << 4;
16623 insn
|= (old_op
& 7) << 12;
16624 insn
|= (old_op
& 0x38) << 13;
16626 insn
|= 0x00000c00;
16627 put_thumb32_insn (buf
, insn
);
16628 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16632 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16634 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16637 if (fragp
->fr_var
== 4)
16639 insn
= THUMB_OP32 (opcode
);
16640 insn
|= (old_op
& 0xf0) << 4;
16641 put_thumb32_insn (buf
, insn
);
16642 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16646 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16647 exp
.X_add_number
-= 4;
16655 if (fragp
->fr_var
== 4)
16657 int r0off
= (opcode
== T_MNEM_mov
16658 || opcode
== T_MNEM_movs
) ? 0 : 8;
16659 insn
= THUMB_OP32 (opcode
);
16660 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16661 insn
|= (old_op
& 0x700) << r0off
;
16662 put_thumb32_insn (buf
, insn
);
16663 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16667 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16672 if (fragp
->fr_var
== 4)
16674 insn
= THUMB_OP32(opcode
);
16675 put_thumb32_insn (buf
, insn
);
16676 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16679 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16683 if (fragp
->fr_var
== 4)
16685 insn
= THUMB_OP32(opcode
);
16686 insn
|= (old_op
& 0xf00) << 14;
16687 put_thumb32_insn (buf
, insn
);
16688 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16691 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16694 case T_MNEM_add_sp
:
16695 case T_MNEM_add_pc
:
16696 case T_MNEM_inc_sp
:
16697 case T_MNEM_dec_sp
:
16698 if (fragp
->fr_var
== 4)
16700 /* ??? Choose between add and addw. */
16701 insn
= THUMB_OP32 (opcode
);
16702 insn
|= (old_op
& 0xf0) << 4;
16703 put_thumb32_insn (buf
, insn
);
16704 if (opcode
== T_MNEM_add_pc
)
16705 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16707 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16710 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16718 if (fragp
->fr_var
== 4)
16720 insn
= THUMB_OP32 (opcode
);
16721 insn
|= (old_op
& 0xf0) << 4;
16722 insn
|= (old_op
& 0xf) << 16;
16723 put_thumb32_insn (buf
, insn
);
16724 if (insn
& (1 << 20))
16725 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16727 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16730 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16736 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16738 fixp
->fx_file
= fragp
->fr_file
;
16739 fixp
->fx_line
= fragp
->fr_line
;
16740 fragp
->fr_fix
+= fragp
->fr_var
;
16743 /* Return the size of a relaxable immediate operand instruction.
16744 SHIFT and SIZE specify the form of the allowable immediate. */
16746 relax_immediate (fragS
*fragp
, int size
, int shift
)
16752 /* ??? Should be able to do better than this. */
16753 if (fragp
->fr_symbol
)
16756 low
= (1 << shift
) - 1;
16757 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16758 offset
= fragp
->fr_offset
;
16759 /* Force misaligned offsets to 32-bit variant. */
16762 if (offset
& ~mask
)
16767 /* Get the address of a symbol during relaxation. */
16769 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
16775 sym
= fragp
->fr_symbol
;
16776 sym_frag
= symbol_get_frag (sym
);
16777 know (S_GET_SEGMENT (sym
) != absolute_section
16778 || sym_frag
== &zero_address_frag
);
16779 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
16781 /* If frag has yet to be reached on this pass, assume it will
16782 move by STRETCH just as we did. If this is not so, it will
16783 be because some frag between grows, and that will force
16787 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16791 /* Adjust stretch for any alignment frag. Note that if have
16792 been expanding the earlier code, the symbol may be
16793 defined in what appears to be an earlier frag. FIXME:
16794 This doesn't handle the fr_subtype field, which specifies
16795 a maximum number of bytes to skip when doing an
16797 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16799 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16802 stretch
= - ((- stretch
)
16803 & ~ ((1 << (int) f
->fr_offset
) - 1));
16805 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16817 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16820 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
16825 /* Assume worst case for symbols not known to be in the same section. */
16826 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16827 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16830 val
= relaxed_symbol_addr (fragp
, stretch
);
16831 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16832 addr
= (addr
+ 4) & ~3;
16833 /* Force misaligned targets to 32-bit variant. */
16837 if (val
< 0 || val
> 1020)
16842 /* Return the size of a relaxable add/sub immediate instruction. */
16844 relax_addsub (fragS
*fragp
, asection
*sec
)
16849 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16850 op
= bfd_get_16(sec
->owner
, buf
);
16851 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16852 return relax_immediate (fragp
, 8, 0);
16854 return relax_immediate (fragp
, 3, 0);
16858 /* Return the size of a relaxable branch instruction. BITS is the
16859 size of the offset field in the narrow instruction. */
16862 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
16868 /* Assume worst case for symbols not known to be in the same section. */
16869 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16870 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16873 val
= relaxed_symbol_addr (fragp
, stretch
);
16874 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16877 /* Offset is a signed value *2 */
16879 if (val
>= limit
|| val
< -limit
)
16885 /* Relax a machine dependent frag. This returns the amount by which
16886 the current size of the frag should change. */
16889 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16894 oldsize
= fragp
->fr_var
;
16895 switch (fragp
->fr_subtype
)
16897 case T_MNEM_ldr_pc2
:
16898 newsize
= relax_adr (fragp
, sec
, stretch
);
16900 case T_MNEM_ldr_pc
:
16901 case T_MNEM_ldr_sp
:
16902 case T_MNEM_str_sp
:
16903 newsize
= relax_immediate (fragp
, 8, 2);
16907 newsize
= relax_immediate (fragp
, 5, 2);
16911 newsize
= relax_immediate (fragp
, 5, 1);
16915 newsize
= relax_immediate (fragp
, 5, 0);
16918 newsize
= relax_adr (fragp
, sec
, stretch
);
16924 newsize
= relax_immediate (fragp
, 8, 0);
16927 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
16930 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
16932 case T_MNEM_add_sp
:
16933 case T_MNEM_add_pc
:
16934 newsize
= relax_immediate (fragp
, 8, 2);
16936 case T_MNEM_inc_sp
:
16937 case T_MNEM_dec_sp
:
16938 newsize
= relax_immediate (fragp
, 7, 2);
16944 newsize
= relax_addsub (fragp
, sec
);
16950 fragp
->fr_var
= newsize
;
16951 /* Freeze wide instructions that are at or before the same location as
16952 in the previous pass. This avoids infinite loops.
16953 Don't freeze them unconditionally because targets may be artificially
16954 misaligned by the expansion of preceding frags. */
16955 if (stretch
<= 0 && newsize
> 2)
16957 md_convert_frag (sec
->owner
, sec
, fragp
);
16961 return newsize
- oldsize
;
16964 /* Round up a section size to the appropriate boundary. */
16967 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16970 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16971 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16973 /* For a.out, force the section size to be aligned. If we don't do
16974 this, BFD will align it for us, but it will not write out the
16975 final bytes of the section. This may be a bug in BFD, but it is
16976 easier to fix it here since that is how the other a.out targets
16980 align
= bfd_get_section_alignment (stdoutput
, segment
);
16981 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
16988 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16989 of an rs_align_code fragment. */
16992 arm_handle_align (fragS
* fragP
)
16994 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16995 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16996 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16997 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16999 int bytes
, fix
, noop_size
;
17003 if (fragP
->fr_type
!= rs_align_code
)
17006 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17007 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17010 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17011 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17013 if (fragP
->tc_frag_data
)
17015 if (target_big_endian
)
17016 noop
= thumb_bigend_noop
;
17019 noop_size
= sizeof (thumb_noop
);
17023 if (target_big_endian
)
17024 noop
= arm_bigend_noop
;
17027 noop_size
= sizeof (arm_noop
);
17030 if (bytes
& (noop_size
- 1))
17032 fix
= bytes
& (noop_size
- 1);
17033 memset (p
, 0, fix
);
17038 while (bytes
>= noop_size
)
17040 memcpy (p
, noop
, noop_size
);
17042 bytes
-= noop_size
;
17046 fragP
->fr_fix
+= fix
;
17047 fragP
->fr_var
= noop_size
;
17050 /* Called from md_do_align. Used to create an alignment
17051 frag in a code section. */
17054 arm_frag_align_code (int n
, int max
)
17058 /* We assume that there will never be a requirement
17059 to support alignments greater than 32 bytes. */
17060 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17061 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17063 p
= frag_var (rs_align_code
,
17064 MAX_MEM_FOR_RS_ALIGN_CODE
,
17066 (relax_substateT
) max
,
17073 /* Perform target specific initialisation of a frag. */
17076 arm_init_frag (fragS
* fragP
)
17078 /* Record whether this frag is in an ARM or a THUMB area. */
17079 fragP
->tc_frag_data
= thumb_mode
;
17083 /* When we change sections we need to issue a new mapping symbol. */
17086 arm_elf_change_section (void)
17089 segment_info_type
*seginfo
;
17091 /* Link an unlinked unwind index table section to the .text section. */
17092 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17093 && elf_linked_to_section (now_seg
) == NULL
)
17094 elf_linked_to_section (now_seg
) = text_section
;
17096 if (!SEG_NORMAL (now_seg
))
17099 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17101 /* We can ignore sections that only contain debug info. */
17102 if ((flags
& SEC_ALLOC
) == 0)
17105 seginfo
= seg_info (now_seg
);
17106 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17107 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17111 arm_elf_section_type (const char * str
, size_t len
)
17113 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17114 return SHT_ARM_EXIDX
;
17119 /* Code to deal with unwinding tables. */
17121 static void add_unwind_adjustsp (offsetT
);
17123 /* Generate any deferred unwind frame offset. */
17126 flush_pending_unwind (void)
17130 offset
= unwind
.pending_offset
;
17131 unwind
.pending_offset
= 0;
17133 add_unwind_adjustsp (offset
);
17136 /* Add an opcode to this list for this function. Two-byte opcodes should
17137 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17141 add_unwind_opcode (valueT op
, int length
)
17143 /* Add any deferred stack adjustment. */
17144 if (unwind
.pending_offset
)
17145 flush_pending_unwind ();
17147 unwind
.sp_restored
= 0;
17149 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17151 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17152 if (unwind
.opcodes
)
17153 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17154 unwind
.opcode_alloc
);
17156 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17161 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17163 unwind
.opcode_count
++;
17167 /* Add unwind opcodes to adjust the stack pointer. */
17170 add_unwind_adjustsp (offsetT offset
)
17174 if (offset
> 0x200)
17176 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17181 /* Long form: 0xb2, uleb128. */
17182 /* This might not fit in a word so add the individual bytes,
17183 remembering the list is built in reverse order. */
17184 o
= (valueT
) ((offset
- 0x204) >> 2);
17186 add_unwind_opcode (0, 1);
17188 /* Calculate the uleb128 encoding of the offset. */
17192 bytes
[n
] = o
& 0x7f;
17198 /* Add the insn. */
17200 add_unwind_opcode (bytes
[n
- 1], 1);
17201 add_unwind_opcode (0xb2, 1);
17203 else if (offset
> 0x100)
17205 /* Two short opcodes. */
17206 add_unwind_opcode (0x3f, 1);
17207 op
= (offset
- 0x104) >> 2;
17208 add_unwind_opcode (op
, 1);
17210 else if (offset
> 0)
17212 /* Short opcode. */
17213 op
= (offset
- 4) >> 2;
17214 add_unwind_opcode (op
, 1);
17216 else if (offset
< 0)
17219 while (offset
> 0x100)
17221 add_unwind_opcode (0x7f, 1);
17224 op
= ((offset
- 4) >> 2) | 0x40;
17225 add_unwind_opcode (op
, 1);
17229 /* Finish the list of unwind opcodes for this function. */
17231 finish_unwind_opcodes (void)
17235 if (unwind
.fp_used
)
17237 /* Adjust sp as necessary. */
17238 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17239 flush_pending_unwind ();
17241 /* After restoring sp from the frame pointer. */
17242 op
= 0x90 | unwind
.fp_reg
;
17243 add_unwind_opcode (op
, 1);
17246 flush_pending_unwind ();
17250 /* Start an exception table entry. If idx is nonzero this is an index table
17254 start_unwind_section (const segT text_seg
, int idx
)
17256 const char * text_name
;
17257 const char * prefix
;
17258 const char * prefix_once
;
17259 const char * group_name
;
17263 size_t sec_name_len
;
17270 prefix
= ELF_STRING_ARM_unwind
;
17271 prefix_once
= ELF_STRING_ARM_unwind_once
;
17272 type
= SHT_ARM_EXIDX
;
17276 prefix
= ELF_STRING_ARM_unwind_info
;
17277 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17278 type
= SHT_PROGBITS
;
17281 text_name
= segment_name (text_seg
);
17282 if (streq (text_name
, ".text"))
17285 if (strncmp (text_name
, ".gnu.linkonce.t.",
17286 strlen (".gnu.linkonce.t.")) == 0)
17288 prefix
= prefix_once
;
17289 text_name
+= strlen (".gnu.linkonce.t.");
17292 prefix_len
= strlen (prefix
);
17293 text_len
= strlen (text_name
);
17294 sec_name_len
= prefix_len
+ text_len
;
17295 sec_name
= xmalloc (sec_name_len
+ 1);
17296 memcpy (sec_name
, prefix
, prefix_len
);
17297 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17298 sec_name
[prefix_len
+ text_len
] = '\0';
17304 /* Handle COMDAT group. */
17305 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17307 group_name
= elf_group_name (text_seg
);
17308 if (group_name
== NULL
)
17310 as_bad (_("Group section `%s' has no group signature"),
17311 segment_name (text_seg
));
17312 ignore_rest_of_line ();
17315 flags
|= SHF_GROUP
;
17319 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17321 /* Set the section link for index tables. */
17323 elf_linked_to_section (now_seg
) = text_seg
;
17327 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17328 personality routine data. Returns zero, or the index table value for
17329 and inline entry. */
17332 create_unwind_entry (int have_data
)
17337 /* The current word of data. */
17339 /* The number of bytes left in this word. */
17342 finish_unwind_opcodes ();
17344 /* Remember the current text section. */
17345 unwind
.saved_seg
= now_seg
;
17346 unwind
.saved_subseg
= now_subseg
;
17348 start_unwind_section (now_seg
, 0);
17350 if (unwind
.personality_routine
== NULL
)
17352 if (unwind
.personality_index
== -2)
17355 as_bad (_("handlerdata in cantunwind frame"));
17356 return 1; /* EXIDX_CANTUNWIND. */
17359 /* Use a default personality routine if none is specified. */
17360 if (unwind
.personality_index
== -1)
17362 if (unwind
.opcode_count
> 3)
17363 unwind
.personality_index
= 1;
17365 unwind
.personality_index
= 0;
17368 /* Space for the personality routine entry. */
17369 if (unwind
.personality_index
== 0)
17371 if (unwind
.opcode_count
> 3)
17372 as_bad (_("too many unwind opcodes for personality routine 0"));
17376 /* All the data is inline in the index table. */
17379 while (unwind
.opcode_count
> 0)
17381 unwind
.opcode_count
--;
17382 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17386 /* Pad with "finish" opcodes. */
17388 data
= (data
<< 8) | 0xb0;
17395 /* We get two opcodes "free" in the first word. */
17396 size
= unwind
.opcode_count
- 2;
17399 /* An extra byte is required for the opcode count. */
17400 size
= unwind
.opcode_count
+ 1;
17402 size
= (size
+ 3) >> 2;
17404 as_bad (_("too many unwind opcodes"));
17406 frag_align (2, 0, 0);
17407 record_alignment (now_seg
, 2);
17408 unwind
.table_entry
= expr_build_dot ();
17410 /* Allocate the table entry. */
17411 ptr
= frag_more ((size
<< 2) + 4);
17412 where
= frag_now_fix () - ((size
<< 2) + 4);
17414 switch (unwind
.personality_index
)
17417 /* ??? Should this be a PLT generating relocation? */
17418 /* Custom personality routine. */
17419 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17420 BFD_RELOC_ARM_PREL31
);
17425 /* Set the first byte to the number of additional words. */
17430 /* ABI defined personality routines. */
17432 /* Three opcodes bytes are packed into the first word. */
17439 /* The size and first two opcode bytes go in the first word. */
17440 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17445 /* Should never happen. */
17449 /* Pack the opcodes into words (MSB first), reversing the list at the same
17451 while (unwind
.opcode_count
> 0)
17455 md_number_to_chars (ptr
, data
, 4);
17460 unwind
.opcode_count
--;
17462 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17465 /* Finish off the last word. */
17468 /* Pad with "finish" opcodes. */
17470 data
= (data
<< 8) | 0xb0;
17472 md_number_to_chars (ptr
, data
, 4);
17477 /* Add an empty descriptor if there is no user-specified data. */
17478 ptr
= frag_more (4);
17479 md_number_to_chars (ptr
, 0, 4);
17486 /* Initialize the DWARF-2 unwind information for this procedure. */
17489 tc_arm_frame_initial_instructions (void)
17491 cfi_add_CFA_def_cfa (REG_SP
, 0);
17493 #endif /* OBJ_ELF */
17495 /* Convert REGNAME to a DWARF-2 register number. */
17498 tc_arm_regname_to_dw2regnum (char *regname
)
17500 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17510 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17514 expr
.X_op
= O_secrel
;
17515 expr
.X_add_symbol
= symbol
;
17516 expr
.X_add_number
= 0;
17517 emit_expr (&expr
, size
);
17521 /* MD interface: Symbol and relocation handling. */
17523 /* Return the address within the segment that a PC-relative fixup is
17524 relative to. For ARM, PC-relative fixups applied to instructions
17525 are generally relative to the location of the fixup plus 8 bytes.
17526 Thumb branches are offset by 4, and Thumb loads relative to PC
17527 require special handling. */
17530 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17532 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17534 /* If this is pc-relative and we are going to emit a relocation
17535 then we just want to put out any pipeline compensation that the linker
17536 will need. Otherwise we want to use the calculated base.
17537 For WinCE we skip the bias for externals as well, since this
17538 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17540 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17541 || (arm_force_relocation (fixP
)
17543 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17548 switch (fixP
->fx_r_type
)
17550 /* PC relative addressing on the Thumb is slightly odd as the
17551 bottom two bits of the PC are forced to zero for the
17552 calculation. This happens *after* application of the
17553 pipeline offset. However, Thumb adrl already adjusts for
17554 this, so we need not do it again. */
17555 case BFD_RELOC_ARM_THUMB_ADD
:
17558 case BFD_RELOC_ARM_THUMB_OFFSET
:
17559 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17560 case BFD_RELOC_ARM_T32_ADD_PC12
:
17561 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17562 return (base
+ 4) & ~3;
17564 /* Thumb branches are simply offset by +4. */
17565 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17566 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17567 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17568 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17569 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17570 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17571 case BFD_RELOC_THUMB_PCREL_BLX
:
17574 /* ARM mode branches are offset by +8. However, the Windows CE
17575 loader expects the relocation not to take this into account. */
17576 case BFD_RELOC_ARM_PCREL_BRANCH
:
17577 case BFD_RELOC_ARM_PCREL_CALL
:
17578 case BFD_RELOC_ARM_PCREL_JUMP
:
17579 case BFD_RELOC_ARM_PCREL_BLX
:
17580 case BFD_RELOC_ARM_PLT32
:
17582 /* When handling fixups immediately, because we have already
17583 discovered the value of a symbol, or the address of the frag involved
17584 we must account for the offset by +8, as the OS loader will never see the reloc.
17585 see fixup_segment() in write.c
17586 The S_IS_EXTERNAL test handles the case of global symbols.
17587 Those need the calculated base, not just the pipe compensation the linker will need. */
17589 && fixP
->fx_addsy
!= NULL
17590 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17591 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17598 /* ARM mode loads relative to PC are also offset by +8. Unlike
17599 branches, the Windows CE loader *does* expect the relocation
17600 to take this into account. */
17601 case BFD_RELOC_ARM_OFFSET_IMM
:
17602 case BFD_RELOC_ARM_OFFSET_IMM8
:
17603 case BFD_RELOC_ARM_HWLITERAL
:
17604 case BFD_RELOC_ARM_LITERAL
:
17605 case BFD_RELOC_ARM_CP_OFF_IMM
:
17609 /* Other PC-relative relocations are un-offset. */
17615 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17616 Otherwise we have no need to default values of symbols. */
17619 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17622 if (name
[0] == '_' && name
[1] == 'G'
17623 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17627 if (symbol_find (name
))
17628 as_bad (_("GOT already in the symbol table"));
17630 GOT_symbol
= symbol_new (name
, undefined_section
,
17631 (valueT
) 0, & zero_address_frag
);
17641 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17642 computed as two separate immediate values, added together. We
17643 already know that this value cannot be computed by just one ARM
17646 static unsigned int
17647 validate_immediate_twopart (unsigned int val
,
17648 unsigned int * highpart
)
17653 for (i
= 0; i
< 32; i
+= 2)
17654 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17660 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17662 else if (a
& 0xff0000)
17664 if (a
& 0xff000000)
17666 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17670 assert (a
& 0xff000000);
17671 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17674 return (a
& 0xff) | (i
<< 7);
17681 validate_offset_imm (unsigned int val
, int hwse
)
17683 if ((hwse
&& val
> 255) || val
> 4095)
17688 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17689 negative immediate constant by altering the instruction. A bit of
17694 by inverting the second operand, and
17697 by negating the second operand. */
17700 negate_data_op (unsigned long * instruction
,
17701 unsigned long value
)
17704 unsigned long negated
, inverted
;
17706 negated
= encode_arm_immediate (-value
);
17707 inverted
= encode_arm_immediate (~value
);
17709 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17712 /* First negates. */
17713 case OPCODE_SUB
: /* ADD <-> SUB */
17714 new_inst
= OPCODE_ADD
;
17719 new_inst
= OPCODE_SUB
;
17723 case OPCODE_CMP
: /* CMP <-> CMN */
17724 new_inst
= OPCODE_CMN
;
17729 new_inst
= OPCODE_CMP
;
17733 /* Now Inverted ops. */
17734 case OPCODE_MOV
: /* MOV <-> MVN */
17735 new_inst
= OPCODE_MVN
;
17740 new_inst
= OPCODE_MOV
;
17744 case OPCODE_AND
: /* AND <-> BIC */
17745 new_inst
= OPCODE_BIC
;
17750 new_inst
= OPCODE_AND
;
17754 case OPCODE_ADC
: /* ADC <-> SBC */
17755 new_inst
= OPCODE_SBC
;
17760 new_inst
= OPCODE_ADC
;
17764 /* We cannot do anything. */
17769 if (value
== (unsigned) FAIL
)
17772 *instruction
&= OPCODE_MASK
;
17773 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17777 /* Like negate_data_op, but for Thumb-2. */
17779 static unsigned int
17780 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17784 unsigned int negated
, inverted
;
17786 negated
= encode_thumb32_immediate (-value
);
17787 inverted
= encode_thumb32_immediate (~value
);
17789 rd
= (*instruction
>> 8) & 0xf;
17790 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17793 /* ADD <-> SUB. Includes CMP <-> CMN. */
17794 case T2_OPCODE_SUB
:
17795 new_inst
= T2_OPCODE_ADD
;
17799 case T2_OPCODE_ADD
:
17800 new_inst
= T2_OPCODE_SUB
;
17804 /* ORR <-> ORN. Includes MOV <-> MVN. */
17805 case T2_OPCODE_ORR
:
17806 new_inst
= T2_OPCODE_ORN
;
17810 case T2_OPCODE_ORN
:
17811 new_inst
= T2_OPCODE_ORR
;
17815 /* AND <-> BIC. TST has no inverted equivalent. */
17816 case T2_OPCODE_AND
:
17817 new_inst
= T2_OPCODE_BIC
;
17824 case T2_OPCODE_BIC
:
17825 new_inst
= T2_OPCODE_AND
;
17830 case T2_OPCODE_ADC
:
17831 new_inst
= T2_OPCODE_SBC
;
17835 case T2_OPCODE_SBC
:
17836 new_inst
= T2_OPCODE_ADC
;
17840 /* We cannot do anything. */
17845 if (value
== (unsigned int)FAIL
)
17848 *instruction
&= T2_OPCODE_MASK
;
17849 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17853 /* Read a 32-bit thumb instruction from buf. */
17854 static unsigned long
17855 get_thumb32_insn (char * buf
)
17857 unsigned long insn
;
17858 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17859 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17865 /* We usually want to set the low bit on the address of thumb function
17866 symbols. In particular .word foo - . should have the low bit set.
17867 Generic code tries to fold the difference of two symbols to
17868 a constant. Prevent this and force a relocation when the first symbols
17869 is a thumb function. */
17871 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17873 if (op
== O_subtract
17874 && l
->X_op
== O_symbol
17875 && r
->X_op
== O_symbol
17876 && THUMB_IS_FUNC (l
->X_add_symbol
))
17878 l
->X_op
= O_subtract
;
17879 l
->X_op_symbol
= r
->X_add_symbol
;
17880 l
->X_add_number
-= r
->X_add_number
;
17883 /* Process as normal. */
17888 md_apply_fix (fixS
* fixP
,
17892 offsetT value
= * valP
;
17894 unsigned int newimm
;
17895 unsigned long temp
;
17897 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17899 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17901 /* Note whether this will delete the relocation. */
17903 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17906 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17907 consistency with the behaviour on 32-bit hosts. Remember value
17909 value
&= 0xffffffff;
17910 value
^= 0x80000000;
17911 value
-= 0x80000000;
17914 fixP
->fx_addnumber
= value
;
17916 /* Same treatment for fixP->fx_offset. */
17917 fixP
->fx_offset
&= 0xffffffff;
17918 fixP
->fx_offset
^= 0x80000000;
17919 fixP
->fx_offset
-= 0x80000000;
17921 switch (fixP
->fx_r_type
)
17923 case BFD_RELOC_NONE
:
17924 /* This will need to go in the object file. */
17928 case BFD_RELOC_ARM_IMMEDIATE
:
17929 /* We claim that this fixup has been processed here,
17930 even if in fact we generate an error because we do
17931 not have a reloc for it, so tc_gen_reloc will reject it. */
17935 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17938 _("undefined symbol %s used as an immediate value"),
17939 S_GET_NAME (fixP
->fx_addsy
));
17943 newimm
= encode_arm_immediate (value
);
17944 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17946 /* If the instruction will fail, see if we can fix things up by
17947 changing the opcode. */
17948 if (newimm
== (unsigned int) FAIL
17949 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17952 _("invalid constant (%lx) after fixup"),
17953 (unsigned long) value
);
17957 newimm
|= (temp
& 0xfffff000);
17958 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17961 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17963 unsigned int highpart
= 0;
17964 unsigned int newinsn
= 0xe1a00000; /* nop. */
17966 newimm
= encode_arm_immediate (value
);
17967 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17969 /* If the instruction will fail, see if we can fix things up by
17970 changing the opcode. */
17971 if (newimm
== (unsigned int) FAIL
17972 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17974 /* No ? OK - try using two ADD instructions to generate
17976 newimm
= validate_immediate_twopart (value
, & highpart
);
17978 /* Yes - then make sure that the second instruction is
17980 if (newimm
!= (unsigned int) FAIL
)
17982 /* Still No ? Try using a negated value. */
17983 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17984 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17985 /* Otherwise - give up. */
17988 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17989 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17994 /* Replace the first operand in the 2nd instruction (which
17995 is the PC) with the destination register. We have
17996 already added in the PC in the first instruction and we
17997 do not want to do it again. */
17998 newinsn
&= ~ 0xf0000;
17999 newinsn
|= ((newinsn
& 0x0f000) << 4);
18002 newimm
|= (temp
& 0xfffff000);
18003 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18005 highpart
|= (newinsn
& 0xfffff000);
18006 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18010 case BFD_RELOC_ARM_OFFSET_IMM
:
18011 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18014 case BFD_RELOC_ARM_LITERAL
:
18020 if (validate_offset_imm (value
, 0) == FAIL
)
18022 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18023 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18024 _("invalid literal constant: pool needs to be closer"));
18026 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18027 _("bad immediate value for offset (%ld)"),
18032 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18033 newval
&= 0xff7ff000;
18034 newval
|= value
| (sign
? INDEX_UP
: 0);
18035 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18038 case BFD_RELOC_ARM_OFFSET_IMM8
:
18039 case BFD_RELOC_ARM_HWLITERAL
:
18045 if (validate_offset_imm (value
, 1) == FAIL
)
18047 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18049 _("invalid literal constant: pool needs to be closer"));
18051 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18056 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18057 newval
&= 0xff7ff0f0;
18058 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18059 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18062 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18063 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18065 _("bad immediate value for offset (%ld)"), (long) value
);
18068 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18070 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18073 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18074 /* This is a complicated relocation used for all varieties of Thumb32
18075 load/store instruction with immediate offset:
18077 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18078 *4, optional writeback(W)
18079 (doubleword load/store)
18081 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18082 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18083 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18084 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18085 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18087 Uppercase letters indicate bits that are already encoded at
18088 this point. Lowercase letters are our problem. For the
18089 second block of instructions, the secondary opcode nybble
18090 (bits 8..11) is present, and bit 23 is zero, even if this is
18091 a PC-relative operation. */
18092 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18094 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18096 if ((newval
& 0xf0000000) == 0xe0000000)
18098 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18100 newval
|= (1 << 23);
18103 if (value
% 4 != 0)
18105 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18106 _("offset not a multiple of 4"));
18112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18113 _("offset out of range"));
18118 else if ((newval
& 0x000f0000) == 0x000f0000)
18120 /* PC-relative, 12-bit offset. */
18122 newval
|= (1 << 23);
18127 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18128 _("offset out of range"));
18133 else if ((newval
& 0x00000100) == 0x00000100)
18135 /* Writeback: 8-bit, +/- offset. */
18137 newval
|= (1 << 9);
18142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18143 _("offset out of range"));
18148 else if ((newval
& 0x00000f00) == 0x00000e00)
18150 /* T-instruction: positive 8-bit offset. */
18151 if (value
< 0 || value
> 0xff)
18153 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18154 _("offset out of range"));
18162 /* Positive 12-bit or negative 8-bit offset. */
18166 newval
|= (1 << 23);
18176 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18177 _("offset out of range"));
18184 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18185 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18188 case BFD_RELOC_ARM_SHIFT_IMM
:
18189 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18190 if (((unsigned long) value
) > 32
18192 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18194 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18195 _("shift expression is too large"));
18200 /* Shifts of zero must be done as lsl. */
18202 else if (value
== 32)
18204 newval
&= 0xfffff07f;
18205 newval
|= (value
& 0x1f) << 7;
18206 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18209 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18210 case BFD_RELOC_ARM_T32_ADD_IMM
:
18211 case BFD_RELOC_ARM_T32_IMM12
:
18212 case BFD_RELOC_ARM_T32_ADD_PC12
:
18213 /* We claim that this fixup has been processed here,
18214 even if in fact we generate an error because we do
18215 not have a reloc for it, so tc_gen_reloc will reject it. */
18219 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18221 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18222 _("undefined symbol %s used as an immediate value"),
18223 S_GET_NAME (fixP
->fx_addsy
));
18227 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18229 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18232 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18233 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18235 newimm
= encode_thumb32_immediate (value
);
18236 if (newimm
== (unsigned int) FAIL
)
18237 newimm
= thumb32_negate_data_op (&newval
, value
);
18239 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18240 && newimm
== (unsigned int) FAIL
)
18242 /* Turn add/sum into addw/subw. */
18243 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18244 newval
= (newval
& 0xfeffffff) | 0x02000000;
18246 /* 12 bit immediate for addw/subw. */
18250 newval
^= 0x00a00000;
18253 newimm
= (unsigned int) FAIL
;
18258 if (newimm
== (unsigned int)FAIL
)
18260 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18261 _("invalid constant (%lx) after fixup"),
18262 (unsigned long) value
);
18266 newval
|= (newimm
& 0x800) << 15;
18267 newval
|= (newimm
& 0x700) << 4;
18268 newval
|= (newimm
& 0x0ff);
18270 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18271 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18274 case BFD_RELOC_ARM_SMC
:
18275 if (((unsigned long) value
) > 0xffff)
18276 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18277 _("invalid smc expression"));
18278 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18279 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18280 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18283 case BFD_RELOC_ARM_SWI
:
18284 if (fixP
->tc_fix_data
!= 0)
18286 if (((unsigned long) value
) > 0xff)
18287 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18288 _("invalid swi expression"));
18289 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18291 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18295 if (((unsigned long) value
) > 0x00ffffff)
18296 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18297 _("invalid swi expression"));
18298 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18300 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18304 case BFD_RELOC_ARM_MULTI
:
18305 if (((unsigned long) value
) > 0xffff)
18306 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18307 _("invalid expression in load/store multiple"));
18308 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18309 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18313 case BFD_RELOC_ARM_PCREL_CALL
:
18314 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18315 if ((newval
& 0xf0000000) == 0xf0000000)
18319 goto arm_branch_common
;
18321 case BFD_RELOC_ARM_PCREL_JUMP
:
18322 case BFD_RELOC_ARM_PLT32
:
18324 case BFD_RELOC_ARM_PCREL_BRANCH
:
18326 goto arm_branch_common
;
18328 case BFD_RELOC_ARM_PCREL_BLX
:
18331 /* We are going to store value (shifted right by two) in the
18332 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18333 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18334 also be be clear. */
18336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18337 _("misaligned branch destination"));
18338 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18339 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18340 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18341 _("branch out of range"));
18343 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18345 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18346 newval
|= (value
>> 2) & 0x00ffffff;
18347 /* Set the H bit on BLX instructions. */
18351 newval
|= 0x01000000;
18353 newval
&= ~0x01000000;
18355 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18359 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18360 /* CBZ can only branch forward. */
18362 /* Attempts to use CBZ to branch to the next instruction
18363 (which, strictly speaking, are prohibited) will be turned into
18366 FIXME: It may be better to remove the instruction completely and
18367 perform relaxation. */
18370 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18371 newval
= 0xbf00; /* NOP encoding T1 */
18372 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18378 _("branch out of range"));
18380 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18382 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18383 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18384 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18389 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18390 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18391 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18392 _("branch out of range"));
18394 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18396 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18397 newval
|= (value
& 0x1ff) >> 1;
18398 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18402 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18403 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18405 _("branch out of range"));
18407 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18409 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18410 newval
|= (value
& 0xfff) >> 1;
18411 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18415 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18416 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18417 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18418 _("conditional branch out of range"));
18420 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18423 addressT S
, J1
, J2
, lo
, hi
;
18425 S
= (value
& 0x00100000) >> 20;
18426 J2
= (value
& 0x00080000) >> 19;
18427 J1
= (value
& 0x00040000) >> 18;
18428 hi
= (value
& 0x0003f000) >> 12;
18429 lo
= (value
& 0x00000ffe) >> 1;
18431 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18432 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18433 newval
|= (S
<< 10) | hi
;
18434 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18435 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18436 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18440 case BFD_RELOC_THUMB_PCREL_BLX
:
18441 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18442 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18443 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18444 _("branch out of range"));
18446 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18447 /* For a BLX instruction, make sure that the relocation is rounded up
18448 to a word boundary. This follows the semantics of the instruction
18449 which specifies that bit 1 of the target address will come from bit
18450 1 of the base address. */
18451 value
= (value
+ 1) & ~ 1;
18453 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18457 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18458 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18459 newval
|= (value
& 0x7fffff) >> 12;
18460 newval2
|= (value
& 0xfff) >> 1;
18461 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18462 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18466 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18467 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18469 _("branch out of range"));
18471 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18474 addressT S
, I1
, I2
, lo
, hi
;
18476 S
= (value
& 0x01000000) >> 24;
18477 I1
= (value
& 0x00800000) >> 23;
18478 I2
= (value
& 0x00400000) >> 22;
18479 hi
= (value
& 0x003ff000) >> 12;
18480 lo
= (value
& 0x00000ffe) >> 1;
18485 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18486 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18487 newval
|= (S
<< 10) | hi
;
18488 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18489 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18490 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18495 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18496 md_number_to_chars (buf
, value
, 1);
18500 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18501 md_number_to_chars (buf
, value
, 2);
18505 case BFD_RELOC_ARM_TLS_GD32
:
18506 case BFD_RELOC_ARM_TLS_LE32
:
18507 case BFD_RELOC_ARM_TLS_IE32
:
18508 case BFD_RELOC_ARM_TLS_LDM32
:
18509 case BFD_RELOC_ARM_TLS_LDO32
:
18510 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18513 case BFD_RELOC_ARM_GOT32
:
18514 case BFD_RELOC_ARM_GOTOFF
:
18515 case BFD_RELOC_ARM_TARGET2
:
18516 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18517 md_number_to_chars (buf
, 0, 4);
18521 case BFD_RELOC_RVA
:
18523 case BFD_RELOC_ARM_TARGET1
:
18524 case BFD_RELOC_ARM_ROSEGREL32
:
18525 case BFD_RELOC_ARM_SBREL32
:
18526 case BFD_RELOC_32_PCREL
:
18528 case BFD_RELOC_32_SECREL
:
18530 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18532 /* For WinCE we only do this for pcrel fixups. */
18533 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18535 md_number_to_chars (buf
, value
, 4);
18539 case BFD_RELOC_ARM_PREL31
:
18540 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18542 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18543 if ((value
^ (value
>> 1)) & 0x40000000)
18545 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18546 _("rel31 relocation overflow"));
18548 newval
|= value
& 0x7fffffff;
18549 md_number_to_chars (buf
, newval
, 4);
18554 case BFD_RELOC_ARM_CP_OFF_IMM
:
18555 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18556 if (value
< -1023 || value
> 1023 || (value
& 3))
18557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18558 _("co-processor offset out of range"));
18563 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18564 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18565 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18567 newval
= get_thumb32_insn (buf
);
18568 newval
&= 0xff7fff00;
18569 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18570 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18571 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18572 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18574 put_thumb32_insn (buf
, newval
);
18577 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18578 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18579 if (value
< -255 || value
> 255)
18580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18581 _("co-processor offset out of range"));
18583 goto cp_off_common
;
18585 case BFD_RELOC_ARM_THUMB_OFFSET
:
18586 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18587 /* Exactly what ranges, and where the offset is inserted depends
18588 on the type of instruction, we can establish this from the
18590 switch (newval
>> 12)
18592 case 4: /* PC load. */
18593 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18594 forced to zero for these loads; md_pcrel_from has already
18595 compensated for this. */
18597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18598 _("invalid offset, target not word aligned (0x%08lX)"),
18599 (((unsigned long) fixP
->fx_frag
->fr_address
18600 + (unsigned long) fixP
->fx_where
) & ~3)
18601 + (unsigned long) value
);
18603 if (value
& ~0x3fc)
18604 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18605 _("invalid offset, value too big (0x%08lX)"),
18608 newval
|= value
>> 2;
18611 case 9: /* SP load/store. */
18612 if (value
& ~0x3fc)
18613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18614 _("invalid offset, value too big (0x%08lX)"),
18616 newval
|= value
>> 2;
18619 case 6: /* Word load/store. */
18621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18622 _("invalid offset, value too big (0x%08lX)"),
18624 newval
|= value
<< 4; /* 6 - 2. */
18627 case 7: /* Byte load/store. */
18629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18630 _("invalid offset, value too big (0x%08lX)"),
18632 newval
|= value
<< 6;
18635 case 8: /* Halfword load/store. */
18637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18638 _("invalid offset, value too big (0x%08lX)"),
18640 newval
|= value
<< 5; /* 6 - 1. */
18644 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18645 "Unable to process relocation for thumb opcode: %lx",
18646 (unsigned long) newval
);
18649 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18652 case BFD_RELOC_ARM_THUMB_ADD
:
18653 /* This is a complicated relocation, since we use it for all of
18654 the following immediate relocations:
18658 9bit ADD/SUB SP word-aligned
18659 10bit ADD PC/SP word-aligned
18661 The type of instruction being processed is encoded in the
18668 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18670 int rd
= (newval
>> 4) & 0xf;
18671 int rs
= newval
& 0xf;
18672 int subtract
= !!(newval
& 0x8000);
18674 /* Check for HI regs, only very restricted cases allowed:
18675 Adjusting SP, and using PC or SP to get an address. */
18676 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18677 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18678 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18679 _("invalid Hi register with immediate"));
18681 /* If value is negative, choose the opposite instruction. */
18685 subtract
= !subtract
;
18687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18688 _("immediate value out of range"));
18693 if (value
& ~0x1fc)
18694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18695 _("invalid immediate for stack address calculation"));
18696 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18697 newval
|= value
>> 2;
18699 else if (rs
== REG_PC
|| rs
== REG_SP
)
18701 if (subtract
|| value
& ~0x3fc)
18702 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18703 _("invalid immediate for address calculation (value = 0x%08lX)"),
18704 (unsigned long) value
);
18705 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18707 newval
|= value
>> 2;
18712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18713 _("immediate value out of range"));
18714 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18715 newval
|= (rd
<< 8) | value
;
18720 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18721 _("immediate value out of range"));
18722 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18723 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18726 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18729 case BFD_RELOC_ARM_THUMB_IMM
:
18730 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18731 if (value
< 0 || value
> 255)
18732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18733 _("invalid immediate: %ld is out of range"),
18736 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18739 case BFD_RELOC_ARM_THUMB_SHIFT
:
18740 /* 5bit shift value (0..32). LSL cannot take 32. */
18741 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18742 temp
= newval
& 0xf800;
18743 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18745 _("invalid shift value: %ld"), (long) value
);
18746 /* Shifts of zero must be encoded as LSL. */
18748 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18749 /* Shifts of 32 are encoded as zero. */
18750 else if (value
== 32)
18752 newval
|= value
<< 6;
18753 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18756 case BFD_RELOC_VTABLE_INHERIT
:
18757 case BFD_RELOC_VTABLE_ENTRY
:
18761 case BFD_RELOC_ARM_MOVW
:
18762 case BFD_RELOC_ARM_MOVT
:
18763 case BFD_RELOC_ARM_THUMB_MOVW
:
18764 case BFD_RELOC_ARM_THUMB_MOVT
:
18765 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18767 /* REL format relocations are limited to a 16-bit addend. */
18768 if (!fixP
->fx_done
)
18770 if (value
< -0x1000 || value
> 0xffff)
18771 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18772 _("offset out of range"));
18774 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18775 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18780 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18781 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18783 newval
= get_thumb32_insn (buf
);
18784 newval
&= 0xfbf08f00;
18785 newval
|= (value
& 0xf000) << 4;
18786 newval
|= (value
& 0x0800) << 15;
18787 newval
|= (value
& 0x0700) << 4;
18788 newval
|= (value
& 0x00ff);
18789 put_thumb32_insn (buf
, newval
);
18793 newval
= md_chars_to_number (buf
, 4);
18794 newval
&= 0xfff0f000;
18795 newval
|= value
& 0x0fff;
18796 newval
|= (value
& 0xf000) << 4;
18797 md_number_to_chars (buf
, newval
, 4);
18802 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18803 case BFD_RELOC_ARM_ALU_PC_G0
:
18804 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18805 case BFD_RELOC_ARM_ALU_PC_G1
:
18806 case BFD_RELOC_ARM_ALU_PC_G2
:
18807 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18808 case BFD_RELOC_ARM_ALU_SB_G0
:
18809 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18810 case BFD_RELOC_ARM_ALU_SB_G1
:
18811 case BFD_RELOC_ARM_ALU_SB_G2
:
18812 assert (!fixP
->fx_done
);
18813 if (!seg
->use_rela_p
)
18816 bfd_vma encoded_addend
;
18817 bfd_vma addend_abs
= abs (value
);
18819 /* Check that the absolute value of the addend can be
18820 expressed as an 8-bit constant plus a rotation. */
18821 encoded_addend
= encode_arm_immediate (addend_abs
);
18822 if (encoded_addend
== (unsigned int) FAIL
)
18823 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18824 _("the offset 0x%08lX is not representable"),
18825 (unsigned long) addend_abs
);
18827 /* Extract the instruction. */
18828 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18830 /* If the addend is positive, use an ADD instruction.
18831 Otherwise use a SUB. Take care not to destroy the S bit. */
18832 insn
&= 0xff1fffff;
18838 /* Place the encoded addend into the first 12 bits of the
18840 insn
&= 0xfffff000;
18841 insn
|= encoded_addend
;
18843 /* Update the instruction. */
18844 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18848 case BFD_RELOC_ARM_LDR_PC_G0
:
18849 case BFD_RELOC_ARM_LDR_PC_G1
:
18850 case BFD_RELOC_ARM_LDR_PC_G2
:
18851 case BFD_RELOC_ARM_LDR_SB_G0
:
18852 case BFD_RELOC_ARM_LDR_SB_G1
:
18853 case BFD_RELOC_ARM_LDR_SB_G2
:
18854 assert (!fixP
->fx_done
);
18855 if (!seg
->use_rela_p
)
18858 bfd_vma addend_abs
= abs (value
);
18860 /* Check that the absolute value of the addend can be
18861 encoded in 12 bits. */
18862 if (addend_abs
>= 0x1000)
18863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18864 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18865 (unsigned long) addend_abs
);
18867 /* Extract the instruction. */
18868 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18870 /* If the addend is negative, clear bit 23 of the instruction.
18871 Otherwise set it. */
18873 insn
&= ~(1 << 23);
18877 /* Place the absolute value of the addend into the first 12 bits
18878 of the instruction. */
18879 insn
&= 0xfffff000;
18880 insn
|= addend_abs
;
18882 /* Update the instruction. */
18883 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18887 case BFD_RELOC_ARM_LDRS_PC_G0
:
18888 case BFD_RELOC_ARM_LDRS_PC_G1
:
18889 case BFD_RELOC_ARM_LDRS_PC_G2
:
18890 case BFD_RELOC_ARM_LDRS_SB_G0
:
18891 case BFD_RELOC_ARM_LDRS_SB_G1
:
18892 case BFD_RELOC_ARM_LDRS_SB_G2
:
18893 assert (!fixP
->fx_done
);
18894 if (!seg
->use_rela_p
)
18897 bfd_vma addend_abs
= abs (value
);
18899 /* Check that the absolute value of the addend can be
18900 encoded in 8 bits. */
18901 if (addend_abs
>= 0x100)
18902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18903 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18904 (unsigned long) addend_abs
);
18906 /* Extract the instruction. */
18907 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18909 /* If the addend is negative, clear bit 23 of the instruction.
18910 Otherwise set it. */
18912 insn
&= ~(1 << 23);
18916 /* Place the first four bits of the absolute value of the addend
18917 into the first 4 bits of the instruction, and the remaining
18918 four into bits 8 .. 11. */
18919 insn
&= 0xfffff0f0;
18920 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18922 /* Update the instruction. */
18923 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18927 case BFD_RELOC_ARM_LDC_PC_G0
:
18928 case BFD_RELOC_ARM_LDC_PC_G1
:
18929 case BFD_RELOC_ARM_LDC_PC_G2
:
18930 case BFD_RELOC_ARM_LDC_SB_G0
:
18931 case BFD_RELOC_ARM_LDC_SB_G1
:
18932 case BFD_RELOC_ARM_LDC_SB_G2
:
18933 assert (!fixP
->fx_done
);
18934 if (!seg
->use_rela_p
)
18937 bfd_vma addend_abs
= abs (value
);
18939 /* Check that the absolute value of the addend is a multiple of
18940 four and, when divided by four, fits in 8 bits. */
18941 if (addend_abs
& 0x3)
18942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18943 _("bad offset 0x%08lX (must be word-aligned)"),
18944 (unsigned long) addend_abs
);
18946 if ((addend_abs
>> 2) > 0xff)
18947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18948 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18949 (unsigned long) addend_abs
);
18951 /* Extract the instruction. */
18952 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18954 /* If the addend is negative, clear bit 23 of the instruction.
18955 Otherwise set it. */
18957 insn
&= ~(1 << 23);
18961 /* Place the addend (divided by four) into the first eight
18962 bits of the instruction. */
18963 insn
&= 0xfffffff0;
18964 insn
|= addend_abs
>> 2;
18966 /* Update the instruction. */
18967 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18971 case BFD_RELOC_UNUSED
:
18973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18974 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18978 /* Translate internal representation of relocation info to BFD target
18982 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18985 bfd_reloc_code_real_type code
;
18987 reloc
= xmalloc (sizeof (arelent
));
18989 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18990 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18991 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18993 if (fixp
->fx_pcrel
)
18995 if (section
->use_rela_p
)
18996 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18998 fixp
->fx_offset
= reloc
->address
;
19000 reloc
->addend
= fixp
->fx_offset
;
19002 switch (fixp
->fx_r_type
)
19005 if (fixp
->fx_pcrel
)
19007 code
= BFD_RELOC_8_PCREL
;
19012 if (fixp
->fx_pcrel
)
19014 code
= BFD_RELOC_16_PCREL
;
19019 if (fixp
->fx_pcrel
)
19021 code
= BFD_RELOC_32_PCREL
;
19025 case BFD_RELOC_ARM_MOVW
:
19026 if (fixp
->fx_pcrel
)
19028 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19032 case BFD_RELOC_ARM_MOVT
:
19033 if (fixp
->fx_pcrel
)
19035 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19039 case BFD_RELOC_ARM_THUMB_MOVW
:
19040 if (fixp
->fx_pcrel
)
19042 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19046 case BFD_RELOC_ARM_THUMB_MOVT
:
19047 if (fixp
->fx_pcrel
)
19049 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19053 case BFD_RELOC_NONE
:
19054 case BFD_RELOC_ARM_PCREL_BRANCH
:
19055 case BFD_RELOC_ARM_PCREL_BLX
:
19056 case BFD_RELOC_RVA
:
19057 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19058 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19059 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19060 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19061 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19062 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19063 case BFD_RELOC_THUMB_PCREL_BLX
:
19064 case BFD_RELOC_VTABLE_ENTRY
:
19065 case BFD_RELOC_VTABLE_INHERIT
:
19067 case BFD_RELOC_32_SECREL
:
19069 code
= fixp
->fx_r_type
;
19072 case BFD_RELOC_ARM_LITERAL
:
19073 case BFD_RELOC_ARM_HWLITERAL
:
19074 /* If this is called then the a literal has
19075 been referenced across a section boundary. */
19076 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19077 _("literal referenced across section boundary"));
19081 case BFD_RELOC_ARM_GOT32
:
19082 case BFD_RELOC_ARM_GOTOFF
:
19083 case BFD_RELOC_ARM_PLT32
:
19084 case BFD_RELOC_ARM_TARGET1
:
19085 case BFD_RELOC_ARM_ROSEGREL32
:
19086 case BFD_RELOC_ARM_SBREL32
:
19087 case BFD_RELOC_ARM_PREL31
:
19088 case BFD_RELOC_ARM_TARGET2
:
19089 case BFD_RELOC_ARM_TLS_LE32
:
19090 case BFD_RELOC_ARM_TLS_LDO32
:
19091 case BFD_RELOC_ARM_PCREL_CALL
:
19092 case BFD_RELOC_ARM_PCREL_JUMP
:
19093 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19094 case BFD_RELOC_ARM_ALU_PC_G0
:
19095 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19096 case BFD_RELOC_ARM_ALU_PC_G1
:
19097 case BFD_RELOC_ARM_ALU_PC_G2
:
19098 case BFD_RELOC_ARM_LDR_PC_G0
:
19099 case BFD_RELOC_ARM_LDR_PC_G1
:
19100 case BFD_RELOC_ARM_LDR_PC_G2
:
19101 case BFD_RELOC_ARM_LDRS_PC_G0
:
19102 case BFD_RELOC_ARM_LDRS_PC_G1
:
19103 case BFD_RELOC_ARM_LDRS_PC_G2
:
19104 case BFD_RELOC_ARM_LDC_PC_G0
:
19105 case BFD_RELOC_ARM_LDC_PC_G1
:
19106 case BFD_RELOC_ARM_LDC_PC_G2
:
19107 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19108 case BFD_RELOC_ARM_ALU_SB_G0
:
19109 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19110 case BFD_RELOC_ARM_ALU_SB_G1
:
19111 case BFD_RELOC_ARM_ALU_SB_G2
:
19112 case BFD_RELOC_ARM_LDR_SB_G0
:
19113 case BFD_RELOC_ARM_LDR_SB_G1
:
19114 case BFD_RELOC_ARM_LDR_SB_G2
:
19115 case BFD_RELOC_ARM_LDRS_SB_G0
:
19116 case BFD_RELOC_ARM_LDRS_SB_G1
:
19117 case BFD_RELOC_ARM_LDRS_SB_G2
:
19118 case BFD_RELOC_ARM_LDC_SB_G0
:
19119 case BFD_RELOC_ARM_LDC_SB_G1
:
19120 case BFD_RELOC_ARM_LDC_SB_G2
:
19121 code
= fixp
->fx_r_type
;
19124 case BFD_RELOC_ARM_TLS_GD32
:
19125 case BFD_RELOC_ARM_TLS_IE32
:
19126 case BFD_RELOC_ARM_TLS_LDM32
:
19127 /* BFD will include the symbol's address in the addend.
19128 But we don't want that, so subtract it out again here. */
19129 if (!S_IS_COMMON (fixp
->fx_addsy
))
19130 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19131 code
= fixp
->fx_r_type
;
19135 case BFD_RELOC_ARM_IMMEDIATE
:
19136 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19137 _("internal relocation (type: IMMEDIATE) not fixed up"));
19140 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19141 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19142 _("ADRL used for a symbol not defined in the same file"));
19145 case BFD_RELOC_ARM_OFFSET_IMM
:
19146 if (section
->use_rela_p
)
19148 code
= fixp
->fx_r_type
;
19152 if (fixp
->fx_addsy
!= NULL
19153 && !S_IS_DEFINED (fixp
->fx_addsy
)
19154 && S_IS_LOCAL (fixp
->fx_addsy
))
19156 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19157 _("undefined local label `%s'"),
19158 S_GET_NAME (fixp
->fx_addsy
));
19162 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19163 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19170 switch (fixp
->fx_r_type
)
19172 case BFD_RELOC_NONE
: type
= "NONE"; break;
19173 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19174 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19175 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19176 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19177 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19178 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19179 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19180 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19181 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19182 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19183 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19184 default: type
= _("<unknown>"); break;
19186 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19187 _("cannot represent %s relocation in this object file format"),
19194 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19196 && fixp
->fx_addsy
== GOT_symbol
)
19198 code
= BFD_RELOC_ARM_GOTPC
;
19199 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19203 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19205 if (reloc
->howto
== NULL
)
19207 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19208 _("cannot represent %s relocation in this object file format"),
19209 bfd_get_reloc_code_name (code
));
19213 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19214 vtable entry to be used in the relocation's section offset. */
19215 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19216 reloc
->address
= fixp
->fx_offset
;
19221 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19224 cons_fix_new_arm (fragS
* frag
,
19229 bfd_reloc_code_real_type type
;
19233 FIXME: @@ Should look at CPU word size. */
19237 type
= BFD_RELOC_8
;
19240 type
= BFD_RELOC_16
;
19244 type
= BFD_RELOC_32
;
19247 type
= BFD_RELOC_64
;
19252 if (exp
->X_op
== O_secrel
)
19254 exp
->X_op
= O_symbol
;
19255 type
= BFD_RELOC_32_SECREL
;
19259 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19262 #if defined OBJ_COFF || defined OBJ_ELF
19264 arm_validate_fix (fixS
* fixP
)
19266 /* If the destination of the branch is a defined symbol which does not have
19267 the THUMB_FUNC attribute, then we must be calling a function which has
19268 the (interfacearm) attribute. We look for the Thumb entry point to that
19269 function and change the branch to refer to that function instead. */
19270 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19271 && fixP
->fx_addsy
!= NULL
19272 && S_IS_DEFINED (fixP
->fx_addsy
)
19273 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19275 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19281 arm_force_relocation (struct fix
* fixp
)
19283 #if defined (OBJ_COFF) && defined (TE_PE)
19284 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19288 /* Resolve these relocations even if the symbol is extern or weak. */
19289 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19290 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19291 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19292 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19293 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19294 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19295 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19298 /* Always leave these relocations for the linker. */
19299 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19300 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19301 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19304 /* Always generate relocations against function symbols. */
19305 if (fixp
->fx_r_type
== BFD_RELOC_32
19307 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19310 return generic_force_reloc (fixp
);
19313 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19314 /* Relocations against function names must be left unadjusted,
19315 so that the linker can use this information to generate interworking
19316 stubs. The MIPS version of this function
19317 also prevents relocations that are mips-16 specific, but I do not
19318 know why it does this.
19321 There is one other problem that ought to be addressed here, but
19322 which currently is not: Taking the address of a label (rather
19323 than a function) and then later jumping to that address. Such
19324 addresses also ought to have their bottom bit set (assuming that
19325 they reside in Thumb code), but at the moment they will not. */
19328 arm_fix_adjustable (fixS
* fixP
)
19330 if (fixP
->fx_addsy
== NULL
)
19333 /* Preserve relocations against symbols with function type. */
19334 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19337 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19338 && fixP
->fx_subsy
== NULL
)
19341 /* We need the symbol name for the VTABLE entries. */
19342 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19343 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19346 /* Don't allow symbols to be discarded on GOT related relocs. */
19347 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19348 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19349 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19350 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19351 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19352 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19353 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19354 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19355 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19358 /* Similarly for group relocations. */
19359 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19360 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19361 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19366 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19371 elf32_arm_target_format (void)
19374 return (target_big_endian
19375 ? "elf32-bigarm-symbian"
19376 : "elf32-littlearm-symbian");
19377 #elif defined (TE_VXWORKS)
19378 return (target_big_endian
19379 ? "elf32-bigarm-vxworks"
19380 : "elf32-littlearm-vxworks");
19382 if (target_big_endian
)
19383 return "elf32-bigarm";
19385 return "elf32-littlearm";
19390 armelf_frob_symbol (symbolS
* symp
,
19393 elf_frob_symbol (symp
, puntp
);
19397 /* MD interface: Finalization. */
19399 /* A good place to do this, although this was probably not intended
19400 for this kind of use. We need to dump the literal pool before
19401 references are made to a null symbol pointer. */
19406 literal_pool
* pool
;
19408 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19410 /* Put it at the end of the relevant section. */
19411 subseg_set (pool
->section
, pool
->sub_section
);
19413 arm_elf_change_section ();
19419 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19423 arm_adjust_symtab (void)
19428 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19430 if (ARM_IS_THUMB (sym
))
19432 if (THUMB_IS_FUNC (sym
))
19434 /* Mark the symbol as a Thumb function. */
19435 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19436 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19437 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19439 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19440 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19442 as_bad (_("%s: unexpected function type: %d"),
19443 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19445 else switch (S_GET_STORAGE_CLASS (sym
))
19448 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19451 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19454 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19462 if (ARM_IS_INTERWORK (sym
))
19463 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19470 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19472 if (ARM_IS_THUMB (sym
))
19474 elf_symbol_type
* elf_sym
;
19476 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19477 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19479 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19480 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19482 /* If it's a .thumb_func, declare it as so,
19483 otherwise tag label as .code 16. */
19484 if (THUMB_IS_FUNC (sym
))
19485 elf_sym
->internal_elf_sym
.st_info
=
19486 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19487 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19488 elf_sym
->internal_elf_sym
.st_info
=
19489 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19496 /* MD interface: Initialization. */
19499 set_constant_flonums (void)
19503 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19504 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19508 /* Auto-select Thumb mode if it's the only available instruction set for the
19509 given architecture. */
19512 autoselect_thumb_from_cpu_variant (void)
19514 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19515 opcode_select (16);
19524 if ( (arm_ops_hsh
= hash_new ()) == NULL
19525 || (arm_cond_hsh
= hash_new ()) == NULL
19526 || (arm_shift_hsh
= hash_new ()) == NULL
19527 || (arm_psr_hsh
= hash_new ()) == NULL
19528 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19529 || (arm_reg_hsh
= hash_new ()) == NULL
19530 || (arm_reloc_hsh
= hash_new ()) == NULL
19531 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19532 as_fatal (_("virtual memory exhausted"));
19534 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19535 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
19536 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19537 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19538 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19539 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19540 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19541 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19542 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19543 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19544 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19545 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19547 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19549 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19550 (PTR
) (barrier_opt_names
+ i
));
19552 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19553 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19556 set_constant_flonums ();
19558 /* Set the cpu variant based on the command-line options. We prefer
19559 -mcpu= over -march= if both are set (as for GCC); and we prefer
19560 -mfpu= over any other way of setting the floating point unit.
19561 Use of legacy options with new options are faulted. */
19564 if (mcpu_cpu_opt
|| march_cpu_opt
)
19565 as_bad (_("use of old and new-style options to set CPU type"));
19567 mcpu_cpu_opt
= legacy_cpu
;
19569 else if (!mcpu_cpu_opt
)
19570 mcpu_cpu_opt
= march_cpu_opt
;
19575 as_bad (_("use of old and new-style options to set FPU type"));
19577 mfpu_opt
= legacy_fpu
;
19579 else if (!mfpu_opt
)
19581 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19582 /* Some environments specify a default FPU. If they don't, infer it
19583 from the processor. */
19585 mfpu_opt
= mcpu_fpu_opt
;
19587 mfpu_opt
= march_fpu_opt
;
19589 mfpu_opt
= &fpu_default
;
19595 if (mcpu_cpu_opt
!= NULL
)
19596 mfpu_opt
= &fpu_default
;
19597 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19598 mfpu_opt
= &fpu_arch_vfp_v2
;
19600 mfpu_opt
= &fpu_arch_fpa
;
19606 mcpu_cpu_opt
= &cpu_default
;
19607 selected_cpu
= cpu_default
;
19611 selected_cpu
= *mcpu_cpu_opt
;
19613 mcpu_cpu_opt
= &arm_arch_any
;
19616 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19618 autoselect_thumb_from_cpu_variant ();
19620 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19622 #if defined OBJ_COFF || defined OBJ_ELF
19624 unsigned int flags
= 0;
19626 #if defined OBJ_ELF
19627 flags
= meabi_flags
;
19629 switch (meabi_flags
)
19631 case EF_ARM_EABI_UNKNOWN
:
19633 /* Set the flags in the private structure. */
19634 if (uses_apcs_26
) flags
|= F_APCS26
;
19635 if (support_interwork
) flags
|= F_INTERWORK
;
19636 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19637 if (pic_code
) flags
|= F_PIC
;
19638 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19639 flags
|= F_SOFT_FLOAT
;
19641 switch (mfloat_abi_opt
)
19643 case ARM_FLOAT_ABI_SOFT
:
19644 case ARM_FLOAT_ABI_SOFTFP
:
19645 flags
|= F_SOFT_FLOAT
;
19648 case ARM_FLOAT_ABI_HARD
:
19649 if (flags
& F_SOFT_FLOAT
)
19650 as_bad (_("hard-float conflicts with specified fpu"));
19654 /* Using pure-endian doubles (even if soft-float). */
19655 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19656 flags
|= F_VFP_FLOAT
;
19658 #if defined OBJ_ELF
19659 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19660 flags
|= EF_ARM_MAVERICK_FLOAT
;
19663 case EF_ARM_EABI_VER4
:
19664 case EF_ARM_EABI_VER5
:
19665 /* No additional flags to set. */
19672 bfd_set_private_flags (stdoutput
, flags
);
19674 /* We have run out flags in the COFF header to encode the
19675 status of ATPCS support, so instead we create a dummy,
19676 empty, debug section called .arm.atpcs. */
19681 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19685 bfd_set_section_flags
19686 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19687 bfd_set_section_size (stdoutput
, sec
, 0);
19688 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19694 /* Record the CPU type as well. */
19695 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19696 mach
= bfd_mach_arm_iWMMXt2
;
19697 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19698 mach
= bfd_mach_arm_iWMMXt
;
19699 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19700 mach
= bfd_mach_arm_XScale
;
19701 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19702 mach
= bfd_mach_arm_ep9312
;
19703 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19704 mach
= bfd_mach_arm_5TE
;
19705 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19707 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19708 mach
= bfd_mach_arm_5T
;
19710 mach
= bfd_mach_arm_5
;
19712 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19714 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19715 mach
= bfd_mach_arm_4T
;
19717 mach
= bfd_mach_arm_4
;
19719 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19720 mach
= bfd_mach_arm_3M
;
19721 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19722 mach
= bfd_mach_arm_3
;
19723 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19724 mach
= bfd_mach_arm_2a
;
19725 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19726 mach
= bfd_mach_arm_2
;
19728 mach
= bfd_mach_arm_unknown
;
19730 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19733 /* Command line processing. */
19736 Invocation line includes a switch not recognized by the base assembler.
19737 See if it's a processor-specific option.
19739 This routine is somewhat complicated by the need for backwards
19740 compatibility (since older releases of gcc can't be changed).
19741 The new options try to make the interface as compatible as
19744 New options (supported) are:
19746 -mcpu=<cpu name> Assemble for selected processor
19747 -march=<architecture name> Assemble for selected architecture
19748 -mfpu=<fpu architecture> Assemble for selected FPU.
19749 -EB/-mbig-endian Big-endian
19750 -EL/-mlittle-endian Little-endian
19751 -k Generate PIC code
19752 -mthumb Start in Thumb mode
19753 -mthumb-interwork Code supports ARM/Thumb interworking
19755 For now we will also provide support for:
19757 -mapcs-32 32-bit Program counter
19758 -mapcs-26 26-bit Program counter
19759 -macps-float Floats passed in FP registers
19760 -mapcs-reentrant Reentrant code
19762 (sometime these will probably be replaced with -mapcs=<list of options>
19763 and -matpcs=<list of options>)
19765 The remaining options are only supported for back-wards compatibility.
19766 Cpu variants, the arm part is optional:
19767 -m[arm]1 Currently not supported.
19768 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19769 -m[arm]3 Arm 3 processor
19770 -m[arm]6[xx], Arm 6 processors
19771 -m[arm]7[xx][t][[d]m] Arm 7 processors
19772 -m[arm]8[10] Arm 8 processors
19773 -m[arm]9[20][tdmi] Arm 9 processors
19774 -mstrongarm[110[0]] StrongARM processors
19775 -mxscale XScale processors
19776 -m[arm]v[2345[t[e]]] Arm architectures
19777 -mall All (except the ARM1)
19779 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19780 -mfpe-old (No float load/store multiples)
19781 -mvfpxd VFP Single precision
19783 -mno-fpu Disable all floating point instructions
19785 The following CPU names are recognized:
19786 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19787 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19788 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19789 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19790 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19791 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19792 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19796 const char * md_shortopts
= "m:k";
19798 #ifdef ARM_BI_ENDIAN
19799 #define OPTION_EB (OPTION_MD_BASE + 0)
19800 #define OPTION_EL (OPTION_MD_BASE + 1)
19802 #if TARGET_BYTES_BIG_ENDIAN
19803 #define OPTION_EB (OPTION_MD_BASE + 0)
19805 #define OPTION_EL (OPTION_MD_BASE + 1)
19809 struct option md_longopts
[] =
19812 {"EB", no_argument
, NULL
, OPTION_EB
},
19815 {"EL", no_argument
, NULL
, OPTION_EL
},
19817 {NULL
, no_argument
, NULL
, 0}
19820 size_t md_longopts_size
= sizeof (md_longopts
);
19822 struct arm_option_table
19824 char *option
; /* Option name to match. */
19825 char *help
; /* Help information. */
19826 int *var
; /* Variable to change. */
19827 int value
; /* What to change it to. */
19828 char *deprecated
; /* If non-null, print this message. */
19831 struct arm_option_table arm_opts
[] =
19833 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19834 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19835 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19836 &support_interwork
, 1, NULL
},
19837 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19838 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19839 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19841 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19842 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19843 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19844 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19847 /* These are recognized by the assembler, but have no affect on code. */
19848 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19849 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19850 {NULL
, NULL
, NULL
, 0, NULL
}
19853 struct arm_legacy_option_table
19855 char *option
; /* Option name to match. */
19856 const arm_feature_set
**var
; /* Variable to change. */
19857 const arm_feature_set value
; /* What to change it to. */
19858 char *deprecated
; /* If non-null, print this message. */
19861 const struct arm_legacy_option_table arm_legacy_opts
[] =
19863 /* DON'T add any new processors to this list -- we want the whole list
19864 to go away... Add them to the processors table instead. */
19865 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19866 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19867 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19868 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19869 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19870 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19871 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19872 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19873 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19874 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19875 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19876 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19877 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19878 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19879 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19880 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19881 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19882 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19883 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19884 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19885 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19886 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19887 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19888 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19889 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19890 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19891 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19892 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19893 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19894 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19895 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19896 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19897 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19898 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19899 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19900 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19901 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19902 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19903 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19904 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19905 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19906 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19907 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19908 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19909 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19910 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19911 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19912 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19913 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19914 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19915 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19916 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19917 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19918 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19919 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19920 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19921 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19922 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19923 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19924 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19925 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19926 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19927 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19928 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19929 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19930 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19931 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19932 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19933 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19934 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19935 N_("use -mcpu=strongarm110")},
19936 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19937 N_("use -mcpu=strongarm1100")},
19938 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19939 N_("use -mcpu=strongarm1110")},
19940 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19941 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19942 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19944 /* Architecture variants -- don't add any more to this list either. */
19945 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19946 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19947 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19948 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19949 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19950 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19951 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19952 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19953 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19954 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19955 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19956 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19957 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19958 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19959 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19960 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19961 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19962 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19964 /* Floating point variants -- don't add any more to this list either. */
19965 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19966 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19967 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19968 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19969 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19971 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19974 struct arm_cpu_option_table
19977 const arm_feature_set value
;
19978 /* For some CPUs we assume an FPU unless the user explicitly sets
19980 const arm_feature_set default_fpu
;
19981 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19983 const char *canonical_name
;
19986 /* This list should, at a minimum, contain all the cpu names
19987 recognized by GCC. */
19988 static const struct arm_cpu_option_table arm_cpus
[] =
19990 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19991 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19992 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19993 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19994 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19995 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19996 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19997 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19998 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19999 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20000 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20001 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20002 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20003 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20004 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20005 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20006 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20007 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20008 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20009 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20010 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20011 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20012 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20013 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20014 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20015 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20016 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20017 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20018 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20019 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20020 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20021 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20022 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20023 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20024 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20025 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20026 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20027 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20028 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20029 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20030 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20031 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20032 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20033 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20034 /* For V5 or later processors we default to using VFP; but the user
20035 should really set the FPU type explicitly. */
20036 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20037 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20038 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20039 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20040 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20041 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20042 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20043 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20044 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20045 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20046 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20047 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20048 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20049 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20050 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20051 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20052 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20053 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20054 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20055 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20056 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20057 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20058 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20059 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20060 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20061 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20062 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20063 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20064 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20065 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20066 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20067 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20068 | FPU_NEON_EXT_V1
),
20070 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20071 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20072 /* ??? XSCALE is really an architecture. */
20073 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20074 /* ??? iwmmxt is not a processor. */
20075 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20076 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20077 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20079 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20080 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20083 struct arm_arch_option_table
20086 const arm_feature_set value
;
20087 const arm_feature_set default_fpu
;
20090 /* This list should, at a minimum, contain all the architecture names
20091 recognized by GCC. */
20092 static const struct arm_arch_option_table arm_archs
[] =
20094 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20095 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20096 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20097 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20098 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20099 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20100 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20101 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20102 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20103 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20104 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20105 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20106 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20107 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20108 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20109 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20110 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20111 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20112 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20113 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20114 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20115 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20116 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20117 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20118 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20119 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20120 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20121 /* The official spelling of the ARMv7 profile variants is the dashed form.
20122 Accept the non-dashed form for compatibility with old toolchains. */
20123 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20124 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20125 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20126 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20127 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20128 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20129 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20130 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20131 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20132 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20135 /* ISA extensions in the co-processor space. */
20136 struct arm_option_cpu_value_table
20139 const arm_feature_set value
;
20142 static const struct arm_option_cpu_value_table arm_extensions
[] =
20144 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20145 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20146 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20147 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20148 {NULL
, ARM_ARCH_NONE
}
20151 /* This list should, at a minimum, contain all the fpu names
20152 recognized by GCC. */
20153 static const struct arm_option_cpu_value_table arm_fpus
[] =
20155 {"softfpa", FPU_NONE
},
20156 {"fpe", FPU_ARCH_FPE
},
20157 {"fpe2", FPU_ARCH_FPE
},
20158 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20159 {"fpa", FPU_ARCH_FPA
},
20160 {"fpa10", FPU_ARCH_FPA
},
20161 {"fpa11", FPU_ARCH_FPA
},
20162 {"arm7500fe", FPU_ARCH_FPA
},
20163 {"softvfp", FPU_ARCH_VFP
},
20164 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20165 {"vfp", FPU_ARCH_VFP_V2
},
20166 {"vfp9", FPU_ARCH_VFP_V2
},
20167 {"vfp3", FPU_ARCH_VFP_V3
},
20168 {"vfp10", FPU_ARCH_VFP_V2
},
20169 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20170 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20171 {"arm1020t", FPU_ARCH_VFP_V1
},
20172 {"arm1020e", FPU_ARCH_VFP_V2
},
20173 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20174 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20175 {"maverick", FPU_ARCH_MAVERICK
},
20176 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20177 {NULL
, ARM_ARCH_NONE
}
20180 struct arm_option_value_table
20186 static const struct arm_option_value_table arm_float_abis
[] =
20188 {"hard", ARM_FLOAT_ABI_HARD
},
20189 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20190 {"soft", ARM_FLOAT_ABI_SOFT
},
20195 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20196 static const struct arm_option_value_table arm_eabis
[] =
20198 {"gnu", EF_ARM_EABI_UNKNOWN
},
20199 {"4", EF_ARM_EABI_VER4
},
20200 {"5", EF_ARM_EABI_VER5
},
20205 struct arm_long_option_table
20207 char * option
; /* Substring to match. */
20208 char * help
; /* Help information. */
20209 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20210 char * deprecated
; /* If non-null, print this message. */
20214 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20216 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20218 /* Copy the feature set, so that we can modify it. */
20219 *ext_set
= **opt_p
;
20222 while (str
!= NULL
&& *str
!= 0)
20224 const struct arm_option_cpu_value_table
* opt
;
20230 as_bad (_("invalid architectural extension"));
20235 ext
= strchr (str
, '+');
20238 optlen
= ext
- str
;
20240 optlen
= strlen (str
);
20244 as_bad (_("missing architectural extension"));
20248 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20249 if (strncmp (opt
->name
, str
, optlen
) == 0)
20251 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20255 if (opt
->name
== NULL
)
20257 as_bad (_("unknown architectural extension `%s'"), str
);
20268 arm_parse_cpu (char * str
)
20270 const struct arm_cpu_option_table
* opt
;
20271 char * ext
= strchr (str
, '+');
20275 optlen
= ext
- str
;
20277 optlen
= strlen (str
);
20281 as_bad (_("missing cpu name `%s'"), str
);
20285 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20286 if (strncmp (opt
->name
, str
, optlen
) == 0)
20288 mcpu_cpu_opt
= &opt
->value
;
20289 mcpu_fpu_opt
= &opt
->default_fpu
;
20290 if (opt
->canonical_name
)
20291 strcpy (selected_cpu_name
, opt
->canonical_name
);
20295 for (i
= 0; i
< optlen
; i
++)
20296 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20297 selected_cpu_name
[i
] = 0;
20301 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20306 as_bad (_("unknown cpu `%s'"), str
);
20311 arm_parse_arch (char * str
)
20313 const struct arm_arch_option_table
*opt
;
20314 char *ext
= strchr (str
, '+');
20318 optlen
= ext
- str
;
20320 optlen
= strlen (str
);
20324 as_bad (_("missing architecture name `%s'"), str
);
20328 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20329 if (streq (opt
->name
, str
))
20331 march_cpu_opt
= &opt
->value
;
20332 march_fpu_opt
= &opt
->default_fpu
;
20333 strcpy (selected_cpu_name
, opt
->name
);
20336 return arm_parse_extension (ext
, &march_cpu_opt
);
20341 as_bad (_("unknown architecture `%s'\n"), str
);
20346 arm_parse_fpu (char * str
)
20348 const struct arm_option_cpu_value_table
* opt
;
20350 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20351 if (streq (opt
->name
, str
))
20353 mfpu_opt
= &opt
->value
;
20357 as_bad (_("unknown floating point format `%s'\n"), str
);
20362 arm_parse_float_abi (char * str
)
20364 const struct arm_option_value_table
* opt
;
20366 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20367 if (streq (opt
->name
, str
))
20369 mfloat_abi_opt
= opt
->value
;
20373 as_bad (_("unknown floating point abi `%s'\n"), str
);
20379 arm_parse_eabi (char * str
)
20381 const struct arm_option_value_table
*opt
;
20383 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20384 if (streq (opt
->name
, str
))
20386 meabi_flags
= opt
->value
;
20389 as_bad (_("unknown EABI `%s'\n"), str
);
20394 struct arm_long_option_table arm_long_opts
[] =
20396 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20397 arm_parse_cpu
, NULL
},
20398 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20399 arm_parse_arch
, NULL
},
20400 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20401 arm_parse_fpu
, NULL
},
20402 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20403 arm_parse_float_abi
, NULL
},
20405 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20406 arm_parse_eabi
, NULL
},
20408 {NULL
, NULL
, 0, NULL
}
20412 md_parse_option (int c
, char * arg
)
20414 struct arm_option_table
*opt
;
20415 const struct arm_legacy_option_table
*fopt
;
20416 struct arm_long_option_table
*lopt
;
20422 target_big_endian
= 1;
20428 target_big_endian
= 0;
20433 /* Listing option. Just ignore these, we don't support additional
20438 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20440 if (c
== opt
->option
[0]
20441 && ((arg
== NULL
&& opt
->option
[1] == 0)
20442 || streq (arg
, opt
->option
+ 1)))
20444 #if WARN_DEPRECATED
20445 /* If the option is deprecated, tell the user. */
20446 if (opt
->deprecated
!= NULL
)
20447 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20448 arg
? arg
: "", _(opt
->deprecated
));
20451 if (opt
->var
!= NULL
)
20452 *opt
->var
= opt
->value
;
20458 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20460 if (c
== fopt
->option
[0]
20461 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20462 || streq (arg
, fopt
->option
+ 1)))
20464 #if WARN_DEPRECATED
20465 /* If the option is deprecated, tell the user. */
20466 if (fopt
->deprecated
!= NULL
)
20467 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20468 arg
? arg
: "", _(fopt
->deprecated
));
20471 if (fopt
->var
!= NULL
)
20472 *fopt
->var
= &fopt
->value
;
20478 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20480 /* These options are expected to have an argument. */
20481 if (c
== lopt
->option
[0]
20483 && strncmp (arg
, lopt
->option
+ 1,
20484 strlen (lopt
->option
+ 1)) == 0)
20486 #if WARN_DEPRECATED
20487 /* If the option is deprecated, tell the user. */
20488 if (lopt
->deprecated
!= NULL
)
20489 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20490 _(lopt
->deprecated
));
20493 /* Call the sup-option parser. */
20494 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20505 md_show_usage (FILE * fp
)
20507 struct arm_option_table
*opt
;
20508 struct arm_long_option_table
*lopt
;
20510 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20512 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20513 if (opt
->help
!= NULL
)
20514 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20516 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20517 if (lopt
->help
!= NULL
)
20518 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20522 -EB assemble code for a big-endian cpu\n"));
20527 -EL assemble code for a little-endian cpu\n"));
20536 arm_feature_set flags
;
20537 } cpu_arch_ver_table
;
20539 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20540 least features first. */
20541 static const cpu_arch_ver_table cpu_arch_ver
[] =
20546 {4, ARM_ARCH_V5TE
},
20547 {5, ARM_ARCH_V5TEJ
},
20551 {9, ARM_ARCH_V6T2
},
20552 {10, ARM_ARCH_V7A
},
20553 {10, ARM_ARCH_V7R
},
20554 {10, ARM_ARCH_V7M
},
20558 /* Set the public EABI object attributes. */
20560 aeabi_set_public_attributes (void)
20563 arm_feature_set flags
;
20564 arm_feature_set tmp
;
20565 const cpu_arch_ver_table
*p
;
20567 /* Choose the architecture based on the capabilities of the requested cpu
20568 (if any) and/or the instructions actually used. */
20569 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20570 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20571 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20572 /*Allow the user to override the reported architecture. */
20575 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20576 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20581 for (p
= cpu_arch_ver
; p
->val
; p
++)
20583 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20586 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20590 /* Tag_CPU_name. */
20591 if (selected_cpu_name
[0])
20595 p
= selected_cpu_name
;
20596 if (strncmp (p
, "armv", 4) == 0)
20601 for (i
= 0; p
[i
]; i
++)
20602 p
[i
] = TOUPPER (p
[i
]);
20604 bfd_elf_add_proc_attr_string (stdoutput
, 5, p
);
20606 /* Tag_CPU_arch. */
20607 bfd_elf_add_proc_attr_int (stdoutput
, 6, arch
);
20608 /* Tag_CPU_arch_profile. */
20609 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20610 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'A');
20611 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20612 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'R');
20613 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20614 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'M');
20615 /* Tag_ARM_ISA_use. */
20616 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20617 bfd_elf_add_proc_attr_int (stdoutput
, 8, 1);
20618 /* Tag_THUMB_ISA_use. */
20619 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20620 bfd_elf_add_proc_attr_int (stdoutput
, 9,
20621 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20622 /* Tag_VFP_arch. */
20623 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20624 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20625 bfd_elf_add_proc_attr_int (stdoutput
, 10, 3);
20626 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20627 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20628 bfd_elf_add_proc_attr_int (stdoutput
, 10, 2);
20629 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20630 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20631 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20632 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20633 bfd_elf_add_proc_attr_int (stdoutput
, 10, 1);
20634 /* Tag_WMMX_arch. */
20635 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20636 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20637 bfd_elf_add_proc_attr_int (stdoutput
, 11, 1);
20638 /* Tag_NEON_arch. */
20639 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20640 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20641 bfd_elf_add_proc_attr_int (stdoutput
, 12, 1);
20644 /* Add the default contents for the .ARM.attributes section. */
20648 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20651 aeabi_set_public_attributes ();
20653 #endif /* OBJ_ELF */
20656 /* Parse a .cpu directive. */
20659 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20661 const struct arm_cpu_option_table
*opt
;
20665 name
= input_line_pointer
;
20666 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20667 input_line_pointer
++;
20668 saved_char
= *input_line_pointer
;
20669 *input_line_pointer
= 0;
20671 /* Skip the first "all" entry. */
20672 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20673 if (streq (opt
->name
, name
))
20675 mcpu_cpu_opt
= &opt
->value
;
20676 selected_cpu
= opt
->value
;
20677 if (opt
->canonical_name
)
20678 strcpy (selected_cpu_name
, opt
->canonical_name
);
20682 for (i
= 0; opt
->name
[i
]; i
++)
20683 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20684 selected_cpu_name
[i
] = 0;
20686 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20687 *input_line_pointer
= saved_char
;
20688 demand_empty_rest_of_line ();
20691 as_bad (_("unknown cpu `%s'"), name
);
20692 *input_line_pointer
= saved_char
;
20693 ignore_rest_of_line ();
20697 /* Parse a .arch directive. */
20700 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20702 const struct arm_arch_option_table
*opt
;
20706 name
= input_line_pointer
;
20707 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20708 input_line_pointer
++;
20709 saved_char
= *input_line_pointer
;
20710 *input_line_pointer
= 0;
20712 /* Skip the first "all" entry. */
20713 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20714 if (streq (opt
->name
, name
))
20716 mcpu_cpu_opt
= &opt
->value
;
20717 selected_cpu
= opt
->value
;
20718 strcpy (selected_cpu_name
, opt
->name
);
20719 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20720 *input_line_pointer
= saved_char
;
20721 demand_empty_rest_of_line ();
20725 as_bad (_("unknown architecture `%s'\n"), name
);
20726 *input_line_pointer
= saved_char
;
20727 ignore_rest_of_line ();
20731 /* Parse a .object_arch directive. */
20734 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
20736 const struct arm_arch_option_table
*opt
;
20740 name
= input_line_pointer
;
20741 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20742 input_line_pointer
++;
20743 saved_char
= *input_line_pointer
;
20744 *input_line_pointer
= 0;
20746 /* Skip the first "all" entry. */
20747 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20748 if (streq (opt
->name
, name
))
20750 object_arch
= &opt
->value
;
20751 *input_line_pointer
= saved_char
;
20752 demand_empty_rest_of_line ();
20756 as_bad (_("unknown architecture `%s'\n"), name
);
20757 *input_line_pointer
= saved_char
;
20758 ignore_rest_of_line ();
20762 /* Parse a .fpu directive. */
20765 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20767 const struct arm_option_cpu_value_table
*opt
;
20771 name
= input_line_pointer
;
20772 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20773 input_line_pointer
++;
20774 saved_char
= *input_line_pointer
;
20775 *input_line_pointer
= 0;
20777 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20778 if (streq (opt
->name
, name
))
20780 mfpu_opt
= &opt
->value
;
20781 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20782 *input_line_pointer
= saved_char
;
20783 demand_empty_rest_of_line ();
20787 as_bad (_("unknown floating point format `%s'\n"), name
);
20788 *input_line_pointer
= saved_char
;
20789 ignore_rest_of_line ();
20792 /* Copy symbol information. */
20794 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
20796 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);