1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
80 /* Bit N indicates that an R_ARM_NONE relocation has been output for
81 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
82 emitted only once per section, to save unnecessary bloat. */
83 static unsigned int marked_pr_dependency
= 0;
87 /* Results from operand parsing worker functions. */
91 PARSE_OPERAND_SUCCESS
,
93 PARSE_OPERAND_FAIL_NO_BACKTRACK
94 } parse_operand_result
;
103 /* Types of processor to assemble for. */
105 #if defined __XSCALE__
106 #define CPU_DEFAULT ARM_ARCH_XSCALE
108 #if defined __thumb__
109 #define CPU_DEFAULT ARM_ARCH_V5T
116 # define FPU_DEFAULT FPU_ARCH_FPA
117 # elif defined (TE_NetBSD)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
121 /* Legacy a.out format. */
122 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
124 # elif defined (TE_VXWORKS)
125 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
127 /* For backwards compatibility, default to FPA. */
128 # define FPU_DEFAULT FPU_ARCH_FPA
130 #endif /* ifndef FPU_DEFAULT */
132 #define streq(a, b) (strcmp (a, b) == 0)
134 static arm_feature_set cpu_variant
;
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
149 /* Variables that we set while parsing command-line options. Once all
150 options have been read we re-process these values to set the real
152 static const arm_feature_set
*legacy_cpu
= NULL
;
153 static const arm_feature_set
*legacy_fpu
= NULL
;
155 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
156 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
157 static const arm_feature_set
*march_cpu_opt
= NULL
;
158 static const arm_feature_set
*march_fpu_opt
= NULL
;
159 static const arm_feature_set
*mfpu_opt
= NULL
;
160 static const arm_feature_set
*object_arch
= NULL
;
162 /* Constants for known architecture features. */
163 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
164 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
165 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
166 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
167 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
168 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
169 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
170 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
171 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
174 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
177 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
179 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
180 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
181 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
182 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
183 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
184 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v4t_5
=
186 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
187 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
188 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
189 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
190 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
191 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
192 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
193 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
194 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
195 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
196 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
197 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
198 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
199 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
200 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
201 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
202 static const arm_feature_set arm_ext_m
=
203 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
205 static const arm_feature_set arm_arch_any
= ARM_ANY
;
206 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
208 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_cext_iwmmxt2
=
211 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
212 static const arm_feature_set arm_cext_iwmmxt
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
214 static const arm_feature_set arm_cext_xscale
=
215 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
216 static const arm_feature_set arm_cext_maverick
=
217 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
218 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
219 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v1xd
=
221 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
222 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
223 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
224 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
225 static const arm_feature_set fpu_vfp_ext_d32
=
226 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
227 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
228 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
229 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
230 static const arm_feature_set fpu_neon_fp16
= ARM_FEATURE (0, FPU_NEON_FP16
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
244 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
249 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
254 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
255 symbolS
* GOT_symbol
;
258 /* 0: assemble for ARM,
259 1: assemble for Thumb,
260 2: assemble for Thumb even though target CPU does not support thumb
262 static int thumb_mode
= 0;
264 /* If unified_syntax is true, we are processing the new unified
265 ARM/Thumb syntax. Important differences from the old ARM mode:
267 - Immediate operands do not require a # prefix.
268 - Conditional affixes always appear at the end of the
269 instruction. (For backward compatibility, those instructions
270 that formerly had them in the middle, continue to accept them
272 - The IT instruction may appear, and if it does is validated
273 against subsequent conditional affixes. It does not generate
276 Important differences from the old Thumb mode:
278 - Immediate operands do not require a # prefix.
279 - Most of the V6T2 instructions are only available in unified mode.
280 - The .N and .W suffixes are recognized and honored (it is an error
281 if they cannot be honored).
282 - All instructions set the flags if and only if they have an 's' affix.
283 - Conditional affixes may be used. They are validated against
284 preceding IT instructions. Unlike ARM mode, you cannot use a
285 conditional affix except in the scope of an IT instruction. */
287 static bfd_boolean unified_syntax
= FALSE
;
302 enum neon_el_type type
;
306 #define NEON_MAX_TYPE_ELS 4
310 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
317 unsigned long instruction
;
321 /* "uncond_value" is set to the value in place of the conditional field in
322 unconditional versions of the instruction, or -1 if nothing is
325 struct neon_type vectype
;
326 /* Set to the opcode if the instruction needs relaxation.
327 Zero if the instruction is not relaxed. */
331 bfd_reloc_code_real_type type
;
340 struct neon_type_el vectype
;
341 unsigned present
: 1; /* Operand present. */
342 unsigned isreg
: 1; /* Operand was a register. */
343 unsigned immisreg
: 1; /* .imm field is a second register. */
344 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
345 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
346 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
347 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
348 instructions. This allows us to disambiguate ARM <-> vector insns. */
349 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
350 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
351 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
352 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
353 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
354 unsigned writeback
: 1; /* Operand has trailing ! */
355 unsigned preind
: 1; /* Preindexed address. */
356 unsigned postind
: 1; /* Postindexed address. */
357 unsigned negative
: 1; /* Index register was negated. */
358 unsigned shifted
: 1; /* Shift applied to operation. */
359 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
363 static struct arm_it inst
;
365 #define NUM_FLOAT_VALS 8
367 const char * fp_const
[] =
369 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
372 /* Number of littlenums required to hold an extended precision number. */
373 #define MAX_LITTLENUMS 6
375 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
385 #define CP_T_X 0x00008000
386 #define CP_T_Y 0x00400000
388 #define CONDS_BIT 0x00100000
389 #define LOAD_BIT 0x00100000
391 #define DOUBLE_LOAD_FLAG 0x00000001
395 const char * template;
399 #define COND_ALWAYS 0xE
403 const char *template;
407 struct asm_barrier_opt
409 const char *template;
413 /* The bit that distinguishes CPSR and SPSR. */
414 #define SPSR_BIT (1 << 22)
416 /* The individual PSR flag bits. */
417 #define PSR_c (1 << 16)
418 #define PSR_x (1 << 17)
419 #define PSR_s (1 << 18)
420 #define PSR_f (1 << 19)
425 bfd_reloc_code_real_type reloc
;
430 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
431 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
436 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
439 /* Bits for DEFINED field in neon_typed_alias. */
440 #define NTA_HASTYPE 1
441 #define NTA_HASINDEX 2
443 struct neon_typed_alias
445 unsigned char defined
;
447 struct neon_type_el eltype
;
450 /* ARM register categories. This includes coprocessor numbers and various
451 architecture extensions' registers. */
477 /* Structure for a hash table entry for a register.
478 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
479 information which states whether a vector type or index is specified (for a
480 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
484 unsigned char number
;
486 unsigned char builtin
;
487 struct neon_typed_alias
*neon
;
490 /* Diagnostics used when we don't get a register of the expected type. */
491 const char *const reg_expected_msgs
[] =
493 N_("ARM register expected"),
494 N_("bad or missing co-processor number"),
495 N_("co-processor register expected"),
496 N_("FPA register expected"),
497 N_("VFP single precision register expected"),
498 N_("VFP/Neon double precision register expected"),
499 N_("Neon quad precision register expected"),
500 N_("VFP single or double precision register expected"),
501 N_("Neon double or quad precision register expected"),
502 N_("VFP single, double or Neon quad precision register expected"),
503 N_("VFP system register expected"),
504 N_("Maverick MVF register expected"),
505 N_("Maverick MVD register expected"),
506 N_("Maverick MVFX register expected"),
507 N_("Maverick MVDX register expected"),
508 N_("Maverick MVAX register expected"),
509 N_("Maverick DSPSC register expected"),
510 N_("iWMMXt data register expected"),
511 N_("iWMMXt control register expected"),
512 N_("iWMMXt scalar register expected"),
513 N_("XScale accumulator register expected"),
516 /* Some well known registers that we refer to directly elsewhere. */
521 /* ARM instructions take 4bytes in the object file, Thumb instructions
527 /* Basic string to match. */
528 const char *template;
530 /* Parameters to instruction. */
531 unsigned char operands
[8];
533 /* Conditional tag - see opcode_lookup. */
534 unsigned int tag
: 4;
536 /* Basic instruction code. */
537 unsigned int avalue
: 28;
539 /* Thumb-format instruction code. */
542 /* Which architecture variant provides this instruction. */
543 const arm_feature_set
*avariant
;
544 const arm_feature_set
*tvariant
;
546 /* Function to call to encode instruction in ARM format. */
547 void (* aencode
) (void);
549 /* Function to call to encode instruction in Thumb format. */
550 void (* tencode
) (void);
553 /* Defines for various bits that we will want to toggle. */
554 #define INST_IMMEDIATE 0x02000000
555 #define OFFSET_REG 0x02000000
556 #define HWOFFSET_IMM 0x00400000
557 #define SHIFT_BY_REG 0x00000010
558 #define PRE_INDEX 0x01000000
559 #define INDEX_UP 0x00800000
560 #define WRITE_BACK 0x00200000
561 #define LDM_TYPE_2_OR_3 0x00400000
562 #define CPSI_MMOD 0x00020000
564 #define LITERAL_MASK 0xf000f000
565 #define OPCODE_MASK 0xfe1fffff
566 #define V4_STR_BIT 0x00000020
568 #define T2_SUBS_PC_LR 0xf3de8f00
570 #define DATA_OP_SHIFT 21
572 #define T2_OPCODE_MASK 0xfe1fffff
573 #define T2_DATA_OP_SHIFT 21
575 /* Codes to distinguish the arithmetic instructions. */
586 #define OPCODE_CMP 10
587 #define OPCODE_CMN 11
588 #define OPCODE_ORR 12
589 #define OPCODE_MOV 13
590 #define OPCODE_BIC 14
591 #define OPCODE_MVN 15
593 #define T2_OPCODE_AND 0
594 #define T2_OPCODE_BIC 1
595 #define T2_OPCODE_ORR 2
596 #define T2_OPCODE_ORN 3
597 #define T2_OPCODE_EOR 4
598 #define T2_OPCODE_ADD 8
599 #define T2_OPCODE_ADC 10
600 #define T2_OPCODE_SBC 11
601 #define T2_OPCODE_SUB 13
602 #define T2_OPCODE_RSB 14
604 #define T_OPCODE_MUL 0x4340
605 #define T_OPCODE_TST 0x4200
606 #define T_OPCODE_CMN 0x42c0
607 #define T_OPCODE_NEG 0x4240
608 #define T_OPCODE_MVN 0x43c0
610 #define T_OPCODE_ADD_R3 0x1800
611 #define T_OPCODE_SUB_R3 0x1a00
612 #define T_OPCODE_ADD_HI 0x4400
613 #define T_OPCODE_ADD_ST 0xb000
614 #define T_OPCODE_SUB_ST 0xb080
615 #define T_OPCODE_ADD_SP 0xa800
616 #define T_OPCODE_ADD_PC 0xa000
617 #define T_OPCODE_ADD_I8 0x3000
618 #define T_OPCODE_SUB_I8 0x3800
619 #define T_OPCODE_ADD_I3 0x1c00
620 #define T_OPCODE_SUB_I3 0x1e00
622 #define T_OPCODE_ASR_R 0x4100
623 #define T_OPCODE_LSL_R 0x4080
624 #define T_OPCODE_LSR_R 0x40c0
625 #define T_OPCODE_ROR_R 0x41c0
626 #define T_OPCODE_ASR_I 0x1000
627 #define T_OPCODE_LSL_I 0x0000
628 #define T_OPCODE_LSR_I 0x0800
630 #define T_OPCODE_MOV_I8 0x2000
631 #define T_OPCODE_CMP_I8 0x2800
632 #define T_OPCODE_CMP_LR 0x4280
633 #define T_OPCODE_MOV_HR 0x4600
634 #define T_OPCODE_CMP_HR 0x4500
636 #define T_OPCODE_LDR_PC 0x4800
637 #define T_OPCODE_LDR_SP 0x9800
638 #define T_OPCODE_STR_SP 0x9000
639 #define T_OPCODE_LDR_IW 0x6800
640 #define T_OPCODE_STR_IW 0x6000
641 #define T_OPCODE_LDR_IH 0x8800
642 #define T_OPCODE_STR_IH 0x8000
643 #define T_OPCODE_LDR_IB 0x7800
644 #define T_OPCODE_STR_IB 0x7000
645 #define T_OPCODE_LDR_RW 0x5800
646 #define T_OPCODE_STR_RW 0x5000
647 #define T_OPCODE_LDR_RH 0x5a00
648 #define T_OPCODE_STR_RH 0x5200
649 #define T_OPCODE_LDR_RB 0x5c00
650 #define T_OPCODE_STR_RB 0x5400
652 #define T_OPCODE_PUSH 0xb400
653 #define T_OPCODE_POP 0xbc00
655 #define T_OPCODE_BRANCH 0xe000
657 #define THUMB_SIZE 2 /* Size of thumb instruction. */
658 #define THUMB_PP_PC_LR 0x0100
659 #define THUMB_LOAD_BIT 0x0800
660 #define THUMB2_LOAD_BIT 0x00100000
662 #define BAD_ARGS _("bad arguments to instruction")
663 #define BAD_PC _("r15 not allowed here")
664 #define BAD_COND _("instruction cannot be conditional")
665 #define BAD_OVERLAP _("registers may not be the same")
666 #define BAD_HIREG _("lo register required")
667 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
668 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
669 #define BAD_BRANCH _("branch must be last instruction in IT block")
670 #define BAD_NOT_IT _("instruction not allowed in IT block")
671 #define BAD_FPU _("selected FPU does not support instruction")
673 static struct hash_control
*arm_ops_hsh
;
674 static struct hash_control
*arm_cond_hsh
;
675 static struct hash_control
*arm_shift_hsh
;
676 static struct hash_control
*arm_psr_hsh
;
677 static struct hash_control
*arm_v7m_psr_hsh
;
678 static struct hash_control
*arm_reg_hsh
;
679 static struct hash_control
*arm_reloc_hsh
;
680 static struct hash_control
*arm_barrier_opt_hsh
;
682 /* Stuff needed to resolve the label ambiguity
691 symbolS
* last_label_seen
;
692 static int label_is_thumb_function_name
= FALSE
;
694 /* Literal pool structure. Held on a per-section
695 and per-sub-section basis. */
697 #define MAX_LITERAL_POOL_SIZE 1024
698 typedef struct literal_pool
700 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
701 unsigned int next_free_entry
;
706 struct literal_pool
* next
;
709 /* Pointer to a linked list of literal pools. */
710 literal_pool
* list_of_pools
= NULL
;
712 /* State variables for IT block handling. */
713 static bfd_boolean current_it_mask
= 0;
714 static int current_cc
;
718 /* This array holds the chars that always start a comment. If the
719 pre-processor is disabled, these aren't very useful. */
720 const char comment_chars
[] = "@";
722 /* This array holds the chars that only start a comment at the beginning of
723 a line. If the line seems to have the form '# 123 filename'
724 .line and .file directives will appear in the pre-processed output. */
725 /* Note that input_file.c hand checks for '#' at the beginning of the
726 first line of the input file. This is because the compiler outputs
727 #NO_APP at the beginning of its output. */
728 /* Also note that comments like this one will always work. */
729 const char line_comment_chars
[] = "#";
731 const char line_separator_chars
[] = ";";
733 /* Chars that can be used to separate mant
734 from exp in floating point numbers. */
735 const char EXP_CHARS
[] = "eE";
737 /* Chars that mean this number is a floating point constant. */
741 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
743 /* Prefix characters that indicate the start of an immediate
745 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
747 /* Separator character handling. */
749 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
752 skip_past_char (char ** str
, char c
)
762 #define skip_past_comma(str) skip_past_char (str, ',')
764 /* Arithmetic expressions (possibly involving symbols). */
766 /* Return TRUE if anything in the expression is a bignum. */
769 walk_no_bignums (symbolS
* sp
)
771 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
774 if (symbol_get_value_expression (sp
)->X_add_symbol
)
776 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
777 || (symbol_get_value_expression (sp
)->X_op_symbol
778 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
784 static int in_my_get_expression
= 0;
786 /* Third argument to my_get_expression. */
787 #define GE_NO_PREFIX 0
788 #define GE_IMM_PREFIX 1
789 #define GE_OPT_PREFIX 2
790 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
791 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
792 #define GE_OPT_PREFIX_BIG 3
795 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
800 /* In unified syntax, all prefixes are optional. */
802 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
807 case GE_NO_PREFIX
: break;
809 if (!is_immediate_prefix (**str
))
811 inst
.error
= _("immediate expression requires a # prefix");
817 case GE_OPT_PREFIX_BIG
:
818 if (is_immediate_prefix (**str
))
824 memset (ep
, 0, sizeof (expressionS
));
826 save_in
= input_line_pointer
;
827 input_line_pointer
= *str
;
828 in_my_get_expression
= 1;
829 seg
= expression (ep
);
830 in_my_get_expression
= 0;
832 if (ep
->X_op
== O_illegal
)
834 /* We found a bad expression in md_operand(). */
835 *str
= input_line_pointer
;
836 input_line_pointer
= save_in
;
837 if (inst
.error
== NULL
)
838 inst
.error
= _("bad expression");
843 if (seg
!= absolute_section
844 && seg
!= text_section
845 && seg
!= data_section
846 && seg
!= bss_section
847 && seg
!= undefined_section
)
849 inst
.error
= _("bad segment");
850 *str
= input_line_pointer
;
851 input_line_pointer
= save_in
;
856 /* Get rid of any bignums now, so that we don't generate an error for which
857 we can't establish a line number later on. Big numbers are never valid
858 in instructions, which is where this routine is always called. */
859 if (prefix_mode
!= GE_OPT_PREFIX_BIG
860 && (ep
->X_op
== O_big
862 && (walk_no_bignums (ep
->X_add_symbol
)
864 && walk_no_bignums (ep
->X_op_symbol
))))))
866 inst
.error
= _("invalid constant");
867 *str
= input_line_pointer
;
868 input_line_pointer
= save_in
;
872 *str
= input_line_pointer
;
873 input_line_pointer
= save_in
;
877 /* Turn a string in input_line_pointer into a floating point constant
878 of type TYPE, and store the appropriate bytes in *LITP. The number
879 of LITTLENUMS emitted is stored in *SIZEP. An error message is
880 returned, or NULL on OK.
882 Note that fp constants aren't represent in the normal way on the ARM.
883 In big endian mode, things are as expected. However, in little endian
884 mode fp constants are big-endian word-wise, and little-endian byte-wise
885 within the words. For example, (double) 1.1 in big endian mode is
886 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
887 the byte sequence 99 99 f1 3f 9a 99 99 99.
889 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
892 md_atof (int type
, char * litP
, int * sizeP
)
895 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
927 return _("Unrecognized or unsupported floating point constant");
930 t
= atof_ieee (input_line_pointer
, type
, words
);
932 input_line_pointer
= t
;
933 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
935 if (target_big_endian
)
937 for (i
= 0; i
< prec
; i
++)
939 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
940 litP
+= sizeof (LITTLENUM_TYPE
);
945 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
946 for (i
= prec
- 1; i
>= 0; i
--)
948 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
949 litP
+= sizeof (LITTLENUM_TYPE
);
952 /* For a 4 byte float the order of elements in `words' is 1 0.
953 For an 8 byte float the order is 1 0 3 2. */
954 for (i
= 0; i
< prec
; i
+= 2)
956 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
957 sizeof (LITTLENUM_TYPE
));
958 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
959 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
960 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
967 /* We handle all bad expressions here, so that we can report the faulty
968 instruction in the error message. */
970 md_operand (expressionS
* expr
)
972 if (in_my_get_expression
)
973 expr
->X_op
= O_illegal
;
976 /* Immediate values. */
978 /* Generic immediate-value read function for use in directives.
979 Accepts anything that 'expression' can fold to a constant.
980 *val receives the number. */
983 immediate_for_directive (int *val
)
986 exp
.X_op
= O_illegal
;
988 if (is_immediate_prefix (*input_line_pointer
))
990 input_line_pointer
++;
994 if (exp
.X_op
!= O_constant
)
996 as_bad (_("expected #constant"));
997 ignore_rest_of_line ();
1000 *val
= exp
.X_add_number
;
1005 /* Register parsing. */
1007 /* Generic register parser. CCP points to what should be the
1008 beginning of a register name. If it is indeed a valid register
1009 name, advance CCP over it and return the reg_entry structure;
1010 otherwise return NULL. Does not issue diagnostics. */
1012 static struct reg_entry
*
1013 arm_reg_parse_multi (char **ccp
)
1017 struct reg_entry
*reg
;
1019 #ifdef REGISTER_PREFIX
1020 if (*start
!= REGISTER_PREFIX
)
1024 #ifdef OPTIONAL_REGISTER_PREFIX
1025 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1030 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1035 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1037 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1047 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1048 enum arm_reg_type type
)
1050 /* Alternative syntaxes are accepted for a few register classes. */
1057 /* Generic coprocessor register names are allowed for these. */
1058 if (reg
&& reg
->type
== REG_TYPE_CN
)
1063 /* For backward compatibility, a bare number is valid here. */
1065 unsigned long processor
= strtoul (start
, ccp
, 10);
1066 if (*ccp
!= start
&& processor
<= 15)
1070 case REG_TYPE_MMXWC
:
1071 /* WC includes WCG. ??? I'm not sure this is true for all
1072 instructions that take WC registers. */
1073 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1084 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1085 return value is the register number or FAIL. */
1088 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1091 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1094 /* Do not allow a scalar (reg+index) to parse as a register. */
1095 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1098 if (reg
&& reg
->type
== type
)
1101 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1108 /* Parse a Neon type specifier. *STR should point at the leading '.'
1109 character. Does no verification at this stage that the type fits the opcode
1116 Can all be legally parsed by this function.
1118 Fills in neon_type struct pointer with parsed information, and updates STR
1119 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1120 type, FAIL if not. */
1123 parse_neon_type (struct neon_type
*type
, char **str
)
1130 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1132 enum neon_el_type thistype
= NT_untyped
;
1133 unsigned thissize
= -1u;
1140 /* Just a size without an explicit type. */
1144 switch (TOLOWER (*ptr
))
1146 case 'i': thistype
= NT_integer
; break;
1147 case 'f': thistype
= NT_float
; break;
1148 case 'p': thistype
= NT_poly
; break;
1149 case 's': thistype
= NT_signed
; break;
1150 case 'u': thistype
= NT_unsigned
; break;
1152 thistype
= NT_float
;
1157 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1163 /* .f is an abbreviation for .f32. */
1164 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1169 thissize
= strtoul (ptr
, &ptr
, 10);
1171 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1174 as_bad (_("bad size %d in type specifier"), thissize
);
1182 type
->el
[type
->elems
].type
= thistype
;
1183 type
->el
[type
->elems
].size
= thissize
;
1188 /* Empty/missing type is not a successful parse. */
1189 if (type
->elems
== 0)
1197 /* Errors may be set multiple times during parsing or bit encoding
1198 (particularly in the Neon bits), but usually the earliest error which is set
1199 will be the most meaningful. Avoid overwriting it with later (cascading)
1200 errors by calling this function. */
1203 first_error (const char *err
)
1209 /* Parse a single type, e.g. ".s32", leading period included. */
1211 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1214 struct neon_type optype
;
1218 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1220 if (optype
.elems
== 1)
1221 *vectype
= optype
.el
[0];
1224 first_error (_("only one type should be specified for operand"));
1230 first_error (_("vector type expected"));
1242 /* Special meanings for indices (which have a range of 0-7), which will fit into
1245 #define NEON_ALL_LANES 15
1246 #define NEON_INTERLEAVE_LANES 14
1248 /* Parse either a register or a scalar, with an optional type. Return the
1249 register number, and optionally fill in the actual type of the register
1250 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1251 type/index information in *TYPEINFO. */
1254 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1255 enum arm_reg_type
*rtype
,
1256 struct neon_typed_alias
*typeinfo
)
1259 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1260 struct neon_typed_alias atype
;
1261 struct neon_type_el parsetype
;
1265 atype
.eltype
.type
= NT_invtype
;
1266 atype
.eltype
.size
= -1;
1268 /* Try alternate syntax for some types of register. Note these are mutually
1269 exclusive with the Neon syntax extensions. */
1272 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1280 /* Undo polymorphism when a set of register types may be accepted. */
1281 if ((type
== REG_TYPE_NDQ
1282 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1283 || (type
== REG_TYPE_VFSD
1284 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1285 || (type
== REG_TYPE_NSDQ
1286 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1287 || reg
->type
== REG_TYPE_NQ
))
1288 || (type
== REG_TYPE_MMXWC
1289 && (reg
->type
== REG_TYPE_MMXWCG
)))
1292 if (type
!= reg
->type
)
1298 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1300 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1302 first_error (_("can't redefine type for operand"));
1305 atype
.defined
|= NTA_HASTYPE
;
1306 atype
.eltype
= parsetype
;
1309 if (skip_past_char (&str
, '[') == SUCCESS
)
1311 if (type
!= REG_TYPE_VFD
)
1313 first_error (_("only D registers may be indexed"));
1317 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1319 first_error (_("can't change index for operand"));
1323 atype
.defined
|= NTA_HASINDEX
;
1325 if (skip_past_char (&str
, ']') == SUCCESS
)
1326 atype
.index
= NEON_ALL_LANES
;
1331 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1333 if (exp
.X_op
!= O_constant
)
1335 first_error (_("constant expression required"));
1339 if (skip_past_char (&str
, ']') == FAIL
)
1342 atype
.index
= exp
.X_add_number
;
1357 /* Like arm_reg_parse, but allow allow the following extra features:
1358 - If RTYPE is non-zero, return the (possibly restricted) type of the
1359 register (e.g. Neon double or quad reg when either has been requested).
1360 - If this is a Neon vector type with additional type information, fill
1361 in the struct pointed to by VECTYPE (if non-NULL).
1362 This function will fault on encountering a scalar. */
1365 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1366 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1368 struct neon_typed_alias atype
;
1370 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1375 /* Do not allow a scalar (reg+index) to parse as a register. */
1376 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1378 first_error (_("register operand expected, but got scalar"));
1383 *vectype
= atype
.eltype
;
1390 #define NEON_SCALAR_REG(X) ((X) >> 4)
1391 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1393 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1394 have enough information to be able to do a good job bounds-checking. So, we
1395 just do easy checks here, and do further checks later. */
1398 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1402 struct neon_typed_alias atype
;
1404 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1406 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1409 if (atype
.index
== NEON_ALL_LANES
)
1411 first_error (_("scalar must have an index"));
1414 else if (atype
.index
>= 64 / elsize
)
1416 first_error (_("scalar index out of range"));
1421 *type
= atype
.eltype
;
1425 return reg
* 16 + atype
.index
;
1428 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1430 parse_reg_list (char ** strp
)
1432 char * str
= * strp
;
1436 /* We come back here if we get ranges concatenated by '+' or '|'. */
1451 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1453 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1463 first_error (_("bad range in register list"));
1467 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1469 if (range
& (1 << i
))
1471 (_("Warning: duplicated register (r%d) in register list"),
1479 if (range
& (1 << reg
))
1480 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1482 else if (reg
<= cur_reg
)
1483 as_tsktsk (_("Warning: register range not in ascending order"));
1488 while (skip_past_comma (&str
) != FAIL
1489 || (in_range
= 1, *str
++ == '-'));
1494 first_error (_("missing `}'"));
1502 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1505 if (expr
.X_op
== O_constant
)
1507 if (expr
.X_add_number
1508 != (expr
.X_add_number
& 0x0000ffff))
1510 inst
.error
= _("invalid register mask");
1514 if ((range
& expr
.X_add_number
) != 0)
1516 int regno
= range
& expr
.X_add_number
;
1519 regno
= (1 << regno
) - 1;
1521 (_("Warning: duplicated register (r%d) in register list"),
1525 range
|= expr
.X_add_number
;
1529 if (inst
.reloc
.type
!= 0)
1531 inst
.error
= _("expression too complex");
1535 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1536 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1537 inst
.reloc
.pc_rel
= 0;
1541 if (*str
== '|' || *str
== '+')
1547 while (another_range
);
1553 /* Types of registers in a list. */
1562 /* Parse a VFP register list. If the string is invalid return FAIL.
1563 Otherwise return the number of registers, and set PBASE to the first
1564 register. Parses registers of type ETYPE.
1565 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1566 - Q registers can be used to specify pairs of D registers
1567 - { } can be omitted from around a singleton register list
1568 FIXME: This is not implemented, as it would require backtracking in
1571 This could be done (the meaning isn't really ambiguous), but doesn't
1572 fit in well with the current parsing framework.
1573 - 32 D registers may be used (also true for VFPv3).
1574 FIXME: Types are ignored in these register lists, which is probably a
1578 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1583 enum arm_reg_type regtype
= 0;
1587 unsigned long mask
= 0;
1592 inst
.error
= _("expecting {");
1601 regtype
= REG_TYPE_VFS
;
1606 regtype
= REG_TYPE_VFD
;
1609 case REGLIST_NEON_D
:
1610 regtype
= REG_TYPE_NDQ
;
1614 if (etype
!= REGLIST_VFP_S
)
1616 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1617 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1621 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1624 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1631 base_reg
= max_regs
;
1635 int setmask
= 1, addregs
= 1;
1637 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1639 if (new_base
== FAIL
)
1641 first_error (_(reg_expected_msgs
[regtype
]));
1645 if (new_base
>= max_regs
)
1647 first_error (_("register out of range in list"));
1651 /* Note: a value of 2 * n is returned for the register Q<n>. */
1652 if (regtype
== REG_TYPE_NQ
)
1658 if (new_base
< base_reg
)
1659 base_reg
= new_base
;
1661 if (mask
& (setmask
<< new_base
))
1663 first_error (_("invalid register list"));
1667 if ((mask
>> new_base
) != 0 && ! warned
)
1669 as_tsktsk (_("register list not in ascending order"));
1673 mask
|= setmask
<< new_base
;
1676 if (*str
== '-') /* We have the start of a range expression */
1682 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1685 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1689 if (high_range
>= max_regs
)
1691 first_error (_("register out of range in list"));
1695 if (regtype
== REG_TYPE_NQ
)
1696 high_range
= high_range
+ 1;
1698 if (high_range
<= new_base
)
1700 inst
.error
= _("register range not in ascending order");
1704 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1706 if (mask
& (setmask
<< new_base
))
1708 inst
.error
= _("invalid register list");
1712 mask
|= setmask
<< new_base
;
1717 while (skip_past_comma (&str
) != FAIL
);
1721 /* Sanity check -- should have raised a parse error above. */
1722 if (count
== 0 || count
> max_regs
)
1727 /* Final test -- the registers must be consecutive. */
1729 for (i
= 0; i
< count
; i
++)
1731 if ((mask
& (1u << i
)) == 0)
1733 inst
.error
= _("non-contiguous register range");
1743 /* True if two alias types are the same. */
1746 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1754 if (a
->defined
!= b
->defined
)
1757 if ((a
->defined
& NTA_HASTYPE
) != 0
1758 && (a
->eltype
.type
!= b
->eltype
.type
1759 || a
->eltype
.size
!= b
->eltype
.size
))
1762 if ((a
->defined
& NTA_HASINDEX
) != 0
1763 && (a
->index
!= b
->index
))
1769 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1770 The base register is put in *PBASE.
1771 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1773 The register stride (minus one) is put in bit 4 of the return value.
1774 Bits [6:5] encode the list length (minus one).
1775 The type of the list elements is put in *ELTYPE, if non-NULL. */
1777 #define NEON_LANE(X) ((X) & 0xf)
1778 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1779 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1782 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1783 struct neon_type_el
*eltype
)
1790 int leading_brace
= 0;
1791 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1793 const char *const incr_error
= "register stride must be 1 or 2";
1794 const char *const type_error
= "mismatched element/structure types in list";
1795 struct neon_typed_alias firsttype
;
1797 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1802 struct neon_typed_alias atype
;
1803 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1807 first_error (_(reg_expected_msgs
[rtype
]));
1814 if (rtype
== REG_TYPE_NQ
)
1821 else if (reg_incr
== -1)
1823 reg_incr
= getreg
- base_reg
;
1824 if (reg_incr
< 1 || reg_incr
> 2)
1826 first_error (_(incr_error
));
1830 else if (getreg
!= base_reg
+ reg_incr
* count
)
1832 first_error (_(incr_error
));
1836 if (!neon_alias_types_same (&atype
, &firsttype
))
1838 first_error (_(type_error
));
1842 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1846 struct neon_typed_alias htype
;
1847 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1849 lane
= NEON_INTERLEAVE_LANES
;
1850 else if (lane
!= NEON_INTERLEAVE_LANES
)
1852 first_error (_(type_error
));
1857 else if (reg_incr
!= 1)
1859 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1863 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1866 first_error (_(reg_expected_msgs
[rtype
]));
1869 if (!neon_alias_types_same (&htype
, &firsttype
))
1871 first_error (_(type_error
));
1874 count
+= hireg
+ dregs
- getreg
;
1878 /* If we're using Q registers, we can't use [] or [n] syntax. */
1879 if (rtype
== REG_TYPE_NQ
)
1885 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1889 else if (lane
!= atype
.index
)
1891 first_error (_(type_error
));
1895 else if (lane
== -1)
1896 lane
= NEON_INTERLEAVE_LANES
;
1897 else if (lane
!= NEON_INTERLEAVE_LANES
)
1899 first_error (_(type_error
));
1904 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1906 /* No lane set by [x]. We must be interleaving structures. */
1908 lane
= NEON_INTERLEAVE_LANES
;
1911 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1912 || (count
> 1 && reg_incr
== -1))
1914 first_error (_("error parsing element/structure list"));
1918 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1920 first_error (_("expected }"));
1928 *eltype
= firsttype
.eltype
;
1933 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1936 /* Parse an explicit relocation suffix on an expression. This is
1937 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1938 arm_reloc_hsh contains no entries, so this function can only
1939 succeed if there is no () after the word. Returns -1 on error,
1940 BFD_RELOC_UNUSED if there wasn't any suffix. */
1942 parse_reloc (char **str
)
1944 struct reloc_entry
*r
;
1948 return BFD_RELOC_UNUSED
;
1953 while (*q
&& *q
!= ')' && *q
!= ',')
1958 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1965 /* Directives: register aliases. */
1967 static struct reg_entry
*
1968 insert_reg_alias (char *str
, int number
, int type
)
1970 struct reg_entry
*new;
1973 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1976 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1978 /* Only warn about a redefinition if it's not defined as the
1980 else if (new->number
!= number
|| new->type
!= type
)
1981 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1986 name
= xstrdup (str
);
1987 new = xmalloc (sizeof (struct reg_entry
));
1990 new->number
= number
;
1992 new->builtin
= FALSE
;
1995 if (hash_insert (arm_reg_hsh
, name
, (void *) new))
2002 insert_neon_reg_alias (char *str
, int number
, int type
,
2003 struct neon_typed_alias
*atype
)
2005 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2009 first_error (_("attempt to redefine typed alias"));
2015 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2016 *reg
->neon
= *atype
;
2020 /* Look for the .req directive. This is of the form:
2022 new_register_name .req existing_register_name
2024 If we find one, or if it looks sufficiently like one that we want to
2025 handle any error here, return TRUE. Otherwise return FALSE. */
2028 create_register_alias (char * newname
, char *p
)
2030 struct reg_entry
*old
;
2031 char *oldname
, *nbuf
;
2034 /* The input scrubber ensures that whitespace after the mnemonic is
2035 collapsed to single spaces. */
2037 if (strncmp (oldname
, " .req ", 6) != 0)
2041 if (*oldname
== '\0')
2044 old
= hash_find (arm_reg_hsh
, oldname
);
2047 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2051 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2052 the desired alias name, and p points to its end. If not, then
2053 the desired alias name is in the global original_case_string. */
2054 #ifdef TC_CASE_SENSITIVE
2057 newname
= original_case_string
;
2058 nlen
= strlen (newname
);
2061 nbuf
= alloca (nlen
+ 1);
2062 memcpy (nbuf
, newname
, nlen
);
2065 /* Create aliases under the new name as stated; an all-lowercase
2066 version of the new name; and an all-uppercase version of the new
2068 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2070 for (p
= nbuf
; *p
; p
++)
2073 if (strncmp (nbuf
, newname
, nlen
))
2075 /* If this attempt to create an additional alias fails, do not bother
2076 trying to create the all-lower case alias. We will fail and issue
2077 a second, duplicate error message. This situation arises when the
2078 programmer does something like:
2081 The second .req creates the "Foo" alias but then fails to create
2082 the artificial FOO alias because it has already been created by the
2084 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2088 for (p
= nbuf
; *p
; p
++)
2091 if (strncmp (nbuf
, newname
, nlen
))
2092 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2098 /* Create a Neon typed/indexed register alias using directives, e.g.:
2103 These typed registers can be used instead of the types specified after the
2104 Neon mnemonic, so long as all operands given have types. Types can also be
2105 specified directly, e.g.:
2106 vadd d0.s32, d1.s32, d2.s32 */
2109 create_neon_reg_alias (char *newname
, char *p
)
2111 enum arm_reg_type basetype
;
2112 struct reg_entry
*basereg
;
2113 struct reg_entry mybasereg
;
2114 struct neon_type ntype
;
2115 struct neon_typed_alias typeinfo
;
2116 char *namebuf
, *nameend
;
2119 typeinfo
.defined
= 0;
2120 typeinfo
.eltype
.type
= NT_invtype
;
2121 typeinfo
.eltype
.size
= -1;
2122 typeinfo
.index
= -1;
2126 if (strncmp (p
, " .dn ", 5) == 0)
2127 basetype
= REG_TYPE_VFD
;
2128 else if (strncmp (p
, " .qn ", 5) == 0)
2129 basetype
= REG_TYPE_NQ
;
2138 basereg
= arm_reg_parse_multi (&p
);
2140 if (basereg
&& basereg
->type
!= basetype
)
2142 as_bad (_("bad type for register"));
2146 if (basereg
== NULL
)
2149 /* Try parsing as an integer. */
2150 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2151 if (exp
.X_op
!= O_constant
)
2153 as_bad (_("expression must be constant"));
2156 basereg
= &mybasereg
;
2157 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2163 typeinfo
= *basereg
->neon
;
2165 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2167 /* We got a type. */
2168 if (typeinfo
.defined
& NTA_HASTYPE
)
2170 as_bad (_("can't redefine the type of a register alias"));
2174 typeinfo
.defined
|= NTA_HASTYPE
;
2175 if (ntype
.elems
!= 1)
2177 as_bad (_("you must specify a single type only"));
2180 typeinfo
.eltype
= ntype
.el
[0];
2183 if (skip_past_char (&p
, '[') == SUCCESS
)
2186 /* We got a scalar index. */
2188 if (typeinfo
.defined
& NTA_HASINDEX
)
2190 as_bad (_("can't redefine the index of a scalar alias"));
2194 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2196 if (exp
.X_op
!= O_constant
)
2198 as_bad (_("scalar index must be constant"));
2202 typeinfo
.defined
|= NTA_HASINDEX
;
2203 typeinfo
.index
= exp
.X_add_number
;
2205 if (skip_past_char (&p
, ']') == FAIL
)
2207 as_bad (_("expecting ]"));
2212 namelen
= nameend
- newname
;
2213 namebuf
= alloca (namelen
+ 1);
2214 strncpy (namebuf
, newname
, namelen
);
2215 namebuf
[namelen
] = '\0';
2217 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2218 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2220 /* Insert name in all uppercase. */
2221 for (p
= namebuf
; *p
; p
++)
2224 if (strncmp (namebuf
, newname
, namelen
))
2225 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2226 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2228 /* Insert name in all lowercase. */
2229 for (p
= namebuf
; *p
; p
++)
2232 if (strncmp (namebuf
, newname
, namelen
))
2233 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2234 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2239 /* Should never be called, as .req goes between the alias and the
2240 register name, not at the beginning of the line. */
2242 s_req (int a ATTRIBUTE_UNUSED
)
2244 as_bad (_("invalid syntax for .req directive"));
2248 s_dn (int a ATTRIBUTE_UNUSED
)
2250 as_bad (_("invalid syntax for .dn directive"));
2254 s_qn (int a ATTRIBUTE_UNUSED
)
2256 as_bad (_("invalid syntax for .qn directive"));
2259 /* The .unreq directive deletes an alias which was previously defined
2260 by .req. For example:
2266 s_unreq (int a ATTRIBUTE_UNUSED
)
2271 name
= input_line_pointer
;
2273 while (*input_line_pointer
!= 0
2274 && *input_line_pointer
!= ' '
2275 && *input_line_pointer
!= '\n')
2276 ++input_line_pointer
;
2278 saved_char
= *input_line_pointer
;
2279 *input_line_pointer
= 0;
2282 as_bad (_("invalid syntax for .unreq directive"));
2285 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2288 as_bad (_("unknown register alias '%s'"), name
);
2289 else if (reg
->builtin
)
2290 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2297 hash_delete (arm_reg_hsh
, name
, FALSE
);
2298 free ((char *) reg
->name
);
2303 /* Also locate the all upper case and all lower case versions.
2304 Do not complain if we cannot find one or the other as it
2305 was probably deleted above. */
2307 nbuf
= strdup (name
);
2308 for (p
= nbuf
; *p
; p
++)
2310 reg
= hash_find (arm_reg_hsh
, nbuf
);
2313 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2314 free ((char *) reg
->name
);
2320 for (p
= nbuf
; *p
; p
++)
2322 reg
= hash_find (arm_reg_hsh
, nbuf
);
2325 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2326 free ((char *) reg
->name
);
2336 *input_line_pointer
= saved_char
;
2337 demand_empty_rest_of_line ();
2340 /* Directives: Instruction set selection. */
2343 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2344 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2345 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2346 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2348 static enum mstate mapstate
= MAP_UNDEFINED
;
2351 mapping_state (enum mstate state
)
2354 const char * symname
;
2357 if (mapstate
== state
)
2358 /* The mapping symbol has already been emitted.
2359 There is nothing else to do. */
2368 type
= BSF_NO_FLAGS
;
2372 type
= BSF_NO_FLAGS
;
2376 type
= BSF_NO_FLAGS
;
2384 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2386 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2387 symbol_table_insert (symbolP
);
2388 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2393 THUMB_SET_FUNC (symbolP
, 0);
2394 ARM_SET_THUMB (symbolP
, 0);
2395 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2399 THUMB_SET_FUNC (symbolP
, 1);
2400 ARM_SET_THUMB (symbolP
, 1);
2401 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2410 #define mapping_state(x) /* nothing */
2413 /* Find the real, Thumb encoded start of a Thumb function. */
2416 find_real_start (symbolS
* symbolP
)
2419 const char * name
= S_GET_NAME (symbolP
);
2420 symbolS
* new_target
;
2422 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2423 #define STUB_NAME ".real_start_of"
2428 /* The compiler may generate BL instructions to local labels because
2429 it needs to perform a branch to a far away location. These labels
2430 do not have a corresponding ".real_start_of" label. We check
2431 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2432 the ".real_start_of" convention for nonlocal branches. */
2433 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2436 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2437 new_target
= symbol_find (real_start
);
2439 if (new_target
== NULL
)
2441 as_warn (_("Failed to find real start of function: %s\n"), name
);
2442 new_target
= symbolP
;
2449 opcode_select (int width
)
2456 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2457 as_bad (_("selected processor does not support THUMB opcodes"));
2460 /* No need to force the alignment, since we will have been
2461 coming from ARM mode, which is word-aligned. */
2462 record_alignment (now_seg
, 1);
2464 mapping_state (MAP_THUMB
);
2470 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2471 as_bad (_("selected processor does not support ARM opcodes"));
2476 frag_align (2, 0, 0);
2478 record_alignment (now_seg
, 1);
2480 mapping_state (MAP_ARM
);
2484 as_bad (_("invalid instruction size selected (%d)"), width
);
2489 s_arm (int ignore ATTRIBUTE_UNUSED
)
2492 demand_empty_rest_of_line ();
2496 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2499 demand_empty_rest_of_line ();
2503 s_code (int unused ATTRIBUTE_UNUSED
)
2507 temp
= get_absolute_expression ();
2512 opcode_select (temp
);
2516 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2521 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2523 /* If we are not already in thumb mode go into it, EVEN if
2524 the target processor does not support thumb instructions.
2525 This is used by gcc/config/arm/lib1funcs.asm for example
2526 to compile interworking support functions even if the
2527 target processor should not support interworking. */
2531 record_alignment (now_seg
, 1);
2534 demand_empty_rest_of_line ();
2538 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2542 /* The following label is the name/address of the start of a Thumb function.
2543 We need to know this for the interworking support. */
2544 label_is_thumb_function_name
= TRUE
;
2547 /* Perform a .set directive, but also mark the alias as
2548 being a thumb function. */
2551 s_thumb_set (int equiv
)
2553 /* XXX the following is a duplicate of the code for s_set() in read.c
2554 We cannot just call that code as we need to get at the symbol that
2561 /* Especial apologies for the random logic:
2562 This just grew, and could be parsed much more simply!
2564 name
= input_line_pointer
;
2565 delim
= get_symbol_end ();
2566 end_name
= input_line_pointer
;
2569 if (*input_line_pointer
!= ',')
2572 as_bad (_("expected comma after name \"%s\""), name
);
2574 ignore_rest_of_line ();
2578 input_line_pointer
++;
2581 if (name
[0] == '.' && name
[1] == '\0')
2583 /* XXX - this should not happen to .thumb_set. */
2587 if ((symbolP
= symbol_find (name
)) == NULL
2588 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2591 /* When doing symbol listings, play games with dummy fragments living
2592 outside the normal fragment chain to record the file and line info
2594 if (listing
& LISTING_SYMBOLS
)
2596 extern struct list_info_struct
* listing_tail
;
2597 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2599 memset (dummy_frag
, 0, sizeof (fragS
));
2600 dummy_frag
->fr_type
= rs_fill
;
2601 dummy_frag
->line
= listing_tail
;
2602 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2603 dummy_frag
->fr_symbol
= symbolP
;
2607 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2610 /* "set" symbols are local unless otherwise specified. */
2611 SF_SET_LOCAL (symbolP
);
2612 #endif /* OBJ_COFF */
2613 } /* Make a new symbol. */
2615 symbol_table_insert (symbolP
);
2620 && S_IS_DEFINED (symbolP
)
2621 && S_GET_SEGMENT (symbolP
) != reg_section
)
2622 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2624 pseudo_set (symbolP
);
2626 demand_empty_rest_of_line ();
2628 /* XXX Now we come to the Thumb specific bit of code. */
2630 THUMB_SET_FUNC (symbolP
, 1);
2631 ARM_SET_THUMB (symbolP
, 1);
2632 #if defined OBJ_ELF || defined OBJ_COFF
2633 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2637 /* Directives: Mode selection. */
2639 /* .syntax [unified|divided] - choose the new unified syntax
2640 (same for Arm and Thumb encoding, modulo slight differences in what
2641 can be represented) or the old divergent syntax for each mode. */
2643 s_syntax (int unused ATTRIBUTE_UNUSED
)
2647 name
= input_line_pointer
;
2648 delim
= get_symbol_end ();
2650 if (!strcasecmp (name
, "unified"))
2651 unified_syntax
= TRUE
;
2652 else if (!strcasecmp (name
, "divided"))
2653 unified_syntax
= FALSE
;
2656 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2659 *input_line_pointer
= delim
;
2660 demand_empty_rest_of_line ();
2663 /* Directives: sectioning and alignment. */
2665 /* Same as s_align_ptwo but align 0 => align 2. */
2668 s_align (int unused ATTRIBUTE_UNUSED
)
2673 long max_alignment
= 15;
2675 temp
= get_absolute_expression ();
2676 if (temp
> max_alignment
)
2677 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2680 as_bad (_("alignment negative. 0 assumed."));
2684 if (*input_line_pointer
== ',')
2686 input_line_pointer
++;
2687 temp_fill
= get_absolute_expression ();
2699 /* Only make a frag if we HAVE to. */
2700 if (temp
&& !need_pass_2
)
2702 if (!fill_p
&& subseg_text_p (now_seg
))
2703 frag_align_code (temp
, 0);
2705 frag_align (temp
, (int) temp_fill
, 0);
2707 demand_empty_rest_of_line ();
2709 record_alignment (now_seg
, temp
);
2713 s_bss (int ignore ATTRIBUTE_UNUSED
)
2715 /* We don't support putting frags in the BSS segment, we fake it by
2716 marking in_bss, then looking at s_skip for clues. */
2717 subseg_set (bss_section
, 0);
2718 demand_empty_rest_of_line ();
2719 mapping_state (MAP_DATA
);
2723 s_even (int ignore ATTRIBUTE_UNUSED
)
2725 /* Never make frag if expect extra pass. */
2727 frag_align (1, 0, 0);
2729 record_alignment (now_seg
, 1);
2731 demand_empty_rest_of_line ();
2734 /* Directives: Literal pools. */
2736 static literal_pool
*
2737 find_literal_pool (void)
2739 literal_pool
* pool
;
2741 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2743 if (pool
->section
== now_seg
2744 && pool
->sub_section
== now_subseg
)
2751 static literal_pool
*
2752 find_or_make_literal_pool (void)
2754 /* Next literal pool ID number. */
2755 static unsigned int latest_pool_num
= 1;
2756 literal_pool
* pool
;
2758 pool
= find_literal_pool ();
2762 /* Create a new pool. */
2763 pool
= xmalloc (sizeof (* pool
));
2767 pool
->next_free_entry
= 0;
2768 pool
->section
= now_seg
;
2769 pool
->sub_section
= now_subseg
;
2770 pool
->next
= list_of_pools
;
2771 pool
->symbol
= NULL
;
2773 /* Add it to the list. */
2774 list_of_pools
= pool
;
2777 /* New pools, and emptied pools, will have a NULL symbol. */
2778 if (pool
->symbol
== NULL
)
2780 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2781 (valueT
) 0, &zero_address_frag
);
2782 pool
->id
= latest_pool_num
++;
2789 /* Add the literal in the global 'inst'
2790 structure to the relevant literal pool. */
2793 add_to_lit_pool (void)
2795 literal_pool
* pool
;
2798 pool
= find_or_make_literal_pool ();
2800 /* Check if this literal value is already in the pool. */
2801 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2803 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2804 && (inst
.reloc
.exp
.X_op
== O_constant
)
2805 && (pool
->literals
[entry
].X_add_number
2806 == inst
.reloc
.exp
.X_add_number
)
2807 && (pool
->literals
[entry
].X_unsigned
2808 == inst
.reloc
.exp
.X_unsigned
))
2811 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2812 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2813 && (pool
->literals
[entry
].X_add_number
2814 == inst
.reloc
.exp
.X_add_number
)
2815 && (pool
->literals
[entry
].X_add_symbol
2816 == inst
.reloc
.exp
.X_add_symbol
)
2817 && (pool
->literals
[entry
].X_op_symbol
2818 == inst
.reloc
.exp
.X_op_symbol
))
2822 /* Do we need to create a new entry? */
2823 if (entry
== pool
->next_free_entry
)
2825 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2827 inst
.error
= _("literal pool overflow");
2831 pool
->literals
[entry
] = inst
.reloc
.exp
;
2832 pool
->next_free_entry
+= 1;
2835 inst
.reloc
.exp
.X_op
= O_symbol
;
2836 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2837 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2842 /* Can't use symbol_new here, so have to create a symbol and then at
2843 a later date assign it a value. Thats what these functions do. */
2846 symbol_locate (symbolS
* symbolP
,
2847 const char * name
, /* It is copied, the caller can modify. */
2848 segT segment
, /* Segment identifier (SEG_<something>). */
2849 valueT valu
, /* Symbol value. */
2850 fragS
* frag
) /* Associated fragment. */
2852 unsigned int name_length
;
2853 char * preserved_copy_of_name
;
2855 name_length
= strlen (name
) + 1; /* +1 for \0. */
2856 obstack_grow (¬es
, name
, name_length
);
2857 preserved_copy_of_name
= obstack_finish (¬es
);
2859 #ifdef tc_canonicalize_symbol_name
2860 preserved_copy_of_name
=
2861 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2864 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2866 S_SET_SEGMENT (symbolP
, segment
);
2867 S_SET_VALUE (symbolP
, valu
);
2868 symbol_clear_list_pointers (symbolP
);
2870 symbol_set_frag (symbolP
, frag
);
2872 /* Link to end of symbol chain. */
2874 extern int symbol_table_frozen
;
2876 if (symbol_table_frozen
)
2880 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2882 obj_symbol_new_hook (symbolP
);
2884 #ifdef tc_symbol_new_hook
2885 tc_symbol_new_hook (symbolP
);
2889 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2890 #endif /* DEBUG_SYMS */
2895 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2898 literal_pool
* pool
;
2901 pool
= find_literal_pool ();
2903 || pool
->symbol
== NULL
2904 || pool
->next_free_entry
== 0)
2907 mapping_state (MAP_DATA
);
2909 /* Align pool as you have word accesses.
2910 Only make a frag if we have to. */
2912 frag_align (2, 0, 0);
2914 record_alignment (now_seg
, 2);
2916 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2918 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2919 (valueT
) frag_now_fix (), frag_now
);
2920 symbol_table_insert (pool
->symbol
);
2922 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2924 #if defined OBJ_COFF || defined OBJ_ELF
2925 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2928 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2929 /* First output the expression in the instruction to the pool. */
2930 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2932 /* Mark the pool as empty. */
2933 pool
->next_free_entry
= 0;
2934 pool
->symbol
= NULL
;
2938 /* Forward declarations for functions below, in the MD interface
2940 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2941 static valueT
create_unwind_entry (int);
2942 static void start_unwind_section (const segT
, int);
2943 static void add_unwind_opcode (valueT
, int);
2944 static void flush_pending_unwind (void);
2946 /* Directives: Data. */
2949 s_arm_elf_cons (int nbytes
)
2953 #ifdef md_flush_pending_output
2954 md_flush_pending_output ();
2957 if (is_it_end_of_statement ())
2959 demand_empty_rest_of_line ();
2963 #ifdef md_cons_align
2964 md_cons_align (nbytes
);
2967 mapping_state (MAP_DATA
);
2971 char *base
= input_line_pointer
;
2975 if (exp
.X_op
!= O_symbol
)
2976 emit_expr (&exp
, (unsigned int) nbytes
);
2979 char *before_reloc
= input_line_pointer
;
2980 reloc
= parse_reloc (&input_line_pointer
);
2983 as_bad (_("unrecognized relocation suffix"));
2984 ignore_rest_of_line ();
2987 else if (reloc
== BFD_RELOC_UNUSED
)
2988 emit_expr (&exp
, (unsigned int) nbytes
);
2991 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2992 int size
= bfd_get_reloc_size (howto
);
2994 if (reloc
== BFD_RELOC_ARM_PLT32
)
2996 as_bad (_("(plt) is only valid on branch targets"));
2997 reloc
= BFD_RELOC_UNUSED
;
3002 as_bad (_("%s relocations do not fit in %d bytes"),
3003 howto
->name
, nbytes
);
3006 /* We've parsed an expression stopping at O_symbol.
3007 But there may be more expression left now that we
3008 have parsed the relocation marker. Parse it again.
3009 XXX Surely there is a cleaner way to do this. */
3010 char *p
= input_line_pointer
;
3012 char *save_buf
= alloca (input_line_pointer
- base
);
3013 memcpy (save_buf
, base
, input_line_pointer
- base
);
3014 memmove (base
+ (input_line_pointer
- before_reloc
),
3015 base
, before_reloc
- base
);
3017 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3019 memcpy (base
, save_buf
, p
- base
);
3021 offset
= nbytes
- size
;
3022 p
= frag_more ((int) nbytes
);
3023 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3024 size
, &exp
, 0, reloc
);
3029 while (*input_line_pointer
++ == ',');
3031 /* Put terminator back into stream. */
3032 input_line_pointer
--;
3033 demand_empty_rest_of_line ();
3037 /* Parse a .rel31 directive. */
3040 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3047 if (*input_line_pointer
== '1')
3048 highbit
= 0x80000000;
3049 else if (*input_line_pointer
!= '0')
3050 as_bad (_("expected 0 or 1"));
3052 input_line_pointer
++;
3053 if (*input_line_pointer
!= ',')
3054 as_bad (_("missing comma"));
3055 input_line_pointer
++;
3057 #ifdef md_flush_pending_output
3058 md_flush_pending_output ();
3061 #ifdef md_cons_align
3065 mapping_state (MAP_DATA
);
3070 md_number_to_chars (p
, highbit
, 4);
3071 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3072 BFD_RELOC_ARM_PREL31
);
3074 demand_empty_rest_of_line ();
3077 /* Directives: AEABI stack-unwind tables. */
3079 /* Parse an unwind_fnstart directive. Simply records the current location. */
3082 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3084 demand_empty_rest_of_line ();
3085 /* Mark the start of the function. */
3086 unwind
.proc_start
= expr_build_dot ();
3088 /* Reset the rest of the unwind info. */
3089 unwind
.opcode_count
= 0;
3090 unwind
.table_entry
= NULL
;
3091 unwind
.personality_routine
= NULL
;
3092 unwind
.personality_index
= -1;
3093 unwind
.frame_size
= 0;
3094 unwind
.fp_offset
= 0;
3097 unwind
.sp_restored
= 0;
3101 /* Parse a handlerdata directive. Creates the exception handling table entry
3102 for the function. */
3105 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3107 demand_empty_rest_of_line ();
3108 if (unwind
.table_entry
)
3109 as_bad (_("duplicate .handlerdata directive"));
3111 create_unwind_entry (1);
3114 /* Parse an unwind_fnend directive. Generates the index table entry. */
3117 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3123 demand_empty_rest_of_line ();
3125 /* Add eh table entry. */
3126 if (unwind
.table_entry
== NULL
)
3127 val
= create_unwind_entry (0);
3131 /* Add index table entry. This is two words. */
3132 start_unwind_section (unwind
.saved_seg
, 1);
3133 frag_align (2, 0, 0);
3134 record_alignment (now_seg
, 2);
3136 ptr
= frag_more (8);
3137 where
= frag_now_fix () - 8;
3139 /* Self relative offset of the function start. */
3140 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3141 BFD_RELOC_ARM_PREL31
);
3143 /* Indicate dependency on EHABI-defined personality routines to the
3144 linker, if it hasn't been done already. */
3145 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3146 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3148 static const char *const name
[] =
3150 "__aeabi_unwind_cpp_pr0",
3151 "__aeabi_unwind_cpp_pr1",
3152 "__aeabi_unwind_cpp_pr2"
3154 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3155 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3156 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3157 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3158 = marked_pr_dependency
;
3162 /* Inline exception table entry. */
3163 md_number_to_chars (ptr
+ 4, val
, 4);
3165 /* Self relative offset of the table entry. */
3166 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3167 BFD_RELOC_ARM_PREL31
);
3169 /* Restore the original section. */
3170 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3174 /* Parse an unwind_cantunwind directive. */
3177 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3179 demand_empty_rest_of_line ();
3180 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3181 as_bad (_("personality routine specified for cantunwind frame"));
3183 unwind
.personality_index
= -2;
3187 /* Parse a personalityindex directive. */
3190 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3194 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3195 as_bad (_("duplicate .personalityindex directive"));
3199 if (exp
.X_op
!= O_constant
3200 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3202 as_bad (_("bad personality routine number"));
3203 ignore_rest_of_line ();
3207 unwind
.personality_index
= exp
.X_add_number
;
3209 demand_empty_rest_of_line ();
3213 /* Parse a personality directive. */
3216 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3220 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3221 as_bad (_("duplicate .personality directive"));
3223 name
= input_line_pointer
;
3224 c
= get_symbol_end ();
3225 p
= input_line_pointer
;
3226 unwind
.personality_routine
= symbol_find_or_make (name
);
3228 demand_empty_rest_of_line ();
3232 /* Parse a directive saving core registers. */
3235 s_arm_unwind_save_core (void)
3241 range
= parse_reg_list (&input_line_pointer
);
3244 as_bad (_("expected register list"));
3245 ignore_rest_of_line ();
3249 demand_empty_rest_of_line ();
3251 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3252 into .unwind_save {..., sp...}. We aren't bothered about the value of
3253 ip because it is clobbered by calls. */
3254 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3255 && (range
& 0x3000) == 0x1000)
3257 unwind
.opcode_count
--;
3258 unwind
.sp_restored
= 0;
3259 range
= (range
| 0x2000) & ~0x1000;
3260 unwind
.pending_offset
= 0;
3266 /* See if we can use the short opcodes. These pop a block of up to 8
3267 registers starting with r4, plus maybe r14. */
3268 for (n
= 0; n
< 8; n
++)
3270 /* Break at the first non-saved register. */
3271 if ((range
& (1 << (n
+ 4))) == 0)
3274 /* See if there are any other bits set. */
3275 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3277 /* Use the long form. */
3278 op
= 0x8000 | ((range
>> 4) & 0xfff);
3279 add_unwind_opcode (op
, 2);
3283 /* Use the short form. */
3285 op
= 0xa8; /* Pop r14. */
3287 op
= 0xa0; /* Do not pop r14. */
3289 add_unwind_opcode (op
, 1);
3296 op
= 0xb100 | (range
& 0xf);
3297 add_unwind_opcode (op
, 2);
3300 /* Record the number of bytes pushed. */
3301 for (n
= 0; n
< 16; n
++)
3303 if (range
& (1 << n
))
3304 unwind
.frame_size
+= 4;
3309 /* Parse a directive saving FPA registers. */
3312 s_arm_unwind_save_fpa (int reg
)
3318 /* Get Number of registers to transfer. */
3319 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3322 exp
.X_op
= O_illegal
;
3324 if (exp
.X_op
!= O_constant
)
3326 as_bad (_("expected , <constant>"));
3327 ignore_rest_of_line ();
3331 num_regs
= exp
.X_add_number
;
3333 if (num_regs
< 1 || num_regs
> 4)
3335 as_bad (_("number of registers must be in the range [1:4]"));
3336 ignore_rest_of_line ();
3340 demand_empty_rest_of_line ();
3345 op
= 0xb4 | (num_regs
- 1);
3346 add_unwind_opcode (op
, 1);
3351 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3352 add_unwind_opcode (op
, 2);
3354 unwind
.frame_size
+= num_regs
* 12;
3358 /* Parse a directive saving VFP registers for ARMv6 and above. */
3361 s_arm_unwind_save_vfp_armv6 (void)
3366 int num_vfpv3_regs
= 0;
3367 int num_regs_below_16
;
3369 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3372 as_bad (_("expected register list"));
3373 ignore_rest_of_line ();
3377 demand_empty_rest_of_line ();
3379 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3380 than FSTMX/FLDMX-style ones). */
3382 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3384 num_vfpv3_regs
= count
;
3385 else if (start
+ count
> 16)
3386 num_vfpv3_regs
= start
+ count
- 16;
3388 if (num_vfpv3_regs
> 0)
3390 int start_offset
= start
> 16 ? start
- 16 : 0;
3391 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3392 add_unwind_opcode (op
, 2);
3395 /* Generate opcode for registers numbered in the range 0 .. 15. */
3396 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3397 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3398 if (num_regs_below_16
> 0)
3400 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3401 add_unwind_opcode (op
, 2);
3404 unwind
.frame_size
+= count
* 8;
3408 /* Parse a directive saving VFP registers for pre-ARMv6. */
3411 s_arm_unwind_save_vfp (void)
3417 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3420 as_bad (_("expected register list"));
3421 ignore_rest_of_line ();
3425 demand_empty_rest_of_line ();
3430 op
= 0xb8 | (count
- 1);
3431 add_unwind_opcode (op
, 1);
3436 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3437 add_unwind_opcode (op
, 2);
3439 unwind
.frame_size
+= count
* 8 + 4;
3443 /* Parse a directive saving iWMMXt data registers. */
3446 s_arm_unwind_save_mmxwr (void)
3454 if (*input_line_pointer
== '{')
3455 input_line_pointer
++;
3459 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3463 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3468 as_tsktsk (_("register list not in ascending order"));
3471 if (*input_line_pointer
== '-')
3473 input_line_pointer
++;
3474 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3477 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3480 else if (reg
>= hi_reg
)
3482 as_bad (_("bad register range"));
3485 for (; reg
< hi_reg
; reg
++)
3489 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3491 if (*input_line_pointer
== '}')
3492 input_line_pointer
++;
3494 demand_empty_rest_of_line ();
3496 /* Generate any deferred opcodes because we're going to be looking at
3498 flush_pending_unwind ();
3500 for (i
= 0; i
< 16; i
++)
3502 if (mask
& (1 << i
))
3503 unwind
.frame_size
+= 8;
3506 /* Attempt to combine with a previous opcode. We do this because gcc
3507 likes to output separate unwind directives for a single block of
3509 if (unwind
.opcode_count
> 0)
3511 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3512 if ((i
& 0xf8) == 0xc0)
3515 /* Only merge if the blocks are contiguous. */
3518 if ((mask
& 0xfe00) == (1 << 9))
3520 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3521 unwind
.opcode_count
--;
3524 else if (i
== 6 && unwind
.opcode_count
>= 2)
3526 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3530 op
= 0xffff << (reg
- 1);
3532 && ((mask
& op
) == (1u << (reg
- 1))))
3534 op
= (1 << (reg
+ i
+ 1)) - 1;
3535 op
&= ~((1 << reg
) - 1);
3537 unwind
.opcode_count
-= 2;
3544 /* We want to generate opcodes in the order the registers have been
3545 saved, ie. descending order. */
3546 for (reg
= 15; reg
>= -1; reg
--)
3548 /* Save registers in blocks. */
3550 || !(mask
& (1 << reg
)))
3552 /* We found an unsaved reg. Generate opcodes to save the
3559 op
= 0xc0 | (hi_reg
- 10);
3560 add_unwind_opcode (op
, 1);
3565 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3566 add_unwind_opcode (op
, 2);
3575 ignore_rest_of_line ();
3579 s_arm_unwind_save_mmxwcg (void)
3586 if (*input_line_pointer
== '{')
3587 input_line_pointer
++;
3591 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3595 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3601 as_tsktsk (_("register list not in ascending order"));
3604 if (*input_line_pointer
== '-')
3606 input_line_pointer
++;
3607 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3610 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3613 else if (reg
>= hi_reg
)
3615 as_bad (_("bad register range"));
3618 for (; reg
< hi_reg
; reg
++)
3622 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3624 if (*input_line_pointer
== '}')
3625 input_line_pointer
++;
3627 demand_empty_rest_of_line ();
3629 /* Generate any deferred opcodes because we're going to be looking at
3631 flush_pending_unwind ();
3633 for (reg
= 0; reg
< 16; reg
++)
3635 if (mask
& (1 << reg
))
3636 unwind
.frame_size
+= 4;
3639 add_unwind_opcode (op
, 2);
3642 ignore_rest_of_line ();
3646 /* Parse an unwind_save directive.
3647 If the argument is non-zero, this is a .vsave directive. */
3650 s_arm_unwind_save (int arch_v6
)
3653 struct reg_entry
*reg
;
3654 bfd_boolean had_brace
= FALSE
;
3656 /* Figure out what sort of save we have. */
3657 peek
= input_line_pointer
;
3665 reg
= arm_reg_parse_multi (&peek
);
3669 as_bad (_("register expected"));
3670 ignore_rest_of_line ();
3679 as_bad (_("FPA .unwind_save does not take a register list"));
3680 ignore_rest_of_line ();
3683 input_line_pointer
= peek
;
3684 s_arm_unwind_save_fpa (reg
->number
);
3687 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3690 s_arm_unwind_save_vfp_armv6 ();
3692 s_arm_unwind_save_vfp ();
3694 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3695 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3698 as_bad (_(".unwind_save does not support this kind of register"));
3699 ignore_rest_of_line ();
3704 /* Parse an unwind_movsp directive. */
3707 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3713 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3716 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
3717 ignore_rest_of_line ();
3721 /* Optional constant. */
3722 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3724 if (immediate_for_directive (&offset
) == FAIL
)
3730 demand_empty_rest_of_line ();
3732 if (reg
== REG_SP
|| reg
== REG_PC
)
3734 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3738 if (unwind
.fp_reg
!= REG_SP
)
3739 as_bad (_("unexpected .unwind_movsp directive"));
3741 /* Generate opcode to restore the value. */
3743 add_unwind_opcode (op
, 1);
3745 /* Record the information for later. */
3746 unwind
.fp_reg
= reg
;
3747 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3748 unwind
.sp_restored
= 1;
3751 /* Parse an unwind_pad directive. */
3754 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3758 if (immediate_for_directive (&offset
) == FAIL
)
3763 as_bad (_("stack increment must be multiple of 4"));
3764 ignore_rest_of_line ();
3768 /* Don't generate any opcodes, just record the details for later. */
3769 unwind
.frame_size
+= offset
;
3770 unwind
.pending_offset
+= offset
;
3772 demand_empty_rest_of_line ();
3775 /* Parse an unwind_setfp directive. */
3778 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3784 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3785 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3788 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3790 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3792 as_bad (_("expected <reg>, <reg>"));
3793 ignore_rest_of_line ();
3797 /* Optional constant. */
3798 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3800 if (immediate_for_directive (&offset
) == FAIL
)
3806 demand_empty_rest_of_line ();
3808 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3810 as_bad (_("register must be either sp or set by a previous"
3811 "unwind_movsp directive"));
3815 /* Don't generate any opcodes, just record the information for later. */
3816 unwind
.fp_reg
= fp_reg
;
3819 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3821 unwind
.fp_offset
-= offset
;
3824 /* Parse an unwind_raw directive. */
3827 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3830 /* This is an arbitrary limit. */
3831 unsigned char op
[16];
3835 if (exp
.X_op
== O_constant
3836 && skip_past_comma (&input_line_pointer
) != FAIL
)
3838 unwind
.frame_size
+= exp
.X_add_number
;
3842 exp
.X_op
= O_illegal
;
3844 if (exp
.X_op
!= O_constant
)
3846 as_bad (_("expected <offset>, <opcode>"));
3847 ignore_rest_of_line ();
3853 /* Parse the opcode. */
3858 as_bad (_("unwind opcode too long"));
3859 ignore_rest_of_line ();
3861 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3863 as_bad (_("invalid unwind opcode"));
3864 ignore_rest_of_line ();
3867 op
[count
++] = exp
.X_add_number
;
3869 /* Parse the next byte. */
3870 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3876 /* Add the opcode bytes in reverse order. */
3878 add_unwind_opcode (op
[count
], 1);
3880 demand_empty_rest_of_line ();
3884 /* Parse a .eabi_attribute directive. */
3887 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3889 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
3891 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
3892 attributes_set_explicitly
[tag
] = 1;
3894 #endif /* OBJ_ELF */
3896 static void s_arm_arch (int);
3897 static void s_arm_object_arch (int);
3898 static void s_arm_cpu (int);
3899 static void s_arm_fpu (int);
3904 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3911 if (exp
.X_op
== O_symbol
)
3912 exp
.X_op
= O_secrel
;
3914 emit_expr (&exp
, 4);
3916 while (*input_line_pointer
++ == ',');
3918 input_line_pointer
--;
3919 demand_empty_rest_of_line ();
3923 /* This table describes all the machine specific pseudo-ops the assembler
3924 has to support. The fields are:
3925 pseudo-op name without dot
3926 function to call to execute this pseudo-op
3927 Integer arg to pass to the function. */
3929 const pseudo_typeS md_pseudo_table
[] =
3931 /* Never called because '.req' does not start a line. */
3932 { "req", s_req
, 0 },
3933 /* Following two are likewise never called. */
3936 { "unreq", s_unreq
, 0 },
3937 { "bss", s_bss
, 0 },
3938 { "align", s_align
, 0 },
3939 { "arm", s_arm
, 0 },
3940 { "thumb", s_thumb
, 0 },
3941 { "code", s_code
, 0 },
3942 { "force_thumb", s_force_thumb
, 0 },
3943 { "thumb_func", s_thumb_func
, 0 },
3944 { "thumb_set", s_thumb_set
, 0 },
3945 { "even", s_even
, 0 },
3946 { "ltorg", s_ltorg
, 0 },
3947 { "pool", s_ltorg
, 0 },
3948 { "syntax", s_syntax
, 0 },
3949 { "cpu", s_arm_cpu
, 0 },
3950 { "arch", s_arm_arch
, 0 },
3951 { "object_arch", s_arm_object_arch
, 0 },
3952 { "fpu", s_arm_fpu
, 0 },
3954 { "word", s_arm_elf_cons
, 4 },
3955 { "long", s_arm_elf_cons
, 4 },
3956 { "rel31", s_arm_rel31
, 0 },
3957 { "fnstart", s_arm_unwind_fnstart
, 0 },
3958 { "fnend", s_arm_unwind_fnend
, 0 },
3959 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3960 { "personality", s_arm_unwind_personality
, 0 },
3961 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3962 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3963 { "save", s_arm_unwind_save
, 0 },
3964 { "vsave", s_arm_unwind_save
, 1 },
3965 { "movsp", s_arm_unwind_movsp
, 0 },
3966 { "pad", s_arm_unwind_pad
, 0 },
3967 { "setfp", s_arm_unwind_setfp
, 0 },
3968 { "unwind_raw", s_arm_unwind_raw
, 0 },
3969 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3973 /* These are used for dwarf. */
3977 /* These are used for dwarf2. */
3978 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3979 { "loc", dwarf2_directive_loc
, 0 },
3980 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3982 { "extend", float_cons
, 'x' },
3983 { "ldouble", float_cons
, 'x' },
3984 { "packed", float_cons
, 'p' },
3986 {"secrel32", pe_directive_secrel
, 0},
3991 /* Parser functions used exclusively in instruction operands. */
3993 /* Generic immediate-value read function for use in insn parsing.
3994 STR points to the beginning of the immediate (the leading #);
3995 VAL receives the value; if the value is outside [MIN, MAX]
3996 issue an error. PREFIX_OPT is true if the immediate prefix is
4000 parse_immediate (char **str
, int *val
, int min
, int max
,
4001 bfd_boolean prefix_opt
)
4004 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4005 if (exp
.X_op
!= O_constant
)
4007 inst
.error
= _("constant expression required");
4011 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4013 inst
.error
= _("immediate value out of range");
4017 *val
= exp
.X_add_number
;
4021 /* Less-generic immediate-value read function with the possibility of loading a
4022 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4023 instructions. Puts the result directly in inst.operands[i]. */
4026 parse_big_immediate (char **str
, int i
)
4031 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4033 if (exp
.X_op
== O_constant
)
4035 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4036 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4037 O_constant. We have to be careful not to break compilation for
4038 32-bit X_add_number, though. */
4039 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4041 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4042 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4043 inst
.operands
[i
].regisimm
= 1;
4046 else if (exp
.X_op
== O_big
4047 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4048 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4050 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4051 /* Bignums have their least significant bits in
4052 generic_bignum[0]. Make sure we put 32 bits in imm and
4053 32 bits in reg, in a (hopefully) portable way. */
4054 assert (parts
!= 0);
4055 inst
.operands
[i
].imm
= 0;
4056 for (j
= 0; j
< parts
; j
++, idx
++)
4057 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4058 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4059 inst
.operands
[i
].reg
= 0;
4060 for (j
= 0; j
< parts
; j
++, idx
++)
4061 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4062 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4063 inst
.operands
[i
].regisimm
= 1;
4073 /* Returns the pseudo-register number of an FPA immediate constant,
4074 or FAIL if there isn't a valid constant here. */
4077 parse_fpa_immediate (char ** str
)
4079 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4085 /* First try and match exact strings, this is to guarantee
4086 that some formats will work even for cross assembly. */
4088 for (i
= 0; fp_const
[i
]; i
++)
4090 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4094 *str
+= strlen (fp_const
[i
]);
4095 if (is_end_of_line
[(unsigned char) **str
])
4101 /* Just because we didn't get a match doesn't mean that the constant
4102 isn't valid, just that it is in a format that we don't
4103 automatically recognize. Try parsing it with the standard
4104 expression routines. */
4106 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4108 /* Look for a raw floating point number. */
4109 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4110 && is_end_of_line
[(unsigned char) *save_in
])
4112 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4114 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4116 if (words
[j
] != fp_values
[i
][j
])
4120 if (j
== MAX_LITTLENUMS
)
4128 /* Try and parse a more complex expression, this will probably fail
4129 unless the code uses a floating point prefix (eg "0f"). */
4130 save_in
= input_line_pointer
;
4131 input_line_pointer
= *str
;
4132 if (expression (&exp
) == absolute_section
4133 && exp
.X_op
== O_big
4134 && exp
.X_add_number
< 0)
4136 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4138 if (gen_to_words (words
, 5, (long) 15) == 0)
4140 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4142 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4144 if (words
[j
] != fp_values
[i
][j
])
4148 if (j
== MAX_LITTLENUMS
)
4150 *str
= input_line_pointer
;
4151 input_line_pointer
= save_in
;
4158 *str
= input_line_pointer
;
4159 input_line_pointer
= save_in
;
4160 inst
.error
= _("invalid FPA immediate expression");
4164 /* Returns 1 if a number has "quarter-precision" float format
4165 0baBbbbbbc defgh000 00000000 00000000. */
4168 is_quarter_float (unsigned imm
)
4170 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4171 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4174 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4175 0baBbbbbbc defgh000 00000000 00000000.
4176 The zero and minus-zero cases need special handling, since they can't be
4177 encoded in the "quarter-precision" float format, but can nonetheless be
4178 loaded as integer constants. */
4181 parse_qfloat_immediate (char **ccp
, int *immed
)
4185 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4186 int found_fpchar
= 0;
4188 skip_past_char (&str
, '#');
4190 /* We must not accidentally parse an integer as a floating-point number. Make
4191 sure that the value we parse is not an integer by checking for special
4192 characters '.' or 'e'.
4193 FIXME: This is a horrible hack, but doing better is tricky because type
4194 information isn't in a very usable state at parse time. */
4196 skip_whitespace (fpnum
);
4198 if (strncmp (fpnum
, "0x", 2) == 0)
4202 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4203 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4213 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4215 unsigned fpword
= 0;
4218 /* Our FP word must be 32 bits (single-precision FP). */
4219 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4221 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4225 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4238 /* Shift operands. */
4241 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4244 struct asm_shift_name
4247 enum shift_kind kind
;
4250 /* Third argument to parse_shift. */
4251 enum parse_shift_mode
4253 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4254 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4255 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4256 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4257 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4260 /* Parse a <shift> specifier on an ARM data processing instruction.
4261 This has three forms:
4263 (LSL|LSR|ASL|ASR|ROR) Rs
4264 (LSL|LSR|ASL|ASR|ROR) #imm
4267 Note that ASL is assimilated to LSL in the instruction encoding, and
4268 RRX to ROR #0 (which cannot be written as such). */
4271 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4273 const struct asm_shift_name
*shift_name
;
4274 enum shift_kind shift
;
4279 for (p
= *str
; ISALPHA (*p
); p
++)
4284 inst
.error
= _("shift expression expected");
4288 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4290 if (shift_name
== NULL
)
4292 inst
.error
= _("shift expression expected");
4296 shift
= shift_name
->kind
;
4300 case NO_SHIFT_RESTRICT
:
4301 case SHIFT_IMMEDIATE
: break;
4303 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4304 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4306 inst
.error
= _("'LSL' or 'ASR' required");
4311 case SHIFT_LSL_IMMEDIATE
:
4312 if (shift
!= SHIFT_LSL
)
4314 inst
.error
= _("'LSL' required");
4319 case SHIFT_ASR_IMMEDIATE
:
4320 if (shift
!= SHIFT_ASR
)
4322 inst
.error
= _("'ASR' required");
4330 if (shift
!= SHIFT_RRX
)
4332 /* Whitespace can appear here if the next thing is a bare digit. */
4333 skip_whitespace (p
);
4335 if (mode
== NO_SHIFT_RESTRICT
4336 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4338 inst
.operands
[i
].imm
= reg
;
4339 inst
.operands
[i
].immisreg
= 1;
4341 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4344 inst
.operands
[i
].shift_kind
= shift
;
4345 inst
.operands
[i
].shifted
= 1;
4350 /* Parse a <shifter_operand> for an ARM data processing instruction:
4353 #<immediate>, <rotate>
4357 where <shift> is defined by parse_shift above, and <rotate> is a
4358 multiple of 2 between 0 and 30. Validation of immediate operands
4359 is deferred to md_apply_fix. */
4362 parse_shifter_operand (char **str
, int i
)
4367 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4369 inst
.operands
[i
].reg
= value
;
4370 inst
.operands
[i
].isreg
= 1;
4372 /* parse_shift will override this if appropriate */
4373 inst
.reloc
.exp
.X_op
= O_constant
;
4374 inst
.reloc
.exp
.X_add_number
= 0;
4376 if (skip_past_comma (str
) == FAIL
)
4379 /* Shift operation on register. */
4380 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4383 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4386 if (skip_past_comma (str
) == SUCCESS
)
4388 /* #x, y -- ie explicit rotation by Y. */
4389 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4392 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4394 inst
.error
= _("constant expression expected");
4398 value
= expr
.X_add_number
;
4399 if (value
< 0 || value
> 30 || value
% 2 != 0)
4401 inst
.error
= _("invalid rotation");
4404 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4406 inst
.error
= _("invalid constant");
4410 /* Convert to decoded value. md_apply_fix will put it back. */
4411 inst
.reloc
.exp
.X_add_number
4412 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4413 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4416 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4417 inst
.reloc
.pc_rel
= 0;
4421 /* Group relocation information. Each entry in the table contains the
4422 textual name of the relocation as may appear in assembler source
4423 and must end with a colon.
4424 Along with this textual name are the relocation codes to be used if
4425 the corresponding instruction is an ALU instruction (ADD or SUB only),
4426 an LDR, an LDRS, or an LDC. */
4428 struct group_reloc_table_entry
4439 /* Varieties of non-ALU group relocation. */
4446 static struct group_reloc_table_entry group_reloc_table
[] =
4447 { /* Program counter relative: */
4449 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4454 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4455 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4456 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4457 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4459 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4464 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4465 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4466 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4467 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4469 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4470 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4471 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4472 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4473 /* Section base relative */
4475 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4480 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4481 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4482 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4483 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4485 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4490 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4491 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4492 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4493 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4495 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4496 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4497 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4498 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4500 /* Given the address of a pointer pointing to the textual name of a group
4501 relocation as may appear in assembler source, attempt to find its details
4502 in group_reloc_table. The pointer will be updated to the character after
4503 the trailing colon. On failure, FAIL will be returned; SUCCESS
4504 otherwise. On success, *entry will be updated to point at the relevant
4505 group_reloc_table entry. */
4508 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4511 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4513 int length
= strlen (group_reloc_table
[i
].name
);
4515 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4516 && (*str
)[length
] == ':')
4518 *out
= &group_reloc_table
[i
];
4519 *str
+= (length
+ 1);
4527 /* Parse a <shifter_operand> for an ARM data processing instruction
4528 (as for parse_shifter_operand) where group relocations are allowed:
4531 #<immediate>, <rotate>
4532 #:<group_reloc>:<expression>
4536 where <group_reloc> is one of the strings defined in group_reloc_table.
4537 The hashes are optional.
4539 Everything else is as for parse_shifter_operand. */
4541 static parse_operand_result
4542 parse_shifter_operand_group_reloc (char **str
, int i
)
4544 /* Determine if we have the sequence of characters #: or just :
4545 coming next. If we do, then we check for a group relocation.
4546 If we don't, punt the whole lot to parse_shifter_operand. */
4548 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4549 || (*str
)[0] == ':')
4551 struct group_reloc_table_entry
*entry
;
4553 if ((*str
)[0] == '#')
4558 /* Try to parse a group relocation. Anything else is an error. */
4559 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4561 inst
.error
= _("unknown group relocation");
4562 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4565 /* We now have the group relocation table entry corresponding to
4566 the name in the assembler source. Next, we parse the expression. */
4567 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4568 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4570 /* Record the relocation type (always the ALU variant here). */
4571 inst
.reloc
.type
= entry
->alu_code
;
4572 assert (inst
.reloc
.type
!= 0);
4574 return PARSE_OPERAND_SUCCESS
;
4577 return parse_shifter_operand (str
, i
) == SUCCESS
4578 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4580 /* Never reached. */
4583 /* Parse all forms of an ARM address expression. Information is written
4584 to inst.operands[i] and/or inst.reloc.
4586 Preindexed addressing (.preind=1):
4588 [Rn, #offset] .reg=Rn .reloc.exp=offset
4589 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4590 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4591 .shift_kind=shift .reloc.exp=shift_imm
4593 These three may have a trailing ! which causes .writeback to be set also.
4595 Postindexed addressing (.postind=1, .writeback=1):
4597 [Rn], #offset .reg=Rn .reloc.exp=offset
4598 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4599 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4600 .shift_kind=shift .reloc.exp=shift_imm
4602 Unindexed addressing (.preind=0, .postind=0):
4604 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4608 [Rn]{!} shorthand for [Rn,#0]{!}
4609 =immediate .isreg=0 .reloc.exp=immediate
4610 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4612 It is the caller's responsibility to check for addressing modes not
4613 supported by the instruction, and to set inst.reloc.type. */
4615 static parse_operand_result
4616 parse_address_main (char **str
, int i
, int group_relocations
,
4617 group_reloc_type group_type
)
4622 if (skip_past_char (&p
, '[') == FAIL
)
4624 if (skip_past_char (&p
, '=') == FAIL
)
4626 /* bare address - translate to PC-relative offset */
4627 inst
.reloc
.pc_rel
= 1;
4628 inst
.operands
[i
].reg
= REG_PC
;
4629 inst
.operands
[i
].isreg
= 1;
4630 inst
.operands
[i
].preind
= 1;
4632 /* else a load-constant pseudo op, no special treatment needed here */
4634 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4635 return PARSE_OPERAND_FAIL
;
4638 return PARSE_OPERAND_SUCCESS
;
4641 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4643 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4644 return PARSE_OPERAND_FAIL
;
4646 inst
.operands
[i
].reg
= reg
;
4647 inst
.operands
[i
].isreg
= 1;
4649 if (skip_past_comma (&p
) == SUCCESS
)
4651 inst
.operands
[i
].preind
= 1;
4654 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4656 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4658 inst
.operands
[i
].imm
= reg
;
4659 inst
.operands
[i
].immisreg
= 1;
4661 if (skip_past_comma (&p
) == SUCCESS
)
4662 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4663 return PARSE_OPERAND_FAIL
;
4665 else if (skip_past_char (&p
, ':') == SUCCESS
)
4667 /* FIXME: '@' should be used here, but it's filtered out by generic
4668 code before we get to see it here. This may be subject to
4671 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4672 if (exp
.X_op
!= O_constant
)
4674 inst
.error
= _("alignment must be constant");
4675 return PARSE_OPERAND_FAIL
;
4677 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4678 inst
.operands
[i
].immisalign
= 1;
4679 /* Alignments are not pre-indexes. */
4680 inst
.operands
[i
].preind
= 0;
4684 if (inst
.operands
[i
].negative
)
4686 inst
.operands
[i
].negative
= 0;
4690 if (group_relocations
4691 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4693 struct group_reloc_table_entry
*entry
;
4695 /* Skip over the #: or : sequence. */
4701 /* Try to parse a group relocation. Anything else is an
4703 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4705 inst
.error
= _("unknown group relocation");
4706 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4709 /* We now have the group relocation table entry corresponding to
4710 the name in the assembler source. Next, we parse the
4712 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4713 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4715 /* Record the relocation type. */
4719 inst
.reloc
.type
= entry
->ldr_code
;
4723 inst
.reloc
.type
= entry
->ldrs_code
;
4727 inst
.reloc
.type
= entry
->ldc_code
;
4734 if (inst
.reloc
.type
== 0)
4736 inst
.error
= _("this group relocation is not allowed on this instruction");
4737 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4741 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4742 return PARSE_OPERAND_FAIL
;
4746 if (skip_past_char (&p
, ']') == FAIL
)
4748 inst
.error
= _("']' expected");
4749 return PARSE_OPERAND_FAIL
;
4752 if (skip_past_char (&p
, '!') == SUCCESS
)
4753 inst
.operands
[i
].writeback
= 1;
4755 else if (skip_past_comma (&p
) == SUCCESS
)
4757 if (skip_past_char (&p
, '{') == SUCCESS
)
4759 /* [Rn], {expr} - unindexed, with option */
4760 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4761 0, 255, TRUE
) == FAIL
)
4762 return PARSE_OPERAND_FAIL
;
4764 if (skip_past_char (&p
, '}') == FAIL
)
4766 inst
.error
= _("'}' expected at end of 'option' field");
4767 return PARSE_OPERAND_FAIL
;
4769 if (inst
.operands
[i
].preind
)
4771 inst
.error
= _("cannot combine index with option");
4772 return PARSE_OPERAND_FAIL
;
4775 return PARSE_OPERAND_SUCCESS
;
4779 inst
.operands
[i
].postind
= 1;
4780 inst
.operands
[i
].writeback
= 1;
4782 if (inst
.operands
[i
].preind
)
4784 inst
.error
= _("cannot combine pre- and post-indexing");
4785 return PARSE_OPERAND_FAIL
;
4789 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4791 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4793 /* We might be using the immediate for alignment already. If we
4794 are, OR the register number into the low-order bits. */
4795 if (inst
.operands
[i
].immisalign
)
4796 inst
.operands
[i
].imm
|= reg
;
4798 inst
.operands
[i
].imm
= reg
;
4799 inst
.operands
[i
].immisreg
= 1;
4801 if (skip_past_comma (&p
) == SUCCESS
)
4802 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4803 return PARSE_OPERAND_FAIL
;
4807 if (inst
.operands
[i
].negative
)
4809 inst
.operands
[i
].negative
= 0;
4812 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4813 return PARSE_OPERAND_FAIL
;
4818 /* If at this point neither .preind nor .postind is set, we have a
4819 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4820 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4822 inst
.operands
[i
].preind
= 1;
4823 inst
.reloc
.exp
.X_op
= O_constant
;
4824 inst
.reloc
.exp
.X_add_number
= 0;
4827 return PARSE_OPERAND_SUCCESS
;
4831 parse_address (char **str
, int i
)
4833 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4837 static parse_operand_result
4838 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4840 return parse_address_main (str
, i
, 1, type
);
4843 /* Parse an operand for a MOVW or MOVT instruction. */
4845 parse_half (char **str
)
4850 skip_past_char (&p
, '#');
4851 if (strncasecmp (p
, ":lower16:", 9) == 0)
4852 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4853 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4854 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4856 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4859 skip_whitespace (p
);
4862 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4865 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4867 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4869 inst
.error
= _("constant expression expected");
4872 if (inst
.reloc
.exp
.X_add_number
< 0
4873 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4875 inst
.error
= _("immediate value out of range");
4883 /* Miscellaneous. */
4885 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4886 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4888 parse_psr (char **str
)
4891 unsigned long psr_field
;
4892 const struct asm_psr
*psr
;
4895 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4896 feature for ease of use and backwards compatibility. */
4898 if (strncasecmp (p
, "SPSR", 4) == 0)
4899 psr_field
= SPSR_BIT
;
4900 else if (strncasecmp (p
, "CPSR", 4) == 0)
4907 while (ISALNUM (*p
) || *p
== '_');
4909 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4920 /* A suffix follows. */
4926 while (ISALNUM (*p
) || *p
== '_');
4928 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4932 psr_field
|= psr
->field
;
4937 goto error
; /* Garbage after "[CS]PSR". */
4939 psr_field
|= (PSR_c
| PSR_f
);
4945 inst
.error
= _("flag for {c}psr instruction expected");
4949 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4950 value suitable for splatting into the AIF field of the instruction. */
4953 parse_cps_flags (char **str
)
4962 case '\0': case ',':
4965 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4966 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4967 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4970 inst
.error
= _("unrecognized CPS flag");
4975 if (saw_a_flag
== 0)
4977 inst
.error
= _("missing CPS flags");
4985 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4986 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4989 parse_endian_specifier (char **str
)
4994 if (strncasecmp (s
, "BE", 2))
4996 else if (strncasecmp (s
, "LE", 2))
5000 inst
.error
= _("valid endian specifiers are be or le");
5004 if (ISALNUM (s
[2]) || s
[2] == '_')
5006 inst
.error
= _("valid endian specifiers are be or le");
5011 return little_endian
;
5014 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5015 value suitable for poking into the rotate field of an sxt or sxta
5016 instruction, or FAIL on error. */
5019 parse_ror (char **str
)
5024 if (strncasecmp (s
, "ROR", 3) == 0)
5028 inst
.error
= _("missing rotation field after comma");
5032 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5037 case 0: *str
= s
; return 0x0;
5038 case 8: *str
= s
; return 0x1;
5039 case 16: *str
= s
; return 0x2;
5040 case 24: *str
= s
; return 0x3;
5043 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5048 /* Parse a conditional code (from conds[] below). The value returned is in the
5049 range 0 .. 14, or FAIL. */
5051 parse_cond (char **str
)
5054 const struct asm_cond
*c
;
5056 /* Condition codes are always 2 characters, so matching up to
5057 3 characters is sufficient. */
5062 while (ISALPHA (*q
) && n
< 3)
5064 cond
[n
] = TOLOWER(*q
);
5069 c
= hash_find_n (arm_cond_hsh
, cond
, n
);
5072 inst
.error
= _("condition required");
5080 /* Parse an option for a barrier instruction. Returns the encoding for the
5083 parse_barrier (char **str
)
5086 const struct asm_barrier_opt
*o
;
5089 while (ISALPHA (*q
))
5092 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5100 /* Parse the operands of a table branch instruction. Similar to a memory
5103 parse_tb (char **str
)
5108 if (skip_past_char (&p
, '[') == FAIL
)
5110 inst
.error
= _("'[' expected");
5114 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5116 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5119 inst
.operands
[0].reg
= reg
;
5121 if (skip_past_comma (&p
) == FAIL
)
5123 inst
.error
= _("',' expected");
5127 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5129 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5132 inst
.operands
[0].imm
= reg
;
5134 if (skip_past_comma (&p
) == SUCCESS
)
5136 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5138 if (inst
.reloc
.exp
.X_add_number
!= 1)
5140 inst
.error
= _("invalid shift");
5143 inst
.operands
[0].shifted
= 1;
5146 if (skip_past_char (&p
, ']') == FAIL
)
5148 inst
.error
= _("']' expected");
5155 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5156 information on the types the operands can take and how they are encoded.
5157 Up to four operands may be read; this function handles setting the
5158 ".present" field for each read operand itself.
5159 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5160 else returns FAIL. */
5163 parse_neon_mov (char **str
, int *which_operand
)
5165 int i
= *which_operand
, val
;
5166 enum arm_reg_type rtype
;
5168 struct neon_type_el optype
;
5170 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5172 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5173 inst
.operands
[i
].reg
= val
;
5174 inst
.operands
[i
].isscalar
= 1;
5175 inst
.operands
[i
].vectype
= optype
;
5176 inst
.operands
[i
++].present
= 1;
5178 if (skip_past_comma (&ptr
) == FAIL
)
5181 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5184 inst
.operands
[i
].reg
= val
;
5185 inst
.operands
[i
].isreg
= 1;
5186 inst
.operands
[i
].present
= 1;
5188 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5191 /* Cases 0, 1, 2, 3, 5 (D only). */
5192 if (skip_past_comma (&ptr
) == FAIL
)
5195 inst
.operands
[i
].reg
= val
;
5196 inst
.operands
[i
].isreg
= 1;
5197 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5198 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5199 inst
.operands
[i
].isvec
= 1;
5200 inst
.operands
[i
].vectype
= optype
;
5201 inst
.operands
[i
++].present
= 1;
5203 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5205 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5206 Case 13: VMOV <Sd>, <Rm> */
5207 inst
.operands
[i
].reg
= val
;
5208 inst
.operands
[i
].isreg
= 1;
5209 inst
.operands
[i
].present
= 1;
5211 if (rtype
== REG_TYPE_NQ
)
5213 first_error (_("can't use Neon quad register here"));
5216 else if (rtype
!= REG_TYPE_VFS
)
5219 if (skip_past_comma (&ptr
) == FAIL
)
5221 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5223 inst
.operands
[i
].reg
= val
;
5224 inst
.operands
[i
].isreg
= 1;
5225 inst
.operands
[i
].present
= 1;
5228 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5231 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5232 Case 1: VMOV<c><q> <Dd>, <Dm>
5233 Case 8: VMOV.F32 <Sd>, <Sm>
5234 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5236 inst
.operands
[i
].reg
= val
;
5237 inst
.operands
[i
].isreg
= 1;
5238 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5239 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5240 inst
.operands
[i
].isvec
= 1;
5241 inst
.operands
[i
].vectype
= optype
;
5242 inst
.operands
[i
].present
= 1;
5244 if (skip_past_comma (&ptr
) == SUCCESS
)
5249 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5252 inst
.operands
[i
].reg
= val
;
5253 inst
.operands
[i
].isreg
= 1;
5254 inst
.operands
[i
++].present
= 1;
5256 if (skip_past_comma (&ptr
) == FAIL
)
5259 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5262 inst
.operands
[i
].reg
= val
;
5263 inst
.operands
[i
].isreg
= 1;
5264 inst
.operands
[i
++].present
= 1;
5267 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5268 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5269 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5270 Case 10: VMOV.F32 <Sd>, #<imm>
5271 Case 11: VMOV.F64 <Dd>, #<imm> */
5272 inst
.operands
[i
].immisfloat
= 1;
5273 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5274 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5275 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5279 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5283 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5286 inst
.operands
[i
].reg
= val
;
5287 inst
.operands
[i
].isreg
= 1;
5288 inst
.operands
[i
++].present
= 1;
5290 if (skip_past_comma (&ptr
) == FAIL
)
5293 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5295 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5296 inst
.operands
[i
].reg
= val
;
5297 inst
.operands
[i
].isscalar
= 1;
5298 inst
.operands
[i
].present
= 1;
5299 inst
.operands
[i
].vectype
= optype
;
5301 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5303 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5304 inst
.operands
[i
].reg
= val
;
5305 inst
.operands
[i
].isreg
= 1;
5306 inst
.operands
[i
++].present
= 1;
5308 if (skip_past_comma (&ptr
) == FAIL
)
5311 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5314 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5318 inst
.operands
[i
].reg
= val
;
5319 inst
.operands
[i
].isreg
= 1;
5320 inst
.operands
[i
].isvec
= 1;
5321 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5322 inst
.operands
[i
].vectype
= optype
;
5323 inst
.operands
[i
].present
= 1;
5325 if (rtype
== REG_TYPE_VFS
)
5329 if (skip_past_comma (&ptr
) == FAIL
)
5331 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5334 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5337 inst
.operands
[i
].reg
= val
;
5338 inst
.operands
[i
].isreg
= 1;
5339 inst
.operands
[i
].isvec
= 1;
5340 inst
.operands
[i
].issingle
= 1;
5341 inst
.operands
[i
].vectype
= optype
;
5342 inst
.operands
[i
].present
= 1;
5345 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5349 inst
.operands
[i
].reg
= val
;
5350 inst
.operands
[i
].isreg
= 1;
5351 inst
.operands
[i
].isvec
= 1;
5352 inst
.operands
[i
].issingle
= 1;
5353 inst
.operands
[i
].vectype
= optype
;
5354 inst
.operands
[i
++].present
= 1;
5359 first_error (_("parse error"));
5363 /* Successfully parsed the operands. Update args. */
5369 first_error (_("expected comma"));
5373 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5377 /* Matcher codes for parse_operands. */
5378 enum operand_parse_code
5380 OP_stop
, /* end of line */
5382 OP_RR
, /* ARM register */
5383 OP_RRnpc
, /* ARM register, not r15 */
5384 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5385 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5386 OP_RCP
, /* Coprocessor number */
5387 OP_RCN
, /* Coprocessor register */
5388 OP_RF
, /* FPA register */
5389 OP_RVS
, /* VFP single precision register */
5390 OP_RVD
, /* VFP double precision register (0..15) */
5391 OP_RND
, /* Neon double precision register (0..31) */
5392 OP_RNQ
, /* Neon quad precision register */
5393 OP_RVSD
, /* VFP single or double precision register */
5394 OP_RNDQ
, /* Neon double or quad precision register */
5395 OP_RNSDQ
, /* Neon single, double or quad precision register */
5396 OP_RNSC
, /* Neon scalar D[X] */
5397 OP_RVC
, /* VFP control register */
5398 OP_RMF
, /* Maverick F register */
5399 OP_RMD
, /* Maverick D register */
5400 OP_RMFX
, /* Maverick FX register */
5401 OP_RMDX
, /* Maverick DX register */
5402 OP_RMAX
, /* Maverick AX register */
5403 OP_RMDS
, /* Maverick DSPSC register */
5404 OP_RIWR
, /* iWMMXt wR register */
5405 OP_RIWC
, /* iWMMXt wC register */
5406 OP_RIWG
, /* iWMMXt wCG register */
5407 OP_RXA
, /* XScale accumulator register */
5409 OP_REGLST
, /* ARM register list */
5410 OP_VRSLST
, /* VFP single-precision register list */
5411 OP_VRDLST
, /* VFP double-precision register list */
5412 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5413 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5414 OP_NSTRLST
, /* Neon element/structure list */
5416 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5417 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5418 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5419 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5420 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5421 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5422 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5423 OP_VMOV
, /* Neon VMOV operands. */
5424 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5425 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5426 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5428 OP_I0
, /* immediate zero */
5429 OP_I7
, /* immediate value 0 .. 7 */
5430 OP_I15
, /* 0 .. 15 */
5431 OP_I16
, /* 1 .. 16 */
5432 OP_I16z
, /* 0 .. 16 */
5433 OP_I31
, /* 0 .. 31 */
5434 OP_I31w
, /* 0 .. 31, optional trailing ! */
5435 OP_I32
, /* 1 .. 32 */
5436 OP_I32z
, /* 0 .. 32 */
5437 OP_I63
, /* 0 .. 63 */
5438 OP_I63s
, /* -64 .. 63 */
5439 OP_I64
, /* 1 .. 64 */
5440 OP_I64z
, /* 0 .. 64 */
5441 OP_I255
, /* 0 .. 255 */
5443 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5444 OP_I7b
, /* 0 .. 7 */
5445 OP_I15b
, /* 0 .. 15 */
5446 OP_I31b
, /* 0 .. 31 */
5448 OP_SH
, /* shifter operand */
5449 OP_SHG
, /* shifter operand with possible group relocation */
5450 OP_ADDR
, /* Memory address expression (any mode) */
5451 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5452 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5453 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5454 OP_EXP
, /* arbitrary expression */
5455 OP_EXPi
, /* same, with optional immediate prefix */
5456 OP_EXPr
, /* same, with optional relocation suffix */
5457 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5459 OP_CPSF
, /* CPS flags */
5460 OP_ENDI
, /* Endianness specifier */
5461 OP_PSR
, /* CPSR/SPSR mask for msr */
5462 OP_COND
, /* conditional code */
5463 OP_TB
, /* Table branch. */
5465 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5466 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5468 OP_RRnpc_I0
, /* ARM register or literal 0 */
5469 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5470 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5471 OP_RF_IF
, /* FPA register or immediate */
5472 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5473 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5475 /* Optional operands. */
5476 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5477 OP_oI31b
, /* 0 .. 31 */
5478 OP_oI32b
, /* 1 .. 32 */
5479 OP_oIffffb
, /* 0 .. 65535 */
5480 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5482 OP_oRR
, /* ARM register */
5483 OP_oRRnpc
, /* ARM register, not the PC */
5484 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5485 OP_oRND
, /* Optional Neon double precision register */
5486 OP_oRNQ
, /* Optional Neon quad precision register */
5487 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5488 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5489 OP_oSHll
, /* LSL immediate */
5490 OP_oSHar
, /* ASR immediate */
5491 OP_oSHllar
, /* LSL or ASR immediate */
5492 OP_oROR
, /* ROR 0/8/16/24 */
5493 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5495 OP_FIRST_OPTIONAL
= OP_oI7b
5498 /* Generic instruction operand parser. This does no encoding and no
5499 semantic validation; it merely squirrels values away in the inst
5500 structure. Returns SUCCESS or FAIL depending on whether the
5501 specified grammar matched. */
5503 parse_operands (char *str
, const unsigned char *pattern
)
5505 unsigned const char *upat
= pattern
;
5506 char *backtrack_pos
= 0;
5507 const char *backtrack_error
= 0;
5508 int i
, val
, backtrack_index
= 0;
5509 enum arm_reg_type rtype
;
5510 parse_operand_result result
;
5512 #define po_char_or_fail(chr) do { \
5513 if (skip_past_char (&str, chr) == FAIL) \
5517 #define po_reg_or_fail(regtype) do { \
5518 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5519 &inst.operands[i].vectype); \
5522 first_error (_(reg_expected_msgs[regtype])); \
5525 inst.operands[i].reg = val; \
5526 inst.operands[i].isreg = 1; \
5527 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5528 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5529 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5530 || rtype == REG_TYPE_VFD \
5531 || rtype == REG_TYPE_NQ); \
5534 #define po_reg_or_goto(regtype, label) do { \
5535 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5536 &inst.operands[i].vectype); \
5540 inst.operands[i].reg = val; \
5541 inst.operands[i].isreg = 1; \
5542 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5543 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5544 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5545 || rtype == REG_TYPE_VFD \
5546 || rtype == REG_TYPE_NQ); \
5549 #define po_imm_or_fail(min, max, popt) do { \
5550 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5552 inst.operands[i].imm = val; \
5555 #define po_scalar_or_goto(elsz, label) do { \
5556 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5559 inst.operands[i].reg = val; \
5560 inst.operands[i].isscalar = 1; \
5563 #define po_misc_or_fail(expr) do { \
5568 #define po_misc_or_fail_no_backtrack(expr) do { \
5570 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5571 backtrack_pos = 0; \
5572 if (result != PARSE_OPERAND_SUCCESS) \
5576 skip_whitespace (str
);
5578 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5580 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5582 /* Remember where we are in case we need to backtrack. */
5583 assert (!backtrack_pos
);
5584 backtrack_pos
= str
;
5585 backtrack_error
= inst
.error
;
5586 backtrack_index
= i
;
5589 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5590 po_char_or_fail (',');
5598 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5599 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5600 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5601 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5602 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5603 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5605 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5607 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5609 /* Also accept generic coprocessor regs for unknown registers. */
5611 po_reg_or_fail (REG_TYPE_CN
);
5613 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5614 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5615 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5616 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5617 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5618 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5619 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5620 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5621 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5622 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5624 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5626 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5627 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5629 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5631 /* Neon scalar. Using an element size of 8 means that some invalid
5632 scalars are accepted here, so deal with those in later code. */
5633 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5635 /* WARNING: We can expand to two operands here. This has the potential
5636 to totally confuse the backtracking mechanism! It will be OK at
5637 least as long as we don't try to use optional args as well,
5641 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5642 inst
.operands
[i
].present
= 1;
5644 skip_past_comma (&str
);
5645 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5648 /* Optional register operand was omitted. Unfortunately, it's in
5649 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5650 here (this is a bit grotty). */
5651 inst
.operands
[i
] = inst
.operands
[i
-1];
5652 inst
.operands
[i
-1].present
= 0;
5655 /* There's a possibility of getting a 64-bit immediate here, so
5656 we need special handling. */
5657 if (parse_big_immediate (&str
, i
) == FAIL
)
5659 inst
.error
= _("immediate value is out of range");
5667 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5670 po_imm_or_fail (0, 0, TRUE
);
5675 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5680 po_scalar_or_goto (8, try_rr
);
5683 po_reg_or_fail (REG_TYPE_RN
);
5689 po_scalar_or_goto (8, try_nsdq
);
5692 po_reg_or_fail (REG_TYPE_NSDQ
);
5698 po_scalar_or_goto (8, try_ndq
);
5701 po_reg_or_fail (REG_TYPE_NDQ
);
5707 po_scalar_or_goto (8, try_vfd
);
5710 po_reg_or_fail (REG_TYPE_VFD
);
5715 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5716 not careful then bad things might happen. */
5717 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5722 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5725 /* There's a possibility of getting a 64-bit immediate here, so
5726 we need special handling. */
5727 if (parse_big_immediate (&str
, i
) == FAIL
)
5729 inst
.error
= _("immediate value is out of range");
5737 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5740 po_imm_or_fail (0, 63, TRUE
);
5745 po_char_or_fail ('[');
5746 po_reg_or_fail (REG_TYPE_RN
);
5747 po_char_or_fail (']');
5752 po_reg_or_fail (REG_TYPE_RN
);
5753 if (skip_past_char (&str
, '!') == SUCCESS
)
5754 inst
.operands
[i
].writeback
= 1;
5758 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5759 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5760 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5761 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5762 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5763 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5764 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5765 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5766 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5767 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5768 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5769 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5771 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5773 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5774 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5776 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5777 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5778 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5780 /* Immediate variants */
5782 po_char_or_fail ('{');
5783 po_imm_or_fail (0, 255, TRUE
);
5784 po_char_or_fail ('}');
5788 /* The expression parser chokes on a trailing !, so we have
5789 to find it first and zap it. */
5792 while (*s
&& *s
!= ',')
5797 inst
.operands
[i
].writeback
= 1;
5799 po_imm_or_fail (0, 31, TRUE
);
5807 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5812 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5817 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5819 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5821 val
= parse_reloc (&str
);
5824 inst
.error
= _("unrecognized relocation suffix");
5827 else if (val
!= BFD_RELOC_UNUSED
)
5829 inst
.operands
[i
].imm
= val
;
5830 inst
.operands
[i
].hasreloc
= 1;
5835 /* Operand for MOVW or MOVT. */
5837 po_misc_or_fail (parse_half (&str
));
5840 /* Register or expression */
5841 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5842 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5844 /* Register or immediate */
5845 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5846 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5848 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5850 if (!is_immediate_prefix (*str
))
5853 val
= parse_fpa_immediate (&str
);
5856 /* FPA immediates are encoded as registers 8-15.
5857 parse_fpa_immediate has already applied the offset. */
5858 inst
.operands
[i
].reg
= val
;
5859 inst
.operands
[i
].isreg
= 1;
5862 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5863 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5865 /* Two kinds of register */
5868 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5870 || (rege
->type
!= REG_TYPE_MMXWR
5871 && rege
->type
!= REG_TYPE_MMXWC
5872 && rege
->type
!= REG_TYPE_MMXWCG
))
5874 inst
.error
= _("iWMMXt data or control register expected");
5877 inst
.operands
[i
].reg
= rege
->number
;
5878 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5884 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5886 || (rege
->type
!= REG_TYPE_MMXWC
5887 && rege
->type
!= REG_TYPE_MMXWCG
))
5889 inst
.error
= _("iWMMXt control register expected");
5892 inst
.operands
[i
].reg
= rege
->number
;
5893 inst
.operands
[i
].isreg
= 1;
5898 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5899 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5900 case OP_oROR
: val
= parse_ror (&str
); break;
5901 case OP_PSR
: val
= parse_psr (&str
); break;
5902 case OP_COND
: val
= parse_cond (&str
); break;
5903 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5906 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5907 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5910 val
= parse_psr (&str
);
5914 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5917 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5919 if (strncasecmp (str
, "APSR_", 5) == 0)
5926 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5927 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5928 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5929 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5930 default: found
= 16;
5934 inst
.operands
[i
].isvec
= 1;
5941 po_misc_or_fail (parse_tb (&str
));
5944 /* Register lists */
5946 val
= parse_reg_list (&str
);
5949 inst
.operands
[1].writeback
= 1;
5955 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5959 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5963 /* Allow Q registers too. */
5964 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5969 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5971 inst
.operands
[i
].issingle
= 1;
5976 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5981 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5982 &inst
.operands
[i
].vectype
);
5985 /* Addressing modes */
5987 po_misc_or_fail (parse_address (&str
, i
));
5991 po_misc_or_fail_no_backtrack (
5992 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5996 po_misc_or_fail_no_backtrack (
5997 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6001 po_misc_or_fail_no_backtrack (
6002 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6006 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6010 po_misc_or_fail_no_backtrack (
6011 parse_shifter_operand_group_reloc (&str
, i
));
6015 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6019 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6023 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6027 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6030 /* Various value-based sanity checks and shared operations. We
6031 do not signal immediate failures for the register constraints;
6032 this allows a syntax error to take precedence. */
6041 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6042 inst
.error
= BAD_PC
;
6060 inst
.operands
[i
].imm
= val
;
6067 /* If we get here, this operand was successfully parsed. */
6068 inst
.operands
[i
].present
= 1;
6072 inst
.error
= BAD_ARGS
;
6077 /* The parse routine should already have set inst.error, but set a
6078 default here just in case. */
6080 inst
.error
= _("syntax error");
6084 /* Do not backtrack over a trailing optional argument that
6085 absorbed some text. We will only fail again, with the
6086 'garbage following instruction' error message, which is
6087 probably less helpful than the current one. */
6088 if (backtrack_index
== i
&& backtrack_pos
!= str
6089 && upat
[i
+1] == OP_stop
)
6092 inst
.error
= _("syntax error");
6096 /* Try again, skipping the optional argument at backtrack_pos. */
6097 str
= backtrack_pos
;
6098 inst
.error
= backtrack_error
;
6099 inst
.operands
[backtrack_index
].present
= 0;
6100 i
= backtrack_index
;
6104 /* Check that we have parsed all the arguments. */
6105 if (*str
!= '\0' && !inst
.error
)
6106 inst
.error
= _("garbage following instruction");
6108 return inst
.error
? FAIL
: SUCCESS
;
6111 #undef po_char_or_fail
6112 #undef po_reg_or_fail
6113 #undef po_reg_or_goto
6114 #undef po_imm_or_fail
6115 #undef po_scalar_or_fail
6117 /* Shorthand macro for instruction encoding functions issuing errors. */
6118 #define constraint(expr, err) do { \
6126 /* Functions for operand encoding. ARM, then Thumb. */
6128 #define rotate_left(v, n) (v << n | v >> (32 - n))
6130 /* If VAL can be encoded in the immediate field of an ARM instruction,
6131 return the encoded form. Otherwise, return FAIL. */
6134 encode_arm_immediate (unsigned int val
)
6138 for (i
= 0; i
< 32; i
+= 2)
6139 if ((a
= rotate_left (val
, i
)) <= 0xff)
6140 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6145 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6146 return the encoded form. Otherwise, return FAIL. */
6148 encode_thumb32_immediate (unsigned int val
)
6155 for (i
= 1; i
<= 24; i
++)
6158 if ((val
& ~(0xff << i
)) == 0)
6159 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6163 if (val
== ((a
<< 16) | a
))
6165 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6169 if (val
== ((a
<< 16) | a
))
6170 return 0x200 | (a
>> 8);
6174 /* Encode a VFP SP or DP register number into inst.instruction. */
6177 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6179 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6182 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6185 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6188 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6193 first_error (_("D register out of range for selected VFP version"));
6201 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6205 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6209 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6213 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6217 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6221 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6229 /* Encode a <shift> in an ARM-format instruction. The immediate,
6230 if any, is handled by md_apply_fix. */
6232 encode_arm_shift (int i
)
6234 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6235 inst
.instruction
|= SHIFT_ROR
<< 5;
6238 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6239 if (inst
.operands
[i
].immisreg
)
6241 inst
.instruction
|= SHIFT_BY_REG
;
6242 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6245 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6250 encode_arm_shifter_operand (int i
)
6252 if (inst
.operands
[i
].isreg
)
6254 inst
.instruction
|= inst
.operands
[i
].reg
;
6255 encode_arm_shift (i
);
6258 inst
.instruction
|= INST_IMMEDIATE
;
6261 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6263 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6265 assert (inst
.operands
[i
].isreg
);
6266 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6268 if (inst
.operands
[i
].preind
)
6272 inst
.error
= _("instruction does not accept preindexed addressing");
6275 inst
.instruction
|= PRE_INDEX
;
6276 if (inst
.operands
[i
].writeback
)
6277 inst
.instruction
|= WRITE_BACK
;
6280 else if (inst
.operands
[i
].postind
)
6282 assert (inst
.operands
[i
].writeback
);
6284 inst
.instruction
|= WRITE_BACK
;
6286 else /* unindexed - only for coprocessor */
6288 inst
.error
= _("instruction does not accept unindexed addressing");
6292 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6293 && (((inst
.instruction
& 0x000f0000) >> 16)
6294 == ((inst
.instruction
& 0x0000f000) >> 12)))
6295 as_warn ((inst
.instruction
& LOAD_BIT
)
6296 ? _("destination register same as write-back base")
6297 : _("source register same as write-back base"));
6300 /* inst.operands[i] was set up by parse_address. Encode it into an
6301 ARM-format mode 2 load or store instruction. If is_t is true,
6302 reject forms that cannot be used with a T instruction (i.e. not
6305 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6307 encode_arm_addr_mode_common (i
, is_t
);
6309 if (inst
.operands
[i
].immisreg
)
6311 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6312 inst
.instruction
|= inst
.operands
[i
].imm
;
6313 if (!inst
.operands
[i
].negative
)
6314 inst
.instruction
|= INDEX_UP
;
6315 if (inst
.operands
[i
].shifted
)
6317 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6318 inst
.instruction
|= SHIFT_ROR
<< 5;
6321 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6322 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6326 else /* immediate offset in inst.reloc */
6328 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6329 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6333 /* inst.operands[i] was set up by parse_address. Encode it into an
6334 ARM-format mode 3 load or store instruction. Reject forms that
6335 cannot be used with such instructions. If is_t is true, reject
6336 forms that cannot be used with a T instruction (i.e. not
6339 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6341 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6343 inst
.error
= _("instruction does not accept scaled register index");
6347 encode_arm_addr_mode_common (i
, is_t
);
6349 if (inst
.operands
[i
].immisreg
)
6351 inst
.instruction
|= inst
.operands
[i
].imm
;
6352 if (!inst
.operands
[i
].negative
)
6353 inst
.instruction
|= INDEX_UP
;
6355 else /* immediate offset in inst.reloc */
6357 inst
.instruction
|= HWOFFSET_IMM
;
6358 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6359 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6363 /* inst.operands[i] was set up by parse_address. Encode it into an
6364 ARM-format instruction. Reject all forms which cannot be encoded
6365 into a coprocessor load/store instruction. If wb_ok is false,
6366 reject use of writeback; if unind_ok is false, reject use of
6367 unindexed addressing. If reloc_override is not 0, use it instead
6368 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6369 (in which case it is preserved). */
6372 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6374 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6376 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6378 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6380 assert (!inst
.operands
[i
].writeback
);
6383 inst
.error
= _("instruction does not support unindexed addressing");
6386 inst
.instruction
|= inst
.operands
[i
].imm
;
6387 inst
.instruction
|= INDEX_UP
;
6391 if (inst
.operands
[i
].preind
)
6392 inst
.instruction
|= PRE_INDEX
;
6394 if (inst
.operands
[i
].writeback
)
6396 if (inst
.operands
[i
].reg
== REG_PC
)
6398 inst
.error
= _("pc may not be used with write-back");
6403 inst
.error
= _("instruction does not support writeback");
6406 inst
.instruction
|= WRITE_BACK
;
6410 inst
.reloc
.type
= reloc_override
;
6411 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6412 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6413 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6416 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6418 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6424 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6425 Determine whether it can be performed with a move instruction; if
6426 it can, convert inst.instruction to that move instruction and
6427 return 1; if it can't, convert inst.instruction to a literal-pool
6428 load and return 0. If this is not a valid thing to do in the
6429 current context, set inst.error and return 1.
6431 inst.operands[i] describes the destination register. */
6434 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6439 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6443 if ((inst
.instruction
& tbit
) == 0)
6445 inst
.error
= _("invalid pseudo operation");
6448 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6450 inst
.error
= _("constant expression expected");
6453 if (inst
.reloc
.exp
.X_op
== O_constant
)
6457 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6459 /* This can be done with a mov(1) instruction. */
6460 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6461 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6467 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6470 /* This can be done with a mov instruction. */
6471 inst
.instruction
&= LITERAL_MASK
;
6472 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6473 inst
.instruction
|= value
& 0xfff;
6477 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6480 /* This can be done with a mvn instruction. */
6481 inst
.instruction
&= LITERAL_MASK
;
6482 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6483 inst
.instruction
|= value
& 0xfff;
6489 if (add_to_lit_pool () == FAIL
)
6491 inst
.error
= _("literal pool insertion failed");
6494 inst
.operands
[1].reg
= REG_PC
;
6495 inst
.operands
[1].isreg
= 1;
6496 inst
.operands
[1].preind
= 1;
6497 inst
.reloc
.pc_rel
= 1;
6498 inst
.reloc
.type
= (thumb_p
6499 ? BFD_RELOC_ARM_THUMB_OFFSET
6501 ? BFD_RELOC_ARM_HWLITERAL
6502 : BFD_RELOC_ARM_LITERAL
));
6506 /* Functions for instruction encoding, sorted by sub-architecture.
6507 First some generics; their names are taken from the conventional
6508 bit positions for register arguments in ARM format instructions. */
6518 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6524 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6525 inst
.instruction
|= inst
.operands
[1].reg
;
6531 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6532 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6538 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6539 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6545 unsigned Rn
= inst
.operands
[2].reg
;
6546 /* Enforce restrictions on SWP instruction. */
6547 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6548 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6549 _("Rn must not overlap other operands"));
6550 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6551 inst
.instruction
|= inst
.operands
[1].reg
;
6552 inst
.instruction
|= Rn
<< 16;
6558 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6559 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6560 inst
.instruction
|= inst
.operands
[2].reg
;
6566 inst
.instruction
|= inst
.operands
[0].reg
;
6567 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6568 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6574 inst
.instruction
|= inst
.operands
[0].imm
;
6580 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6581 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6584 /* ARM instructions, in alphabetical order by function name (except
6585 that wrapper functions appear immediately after the function they
6588 /* This is a pseudo-op of the form "adr rd, label" to be converted
6589 into a relative address of the form "add rd, pc, #label-.-8". */
6594 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6596 /* Frag hacking will turn this into a sub instruction if the offset turns
6597 out to be negative. */
6598 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6599 inst
.reloc
.pc_rel
= 1;
6600 inst
.reloc
.exp
.X_add_number
-= 8;
6603 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6604 into a relative address of the form:
6605 add rd, pc, #low(label-.-8)"
6606 add rd, rd, #high(label-.-8)" */
6611 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6613 /* Frag hacking will turn this into a sub instruction if the offset turns
6614 out to be negative. */
6615 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6616 inst
.reloc
.pc_rel
= 1;
6617 inst
.size
= INSN_SIZE
* 2;
6618 inst
.reloc
.exp
.X_add_number
-= 8;
6624 if (!inst
.operands
[1].present
)
6625 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6626 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6627 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6628 encode_arm_shifter_operand (2);
6634 if (inst
.operands
[0].present
)
6636 constraint ((inst
.instruction
& 0xf0) != 0x40
6637 && inst
.operands
[0].imm
!= 0xf,
6638 _("bad barrier type"));
6639 inst
.instruction
|= inst
.operands
[0].imm
;
6642 inst
.instruction
|= 0xf;
6648 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6649 constraint (msb
> 32, _("bit-field extends past end of register"));
6650 /* The instruction encoding stores the LSB and MSB,
6651 not the LSB and width. */
6652 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6653 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6654 inst
.instruction
|= (msb
- 1) << 16;
6662 /* #0 in second position is alternative syntax for bfc, which is
6663 the same instruction but with REG_PC in the Rm field. */
6664 if (!inst
.operands
[1].isreg
)
6665 inst
.operands
[1].reg
= REG_PC
;
6667 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6668 constraint (msb
> 32, _("bit-field extends past end of register"));
6669 /* The instruction encoding stores the LSB and MSB,
6670 not the LSB and width. */
6671 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6672 inst
.instruction
|= inst
.operands
[1].reg
;
6673 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6674 inst
.instruction
|= (msb
- 1) << 16;
6680 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6681 _("bit-field extends past end of register"));
6682 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6683 inst
.instruction
|= inst
.operands
[1].reg
;
6684 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6685 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6688 /* ARM V5 breakpoint instruction (argument parse)
6689 BKPT <16 bit unsigned immediate>
6690 Instruction is not conditional.
6691 The bit pattern given in insns[] has the COND_ALWAYS condition,
6692 and it is an error if the caller tried to override that. */
6697 /* Top 12 of 16 bits to bits 19:8. */
6698 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6700 /* Bottom 4 of 16 bits to bits 3:0. */
6701 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6705 encode_branch (int default_reloc
)
6707 if (inst
.operands
[0].hasreloc
)
6709 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6710 _("the only suffix valid here is '(plt)'"));
6711 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6715 inst
.reloc
.type
= default_reloc
;
6717 inst
.reloc
.pc_rel
= 1;
6724 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6725 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6728 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6735 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6737 if (inst
.cond
== COND_ALWAYS
)
6738 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6740 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6744 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6747 /* ARM V5 branch-link-exchange instruction (argument parse)
6748 BLX <target_addr> ie BLX(1)
6749 BLX{<condition>} <Rm> ie BLX(2)
6750 Unfortunately, there are two different opcodes for this mnemonic.
6751 So, the insns[].value is not used, and the code here zaps values
6752 into inst.instruction.
6753 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6758 if (inst
.operands
[0].isreg
)
6760 /* Arg is a register; the opcode provided by insns[] is correct.
6761 It is not illegal to do "blx pc", just useless. */
6762 if (inst
.operands
[0].reg
== REG_PC
)
6763 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6765 inst
.instruction
|= inst
.operands
[0].reg
;
6769 /* Arg is an address; this instruction cannot be executed
6770 conditionally, and the opcode must be adjusted. */
6771 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6772 inst
.instruction
= 0xfa000000;
6774 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6775 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6778 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6785 bfd_boolean want_reloc
;
6787 if (inst
.operands
[0].reg
== REG_PC
)
6788 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6790 inst
.instruction
|= inst
.operands
[0].reg
;
6791 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
6792 it is for ARMv4t or earlier. */
6793 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
6794 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
6798 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
6803 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
6807 /* ARM v5TEJ. Jump to Jazelle code. */
6812 if (inst
.operands
[0].reg
== REG_PC
)
6813 as_tsktsk (_("use of r15 in bxj is not really useful"));
6815 inst
.instruction
|= inst
.operands
[0].reg
;
6818 /* Co-processor data operation:
6819 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6820 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6824 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6825 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6826 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6827 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6828 inst
.instruction
|= inst
.operands
[4].reg
;
6829 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6835 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6836 encode_arm_shifter_operand (1);
6839 /* Transfer between coprocessor and ARM registers.
6840 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6845 No special properties. */
6850 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6851 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6852 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6853 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6854 inst
.instruction
|= inst
.operands
[4].reg
;
6855 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6858 /* Transfer between coprocessor register and pair of ARM registers.
6859 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6864 Two XScale instructions are special cases of these:
6866 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6867 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6869 Result unpredictable if Rd or Rn is R15. */
6874 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6875 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6876 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6877 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6878 inst
.instruction
|= inst
.operands
[4].reg
;
6884 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6885 if (inst
.operands
[1].present
)
6887 inst
.instruction
|= CPSI_MMOD
;
6888 inst
.instruction
|= inst
.operands
[1].imm
;
6895 inst
.instruction
|= inst
.operands
[0].imm
;
6901 /* There is no IT instruction in ARM mode. We
6902 process it but do not generate code for it. */
6909 int base_reg
= inst
.operands
[0].reg
;
6910 int range
= inst
.operands
[1].imm
;
6912 inst
.instruction
|= base_reg
<< 16;
6913 inst
.instruction
|= range
;
6915 if (inst
.operands
[1].writeback
)
6916 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6918 if (inst
.operands
[0].writeback
)
6920 inst
.instruction
|= WRITE_BACK
;
6921 /* Check for unpredictable uses of writeback. */
6922 if (inst
.instruction
& LOAD_BIT
)
6924 /* Not allowed in LDM type 2. */
6925 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6926 && ((range
& (1 << REG_PC
)) == 0))
6927 as_warn (_("writeback of base register is UNPREDICTABLE"));
6928 /* Only allowed if base reg not in list for other types. */
6929 else if (range
& (1 << base_reg
))
6930 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6934 /* Not allowed for type 2. */
6935 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6936 as_warn (_("writeback of base register is UNPREDICTABLE"));
6937 /* Only allowed if base reg not in list, or first in list. */
6938 else if ((range
& (1 << base_reg
))
6939 && (range
& ((1 << base_reg
) - 1)))
6940 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6945 /* ARMv5TE load-consecutive (argument parse)
6954 constraint (inst
.operands
[0].reg
% 2 != 0,
6955 _("first destination register must be even"));
6956 constraint (inst
.operands
[1].present
6957 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6958 _("can only load two consecutive registers"));
6959 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6960 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6962 if (!inst
.operands
[1].present
)
6963 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6965 if (inst
.instruction
& LOAD_BIT
)
6967 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6968 register and the first register written; we have to diagnose
6969 overlap between the base and the second register written here. */
6971 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6972 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6973 as_warn (_("base register written back, and overlaps "
6974 "second destination register"));
6976 /* For an index-register load, the index register must not overlap the
6977 destination (even if not write-back). */
6978 else if (inst
.operands
[2].immisreg
6979 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6980 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6981 as_warn (_("index register overlaps destination register"));
6984 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6985 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6991 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6992 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6993 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6994 || inst
.operands
[1].negative
6995 /* This can arise if the programmer has written
6997 or if they have mistakenly used a register name as the last
7000 It is very difficult to distinguish between these two cases
7001 because "rX" might actually be a label. ie the register
7002 name has been occluded by a symbol of the same name. So we
7003 just generate a general 'bad addressing mode' type error
7004 message and leave it up to the programmer to discover the
7005 true cause and fix their mistake. */
7006 || (inst
.operands
[1].reg
== REG_PC
),
7009 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7010 || inst
.reloc
.exp
.X_add_number
!= 0,
7011 _("offset must be zero in ARM encoding"));
7013 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7014 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7015 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7021 constraint (inst
.operands
[0].reg
% 2 != 0,
7022 _("even register required"));
7023 constraint (inst
.operands
[1].present
7024 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7025 _("can only load two consecutive registers"));
7026 /* If op 1 were present and equal to PC, this function wouldn't
7027 have been called in the first place. */
7028 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7031 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7037 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7038 if (!inst
.operands
[1].isreg
)
7039 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7041 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7047 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7049 if (inst
.operands
[1].preind
)
7051 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7052 || inst
.reloc
.exp
.X_add_number
!= 0,
7053 _("this instruction requires a post-indexed address"));
7055 inst
.operands
[1].preind
= 0;
7056 inst
.operands
[1].postind
= 1;
7057 inst
.operands
[1].writeback
= 1;
7059 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7060 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7063 /* Halfword and signed-byte load/store operations. */
7068 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7069 if (!inst
.operands
[1].isreg
)
7070 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7072 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7078 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7080 if (inst
.operands
[1].preind
)
7082 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7083 || inst
.reloc
.exp
.X_add_number
!= 0,
7084 _("this instruction requires a post-indexed address"));
7086 inst
.operands
[1].preind
= 0;
7087 inst
.operands
[1].postind
= 1;
7088 inst
.operands
[1].writeback
= 1;
7090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7091 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7094 /* Co-processor register load/store.
7095 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7099 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7100 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7101 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7107 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7108 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7109 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7110 && !(inst
.instruction
& 0x00400000))
7111 as_tsktsk (_("Rd and Rm should be different in mla"));
7113 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7114 inst
.instruction
|= inst
.operands
[1].reg
;
7115 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7116 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7122 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7123 encode_arm_shifter_operand (1);
7126 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7133 top
= (inst
.instruction
& 0x00400000) != 0;
7134 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7135 _(":lower16: not allowed this instruction"));
7136 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7137 _(":upper16: not allowed instruction"));
7138 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7139 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7141 imm
= inst
.reloc
.exp
.X_add_number
;
7142 /* The value is in two pieces: 0:11, 16:19. */
7143 inst
.instruction
|= (imm
& 0x00000fff);
7144 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7148 static void do_vfp_nsyn_opcode (const char *);
7151 do_vfp_nsyn_mrs (void)
7153 if (inst
.operands
[0].isvec
)
7155 if (inst
.operands
[1].reg
!= 1)
7156 first_error (_("operand 1 must be FPSCR"));
7157 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7158 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7159 do_vfp_nsyn_opcode ("fmstat");
7161 else if (inst
.operands
[1].isvec
)
7162 do_vfp_nsyn_opcode ("fmrx");
7170 do_vfp_nsyn_msr (void)
7172 if (inst
.operands
[0].isvec
)
7173 do_vfp_nsyn_opcode ("fmxr");
7183 if (do_vfp_nsyn_mrs () == SUCCESS
)
7186 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7187 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7189 _("'CPSR' or 'SPSR' expected"));
7190 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7191 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7194 /* Two possible forms:
7195 "{C|S}PSR_<field>, Rm",
7196 "{C|S}PSR_f, #expression". */
7201 if (do_vfp_nsyn_msr () == SUCCESS
)
7204 inst
.instruction
|= inst
.operands
[0].imm
;
7205 if (inst
.operands
[1].isreg
)
7206 inst
.instruction
|= inst
.operands
[1].reg
;
7209 inst
.instruction
|= INST_IMMEDIATE
;
7210 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7211 inst
.reloc
.pc_rel
= 0;
7218 if (!inst
.operands
[2].present
)
7219 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7220 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7221 inst
.instruction
|= inst
.operands
[1].reg
;
7222 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7224 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7225 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7226 as_tsktsk (_("Rd and Rm should be different in mul"));
7229 /* Long Multiply Parser
7230 UMULL RdLo, RdHi, Rm, Rs
7231 SMULL RdLo, RdHi, Rm, Rs
7232 UMLAL RdLo, RdHi, Rm, Rs
7233 SMLAL RdLo, RdHi, Rm, Rs. */
7238 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7239 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7240 inst
.instruction
|= inst
.operands
[2].reg
;
7241 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7243 /* rdhi and rdlo must be different. */
7244 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7245 as_tsktsk (_("rdhi and rdlo must be different"));
7247 /* rdhi, rdlo and rm must all be different before armv6. */
7248 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7249 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7250 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7251 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7257 if (inst
.operands
[0].present
)
7259 /* Architectural NOP hints are CPSR sets with no bits selected. */
7260 inst
.instruction
&= 0xf0000000;
7261 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7265 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7266 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7267 Condition defaults to COND_ALWAYS.
7268 Error if Rd, Rn or Rm are R15. */
7273 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7274 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7275 inst
.instruction
|= inst
.operands
[2].reg
;
7276 if (inst
.operands
[3].present
)
7277 encode_arm_shift (3);
7280 /* ARM V6 PKHTB (Argument Parse). */
7285 if (!inst
.operands
[3].present
)
7287 /* If the shift specifier is omitted, turn the instruction
7288 into pkhbt rd, rm, rn. */
7289 inst
.instruction
&= 0xfff00010;
7290 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7291 inst
.instruction
|= inst
.operands
[1].reg
;
7292 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7296 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7297 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7298 inst
.instruction
|= inst
.operands
[2].reg
;
7299 encode_arm_shift (3);
7303 /* ARMv5TE: Preload-Cache
7307 Syntactically, like LDR with B=1, W=0, L=1. */
7312 constraint (!inst
.operands
[0].isreg
,
7313 _("'[' expected after PLD mnemonic"));
7314 constraint (inst
.operands
[0].postind
,
7315 _("post-indexed expression used in preload instruction"));
7316 constraint (inst
.operands
[0].writeback
,
7317 _("writeback used in preload instruction"));
7318 constraint (!inst
.operands
[0].preind
,
7319 _("unindexed addressing used in preload instruction"));
7320 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7323 /* ARMv7: PLI <addr_mode> */
7327 constraint (!inst
.operands
[0].isreg
,
7328 _("'[' expected after PLI mnemonic"));
7329 constraint (inst
.operands
[0].postind
,
7330 _("post-indexed expression used in preload instruction"));
7331 constraint (inst
.operands
[0].writeback
,
7332 _("writeback used in preload instruction"));
7333 constraint (!inst
.operands
[0].preind
,
7334 _("unindexed addressing used in preload instruction"));
7335 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7336 inst
.instruction
&= ~PRE_INDEX
;
7342 inst
.operands
[1] = inst
.operands
[0];
7343 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7344 inst
.operands
[0].isreg
= 1;
7345 inst
.operands
[0].writeback
= 1;
7346 inst
.operands
[0].reg
= REG_SP
;
7350 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7351 word at the specified address and the following word
7353 Unconditionally executed.
7354 Error if Rn is R15. */
7359 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7360 if (inst
.operands
[0].writeback
)
7361 inst
.instruction
|= WRITE_BACK
;
7364 /* ARM V6 ssat (argument parse). */
7369 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7370 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7371 inst
.instruction
|= inst
.operands
[2].reg
;
7373 if (inst
.operands
[3].present
)
7374 encode_arm_shift (3);
7377 /* ARM V6 usat (argument parse). */
7382 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7383 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7384 inst
.instruction
|= inst
.operands
[2].reg
;
7386 if (inst
.operands
[3].present
)
7387 encode_arm_shift (3);
7390 /* ARM V6 ssat16 (argument parse). */
7395 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7396 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7397 inst
.instruction
|= inst
.operands
[2].reg
;
7403 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7404 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7405 inst
.instruction
|= inst
.operands
[2].reg
;
7408 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7409 preserving the other bits.
7411 setend <endian_specifier>, where <endian_specifier> is either
7417 if (inst
.operands
[0].imm
)
7418 inst
.instruction
|= 0x200;
7424 unsigned int Rm
= (inst
.operands
[1].present
7425 ? inst
.operands
[1].reg
7426 : inst
.operands
[0].reg
);
7428 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7429 inst
.instruction
|= Rm
;
7430 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7432 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7433 inst
.instruction
|= SHIFT_BY_REG
;
7436 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7442 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7443 inst
.reloc
.pc_rel
= 0;
7449 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7450 inst
.reloc
.pc_rel
= 0;
7453 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7454 SMLAxy{cond} Rd,Rm,Rs,Rn
7455 SMLAWy{cond} Rd,Rm,Rs,Rn
7456 Error if any register is R15. */
7461 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7462 inst
.instruction
|= inst
.operands
[1].reg
;
7463 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7464 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7467 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7468 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7469 Error if any register is R15.
7470 Warning if Rdlo == Rdhi. */
7475 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7476 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7477 inst
.instruction
|= inst
.operands
[2].reg
;
7478 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7480 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7481 as_tsktsk (_("rdhi and rdlo must be different"));
7484 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7485 SMULxy{cond} Rd,Rm,Rs
7486 Error if any register is R15. */
7491 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7492 inst
.instruction
|= inst
.operands
[1].reg
;
7493 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7496 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7497 the same for both ARM and Thumb-2. */
7504 if (inst
.operands
[0].present
)
7506 reg
= inst
.operands
[0].reg
;
7507 constraint (reg
!= 13, _("SRS base register must be r13"));
7512 inst
.instruction
|= reg
<< 16;
7513 inst
.instruction
|= inst
.operands
[1].imm
;
7514 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7515 inst
.instruction
|= WRITE_BACK
;
7518 /* ARM V6 strex (argument parse). */
7523 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7524 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7525 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7526 || inst
.operands
[2].negative
7527 /* See comment in do_ldrex(). */
7528 || (inst
.operands
[2].reg
== REG_PC
),
7531 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7532 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7534 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7535 || inst
.reloc
.exp
.X_add_number
!= 0,
7536 _("offset must be zero in ARM encoding"));
7538 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7539 inst
.instruction
|= inst
.operands
[1].reg
;
7540 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7541 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7547 constraint (inst
.operands
[1].reg
% 2 != 0,
7548 _("even register required"));
7549 constraint (inst
.operands
[2].present
7550 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7551 _("can only store two consecutive registers"));
7552 /* If op 2 were present and equal to PC, this function wouldn't
7553 have been called in the first place. */
7554 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7556 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7557 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7558 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7561 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7562 inst
.instruction
|= inst
.operands
[1].reg
;
7563 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7566 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7567 extends it to 32-bits, and adds the result to a value in another
7568 register. You can specify a rotation by 0, 8, 16, or 24 bits
7569 before extracting the 16-bit value.
7570 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7571 Condition defaults to COND_ALWAYS.
7572 Error if any register uses R15. */
7577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7578 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7579 inst
.instruction
|= inst
.operands
[2].reg
;
7580 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7585 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7586 Condition defaults to COND_ALWAYS.
7587 Error if any register uses R15. */
7592 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7593 inst
.instruction
|= inst
.operands
[1].reg
;
7594 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7597 /* VFP instructions. In a logical order: SP variant first, monad
7598 before dyad, arithmetic then move then load/store. */
7601 do_vfp_sp_monadic (void)
7603 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7604 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7608 do_vfp_sp_dyadic (void)
7610 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7611 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7612 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7616 do_vfp_sp_compare_z (void)
7618 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7622 do_vfp_dp_sp_cvt (void)
7624 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7625 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7629 do_vfp_sp_dp_cvt (void)
7631 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7632 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7636 do_vfp_reg_from_sp (void)
7638 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7639 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7643 do_vfp_reg2_from_sp2 (void)
7645 constraint (inst
.operands
[2].imm
!= 2,
7646 _("only two consecutive VFP SP registers allowed here"));
7647 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7648 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7649 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7653 do_vfp_sp_from_reg (void)
7655 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7656 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7660 do_vfp_sp2_from_reg2 (void)
7662 constraint (inst
.operands
[0].imm
!= 2,
7663 _("only two consecutive VFP SP registers allowed here"));
7664 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7665 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7666 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7670 do_vfp_sp_ldst (void)
7672 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7673 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7677 do_vfp_dp_ldst (void)
7679 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7680 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7685 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7687 if (inst
.operands
[0].writeback
)
7688 inst
.instruction
|= WRITE_BACK
;
7690 constraint (ldstm_type
!= VFP_LDSTMIA
,
7691 _("this addressing mode requires base-register writeback"));
7692 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7693 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7694 inst
.instruction
|= inst
.operands
[1].imm
;
7698 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7702 if (inst
.operands
[0].writeback
)
7703 inst
.instruction
|= WRITE_BACK
;
7705 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7706 _("this addressing mode requires base-register writeback"));
7708 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7709 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7711 count
= inst
.operands
[1].imm
<< 1;
7712 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7715 inst
.instruction
|= count
;
7719 do_vfp_sp_ldstmia (void)
7721 vfp_sp_ldstm (VFP_LDSTMIA
);
7725 do_vfp_sp_ldstmdb (void)
7727 vfp_sp_ldstm (VFP_LDSTMDB
);
7731 do_vfp_dp_ldstmia (void)
7733 vfp_dp_ldstm (VFP_LDSTMIA
);
7737 do_vfp_dp_ldstmdb (void)
7739 vfp_dp_ldstm (VFP_LDSTMDB
);
7743 do_vfp_xp_ldstmia (void)
7745 vfp_dp_ldstm (VFP_LDSTMIAX
);
7749 do_vfp_xp_ldstmdb (void)
7751 vfp_dp_ldstm (VFP_LDSTMDBX
);
7755 do_vfp_dp_rd_rm (void)
7757 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7758 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7762 do_vfp_dp_rn_rd (void)
7764 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7765 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7769 do_vfp_dp_rd_rn (void)
7771 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7772 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7776 do_vfp_dp_rd_rn_rm (void)
7778 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7779 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7780 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7786 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7790 do_vfp_dp_rm_rd_rn (void)
7792 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7793 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7794 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7797 /* VFPv3 instructions. */
7799 do_vfp_sp_const (void)
7801 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7802 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7803 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7807 do_vfp_dp_const (void)
7809 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7810 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7811 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7815 vfp_conv (int srcsize
)
7817 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7818 inst
.instruction
|= (immbits
& 1) << 5;
7819 inst
.instruction
|= (immbits
>> 1);
7823 do_vfp_sp_conv_16 (void)
7825 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7830 do_vfp_dp_conv_16 (void)
7832 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7837 do_vfp_sp_conv_32 (void)
7839 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7844 do_vfp_dp_conv_32 (void)
7846 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7850 /* FPA instructions. Also in a logical order. */
7855 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7856 inst
.instruction
|= inst
.operands
[1].reg
;
7860 do_fpa_ldmstm (void)
7862 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7863 switch (inst
.operands
[1].imm
)
7865 case 1: inst
.instruction
|= CP_T_X
; break;
7866 case 2: inst
.instruction
|= CP_T_Y
; break;
7867 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7872 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7874 /* The instruction specified "ea" or "fd", so we can only accept
7875 [Rn]{!}. The instruction does not really support stacking or
7876 unstacking, so we have to emulate these by setting appropriate
7877 bits and offsets. */
7878 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7879 || inst
.reloc
.exp
.X_add_number
!= 0,
7880 _("this instruction does not support indexing"));
7882 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7883 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7885 if (!(inst
.instruction
& INDEX_UP
))
7886 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7888 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7890 inst
.operands
[2].preind
= 0;
7891 inst
.operands
[2].postind
= 1;
7895 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7898 /* iWMMXt instructions: strictly in alphabetical order. */
7901 do_iwmmxt_tandorc (void)
7903 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7907 do_iwmmxt_textrc (void)
7909 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7910 inst
.instruction
|= inst
.operands
[1].imm
;
7914 do_iwmmxt_textrm (void)
7916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7917 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7918 inst
.instruction
|= inst
.operands
[2].imm
;
7922 do_iwmmxt_tinsr (void)
7924 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7925 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7926 inst
.instruction
|= inst
.operands
[2].imm
;
7930 do_iwmmxt_tmia (void)
7932 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7933 inst
.instruction
|= inst
.operands
[1].reg
;
7934 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7938 do_iwmmxt_waligni (void)
7940 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7941 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7942 inst
.instruction
|= inst
.operands
[2].reg
;
7943 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7947 do_iwmmxt_wmerge (void)
7949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7950 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7951 inst
.instruction
|= inst
.operands
[2].reg
;
7952 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7956 do_iwmmxt_wmov (void)
7958 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7959 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7960 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7961 inst
.instruction
|= inst
.operands
[1].reg
;
7965 do_iwmmxt_wldstbh (void)
7968 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7970 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7972 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7973 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7977 do_iwmmxt_wldstw (void)
7979 /* RIWR_RIWC clears .isreg for a control register. */
7980 if (!inst
.operands
[0].isreg
)
7982 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7983 inst
.instruction
|= 0xf0000000;
7986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7987 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7991 do_iwmmxt_wldstd (void)
7993 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7994 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7995 && inst
.operands
[1].immisreg
)
7997 inst
.instruction
&= ~0x1a000ff;
7998 inst
.instruction
|= (0xf << 28);
7999 if (inst
.operands
[1].preind
)
8000 inst
.instruction
|= PRE_INDEX
;
8001 if (!inst
.operands
[1].negative
)
8002 inst
.instruction
|= INDEX_UP
;
8003 if (inst
.operands
[1].writeback
)
8004 inst
.instruction
|= WRITE_BACK
;
8005 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8006 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8007 inst
.instruction
|= inst
.operands
[1].imm
;
8010 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8014 do_iwmmxt_wshufh (void)
8016 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8017 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8018 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8019 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8023 do_iwmmxt_wzero (void)
8025 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8026 inst
.instruction
|= inst
.operands
[0].reg
;
8027 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8028 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8032 do_iwmmxt_wrwrwr_or_imm5 (void)
8034 if (inst
.operands
[2].isreg
)
8037 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8038 _("immediate operand requires iWMMXt2"));
8040 if (inst
.operands
[2].imm
== 0)
8042 switch ((inst
.instruction
>> 20) & 0xf)
8048 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8049 inst
.operands
[2].imm
= 16;
8050 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8056 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8057 inst
.operands
[2].imm
= 32;
8058 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8065 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8067 wrn
= (inst
.instruction
>> 16) & 0xf;
8068 inst
.instruction
&= 0xff0fff0f;
8069 inst
.instruction
|= wrn
;
8070 /* Bail out here; the instruction is now assembled. */
8075 /* Map 32 -> 0, etc. */
8076 inst
.operands
[2].imm
&= 0x1f;
8077 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8081 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8082 operations first, then control, shift, and load/store. */
8084 /* Insns like "foo X,Y,Z". */
8087 do_mav_triple (void)
8089 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8090 inst
.instruction
|= inst
.operands
[1].reg
;
8091 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8094 /* Insns like "foo W,X,Y,Z".
8095 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8100 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8101 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8102 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8103 inst
.instruction
|= inst
.operands
[3].reg
;
8106 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8110 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8113 /* Maverick shift immediate instructions.
8114 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8115 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8120 int imm
= inst
.operands
[2].imm
;
8122 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8123 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8125 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8126 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8127 Bit 4 should be 0. */
8128 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8130 inst
.instruction
|= imm
;
8133 /* XScale instructions. Also sorted arithmetic before move. */
8135 /* Xscale multiply-accumulate (argument parse)
8138 MIAxycc acc0,Rm,Rs. */
8143 inst
.instruction
|= inst
.operands
[1].reg
;
8144 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8147 /* Xscale move-accumulator-register (argument parse)
8149 MARcc acc0,RdLo,RdHi. */
8154 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8155 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8158 /* Xscale move-register-accumulator (argument parse)
8160 MRAcc RdLo,RdHi,acc0. */
8165 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8166 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8167 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8170 /* Encoding functions relevant only to Thumb. */
8172 /* inst.operands[i] is a shifted-register operand; encode
8173 it into inst.instruction in the format used by Thumb32. */
8176 encode_thumb32_shifted_operand (int i
)
8178 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8179 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8181 constraint (inst
.operands
[i
].immisreg
,
8182 _("shift by register not allowed in thumb mode"));
8183 inst
.instruction
|= inst
.operands
[i
].reg
;
8184 if (shift
== SHIFT_RRX
)
8185 inst
.instruction
|= SHIFT_ROR
<< 4;
8188 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8189 _("expression too complex"));
8191 constraint (value
> 32
8192 || (value
== 32 && (shift
== SHIFT_LSL
8193 || shift
== SHIFT_ROR
)),
8194 _("shift expression is too large"));
8198 else if (value
== 32)
8201 inst
.instruction
|= shift
<< 4;
8202 inst
.instruction
|= (value
& 0x1c) << 10;
8203 inst
.instruction
|= (value
& 0x03) << 6;
8208 /* inst.operands[i] was set up by parse_address. Encode it into a
8209 Thumb32 format load or store instruction. Reject forms that cannot
8210 be used with such instructions. If is_t is true, reject forms that
8211 cannot be used with a T instruction; if is_d is true, reject forms
8212 that cannot be used with a D instruction. */
8215 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8217 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8219 constraint (!inst
.operands
[i
].isreg
,
8220 _("Instruction does not support =N addresses"));
8222 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8223 if (inst
.operands
[i
].immisreg
)
8225 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8226 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8227 constraint (inst
.operands
[i
].negative
,
8228 _("Thumb does not support negative register indexing"));
8229 constraint (inst
.operands
[i
].postind
,
8230 _("Thumb does not support register post-indexing"));
8231 constraint (inst
.operands
[i
].writeback
,
8232 _("Thumb does not support register indexing with writeback"));
8233 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8234 _("Thumb supports only LSL in shifted register indexing"));
8236 inst
.instruction
|= inst
.operands
[i
].imm
;
8237 if (inst
.operands
[i
].shifted
)
8239 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8240 _("expression too complex"));
8241 constraint (inst
.reloc
.exp
.X_add_number
< 0
8242 || inst
.reloc
.exp
.X_add_number
> 3,
8243 _("shift out of range"));
8244 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8246 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8248 else if (inst
.operands
[i
].preind
)
8250 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8251 _("cannot use writeback with PC-relative addressing"));
8252 constraint (is_t
&& inst
.operands
[i
].writeback
,
8253 _("cannot use writeback with this instruction"));
8257 inst
.instruction
|= 0x01000000;
8258 if (inst
.operands
[i
].writeback
)
8259 inst
.instruction
|= 0x00200000;
8263 inst
.instruction
|= 0x00000c00;
8264 if (inst
.operands
[i
].writeback
)
8265 inst
.instruction
|= 0x00000100;
8267 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8269 else if (inst
.operands
[i
].postind
)
8271 assert (inst
.operands
[i
].writeback
);
8272 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8273 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8276 inst
.instruction
|= 0x00200000;
8278 inst
.instruction
|= 0x00000900;
8279 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8281 else /* unindexed - only for coprocessor */
8282 inst
.error
= _("instruction does not accept unindexed addressing");
8285 /* Table of Thumb instructions which exist in both 16- and 32-bit
8286 encodings (the latter only in post-V6T2 cores). The index is the
8287 value used in the insns table below. When there is more than one
8288 possible 16-bit encoding for the instruction, this table always
8290 Also contains several pseudo-instructions used during relaxation. */
8291 #define T16_32_TAB \
8292 X(adc, 4140, eb400000), \
8293 X(adcs, 4140, eb500000), \
8294 X(add, 1c00, eb000000), \
8295 X(adds, 1c00, eb100000), \
8296 X(addi, 0000, f1000000), \
8297 X(addis, 0000, f1100000), \
8298 X(add_pc,000f, f20f0000), \
8299 X(add_sp,000d, f10d0000), \
8300 X(adr, 000f, f20f0000), \
8301 X(and, 4000, ea000000), \
8302 X(ands, 4000, ea100000), \
8303 X(asr, 1000, fa40f000), \
8304 X(asrs, 1000, fa50f000), \
8305 X(b, e000, f000b000), \
8306 X(bcond, d000, f0008000), \
8307 X(bic, 4380, ea200000), \
8308 X(bics, 4380, ea300000), \
8309 X(cmn, 42c0, eb100f00), \
8310 X(cmp, 2800, ebb00f00), \
8311 X(cpsie, b660, f3af8400), \
8312 X(cpsid, b670, f3af8600), \
8313 X(cpy, 4600, ea4f0000), \
8314 X(dec_sp,80dd, f1ad0d00), \
8315 X(eor, 4040, ea800000), \
8316 X(eors, 4040, ea900000), \
8317 X(inc_sp,00dd, f10d0d00), \
8318 X(ldmia, c800, e8900000), \
8319 X(ldr, 6800, f8500000), \
8320 X(ldrb, 7800, f8100000), \
8321 X(ldrh, 8800, f8300000), \
8322 X(ldrsb, 5600, f9100000), \
8323 X(ldrsh, 5e00, f9300000), \
8324 X(ldr_pc,4800, f85f0000), \
8325 X(ldr_pc2,4800, f85f0000), \
8326 X(ldr_sp,9800, f85d0000), \
8327 X(lsl, 0000, fa00f000), \
8328 X(lsls, 0000, fa10f000), \
8329 X(lsr, 0800, fa20f000), \
8330 X(lsrs, 0800, fa30f000), \
8331 X(mov, 2000, ea4f0000), \
8332 X(movs, 2000, ea5f0000), \
8333 X(mul, 4340, fb00f000), \
8334 X(muls, 4340, ffffffff), /* no 32b muls */ \
8335 X(mvn, 43c0, ea6f0000), \
8336 X(mvns, 43c0, ea7f0000), \
8337 X(neg, 4240, f1c00000), /* rsb #0 */ \
8338 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8339 X(orr, 4300, ea400000), \
8340 X(orrs, 4300, ea500000), \
8341 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8342 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8343 X(rev, ba00, fa90f080), \
8344 X(rev16, ba40, fa90f090), \
8345 X(revsh, bac0, fa90f0b0), \
8346 X(ror, 41c0, fa60f000), \
8347 X(rors, 41c0, fa70f000), \
8348 X(sbc, 4180, eb600000), \
8349 X(sbcs, 4180, eb700000), \
8350 X(stmia, c000, e8800000), \
8351 X(str, 6000, f8400000), \
8352 X(strb, 7000, f8000000), \
8353 X(strh, 8000, f8200000), \
8354 X(str_sp,9000, f84d0000), \
8355 X(sub, 1e00, eba00000), \
8356 X(subs, 1e00, ebb00000), \
8357 X(subi, 8000, f1a00000), \
8358 X(subis, 8000, f1b00000), \
8359 X(sxtb, b240, fa4ff080), \
8360 X(sxth, b200, fa0ff080), \
8361 X(tst, 4200, ea100f00), \
8362 X(uxtb, b2c0, fa5ff080), \
8363 X(uxth, b280, fa1ff080), \
8364 X(nop, bf00, f3af8000), \
8365 X(yield, bf10, f3af8001), \
8366 X(wfe, bf20, f3af8002), \
8367 X(wfi, bf30, f3af8003), \
8368 X(sev, bf40, f3af9004), /* typo, 8004? */
8370 /* To catch errors in encoding functions, the codes are all offset by
8371 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8372 as 16-bit instructions. */
8373 #define X(a,b,c) T_MNEM_##a
8374 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8377 #define X(a,b,c) 0x##b
8378 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8379 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8382 #define X(a,b,c) 0x##c
8383 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8384 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8385 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8389 /* Thumb instruction encoders, in alphabetical order. */
8393 do_t_add_sub_w (void)
8397 Rd
= inst
.operands
[0].reg
;
8398 Rn
= inst
.operands
[1].reg
;
8400 constraint (Rd
== 15, _("PC not allowed as destination"));
8401 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8402 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8405 /* Parse an add or subtract instruction. We get here with inst.instruction
8406 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8413 Rd
= inst
.operands
[0].reg
;
8414 Rs
= (inst
.operands
[1].present
8415 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8416 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8424 flags
= (inst
.instruction
== T_MNEM_adds
8425 || inst
.instruction
== T_MNEM_subs
);
8427 narrow
= (current_it_mask
== 0);
8429 narrow
= (current_it_mask
!= 0);
8430 if (!inst
.operands
[2].isreg
)
8434 add
= (inst
.instruction
== T_MNEM_add
8435 || inst
.instruction
== T_MNEM_adds
);
8437 if (inst
.size_req
!= 4)
8439 /* Attempt to use a narrow opcode, with relaxation if
8441 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8442 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8443 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8444 opcode
= T_MNEM_add_sp
;
8445 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8446 opcode
= T_MNEM_add_pc
;
8447 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8450 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8452 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8456 inst
.instruction
= THUMB_OP16(opcode
);
8457 inst
.instruction
|= (Rd
<< 4) | Rs
;
8458 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8459 if (inst
.size_req
!= 2)
8460 inst
.relax
= opcode
;
8463 constraint (inst
.size_req
== 2, BAD_HIREG
);
8465 if (inst
.size_req
== 4
8466 || (inst
.size_req
!= 2 && !opcode
))
8470 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8471 _("only SUBS PC, LR, #const allowed"));
8472 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8473 _("expression too complex"));
8474 constraint (inst
.reloc
.exp
.X_add_number
< 0
8475 || inst
.reloc
.exp
.X_add_number
> 0xff,
8476 _("immediate value out of range"));
8477 inst
.instruction
= T2_SUBS_PC_LR
8478 | inst
.reloc
.exp
.X_add_number
;
8479 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8482 else if (Rs
== REG_PC
)
8484 /* Always use addw/subw. */
8485 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8486 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8490 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8491 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8494 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8496 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8498 inst
.instruction
|= Rd
<< 8;
8499 inst
.instruction
|= Rs
<< 16;
8504 Rn
= inst
.operands
[2].reg
;
8505 /* See if we can do this with a 16-bit instruction. */
8506 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8508 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8513 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8514 || inst
.instruction
== T_MNEM_add
)
8517 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8521 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8523 /* Thumb-1 cores (except v6-M) require at least one high
8524 register in a narrow non flag setting add. */
8525 if (Rd
> 7 || Rn
> 7
8526 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8527 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8534 inst
.instruction
= T_OPCODE_ADD_HI
;
8535 inst
.instruction
|= (Rd
& 8) << 4;
8536 inst
.instruction
|= (Rd
& 7);
8537 inst
.instruction
|= Rn
<< 3;
8542 /* If we get here, it can't be done in 16 bits. */
8543 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8544 _("shift must be constant"));
8545 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8546 inst
.instruction
|= Rd
<< 8;
8547 inst
.instruction
|= Rs
<< 16;
8548 encode_thumb32_shifted_operand (2);
8553 constraint (inst
.instruction
== T_MNEM_adds
8554 || inst
.instruction
== T_MNEM_subs
,
8557 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8559 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8560 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8563 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8565 inst
.instruction
|= (Rd
<< 4) | Rs
;
8566 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8570 Rn
= inst
.operands
[2].reg
;
8571 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8573 /* We now have Rd, Rs, and Rn set to registers. */
8574 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8576 /* Can't do this for SUB. */
8577 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8578 inst
.instruction
= T_OPCODE_ADD_HI
;
8579 inst
.instruction
|= (Rd
& 8) << 4;
8580 inst
.instruction
|= (Rd
& 7);
8582 inst
.instruction
|= Rn
<< 3;
8584 inst
.instruction
|= Rs
<< 3;
8586 constraint (1, _("dest must overlap one source register"));
8590 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8591 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8592 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8600 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8602 /* Defer to section relaxation. */
8603 inst
.relax
= inst
.instruction
;
8604 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8605 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8607 else if (unified_syntax
&& inst
.size_req
!= 2)
8609 /* Generate a 32-bit opcode. */
8610 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8611 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8612 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8613 inst
.reloc
.pc_rel
= 1;
8617 /* Generate a 16-bit opcode. */
8618 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8619 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8620 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8621 inst
.reloc
.pc_rel
= 1;
8623 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8627 /* Arithmetic instructions for which there is just one 16-bit
8628 instruction encoding, and it allows only two low registers.
8629 For maximal compatibility with ARM syntax, we allow three register
8630 operands even when Thumb-32 instructions are not available, as long
8631 as the first two are identical. For instance, both "sbc r0,r1" and
8632 "sbc r0,r0,r1" are allowed. */
8638 Rd
= inst
.operands
[0].reg
;
8639 Rs
= (inst
.operands
[1].present
8640 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8641 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8642 Rn
= inst
.operands
[2].reg
;
8646 if (!inst
.operands
[2].isreg
)
8648 /* For an immediate, we always generate a 32-bit opcode;
8649 section relaxation will shrink it later if possible. */
8650 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8651 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8652 inst
.instruction
|= Rd
<< 8;
8653 inst
.instruction
|= Rs
<< 16;
8654 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8660 /* See if we can do this with a 16-bit instruction. */
8661 if (THUMB_SETS_FLAGS (inst
.instruction
))
8662 narrow
= current_it_mask
== 0;
8664 narrow
= current_it_mask
!= 0;
8666 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8668 if (inst
.operands
[2].shifted
)
8670 if (inst
.size_req
== 4)
8676 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8677 inst
.instruction
|= Rd
;
8678 inst
.instruction
|= Rn
<< 3;
8682 /* If we get here, it can't be done in 16 bits. */
8683 constraint (inst
.operands
[2].shifted
8684 && inst
.operands
[2].immisreg
,
8685 _("shift must be constant"));
8686 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8687 inst
.instruction
|= Rd
<< 8;
8688 inst
.instruction
|= Rs
<< 16;
8689 encode_thumb32_shifted_operand (2);
8694 /* On its face this is a lie - the instruction does set the
8695 flags. However, the only supported mnemonic in this mode
8697 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8699 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8700 _("unshifted register required"));
8701 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8702 constraint (Rd
!= Rs
,
8703 _("dest and source1 must be the same register"));
8705 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8706 inst
.instruction
|= Rd
;
8707 inst
.instruction
|= Rn
<< 3;
8711 /* Similarly, but for instructions where the arithmetic operation is
8712 commutative, so we can allow either of them to be different from
8713 the destination operand in a 16-bit instruction. For instance, all
8714 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8721 Rd
= inst
.operands
[0].reg
;
8722 Rs
= (inst
.operands
[1].present
8723 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8724 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8725 Rn
= inst
.operands
[2].reg
;
8729 if (!inst
.operands
[2].isreg
)
8731 /* For an immediate, we always generate a 32-bit opcode;
8732 section relaxation will shrink it later if possible. */
8733 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8734 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8735 inst
.instruction
|= Rd
<< 8;
8736 inst
.instruction
|= Rs
<< 16;
8737 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8743 /* See if we can do this with a 16-bit instruction. */
8744 if (THUMB_SETS_FLAGS (inst
.instruction
))
8745 narrow
= current_it_mask
== 0;
8747 narrow
= current_it_mask
!= 0;
8749 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8751 if (inst
.operands
[2].shifted
)
8753 if (inst
.size_req
== 4)
8760 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8761 inst
.instruction
|= Rd
;
8762 inst
.instruction
|= Rn
<< 3;
8767 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8768 inst
.instruction
|= Rd
;
8769 inst
.instruction
|= Rs
<< 3;
8774 /* If we get here, it can't be done in 16 bits. */
8775 constraint (inst
.operands
[2].shifted
8776 && inst
.operands
[2].immisreg
,
8777 _("shift must be constant"));
8778 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8779 inst
.instruction
|= Rd
<< 8;
8780 inst
.instruction
|= Rs
<< 16;
8781 encode_thumb32_shifted_operand (2);
8786 /* On its face this is a lie - the instruction does set the
8787 flags. However, the only supported mnemonic in this mode
8789 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8791 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8792 _("unshifted register required"));
8793 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8795 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8796 inst
.instruction
|= Rd
;
8799 inst
.instruction
|= Rn
<< 3;
8801 inst
.instruction
|= Rs
<< 3;
8803 constraint (1, _("dest must overlap one source register"));
8810 if (inst
.operands
[0].present
)
8812 constraint ((inst
.instruction
& 0xf0) != 0x40
8813 && inst
.operands
[0].imm
!= 0xf,
8814 _("bad barrier type"));
8815 inst
.instruction
|= inst
.operands
[0].imm
;
8818 inst
.instruction
|= 0xf;
8824 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8825 constraint (msb
> 32, _("bit-field extends past end of register"));
8826 /* The instruction encoding stores the LSB and MSB,
8827 not the LSB and width. */
8828 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8829 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8830 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8831 inst
.instruction
|= msb
- 1;
8839 /* #0 in second position is alternative syntax for bfc, which is
8840 the same instruction but with REG_PC in the Rm field. */
8841 if (!inst
.operands
[1].isreg
)
8842 inst
.operands
[1].reg
= REG_PC
;
8844 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8845 constraint (msb
> 32, _("bit-field extends past end of register"));
8846 /* The instruction encoding stores the LSB and MSB,
8847 not the LSB and width. */
8848 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8849 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8850 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8851 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8852 inst
.instruction
|= msb
- 1;
8858 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8859 _("bit-field extends past end of register"));
8860 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8861 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8862 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8863 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8864 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8867 /* ARM V5 Thumb BLX (argument parse)
8868 BLX <target_addr> which is BLX(1)
8869 BLX <Rm> which is BLX(2)
8870 Unfortunately, there are two different opcodes for this mnemonic.
8871 So, the insns[].value is not used, and the code here zaps values
8872 into inst.instruction.
8874 ??? How to take advantage of the additional two bits of displacement
8875 available in Thumb32 mode? Need new relocation? */
8880 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8881 if (inst
.operands
[0].isreg
)
8882 /* We have a register, so this is BLX(2). */
8883 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8886 /* No register. This must be BLX(1). */
8887 inst
.instruction
= 0xf000e800;
8889 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8890 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8893 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8894 inst
.reloc
.pc_rel
= 1;
8904 if (current_it_mask
)
8906 /* Conditional branches inside IT blocks are encoded as unconditional
8909 /* A branch must be the last instruction in an IT block. */
8910 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8915 if (cond
!= COND_ALWAYS
)
8916 opcode
= T_MNEM_bcond
;
8918 opcode
= inst
.instruction
;
8920 if (unified_syntax
&& inst
.size_req
== 4)
8922 inst
.instruction
= THUMB_OP32(opcode
);
8923 if (cond
== COND_ALWAYS
)
8924 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8927 assert (cond
!= 0xF);
8928 inst
.instruction
|= cond
<< 22;
8929 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8934 inst
.instruction
= THUMB_OP16(opcode
);
8935 if (cond
== COND_ALWAYS
)
8936 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8939 inst
.instruction
|= cond
<< 8;
8940 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8942 /* Allow section relaxation. */
8943 if (unified_syntax
&& inst
.size_req
!= 2)
8944 inst
.relax
= opcode
;
8947 inst
.reloc
.pc_rel
= 1;
8953 constraint (inst
.cond
!= COND_ALWAYS
,
8954 _("instruction is always unconditional"));
8955 if (inst
.operands
[0].present
)
8957 constraint (inst
.operands
[0].imm
> 255,
8958 _("immediate value out of range"));
8959 inst
.instruction
|= inst
.operands
[0].imm
;
8964 do_t_branch23 (void)
8966 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8967 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8968 inst
.reloc
.pc_rel
= 1;
8970 /* If the destination of the branch is a defined symbol which does not have
8971 the THUMB_FUNC attribute, then we must be calling a function which has
8972 the (interfacearm) attribute. We look for the Thumb entry point to that
8973 function and change the branch to refer to that function instead. */
8974 if ( inst
.reloc
.exp
.X_op
== O_symbol
8975 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8976 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8977 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8978 inst
.reloc
.exp
.X_add_symbol
=
8979 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8985 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8986 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8987 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8988 should cause the alignment to be checked once it is known. This is
8989 because BX PC only works if the instruction is word aligned. */
8995 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8996 if (inst
.operands
[0].reg
== REG_PC
)
8997 as_tsktsk (_("use of r15 in bxj is not really useful"));
8999 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9005 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9006 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9007 inst
.instruction
|= inst
.operands
[1].reg
;
9013 constraint (current_it_mask
, BAD_NOT_IT
);
9014 inst
.instruction
|= inst
.operands
[0].imm
;
9020 constraint (current_it_mask
, BAD_NOT_IT
);
9022 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9023 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9025 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9026 inst
.instruction
= 0xf3af8000;
9027 inst
.instruction
|= imod
<< 9;
9028 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9029 if (inst
.operands
[1].present
)
9030 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9034 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9035 && (inst
.operands
[0].imm
& 4),
9036 _("selected processor does not support 'A' form "
9037 "of this instruction"));
9038 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9039 _("Thumb does not support the 2-argument "
9040 "form of this instruction"));
9041 inst
.instruction
|= inst
.operands
[0].imm
;
9045 /* THUMB CPY instruction (argument parse). */
9050 if (inst
.size_req
== 4)
9052 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9053 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9054 inst
.instruction
|= inst
.operands
[1].reg
;
9058 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9059 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9060 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9067 constraint (current_it_mask
, BAD_NOT_IT
);
9068 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9069 inst
.instruction
|= inst
.operands
[0].reg
;
9070 inst
.reloc
.pc_rel
= 1;
9071 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9077 inst
.instruction
|= inst
.operands
[0].imm
;
9083 if (!inst
.operands
[1].present
)
9084 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9085 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9086 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9087 inst
.instruction
|= inst
.operands
[2].reg
;
9093 if (unified_syntax
&& inst
.size_req
== 4)
9094 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9096 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9102 unsigned int cond
= inst
.operands
[0].imm
;
9104 constraint (current_it_mask
, BAD_NOT_IT
);
9105 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9108 /* If the condition is a negative condition, invert the mask. */
9109 if ((cond
& 0x1) == 0x0)
9111 unsigned int mask
= inst
.instruction
& 0x000f;
9113 if ((mask
& 0x7) == 0)
9114 /* no conversion needed */;
9115 else if ((mask
& 0x3) == 0)
9117 else if ((mask
& 0x1) == 0)
9122 inst
.instruction
&= 0xfff0;
9123 inst
.instruction
|= mask
;
9126 inst
.instruction
|= cond
<< 4;
9129 /* Helper function used for both push/pop and ldm/stm. */
9131 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9135 load
= (inst
.instruction
& (1 << 20)) != 0;
9137 if (mask
& (1 << 13))
9138 inst
.error
= _("SP not allowed in register list");
9141 if (mask
& (1 << 14)
9142 && mask
& (1 << 15))
9143 inst
.error
= _("LR and PC should not both be in register list");
9145 if ((mask
& (1 << base
)) != 0
9147 as_warn (_("base register should not be in register list "
9148 "when written back"));
9152 if (mask
& (1 << 15))
9153 inst
.error
= _("PC not allowed in register list");
9155 if (mask
& (1 << base
))
9156 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9159 if ((mask
& (mask
- 1)) == 0)
9161 /* Single register transfers implemented as str/ldr. */
9164 if (inst
.instruction
& (1 << 23))
9165 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9167 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9171 if (inst
.instruction
& (1 << 23))
9172 inst
.instruction
= 0x00800000; /* ia -> [base] */
9174 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9177 inst
.instruction
|= 0xf8400000;
9179 inst
.instruction
|= 0x00100000;
9181 mask
= ffs (mask
) - 1;
9185 inst
.instruction
|= WRITE_BACK
;
9187 inst
.instruction
|= mask
;
9188 inst
.instruction
|= base
<< 16;
9194 /* This really doesn't seem worth it. */
9195 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9196 _("expression too complex"));
9197 constraint (inst
.operands
[1].writeback
,
9198 _("Thumb load/store multiple does not support {reglist}^"));
9206 /* See if we can use a 16-bit instruction. */
9207 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9208 && inst
.size_req
!= 4
9209 && !(inst
.operands
[1].imm
& ~0xff))
9211 mask
= 1 << inst
.operands
[0].reg
;
9213 if (inst
.operands
[0].reg
<= 7
9214 && (inst
.instruction
== T_MNEM_stmia
9215 ? inst
.operands
[0].writeback
9216 : (inst
.operands
[0].writeback
9217 == !(inst
.operands
[1].imm
& mask
))))
9219 if (inst
.instruction
== T_MNEM_stmia
9220 && (inst
.operands
[1].imm
& mask
)
9221 && (inst
.operands
[1].imm
& (mask
- 1)))
9222 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9223 inst
.operands
[0].reg
);
9225 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9226 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9227 inst
.instruction
|= inst
.operands
[1].imm
;
9230 else if (inst
.operands
[0] .reg
== REG_SP
9231 && inst
.operands
[0].writeback
)
9233 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9234 ? T_MNEM_push
: T_MNEM_pop
);
9235 inst
.instruction
|= inst
.operands
[1].imm
;
9242 if (inst
.instruction
< 0xffff)
9243 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9245 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9246 inst
.operands
[0].writeback
);
9251 constraint (inst
.operands
[0].reg
> 7
9252 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9253 constraint (inst
.instruction
!= T_MNEM_ldmia
9254 && inst
.instruction
!= T_MNEM_stmia
,
9255 _("Thumb-2 instruction only valid in unified syntax"));
9256 if (inst
.instruction
== T_MNEM_stmia
)
9258 if (!inst
.operands
[0].writeback
)
9259 as_warn (_("this instruction will write back the base register"));
9260 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9261 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9262 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9263 inst
.operands
[0].reg
);
9267 if (!inst
.operands
[0].writeback
9268 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9269 as_warn (_("this instruction will write back the base register"));
9270 else if (inst
.operands
[0].writeback
9271 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9272 as_warn (_("this instruction will not write back the base register"));
9275 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9276 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9277 inst
.instruction
|= inst
.operands
[1].imm
;
9284 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9285 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9286 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9287 || inst
.operands
[1].negative
,
9290 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9291 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9292 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9298 if (!inst
.operands
[1].present
)
9300 constraint (inst
.operands
[0].reg
== REG_LR
,
9301 _("r14 not allowed as first register "
9302 "when second register is omitted"));
9303 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9305 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9308 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9309 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9310 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9316 unsigned long opcode
;
9319 opcode
= inst
.instruction
;
9322 if (!inst
.operands
[1].isreg
)
9324 if (opcode
<= 0xffff)
9325 inst
.instruction
= THUMB_OP32 (opcode
);
9326 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9329 if (inst
.operands
[1].isreg
9330 && !inst
.operands
[1].writeback
9331 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9332 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9334 && inst
.size_req
!= 4)
9336 /* Insn may have a 16-bit form. */
9337 Rn
= inst
.operands
[1].reg
;
9338 if (inst
.operands
[1].immisreg
)
9340 inst
.instruction
= THUMB_OP16 (opcode
);
9342 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9345 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9346 && opcode
!= T_MNEM_ldrsb
)
9347 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9348 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9355 if (inst
.reloc
.pc_rel
)
9356 opcode
= T_MNEM_ldr_pc2
;
9358 opcode
= T_MNEM_ldr_pc
;
9362 if (opcode
== T_MNEM_ldr
)
9363 opcode
= T_MNEM_ldr_sp
;
9365 opcode
= T_MNEM_str_sp
;
9367 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9371 inst
.instruction
= inst
.operands
[0].reg
;
9372 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9374 inst
.instruction
|= THUMB_OP16 (opcode
);
9375 if (inst
.size_req
== 2)
9376 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9378 inst
.relax
= opcode
;
9382 /* Definitely a 32-bit variant. */
9383 inst
.instruction
= THUMB_OP32 (opcode
);
9384 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9385 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9389 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9391 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9393 /* Only [Rn,Rm] is acceptable. */
9394 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9395 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9396 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9397 || inst
.operands
[1].negative
,
9398 _("Thumb does not support this addressing mode"));
9399 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9403 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9404 if (!inst
.operands
[1].isreg
)
9405 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9408 constraint (!inst
.operands
[1].preind
9409 || inst
.operands
[1].shifted
9410 || inst
.operands
[1].writeback
,
9411 _("Thumb does not support this addressing mode"));
9412 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9414 constraint (inst
.instruction
& 0x0600,
9415 _("byte or halfword not valid for base register"));
9416 constraint (inst
.operands
[1].reg
== REG_PC
9417 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9418 _("r15 based store not allowed"));
9419 constraint (inst
.operands
[1].immisreg
,
9420 _("invalid base register for register offset"));
9422 if (inst
.operands
[1].reg
== REG_PC
)
9423 inst
.instruction
= T_OPCODE_LDR_PC
;
9424 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9425 inst
.instruction
= T_OPCODE_LDR_SP
;
9427 inst
.instruction
= T_OPCODE_STR_SP
;
9429 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9430 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9434 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9435 if (!inst
.operands
[1].immisreg
)
9437 /* Immediate offset. */
9438 inst
.instruction
|= inst
.operands
[0].reg
;
9439 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9440 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9444 /* Register offset. */
9445 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9446 constraint (inst
.operands
[1].negative
,
9447 _("Thumb does not support this addressing mode"));
9450 switch (inst
.instruction
)
9452 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9453 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9454 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9455 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9456 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9457 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9458 case 0x5600 /* ldrsb */:
9459 case 0x5e00 /* ldrsh */: break;
9463 inst
.instruction
|= inst
.operands
[0].reg
;
9464 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9465 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9471 if (!inst
.operands
[1].present
)
9473 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9474 constraint (inst
.operands
[0].reg
== REG_LR
,
9475 _("r14 not allowed here"));
9477 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9478 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9479 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9485 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9486 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9492 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9493 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9494 inst
.instruction
|= inst
.operands
[2].reg
;
9495 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9502 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9503 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9504 inst
.instruction
|= inst
.operands
[3].reg
;
9512 int r0off
= (inst
.instruction
== T_MNEM_mov
9513 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9514 unsigned long opcode
;
9516 bfd_boolean low_regs
;
9518 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9519 opcode
= inst
.instruction
;
9520 if (current_it_mask
)
9521 narrow
= opcode
!= T_MNEM_movs
;
9523 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9524 if (inst
.size_req
== 4
9525 || inst
.operands
[1].shifted
)
9528 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9529 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9530 && !inst
.operands
[1].shifted
9531 && inst
.operands
[0].reg
== REG_PC
9532 && inst
.operands
[1].reg
== REG_LR
)
9534 inst
.instruction
= T2_SUBS_PC_LR
;
9538 if (!inst
.operands
[1].isreg
)
9540 /* Immediate operand. */
9541 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9543 if (low_regs
&& narrow
)
9545 inst
.instruction
= THUMB_OP16 (opcode
);
9546 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9547 if (inst
.size_req
== 2)
9548 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9550 inst
.relax
= opcode
;
9554 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9555 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9556 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9557 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9560 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9561 && (inst
.instruction
== T_MNEM_mov
9562 || inst
.instruction
== T_MNEM_movs
))
9564 /* Register shifts are encoded as separate shift instructions. */
9565 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9567 if (current_it_mask
)
9572 if (inst
.size_req
== 4)
9575 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9578 if (inst
.operands
[0].reg
!= inst
.operands
[1].reg
)
9581 switch (inst
.operands
[1].shift_kind
)
9584 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9587 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9590 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9593 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9599 inst
.instruction
= opcode
;
9602 inst
.instruction
|= inst
.operands
[0].reg
;
9603 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9608 inst
.instruction
|= CONDS_BIT
;
9610 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9611 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9612 inst
.instruction
|= inst
.operands
[1].imm
;
9617 /* Some mov with immediate shift have narrow variants.
9618 Register shifts are handled above. */
9619 if (low_regs
&& inst
.operands
[1].shifted
9620 && (inst
.instruction
== T_MNEM_mov
9621 || inst
.instruction
== T_MNEM_movs
))
9623 if (current_it_mask
)
9624 narrow
= (inst
.instruction
== T_MNEM_mov
);
9626 narrow
= (inst
.instruction
== T_MNEM_movs
);
9631 switch (inst
.operands
[1].shift_kind
)
9633 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9634 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9635 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9636 default: narrow
= FALSE
; break;
9642 inst
.instruction
|= inst
.operands
[0].reg
;
9643 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9644 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9648 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9649 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9650 encode_thumb32_shifted_operand (1);
9654 switch (inst
.instruction
)
9657 inst
.instruction
= T_OPCODE_MOV_HR
;
9658 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9659 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9660 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9664 /* We know we have low registers at this point.
9665 Generate ADD Rd, Rs, #0. */
9666 inst
.instruction
= T_OPCODE_ADD_I3
;
9667 inst
.instruction
|= inst
.operands
[0].reg
;
9668 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9674 inst
.instruction
= T_OPCODE_CMP_LR
;
9675 inst
.instruction
|= inst
.operands
[0].reg
;
9676 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9680 inst
.instruction
= T_OPCODE_CMP_HR
;
9681 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9682 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9683 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9690 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9691 if (inst
.operands
[1].isreg
)
9693 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9695 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9696 since a MOV instruction produces unpredictable results. */
9697 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9698 inst
.instruction
= T_OPCODE_ADD_I3
;
9700 inst
.instruction
= T_OPCODE_CMP_LR
;
9702 inst
.instruction
|= inst
.operands
[0].reg
;
9703 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9707 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9708 inst
.instruction
= T_OPCODE_MOV_HR
;
9710 inst
.instruction
= T_OPCODE_CMP_HR
;
9716 constraint (inst
.operands
[0].reg
> 7,
9717 _("only lo regs allowed with immediate"));
9718 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9719 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9729 top
= (inst
.instruction
& 0x00800000) != 0;
9730 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9732 constraint (top
, _(":lower16: not allowed this instruction"));
9733 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9735 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9737 constraint (!top
, _(":upper16: not allowed this instruction"));
9738 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9741 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9742 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9744 imm
= inst
.reloc
.exp
.X_add_number
;
9745 inst
.instruction
|= (imm
& 0xf000) << 4;
9746 inst
.instruction
|= (imm
& 0x0800) << 15;
9747 inst
.instruction
|= (imm
& 0x0700) << 4;
9748 inst
.instruction
|= (imm
& 0x00ff);
9757 int r0off
= (inst
.instruction
== T_MNEM_mvn
9758 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9761 if (inst
.size_req
== 4
9762 || inst
.instruction
> 0xffff
9763 || inst
.operands
[1].shifted
9764 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9766 else if (inst
.instruction
== T_MNEM_cmn
)
9768 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9769 narrow
= (current_it_mask
== 0);
9771 narrow
= (current_it_mask
!= 0);
9773 if (!inst
.operands
[1].isreg
)
9775 /* For an immediate, we always generate a 32-bit opcode;
9776 section relaxation will shrink it later if possible. */
9777 if (inst
.instruction
< 0xffff)
9778 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9779 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9780 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9781 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9785 /* See if we can do this with a 16-bit instruction. */
9788 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9789 inst
.instruction
|= inst
.operands
[0].reg
;
9790 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9794 constraint (inst
.operands
[1].shifted
9795 && inst
.operands
[1].immisreg
,
9796 _("shift must be constant"));
9797 if (inst
.instruction
< 0xffff)
9798 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9799 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9800 encode_thumb32_shifted_operand (1);
9806 constraint (inst
.instruction
> 0xffff
9807 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9808 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9809 _("unshifted register required"));
9810 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9813 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9814 inst
.instruction
|= inst
.operands
[0].reg
;
9815 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9824 if (do_vfp_nsyn_mrs () == SUCCESS
)
9827 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9830 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
9831 _("selected processor does not support "
9832 "requested special purpose register"));
9836 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9837 _("selected processor does not support "
9838 "requested special purpose register"));
9839 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9840 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9841 _("'CPSR' or 'SPSR' expected"));
9844 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9845 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9846 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9854 if (do_vfp_nsyn_msr () == SUCCESS
)
9857 constraint (!inst
.operands
[1].isreg
,
9858 _("Thumb encoding does not support an immediate here"));
9859 flags
= inst
.operands
[0].imm
;
9862 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9863 _("selected processor does not support "
9864 "requested special purpose register"));
9868 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
9869 _("selected processor does not support "
9870 "requested special purpose register"));
9873 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9874 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9875 inst
.instruction
|= (flags
& 0xff);
9876 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9884 if (!inst
.operands
[2].present
)
9885 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9889 if (inst
.size_req
== 4
9890 || (inst
.operands
[0].reg
!= inst
.operands
[1].reg
9891 && inst
.operands
[0].reg
!= inst
.operands
[2].reg
)
9892 || inst
.operands
[1].reg
> 7
9893 || inst
.operands
[2].reg
> 7)
9895 else if (inst
.instruction
== T_MNEM_muls
)
9896 narrow
= (current_it_mask
== 0);
9898 narrow
= (current_it_mask
!= 0);
9902 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9903 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[2].reg
> 7,
9910 /* 16-bit MULS/Conditional MUL. */
9911 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9912 inst
.instruction
|= inst
.operands
[0].reg
;
9914 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9915 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9916 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9917 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9919 constraint (1, _("dest must overlap one source register"));
9923 constraint(inst
.instruction
!= T_MNEM_mul
,
9924 _("Thumb-2 MUL must not set flags"));
9926 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9927 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9928 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9929 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9937 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9938 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9939 inst
.instruction
|= inst
.operands
[3].reg
;
9941 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9942 as_tsktsk (_("rdhi and rdlo must be different"));
9950 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9952 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9953 inst
.instruction
|= inst
.operands
[0].imm
;
9957 /* PR9722: Check for Thumb2 availability before
9958 generating a thumb2 nop instruction. */
9959 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
9961 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9962 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9965 inst
.instruction
= 0x46c0;
9970 constraint (inst
.operands
[0].present
,
9971 _("Thumb does not support NOP with hints"));
9972 inst
.instruction
= 0x46c0;
9983 if (THUMB_SETS_FLAGS (inst
.instruction
))
9984 narrow
= (current_it_mask
== 0);
9986 narrow
= (current_it_mask
!= 0);
9987 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9989 if (inst
.size_req
== 4)
9994 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9995 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9996 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10000 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10001 inst
.instruction
|= inst
.operands
[0].reg
;
10002 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10007 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10009 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10011 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10012 inst
.instruction
|= inst
.operands
[0].reg
;
10013 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10022 Rd
= inst
.operands
[0].reg
;
10023 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10025 inst
.instruction
|= Rd
<< 8;
10026 inst
.instruction
|= Rn
<< 16;
10028 if (!inst
.operands
[2].isreg
)
10030 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10031 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10037 Rm
= inst
.operands
[2].reg
;
10039 constraint (inst
.operands
[2].shifted
10040 && inst
.operands
[2].immisreg
,
10041 _("shift must be constant"));
10042 encode_thumb32_shifted_operand (2);
10049 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10050 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10051 inst
.instruction
|= inst
.operands
[2].reg
;
10052 if (inst
.operands
[3].present
)
10054 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10055 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10056 _("expression too complex"));
10057 inst
.instruction
|= (val
& 0x1c) << 10;
10058 inst
.instruction
|= (val
& 0x03) << 6;
10065 if (!inst
.operands
[3].present
)
10066 inst
.instruction
&= ~0x00000020;
10073 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10077 do_t_push_pop (void)
10081 constraint (inst
.operands
[0].writeback
,
10082 _("push/pop do not support {reglist}^"));
10083 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10084 _("expression too complex"));
10086 mask
= inst
.operands
[0].imm
;
10087 if ((mask
& ~0xff) == 0)
10088 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10089 else if ((inst
.instruction
== T_MNEM_push
10090 && (mask
& ~0xff) == 1 << REG_LR
)
10091 || (inst
.instruction
== T_MNEM_pop
10092 && (mask
& ~0xff) == 1 << REG_PC
))
10094 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10095 inst
.instruction
|= THUMB_PP_PC_LR
;
10096 inst
.instruction
|= mask
& 0xff;
10098 else if (unified_syntax
)
10100 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10101 encode_thumb2_ldmstm (13, mask
, TRUE
);
10105 inst
.error
= _("invalid register list to push/pop instruction");
10113 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10114 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10115 inst
.instruction
|= inst
.operands
[1].reg
;
10121 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10122 && inst
.size_req
!= 4)
10124 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10125 inst
.instruction
|= inst
.operands
[0].reg
;
10126 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10128 else if (unified_syntax
)
10130 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10131 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10132 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10133 inst
.instruction
|= inst
.operands
[1].reg
;
10136 inst
.error
= BAD_HIREG
;
10144 Rd
= inst
.operands
[0].reg
;
10145 Rm
= inst
.operands
[1].reg
;
10147 inst
.instruction
|= Rd
<< 8;
10148 inst
.instruction
|= Rm
;
10156 Rd
= inst
.operands
[0].reg
;
10157 Rs
= (inst
.operands
[1].present
10158 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10159 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10161 inst
.instruction
|= Rd
<< 8;
10162 inst
.instruction
|= Rs
<< 16;
10163 if (!inst
.operands
[2].isreg
)
10165 bfd_boolean narrow
;
10167 if ((inst
.instruction
& 0x00100000) != 0)
10168 narrow
= (current_it_mask
== 0);
10170 narrow
= (current_it_mask
!= 0);
10172 if (Rd
> 7 || Rs
> 7)
10175 if (inst
.size_req
== 4 || !unified_syntax
)
10178 if (inst
.reloc
.exp
.X_op
!= O_constant
10179 || inst
.reloc
.exp
.X_add_number
!= 0)
10182 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10183 relaxation, but it doesn't seem worth the hassle. */
10186 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10187 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10188 inst
.instruction
|= Rs
<< 3;
10189 inst
.instruction
|= Rd
;
10193 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10194 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10198 encode_thumb32_shifted_operand (2);
10204 constraint (current_it_mask
, BAD_NOT_IT
);
10205 if (inst
.operands
[0].imm
)
10206 inst
.instruction
|= 0x8;
10212 if (!inst
.operands
[1].present
)
10213 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10215 if (unified_syntax
)
10217 bfd_boolean narrow
;
10220 switch (inst
.instruction
)
10223 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10225 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10227 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10229 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10233 if (THUMB_SETS_FLAGS (inst
.instruction
))
10234 narrow
= (current_it_mask
== 0);
10236 narrow
= (current_it_mask
!= 0);
10237 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10239 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10241 if (inst
.operands
[2].isreg
10242 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10243 || inst
.operands
[2].reg
> 7))
10245 if (inst
.size_req
== 4)
10250 if (inst
.operands
[2].isreg
)
10252 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10253 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10254 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10255 inst
.instruction
|= inst
.operands
[2].reg
;
10259 inst
.operands
[1].shifted
= 1;
10260 inst
.operands
[1].shift_kind
= shift_kind
;
10261 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10262 ? T_MNEM_movs
: T_MNEM_mov
);
10263 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10264 encode_thumb32_shifted_operand (1);
10265 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10266 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10271 if (inst
.operands
[2].isreg
)
10273 switch (shift_kind
)
10275 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10276 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10277 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10278 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10282 inst
.instruction
|= inst
.operands
[0].reg
;
10283 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10287 switch (shift_kind
)
10289 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10290 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10291 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10294 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10295 inst
.instruction
|= inst
.operands
[0].reg
;
10296 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10302 constraint (inst
.operands
[0].reg
> 7
10303 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10304 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10306 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10308 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10309 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10310 _("source1 and dest must be same register"));
10312 switch (inst
.instruction
)
10314 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10315 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10316 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10317 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10321 inst
.instruction
|= inst
.operands
[0].reg
;
10322 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10326 switch (inst
.instruction
)
10328 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10329 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10330 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10331 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10334 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10335 inst
.instruction
|= inst
.operands
[0].reg
;
10336 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10344 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10345 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10346 inst
.instruction
|= inst
.operands
[2].reg
;
10352 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10353 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10354 _("expression too complex"));
10355 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10356 inst
.instruction
|= (value
& 0xf000) >> 12;
10357 inst
.instruction
|= (value
& 0x0ff0);
10358 inst
.instruction
|= (value
& 0x000f) << 16;
10364 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10365 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10366 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10368 if (inst
.operands
[3].present
)
10370 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10371 _("expression too complex"));
10373 if (inst
.reloc
.exp
.X_add_number
!= 0)
10375 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10376 inst
.instruction
|= 0x00200000; /* sh bit */
10377 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10378 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10380 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10387 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10388 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10389 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10395 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10396 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10397 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10398 || inst
.operands
[2].negative
,
10401 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10402 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10403 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10404 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10410 if (!inst
.operands
[2].present
)
10411 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10413 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10414 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10415 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10416 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10419 inst
.instruction
|= inst
.operands
[0].reg
;
10420 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10421 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10422 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10428 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10429 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10430 inst
.instruction
|= inst
.operands
[2].reg
;
10431 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10437 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10438 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10439 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10441 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10442 inst
.instruction
|= inst
.operands
[0].reg
;
10443 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10445 else if (unified_syntax
)
10447 if (inst
.instruction
<= 0xffff)
10448 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10449 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10450 inst
.instruction
|= inst
.operands
[1].reg
;
10451 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10455 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10456 _("Thumb encoding does not support rotation"));
10457 constraint (1, BAD_HIREG
);
10464 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10472 half
= (inst
.instruction
& 0x10) != 0;
10473 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10474 constraint (inst
.operands
[0].immisreg
,
10475 _("instruction requires register index"));
10476 constraint (inst
.operands
[0].imm
== 15,
10477 _("PC is not a valid index register"));
10478 constraint (!half
&& inst
.operands
[0].shifted
,
10479 _("instruction does not allow shifted index"));
10480 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10486 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10487 inst
.instruction
|= inst
.operands
[1].imm
;
10488 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10490 if (inst
.operands
[3].present
)
10492 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10493 _("expression too complex"));
10494 if (inst
.reloc
.exp
.X_add_number
!= 0)
10496 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10497 inst
.instruction
|= 0x00200000; /* sh bit */
10499 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10500 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10502 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10509 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10510 inst
.instruction
|= inst
.operands
[1].imm
;
10511 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10514 /* Neon instruction encoder helpers. */
10516 /* Encodings for the different types for various Neon opcodes. */
10518 /* An "invalid" code for the following tables. */
10521 struct neon_tab_entry
10524 unsigned float_or_poly
;
10525 unsigned scalar_or_imm
;
10528 /* Map overloaded Neon opcodes to their respective encodings. */
10529 #define NEON_ENC_TAB \
10530 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10531 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10532 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10533 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10534 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10535 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10536 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10537 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10538 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10539 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10540 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10541 /* Register variants of the following two instructions are encoded as
10542 vcge / vcgt with the operands reversed. */ \
10543 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10544 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10545 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10546 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10547 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10548 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10549 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10550 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10551 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10552 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10553 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10554 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10555 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10556 X(vshl, 0x0000400, N_INV, 0x0800510), \
10557 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10558 X(vand, 0x0000110, N_INV, 0x0800030), \
10559 X(vbic, 0x0100110, N_INV, 0x0800030), \
10560 X(veor, 0x1000110, N_INV, N_INV), \
10561 X(vorn, 0x0300110, N_INV, 0x0800010), \
10562 X(vorr, 0x0200110, N_INV, 0x0800010), \
10563 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10564 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10565 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10566 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10567 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10568 X(vst1, 0x0000000, 0x0800000, N_INV), \
10569 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10570 X(vst2, 0x0000100, 0x0800100, N_INV), \
10571 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10572 X(vst3, 0x0000200, 0x0800200, N_INV), \
10573 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10574 X(vst4, 0x0000300, 0x0800300, N_INV), \
10575 X(vmovn, 0x1b20200, N_INV, N_INV), \
10576 X(vtrn, 0x1b20080, N_INV, N_INV), \
10577 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10578 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10579 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10580 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10581 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10582 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10583 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10584 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10585 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10589 #define X(OPC,I,F,S) N_MNEM_##OPC
10594 static const struct neon_tab_entry neon_enc_tab
[] =
10596 #define X(OPC,I,F,S) { (I), (F), (S) }
10601 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10602 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10603 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10604 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10605 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10606 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10607 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10608 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10609 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10610 #define NEON_ENC_SINGLE(X) \
10611 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10612 #define NEON_ENC_DOUBLE(X) \
10613 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10615 /* Define shapes for instruction operands. The following mnemonic characters
10616 are used in this table:
10618 F - VFP S<n> register
10619 D - Neon D<n> register
10620 Q - Neon Q<n> register
10624 L - D<n> register list
10626 This table is used to generate various data:
10627 - enumerations of the form NS_DDR to be used as arguments to
10629 - a table classifying shapes into single, double, quad, mixed.
10630 - a table used to drive neon_select_shape. */
10632 #define NEON_SHAPE_DEF \
10633 X(3, (D, D, D), DOUBLE), \
10634 X(3, (Q, Q, Q), QUAD), \
10635 X(3, (D, D, I), DOUBLE), \
10636 X(3, (Q, Q, I), QUAD), \
10637 X(3, (D, D, S), DOUBLE), \
10638 X(3, (Q, Q, S), QUAD), \
10639 X(2, (D, D), DOUBLE), \
10640 X(2, (Q, Q), QUAD), \
10641 X(2, (D, S), DOUBLE), \
10642 X(2, (Q, S), QUAD), \
10643 X(2, (D, R), DOUBLE), \
10644 X(2, (Q, R), QUAD), \
10645 X(2, (D, I), DOUBLE), \
10646 X(2, (Q, I), QUAD), \
10647 X(3, (D, L, D), DOUBLE), \
10648 X(2, (D, Q), MIXED), \
10649 X(2, (Q, D), MIXED), \
10650 X(3, (D, Q, I), MIXED), \
10651 X(3, (Q, D, I), MIXED), \
10652 X(3, (Q, D, D), MIXED), \
10653 X(3, (D, Q, Q), MIXED), \
10654 X(3, (Q, Q, D), MIXED), \
10655 X(3, (Q, D, S), MIXED), \
10656 X(3, (D, Q, S), MIXED), \
10657 X(4, (D, D, D, I), DOUBLE), \
10658 X(4, (Q, Q, Q, I), QUAD), \
10659 X(2, (F, F), SINGLE), \
10660 X(3, (F, F, F), SINGLE), \
10661 X(2, (F, I), SINGLE), \
10662 X(2, (F, D), MIXED), \
10663 X(2, (D, F), MIXED), \
10664 X(3, (F, F, I), MIXED), \
10665 X(4, (R, R, F, F), SINGLE), \
10666 X(4, (F, F, R, R), SINGLE), \
10667 X(3, (D, R, R), DOUBLE), \
10668 X(3, (R, R, D), DOUBLE), \
10669 X(2, (S, R), SINGLE), \
10670 X(2, (R, S), SINGLE), \
10671 X(2, (F, R), SINGLE), \
10672 X(2, (R, F), SINGLE)
10674 #define S2(A,B) NS_##A##B
10675 #define S3(A,B,C) NS_##A##B##C
10676 #define S4(A,B,C,D) NS_##A##B##C##D
10678 #define X(N, L, C) S##N L
10691 enum neon_shape_class
10699 #define X(N, L, C) SC_##C
10701 static enum neon_shape_class neon_shape_class
[] =
10719 /* Register widths of above. */
10720 static unsigned neon_shape_el_size
[] =
10731 struct neon_shape_info
10734 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10737 #define S2(A,B) { SE_##A, SE_##B }
10738 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10739 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10741 #define X(N, L, C) { N, S##N L }
10743 static struct neon_shape_info neon_shape_tab
[] =
10753 /* Bit masks used in type checking given instructions.
10754 'N_EQK' means the type must be the same as (or based on in some way) the key
10755 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10756 set, various other bits can be set as well in order to modify the meaning of
10757 the type constraint. */
10759 enum neon_type_mask
10782 N_KEY
= 0x1000000, /* key element (main type specifier). */
10783 N_EQK
= 0x2000000, /* given operand has the same type & size as the key. */
10784 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
10785 N_DBL
= 0x0000001, /* if N_EQK, this operand is twice the size. */
10786 N_HLF
= 0x0000002, /* if N_EQK, this operand is half the size. */
10787 N_SGN
= 0x0000004, /* if N_EQK, this operand is forced to be signed. */
10788 N_UNS
= 0x0000008, /* if N_EQK, this operand is forced to be unsigned. */
10789 N_INT
= 0x0000010, /* if N_EQK, this operand is forced to be integer. */
10790 N_FLT
= 0x0000020, /* if N_EQK, this operand is forced to be float. */
10791 N_SIZ
= 0x0000040, /* if N_EQK, this operand is forced to be size-only. */
10793 N_MAX_NONSPECIAL
= N_F64
10796 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10798 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10799 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10800 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10801 #define N_SUF_32 (N_SU_32 | N_F32)
10802 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10803 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10805 /* Pass this as the first type argument to neon_check_type to ignore types
10807 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10809 /* Select a "shape" for the current instruction (describing register types or
10810 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10811 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10812 function of operand parsing, so this function doesn't need to be called.
10813 Shapes should be listed in order of decreasing length. */
10815 static enum neon_shape
10816 neon_select_shape (enum neon_shape shape
, ...)
10819 enum neon_shape first_shape
= shape
;
10821 /* Fix missing optional operands. FIXME: we don't know at this point how
10822 many arguments we should have, so this makes the assumption that we have
10823 > 1. This is true of all current Neon opcodes, I think, but may not be
10824 true in the future. */
10825 if (!inst
.operands
[1].present
)
10826 inst
.operands
[1] = inst
.operands
[0];
10828 va_start (ap
, shape
);
10830 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10835 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10837 if (!inst
.operands
[j
].present
)
10843 switch (neon_shape_tab
[shape
].el
[j
])
10846 if (!(inst
.operands
[j
].isreg
10847 && inst
.operands
[j
].isvec
10848 && inst
.operands
[j
].issingle
10849 && !inst
.operands
[j
].isquad
))
10854 if (!(inst
.operands
[j
].isreg
10855 && inst
.operands
[j
].isvec
10856 && !inst
.operands
[j
].isquad
10857 && !inst
.operands
[j
].issingle
))
10862 if (!(inst
.operands
[j
].isreg
10863 && !inst
.operands
[j
].isvec
))
10868 if (!(inst
.operands
[j
].isreg
10869 && inst
.operands
[j
].isvec
10870 && inst
.operands
[j
].isquad
10871 && !inst
.operands
[j
].issingle
))
10876 if (!(!inst
.operands
[j
].isreg
10877 && !inst
.operands
[j
].isscalar
))
10882 if (!(!inst
.operands
[j
].isreg
10883 && inst
.operands
[j
].isscalar
))
10897 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10898 first_error (_("invalid instruction shape"));
10903 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10904 means the Q bit should be set). */
10907 neon_quad (enum neon_shape shape
)
10909 return neon_shape_class
[shape
] == SC_QUAD
;
10913 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10916 /* Allow modification to be made to types which are constrained to be
10917 based on the key element, based on bits set alongside N_EQK. */
10918 if ((typebits
& N_EQK
) != 0)
10920 if ((typebits
& N_HLF
) != 0)
10922 else if ((typebits
& N_DBL
) != 0)
10924 if ((typebits
& N_SGN
) != 0)
10925 *g_type
= NT_signed
;
10926 else if ((typebits
& N_UNS
) != 0)
10927 *g_type
= NT_unsigned
;
10928 else if ((typebits
& N_INT
) != 0)
10929 *g_type
= NT_integer
;
10930 else if ((typebits
& N_FLT
) != 0)
10931 *g_type
= NT_float
;
10932 else if ((typebits
& N_SIZ
) != 0)
10933 *g_type
= NT_untyped
;
10937 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10938 operand type, i.e. the single type specified in a Neon instruction when it
10939 is the only one given. */
10941 static struct neon_type_el
10942 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10944 struct neon_type_el dest
= *key
;
10946 assert ((thisarg
& N_EQK
) != 0);
10948 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10953 /* Convert Neon type and size into compact bitmask representation. */
10955 static enum neon_type_mask
10956 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10963 case 8: return N_8
;
10964 case 16: return N_16
;
10965 case 32: return N_32
;
10966 case 64: return N_64
;
10974 case 8: return N_I8
;
10975 case 16: return N_I16
;
10976 case 32: return N_I32
;
10977 case 64: return N_I64
;
10985 case 16: return N_F16
;
10986 case 32: return N_F32
;
10987 case 64: return N_F64
;
10995 case 8: return N_P8
;
10996 case 16: return N_P16
;
11004 case 8: return N_S8
;
11005 case 16: return N_S16
;
11006 case 32: return N_S32
;
11007 case 64: return N_S64
;
11015 case 8: return N_U8
;
11016 case 16: return N_U16
;
11017 case 32: return N_U32
;
11018 case 64: return N_U64
;
11029 /* Convert compact Neon bitmask type representation to a type and size. Only
11030 handles the case where a single bit is set in the mask. */
11033 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11034 enum neon_type_mask mask
)
11036 if ((mask
& N_EQK
) != 0)
11039 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11041 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11043 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11045 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11050 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11052 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11053 *type
= NT_unsigned
;
11054 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11055 *type
= NT_integer
;
11056 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11057 *type
= NT_untyped
;
11058 else if ((mask
& (N_P8
| N_P16
)) != 0)
11060 else if ((mask
& (N_F32
| N_F64
)) != 0)
11068 /* Modify a bitmask of allowed types. This is only needed for type
11072 modify_types_allowed (unsigned allowed
, unsigned mods
)
11075 enum neon_el_type type
;
11081 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11083 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
11085 neon_modify_type_size (mods
, &type
, &size
);
11086 destmask
|= type_chk_of_el_type (type
, size
);
11093 /* Check type and return type classification.
11094 The manual states (paraphrase): If one datatype is given, it indicates the
11096 - the second operand, if there is one
11097 - the operand, if there is no second operand
11098 - the result, if there are no operands.
11099 This isn't quite good enough though, so we use a concept of a "key" datatype
11100 which is set on a per-instruction basis, which is the one which matters when
11101 only one data type is written.
11102 Note: this function has side-effects (e.g. filling in missing operands). All
11103 Neon instructions should call it before performing bit encoding. */
11105 static struct neon_type_el
11106 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11109 unsigned i
, pass
, key_el
= 0;
11110 unsigned types
[NEON_MAX_TYPE_ELS
];
11111 enum neon_el_type k_type
= NT_invtype
;
11112 unsigned k_size
= -1u;
11113 struct neon_type_el badtype
= {NT_invtype
, -1};
11114 unsigned key_allowed
= 0;
11116 /* Optional registers in Neon instructions are always (not) in operand 1.
11117 Fill in the missing operand here, if it was omitted. */
11118 if (els
> 1 && !inst
.operands
[1].present
)
11119 inst
.operands
[1] = inst
.operands
[0];
11121 /* Suck up all the varargs. */
11123 for (i
= 0; i
< els
; i
++)
11125 unsigned thisarg
= va_arg (ap
, unsigned);
11126 if (thisarg
== N_IGNORE_TYPE
)
11131 types
[i
] = thisarg
;
11132 if ((thisarg
& N_KEY
) != 0)
11137 if (inst
.vectype
.elems
> 0)
11138 for (i
= 0; i
< els
; i
++)
11139 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11141 first_error (_("types specified in both the mnemonic and operands"));
11145 /* Duplicate inst.vectype elements here as necessary.
11146 FIXME: No idea if this is exactly the same as the ARM assembler,
11147 particularly when an insn takes one register and one non-register
11149 if (inst
.vectype
.elems
== 1 && els
> 1)
11152 inst
.vectype
.elems
= els
;
11153 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11154 for (j
= 0; j
< els
; j
++)
11156 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11159 else if (inst
.vectype
.elems
== 0 && els
> 0)
11162 /* No types were given after the mnemonic, so look for types specified
11163 after each operand. We allow some flexibility here; as long as the
11164 "key" operand has a type, we can infer the others. */
11165 for (j
= 0; j
< els
; j
++)
11166 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11167 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11169 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11171 for (j
= 0; j
< els
; j
++)
11172 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11173 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11178 first_error (_("operand types can't be inferred"));
11182 else if (inst
.vectype
.elems
!= els
)
11184 first_error (_("type specifier has the wrong number of parts"));
11188 for (pass
= 0; pass
< 2; pass
++)
11190 for (i
= 0; i
< els
; i
++)
11192 unsigned thisarg
= types
[i
];
11193 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11194 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11195 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11196 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11198 /* Decay more-specific signed & unsigned types to sign-insensitive
11199 integer types if sign-specific variants are unavailable. */
11200 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11201 && (types_allowed
& N_SU_ALL
) == 0)
11202 g_type
= NT_integer
;
11204 /* If only untyped args are allowed, decay any more specific types to
11205 them. Some instructions only care about signs for some element
11206 sizes, so handle that properly. */
11207 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11208 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11209 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11210 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11211 g_type
= NT_untyped
;
11215 if ((thisarg
& N_KEY
) != 0)
11219 key_allowed
= thisarg
& ~N_KEY
;
11224 if ((thisarg
& N_VFP
) != 0)
11226 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11227 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11229 /* In VFP mode, operands must match register widths. If we
11230 have a key operand, use its width, else use the width of
11231 the current operand. */
11237 if (regwidth
!= match
)
11239 first_error (_("operand size must match register width"));
11244 if ((thisarg
& N_EQK
) == 0)
11246 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11248 if ((given_type
& types_allowed
) == 0)
11250 first_error (_("bad type in Neon instruction"));
11256 enum neon_el_type mod_k_type
= k_type
;
11257 unsigned mod_k_size
= k_size
;
11258 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11259 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11261 first_error (_("inconsistent types in Neon instruction"));
11269 return inst
.vectype
.el
[key_el
];
11272 /* Neon-style VFP instruction forwarding. */
11274 /* Thumb VFP instructions have 0xE in the condition field. */
11277 do_vfp_cond_or_thumb (void)
11280 inst
.instruction
|= 0xe0000000;
11282 inst
.instruction
|= inst
.cond
<< 28;
11285 /* Look up and encode a simple mnemonic, for use as a helper function for the
11286 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11287 etc. It is assumed that operand parsing has already been done, and that the
11288 operands are in the form expected by the given opcode (this isn't necessarily
11289 the same as the form in which they were parsed, hence some massaging must
11290 take place before this function is called).
11291 Checks current arch version against that in the looked-up opcode. */
11294 do_vfp_nsyn_opcode (const char *opname
)
11296 const struct asm_opcode
*opcode
;
11298 opcode
= hash_find (arm_ops_hsh
, opname
);
11303 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11304 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11309 inst
.instruction
= opcode
->tvalue
;
11310 opcode
->tencode ();
11314 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11315 opcode
->aencode ();
11320 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11322 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11327 do_vfp_nsyn_opcode ("fadds");
11329 do_vfp_nsyn_opcode ("fsubs");
11334 do_vfp_nsyn_opcode ("faddd");
11336 do_vfp_nsyn_opcode ("fsubd");
11340 /* Check operand types to see if this is a VFP instruction, and if so call
11344 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11346 enum neon_shape rs
;
11347 struct neon_type_el et
;
11352 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11353 et
= neon_check_type (2, rs
,
11354 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11358 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11359 et
= neon_check_type (3, rs
,
11360 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11367 if (et
.type
!= NT_invtype
)
11379 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11381 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11386 do_vfp_nsyn_opcode ("fmacs");
11388 do_vfp_nsyn_opcode ("fmscs");
11393 do_vfp_nsyn_opcode ("fmacd");
11395 do_vfp_nsyn_opcode ("fmscd");
11400 do_vfp_nsyn_mul (enum neon_shape rs
)
11403 do_vfp_nsyn_opcode ("fmuls");
11405 do_vfp_nsyn_opcode ("fmuld");
11409 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11411 int is_neg
= (inst
.instruction
& 0x80) != 0;
11412 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11417 do_vfp_nsyn_opcode ("fnegs");
11419 do_vfp_nsyn_opcode ("fabss");
11424 do_vfp_nsyn_opcode ("fnegd");
11426 do_vfp_nsyn_opcode ("fabsd");
11430 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11431 insns belong to Neon, and are handled elsewhere. */
11434 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11436 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11440 do_vfp_nsyn_opcode ("fldmdbs");
11442 do_vfp_nsyn_opcode ("fldmias");
11447 do_vfp_nsyn_opcode ("fstmdbs");
11449 do_vfp_nsyn_opcode ("fstmias");
11454 do_vfp_nsyn_sqrt (void)
11456 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11457 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11460 do_vfp_nsyn_opcode ("fsqrts");
11462 do_vfp_nsyn_opcode ("fsqrtd");
11466 do_vfp_nsyn_div (void)
11468 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11469 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11470 N_F32
| N_F64
| N_KEY
| N_VFP
);
11473 do_vfp_nsyn_opcode ("fdivs");
11475 do_vfp_nsyn_opcode ("fdivd");
11479 do_vfp_nsyn_nmul (void)
11481 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11482 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11483 N_F32
| N_F64
| N_KEY
| N_VFP
);
11487 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11488 do_vfp_sp_dyadic ();
11492 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11493 do_vfp_dp_rd_rn_rm ();
11495 do_vfp_cond_or_thumb ();
11499 do_vfp_nsyn_cmp (void)
11501 if (inst
.operands
[1].isreg
)
11503 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11504 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11508 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11509 do_vfp_sp_monadic ();
11513 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11514 do_vfp_dp_rd_rm ();
11519 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11520 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11522 switch (inst
.instruction
& 0x0fffffff)
11525 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11528 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11536 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11537 do_vfp_sp_compare_z ();
11541 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11545 do_vfp_cond_or_thumb ();
11549 nsyn_insert_sp (void)
11551 inst
.operands
[1] = inst
.operands
[0];
11552 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11553 inst
.operands
[0].reg
= 13;
11554 inst
.operands
[0].isreg
= 1;
11555 inst
.operands
[0].writeback
= 1;
11556 inst
.operands
[0].present
= 1;
11560 do_vfp_nsyn_push (void)
11563 if (inst
.operands
[1].issingle
)
11564 do_vfp_nsyn_opcode ("fstmdbs");
11566 do_vfp_nsyn_opcode ("fstmdbd");
11570 do_vfp_nsyn_pop (void)
11573 if (inst
.operands
[1].issingle
)
11574 do_vfp_nsyn_opcode ("fldmias");
11576 do_vfp_nsyn_opcode ("fldmiad");
11579 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11580 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11583 neon_dp_fixup (unsigned i
)
11587 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11601 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11605 neon_logbits (unsigned x
)
11607 return ffs (x
) - 4;
11610 #define LOW4(R) ((R) & 0xf)
11611 #define HI1(R) (((R) >> 4) & 1)
11613 /* Encode insns with bit pattern:
11615 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11616 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11618 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11619 different meaning for some instruction. */
11622 neon_three_same (int isquad
, int ubit
, int size
)
11624 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11625 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11626 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11627 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11628 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11629 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11630 inst
.instruction
|= (isquad
!= 0) << 6;
11631 inst
.instruction
|= (ubit
!= 0) << 24;
11633 inst
.instruction
|= neon_logbits (size
) << 20;
11635 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11638 /* Encode instructions of the form:
11640 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11641 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11643 Don't write size if SIZE == -1. */
11646 neon_two_same (int qbit
, int ubit
, int size
)
11648 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11649 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11650 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11651 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11652 inst
.instruction
|= (qbit
!= 0) << 6;
11653 inst
.instruction
|= (ubit
!= 0) << 24;
11656 inst
.instruction
|= neon_logbits (size
) << 18;
11658 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11661 /* Neon instruction encoders, in approximate order of appearance. */
11664 do_neon_dyadic_i_su (void)
11666 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11667 struct neon_type_el et
= neon_check_type (3, rs
,
11668 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11669 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11673 do_neon_dyadic_i64_su (void)
11675 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11676 struct neon_type_el et
= neon_check_type (3, rs
,
11677 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11678 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11682 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11685 unsigned size
= et
.size
>> 3;
11686 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11687 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11688 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11689 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11690 inst
.instruction
|= (isquad
!= 0) << 6;
11691 inst
.instruction
|= immbits
<< 16;
11692 inst
.instruction
|= (size
>> 3) << 7;
11693 inst
.instruction
|= (size
& 0x7) << 19;
11695 inst
.instruction
|= (uval
!= 0) << 24;
11697 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11701 do_neon_shl_imm (void)
11703 if (!inst
.operands
[2].isreg
)
11705 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11706 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11707 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11708 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11712 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11713 struct neon_type_el et
= neon_check_type (3, rs
,
11714 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11717 /* VSHL/VQSHL 3-register variants have syntax such as:
11719 whereas other 3-register operations encoded by neon_three_same have
11722 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11724 tmp
= inst
.operands
[2].reg
;
11725 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11726 inst
.operands
[1].reg
= tmp
;
11727 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11728 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11733 do_neon_qshl_imm (void)
11735 if (!inst
.operands
[2].isreg
)
11737 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11738 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11740 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11741 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11742 inst
.operands
[2].imm
);
11746 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11747 struct neon_type_el et
= neon_check_type (3, rs
,
11748 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11751 /* See note in do_neon_shl_imm. */
11752 tmp
= inst
.operands
[2].reg
;
11753 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11754 inst
.operands
[1].reg
= tmp
;
11755 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11756 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11761 do_neon_rshl (void)
11763 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11764 struct neon_type_el et
= neon_check_type (3, rs
,
11765 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11768 tmp
= inst
.operands
[2].reg
;
11769 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11770 inst
.operands
[1].reg
= tmp
;
11771 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11775 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11777 /* Handle .I8 pseudo-instructions. */
11780 /* Unfortunately, this will make everything apart from zero out-of-range.
11781 FIXME is this the intended semantics? There doesn't seem much point in
11782 accepting .I8 if so. */
11783 immediate
|= immediate
<< 8;
11789 if (immediate
== (immediate
& 0x000000ff))
11791 *immbits
= immediate
;
11794 else if (immediate
== (immediate
& 0x0000ff00))
11796 *immbits
= immediate
>> 8;
11799 else if (immediate
== (immediate
& 0x00ff0000))
11801 *immbits
= immediate
>> 16;
11804 else if (immediate
== (immediate
& 0xff000000))
11806 *immbits
= immediate
>> 24;
11809 if ((immediate
& 0xffff) != (immediate
>> 16))
11810 goto bad_immediate
;
11811 immediate
&= 0xffff;
11814 if (immediate
== (immediate
& 0x000000ff))
11816 *immbits
= immediate
;
11819 else if (immediate
== (immediate
& 0x0000ff00))
11821 *immbits
= immediate
>> 8;
11826 first_error (_("immediate value out of range"));
11830 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11834 neon_bits_same_in_bytes (unsigned imm
)
11836 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11837 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11838 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11839 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11842 /* For immediate of above form, return 0bABCD. */
11845 neon_squash_bits (unsigned imm
)
11847 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11848 | ((imm
& 0x01000000) >> 21);
11851 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11854 neon_qfloat_bits (unsigned imm
)
11856 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11859 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11860 the instruction. *OP is passed as the initial value of the op field, and
11861 may be set to a different value depending on the constant (i.e.
11862 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11863 MVN). If the immediate looks like a repeated pattern then also
11864 try smaller element sizes. */
11867 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
11868 unsigned *immbits
, int *op
, int size
,
11869 enum neon_el_type type
)
11871 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11873 if (type
== NT_float
&& !float_p
)
11876 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11878 if (size
!= 32 || *op
== 1)
11880 *immbits
= neon_qfloat_bits (immlo
);
11886 if (neon_bits_same_in_bytes (immhi
)
11887 && neon_bits_same_in_bytes (immlo
))
11891 *immbits
= (neon_squash_bits (immhi
) << 4)
11892 | neon_squash_bits (immlo
);
11897 if (immhi
!= immlo
)
11903 if (immlo
== (immlo
& 0x000000ff))
11908 else if (immlo
== (immlo
& 0x0000ff00))
11910 *immbits
= immlo
>> 8;
11913 else if (immlo
== (immlo
& 0x00ff0000))
11915 *immbits
= immlo
>> 16;
11918 else if (immlo
== (immlo
& 0xff000000))
11920 *immbits
= immlo
>> 24;
11923 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11925 *immbits
= (immlo
>> 8) & 0xff;
11928 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11930 *immbits
= (immlo
>> 16) & 0xff;
11934 if ((immlo
& 0xffff) != (immlo
>> 16))
11941 if (immlo
== (immlo
& 0x000000ff))
11946 else if (immlo
== (immlo
& 0x0000ff00))
11948 *immbits
= immlo
>> 8;
11952 if ((immlo
& 0xff) != (immlo
>> 8))
11957 if (immlo
== (immlo
& 0x000000ff))
11959 /* Don't allow MVN with 8-bit immediate. */
11969 /* Write immediate bits [7:0] to the following locations:
11971 |28/24|23 19|18 16|15 4|3 0|
11972 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11974 This function is used by VMOV/VMVN/VORR/VBIC. */
11977 neon_write_immbits (unsigned immbits
)
11979 inst
.instruction
|= immbits
& 0xf;
11980 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11981 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11984 /* Invert low-order SIZE bits of XHI:XLO. */
11987 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11989 unsigned immlo
= xlo
? *xlo
: 0;
11990 unsigned immhi
= xhi
? *xhi
: 0;
11995 immlo
= (~immlo
) & 0xff;
11999 immlo
= (~immlo
) & 0xffff;
12003 immhi
= (~immhi
) & 0xffffffff;
12004 /* fall through. */
12007 immlo
= (~immlo
) & 0xffffffff;
12022 do_neon_logic (void)
12024 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12026 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12027 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12028 /* U bit and size field were set as part of the bitmask. */
12029 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12030 neon_three_same (neon_quad (rs
), 0, -1);
12034 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12035 struct neon_type_el et
= neon_check_type (2, rs
,
12036 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12037 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
12041 if (et
.type
== NT_invtype
)
12044 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12046 immbits
= inst
.operands
[1].imm
;
12049 /* .i64 is a pseudo-op, so the immediate must be a repeating
12051 if (immbits
!= (inst
.operands
[1].regisimm
?
12052 inst
.operands
[1].reg
: 0))
12054 /* Set immbits to an invalid constant. */
12055 immbits
= 0xdeadbeef;
12062 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12066 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12070 /* Pseudo-instruction for VBIC. */
12071 neon_invert_size (&immbits
, 0, et
.size
);
12072 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12076 /* Pseudo-instruction for VORR. */
12077 neon_invert_size (&immbits
, 0, et
.size
);
12078 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12088 inst
.instruction
|= neon_quad (rs
) << 6;
12089 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12090 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12091 inst
.instruction
|= cmode
<< 8;
12092 neon_write_immbits (immbits
);
12094 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12099 do_neon_bitfield (void)
12101 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12102 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12103 neon_three_same (neon_quad (rs
), 0, -1);
12107 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12110 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12111 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12113 if (et
.type
== NT_float
)
12115 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12116 neon_three_same (neon_quad (rs
), 0, -1);
12120 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12121 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12126 do_neon_dyadic_if_su (void)
12128 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12132 do_neon_dyadic_if_su_d (void)
12134 /* This version only allow D registers, but that constraint is enforced during
12135 operand parsing so we don't need to do anything extra here. */
12136 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12140 do_neon_dyadic_if_i_d (void)
12142 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12143 affected if we specify unsigned args. */
12144 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12147 enum vfp_or_neon_is_neon_bits
12150 NEON_CHECK_ARCH
= 2
12153 /* Call this function if an instruction which may have belonged to the VFP or
12154 Neon instruction sets, but turned out to be a Neon instruction (due to the
12155 operand types involved, etc.). We have to check and/or fix-up a couple of
12158 - Make sure the user hasn't attempted to make a Neon instruction
12160 - Alter the value in the condition code field if necessary.
12161 - Make sure that the arch supports Neon instructions.
12163 Which of these operations take place depends on bits from enum
12164 vfp_or_neon_is_neon_bits.
12166 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12167 current instruction's condition is COND_ALWAYS, the condition field is
12168 changed to inst.uncond_value. This is necessary because instructions shared
12169 between VFP and Neon may be conditional for the VFP variants only, and the
12170 unconditional Neon version must have, e.g., 0xF in the condition field. */
12173 vfp_or_neon_is_neon (unsigned check
)
12175 /* Conditions are always legal in Thumb mode (IT blocks). */
12176 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12178 if (inst
.cond
!= COND_ALWAYS
)
12180 first_error (_(BAD_COND
));
12183 if (inst
.uncond_value
!= -1)
12184 inst
.instruction
|= inst
.uncond_value
<< 28;
12187 if ((check
& NEON_CHECK_ARCH
)
12188 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12190 first_error (_(BAD_FPU
));
12198 do_neon_addsub_if_i (void)
12200 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12203 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12206 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12207 affected if we specify unsigned args. */
12208 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12211 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12213 V<op> A,B (A is operand 0, B is operand 2)
12218 so handle that case specially. */
12221 neon_exchange_operands (void)
12223 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12224 if (inst
.operands
[1].present
)
12226 /* Swap operands[1] and operands[2]. */
12227 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12228 inst
.operands
[1] = inst
.operands
[2];
12229 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12233 inst
.operands
[1] = inst
.operands
[2];
12234 inst
.operands
[2] = inst
.operands
[0];
12239 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12241 if (inst
.operands
[2].isreg
)
12244 neon_exchange_operands ();
12245 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12249 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12250 struct neon_type_el et
= neon_check_type (2, rs
,
12251 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12253 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12254 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12255 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12256 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12257 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12258 inst
.instruction
|= neon_quad (rs
) << 6;
12259 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12260 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12262 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12269 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12273 do_neon_cmp_inv (void)
12275 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12281 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12284 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12285 scalars, which are encoded in 5 bits, M : Rm.
12286 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12287 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12291 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12293 unsigned regno
= NEON_SCALAR_REG (scalar
);
12294 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12299 if (regno
> 7 || elno
> 3)
12301 return regno
| (elno
<< 3);
12304 if (regno
> 15 || elno
> 1)
12306 return regno
| (elno
<< 4);
12310 first_error (_("scalar out of range for multiply instruction"));
12316 /* Encode multiply / multiply-accumulate scalar instructions. */
12319 neon_mul_mac (struct neon_type_el et
, int ubit
)
12323 /* Give a more helpful error message if we have an invalid type. */
12324 if (et
.type
== NT_invtype
)
12327 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12328 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12329 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12330 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12331 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12332 inst
.instruction
|= LOW4 (scalar
);
12333 inst
.instruction
|= HI1 (scalar
) << 5;
12334 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12335 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12336 inst
.instruction
|= (ubit
!= 0) << 24;
12338 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12342 do_neon_mac_maybe_scalar (void)
12344 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12347 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12350 if (inst
.operands
[2].isscalar
)
12352 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12353 struct neon_type_el et
= neon_check_type (3, rs
,
12354 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12355 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12356 neon_mul_mac (et
, neon_quad (rs
));
12360 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12361 affected if we specify unsigned args. */
12362 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12369 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12370 struct neon_type_el et
= neon_check_type (3, rs
,
12371 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12372 neon_three_same (neon_quad (rs
), 0, et
.size
);
12375 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12376 same types as the MAC equivalents. The polynomial type for this instruction
12377 is encoded the same as the integer type. */
12382 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12385 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12388 if (inst
.operands
[2].isscalar
)
12389 do_neon_mac_maybe_scalar ();
12391 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12395 do_neon_qdmulh (void)
12397 if (inst
.operands
[2].isscalar
)
12399 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12400 struct neon_type_el et
= neon_check_type (3, rs
,
12401 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12402 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12403 neon_mul_mac (et
, neon_quad (rs
));
12407 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12408 struct neon_type_el et
= neon_check_type (3, rs
,
12409 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12410 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12411 /* The U bit (rounding) comes from bit mask. */
12412 neon_three_same (neon_quad (rs
), 0, et
.size
);
12417 do_neon_fcmp_absolute (void)
12419 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12420 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12421 /* Size field comes from bit mask. */
12422 neon_three_same (neon_quad (rs
), 1, -1);
12426 do_neon_fcmp_absolute_inv (void)
12428 neon_exchange_operands ();
12429 do_neon_fcmp_absolute ();
12433 do_neon_step (void)
12435 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12436 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12437 neon_three_same (neon_quad (rs
), 0, -1);
12441 do_neon_abs_neg (void)
12443 enum neon_shape rs
;
12444 struct neon_type_el et
;
12446 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12449 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12452 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12453 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12455 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12456 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12457 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12458 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12459 inst
.instruction
|= neon_quad (rs
) << 6;
12460 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12461 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12463 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12469 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12470 struct neon_type_el et
= neon_check_type (2, rs
,
12471 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12472 int imm
= inst
.operands
[2].imm
;
12473 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12474 _("immediate out of range for insert"));
12475 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12481 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12482 struct neon_type_el et
= neon_check_type (2, rs
,
12483 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12484 int imm
= inst
.operands
[2].imm
;
12485 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12486 _("immediate out of range for insert"));
12487 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12491 do_neon_qshlu_imm (void)
12493 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12494 struct neon_type_el et
= neon_check_type (2, rs
,
12495 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12496 int imm
= inst
.operands
[2].imm
;
12497 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12498 _("immediate out of range for shift"));
12499 /* Only encodes the 'U present' variant of the instruction.
12500 In this case, signed types have OP (bit 8) set to 0.
12501 Unsigned types have OP set to 1. */
12502 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12503 /* The rest of the bits are the same as other immediate shifts. */
12504 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12508 do_neon_qmovn (void)
12510 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12511 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12512 /* Saturating move where operands can be signed or unsigned, and the
12513 destination has the same signedness. */
12514 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12515 if (et
.type
== NT_unsigned
)
12516 inst
.instruction
|= 0xc0;
12518 inst
.instruction
|= 0x80;
12519 neon_two_same (0, 1, et
.size
/ 2);
12523 do_neon_qmovun (void)
12525 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12526 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12527 /* Saturating move with unsigned results. Operands must be signed. */
12528 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12529 neon_two_same (0, 1, et
.size
/ 2);
12533 do_neon_rshift_sat_narrow (void)
12535 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12536 or unsigned. If operands are unsigned, results must also be unsigned. */
12537 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12538 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12539 int imm
= inst
.operands
[2].imm
;
12540 /* This gets the bounds check, size encoding and immediate bits calculation
12544 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12545 VQMOVN.I<size> <Dd>, <Qm>. */
12548 inst
.operands
[2].present
= 0;
12549 inst
.instruction
= N_MNEM_vqmovn
;
12554 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12555 _("immediate out of range"));
12556 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12560 do_neon_rshift_sat_narrow_u (void)
12562 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12563 or unsigned. If operands are unsigned, results must also be unsigned. */
12564 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12565 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12566 int imm
= inst
.operands
[2].imm
;
12567 /* This gets the bounds check, size encoding and immediate bits calculation
12571 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12572 VQMOVUN.I<size> <Dd>, <Qm>. */
12575 inst
.operands
[2].present
= 0;
12576 inst
.instruction
= N_MNEM_vqmovun
;
12581 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12582 _("immediate out of range"));
12583 /* FIXME: The manual is kind of unclear about what value U should have in
12584 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12586 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12590 do_neon_movn (void)
12592 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12593 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12594 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12595 neon_two_same (0, 1, et
.size
/ 2);
12599 do_neon_rshift_narrow (void)
12601 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12602 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12603 int imm
= inst
.operands
[2].imm
;
12604 /* This gets the bounds check, size encoding and immediate bits calculation
12608 /* If immediate is zero then we are a pseudo-instruction for
12609 VMOVN.I<size> <Dd>, <Qm> */
12612 inst
.operands
[2].present
= 0;
12613 inst
.instruction
= N_MNEM_vmovn
;
12618 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12619 _("immediate out of range for narrowing operation"));
12620 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12624 do_neon_shll (void)
12626 /* FIXME: Type checking when lengthening. */
12627 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12628 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12629 unsigned imm
= inst
.operands
[2].imm
;
12631 if (imm
== et
.size
)
12633 /* Maximum shift variant. */
12634 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12635 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12636 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12637 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12638 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12639 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12641 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12645 /* A more-specific type check for non-max versions. */
12646 et
= neon_check_type (2, NS_QDI
,
12647 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12648 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12649 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12653 /* Check the various types for the VCVT instruction, and return which version
12654 the current instruction is. */
12657 neon_cvt_flavour (enum neon_shape rs
)
12659 #define CVT_VAR(C,X,Y) \
12660 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12661 if (et.type != NT_invtype) \
12663 inst.error = NULL; \
12666 struct neon_type_el et
;
12667 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12668 || rs
== NS_FF
) ? N_VFP
: 0;
12669 /* The instruction versions which take an immediate take one register
12670 argument, which is extended to the width of the full register. Thus the
12671 "source" and "destination" registers must have the same width. Hack that
12672 here by making the size equal to the key (wider, in this case) operand. */
12673 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12675 CVT_VAR (0, N_S32
, N_F32
);
12676 CVT_VAR (1, N_U32
, N_F32
);
12677 CVT_VAR (2, N_F32
, N_S32
);
12678 CVT_VAR (3, N_F32
, N_U32
);
12679 /* Half-precision conversions. */
12680 CVT_VAR (4, N_F32
, N_F16
);
12681 CVT_VAR (5, N_F16
, N_F32
);
12685 /* VFP instructions. */
12686 CVT_VAR (6, N_F32
, N_F64
);
12687 CVT_VAR (7, N_F64
, N_F32
);
12688 CVT_VAR (8, N_S32
, N_F64
| key
);
12689 CVT_VAR (9, N_U32
, N_F64
| key
);
12690 CVT_VAR (10, N_F64
| key
, N_S32
);
12691 CVT_VAR (11, N_F64
| key
, N_U32
);
12692 /* VFP instructions with bitshift. */
12693 CVT_VAR (12, N_F32
| key
, N_S16
);
12694 CVT_VAR (13, N_F32
| key
, N_U16
);
12695 CVT_VAR (14, N_F64
| key
, N_S16
);
12696 CVT_VAR (15, N_F64
| key
, N_U16
);
12697 CVT_VAR (16, N_S16
, N_F32
| key
);
12698 CVT_VAR (17, N_U16
, N_F32
| key
);
12699 CVT_VAR (18, N_S16
, N_F64
| key
);
12700 CVT_VAR (19, N_U16
, N_F64
| key
);
12706 /* Neon-syntax VFP conversions. */
12709 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12711 const char *opname
= 0;
12713 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12715 /* Conversions with immediate bitshift. */
12716 const char *enc
[] =
12740 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12742 opname
= enc
[flavour
];
12743 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12744 _("operands 0 and 1 must be the same register"));
12745 inst
.operands
[1] = inst
.operands
[2];
12746 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12751 /* Conversions without bitshift. */
12752 const char *enc
[] =
12768 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12769 opname
= enc
[flavour
];
12773 do_vfp_nsyn_opcode (opname
);
12777 do_vfp_nsyn_cvtz (void)
12779 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12780 int flavour
= neon_cvt_flavour (rs
);
12781 const char *enc
[] =
12795 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12796 do_vfp_nsyn_opcode (enc
[flavour
]);
12802 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12803 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
12804 int flavour
= neon_cvt_flavour (rs
);
12806 /* VFP rather than Neon conversions. */
12809 do_vfp_nsyn_cvt (rs
, flavour
);
12819 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12821 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12824 /* Fixed-point conversion with #0 immediate is encoded as an
12825 integer conversion. */
12826 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12828 immbits
= 32 - inst
.operands
[2].imm
;
12829 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12831 inst
.instruction
|= enctab
[flavour
];
12832 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12833 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12834 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12835 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12836 inst
.instruction
|= neon_quad (rs
) << 6;
12837 inst
.instruction
|= 1 << 21;
12838 inst
.instruction
|= immbits
<< 16;
12840 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12848 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12850 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12852 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12856 inst
.instruction
|= enctab
[flavour
];
12858 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12859 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12860 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12861 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12862 inst
.instruction
|= neon_quad (rs
) << 6;
12863 inst
.instruction
|= 2 << 18;
12865 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12869 /* Half-precision conversions for Advanced SIMD -- neon. */
12874 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
12876 as_bad (_("operand size must match register width"));
12881 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
12883 as_bad (_("operand size must match register width"));
12888 inst
.instruction
= 0x3b60600;
12890 inst
.instruction
= 0x3b60700;
12892 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12893 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12894 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12895 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12896 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12900 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12901 do_vfp_nsyn_cvt (rs
, flavour
);
12906 do_neon_cvtb (void)
12908 inst
.instruction
= 0xeb20a40;
12910 /* The sizes are attached to the mnemonic. */
12911 if (inst
.vectype
.el
[0].type
!= NT_invtype
12912 && inst
.vectype
.el
[0].size
== 16)
12913 inst
.instruction
|= 0x00010000;
12915 /* Programmer's syntax: the sizes are attached to the operands. */
12916 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
12917 && inst
.operands
[0].vectype
.size
== 16)
12918 inst
.instruction
|= 0x00010000;
12920 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
12921 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
12922 do_vfp_cond_or_thumb ();
12927 do_neon_cvtt (void)
12930 inst
.instruction
|= 0x80;
12934 neon_move_immediate (void)
12936 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12937 struct neon_type_el et
= neon_check_type (2, rs
,
12938 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12939 unsigned immlo
, immhi
= 0, immbits
;
12940 int op
, cmode
, float_p
;
12942 constraint (et
.type
== NT_invtype
,
12943 _("operand size must be specified for immediate VMOV"));
12945 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12946 op
= (inst
.instruction
& (1 << 5)) != 0;
12948 immlo
= inst
.operands
[1].imm
;
12949 if (inst
.operands
[1].regisimm
)
12950 immhi
= inst
.operands
[1].reg
;
12952 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12953 _("immediate has bits set outside the operand size"));
12955 float_p
= inst
.operands
[1].immisfloat
;
12957 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
12958 et
.size
, et
.type
)) == FAIL
)
12960 /* Invert relevant bits only. */
12961 neon_invert_size (&immlo
, &immhi
, et
.size
);
12962 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12963 with one or the other; those cases are caught by
12964 neon_cmode_for_move_imm. */
12966 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
12967 &op
, et
.size
, et
.type
)) == FAIL
)
12969 first_error (_("immediate out of range"));
12974 inst
.instruction
&= ~(1 << 5);
12975 inst
.instruction
|= op
<< 5;
12977 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12978 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12979 inst
.instruction
|= neon_quad (rs
) << 6;
12980 inst
.instruction
|= cmode
<< 8;
12982 neon_write_immbits (immbits
);
12988 if (inst
.operands
[1].isreg
)
12990 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12992 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12993 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12994 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12995 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12996 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12997 inst
.instruction
|= neon_quad (rs
) << 6;
13001 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13002 neon_move_immediate ();
13005 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13008 /* Encode instructions of form:
13010 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13011 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13014 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13016 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13017 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13018 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13019 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13020 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13021 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13022 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13023 inst
.instruction
|= neon_logbits (size
) << 20;
13025 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13029 do_neon_dyadic_long (void)
13031 /* FIXME: Type checking for lengthening op. */
13032 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13033 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13034 neon_mixed_length (et
, et
.size
);
13038 do_neon_abal (void)
13040 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13041 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13042 neon_mixed_length (et
, et
.size
);
13046 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13048 if (inst
.operands
[2].isscalar
)
13050 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13051 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13052 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13053 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13057 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13058 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13059 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13060 neon_mixed_length (et
, et
.size
);
13065 do_neon_mac_maybe_scalar_long (void)
13067 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13071 do_neon_dyadic_wide (void)
13073 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13074 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13075 neon_mixed_length (et
, et
.size
);
13079 do_neon_dyadic_narrow (void)
13081 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13082 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13083 /* Operand sign is unimportant, and the U bit is part of the opcode,
13084 so force the operand type to integer. */
13085 et
.type
= NT_integer
;
13086 neon_mixed_length (et
, et
.size
/ 2);
13090 do_neon_mul_sat_scalar_long (void)
13092 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13096 do_neon_vmull (void)
13098 if (inst
.operands
[2].isscalar
)
13099 do_neon_mac_maybe_scalar_long ();
13102 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13103 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13104 if (et
.type
== NT_poly
)
13105 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13107 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13108 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13109 zero. Should be OK as-is. */
13110 neon_mixed_length (et
, et
.size
);
13117 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13118 struct neon_type_el et
= neon_check_type (3, rs
,
13119 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13120 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13122 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13123 _("shift out of range"));
13124 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13125 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13126 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13127 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13128 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13129 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13130 inst
.instruction
|= neon_quad (rs
) << 6;
13131 inst
.instruction
|= imm
<< 8;
13133 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13139 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13140 struct neon_type_el et
= neon_check_type (2, rs
,
13141 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13142 unsigned op
= (inst
.instruction
>> 7) & 3;
13143 /* N (width of reversed regions) is encoded as part of the bitmask. We
13144 extract it here to check the elements to be reversed are smaller.
13145 Otherwise we'd get a reserved instruction. */
13146 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13147 assert (elsize
!= 0);
13148 constraint (et
.size
>= elsize
,
13149 _("elements must be smaller than reversal region"));
13150 neon_two_same (neon_quad (rs
), 1, et
.size
);
13156 if (inst
.operands
[1].isscalar
)
13158 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13159 struct neon_type_el et
= neon_check_type (2, rs
,
13160 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13161 unsigned sizebits
= et
.size
>> 3;
13162 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13163 int logsize
= neon_logbits (et
.size
);
13164 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13166 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13169 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13170 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13171 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13172 inst
.instruction
|= LOW4 (dm
);
13173 inst
.instruction
|= HI1 (dm
) << 5;
13174 inst
.instruction
|= neon_quad (rs
) << 6;
13175 inst
.instruction
|= x
<< 17;
13176 inst
.instruction
|= sizebits
<< 16;
13178 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13182 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13183 struct neon_type_el et
= neon_check_type (2, rs
,
13184 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13185 /* Duplicate ARM register to lanes of vector. */
13186 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13189 case 8: inst
.instruction
|= 0x400000; break;
13190 case 16: inst
.instruction
|= 0x000020; break;
13191 case 32: inst
.instruction
|= 0x000000; break;
13194 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13195 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13196 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13197 inst
.instruction
|= neon_quad (rs
) << 21;
13198 /* The encoding for this instruction is identical for the ARM and Thumb
13199 variants, except for the condition field. */
13200 do_vfp_cond_or_thumb ();
13204 /* VMOV has particularly many variations. It can be one of:
13205 0. VMOV<c><q> <Qd>, <Qm>
13206 1. VMOV<c><q> <Dd>, <Dm>
13207 (Register operations, which are VORR with Rm = Rn.)
13208 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13209 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13211 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13212 (ARM register to scalar.)
13213 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13214 (Two ARM registers to vector.)
13215 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13216 (Scalar to ARM register.)
13217 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13218 (Vector to two ARM registers.)
13219 8. VMOV.F32 <Sd>, <Sm>
13220 9. VMOV.F64 <Dd>, <Dm>
13221 (VFP register moves.)
13222 10. VMOV.F32 <Sd>, #imm
13223 11. VMOV.F64 <Dd>, #imm
13224 (VFP float immediate load.)
13225 12. VMOV <Rd>, <Sm>
13226 (VFP single to ARM reg.)
13227 13. VMOV <Sd>, <Rm>
13228 (ARM reg to VFP single.)
13229 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13230 (Two ARM regs to two VFP singles.)
13231 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13232 (Two VFP singles to two ARM regs.)
13234 These cases can be disambiguated using neon_select_shape, except cases 1/9
13235 and 3/11 which depend on the operand type too.
13237 All the encoded bits are hardcoded by this function.
13239 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13240 Cases 5, 7 may be used with VFPv2 and above.
13242 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13243 can specify a type where it doesn't make sense to, and is ignored). */
13248 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13249 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13251 struct neon_type_el et
;
13252 const char *ldconst
= 0;
13256 case NS_DD
: /* case 1/9. */
13257 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13258 /* It is not an error here if no type is given. */
13260 if (et
.type
== NT_float
&& et
.size
== 64)
13262 do_vfp_nsyn_opcode ("fcpyd");
13265 /* fall through. */
13267 case NS_QQ
: /* case 0/1. */
13269 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13271 /* The architecture manual I have doesn't explicitly state which
13272 value the U bit should have for register->register moves, but
13273 the equivalent VORR instruction has U = 0, so do that. */
13274 inst
.instruction
= 0x0200110;
13275 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13276 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13277 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13278 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13279 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13280 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13281 inst
.instruction
|= neon_quad (rs
) << 6;
13283 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13287 case NS_DI
: /* case 3/11. */
13288 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13290 if (et
.type
== NT_float
&& et
.size
== 64)
13292 /* case 11 (fconstd). */
13293 ldconst
= "fconstd";
13294 goto encode_fconstd
;
13296 /* fall through. */
13298 case NS_QI
: /* case 2/3. */
13299 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13301 inst
.instruction
= 0x0800010;
13302 neon_move_immediate ();
13303 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13306 case NS_SR
: /* case 4. */
13308 unsigned bcdebits
= 0;
13309 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13310 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13311 int logsize
= neon_logbits (et
.size
);
13312 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13313 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13315 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13317 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13318 && et
.size
!= 32, _(BAD_FPU
));
13319 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13320 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13324 case 8: bcdebits
= 0x8; break;
13325 case 16: bcdebits
= 0x1; break;
13326 case 32: bcdebits
= 0x0; break;
13330 bcdebits
|= x
<< logsize
;
13332 inst
.instruction
= 0xe000b10;
13333 do_vfp_cond_or_thumb ();
13334 inst
.instruction
|= LOW4 (dn
) << 16;
13335 inst
.instruction
|= HI1 (dn
) << 7;
13336 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13337 inst
.instruction
|= (bcdebits
& 3) << 5;
13338 inst
.instruction
|= (bcdebits
>> 2) << 21;
13342 case NS_DRR
: /* case 5 (fmdrr). */
13343 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13346 inst
.instruction
= 0xc400b10;
13347 do_vfp_cond_or_thumb ();
13348 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13349 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13350 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13351 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13354 case NS_RS
: /* case 6. */
13356 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13357 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13358 unsigned logsize
= neon_logbits (et
.size
);
13359 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13360 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13361 unsigned abcdebits
= 0;
13363 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13365 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13366 && et
.size
!= 32, _(BAD_FPU
));
13367 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13368 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13372 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13373 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13374 case 32: abcdebits
= 0x00; break;
13378 abcdebits
|= x
<< logsize
;
13379 inst
.instruction
= 0xe100b10;
13380 do_vfp_cond_or_thumb ();
13381 inst
.instruction
|= LOW4 (dn
) << 16;
13382 inst
.instruction
|= HI1 (dn
) << 7;
13383 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13384 inst
.instruction
|= (abcdebits
& 3) << 5;
13385 inst
.instruction
|= (abcdebits
>> 2) << 21;
13389 case NS_RRD
: /* case 7 (fmrrd). */
13390 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13393 inst
.instruction
= 0xc500b10;
13394 do_vfp_cond_or_thumb ();
13395 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13396 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13397 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13398 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13401 case NS_FF
: /* case 8 (fcpys). */
13402 do_vfp_nsyn_opcode ("fcpys");
13405 case NS_FI
: /* case 10 (fconsts). */
13406 ldconst
= "fconsts";
13408 if (is_quarter_float (inst
.operands
[1].imm
))
13410 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13411 do_vfp_nsyn_opcode (ldconst
);
13414 first_error (_("immediate out of range"));
13417 case NS_RF
: /* case 12 (fmrs). */
13418 do_vfp_nsyn_opcode ("fmrs");
13421 case NS_FR
: /* case 13 (fmsr). */
13422 do_vfp_nsyn_opcode ("fmsr");
13425 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13426 (one of which is a list), but we have parsed four. Do some fiddling to
13427 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13429 case NS_RRFF
: /* case 14 (fmrrs). */
13430 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13431 _("VFP registers must be adjacent"));
13432 inst
.operands
[2].imm
= 2;
13433 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13434 do_vfp_nsyn_opcode ("fmrrs");
13437 case NS_FFRR
: /* case 15 (fmsrr). */
13438 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13439 _("VFP registers must be adjacent"));
13440 inst
.operands
[1] = inst
.operands
[2];
13441 inst
.operands
[2] = inst
.operands
[3];
13442 inst
.operands
[0].imm
= 2;
13443 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13444 do_vfp_nsyn_opcode ("fmsrr");
13453 do_neon_rshift_round_imm (void)
13455 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13456 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13457 int imm
= inst
.operands
[2].imm
;
13459 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13462 inst
.operands
[2].present
= 0;
13467 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13468 _("immediate out of range for shift"));
13469 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13474 do_neon_movl (void)
13476 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13477 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13478 unsigned sizebits
= et
.size
>> 3;
13479 inst
.instruction
|= sizebits
<< 19;
13480 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13486 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13487 struct neon_type_el et
= neon_check_type (2, rs
,
13488 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13489 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13490 neon_two_same (neon_quad (rs
), 1, et
.size
);
13494 do_neon_zip_uzp (void)
13496 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13497 struct neon_type_el et
= neon_check_type (2, rs
,
13498 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13499 if (rs
== NS_DD
&& et
.size
== 32)
13501 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13502 inst
.instruction
= N_MNEM_vtrn
;
13506 neon_two_same (neon_quad (rs
), 1, et
.size
);
13510 do_neon_sat_abs_neg (void)
13512 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13513 struct neon_type_el et
= neon_check_type (2, rs
,
13514 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13515 neon_two_same (neon_quad (rs
), 1, et
.size
);
13519 do_neon_pair_long (void)
13521 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13522 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13523 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13524 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13525 neon_two_same (neon_quad (rs
), 1, et
.size
);
13529 do_neon_recip_est (void)
13531 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13532 struct neon_type_el et
= neon_check_type (2, rs
,
13533 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13534 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13535 neon_two_same (neon_quad (rs
), 1, et
.size
);
13541 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13542 struct neon_type_el et
= neon_check_type (2, rs
,
13543 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13544 neon_two_same (neon_quad (rs
), 1, et
.size
);
13550 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13551 struct neon_type_el et
= neon_check_type (2, rs
,
13552 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13553 neon_two_same (neon_quad (rs
), 1, et
.size
);
13559 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13560 struct neon_type_el et
= neon_check_type (2, rs
,
13561 N_EQK
| N_INT
, N_8
| N_KEY
);
13562 neon_two_same (neon_quad (rs
), 1, et
.size
);
13568 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13569 neon_two_same (neon_quad (rs
), 1, -1);
13573 do_neon_tbl_tbx (void)
13575 unsigned listlenbits
;
13576 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13578 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13580 first_error (_("bad list length for table lookup"));
13584 listlenbits
= inst
.operands
[1].imm
- 1;
13585 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13586 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13587 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13588 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13589 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13590 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13591 inst
.instruction
|= listlenbits
<< 8;
13593 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13597 do_neon_ldm_stm (void)
13599 /* P, U and L bits are part of bitmask. */
13600 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13601 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13603 if (inst
.operands
[1].issingle
)
13605 do_vfp_nsyn_ldm_stm (is_dbmode
);
13609 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13610 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13612 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13613 _("register list must contain at least 1 and at most 16 "
13616 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13617 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13618 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13619 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13621 inst
.instruction
|= offsetbits
;
13623 do_vfp_cond_or_thumb ();
13627 do_neon_ldr_str (void)
13629 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13631 if (inst
.operands
[0].issingle
)
13634 do_vfp_nsyn_opcode ("flds");
13636 do_vfp_nsyn_opcode ("fsts");
13641 do_vfp_nsyn_opcode ("fldd");
13643 do_vfp_nsyn_opcode ("fstd");
13647 /* "interleave" version also handles non-interleaving register VLD1/VST1
13651 do_neon_ld_st_interleave (void)
13653 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13654 N_8
| N_16
| N_32
| N_64
);
13655 unsigned alignbits
= 0;
13657 /* The bits in this table go:
13658 0: register stride of one (0) or two (1)
13659 1,2: register list length, minus one (1, 2, 3, 4).
13660 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13661 We use -1 for invalid entries. */
13662 const int typetable
[] =
13664 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13665 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13666 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13667 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13671 if (et
.type
== NT_invtype
)
13674 if (inst
.operands
[1].immisalign
)
13675 switch (inst
.operands
[1].imm
>> 8)
13677 case 64: alignbits
= 1; break;
13679 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13680 goto bad_alignment
;
13684 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13685 goto bad_alignment
;
13690 first_error (_("bad alignment"));
13694 inst
.instruction
|= alignbits
<< 4;
13695 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13697 /* Bits [4:6] of the immediate in a list specifier encode register stride
13698 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13699 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13700 up the right value for "type" in a table based on this value and the given
13701 list style, then stick it back. */
13702 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13703 | (((inst
.instruction
>> 8) & 3) << 3);
13705 typebits
= typetable
[idx
];
13707 constraint (typebits
== -1, _("bad list type for instruction"));
13709 inst
.instruction
&= ~0xf00;
13710 inst
.instruction
|= typebits
<< 8;
13713 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13714 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13715 otherwise. The variable arguments are a list of pairs of legal (size, align)
13716 values, terminated with -1. */
13719 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13722 int result
= FAIL
, thissize
, thisalign
;
13724 if (!inst
.operands
[1].immisalign
)
13730 va_start (ap
, do_align
);
13734 thissize
= va_arg (ap
, int);
13735 if (thissize
== -1)
13737 thisalign
= va_arg (ap
, int);
13739 if (size
== thissize
&& align
== thisalign
)
13742 while (result
!= SUCCESS
);
13746 if (result
== SUCCESS
)
13749 first_error (_("unsupported alignment for instruction"));
13755 do_neon_ld_st_lane (void)
13757 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13758 int align_good
, do_align
= 0;
13759 int logsize
= neon_logbits (et
.size
);
13760 int align
= inst
.operands
[1].imm
>> 8;
13761 int n
= (inst
.instruction
>> 8) & 3;
13762 int max_el
= 64 / et
.size
;
13764 if (et
.type
== NT_invtype
)
13767 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13768 _("bad list length"));
13769 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13770 _("scalar index out of range"));
13771 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13773 _("stride of 2 unavailable when element size is 8"));
13777 case 0: /* VLD1 / VST1. */
13778 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13780 if (align_good
== FAIL
)
13784 unsigned alignbits
= 0;
13787 case 16: alignbits
= 0x1; break;
13788 case 32: alignbits
= 0x3; break;
13791 inst
.instruction
|= alignbits
<< 4;
13795 case 1: /* VLD2 / VST2. */
13796 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13798 if (align_good
== FAIL
)
13801 inst
.instruction
|= 1 << 4;
13804 case 2: /* VLD3 / VST3. */
13805 constraint (inst
.operands
[1].immisalign
,
13806 _("can't use alignment with this instruction"));
13809 case 3: /* VLD4 / VST4. */
13810 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13811 16, 64, 32, 64, 32, 128, -1);
13812 if (align_good
== FAIL
)
13816 unsigned alignbits
= 0;
13819 case 8: alignbits
= 0x1; break;
13820 case 16: alignbits
= 0x1; break;
13821 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13824 inst
.instruction
|= alignbits
<< 4;
13831 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13832 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13833 inst
.instruction
|= 1 << (4 + logsize
);
13835 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13836 inst
.instruction
|= logsize
<< 10;
13839 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13842 do_neon_ld_dup (void)
13844 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13845 int align_good
, do_align
= 0;
13847 if (et
.type
== NT_invtype
)
13850 switch ((inst
.instruction
>> 8) & 3)
13852 case 0: /* VLD1. */
13853 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13854 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13855 &do_align
, 16, 16, 32, 32, -1);
13856 if (align_good
== FAIL
)
13858 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13861 case 2: inst
.instruction
|= 1 << 5; break;
13862 default: first_error (_("bad list length")); return;
13864 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13867 case 1: /* VLD2. */
13868 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13869 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13870 if (align_good
== FAIL
)
13872 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13873 _("bad list length"));
13874 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13875 inst
.instruction
|= 1 << 5;
13876 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13879 case 2: /* VLD3. */
13880 constraint (inst
.operands
[1].immisalign
,
13881 _("can't use alignment with this instruction"));
13882 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13883 _("bad list length"));
13884 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13885 inst
.instruction
|= 1 << 5;
13886 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13889 case 3: /* VLD4. */
13891 int align
= inst
.operands
[1].imm
>> 8;
13892 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13893 16, 64, 32, 64, 32, 128, -1);
13894 if (align_good
== FAIL
)
13896 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13897 _("bad list length"));
13898 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13899 inst
.instruction
|= 1 << 5;
13900 if (et
.size
== 32 && align
== 128)
13901 inst
.instruction
|= 0x3 << 6;
13903 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13910 inst
.instruction
|= do_align
<< 4;
13913 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13914 apart from bits [11:4]. */
13917 do_neon_ldx_stx (void)
13919 switch (NEON_LANE (inst
.operands
[0].imm
))
13921 case NEON_INTERLEAVE_LANES
:
13922 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13923 do_neon_ld_st_interleave ();
13926 case NEON_ALL_LANES
:
13927 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13932 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13933 do_neon_ld_st_lane ();
13936 /* L bit comes from bit mask. */
13937 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13939 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13941 if (inst
.operands
[1].postind
)
13943 int postreg
= inst
.operands
[1].imm
& 0xf;
13944 constraint (!inst
.operands
[1].immisreg
,
13945 _("post-index must be a register"));
13946 constraint (postreg
== 0xd || postreg
== 0xf,
13947 _("bad register for post-index"));
13948 inst
.instruction
|= postreg
;
13950 else if (inst
.operands
[1].writeback
)
13952 inst
.instruction
|= 0xd;
13955 inst
.instruction
|= 0xf;
13958 inst
.instruction
|= 0xf9000000;
13960 inst
.instruction
|= 0xf4000000;
13963 /* Overall per-instruction processing. */
13965 /* We need to be able to fix up arbitrary expressions in some statements.
13966 This is so that we can handle symbols that are an arbitrary distance from
13967 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13968 which returns part of an address in a form which will be valid for
13969 a data instruction. We do this by pushing the expression into a symbol
13970 in the expr_section, and creating a fix for that. */
13973 fix_new_arm (fragS
* frag
,
13988 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13992 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13997 /* Mark whether the fix is to a THUMB instruction, or an ARM
13999 new_fix
->tc_fix_data
= thumb_mode
;
14002 /* Create a frg for an instruction requiring relaxation. */
14004 output_relax_insn (void)
14010 /* The size of the instruction is unknown, so tie the debug info to the
14011 start of the instruction. */
14012 dwarf2_emit_insn (0);
14014 switch (inst
.reloc
.exp
.X_op
)
14017 sym
= inst
.reloc
.exp
.X_add_symbol
;
14018 offset
= inst
.reloc
.exp
.X_add_number
;
14022 offset
= inst
.reloc
.exp
.X_add_number
;
14025 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14029 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14030 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14031 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14034 /* Write a 32-bit thumb instruction to buf. */
14036 put_thumb32_insn (char * buf
, unsigned long insn
)
14038 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14039 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14043 output_inst (const char * str
)
14049 as_bad ("%s -- `%s'", inst
.error
, str
);
14054 output_relax_insn ();
14057 if (inst
.size
== 0)
14060 to
= frag_more (inst
.size
);
14062 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14064 assert (inst
.size
== (2 * THUMB_SIZE
));
14065 put_thumb32_insn (to
, inst
.instruction
);
14067 else if (inst
.size
> INSN_SIZE
)
14069 assert (inst
.size
== (2 * INSN_SIZE
));
14070 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14071 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14074 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14076 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14077 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14078 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14081 dwarf2_emit_insn (inst
.size
);
14084 /* Tag values used in struct asm_opcode's tag field. */
14087 OT_unconditional
, /* Instruction cannot be conditionalized.
14088 The ARM condition field is still 0xE. */
14089 OT_unconditionalF
, /* Instruction cannot be conditionalized
14090 and carries 0xF in its ARM condition field. */
14091 OT_csuffix
, /* Instruction takes a conditional suffix. */
14092 OT_csuffixF
, /* Some forms of the instruction take a conditional
14093 suffix, others place 0xF where the condition field
14095 OT_cinfix3
, /* Instruction takes a conditional infix,
14096 beginning at character index 3. (In
14097 unified mode, it becomes a suffix.) */
14098 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14099 tsts, cmps, cmns, and teqs. */
14100 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14101 character index 3, even in unified mode. Used for
14102 legacy instructions where suffix and infix forms
14103 may be ambiguous. */
14104 OT_csuf_or_in3
, /* Instruction takes either a conditional
14105 suffix or an infix at character index 3. */
14106 OT_odd_infix_unc
, /* This is the unconditional variant of an
14107 instruction that takes a conditional infix
14108 at an unusual position. In unified mode,
14109 this variant will accept a suffix. */
14110 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14111 are the conditional variants of instructions that
14112 take conditional infixes in unusual positions.
14113 The infix appears at character index
14114 (tag - OT_odd_infix_0). These are not accepted
14115 in unified mode. */
14118 /* Subroutine of md_assemble, responsible for looking up the primary
14119 opcode from the mnemonic the user wrote. STR points to the
14120 beginning of the mnemonic.
14122 This is not simply a hash table lookup, because of conditional
14123 variants. Most instructions have conditional variants, which are
14124 expressed with a _conditional affix_ to the mnemonic. If we were
14125 to encode each conditional variant as a literal string in the opcode
14126 table, it would have approximately 20,000 entries.
14128 Most mnemonics take this affix as a suffix, and in unified syntax,
14129 'most' is upgraded to 'all'. However, in the divided syntax, some
14130 instructions take the affix as an infix, notably the s-variants of
14131 the arithmetic instructions. Of those instructions, all but six
14132 have the infix appear after the third character of the mnemonic.
14134 Accordingly, the algorithm for looking up primary opcodes given
14137 1. Look up the identifier in the opcode table.
14138 If we find a match, go to step U.
14140 2. Look up the last two characters of the identifier in the
14141 conditions table. If we find a match, look up the first N-2
14142 characters of the identifier in the opcode table. If we
14143 find a match, go to step CE.
14145 3. Look up the fourth and fifth characters of the identifier in
14146 the conditions table. If we find a match, extract those
14147 characters from the identifier, and look up the remaining
14148 characters in the opcode table. If we find a match, go
14153 U. Examine the tag field of the opcode structure, in case this is
14154 one of the six instructions with its conditional infix in an
14155 unusual place. If it is, the tag tells us where to find the
14156 infix; look it up in the conditions table and set inst.cond
14157 accordingly. Otherwise, this is an unconditional instruction.
14158 Again set inst.cond accordingly. Return the opcode structure.
14160 CE. Examine the tag field to make sure this is an instruction that
14161 should receive a conditional suffix. If it is not, fail.
14162 Otherwise, set inst.cond from the suffix we already looked up,
14163 and return the opcode structure.
14165 CM. Examine the tag field to make sure this is an instruction that
14166 should receive a conditional infix after the third character.
14167 If it is not, fail. Otherwise, undo the edits to the current
14168 line of input and proceed as for case CE. */
14170 static const struct asm_opcode
*
14171 opcode_lookup (char **str
)
14175 const struct asm_opcode
*opcode
;
14176 const struct asm_cond
*cond
;
14178 bfd_boolean neon_supported
;
14180 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14182 /* Scan up to the end of the mnemonic, which must end in white space,
14183 '.' (in unified mode, or for Neon instructions), or end of string. */
14184 for (base
= end
= *str
; *end
!= '\0'; end
++)
14185 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14191 /* Handle a possible width suffix and/or Neon type suffix. */
14196 /* The .w and .n suffixes are only valid if the unified syntax is in
14198 if (unified_syntax
&& end
[1] == 'w')
14200 else if (unified_syntax
&& end
[1] == 'n')
14205 inst
.vectype
.elems
= 0;
14207 *str
= end
+ offset
;
14209 if (end
[offset
] == '.')
14211 /* See if we have a Neon type suffix (possible in either unified or
14212 non-unified ARM syntax mode). */
14213 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14216 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14222 /* Look for unaffixed or special-case affixed mnemonic. */
14223 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14227 if (opcode
->tag
< OT_odd_infix_0
)
14229 inst
.cond
= COND_ALWAYS
;
14233 if (warn_on_deprecated
&& unified_syntax
)
14234 as_warn (_("conditional infixes are deprecated in unified syntax"));
14235 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14236 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14239 inst
.cond
= cond
->value
;
14243 /* Cannot have a conditional suffix on a mnemonic of less than two
14245 if (end
- base
< 3)
14248 /* Look for suffixed mnemonic. */
14250 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14251 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14252 if (opcode
&& cond
)
14255 switch (opcode
->tag
)
14257 case OT_cinfix3_legacy
:
14258 /* Ignore conditional suffixes matched on infix only mnemonics. */
14262 case OT_cinfix3_deprecated
:
14263 case OT_odd_infix_unc
:
14264 if (!unified_syntax
)
14266 /* else fall through */
14270 case OT_csuf_or_in3
:
14271 inst
.cond
= cond
->value
;
14274 case OT_unconditional
:
14275 case OT_unconditionalF
:
14278 inst
.cond
= cond
->value
;
14282 /* delayed diagnostic */
14283 inst
.error
= BAD_COND
;
14284 inst
.cond
= COND_ALWAYS
;
14293 /* Cannot have a usual-position infix on a mnemonic of less than
14294 six characters (five would be a suffix). */
14295 if (end
- base
< 6)
14298 /* Look for infixed mnemonic in the usual position. */
14300 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14304 memcpy (save
, affix
, 2);
14305 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14306 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14307 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14308 memcpy (affix
, save
, 2);
14311 && (opcode
->tag
== OT_cinfix3
14312 || opcode
->tag
== OT_cinfix3_deprecated
14313 || opcode
->tag
== OT_csuf_or_in3
14314 || opcode
->tag
== OT_cinfix3_legacy
))
14317 if (warn_on_deprecated
&& unified_syntax
14318 && (opcode
->tag
== OT_cinfix3
14319 || opcode
->tag
== OT_cinfix3_deprecated
))
14320 as_warn (_("conditional infixes are deprecated in unified syntax"));
14322 inst
.cond
= cond
->value
;
14330 md_assemble (char *str
)
14333 const struct asm_opcode
* opcode
;
14335 /* Align the previous label if needed. */
14336 if (last_label_seen
!= NULL
)
14338 symbol_set_frag (last_label_seen
, frag_now
);
14339 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14340 S_SET_SEGMENT (last_label_seen
, now_seg
);
14343 memset (&inst
, '\0', sizeof (inst
));
14344 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14346 opcode
= opcode_lookup (&p
);
14349 /* It wasn't an instruction, but it might be a register alias of
14350 the form alias .req reg, or a Neon .dn/.qn directive. */
14351 if (!create_register_alias (str
, p
)
14352 && !create_neon_reg_alias (str
, p
))
14353 as_bad (_("bad instruction `%s'"), str
);
14358 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
14359 as_warn (_("s suffix on comparison instruction is deprecated"));
14361 /* The value which unconditional instructions should have in place of the
14362 condition field. */
14363 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14367 arm_feature_set variant
;
14369 variant
= cpu_variant
;
14370 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14371 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14372 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14373 /* Check that this instruction is supported for this CPU. */
14374 if (!opcode
->tvariant
14375 || (thumb_mode
== 1
14376 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14378 as_bad (_("selected processor does not support `%s'"), str
);
14381 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14382 && opcode
->tencode
!= do_t_branch
)
14384 as_bad (_("Thumb does not support conditional execution"));
14388 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14390 /* Implicit require narrow instructions on Thumb-1. This avoids
14391 relaxation accidentally introducing Thumb-2 instructions. */
14392 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
14393 && !ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
))
14397 /* Check conditional suffixes. */
14398 if (current_it_mask
)
14401 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14402 current_it_mask
<<= 1;
14403 current_it_mask
&= 0x1f;
14404 /* The BKPT instruction is unconditional even in an IT block. */
14406 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14408 as_bad (_("incorrect condition in IT block"));
14412 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14414 as_bad (_("thumb conditional instruction not in IT block"));
14418 mapping_state (MAP_THUMB
);
14419 inst
.instruction
= opcode
->tvalue
;
14421 if (!parse_operands (p
, opcode
->operands
))
14422 opcode
->tencode ();
14424 /* Clear current_it_mask at the end of an IT block. */
14425 if (current_it_mask
== 0x10)
14426 current_it_mask
= 0;
14428 if (!(inst
.error
|| inst
.relax
))
14430 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14431 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14432 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14434 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14439 /* Something has gone badly wrong if we try to relax a fixed size
14441 assert (inst
.size_req
== 0 || !inst
.relax
);
14443 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14444 *opcode
->tvariant
);
14445 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14446 set those bits when Thumb-2 32-bit instructions are seen. ie.
14447 anything other than bl/blx and v6-M instructions.
14448 This is overly pessimistic for relaxable instructions. */
14449 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14451 && !ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
))
14452 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14455 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14459 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
14460 is_bx
= (opcode
->aencode
== do_bx
);
14462 /* Check that this instruction is supported for this CPU. */
14463 if (!(is_bx
&& fix_v4bx
)
14464 && !(opcode
->avariant
&&
14465 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
14467 as_bad (_("selected processor does not support `%s'"), str
);
14472 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14476 mapping_state (MAP_ARM
);
14477 inst
.instruction
= opcode
->avalue
;
14478 if (opcode
->tag
== OT_unconditionalF
)
14479 inst
.instruction
|= 0xF << 28;
14481 inst
.instruction
|= inst
.cond
<< 28;
14482 inst
.size
= INSN_SIZE
;
14483 if (!parse_operands (p
, opcode
->operands
))
14484 opcode
->aencode ();
14485 /* Arm mode bx is marked as both v4T and v5 because it's still required
14486 on a hypothetical non-thumb v5 core. */
14488 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14490 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14491 *opcode
->avariant
);
14495 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14502 /* Various frobbings of labels and their addresses. */
14505 arm_start_line_hook (void)
14507 last_label_seen
= NULL
;
14511 arm_frob_label (symbolS
* sym
)
14513 last_label_seen
= sym
;
14515 ARM_SET_THUMB (sym
, thumb_mode
);
14517 #if defined OBJ_COFF || defined OBJ_ELF
14518 ARM_SET_INTERWORK (sym
, support_interwork
);
14521 /* Note - do not allow local symbols (.Lxxx) to be labelled
14522 as Thumb functions. This is because these labels, whilst
14523 they exist inside Thumb code, are not the entry points for
14524 possible ARM->Thumb calls. Also, these labels can be used
14525 as part of a computed goto or switch statement. eg gcc
14526 can generate code that looks like this:
14528 ldr r2, [pc, .Laaa]
14538 The first instruction loads the address of the jump table.
14539 The second instruction converts a table index into a byte offset.
14540 The third instruction gets the jump address out of the table.
14541 The fourth instruction performs the jump.
14543 If the address stored at .Laaa is that of a symbol which has the
14544 Thumb_Func bit set, then the linker will arrange for this address
14545 to have the bottom bit set, which in turn would mean that the
14546 address computation performed by the third instruction would end
14547 up with the bottom bit set. Since the ARM is capable of unaligned
14548 word loads, the instruction would then load the incorrect address
14549 out of the jump table, and chaos would ensue. */
14550 if (label_is_thumb_function_name
14551 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14552 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14554 /* When the address of a Thumb function is taken the bottom
14555 bit of that address should be set. This will allow
14556 interworking between Arm and Thumb functions to work
14559 THUMB_SET_FUNC (sym
, 1);
14561 label_is_thumb_function_name
= FALSE
;
14564 dwarf2_emit_label (sym
);
14568 arm_data_in_code (void)
14570 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14572 *input_line_pointer
= '/';
14573 input_line_pointer
+= 5;
14574 *input_line_pointer
= 0;
14582 arm_canonicalize_symbol_name (char * name
)
14586 if (thumb_mode
&& (len
= strlen (name
)) > 5
14587 && streq (name
+ len
- 5, "/data"))
14588 *(name
+ len
- 5) = 0;
14593 /* Table of all register names defined by default. The user can
14594 define additional names with .req. Note that all register names
14595 should appear in both upper and lowercase variants. Some registers
14596 also have mixed-case names. */
14598 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14599 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14600 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14601 #define REGSET(p,t) \
14602 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14603 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14604 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14605 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14606 #define REGSETH(p,t) \
14607 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14608 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14609 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14610 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14611 #define REGSET2(p,t) \
14612 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14613 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14614 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14615 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14617 static const struct reg_entry reg_names
[] =
14619 /* ARM integer registers. */
14620 REGSET(r
, RN
), REGSET(R
, RN
),
14622 /* ATPCS synonyms. */
14623 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14624 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14625 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14627 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14628 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14629 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14631 /* Well-known aliases. */
14632 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14633 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14635 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14636 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14638 /* Coprocessor numbers. */
14639 REGSET(p
, CP
), REGSET(P
, CP
),
14641 /* Coprocessor register numbers. The "cr" variants are for backward
14643 REGSET(c
, CN
), REGSET(C
, CN
),
14644 REGSET(cr
, CN
), REGSET(CR
, CN
),
14646 /* FPA registers. */
14647 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14648 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14650 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14651 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14653 /* VFP SP registers. */
14654 REGSET(s
,VFS
), REGSET(S
,VFS
),
14655 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14657 /* VFP DP Registers. */
14658 REGSET(d
,VFD
), REGSET(D
,VFD
),
14659 /* Extra Neon DP registers. */
14660 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14662 /* Neon QP registers. */
14663 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14665 /* VFP control registers. */
14666 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14667 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14668 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
14669 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
14670 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
14671 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
14673 /* Maverick DSP coprocessor registers. */
14674 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14675 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14677 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14678 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14679 REGDEF(dspsc
,0,DSPSC
),
14681 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14682 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14683 REGDEF(DSPSC
,0,DSPSC
),
14685 /* iWMMXt data registers - p0, c0-15. */
14686 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14688 /* iWMMXt control registers - p1, c0-3. */
14689 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14690 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14691 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14692 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14694 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14695 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14696 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14697 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14698 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14700 /* XScale accumulator registers. */
14701 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14707 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14708 within psr_required_here. */
14709 static const struct asm_psr psrs
[] =
14711 /* Backward compatibility notation. Note that "all" is no longer
14712 truly all possible PSR bits. */
14713 {"all", PSR_c
| PSR_f
},
14717 /* Individual flags. */
14722 /* Combinations of flags. */
14723 {"fs", PSR_f
| PSR_s
},
14724 {"fx", PSR_f
| PSR_x
},
14725 {"fc", PSR_f
| PSR_c
},
14726 {"sf", PSR_s
| PSR_f
},
14727 {"sx", PSR_s
| PSR_x
},
14728 {"sc", PSR_s
| PSR_c
},
14729 {"xf", PSR_x
| PSR_f
},
14730 {"xs", PSR_x
| PSR_s
},
14731 {"xc", PSR_x
| PSR_c
},
14732 {"cf", PSR_c
| PSR_f
},
14733 {"cs", PSR_c
| PSR_s
},
14734 {"cx", PSR_c
| PSR_x
},
14735 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14736 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14737 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14738 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14739 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14740 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14741 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14742 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14743 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14744 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14745 {"scf", PSR_s
| PSR_c
| PSR_f
},
14746 {"scx", PSR_s
| PSR_c
| PSR_x
},
14747 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14748 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14749 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14750 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14751 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14752 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14753 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14754 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14755 {"csf", PSR_c
| PSR_s
| PSR_f
},
14756 {"csx", PSR_c
| PSR_s
| PSR_x
},
14757 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14758 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14759 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14760 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14761 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14762 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14763 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14764 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14765 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14766 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14767 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14768 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14769 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14770 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14771 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14772 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14773 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14774 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14775 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14776 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14777 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14778 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14779 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14780 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14781 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14782 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14785 /* Table of V7M psr names. */
14786 static const struct asm_psr v7m_psrs
[] =
14788 {"apsr", 0 }, {"APSR", 0 },
14789 {"iapsr", 1 }, {"IAPSR", 1 },
14790 {"eapsr", 2 }, {"EAPSR", 2 },
14791 {"psr", 3 }, {"PSR", 3 },
14792 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14793 {"ipsr", 5 }, {"IPSR", 5 },
14794 {"epsr", 6 }, {"EPSR", 6 },
14795 {"iepsr", 7 }, {"IEPSR", 7 },
14796 {"msp", 8 }, {"MSP", 8 },
14797 {"psp", 9 }, {"PSP", 9 },
14798 {"primask", 16}, {"PRIMASK", 16},
14799 {"basepri", 17}, {"BASEPRI", 17},
14800 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14801 {"faultmask", 19}, {"FAULTMASK", 19},
14802 {"control", 20}, {"CONTROL", 20}
14805 /* Table of all shift-in-operand names. */
14806 static const struct asm_shift_name shift_names
[] =
14808 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14809 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14810 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14811 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14812 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14813 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14816 /* Table of all explicit relocation names. */
14818 static struct reloc_entry reloc_names
[] =
14820 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14821 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14822 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14823 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14824 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14825 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14826 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14827 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14828 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14829 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14830 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14834 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14835 static const struct asm_cond conds
[] =
14839 {"cs", 0x2}, {"hs", 0x2},
14840 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14854 static struct asm_barrier_opt barrier_opt_names
[] =
14862 /* Table of ARM-format instructions. */
14864 /* Macros for gluing together operand strings. N.B. In all cases
14865 other than OPS0, the trailing OP_stop comes from default
14866 zero-initialization of the unspecified elements of the array. */
14867 #define OPS0() { OP_stop, }
14868 #define OPS1(a) { OP_##a, }
14869 #define OPS2(a,b) { OP_##a,OP_##b, }
14870 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14871 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14872 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14873 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14875 /* These macros abstract out the exact format of the mnemonic table and
14876 save some repeated characters. */
14878 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14879 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14880 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14881 THUMB_VARIANT, do_##ae, do_##te }
14883 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14884 a T_MNEM_xyz enumerator. */
14885 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14886 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14887 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14888 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14890 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14891 infix after the third character. */
14892 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14893 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14894 THUMB_VARIANT, do_##ae, do_##te }
14895 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14896 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14897 THUMB_VARIANT, do_##ae, do_##te }
14898 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14899 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14900 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14901 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14902 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14903 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14904 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14905 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14907 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14908 appear in the condition table. */
14909 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14910 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14911 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14913 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14914 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14915 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14916 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14917 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14918 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14919 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14920 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14921 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14922 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14923 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14924 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14925 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14926 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14927 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14928 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14929 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14930 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14931 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14932 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14934 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14935 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14936 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14937 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14939 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14940 field is still 0xE. Many of the Thumb variants can be executed
14941 conditionally, so this is checked separately. */
14942 #define TUE(mnem, op, top, nops, ops, ae, te) \
14943 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14944 THUMB_VARIANT, do_##ae, do_##te }
14946 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14947 condition code field. */
14948 #define TUF(mnem, op, top, nops, ops, ae, te) \
14949 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14950 THUMB_VARIANT, do_##ae, do_##te }
14952 /* ARM-only variants of all the above. */
14953 #define CE(mnem, op, nops, ops, ae) \
14954 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14956 #define C3(mnem, op, nops, ops, ae) \
14957 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14959 /* Legacy mnemonics that always have conditional infix after the third
14961 #define CL(mnem, op, nops, ops, ae) \
14962 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14963 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14965 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14966 #define cCE(mnem, op, nops, ops, ae) \
14967 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14969 /* Legacy coprocessor instructions where conditional infix and conditional
14970 suffix are ambiguous. For consistency this includes all FPA instructions,
14971 not just the potentially ambiguous ones. */
14972 #define cCL(mnem, op, nops, ops, ae) \
14973 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14974 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14976 /* Coprocessor, takes either a suffix or a position-3 infix
14977 (for an FPA corner case). */
14978 #define C3E(mnem, op, nops, ops, ae) \
14979 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14980 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14982 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14983 { #m1 #m2 #m3, OPS##nops ops, \
14984 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14985 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14987 #define CM(m1, m2, op, nops, ops, ae) \
14988 xCM_(m1, , m2, op, nops, ops, ae), \
14989 xCM_(m1, eq, m2, op, nops, ops, ae), \
14990 xCM_(m1, ne, m2, op, nops, ops, ae), \
14991 xCM_(m1, cs, m2, op, nops, ops, ae), \
14992 xCM_(m1, hs, m2, op, nops, ops, ae), \
14993 xCM_(m1, cc, m2, op, nops, ops, ae), \
14994 xCM_(m1, ul, m2, op, nops, ops, ae), \
14995 xCM_(m1, lo, m2, op, nops, ops, ae), \
14996 xCM_(m1, mi, m2, op, nops, ops, ae), \
14997 xCM_(m1, pl, m2, op, nops, ops, ae), \
14998 xCM_(m1, vs, m2, op, nops, ops, ae), \
14999 xCM_(m1, vc, m2, op, nops, ops, ae), \
15000 xCM_(m1, hi, m2, op, nops, ops, ae), \
15001 xCM_(m1, ls, m2, op, nops, ops, ae), \
15002 xCM_(m1, ge, m2, op, nops, ops, ae), \
15003 xCM_(m1, lt, m2, op, nops, ops, ae), \
15004 xCM_(m1, gt, m2, op, nops, ops, ae), \
15005 xCM_(m1, le, m2, op, nops, ops, ae), \
15006 xCM_(m1, al, m2, op, nops, ops, ae)
15008 #define UE(mnem, op, nops, ops, ae) \
15009 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
15011 #define UF(mnem, op, nops, ops, ae) \
15012 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
15014 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
15015 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
15016 use the same encoding function for each. */
15017 #define NUF(mnem, op, nops, ops, enc) \
15018 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
15019 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15021 /* Neon data processing, version which indirects through neon_enc_tab for
15022 the various overloaded versions of opcodes. */
15023 #define nUF(mnem, op, nops, ops, enc) \
15024 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
15025 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15027 /* Neon insn with conditional suffix for the ARM version, non-overloaded
15029 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
15030 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
15031 THUMB_VARIANT, do_##enc, do_##enc }
15033 #define NCE(mnem, op, nops, ops, enc) \
15034 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
15036 #define NCEF(mnem, op, nops, ops, enc) \
15037 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
15039 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
15040 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
15041 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
15042 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15044 #define nCE(mnem, op, nops, ops, enc) \
15045 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
15047 #define nCEF(mnem, op, nops, ops, enc) \
15048 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
15052 /* Thumb-only, unconditional. */
15053 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
15055 static const struct asm_opcode insns
[] =
15057 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
15058 #define THUMB_VARIANT &arm_ext_v4t
15059 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15060 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15061 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15062 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15063 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
15064 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
15065 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
15066 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
15067 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15068 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15069 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15070 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15071 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15072 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15073 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15074 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15076 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
15077 for setting PSR flag bits. They are obsolete in V6 and do not
15078 have Thumb equivalents. */
15079 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15080 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15081 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
15082 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15083 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15084 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
15085 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15086 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15087 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
15089 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15090 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15091 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15092 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15094 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15095 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15096 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15097 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15099 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15100 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15101 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15102 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15103 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15104 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15106 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15107 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15108 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
15109 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
15112 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
15113 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
15114 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
15116 /* Thumb-compatibility pseudo ops. */
15117 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15118 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15119 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15120 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15121 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15122 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15123 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15124 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15125 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
15126 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
15127 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
15128 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
15130 /* These may simplify to neg. */
15131 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15132 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15134 #undef THUMB_VARIANT
15135 #define THUMB_VARIANT &arm_ext_v6
15136 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
15138 /* V1 instructions with no Thumb analogue prior to V6T2. */
15139 #undef THUMB_VARIANT
15140 #define THUMB_VARIANT &arm_ext_v6t2
15141 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15142 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15143 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
15145 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15146 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15147 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15148 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15150 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15151 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15153 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15154 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15156 /* V1 instructions with no Thumb analogue at all. */
15157 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
15158 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
15160 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15161 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15162 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15163 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15164 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15165 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15166 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15167 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15170 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15171 #undef THUMB_VARIANT
15172 #define THUMB_VARIANT &arm_ext_v4t
15173 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15174 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15176 #undef THUMB_VARIANT
15177 #define THUMB_VARIANT &arm_ext_v6t2
15178 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15179 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
15181 /* Generic coprocessor instructions. */
15182 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15183 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15184 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15185 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15186 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15187 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15188 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15191 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15192 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15193 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15196 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15197 #undef THUMB_VARIANT
15198 #define THUMB_VARIANT &arm_ext_msr
15199 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15200 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15203 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15204 #undef THUMB_VARIANT
15205 #define THUMB_VARIANT &arm_ext_v6t2
15206 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15207 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15208 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15209 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15210 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15211 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15212 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15213 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15216 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15217 #undef THUMB_VARIANT
15218 #define THUMB_VARIANT &arm_ext_v4t
15219 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15220 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15221 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15222 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15223 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15224 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15227 #define ARM_VARIANT &arm_ext_v4t_5
15228 /* ARM Architecture 4T. */
15229 /* Note: bx (and blx) are required on V5, even if the processor does
15230 not support Thumb. */
15231 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15234 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15235 #undef THUMB_VARIANT
15236 #define THUMB_VARIANT &arm_ext_v5t
15237 /* Note: blx has 2 variants; the .value coded here is for
15238 BLX(2). Only this variant has conditional execution. */
15239 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15240 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15242 #undef THUMB_VARIANT
15243 #define THUMB_VARIANT &arm_ext_v6t2
15244 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15245 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15246 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15247 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15248 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15249 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15250 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15251 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15254 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15255 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15256 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15257 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15258 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15260 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15261 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15263 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15264 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15265 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15266 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15268 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15269 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15270 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15271 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15273 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15274 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15276 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15277 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15278 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15279 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15282 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15283 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15284 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15285 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15287 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15288 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15291 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15292 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15295 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15296 #undef THUMB_VARIANT
15297 #define THUMB_VARIANT &arm_ext_v6
15298 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15299 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15300 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15301 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15302 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15303 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15304 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15305 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15306 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15307 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15309 #undef THUMB_VARIANT
15310 #define THUMB_VARIANT &arm_ext_v6t2
15311 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15312 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15313 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15314 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15316 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15317 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15319 /* ARM V6 not included in V7M (eg. integer SIMD). */
15320 #undef THUMB_VARIANT
15321 #define THUMB_VARIANT &arm_ext_v6_notm
15322 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15323 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15324 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15325 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15326 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15327 TCE(qasx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15328 /* Old name for QASX. */
15329 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15330 TCE(qsax
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15331 /* Old name for QSAX. */
15332 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15333 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15334 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15335 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15336 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15337 TCE(sasx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15338 /* Old name for SASX. */
15339 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15340 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15341 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15342 TCE(shasx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15343 /* Old name for SHASX. */
15344 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15345 TCE(shsax
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15346 /* Old name for SHSAX. */
15347 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15348 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15349 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15350 TCE(ssax
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15351 /* Old name for SSAX. */
15352 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15353 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15354 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15355 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15356 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15357 TCE(uasx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15358 /* Old name for UASX. */
15359 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15360 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15361 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15362 TCE(uhasx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15363 /* Old name for UHASX. */
15364 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15365 TCE(uhsax
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15366 /* Old name for UHSAX. */
15367 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15368 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15369 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15370 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15371 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15372 TCE(uqasx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15373 /* Old name for UQASX. */
15374 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15375 TCE(uqsax
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15376 /* Old name for UQSAX. */
15377 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15378 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15379 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15380 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15381 TCE(usax
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15382 /* Old name for USAX. */
15383 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15384 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15385 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15386 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15387 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15388 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15389 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15390 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15391 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15392 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15393 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15394 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15395 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15396 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15397 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15398 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15399 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15400 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15401 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15402 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15403 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15404 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15405 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15406 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15407 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15408 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15409 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15410 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15411 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15412 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15413 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15414 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15415 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15416 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15417 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15418 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15419 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15420 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15421 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15422 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15423 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15424 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15425 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15426 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15427 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15428 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15431 #define ARM_VARIANT &arm_ext_v6k
15432 #undef THUMB_VARIANT
15433 #define THUMB_VARIANT &arm_ext_v6k
15434 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15435 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15436 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15437 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15439 #undef THUMB_VARIANT
15440 #define THUMB_VARIANT &arm_ext_v6_notm
15441 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15442 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15444 #undef THUMB_VARIANT
15445 #define THUMB_VARIANT &arm_ext_v6t2
15446 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15447 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15448 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15449 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15450 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15453 #define ARM_VARIANT &arm_ext_v6z
15454 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15457 #define ARM_VARIANT &arm_ext_v6t2
15458 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15459 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15460 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15461 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15463 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15464 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15465 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15466 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15468 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15469 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15470 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15471 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15473 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15474 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15475 /* ARM does not really have an IT instruction, so always allow it. */
15477 #define ARM_VARIANT &arm_ext_v1
15478 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15479 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15480 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15481 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15482 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15483 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15484 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15485 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15486 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15487 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15488 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15489 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15490 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15491 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15492 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15493 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
15494 TC3(rrx
, 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
15495 TC3(rrxs
, 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
15497 /* Thumb2 only instructions. */
15499 #define ARM_VARIANT NULL
15501 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15502 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15503 TCE(orn
, 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
15504 TCE(orns
, 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
15505 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15506 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15508 /* Thumb-2 hardware division instructions (R and M profiles only). */
15509 #undef THUMB_VARIANT
15510 #define THUMB_VARIANT &arm_ext_div
15511 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15512 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15514 /* ARM V6M/V7 instructions. */
15516 #define ARM_VARIANT &arm_ext_barrier
15517 #undef THUMB_VARIANT
15518 #define THUMB_VARIANT &arm_ext_barrier
15519 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15520 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15521 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15523 /* ARM V7 instructions. */
15525 #define ARM_VARIANT &arm_ext_v7
15526 #undef THUMB_VARIANT
15527 #define THUMB_VARIANT &arm_ext_v7
15528 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15529 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15532 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15533 cCE(wfs
, e200110
, 1, (RR
), rd
),
15534 cCE(rfs
, e300110
, 1, (RR
), rd
),
15535 cCE(wfc
, e400110
, 1, (RR
), rd
),
15536 cCE(rfc
, e500110
, 1, (RR
), rd
),
15538 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15539 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15540 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15541 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15543 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15544 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15545 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15546 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15548 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15549 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15550 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15551 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15552 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15553 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15554 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15555 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15556 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15557 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15558 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15559 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15561 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15562 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15563 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15564 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15565 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15566 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15567 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15568 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15569 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15570 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15571 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15572 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15574 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15575 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15576 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15577 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15578 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15579 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15580 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15581 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15582 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15583 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15584 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15585 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15587 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15588 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15589 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15590 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15591 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15592 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15593 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15594 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15595 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15596 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15597 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15598 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15600 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15601 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15602 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15603 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15604 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15605 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15606 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15607 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15608 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15609 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15610 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15611 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15613 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15614 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15615 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15616 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15617 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15618 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15619 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15620 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15621 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15622 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15623 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15624 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15626 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15627 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15628 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15629 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15630 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15631 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15632 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15633 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15634 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15635 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15636 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15637 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15639 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15640 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15641 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15642 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15643 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15644 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15645 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15646 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15647 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15648 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15649 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15650 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15652 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15653 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15654 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15655 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15656 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15657 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15658 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15659 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15660 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15661 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15662 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15663 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15665 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15666 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15667 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15668 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15669 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15670 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15671 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15672 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15673 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15674 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15675 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15676 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15678 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15679 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15680 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15681 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15682 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15683 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15684 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15685 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15686 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15687 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15688 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15689 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15691 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15692 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15693 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15694 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15695 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15696 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15697 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15698 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15699 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15700 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15701 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15702 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15704 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15705 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15706 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15707 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15708 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15709 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15710 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15711 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15712 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15713 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15714 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15715 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15717 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15718 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15719 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15720 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15721 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15722 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15723 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15724 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15725 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15726 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15727 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15728 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15730 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15731 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15732 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15733 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15734 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15735 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15736 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15737 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15738 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15739 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15740 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15741 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15743 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15744 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15745 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15746 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15747 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15748 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15749 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15750 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15751 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15752 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15753 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15754 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15756 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15757 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15758 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15759 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15760 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15761 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15762 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15763 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15764 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15765 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15766 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15767 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15769 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15770 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15771 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15772 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15773 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15774 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15775 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15776 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15777 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15778 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15779 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15780 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15782 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15783 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15784 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15785 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15786 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15787 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15788 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15789 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15790 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15791 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15792 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15793 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15795 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15796 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15797 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15798 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15799 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15800 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15801 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15802 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15803 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15804 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15805 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15806 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15808 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15809 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15810 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15811 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15812 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15813 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15814 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15815 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15816 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15817 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15818 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15819 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15821 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15822 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15823 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15824 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15825 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15826 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15827 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15828 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15829 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15830 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15831 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15832 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15834 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15835 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15836 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15837 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15838 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15839 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15840 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15841 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15842 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15843 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15844 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15845 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15847 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15848 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15849 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15850 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15851 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15852 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15853 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15854 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15855 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15856 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15857 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15858 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15860 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15861 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15862 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15863 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15864 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15865 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15866 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15867 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15868 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15869 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15870 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15871 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15873 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15874 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15875 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15876 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15877 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15878 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15879 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15880 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15881 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15882 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15883 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15884 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15886 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15887 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15888 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15889 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15890 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15891 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15892 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15893 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15894 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15895 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15896 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15897 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15899 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15900 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15901 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15902 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15903 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15904 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15905 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15906 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15907 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15908 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15909 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15910 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15912 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15913 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15914 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15915 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15916 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15917 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15918 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15919 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15920 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15921 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15922 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15923 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15925 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15926 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15927 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15928 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15930 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15931 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15932 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15933 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15934 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15935 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15936 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15937 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15938 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15939 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15940 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15941 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15943 /* The implementation of the FIX instruction is broken on some
15944 assemblers, in that it accepts a precision specifier as well as a
15945 rounding specifier, despite the fact that this is meaningless.
15946 To be more compatible, we accept it as well, though of course it
15947 does not set any bits. */
15948 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15949 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15950 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15951 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15952 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15953 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15954 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15955 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15956 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15957 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15958 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15959 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15960 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15962 /* Instructions that were new with the real FPA, call them V2. */
15964 #define ARM_VARIANT &fpu_fpa_ext_v2
15965 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15966 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15967 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15968 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15969 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15970 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15973 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15974 /* Moves and type conversions. */
15975 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15976 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15977 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15978 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15979 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15980 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15981 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15982 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15983 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15984 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15985 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15986 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15988 /* Memory operations. */
15989 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15990 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15991 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15992 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15993 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15994 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15995 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15996 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15997 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15998 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15999 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16000 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16001 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16002 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16003 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16004 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16005 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16006 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16008 /* Monadic operations. */
16009 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16010 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16011 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16013 /* Dyadic operations. */
16014 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16015 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16016 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16017 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16018 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16019 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16020 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16021 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16022 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16025 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16026 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
16027 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16028 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
16031 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
16032 /* Moves and type conversions. */
16033 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16034 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16035 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16036 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
16037 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
16038 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
16039 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
16040 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16041 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16042 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16043 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16044 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16045 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16047 /* Memory operations. */
16048 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
16049 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
16050 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16051 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16052 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16053 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16054 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16055 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16056 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16057 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16059 /* Monadic operations. */
16060 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16061 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16062 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16064 /* Dyadic operations. */
16065 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16066 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16067 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16068 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16069 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16070 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16071 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16072 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16073 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16076 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16077 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
16078 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16079 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
16082 #define ARM_VARIANT &fpu_vfp_ext_v2
16083 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
16084 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
16085 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
16086 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
16088 /* Instructions which may belong to either the Neon or VFP instruction sets.
16089 Individual encoder functions perform additional architecture checks. */
16091 #define ARM_VARIANT &fpu_vfp_ext_v1xd
16092 #undef THUMB_VARIANT
16093 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
16094 /* These mnemonics are unique to VFP. */
16095 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
16096 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
16097 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16098 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16099 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16100 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16101 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16102 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
16103 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
16104 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
16106 /* Mnemonics shared by Neon and VFP. */
16107 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
16108 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16109 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16111 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16112 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16114 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16115 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16117 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16118 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16119 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16120 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16121 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16122 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16123 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16124 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16126 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
16127 nCEF(vcvtb
, vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
16128 nCEF(vcvtt
, vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
16131 /* NOTE: All VMOV encoding is special-cased! */
16132 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
16133 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
16135 #undef THUMB_VARIANT
16136 #define THUMB_VARIANT &fpu_neon_ext_v1
16138 #define ARM_VARIANT &fpu_neon_ext_v1
16139 /* Data processing with three registers of the same length. */
16140 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
16141 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
16142 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
16143 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16144 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16145 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16146 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16147 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16148 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16149 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
16150 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16151 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16152 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16153 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16154 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16155 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16156 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16157 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16158 /* If not immediate, fall back to neon_dyadic_i64_su.
16159 shl_imm should accept I8 I16 I32 I64,
16160 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
16161 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
16162 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
16163 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
16164 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
16165 /* Logic ops, types optional & ignored. */
16166 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
16167 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
16168 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
16169 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
16170 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
16171 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
16172 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
16173 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
16174 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
16175 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
16176 /* Bitfield ops, untyped. */
16177 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16178 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16179 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16180 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16181 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16182 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16183 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
16184 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16185 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16186 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16187 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16188 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16189 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16190 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
16191 back to neon_dyadic_if_su. */
16192 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16193 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16194 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16195 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16196 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16197 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16198 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16199 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16200 /* Comparison. Type I8 I16 I32 F32. */
16201 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
16202 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
16203 /* As above, D registers only. */
16204 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16205 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16206 /* Int and float variants, signedness unimportant. */
16207 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16208 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16209 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
16210 /* Add/sub take types I8 I16 I32 I64 F32. */
16211 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16212 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16213 /* vtst takes sizes 8, 16, 32. */
16214 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
16215 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
16216 /* VMUL takes I8 I16 I32 F32 P8. */
16217 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
16218 /* VQD{R}MULH takes S16 S32. */
16219 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16220 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16221 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16222 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16223 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16224 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16225 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16226 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16227 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16228 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16229 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16230 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16231 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16232 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16233 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16234 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16236 /* Two address, int/float. Types S8 S16 S32 F32. */
16237 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16238 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16240 /* Data processing with two registers and a shift amount. */
16241 /* Right shifts, and variants with rounding.
16242 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16243 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16244 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16245 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16246 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16247 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16248 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16249 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16250 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16251 /* Shift and insert. Sizes accepted 8 16 32 64. */
16252 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16253 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16254 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16255 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16256 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16257 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16258 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16259 /* Right shift immediate, saturating & narrowing, with rounding variants.
16260 Types accepted S16 S32 S64 U16 U32 U64. */
16261 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16262 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16263 /* As above, unsigned. Types accepted S16 S32 S64. */
16264 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16265 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16266 /* Right shift narrowing. Types accepted I16 I32 I64. */
16267 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16268 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16269 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16270 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16271 /* CVT with optional immediate for fixed-point variant. */
16272 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16274 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16275 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16277 /* Data processing, three registers of different lengths. */
16278 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16279 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16280 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16281 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16282 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16283 /* If not scalar, fall back to neon_dyadic_long.
16284 Vector types as above, scalar types S16 S32 U16 U32. */
16285 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16286 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16287 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16288 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16289 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16290 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16291 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16292 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16293 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16294 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16295 /* Saturating doubling multiplies. Types S16 S32. */
16296 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16297 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16298 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16299 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16300 S16 S32 U16 U32. */
16301 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16303 /* Extract. Size 8. */
16304 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16305 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16307 /* Two registers, miscellaneous. */
16308 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16309 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16310 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16311 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16312 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16313 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16314 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16315 /* Vector replicate. Sizes 8 16 32. */
16316 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16317 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16318 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16319 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16320 /* VMOVN. Types I16 I32 I64. */
16321 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16322 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16323 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16324 /* VQMOVUN. Types S16 S32 S64. */
16325 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16326 /* VZIP / VUZP. Sizes 8 16 32. */
16327 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16328 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16329 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16330 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16331 /* VQABS / VQNEG. Types S8 S16 S32. */
16332 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16333 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16334 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16335 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16336 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16337 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16338 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16339 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16340 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16341 /* Reciprocal estimates. Types U32 F32. */
16342 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16343 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16344 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16345 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16346 /* VCLS. Types S8 S16 S32. */
16347 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16348 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16349 /* VCLZ. Types I8 I16 I32. */
16350 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16351 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16352 /* VCNT. Size 8. */
16353 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16354 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16355 /* Two address, untyped. */
16356 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16357 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16358 /* VTRN. Sizes 8 16 32. */
16359 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16360 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16362 /* Table lookup. Size 8. */
16363 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16364 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16366 #undef THUMB_VARIANT
16367 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16369 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16370 /* Neon element/structure load/store. */
16371 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16372 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16373 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16374 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16375 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16376 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16377 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16378 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16380 #undef THUMB_VARIANT
16381 #define THUMB_VARIANT &fpu_vfp_ext_v3
16383 #define ARM_VARIANT &fpu_vfp_ext_v3
16384 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16385 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16386 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16387 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16388 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16389 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16390 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16391 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16392 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16393 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16394 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16395 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16396 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16397 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16398 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16399 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16400 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16401 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16403 #undef THUMB_VARIANT
16405 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16406 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16407 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16408 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16409 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16410 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16411 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16412 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16413 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16416 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16417 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16418 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16419 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16420 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16421 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16422 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16423 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16424 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16425 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16426 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16427 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16428 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16429 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16430 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16431 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16432 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16433 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16434 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16435 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16436 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16437 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16438 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16439 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16440 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16441 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16442 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16443 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16444 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16445 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16446 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16447 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16448 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16449 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16450 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16451 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16452 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16453 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16454 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16455 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16456 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16457 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16458 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16459 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16460 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16461 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16462 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16463 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16464 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16465 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16466 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16467 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16468 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16469 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16470 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16471 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16472 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16473 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16474 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16475 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16476 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16477 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16478 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16479 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16480 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16481 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16482 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16483 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16484 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16485 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16486 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16487 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16488 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16489 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16490 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16491 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16492 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16493 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16494 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16495 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16496 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16497 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16498 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16499 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16500 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16501 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16502 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16503 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16504 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16505 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16506 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16507 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16508 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16509 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16510 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16511 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16512 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16513 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16514 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16515 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16516 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16517 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16518 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16519 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16520 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16521 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16522 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16523 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16524 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16525 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16526 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16527 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16528 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16529 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16530 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16531 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16532 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16533 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16534 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16535 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16536 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16537 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16538 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16539 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16540 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16541 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16542 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16543 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16544 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16545 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16546 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16547 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16548 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16549 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16550 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16551 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16552 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16553 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16554 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16555 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16556 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16557 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16558 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16559 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16560 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16561 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16562 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16563 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16564 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16565 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16566 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16567 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16568 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16569 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16570 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16571 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16572 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16573 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16574 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16575 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16576 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16577 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16578 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16581 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16582 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16583 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16584 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16585 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16586 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16587 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16588 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16589 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16590 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16591 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16592 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16593 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16594 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16595 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16596 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16597 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16598 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16599 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16600 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16601 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16602 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16603 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16604 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16605 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16606 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16607 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16608 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16609 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16610 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16611 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16612 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16613 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16614 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16615 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16616 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16617 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16618 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16619 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16620 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16621 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16622 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16623 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16624 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16625 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16626 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16627 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16628 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16629 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16630 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16631 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16632 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16633 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16634 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16635 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16636 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16637 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16638 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16641 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16642 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16643 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16644 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16645 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16646 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16647 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16648 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16649 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16650 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16651 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16652 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16653 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16654 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16655 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16656 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16657 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16658 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16659 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16660 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16661 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16662 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16663 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16664 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16665 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16666 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16667 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16668 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16669 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16670 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16671 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16672 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16673 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16674 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16675 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16676 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16677 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16678 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16679 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16680 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16681 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16682 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16683 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16684 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16685 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16686 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16687 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16688 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16689 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16690 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16691 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16692 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16693 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16694 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16695 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16696 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16697 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16698 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16699 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16700 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16701 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16702 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16703 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16704 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16705 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16706 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16707 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16708 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16709 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16710 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16711 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16712 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16713 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16714 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16715 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16716 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16717 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16720 #undef THUMB_VARIANT
16747 /* MD interface: bits in the object file. */
16749 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16750 for use in the a.out file, and stores them in the array pointed to by buf.
16751 This knows about the endian-ness of the target machine and does
16752 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16753 2 (short) and 4 (long) Floating numbers are put out as a series of
16754 LITTLENUMS (shorts, here at least). */
16757 md_number_to_chars (char * buf
, valueT val
, int n
)
16759 if (target_big_endian
)
16760 number_to_chars_bigendian (buf
, val
, n
);
16762 number_to_chars_littleendian (buf
, val
, n
);
16766 md_chars_to_number (char * buf
, int n
)
16769 unsigned char * where
= (unsigned char *) buf
;
16771 if (target_big_endian
)
16776 result
|= (*where
++ & 255);
16784 result
|= (where
[n
] & 255);
16791 /* MD interface: Sections. */
16793 /* Estimate the size of a frag before relaxing. Assume everything fits in
16797 md_estimate_size_before_relax (fragS
* fragp
,
16798 segT segtype ATTRIBUTE_UNUSED
)
16804 /* Convert a machine dependent frag. */
16807 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16809 unsigned long insn
;
16810 unsigned long old_op
;
16818 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16820 old_op
= bfd_get_16(abfd
, buf
);
16821 if (fragp
->fr_symbol
)
16823 exp
.X_op
= O_symbol
;
16824 exp
.X_add_symbol
= fragp
->fr_symbol
;
16828 exp
.X_op
= O_constant
;
16830 exp
.X_add_number
= fragp
->fr_offset
;
16831 opcode
= fragp
->fr_subtype
;
16834 case T_MNEM_ldr_pc
:
16835 case T_MNEM_ldr_pc2
:
16836 case T_MNEM_ldr_sp
:
16837 case T_MNEM_str_sp
:
16844 if (fragp
->fr_var
== 4)
16846 insn
= THUMB_OP32 (opcode
);
16847 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16849 insn
|= (old_op
& 0x700) << 4;
16853 insn
|= (old_op
& 7) << 12;
16854 insn
|= (old_op
& 0x38) << 13;
16856 insn
|= 0x00000c00;
16857 put_thumb32_insn (buf
, insn
);
16858 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16862 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16864 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16867 if (fragp
->fr_var
== 4)
16869 insn
= THUMB_OP32 (opcode
);
16870 insn
|= (old_op
& 0xf0) << 4;
16871 put_thumb32_insn (buf
, insn
);
16872 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16876 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16877 exp
.X_add_number
-= 4;
16885 if (fragp
->fr_var
== 4)
16887 int r0off
= (opcode
== T_MNEM_mov
16888 || opcode
== T_MNEM_movs
) ? 0 : 8;
16889 insn
= THUMB_OP32 (opcode
);
16890 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16891 insn
|= (old_op
& 0x700) << r0off
;
16892 put_thumb32_insn (buf
, insn
);
16893 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16897 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16902 if (fragp
->fr_var
== 4)
16904 insn
= THUMB_OP32(opcode
);
16905 put_thumb32_insn (buf
, insn
);
16906 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16909 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16913 if (fragp
->fr_var
== 4)
16915 insn
= THUMB_OP32(opcode
);
16916 insn
|= (old_op
& 0xf00) << 14;
16917 put_thumb32_insn (buf
, insn
);
16918 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16921 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16924 case T_MNEM_add_sp
:
16925 case T_MNEM_add_pc
:
16926 case T_MNEM_inc_sp
:
16927 case T_MNEM_dec_sp
:
16928 if (fragp
->fr_var
== 4)
16930 /* ??? Choose between add and addw. */
16931 insn
= THUMB_OP32 (opcode
);
16932 insn
|= (old_op
& 0xf0) << 4;
16933 put_thumb32_insn (buf
, insn
);
16934 if (opcode
== T_MNEM_add_pc
)
16935 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16937 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16940 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16948 if (fragp
->fr_var
== 4)
16950 insn
= THUMB_OP32 (opcode
);
16951 insn
|= (old_op
& 0xf0) << 4;
16952 insn
|= (old_op
& 0xf) << 16;
16953 put_thumb32_insn (buf
, insn
);
16954 if (insn
& (1 << 20))
16955 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16957 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16960 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16966 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16968 fixp
->fx_file
= fragp
->fr_file
;
16969 fixp
->fx_line
= fragp
->fr_line
;
16970 fragp
->fr_fix
+= fragp
->fr_var
;
16973 /* Return the size of a relaxable immediate operand instruction.
16974 SHIFT and SIZE specify the form of the allowable immediate. */
16976 relax_immediate (fragS
*fragp
, int size
, int shift
)
16982 /* ??? Should be able to do better than this. */
16983 if (fragp
->fr_symbol
)
16986 low
= (1 << shift
) - 1;
16987 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16988 offset
= fragp
->fr_offset
;
16989 /* Force misaligned offsets to 32-bit variant. */
16992 if (offset
& ~mask
)
16997 /* Get the address of a symbol during relaxation. */
16999 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
17005 sym
= fragp
->fr_symbol
;
17006 sym_frag
= symbol_get_frag (sym
);
17007 know (S_GET_SEGMENT (sym
) != absolute_section
17008 || sym_frag
== &zero_address_frag
);
17009 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
17011 /* If frag has yet to be reached on this pass, assume it will
17012 move by STRETCH just as we did. If this is not so, it will
17013 be because some frag between grows, and that will force
17017 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17021 /* Adjust stretch for any alignment frag. Note that if have
17022 been expanding the earlier code, the symbol may be
17023 defined in what appears to be an earlier frag. FIXME:
17024 This doesn't handle the fr_subtype field, which specifies
17025 a maximum number of bytes to skip when doing an
17027 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17029 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17032 stretch
= - ((- stretch
)
17033 & ~ ((1 << (int) f
->fr_offset
) - 1));
17035 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17047 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
17050 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
17055 /* Assume worst case for symbols not known to be in the same section. */
17056 if (!S_IS_DEFINED (fragp
->fr_symbol
)
17057 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
17060 val
= relaxed_symbol_addr (fragp
, stretch
);
17061 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17062 addr
= (addr
+ 4) & ~3;
17063 /* Force misaligned targets to 32-bit variant. */
17067 if (val
< 0 || val
> 1020)
17072 /* Return the size of a relaxable add/sub immediate instruction. */
17074 relax_addsub (fragS
*fragp
, asection
*sec
)
17079 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17080 op
= bfd_get_16(sec
->owner
, buf
);
17081 if ((op
& 0xf) == ((op
>> 4) & 0xf))
17082 return relax_immediate (fragp
, 8, 0);
17084 return relax_immediate (fragp
, 3, 0);
17088 /* Return the size of a relaxable branch instruction. BITS is the
17089 size of the offset field in the narrow instruction. */
17092 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
17098 /* Assume worst case for symbols not known to be in the same section. */
17099 if (!S_IS_DEFINED (fragp
->fr_symbol
)
17100 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
17103 val
= relaxed_symbol_addr (fragp
, stretch
);
17104 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17107 /* Offset is a signed value *2 */
17109 if (val
>= limit
|| val
< -limit
)
17115 /* Relax a machine dependent frag. This returns the amount by which
17116 the current size of the frag should change. */
17119 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17124 oldsize
= fragp
->fr_var
;
17125 switch (fragp
->fr_subtype
)
17127 case T_MNEM_ldr_pc2
:
17128 newsize
= relax_adr (fragp
, sec
, stretch
);
17130 case T_MNEM_ldr_pc
:
17131 case T_MNEM_ldr_sp
:
17132 case T_MNEM_str_sp
:
17133 newsize
= relax_immediate (fragp
, 8, 2);
17137 newsize
= relax_immediate (fragp
, 5, 2);
17141 newsize
= relax_immediate (fragp
, 5, 1);
17145 newsize
= relax_immediate (fragp
, 5, 0);
17148 newsize
= relax_adr (fragp
, sec
, stretch
);
17154 newsize
= relax_immediate (fragp
, 8, 0);
17157 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
17160 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
17162 case T_MNEM_add_sp
:
17163 case T_MNEM_add_pc
:
17164 newsize
= relax_immediate (fragp
, 8, 2);
17166 case T_MNEM_inc_sp
:
17167 case T_MNEM_dec_sp
:
17168 newsize
= relax_immediate (fragp
, 7, 2);
17174 newsize
= relax_addsub (fragp
, sec
);
17180 fragp
->fr_var
= newsize
;
17181 /* Freeze wide instructions that are at or before the same location as
17182 in the previous pass. This avoids infinite loops.
17183 Don't freeze them unconditionally because targets may be artificially
17184 misaligned by the expansion of preceding frags. */
17185 if (stretch
<= 0 && newsize
> 2)
17187 md_convert_frag (sec
->owner
, sec
, fragp
);
17191 return newsize
- oldsize
;
17194 /* Round up a section size to the appropriate boundary. */
17197 md_section_align (segT segment ATTRIBUTE_UNUSED
,
17200 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
17201 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
17203 /* For a.out, force the section size to be aligned. If we don't do
17204 this, BFD will align it for us, but it will not write out the
17205 final bytes of the section. This may be a bug in BFD, but it is
17206 easier to fix it here since that is how the other a.out targets
17210 align
= bfd_get_section_alignment (stdoutput
, segment
);
17211 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
17218 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17219 of an rs_align_code fragment. */
17222 arm_handle_align (fragS
* fragP
)
17224 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17225 static char const thumb_noop
[2] = { 0xc0, 0x46 };
17226 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17227 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
17229 int bytes
, fix
, noop_size
;
17233 if (fragP
->fr_type
!= rs_align_code
)
17236 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17237 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17240 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17241 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17243 if (fragP
->tc_frag_data
)
17245 if (target_big_endian
)
17246 noop
= thumb_bigend_noop
;
17249 noop_size
= sizeof (thumb_noop
);
17253 if (target_big_endian
)
17254 noop
= arm_bigend_noop
;
17257 noop_size
= sizeof (arm_noop
);
17260 if (bytes
& (noop_size
- 1))
17262 fix
= bytes
& (noop_size
- 1);
17263 memset (p
, 0, fix
);
17268 while (bytes
>= noop_size
)
17270 memcpy (p
, noop
, noop_size
);
17272 bytes
-= noop_size
;
17276 fragP
->fr_fix
+= fix
;
17277 fragP
->fr_var
= noop_size
;
17280 /* Called from md_do_align. Used to create an alignment
17281 frag in a code section. */
17284 arm_frag_align_code (int n
, int max
)
17288 /* We assume that there will never be a requirement
17289 to support alignments greater than 32 bytes. */
17290 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17291 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17293 p
= frag_var (rs_align_code
,
17294 MAX_MEM_FOR_RS_ALIGN_CODE
,
17296 (relax_substateT
) max
,
17303 /* Perform target specific initialisation of a frag. */
17306 arm_init_frag (fragS
* fragP
)
17308 /* Record whether this frag is in an ARM or a THUMB area. */
17309 fragP
->tc_frag_data
= thumb_mode
;
17313 /* When we change sections we need to issue a new mapping symbol. */
17316 arm_elf_change_section (void)
17319 segment_info_type
*seginfo
;
17321 /* Link an unlinked unwind index table section to the .text section. */
17322 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17323 && elf_linked_to_section (now_seg
) == NULL
)
17324 elf_linked_to_section (now_seg
) = text_section
;
17326 if (!SEG_NORMAL (now_seg
))
17329 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17331 /* We can ignore sections that only contain debug info. */
17332 if ((flags
& SEC_ALLOC
) == 0)
17335 seginfo
= seg_info (now_seg
);
17336 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17337 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17341 arm_elf_section_type (const char * str
, size_t len
)
17343 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17344 return SHT_ARM_EXIDX
;
17349 /* Code to deal with unwinding tables. */
17351 static void add_unwind_adjustsp (offsetT
);
17353 /* Generate any deferred unwind frame offset. */
17356 flush_pending_unwind (void)
17360 offset
= unwind
.pending_offset
;
17361 unwind
.pending_offset
= 0;
17363 add_unwind_adjustsp (offset
);
17366 /* Add an opcode to this list for this function. Two-byte opcodes should
17367 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17371 add_unwind_opcode (valueT op
, int length
)
17373 /* Add any deferred stack adjustment. */
17374 if (unwind
.pending_offset
)
17375 flush_pending_unwind ();
17377 unwind
.sp_restored
= 0;
17379 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17381 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17382 if (unwind
.opcodes
)
17383 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17384 unwind
.opcode_alloc
);
17386 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17391 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17393 unwind
.opcode_count
++;
17397 /* Add unwind opcodes to adjust the stack pointer. */
17400 add_unwind_adjustsp (offsetT offset
)
17404 if (offset
> 0x200)
17406 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17411 /* Long form: 0xb2, uleb128. */
17412 /* This might not fit in a word so add the individual bytes,
17413 remembering the list is built in reverse order. */
17414 o
= (valueT
) ((offset
- 0x204) >> 2);
17416 add_unwind_opcode (0, 1);
17418 /* Calculate the uleb128 encoding of the offset. */
17422 bytes
[n
] = o
& 0x7f;
17428 /* Add the insn. */
17430 add_unwind_opcode (bytes
[n
- 1], 1);
17431 add_unwind_opcode (0xb2, 1);
17433 else if (offset
> 0x100)
17435 /* Two short opcodes. */
17436 add_unwind_opcode (0x3f, 1);
17437 op
= (offset
- 0x104) >> 2;
17438 add_unwind_opcode (op
, 1);
17440 else if (offset
> 0)
17442 /* Short opcode. */
17443 op
= (offset
- 4) >> 2;
17444 add_unwind_opcode (op
, 1);
17446 else if (offset
< 0)
17449 while (offset
> 0x100)
17451 add_unwind_opcode (0x7f, 1);
17454 op
= ((offset
- 4) >> 2) | 0x40;
17455 add_unwind_opcode (op
, 1);
17459 /* Finish the list of unwind opcodes for this function. */
17461 finish_unwind_opcodes (void)
17465 if (unwind
.fp_used
)
17467 /* Adjust sp as necessary. */
17468 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17469 flush_pending_unwind ();
17471 /* After restoring sp from the frame pointer. */
17472 op
= 0x90 | unwind
.fp_reg
;
17473 add_unwind_opcode (op
, 1);
17476 flush_pending_unwind ();
17480 /* Start an exception table entry. If idx is nonzero this is an index table
17484 start_unwind_section (const segT text_seg
, int idx
)
17486 const char * text_name
;
17487 const char * prefix
;
17488 const char * prefix_once
;
17489 const char * group_name
;
17493 size_t sec_name_len
;
17500 prefix
= ELF_STRING_ARM_unwind
;
17501 prefix_once
= ELF_STRING_ARM_unwind_once
;
17502 type
= SHT_ARM_EXIDX
;
17506 prefix
= ELF_STRING_ARM_unwind_info
;
17507 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17508 type
= SHT_PROGBITS
;
17511 text_name
= segment_name (text_seg
);
17512 if (streq (text_name
, ".text"))
17515 if (strncmp (text_name
, ".gnu.linkonce.t.",
17516 strlen (".gnu.linkonce.t.")) == 0)
17518 prefix
= prefix_once
;
17519 text_name
+= strlen (".gnu.linkonce.t.");
17522 prefix_len
= strlen (prefix
);
17523 text_len
= strlen (text_name
);
17524 sec_name_len
= prefix_len
+ text_len
;
17525 sec_name
= xmalloc (sec_name_len
+ 1);
17526 memcpy (sec_name
, prefix
, prefix_len
);
17527 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17528 sec_name
[prefix_len
+ text_len
] = '\0';
17534 /* Handle COMDAT group. */
17535 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17537 group_name
= elf_group_name (text_seg
);
17538 if (group_name
== NULL
)
17540 as_bad (_("Group section `%s' has no group signature"),
17541 segment_name (text_seg
));
17542 ignore_rest_of_line ();
17545 flags
|= SHF_GROUP
;
17549 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17551 /* Set the section link for index tables. */
17553 elf_linked_to_section (now_seg
) = text_seg
;
17557 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17558 personality routine data. Returns zero, or the index table value for
17559 and inline entry. */
17562 create_unwind_entry (int have_data
)
17567 /* The current word of data. */
17569 /* The number of bytes left in this word. */
17572 finish_unwind_opcodes ();
17574 /* Remember the current text section. */
17575 unwind
.saved_seg
= now_seg
;
17576 unwind
.saved_subseg
= now_subseg
;
17578 start_unwind_section (now_seg
, 0);
17580 if (unwind
.personality_routine
== NULL
)
17582 if (unwind
.personality_index
== -2)
17585 as_bad (_("handlerdata in cantunwind frame"));
17586 return 1; /* EXIDX_CANTUNWIND. */
17589 /* Use a default personality routine if none is specified. */
17590 if (unwind
.personality_index
== -1)
17592 if (unwind
.opcode_count
> 3)
17593 unwind
.personality_index
= 1;
17595 unwind
.personality_index
= 0;
17598 /* Space for the personality routine entry. */
17599 if (unwind
.personality_index
== 0)
17601 if (unwind
.opcode_count
> 3)
17602 as_bad (_("too many unwind opcodes for personality routine 0"));
17606 /* All the data is inline in the index table. */
17609 while (unwind
.opcode_count
> 0)
17611 unwind
.opcode_count
--;
17612 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17616 /* Pad with "finish" opcodes. */
17618 data
= (data
<< 8) | 0xb0;
17625 /* We get two opcodes "free" in the first word. */
17626 size
= unwind
.opcode_count
- 2;
17629 /* An extra byte is required for the opcode count. */
17630 size
= unwind
.opcode_count
+ 1;
17632 size
= (size
+ 3) >> 2;
17634 as_bad (_("too many unwind opcodes"));
17636 frag_align (2, 0, 0);
17637 record_alignment (now_seg
, 2);
17638 unwind
.table_entry
= expr_build_dot ();
17640 /* Allocate the table entry. */
17641 ptr
= frag_more ((size
<< 2) + 4);
17642 where
= frag_now_fix () - ((size
<< 2) + 4);
17644 switch (unwind
.personality_index
)
17647 /* ??? Should this be a PLT generating relocation? */
17648 /* Custom personality routine. */
17649 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17650 BFD_RELOC_ARM_PREL31
);
17655 /* Set the first byte to the number of additional words. */
17660 /* ABI defined personality routines. */
17662 /* Three opcodes bytes are packed into the first word. */
17669 /* The size and first two opcode bytes go in the first word. */
17670 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17675 /* Should never happen. */
17679 /* Pack the opcodes into words (MSB first), reversing the list at the same
17681 while (unwind
.opcode_count
> 0)
17685 md_number_to_chars (ptr
, data
, 4);
17690 unwind
.opcode_count
--;
17692 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17695 /* Finish off the last word. */
17698 /* Pad with "finish" opcodes. */
17700 data
= (data
<< 8) | 0xb0;
17702 md_number_to_chars (ptr
, data
, 4);
17707 /* Add an empty descriptor if there is no user-specified data. */
17708 ptr
= frag_more (4);
17709 md_number_to_chars (ptr
, 0, 4);
17716 /* Initialize the DWARF-2 unwind information for this procedure. */
17719 tc_arm_frame_initial_instructions (void)
17721 cfi_add_CFA_def_cfa (REG_SP
, 0);
17723 #endif /* OBJ_ELF */
17725 /* Convert REGNAME to a DWARF-2 register number. */
17728 tc_arm_regname_to_dw2regnum (char *regname
)
17730 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17740 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17744 expr
.X_op
= O_secrel
;
17745 expr
.X_add_symbol
= symbol
;
17746 expr
.X_add_number
= 0;
17747 emit_expr (&expr
, size
);
17751 /* MD interface: Symbol and relocation handling. */
17753 /* Return the address within the segment that a PC-relative fixup is
17754 relative to. For ARM, PC-relative fixups applied to instructions
17755 are generally relative to the location of the fixup plus 8 bytes.
17756 Thumb branches are offset by 4, and Thumb loads relative to PC
17757 require special handling. */
17760 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17762 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17764 /* If this is pc-relative and we are going to emit a relocation
17765 then we just want to put out any pipeline compensation that the linker
17766 will need. Otherwise we want to use the calculated base.
17767 For WinCE we skip the bias for externals as well, since this
17768 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17770 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17771 || (arm_force_relocation (fixP
)
17773 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17778 switch (fixP
->fx_r_type
)
17780 /* PC relative addressing on the Thumb is slightly odd as the
17781 bottom two bits of the PC are forced to zero for the
17782 calculation. This happens *after* application of the
17783 pipeline offset. However, Thumb adrl already adjusts for
17784 this, so we need not do it again. */
17785 case BFD_RELOC_ARM_THUMB_ADD
:
17788 case BFD_RELOC_ARM_THUMB_OFFSET
:
17789 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17790 case BFD_RELOC_ARM_T32_ADD_PC12
:
17791 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17792 return (base
+ 4) & ~3;
17794 /* Thumb branches are simply offset by +4. */
17795 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17796 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17797 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17798 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17799 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17800 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17801 case BFD_RELOC_THUMB_PCREL_BLX
:
17804 /* ARM mode branches are offset by +8. However, the Windows CE
17805 loader expects the relocation not to take this into account. */
17806 case BFD_RELOC_ARM_PCREL_BRANCH
:
17807 case BFD_RELOC_ARM_PCREL_CALL
:
17808 case BFD_RELOC_ARM_PCREL_JUMP
:
17809 case BFD_RELOC_ARM_PCREL_BLX
:
17810 case BFD_RELOC_ARM_PLT32
:
17812 /* When handling fixups immediately, because we have already
17813 discovered the value of a symbol, or the address of the frag involved
17814 we must account for the offset by +8, as the OS loader will never see the reloc.
17815 see fixup_segment() in write.c
17816 The S_IS_EXTERNAL test handles the case of global symbols.
17817 Those need the calculated base, not just the pipe compensation the linker will need. */
17819 && fixP
->fx_addsy
!= NULL
17820 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17821 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17828 /* ARM mode loads relative to PC are also offset by +8. Unlike
17829 branches, the Windows CE loader *does* expect the relocation
17830 to take this into account. */
17831 case BFD_RELOC_ARM_OFFSET_IMM
:
17832 case BFD_RELOC_ARM_OFFSET_IMM8
:
17833 case BFD_RELOC_ARM_HWLITERAL
:
17834 case BFD_RELOC_ARM_LITERAL
:
17835 case BFD_RELOC_ARM_CP_OFF_IMM
:
17839 /* Other PC-relative relocations are un-offset. */
17845 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17846 Otherwise we have no need to default values of symbols. */
17849 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17852 if (name
[0] == '_' && name
[1] == 'G'
17853 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17857 if (symbol_find (name
))
17858 as_bad (_("GOT already in the symbol table"));
17860 GOT_symbol
= symbol_new (name
, undefined_section
,
17861 (valueT
) 0, & zero_address_frag
);
17871 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17872 computed as two separate immediate values, added together. We
17873 already know that this value cannot be computed by just one ARM
17876 static unsigned int
17877 validate_immediate_twopart (unsigned int val
,
17878 unsigned int * highpart
)
17883 for (i
= 0; i
< 32; i
+= 2)
17884 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17890 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17892 else if (a
& 0xff0000)
17894 if (a
& 0xff000000)
17896 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17900 assert (a
& 0xff000000);
17901 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17904 return (a
& 0xff) | (i
<< 7);
17911 validate_offset_imm (unsigned int val
, int hwse
)
17913 if ((hwse
&& val
> 255) || val
> 4095)
17918 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17919 negative immediate constant by altering the instruction. A bit of
17924 by inverting the second operand, and
17927 by negating the second operand. */
17930 negate_data_op (unsigned long * instruction
,
17931 unsigned long value
)
17934 unsigned long negated
, inverted
;
17936 negated
= encode_arm_immediate (-value
);
17937 inverted
= encode_arm_immediate (~value
);
17939 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17942 /* First negates. */
17943 case OPCODE_SUB
: /* ADD <-> SUB */
17944 new_inst
= OPCODE_ADD
;
17949 new_inst
= OPCODE_SUB
;
17953 case OPCODE_CMP
: /* CMP <-> CMN */
17954 new_inst
= OPCODE_CMN
;
17959 new_inst
= OPCODE_CMP
;
17963 /* Now Inverted ops. */
17964 case OPCODE_MOV
: /* MOV <-> MVN */
17965 new_inst
= OPCODE_MVN
;
17970 new_inst
= OPCODE_MOV
;
17974 case OPCODE_AND
: /* AND <-> BIC */
17975 new_inst
= OPCODE_BIC
;
17980 new_inst
= OPCODE_AND
;
17984 case OPCODE_ADC
: /* ADC <-> SBC */
17985 new_inst
= OPCODE_SBC
;
17990 new_inst
= OPCODE_ADC
;
17994 /* We cannot do anything. */
17999 if (value
== (unsigned) FAIL
)
18002 *instruction
&= OPCODE_MASK
;
18003 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
18007 /* Like negate_data_op, but for Thumb-2. */
18009 static unsigned int
18010 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
18014 unsigned int negated
, inverted
;
18016 negated
= encode_thumb32_immediate (-value
);
18017 inverted
= encode_thumb32_immediate (~value
);
18019 rd
= (*instruction
>> 8) & 0xf;
18020 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
18023 /* ADD <-> SUB. Includes CMP <-> CMN. */
18024 case T2_OPCODE_SUB
:
18025 new_inst
= T2_OPCODE_ADD
;
18029 case T2_OPCODE_ADD
:
18030 new_inst
= T2_OPCODE_SUB
;
18034 /* ORR <-> ORN. Includes MOV <-> MVN. */
18035 case T2_OPCODE_ORR
:
18036 new_inst
= T2_OPCODE_ORN
;
18040 case T2_OPCODE_ORN
:
18041 new_inst
= T2_OPCODE_ORR
;
18045 /* AND <-> BIC. TST has no inverted equivalent. */
18046 case T2_OPCODE_AND
:
18047 new_inst
= T2_OPCODE_BIC
;
18054 case T2_OPCODE_BIC
:
18055 new_inst
= T2_OPCODE_AND
;
18060 case T2_OPCODE_ADC
:
18061 new_inst
= T2_OPCODE_SBC
;
18065 case T2_OPCODE_SBC
:
18066 new_inst
= T2_OPCODE_ADC
;
18070 /* We cannot do anything. */
18075 if (value
== (unsigned int)FAIL
)
18078 *instruction
&= T2_OPCODE_MASK
;
18079 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
18083 /* Read a 32-bit thumb instruction from buf. */
18084 static unsigned long
18085 get_thumb32_insn (char * buf
)
18087 unsigned long insn
;
18088 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
18089 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18095 /* We usually want to set the low bit on the address of thumb function
18096 symbols. In particular .word foo - . should have the low bit set.
18097 Generic code tries to fold the difference of two symbols to
18098 a constant. Prevent this and force a relocation when the first symbols
18099 is a thumb function. */
18101 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
18103 if (op
== O_subtract
18104 && l
->X_op
== O_symbol
18105 && r
->X_op
== O_symbol
18106 && THUMB_IS_FUNC (l
->X_add_symbol
))
18108 l
->X_op
= O_subtract
;
18109 l
->X_op_symbol
= r
->X_add_symbol
;
18110 l
->X_add_number
-= r
->X_add_number
;
18113 /* Process as normal. */
18118 md_apply_fix (fixS
* fixP
,
18122 offsetT value
= * valP
;
18124 unsigned int newimm
;
18125 unsigned long temp
;
18127 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
18129 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
18131 /* Note whether this will delete the relocation. */
18133 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
18136 /* On a 64-bit host, silently truncate 'value' to 32 bits for
18137 consistency with the behaviour on 32-bit hosts. Remember value
18139 value
&= 0xffffffff;
18140 value
^= 0x80000000;
18141 value
-= 0x80000000;
18144 fixP
->fx_addnumber
= value
;
18146 /* Same treatment for fixP->fx_offset. */
18147 fixP
->fx_offset
&= 0xffffffff;
18148 fixP
->fx_offset
^= 0x80000000;
18149 fixP
->fx_offset
-= 0x80000000;
18151 switch (fixP
->fx_r_type
)
18153 case BFD_RELOC_NONE
:
18154 /* This will need to go in the object file. */
18158 case BFD_RELOC_ARM_IMMEDIATE
:
18159 /* We claim that this fixup has been processed here,
18160 even if in fact we generate an error because we do
18161 not have a reloc for it, so tc_gen_reloc will reject it. */
18165 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18167 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18168 _("undefined symbol %s used as an immediate value"),
18169 S_GET_NAME (fixP
->fx_addsy
));
18173 newimm
= encode_arm_immediate (value
);
18174 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18176 /* If the instruction will fail, see if we can fix things up by
18177 changing the opcode. */
18178 if (newimm
== (unsigned int) FAIL
18179 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
18181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18182 _("invalid constant (%lx) after fixup"),
18183 (unsigned long) value
);
18187 newimm
|= (temp
& 0xfffff000);
18188 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18191 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18193 unsigned int highpart
= 0;
18194 unsigned int newinsn
= 0xe1a00000; /* nop. */
18196 newimm
= encode_arm_immediate (value
);
18197 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18199 /* If the instruction will fail, see if we can fix things up by
18200 changing the opcode. */
18201 if (newimm
== (unsigned int) FAIL
18202 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
18204 /* No ? OK - try using two ADD instructions to generate
18206 newimm
= validate_immediate_twopart (value
, & highpart
);
18208 /* Yes - then make sure that the second instruction is
18210 if (newimm
!= (unsigned int) FAIL
)
18212 /* Still No ? Try using a negated value. */
18213 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
18214 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
18215 /* Otherwise - give up. */
18218 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18219 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18224 /* Replace the first operand in the 2nd instruction (which
18225 is the PC) with the destination register. We have
18226 already added in the PC in the first instruction and we
18227 do not want to do it again. */
18228 newinsn
&= ~ 0xf0000;
18229 newinsn
|= ((newinsn
& 0x0f000) << 4);
18232 newimm
|= (temp
& 0xfffff000);
18233 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18235 highpart
|= (newinsn
& 0xfffff000);
18236 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18240 case BFD_RELOC_ARM_OFFSET_IMM
:
18241 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18244 case BFD_RELOC_ARM_LITERAL
:
18250 if (validate_offset_imm (value
, 0) == FAIL
)
18252 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18254 _("invalid literal constant: pool needs to be closer"));
18256 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18257 _("bad immediate value for offset (%ld)"),
18262 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18263 newval
&= 0xff7ff000;
18264 newval
|= value
| (sign
? INDEX_UP
: 0);
18265 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18268 case BFD_RELOC_ARM_OFFSET_IMM8
:
18269 case BFD_RELOC_ARM_HWLITERAL
:
18275 if (validate_offset_imm (value
, 1) == FAIL
)
18277 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18278 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18279 _("invalid literal constant: pool needs to be closer"));
18281 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18286 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18287 newval
&= 0xff7ff0f0;
18288 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18289 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18292 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18293 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18294 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18295 _("bad immediate value for offset (%ld)"), (long) value
);
18298 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18300 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18303 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18304 /* This is a complicated relocation used for all varieties of Thumb32
18305 load/store instruction with immediate offset:
18307 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18308 *4, optional writeback(W)
18309 (doubleword load/store)
18311 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18312 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18313 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18314 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18315 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18317 Uppercase letters indicate bits that are already encoded at
18318 this point. Lowercase letters are our problem. For the
18319 second block of instructions, the secondary opcode nybble
18320 (bits 8..11) is present, and bit 23 is zero, even if this is
18321 a PC-relative operation. */
18322 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18324 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18326 if ((newval
& 0xf0000000) == 0xe0000000)
18328 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18330 newval
|= (1 << 23);
18333 if (value
% 4 != 0)
18335 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18336 _("offset not a multiple of 4"));
18342 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18343 _("offset out of range"));
18348 else if ((newval
& 0x000f0000) == 0x000f0000)
18350 /* PC-relative, 12-bit offset. */
18352 newval
|= (1 << 23);
18357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18358 _("offset out of range"));
18363 else if ((newval
& 0x00000100) == 0x00000100)
18365 /* Writeback: 8-bit, +/- offset. */
18367 newval
|= (1 << 9);
18372 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18373 _("offset out of range"));
18378 else if ((newval
& 0x00000f00) == 0x00000e00)
18380 /* T-instruction: positive 8-bit offset. */
18381 if (value
< 0 || value
> 0xff)
18383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18384 _("offset out of range"));
18392 /* Positive 12-bit or negative 8-bit offset. */
18396 newval
|= (1 << 23);
18406 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18407 _("offset out of range"));
18414 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18415 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18418 case BFD_RELOC_ARM_SHIFT_IMM
:
18419 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18420 if (((unsigned long) value
) > 32
18422 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18425 _("shift expression is too large"));
18430 /* Shifts of zero must be done as lsl. */
18432 else if (value
== 32)
18434 newval
&= 0xfffff07f;
18435 newval
|= (value
& 0x1f) << 7;
18436 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18439 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18440 case BFD_RELOC_ARM_T32_ADD_IMM
:
18441 case BFD_RELOC_ARM_T32_IMM12
:
18442 case BFD_RELOC_ARM_T32_ADD_PC12
:
18443 /* We claim that this fixup has been processed here,
18444 even if in fact we generate an error because we do
18445 not have a reloc for it, so tc_gen_reloc will reject it. */
18449 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18452 _("undefined symbol %s used as an immediate value"),
18453 S_GET_NAME (fixP
->fx_addsy
));
18457 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18459 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18462 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18463 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18465 newimm
= encode_thumb32_immediate (value
);
18466 if (newimm
== (unsigned int) FAIL
)
18467 newimm
= thumb32_negate_data_op (&newval
, value
);
18469 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18470 && newimm
== (unsigned int) FAIL
)
18472 /* Turn add/sum into addw/subw. */
18473 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18474 newval
= (newval
& 0xfeffffff) | 0x02000000;
18476 /* 12 bit immediate for addw/subw. */
18480 newval
^= 0x00a00000;
18483 newimm
= (unsigned int) FAIL
;
18488 if (newimm
== (unsigned int)FAIL
)
18490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18491 _("invalid constant (%lx) after fixup"),
18492 (unsigned long) value
);
18496 newval
|= (newimm
& 0x800) << 15;
18497 newval
|= (newimm
& 0x700) << 4;
18498 newval
|= (newimm
& 0x0ff);
18500 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18501 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18504 case BFD_RELOC_ARM_SMC
:
18505 if (((unsigned long) value
) > 0xffff)
18506 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18507 _("invalid smc expression"));
18508 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18509 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18510 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18513 case BFD_RELOC_ARM_SWI
:
18514 if (fixP
->tc_fix_data
!= 0)
18516 if (((unsigned long) value
) > 0xff)
18517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18518 _("invalid swi expression"));
18519 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18521 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18525 if (((unsigned long) value
) > 0x00ffffff)
18526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18527 _("invalid swi expression"));
18528 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18530 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18534 case BFD_RELOC_ARM_MULTI
:
18535 if (((unsigned long) value
) > 0xffff)
18536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18537 _("invalid expression in load/store multiple"));
18538 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18539 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18543 case BFD_RELOC_ARM_PCREL_CALL
:
18544 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18545 if ((newval
& 0xf0000000) == 0xf0000000)
18549 goto arm_branch_common
;
18551 case BFD_RELOC_ARM_PCREL_JUMP
:
18552 case BFD_RELOC_ARM_PLT32
:
18554 case BFD_RELOC_ARM_PCREL_BRANCH
:
18556 goto arm_branch_common
;
18558 case BFD_RELOC_ARM_PCREL_BLX
:
18561 /* We are going to store value (shifted right by two) in the
18562 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18563 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18564 also be be clear. */
18566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18567 _("misaligned branch destination"));
18568 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18569 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18570 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18571 _("branch out of range"));
18573 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18575 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18576 newval
|= (value
>> 2) & 0x00ffffff;
18577 /* Set the H bit on BLX instructions. */
18581 newval
|= 0x01000000;
18583 newval
&= ~0x01000000;
18585 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18589 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18590 /* CBZ can only branch forward. */
18592 /* Attempts to use CBZ to branch to the next instruction
18593 (which, strictly speaking, are prohibited) will be turned into
18596 FIXME: It may be better to remove the instruction completely and
18597 perform relaxation. */
18600 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18601 newval
= 0xbf00; /* NOP encoding T1 */
18602 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18607 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18608 _("branch out of range"));
18610 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18612 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18613 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18614 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18619 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18620 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18622 _("branch out of range"));
18624 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18626 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18627 newval
|= (value
& 0x1ff) >> 1;
18628 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18632 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18633 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18635 _("branch out of range"));
18637 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18639 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18640 newval
|= (value
& 0xfff) >> 1;
18641 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18645 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18646 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18648 _("conditional branch out of range"));
18650 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18653 addressT S
, J1
, J2
, lo
, hi
;
18655 S
= (value
& 0x00100000) >> 20;
18656 J2
= (value
& 0x00080000) >> 19;
18657 J1
= (value
& 0x00040000) >> 18;
18658 hi
= (value
& 0x0003f000) >> 12;
18659 lo
= (value
& 0x00000ffe) >> 1;
18661 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18662 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18663 newval
|= (S
<< 10) | hi
;
18664 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18665 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18666 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18670 case BFD_RELOC_THUMB_PCREL_BLX
:
18671 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18672 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18674 _("branch out of range"));
18676 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18677 /* For a BLX instruction, make sure that the relocation is rounded up
18678 to a word boundary. This follows the semantics of the instruction
18679 which specifies that bit 1 of the target address will come from bit
18680 1 of the base address. */
18681 value
= (value
+ 1) & ~ 1;
18683 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18687 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18688 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18689 newval
|= (value
& 0x7fffff) >> 12;
18690 newval2
|= (value
& 0xfff) >> 1;
18691 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18692 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18696 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18697 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18699 _("branch out of range"));
18701 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18704 addressT S
, I1
, I2
, lo
, hi
;
18706 S
= (value
& 0x01000000) >> 24;
18707 I1
= (value
& 0x00800000) >> 23;
18708 I2
= (value
& 0x00400000) >> 22;
18709 hi
= (value
& 0x003ff000) >> 12;
18710 lo
= (value
& 0x00000ffe) >> 1;
18715 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18716 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18717 newval
|= (S
<< 10) | hi
;
18718 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18719 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18720 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18725 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18726 md_number_to_chars (buf
, value
, 1);
18730 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18731 md_number_to_chars (buf
, value
, 2);
18735 case BFD_RELOC_ARM_TLS_GD32
:
18736 case BFD_RELOC_ARM_TLS_LE32
:
18737 case BFD_RELOC_ARM_TLS_IE32
:
18738 case BFD_RELOC_ARM_TLS_LDM32
:
18739 case BFD_RELOC_ARM_TLS_LDO32
:
18740 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18743 case BFD_RELOC_ARM_GOT32
:
18744 case BFD_RELOC_ARM_GOTOFF
:
18745 case BFD_RELOC_ARM_TARGET2
:
18746 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18747 md_number_to_chars (buf
, 0, 4);
18751 case BFD_RELOC_RVA
:
18753 case BFD_RELOC_ARM_TARGET1
:
18754 case BFD_RELOC_ARM_ROSEGREL32
:
18755 case BFD_RELOC_ARM_SBREL32
:
18756 case BFD_RELOC_32_PCREL
:
18758 case BFD_RELOC_32_SECREL
:
18760 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18762 /* For WinCE we only do this for pcrel fixups. */
18763 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18765 md_number_to_chars (buf
, value
, 4);
18769 case BFD_RELOC_ARM_PREL31
:
18770 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18772 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18773 if ((value
^ (value
>> 1)) & 0x40000000)
18775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18776 _("rel31 relocation overflow"));
18778 newval
|= value
& 0x7fffffff;
18779 md_number_to_chars (buf
, newval
, 4);
18784 case BFD_RELOC_ARM_CP_OFF_IMM
:
18785 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18786 if (value
< -1023 || value
> 1023 || (value
& 3))
18787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18788 _("co-processor offset out of range"));
18793 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18794 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18795 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18797 newval
= get_thumb32_insn (buf
);
18798 newval
&= 0xff7fff00;
18799 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18800 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18801 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18802 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18804 put_thumb32_insn (buf
, newval
);
18807 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18808 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18809 if (value
< -255 || value
> 255)
18810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18811 _("co-processor offset out of range"));
18813 goto cp_off_common
;
18815 case BFD_RELOC_ARM_THUMB_OFFSET
:
18816 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18817 /* Exactly what ranges, and where the offset is inserted depends
18818 on the type of instruction, we can establish this from the
18820 switch (newval
>> 12)
18822 case 4: /* PC load. */
18823 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18824 forced to zero for these loads; md_pcrel_from has already
18825 compensated for this. */
18827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18828 _("invalid offset, target not word aligned (0x%08lX)"),
18829 (((unsigned long) fixP
->fx_frag
->fr_address
18830 + (unsigned long) fixP
->fx_where
) & ~3)
18831 + (unsigned long) value
);
18833 if (value
& ~0x3fc)
18834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18835 _("invalid offset, value too big (0x%08lX)"),
18838 newval
|= value
>> 2;
18841 case 9: /* SP load/store. */
18842 if (value
& ~0x3fc)
18843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18844 _("invalid offset, value too big (0x%08lX)"),
18846 newval
|= value
>> 2;
18849 case 6: /* Word load/store. */
18851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18852 _("invalid offset, value too big (0x%08lX)"),
18854 newval
|= value
<< 4; /* 6 - 2. */
18857 case 7: /* Byte load/store. */
18859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18860 _("invalid offset, value too big (0x%08lX)"),
18862 newval
|= value
<< 6;
18865 case 8: /* Halfword load/store. */
18867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18868 _("invalid offset, value too big (0x%08lX)"),
18870 newval
|= value
<< 5; /* 6 - 1. */
18874 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18875 "Unable to process relocation for thumb opcode: %lx",
18876 (unsigned long) newval
);
18879 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18882 case BFD_RELOC_ARM_THUMB_ADD
:
18883 /* This is a complicated relocation, since we use it for all of
18884 the following immediate relocations:
18888 9bit ADD/SUB SP word-aligned
18889 10bit ADD PC/SP word-aligned
18891 The type of instruction being processed is encoded in the
18898 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18900 int rd
= (newval
>> 4) & 0xf;
18901 int rs
= newval
& 0xf;
18902 int subtract
= !!(newval
& 0x8000);
18904 /* Check for HI regs, only very restricted cases allowed:
18905 Adjusting SP, and using PC or SP to get an address. */
18906 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18907 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18909 _("invalid Hi register with immediate"));
18911 /* If value is negative, choose the opposite instruction. */
18915 subtract
= !subtract
;
18917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18918 _("immediate value out of range"));
18923 if (value
& ~0x1fc)
18924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18925 _("invalid immediate for stack address calculation"));
18926 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18927 newval
|= value
>> 2;
18929 else if (rs
== REG_PC
|| rs
== REG_SP
)
18931 if (subtract
|| value
& ~0x3fc)
18932 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18933 _("invalid immediate for address calculation (value = 0x%08lX)"),
18934 (unsigned long) value
);
18935 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18937 newval
|= value
>> 2;
18942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18943 _("immediate value out of range"));
18944 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18945 newval
|= (rd
<< 8) | value
;
18950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18951 _("immediate value out of range"));
18952 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18953 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18956 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18959 case BFD_RELOC_ARM_THUMB_IMM
:
18960 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18961 if (value
< 0 || value
> 255)
18962 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18963 _("invalid immediate: %ld is out of range"),
18966 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18969 case BFD_RELOC_ARM_THUMB_SHIFT
:
18970 /* 5bit shift value (0..32). LSL cannot take 32. */
18971 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18972 temp
= newval
& 0xf800;
18973 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18975 _("invalid shift value: %ld"), (long) value
);
18976 /* Shifts of zero must be encoded as LSL. */
18978 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18979 /* Shifts of 32 are encoded as zero. */
18980 else if (value
== 32)
18982 newval
|= value
<< 6;
18983 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18986 case BFD_RELOC_VTABLE_INHERIT
:
18987 case BFD_RELOC_VTABLE_ENTRY
:
18991 case BFD_RELOC_ARM_MOVW
:
18992 case BFD_RELOC_ARM_MOVT
:
18993 case BFD_RELOC_ARM_THUMB_MOVW
:
18994 case BFD_RELOC_ARM_THUMB_MOVT
:
18995 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18997 /* REL format relocations are limited to a 16-bit addend. */
18998 if (!fixP
->fx_done
)
19000 if (value
< -0x8000 || value
> 0x7fff)
19001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19002 _("offset out of range"));
19004 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
19005 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
19010 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
19011 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
19013 newval
= get_thumb32_insn (buf
);
19014 newval
&= 0xfbf08f00;
19015 newval
|= (value
& 0xf000) << 4;
19016 newval
|= (value
& 0x0800) << 15;
19017 newval
|= (value
& 0x0700) << 4;
19018 newval
|= (value
& 0x00ff);
19019 put_thumb32_insn (buf
, newval
);
19023 newval
= md_chars_to_number (buf
, 4);
19024 newval
&= 0xfff0f000;
19025 newval
|= value
& 0x0fff;
19026 newval
|= (value
& 0xf000) << 4;
19027 md_number_to_chars (buf
, newval
, 4);
19032 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19033 case BFD_RELOC_ARM_ALU_PC_G0
:
19034 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19035 case BFD_RELOC_ARM_ALU_PC_G1
:
19036 case BFD_RELOC_ARM_ALU_PC_G2
:
19037 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19038 case BFD_RELOC_ARM_ALU_SB_G0
:
19039 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19040 case BFD_RELOC_ARM_ALU_SB_G1
:
19041 case BFD_RELOC_ARM_ALU_SB_G2
:
19042 assert (!fixP
->fx_done
);
19043 if (!seg
->use_rela_p
)
19046 bfd_vma encoded_addend
;
19047 bfd_vma addend_abs
= abs (value
);
19049 /* Check that the absolute value of the addend can be
19050 expressed as an 8-bit constant plus a rotation. */
19051 encoded_addend
= encode_arm_immediate (addend_abs
);
19052 if (encoded_addend
== (unsigned int) FAIL
)
19053 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19054 _("the offset 0x%08lX is not representable"),
19055 (unsigned long) addend_abs
);
19057 /* Extract the instruction. */
19058 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19060 /* If the addend is positive, use an ADD instruction.
19061 Otherwise use a SUB. Take care not to destroy the S bit. */
19062 insn
&= 0xff1fffff;
19068 /* Place the encoded addend into the first 12 bits of the
19070 insn
&= 0xfffff000;
19071 insn
|= encoded_addend
;
19073 /* Update the instruction. */
19074 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19078 case BFD_RELOC_ARM_LDR_PC_G0
:
19079 case BFD_RELOC_ARM_LDR_PC_G1
:
19080 case BFD_RELOC_ARM_LDR_PC_G2
:
19081 case BFD_RELOC_ARM_LDR_SB_G0
:
19082 case BFD_RELOC_ARM_LDR_SB_G1
:
19083 case BFD_RELOC_ARM_LDR_SB_G2
:
19084 assert (!fixP
->fx_done
);
19085 if (!seg
->use_rela_p
)
19088 bfd_vma addend_abs
= abs (value
);
19090 /* Check that the absolute value of the addend can be
19091 encoded in 12 bits. */
19092 if (addend_abs
>= 0x1000)
19093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19094 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
19095 (unsigned long) addend_abs
);
19097 /* Extract the instruction. */
19098 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19100 /* If the addend is negative, clear bit 23 of the instruction.
19101 Otherwise set it. */
19103 insn
&= ~(1 << 23);
19107 /* Place the absolute value of the addend into the first 12 bits
19108 of the instruction. */
19109 insn
&= 0xfffff000;
19110 insn
|= addend_abs
;
19112 /* Update the instruction. */
19113 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19117 case BFD_RELOC_ARM_LDRS_PC_G0
:
19118 case BFD_RELOC_ARM_LDRS_PC_G1
:
19119 case BFD_RELOC_ARM_LDRS_PC_G2
:
19120 case BFD_RELOC_ARM_LDRS_SB_G0
:
19121 case BFD_RELOC_ARM_LDRS_SB_G1
:
19122 case BFD_RELOC_ARM_LDRS_SB_G2
:
19123 assert (!fixP
->fx_done
);
19124 if (!seg
->use_rela_p
)
19127 bfd_vma addend_abs
= abs (value
);
19129 /* Check that the absolute value of the addend can be
19130 encoded in 8 bits. */
19131 if (addend_abs
>= 0x100)
19132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19133 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
19134 (unsigned long) addend_abs
);
19136 /* Extract the instruction. */
19137 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19139 /* If the addend is negative, clear bit 23 of the instruction.
19140 Otherwise set it. */
19142 insn
&= ~(1 << 23);
19146 /* Place the first four bits of the absolute value of the addend
19147 into the first 4 bits of the instruction, and the remaining
19148 four into bits 8 .. 11. */
19149 insn
&= 0xfffff0f0;
19150 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
19152 /* Update the instruction. */
19153 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19157 case BFD_RELOC_ARM_LDC_PC_G0
:
19158 case BFD_RELOC_ARM_LDC_PC_G1
:
19159 case BFD_RELOC_ARM_LDC_PC_G2
:
19160 case BFD_RELOC_ARM_LDC_SB_G0
:
19161 case BFD_RELOC_ARM_LDC_SB_G1
:
19162 case BFD_RELOC_ARM_LDC_SB_G2
:
19163 assert (!fixP
->fx_done
);
19164 if (!seg
->use_rela_p
)
19167 bfd_vma addend_abs
= abs (value
);
19169 /* Check that the absolute value of the addend is a multiple of
19170 four and, when divided by four, fits in 8 bits. */
19171 if (addend_abs
& 0x3)
19172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19173 _("bad offset 0x%08lX (must be word-aligned)"),
19174 (unsigned long) addend_abs
);
19176 if ((addend_abs
>> 2) > 0xff)
19177 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19178 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
19179 (unsigned long) addend_abs
);
19181 /* Extract the instruction. */
19182 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19184 /* If the addend is negative, clear bit 23 of the instruction.
19185 Otherwise set it. */
19187 insn
&= ~(1 << 23);
19191 /* Place the addend (divided by four) into the first eight
19192 bits of the instruction. */
19193 insn
&= 0xfffffff0;
19194 insn
|= addend_abs
>> 2;
19196 /* Update the instruction. */
19197 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19201 case BFD_RELOC_ARM_V4BX
:
19202 /* This will need to go in the object file. */
19206 case BFD_RELOC_UNUSED
:
19208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19209 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
19213 /* Translate internal representation of relocation info to BFD target
19217 tc_gen_reloc (asection
*section
, fixS
*fixp
)
19220 bfd_reloc_code_real_type code
;
19222 reloc
= xmalloc (sizeof (arelent
));
19224 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
19225 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
19226 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
19228 if (fixp
->fx_pcrel
)
19230 if (section
->use_rela_p
)
19231 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
19233 fixp
->fx_offset
= reloc
->address
;
19235 reloc
->addend
= fixp
->fx_offset
;
19237 switch (fixp
->fx_r_type
)
19240 if (fixp
->fx_pcrel
)
19242 code
= BFD_RELOC_8_PCREL
;
19247 if (fixp
->fx_pcrel
)
19249 code
= BFD_RELOC_16_PCREL
;
19254 if (fixp
->fx_pcrel
)
19256 code
= BFD_RELOC_32_PCREL
;
19260 case BFD_RELOC_ARM_MOVW
:
19261 if (fixp
->fx_pcrel
)
19263 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19267 case BFD_RELOC_ARM_MOVT
:
19268 if (fixp
->fx_pcrel
)
19270 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19274 case BFD_RELOC_ARM_THUMB_MOVW
:
19275 if (fixp
->fx_pcrel
)
19277 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19281 case BFD_RELOC_ARM_THUMB_MOVT
:
19282 if (fixp
->fx_pcrel
)
19284 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19288 case BFD_RELOC_NONE
:
19289 case BFD_RELOC_ARM_PCREL_BRANCH
:
19290 case BFD_RELOC_ARM_PCREL_BLX
:
19291 case BFD_RELOC_RVA
:
19292 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19293 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19294 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19295 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19296 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19297 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19298 case BFD_RELOC_THUMB_PCREL_BLX
:
19299 case BFD_RELOC_VTABLE_ENTRY
:
19300 case BFD_RELOC_VTABLE_INHERIT
:
19302 case BFD_RELOC_32_SECREL
:
19304 code
= fixp
->fx_r_type
;
19307 case BFD_RELOC_ARM_LITERAL
:
19308 case BFD_RELOC_ARM_HWLITERAL
:
19309 /* If this is called then the a literal has
19310 been referenced across a section boundary. */
19311 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19312 _("literal referenced across section boundary"));
19316 case BFD_RELOC_ARM_GOT32
:
19317 case BFD_RELOC_ARM_GOTOFF
:
19318 case BFD_RELOC_ARM_PLT32
:
19319 case BFD_RELOC_ARM_TARGET1
:
19320 case BFD_RELOC_ARM_ROSEGREL32
:
19321 case BFD_RELOC_ARM_SBREL32
:
19322 case BFD_RELOC_ARM_PREL31
:
19323 case BFD_RELOC_ARM_TARGET2
:
19324 case BFD_RELOC_ARM_TLS_LE32
:
19325 case BFD_RELOC_ARM_TLS_LDO32
:
19326 case BFD_RELOC_ARM_PCREL_CALL
:
19327 case BFD_RELOC_ARM_PCREL_JUMP
:
19328 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19329 case BFD_RELOC_ARM_ALU_PC_G0
:
19330 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19331 case BFD_RELOC_ARM_ALU_PC_G1
:
19332 case BFD_RELOC_ARM_ALU_PC_G2
:
19333 case BFD_RELOC_ARM_LDR_PC_G0
:
19334 case BFD_RELOC_ARM_LDR_PC_G1
:
19335 case BFD_RELOC_ARM_LDR_PC_G2
:
19336 case BFD_RELOC_ARM_LDRS_PC_G0
:
19337 case BFD_RELOC_ARM_LDRS_PC_G1
:
19338 case BFD_RELOC_ARM_LDRS_PC_G2
:
19339 case BFD_RELOC_ARM_LDC_PC_G0
:
19340 case BFD_RELOC_ARM_LDC_PC_G1
:
19341 case BFD_RELOC_ARM_LDC_PC_G2
:
19342 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19343 case BFD_RELOC_ARM_ALU_SB_G0
:
19344 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19345 case BFD_RELOC_ARM_ALU_SB_G1
:
19346 case BFD_RELOC_ARM_ALU_SB_G2
:
19347 case BFD_RELOC_ARM_LDR_SB_G0
:
19348 case BFD_RELOC_ARM_LDR_SB_G1
:
19349 case BFD_RELOC_ARM_LDR_SB_G2
:
19350 case BFD_RELOC_ARM_LDRS_SB_G0
:
19351 case BFD_RELOC_ARM_LDRS_SB_G1
:
19352 case BFD_RELOC_ARM_LDRS_SB_G2
:
19353 case BFD_RELOC_ARM_LDC_SB_G0
:
19354 case BFD_RELOC_ARM_LDC_SB_G1
:
19355 case BFD_RELOC_ARM_LDC_SB_G2
:
19356 case BFD_RELOC_ARM_V4BX
:
19357 code
= fixp
->fx_r_type
;
19360 case BFD_RELOC_ARM_TLS_GD32
:
19361 case BFD_RELOC_ARM_TLS_IE32
:
19362 case BFD_RELOC_ARM_TLS_LDM32
:
19363 /* BFD will include the symbol's address in the addend.
19364 But we don't want that, so subtract it out again here. */
19365 if (!S_IS_COMMON (fixp
->fx_addsy
))
19366 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19367 code
= fixp
->fx_r_type
;
19371 case BFD_RELOC_ARM_IMMEDIATE
:
19372 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19373 _("internal relocation (type: IMMEDIATE) not fixed up"));
19376 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19377 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19378 _("ADRL used for a symbol not defined in the same file"));
19381 case BFD_RELOC_ARM_OFFSET_IMM
:
19382 if (section
->use_rela_p
)
19384 code
= fixp
->fx_r_type
;
19388 if (fixp
->fx_addsy
!= NULL
19389 && !S_IS_DEFINED (fixp
->fx_addsy
)
19390 && S_IS_LOCAL (fixp
->fx_addsy
))
19392 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19393 _("undefined local label `%s'"),
19394 S_GET_NAME (fixp
->fx_addsy
));
19398 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19399 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19406 switch (fixp
->fx_r_type
)
19408 case BFD_RELOC_NONE
: type
= "NONE"; break;
19409 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19410 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19411 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19412 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19413 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19414 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19415 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19416 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19417 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19418 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19419 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19420 default: type
= _("<unknown>"); break;
19422 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19423 _("cannot represent %s relocation in this object file format"),
19430 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19432 && fixp
->fx_addsy
== GOT_symbol
)
19434 code
= BFD_RELOC_ARM_GOTPC
;
19435 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19439 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19441 if (reloc
->howto
== NULL
)
19443 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19444 _("cannot represent %s relocation in this object file format"),
19445 bfd_get_reloc_code_name (code
));
19449 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19450 vtable entry to be used in the relocation's section offset. */
19451 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19452 reloc
->address
= fixp
->fx_offset
;
19457 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19460 cons_fix_new_arm (fragS
* frag
,
19465 bfd_reloc_code_real_type type
;
19469 FIXME: @@ Should look at CPU word size. */
19473 type
= BFD_RELOC_8
;
19476 type
= BFD_RELOC_16
;
19480 type
= BFD_RELOC_32
;
19483 type
= BFD_RELOC_64
;
19488 if (exp
->X_op
== O_secrel
)
19490 exp
->X_op
= O_symbol
;
19491 type
= BFD_RELOC_32_SECREL
;
19495 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19498 #if defined OBJ_COFF || defined OBJ_ELF
19500 arm_validate_fix (fixS
* fixP
)
19502 /* If the destination of the branch is a defined symbol which does not have
19503 the THUMB_FUNC attribute, then we must be calling a function which has
19504 the (interfacearm) attribute. We look for the Thumb entry point to that
19505 function and change the branch to refer to that function instead. */
19506 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19507 && fixP
->fx_addsy
!= NULL
19508 && S_IS_DEFINED (fixP
->fx_addsy
)
19509 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19511 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19517 arm_force_relocation (struct fix
* fixp
)
19519 #if defined (OBJ_COFF) && defined (TE_PE)
19520 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19524 /* Resolve these relocations even if the symbol is extern or weak. */
19525 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19526 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19527 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19528 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19529 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19530 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19531 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19534 /* Always leave these relocations for the linker. */
19535 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19536 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19537 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19540 /* Always generate relocations against function symbols. */
19541 if (fixp
->fx_r_type
== BFD_RELOC_32
19543 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19546 return generic_force_reloc (fixp
);
19549 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19550 /* Relocations against function names must be left unadjusted,
19551 so that the linker can use this information to generate interworking
19552 stubs. The MIPS version of this function
19553 also prevents relocations that are mips-16 specific, but I do not
19554 know why it does this.
19557 There is one other problem that ought to be addressed here, but
19558 which currently is not: Taking the address of a label (rather
19559 than a function) and then later jumping to that address. Such
19560 addresses also ought to have their bottom bit set (assuming that
19561 they reside in Thumb code), but at the moment they will not. */
19564 arm_fix_adjustable (fixS
* fixP
)
19566 if (fixP
->fx_addsy
== NULL
)
19569 /* Preserve relocations against symbols with function type. */
19570 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19573 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19574 && fixP
->fx_subsy
== NULL
)
19577 /* We need the symbol name for the VTABLE entries. */
19578 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19579 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19582 /* Don't allow symbols to be discarded on GOT related relocs. */
19583 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19584 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19585 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19586 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19587 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19588 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19589 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19590 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19591 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19594 /* Similarly for group relocations. */
19595 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19596 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19597 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19600 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
19601 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
19602 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
19603 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
19604 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
19605 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
19606 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
19607 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
19608 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
19613 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19618 elf32_arm_target_format (void)
19621 return (target_big_endian
19622 ? "elf32-bigarm-symbian"
19623 : "elf32-littlearm-symbian");
19624 #elif defined (TE_VXWORKS)
19625 return (target_big_endian
19626 ? "elf32-bigarm-vxworks"
19627 : "elf32-littlearm-vxworks");
19629 if (target_big_endian
)
19630 return "elf32-bigarm";
19632 return "elf32-littlearm";
19637 armelf_frob_symbol (symbolS
* symp
,
19640 elf_frob_symbol (symp
, puntp
);
19644 /* MD interface: Finalization. */
19646 /* A good place to do this, although this was probably not intended
19647 for this kind of use. We need to dump the literal pool before
19648 references are made to a null symbol pointer. */
19653 literal_pool
* pool
;
19655 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19657 /* Put it at the end of the relevant section. */
19658 subseg_set (pool
->section
, pool
->sub_section
);
19660 arm_elf_change_section ();
19666 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19670 arm_adjust_symtab (void)
19675 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19677 if (ARM_IS_THUMB (sym
))
19679 if (THUMB_IS_FUNC (sym
))
19681 /* Mark the symbol as a Thumb function. */
19682 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19683 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19684 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19686 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19687 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19689 as_bad (_("%s: unexpected function type: %d"),
19690 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19692 else switch (S_GET_STORAGE_CLASS (sym
))
19695 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19698 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19701 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19709 if (ARM_IS_INTERWORK (sym
))
19710 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19717 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19719 if (ARM_IS_THUMB (sym
))
19721 elf_symbol_type
* elf_sym
;
19723 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19724 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19726 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19727 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19729 /* If it's a .thumb_func, declare it as so,
19730 otherwise tag label as .code 16. */
19731 if (THUMB_IS_FUNC (sym
))
19732 elf_sym
->internal_elf_sym
.st_info
=
19733 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19734 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19735 elf_sym
->internal_elf_sym
.st_info
=
19736 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19743 /* MD interface: Initialization. */
19746 set_constant_flonums (void)
19750 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19751 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19755 /* Auto-select Thumb mode if it's the only available instruction set for the
19756 given architecture. */
19759 autoselect_thumb_from_cpu_variant (void)
19761 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19762 opcode_select (16);
19771 if ( (arm_ops_hsh
= hash_new ()) == NULL
19772 || (arm_cond_hsh
= hash_new ()) == NULL
19773 || (arm_shift_hsh
= hash_new ()) == NULL
19774 || (arm_psr_hsh
= hash_new ()) == NULL
19775 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19776 || (arm_reg_hsh
= hash_new ()) == NULL
19777 || (arm_reloc_hsh
= hash_new ()) == NULL
19778 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19779 as_fatal (_("virtual memory exhausted"));
19781 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19782 hash_insert (arm_ops_hsh
, insns
[i
].template, (void *) (insns
+ i
));
19783 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19784 hash_insert (arm_cond_hsh
, conds
[i
].template, (void *) (conds
+ i
));
19785 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19786 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
19787 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19788 hash_insert (arm_psr_hsh
, psrs
[i
].template, (void *) (psrs
+ i
));
19789 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19790 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (void *) (v7m_psrs
+ i
));
19791 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19792 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
19794 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19796 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19797 (void *) (barrier_opt_names
+ i
));
19799 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19800 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
19803 set_constant_flonums ();
19805 /* Set the cpu variant based on the command-line options. We prefer
19806 -mcpu= over -march= if both are set (as for GCC); and we prefer
19807 -mfpu= over any other way of setting the floating point unit.
19808 Use of legacy options with new options are faulted. */
19811 if (mcpu_cpu_opt
|| march_cpu_opt
)
19812 as_bad (_("use of old and new-style options to set CPU type"));
19814 mcpu_cpu_opt
= legacy_cpu
;
19816 else if (!mcpu_cpu_opt
)
19817 mcpu_cpu_opt
= march_cpu_opt
;
19822 as_bad (_("use of old and new-style options to set FPU type"));
19824 mfpu_opt
= legacy_fpu
;
19826 else if (!mfpu_opt
)
19828 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19829 /* Some environments specify a default FPU. If they don't, infer it
19830 from the processor. */
19832 mfpu_opt
= mcpu_fpu_opt
;
19834 mfpu_opt
= march_fpu_opt
;
19836 mfpu_opt
= &fpu_default
;
19842 if (mcpu_cpu_opt
!= NULL
)
19843 mfpu_opt
= &fpu_default
;
19844 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19845 mfpu_opt
= &fpu_arch_vfp_v2
;
19847 mfpu_opt
= &fpu_arch_fpa
;
19853 mcpu_cpu_opt
= &cpu_default
;
19854 selected_cpu
= cpu_default
;
19858 selected_cpu
= *mcpu_cpu_opt
;
19860 mcpu_cpu_opt
= &arm_arch_any
;
19863 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19865 autoselect_thumb_from_cpu_variant ();
19867 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19869 #if defined OBJ_COFF || defined OBJ_ELF
19871 unsigned int flags
= 0;
19873 #if defined OBJ_ELF
19874 flags
= meabi_flags
;
19876 switch (meabi_flags
)
19878 case EF_ARM_EABI_UNKNOWN
:
19880 /* Set the flags in the private structure. */
19881 if (uses_apcs_26
) flags
|= F_APCS26
;
19882 if (support_interwork
) flags
|= F_INTERWORK
;
19883 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19884 if (pic_code
) flags
|= F_PIC
;
19885 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19886 flags
|= F_SOFT_FLOAT
;
19888 switch (mfloat_abi_opt
)
19890 case ARM_FLOAT_ABI_SOFT
:
19891 case ARM_FLOAT_ABI_SOFTFP
:
19892 flags
|= F_SOFT_FLOAT
;
19895 case ARM_FLOAT_ABI_HARD
:
19896 if (flags
& F_SOFT_FLOAT
)
19897 as_bad (_("hard-float conflicts with specified fpu"));
19901 /* Using pure-endian doubles (even if soft-float). */
19902 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19903 flags
|= F_VFP_FLOAT
;
19905 #if defined OBJ_ELF
19906 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19907 flags
|= EF_ARM_MAVERICK_FLOAT
;
19910 case EF_ARM_EABI_VER4
:
19911 case EF_ARM_EABI_VER5
:
19912 /* No additional flags to set. */
19919 bfd_set_private_flags (stdoutput
, flags
);
19921 /* We have run out flags in the COFF header to encode the
19922 status of ATPCS support, so instead we create a dummy,
19923 empty, debug section called .arm.atpcs. */
19928 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19932 bfd_set_section_flags
19933 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19934 bfd_set_section_size (stdoutput
, sec
, 0);
19935 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19941 /* Record the CPU type as well. */
19942 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19943 mach
= bfd_mach_arm_iWMMXt2
;
19944 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19945 mach
= bfd_mach_arm_iWMMXt
;
19946 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19947 mach
= bfd_mach_arm_XScale
;
19948 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19949 mach
= bfd_mach_arm_ep9312
;
19950 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19951 mach
= bfd_mach_arm_5TE
;
19952 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19954 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19955 mach
= bfd_mach_arm_5T
;
19957 mach
= bfd_mach_arm_5
;
19959 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19961 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19962 mach
= bfd_mach_arm_4T
;
19964 mach
= bfd_mach_arm_4
;
19966 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19967 mach
= bfd_mach_arm_3M
;
19968 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19969 mach
= bfd_mach_arm_3
;
19970 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19971 mach
= bfd_mach_arm_2a
;
19972 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19973 mach
= bfd_mach_arm_2
;
19975 mach
= bfd_mach_arm_unknown
;
19977 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19980 /* Command line processing. */
19983 Invocation line includes a switch not recognized by the base assembler.
19984 See if it's a processor-specific option.
19986 This routine is somewhat complicated by the need for backwards
19987 compatibility (since older releases of gcc can't be changed).
19988 The new options try to make the interface as compatible as
19991 New options (supported) are:
19993 -mcpu=<cpu name> Assemble for selected processor
19994 -march=<architecture name> Assemble for selected architecture
19995 -mfpu=<fpu architecture> Assemble for selected FPU.
19996 -EB/-mbig-endian Big-endian
19997 -EL/-mlittle-endian Little-endian
19998 -k Generate PIC code
19999 -mthumb Start in Thumb mode
20000 -mthumb-interwork Code supports ARM/Thumb interworking
20002 -m[no-]warn-deprecated Warn about deprecated features
20004 For now we will also provide support for:
20006 -mapcs-32 32-bit Program counter
20007 -mapcs-26 26-bit Program counter
20008 -macps-float Floats passed in FP registers
20009 -mapcs-reentrant Reentrant code
20011 (sometime these will probably be replaced with -mapcs=<list of options>
20012 and -matpcs=<list of options>)
20014 The remaining options are only supported for back-wards compatibility.
20015 Cpu variants, the arm part is optional:
20016 -m[arm]1 Currently not supported.
20017 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
20018 -m[arm]3 Arm 3 processor
20019 -m[arm]6[xx], Arm 6 processors
20020 -m[arm]7[xx][t][[d]m] Arm 7 processors
20021 -m[arm]8[10] Arm 8 processors
20022 -m[arm]9[20][tdmi] Arm 9 processors
20023 -mstrongarm[110[0]] StrongARM processors
20024 -mxscale XScale processors
20025 -m[arm]v[2345[t[e]]] Arm architectures
20026 -mall All (except the ARM1)
20028 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
20029 -mfpe-old (No float load/store multiples)
20030 -mvfpxd VFP Single precision
20032 -mno-fpu Disable all floating point instructions
20034 The following CPU names are recognized:
20035 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
20036 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
20037 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
20038 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
20039 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
20040 arm10t arm10e, arm1020t, arm1020e, arm10200e,
20041 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
20045 const char * md_shortopts
= "m:k";
20047 #ifdef ARM_BI_ENDIAN
20048 #define OPTION_EB (OPTION_MD_BASE + 0)
20049 #define OPTION_EL (OPTION_MD_BASE + 1)
20051 #if TARGET_BYTES_BIG_ENDIAN
20052 #define OPTION_EB (OPTION_MD_BASE + 0)
20054 #define OPTION_EL (OPTION_MD_BASE + 1)
20057 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
20059 struct option md_longopts
[] =
20062 {"EB", no_argument
, NULL
, OPTION_EB
},
20065 {"EL", no_argument
, NULL
, OPTION_EL
},
20067 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
20068 {NULL
, no_argument
, NULL
, 0}
20071 size_t md_longopts_size
= sizeof (md_longopts
);
20073 struct arm_option_table
20075 char *option
; /* Option name to match. */
20076 char *help
; /* Help information. */
20077 int *var
; /* Variable to change. */
20078 int value
; /* What to change it to. */
20079 char *deprecated
; /* If non-null, print this message. */
20082 struct arm_option_table arm_opts
[] =
20084 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
20085 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
20086 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
20087 &support_interwork
, 1, NULL
},
20088 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
20089 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
20090 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
20092 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
20093 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
20094 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
20095 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
20098 /* These are recognized by the assembler, but have no affect on code. */
20099 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
20100 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
20102 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
20103 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
20104 &warn_on_deprecated
, 0, NULL
},
20105 {NULL
, NULL
, NULL
, 0, NULL
}
20108 struct arm_legacy_option_table
20110 char *option
; /* Option name to match. */
20111 const arm_feature_set
**var
; /* Variable to change. */
20112 const arm_feature_set value
; /* What to change it to. */
20113 char *deprecated
; /* If non-null, print this message. */
20116 const struct arm_legacy_option_table arm_legacy_opts
[] =
20118 /* DON'T add any new processors to this list -- we want the whole list
20119 to go away... Add them to the processors table instead. */
20120 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20121 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20122 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20123 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20124 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20125 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20126 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20127 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20128 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20129 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20130 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20131 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20132 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20133 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20134 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20135 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20136 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20137 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20138 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20139 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20140 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20141 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20142 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20143 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20144 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20145 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20146 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20147 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20148 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20149 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20150 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20151 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20152 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20153 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20154 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20155 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20156 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20157 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20158 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20159 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20160 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20161 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20162 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20163 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20164 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20165 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20166 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20167 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20168 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20169 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20170 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20171 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20172 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20173 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20174 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20175 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20176 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20177 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20178 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20179 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20180 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20181 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20182 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20183 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20184 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20185 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20186 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20187 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20188 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
20189 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
20190 N_("use -mcpu=strongarm110")},
20191 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
20192 N_("use -mcpu=strongarm1100")},
20193 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
20194 N_("use -mcpu=strongarm1110")},
20195 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
20196 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
20197 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
20199 /* Architecture variants -- don't add any more to this list either. */
20200 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20201 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20202 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20203 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20204 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20205 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20206 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20207 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20208 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20209 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20210 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20211 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20212 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20213 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20214 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20215 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20216 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20217 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20219 /* Floating point variants -- don't add any more to this list either. */
20220 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
20221 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
20222 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
20223 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
20224 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
20226 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
20229 struct arm_cpu_option_table
20232 const arm_feature_set value
;
20233 /* For some CPUs we assume an FPU unless the user explicitly sets
20235 const arm_feature_set default_fpu
;
20236 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20238 const char *canonical_name
;
20241 /* This list should, at a minimum, contain all the cpu names
20242 recognized by GCC. */
20243 static const struct arm_cpu_option_table arm_cpus
[] =
20245 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
20246 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
20247 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
20248 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20249 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20250 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20251 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20252 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20253 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20254 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20255 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20256 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20257 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20258 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20259 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20260 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20261 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20262 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20263 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20264 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20265 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20266 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20267 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20268 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20269 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20270 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20271 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20272 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20273 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20274 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20275 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20276 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20277 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20278 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20279 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20280 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20281 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20282 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20283 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20284 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20285 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20286 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20287 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20288 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20289 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20290 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20291 /* For V5 or later processors we default to using VFP; but the user
20292 should really set the FPU type explicitly. */
20293 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20294 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20295 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20296 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20297 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20298 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20299 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20300 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20301 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20302 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20303 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20304 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20305 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20306 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20307 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20308 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20309 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20310 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20311 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20312 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20313 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20314 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
20315 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20316 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20317 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20318 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20319 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20320 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20321 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20322 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20323 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20324 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20325 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20326 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20327 | FPU_NEON_EXT_V1
),
20329 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20330 | FPU_NEON_EXT_V1
),
20332 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20333 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20334 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
20335 /* ??? XSCALE is really an architecture. */
20336 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20337 /* ??? iwmmxt is not a processor. */
20338 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20339 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20340 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20342 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20343 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20346 struct arm_arch_option_table
20349 const arm_feature_set value
;
20350 const arm_feature_set default_fpu
;
20353 /* This list should, at a minimum, contain all the architecture names
20354 recognized by GCC. */
20355 static const struct arm_arch_option_table arm_archs
[] =
20357 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20358 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20359 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20360 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20361 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20362 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20363 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20364 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20365 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20366 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20367 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20368 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20369 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20370 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20371 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20372 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20373 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20374 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20375 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20376 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20377 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20378 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20379 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20380 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20381 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20382 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20383 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
20384 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20385 /* The official spelling of the ARMv7 profile variants is the dashed form.
20386 Accept the non-dashed form for compatibility with old toolchains. */
20387 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20388 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20389 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20390 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20391 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20392 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20393 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20394 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20395 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20396 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20399 /* ISA extensions in the co-processor space. */
20400 struct arm_option_cpu_value_table
20403 const arm_feature_set value
;
20406 static const struct arm_option_cpu_value_table arm_extensions
[] =
20408 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20409 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20410 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20411 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20412 {NULL
, ARM_ARCH_NONE
}
20415 /* This list should, at a minimum, contain all the fpu names
20416 recognized by GCC. */
20417 static const struct arm_option_cpu_value_table arm_fpus
[] =
20419 {"softfpa", FPU_NONE
},
20420 {"fpe", FPU_ARCH_FPE
},
20421 {"fpe2", FPU_ARCH_FPE
},
20422 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20423 {"fpa", FPU_ARCH_FPA
},
20424 {"fpa10", FPU_ARCH_FPA
},
20425 {"fpa11", FPU_ARCH_FPA
},
20426 {"arm7500fe", FPU_ARCH_FPA
},
20427 {"softvfp", FPU_ARCH_VFP
},
20428 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20429 {"vfp", FPU_ARCH_VFP_V2
},
20430 {"vfp9", FPU_ARCH_VFP_V2
},
20431 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
20432 {"vfp10", FPU_ARCH_VFP_V2
},
20433 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20434 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20435 {"vfpv2", FPU_ARCH_VFP_V2
},
20436 {"vfpv3", FPU_ARCH_VFP_V3
},
20437 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
20438 {"arm1020t", FPU_ARCH_VFP_V1
},
20439 {"arm1020e", FPU_ARCH_VFP_V2
},
20440 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20441 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20442 {"maverick", FPU_ARCH_MAVERICK
},
20443 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20444 {"neon-fp16", FPU_ARCH_NEON_FP16
},
20445 {NULL
, ARM_ARCH_NONE
}
20448 struct arm_option_value_table
20454 static const struct arm_option_value_table arm_float_abis
[] =
20456 {"hard", ARM_FLOAT_ABI_HARD
},
20457 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20458 {"soft", ARM_FLOAT_ABI_SOFT
},
20463 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20464 static const struct arm_option_value_table arm_eabis
[] =
20466 {"gnu", EF_ARM_EABI_UNKNOWN
},
20467 {"4", EF_ARM_EABI_VER4
},
20468 {"5", EF_ARM_EABI_VER5
},
20473 struct arm_long_option_table
20475 char * option
; /* Substring to match. */
20476 char * help
; /* Help information. */
20477 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20478 char * deprecated
; /* If non-null, print this message. */
20482 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20484 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20486 /* Copy the feature set, so that we can modify it. */
20487 *ext_set
= **opt_p
;
20490 while (str
!= NULL
&& *str
!= 0)
20492 const struct arm_option_cpu_value_table
* opt
;
20498 as_bad (_("invalid architectural extension"));
20503 ext
= strchr (str
, '+');
20506 optlen
= ext
- str
;
20508 optlen
= strlen (str
);
20512 as_bad (_("missing architectural extension"));
20516 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20517 if (strncmp (opt
->name
, str
, optlen
) == 0)
20519 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20523 if (opt
->name
== NULL
)
20525 as_bad (_("unknown architectural extension `%s'"), str
);
20536 arm_parse_cpu (char * str
)
20538 const struct arm_cpu_option_table
* opt
;
20539 char * ext
= strchr (str
, '+');
20543 optlen
= ext
- str
;
20545 optlen
= strlen (str
);
20549 as_bad (_("missing cpu name `%s'"), str
);
20553 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20554 if (strncmp (opt
->name
, str
, optlen
) == 0)
20556 mcpu_cpu_opt
= &opt
->value
;
20557 mcpu_fpu_opt
= &opt
->default_fpu
;
20558 if (opt
->canonical_name
)
20559 strcpy (selected_cpu_name
, opt
->canonical_name
);
20563 for (i
= 0; i
< optlen
; i
++)
20564 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20565 selected_cpu_name
[i
] = 0;
20569 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20574 as_bad (_("unknown cpu `%s'"), str
);
20579 arm_parse_arch (char * str
)
20581 const struct arm_arch_option_table
*opt
;
20582 char *ext
= strchr (str
, '+');
20586 optlen
= ext
- str
;
20588 optlen
= strlen (str
);
20592 as_bad (_("missing architecture name `%s'"), str
);
20596 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20597 if (streq (opt
->name
, str
))
20599 march_cpu_opt
= &opt
->value
;
20600 march_fpu_opt
= &opt
->default_fpu
;
20601 strcpy (selected_cpu_name
, opt
->name
);
20604 return arm_parse_extension (ext
, &march_cpu_opt
);
20609 as_bad (_("unknown architecture `%s'\n"), str
);
20614 arm_parse_fpu (char * str
)
20616 const struct arm_option_cpu_value_table
* opt
;
20618 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20619 if (streq (opt
->name
, str
))
20621 mfpu_opt
= &opt
->value
;
20625 as_bad (_("unknown floating point format `%s'\n"), str
);
20630 arm_parse_float_abi (char * str
)
20632 const struct arm_option_value_table
* opt
;
20634 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20635 if (streq (opt
->name
, str
))
20637 mfloat_abi_opt
= opt
->value
;
20641 as_bad (_("unknown floating point abi `%s'\n"), str
);
20647 arm_parse_eabi (char * str
)
20649 const struct arm_option_value_table
*opt
;
20651 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20652 if (streq (opt
->name
, str
))
20654 meabi_flags
= opt
->value
;
20657 as_bad (_("unknown EABI `%s'\n"), str
);
20662 struct arm_long_option_table arm_long_opts
[] =
20664 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20665 arm_parse_cpu
, NULL
},
20666 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20667 arm_parse_arch
, NULL
},
20668 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20669 arm_parse_fpu
, NULL
},
20670 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20671 arm_parse_float_abi
, NULL
},
20673 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
20674 arm_parse_eabi
, NULL
},
20676 {NULL
, NULL
, 0, NULL
}
20680 md_parse_option (int c
, char * arg
)
20682 struct arm_option_table
*opt
;
20683 const struct arm_legacy_option_table
*fopt
;
20684 struct arm_long_option_table
*lopt
;
20690 target_big_endian
= 1;
20696 target_big_endian
= 0;
20700 case OPTION_FIX_V4BX
:
20705 /* Listing option. Just ignore these, we don't support additional
20710 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20712 if (c
== opt
->option
[0]
20713 && ((arg
== NULL
&& opt
->option
[1] == 0)
20714 || streq (arg
, opt
->option
+ 1)))
20716 /* If the option is deprecated, tell the user. */
20717 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
20718 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20719 arg
? arg
: "", _(opt
->deprecated
));
20721 if (opt
->var
!= NULL
)
20722 *opt
->var
= opt
->value
;
20728 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20730 if (c
== fopt
->option
[0]
20731 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20732 || streq (arg
, fopt
->option
+ 1)))
20734 /* If the option is deprecated, tell the user. */
20735 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
20736 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20737 arg
? arg
: "", _(fopt
->deprecated
));
20739 if (fopt
->var
!= NULL
)
20740 *fopt
->var
= &fopt
->value
;
20746 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20748 /* These options are expected to have an argument. */
20749 if (c
== lopt
->option
[0]
20751 && strncmp (arg
, lopt
->option
+ 1,
20752 strlen (lopt
->option
+ 1)) == 0)
20754 /* If the option is deprecated, tell the user. */
20755 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
20756 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20757 _(lopt
->deprecated
));
20759 /* Call the sup-option parser. */
20760 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20771 md_show_usage (FILE * fp
)
20773 struct arm_option_table
*opt
;
20774 struct arm_long_option_table
*lopt
;
20776 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20778 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20779 if (opt
->help
!= NULL
)
20780 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20782 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20783 if (lopt
->help
!= NULL
)
20784 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20788 -EB assemble code for a big-endian cpu\n"));
20793 -EL assemble code for a little-endian cpu\n"));
20797 --fix-v4bx Allow BX in ARMv4 code\n"));
20805 arm_feature_set flags
;
20806 } cpu_arch_ver_table
;
20808 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20809 least features first. */
20810 static const cpu_arch_ver_table cpu_arch_ver
[] =
20816 {4, ARM_ARCH_V5TE
},
20817 {5, ARM_ARCH_V5TEJ
},
20821 {11, ARM_ARCH_V6M
},
20822 {8, ARM_ARCH_V6T2
},
20823 {10, ARM_ARCH_V7A
},
20824 {10, ARM_ARCH_V7R
},
20825 {10, ARM_ARCH_V7M
},
20829 /* Set an attribute if it has not already been set by the user. */
20831 aeabi_set_attribute_int (int tag
, int value
)
20834 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
20835 || !attributes_set_explicitly
[tag
])
20836 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
20840 aeabi_set_attribute_string (int tag
, const char *value
)
20843 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
20844 || !attributes_set_explicitly
[tag
])
20845 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
20848 /* Set the public EABI object attributes. */
20850 aeabi_set_public_attributes (void)
20853 arm_feature_set flags
;
20854 arm_feature_set tmp
;
20855 const cpu_arch_ver_table
*p
;
20857 /* Choose the architecture based on the capabilities of the requested cpu
20858 (if any) and/or the instructions actually used. */
20859 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20860 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20861 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20862 /*Allow the user to override the reported architecture. */
20865 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20866 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20871 for (p
= cpu_arch_ver
; p
->val
; p
++)
20873 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20876 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20880 /* Tag_CPU_name. */
20881 if (selected_cpu_name
[0])
20885 p
= selected_cpu_name
;
20886 if (strncmp (p
, "armv", 4) == 0)
20891 for (i
= 0; p
[i
]; i
++)
20892 p
[i
] = TOUPPER (p
[i
]);
20894 aeabi_set_attribute_string (Tag_CPU_name
, p
);
20896 /* Tag_CPU_arch. */
20897 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
20898 /* Tag_CPU_arch_profile. */
20899 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20900 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
20901 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20902 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
20903 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
20904 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
20905 /* Tag_ARM_ISA_use. */
20906 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
20908 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
20909 /* Tag_THUMB_ISA_use. */
20910 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
20912 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
20913 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
20914 /* Tag_VFP_arch. */
20915 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
20916 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
20917 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3
))
20918 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
20919 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
20920 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
20921 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
20922 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
20923 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
20924 /* Tag_WMMX_arch. */
20925 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
20926 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
20927 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
20928 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
20929 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
20930 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
20931 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
20932 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
20933 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_fp16
))
20934 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
20937 /* Add the default contents for the .ARM.attributes section. */
20941 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20944 aeabi_set_public_attributes ();
20946 #endif /* OBJ_ELF */
20949 /* Parse a .cpu directive. */
20952 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20954 const struct arm_cpu_option_table
*opt
;
20958 name
= input_line_pointer
;
20959 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20960 input_line_pointer
++;
20961 saved_char
= *input_line_pointer
;
20962 *input_line_pointer
= 0;
20964 /* Skip the first "all" entry. */
20965 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20966 if (streq (opt
->name
, name
))
20968 mcpu_cpu_opt
= &opt
->value
;
20969 selected_cpu
= opt
->value
;
20970 if (opt
->canonical_name
)
20971 strcpy (selected_cpu_name
, opt
->canonical_name
);
20975 for (i
= 0; opt
->name
[i
]; i
++)
20976 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20977 selected_cpu_name
[i
] = 0;
20979 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20980 *input_line_pointer
= saved_char
;
20981 demand_empty_rest_of_line ();
20984 as_bad (_("unknown cpu `%s'"), name
);
20985 *input_line_pointer
= saved_char
;
20986 ignore_rest_of_line ();
20990 /* Parse a .arch directive. */
20993 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20995 const struct arm_arch_option_table
*opt
;
20999 name
= input_line_pointer
;
21000 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21001 input_line_pointer
++;
21002 saved_char
= *input_line_pointer
;
21003 *input_line_pointer
= 0;
21005 /* Skip the first "all" entry. */
21006 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
21007 if (streq (opt
->name
, name
))
21009 mcpu_cpu_opt
= &opt
->value
;
21010 selected_cpu
= opt
->value
;
21011 strcpy (selected_cpu_name
, opt
->name
);
21012 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21013 *input_line_pointer
= saved_char
;
21014 demand_empty_rest_of_line ();
21018 as_bad (_("unknown architecture `%s'\n"), name
);
21019 *input_line_pointer
= saved_char
;
21020 ignore_rest_of_line ();
21024 /* Parse a .object_arch directive. */
21027 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
21029 const struct arm_arch_option_table
*opt
;
21033 name
= input_line_pointer
;
21034 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21035 input_line_pointer
++;
21036 saved_char
= *input_line_pointer
;
21037 *input_line_pointer
= 0;
21039 /* Skip the first "all" entry. */
21040 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
21041 if (streq (opt
->name
, name
))
21043 object_arch
= &opt
->value
;
21044 *input_line_pointer
= saved_char
;
21045 demand_empty_rest_of_line ();
21049 as_bad (_("unknown architecture `%s'\n"), name
);
21050 *input_line_pointer
= saved_char
;
21051 ignore_rest_of_line ();
21054 /* Parse a .fpu directive. */
21057 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
21059 const struct arm_option_cpu_value_table
*opt
;
21063 name
= input_line_pointer
;
21064 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21065 input_line_pointer
++;
21066 saved_char
= *input_line_pointer
;
21067 *input_line_pointer
= 0;
21069 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
21070 if (streq (opt
->name
, name
))
21072 mfpu_opt
= &opt
->value
;
21073 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21074 *input_line_pointer
= saved_char
;
21075 demand_empty_rest_of_line ();
21079 as_bad (_("unknown floating point format `%s'\n"), name
);
21080 *input_line_pointer
= saved_char
;
21081 ignore_rest_of_line ();
21084 /* Copy symbol information. */
21087 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
21089 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
21093 /* Given a symbolic attribute NAME, return the proper integer value.
21094 Returns -1 if the attribute is not known. */
21097 arm_convert_symbolic_attribute (const char *name
)
21099 static const struct
21104 attribute_table
[] =
21106 /* When you modify this table you should
21107 also modify the list in doc/c-arm.texi. */
21108 #define T(tag) {#tag, tag}
21109 T (Tag_CPU_raw_name
),
21112 T (Tag_CPU_arch_profile
),
21113 T (Tag_ARM_ISA_use
),
21114 T (Tag_THUMB_ISA_use
),
21117 T (Tag_Advanced_SIMD_arch
),
21118 T (Tag_PCS_config
),
21119 T (Tag_ABI_PCS_R9_use
),
21120 T (Tag_ABI_PCS_RW_data
),
21121 T (Tag_ABI_PCS_RO_data
),
21122 T (Tag_ABI_PCS_GOT_use
),
21123 T (Tag_ABI_PCS_wchar_t
),
21124 T (Tag_ABI_FP_rounding
),
21125 T (Tag_ABI_FP_denormal
),
21126 T (Tag_ABI_FP_exceptions
),
21127 T (Tag_ABI_FP_user_exceptions
),
21128 T (Tag_ABI_FP_number_model
),
21129 T (Tag_ABI_align8_needed
),
21130 T (Tag_ABI_align8_preserved
),
21131 T (Tag_ABI_enum_size
),
21132 T (Tag_ABI_HardFP_use
),
21133 T (Tag_ABI_VFP_args
),
21134 T (Tag_ABI_WMMX_args
),
21135 T (Tag_ABI_optimization_goals
),
21136 T (Tag_ABI_FP_optimization_goals
),
21137 T (Tag_compatibility
),
21138 T (Tag_CPU_unaligned_access
),
21139 T (Tag_VFP_HP_extension
),
21140 T (Tag_ABI_FP_16bit_format
),
21141 T (Tag_nodefaults
),
21142 T (Tag_also_compatible_with
),
21143 T (Tag_conformance
),
21145 T (Tag_Virtualization_use
),
21146 T (Tag_MPextension_use
)
21154 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
21155 if (strcmp (name
, attribute_table
[i
].name
) == 0)
21156 return attribute_table
[i
].tag
;
21160 #endif /* OBJ_ELF */