1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
203 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
204 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
206 static const arm_feature_set arm_arch_any
= ARM_ANY
;
207 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
209 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
212 static const arm_feature_set arm_cext_iwmmxt2
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
214 static const arm_feature_set arm_cext_iwmmxt
=
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
216 static const arm_feature_set arm_cext_xscale
=
217 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
218 static const arm_feature_set arm_cext_maverick
=
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
220 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
221 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
222 static const arm_feature_set fpu_vfp_ext_v1xd
=
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
224 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
225 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
226 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
227 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_ext_d32
=
229 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
230 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
232 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
233 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
234 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
235 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static int mfloat_abi_opt
= -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name
[16];
244 static int meabi_flags
= EABI_DEFAULT
;
246 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
249 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
254 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
259 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
260 symbolS
* GOT_symbol
;
263 /* 0: assemble for ARM,
264 1: assemble for Thumb,
265 2: assemble for Thumb even though target CPU does not support thumb
267 static int thumb_mode
= 0;
268 /* A value distinct from the possible values for thumb_mode that we
269 can use to record whether thumb_mode has been copied into the
270 tc_frag_data field of a frag. */
271 #define MODE_RECORDED (1 << 4)
273 /* Specifies the intrinsic IT insn behavior mode. */
274 enum implicit_it_mode
276 IMPLICIT_IT_MODE_NEVER
= 0x00,
277 IMPLICIT_IT_MODE_ARM
= 0x01,
278 IMPLICIT_IT_MODE_THUMB
= 0x02,
279 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
281 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
283 /* If unified_syntax is true, we are processing the new unified
284 ARM/Thumb syntax. Important differences from the old ARM mode:
286 - Immediate operands do not require a # prefix.
287 - Conditional affixes always appear at the end of the
288 instruction. (For backward compatibility, those instructions
289 that formerly had them in the middle, continue to accept them
291 - The IT instruction may appear, and if it does is validated
292 against subsequent conditional affixes. It does not generate
295 Important differences from the old Thumb mode:
297 - Immediate operands do not require a # prefix.
298 - Most of the V6T2 instructions are only available in unified mode.
299 - The .N and .W suffixes are recognized and honored (it is an error
300 if they cannot be honored).
301 - All instructions set the flags if and only if they have an 's' affix.
302 - Conditional affixes may be used. They are validated against
303 preceding IT instructions. Unlike ARM mode, you cannot use a
304 conditional affix except in the scope of an IT instruction. */
306 static bfd_boolean unified_syntax
= FALSE
;
321 enum neon_el_type type
;
325 #define NEON_MAX_TYPE_ELS 4
329 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
333 enum it_instruction_type
338 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
339 if inside, should be the last one. */
340 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
341 i.e. BKPT and NOP. */
342 IT_INSN
/* The IT insn has been parsed. */
348 unsigned long instruction
;
352 /* "uncond_value" is set to the value in place of the conditional field in
353 unconditional versions of the instruction, or -1 if nothing is
356 struct neon_type vectype
;
357 /* This does not indicate an actual NEON instruction, only that
358 the mnemonic accepts neon-style type suffixes. */
360 /* Set to the opcode if the instruction needs relaxation.
361 Zero if the instruction is not relaxed. */
365 bfd_reloc_code_real_type type
;
370 enum it_instruction_type it_insn_type
;
376 struct neon_type_el vectype
;
377 unsigned present
: 1; /* Operand present. */
378 unsigned isreg
: 1; /* Operand was a register. */
379 unsigned immisreg
: 1; /* .imm field is a second register. */
380 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
381 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
382 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
383 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
384 instructions. This allows us to disambiguate ARM <-> vector insns. */
385 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
386 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
387 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
388 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
389 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
390 unsigned writeback
: 1; /* Operand has trailing ! */
391 unsigned preind
: 1; /* Preindexed address. */
392 unsigned postind
: 1; /* Postindexed address. */
393 unsigned negative
: 1; /* Index register was negated. */
394 unsigned shifted
: 1; /* Shift applied to operation. */
395 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
399 static struct arm_it inst
;
401 #define NUM_FLOAT_VALS 8
403 const char * fp_const
[] =
405 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
408 /* Number of littlenums required to hold an extended precision number. */
409 #define MAX_LITTLENUMS 6
411 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
421 #define CP_T_X 0x00008000
422 #define CP_T_Y 0x00400000
424 #define CONDS_BIT 0x00100000
425 #define LOAD_BIT 0x00100000
427 #define DOUBLE_LOAD_FLAG 0x00000001
431 const char * template_name
;
435 #define COND_ALWAYS 0xE
439 const char * template_name
;
443 struct asm_barrier_opt
445 const char * template_name
;
449 /* The bit that distinguishes CPSR and SPSR. */
450 #define SPSR_BIT (1 << 22)
452 /* The individual PSR flag bits. */
453 #define PSR_c (1 << 16)
454 #define PSR_x (1 << 17)
455 #define PSR_s (1 << 18)
456 #define PSR_f (1 << 19)
461 bfd_reloc_code_real_type reloc
;
466 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
467 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
472 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
475 /* Bits for DEFINED field in neon_typed_alias. */
476 #define NTA_HASTYPE 1
477 #define NTA_HASINDEX 2
479 struct neon_typed_alias
481 unsigned char defined
;
483 struct neon_type_el eltype
;
486 /* ARM register categories. This includes coprocessor numbers and various
487 architecture extensions' registers. */
514 /* Structure for a hash table entry for a register.
515 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
516 information which states whether a vector type or index is specified (for a
517 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
523 unsigned char builtin
;
524 struct neon_typed_alias
* neon
;
527 /* Diagnostics used when we don't get a register of the expected type. */
528 const char * const reg_expected_msgs
[] =
530 N_("ARM register expected"),
531 N_("bad or missing co-processor number"),
532 N_("co-processor register expected"),
533 N_("FPA register expected"),
534 N_("VFP single precision register expected"),
535 N_("VFP/Neon double precision register expected"),
536 N_("Neon quad precision register expected"),
537 N_("VFP single or double precision register expected"),
538 N_("Neon double or quad precision register expected"),
539 N_("VFP single, double or Neon quad precision register expected"),
540 N_("VFP system register expected"),
541 N_("Maverick MVF register expected"),
542 N_("Maverick MVD register expected"),
543 N_("Maverick MVFX register expected"),
544 N_("Maverick MVDX register expected"),
545 N_("Maverick MVAX register expected"),
546 N_("Maverick DSPSC register expected"),
547 N_("iWMMXt data register expected"),
548 N_("iWMMXt control register expected"),
549 N_("iWMMXt scalar register expected"),
550 N_("XScale accumulator register expected"),
553 /* Some well known registers that we refer to directly elsewhere. */
558 /* ARM instructions take 4bytes in the object file, Thumb instructions
564 /* Basic string to match. */
565 const char * template_name
;
567 /* Parameters to instruction. */
568 unsigned int operands
[8];
570 /* Conditional tag - see opcode_lookup. */
571 unsigned int tag
: 4;
573 /* Basic instruction code. */
574 unsigned int avalue
: 28;
576 /* Thumb-format instruction code. */
579 /* Which architecture variant provides this instruction. */
580 const arm_feature_set
* avariant
;
581 const arm_feature_set
* tvariant
;
583 /* Function to call to encode instruction in ARM format. */
584 void (* aencode
) (void);
586 /* Function to call to encode instruction in Thumb format. */
587 void (* tencode
) (void);
590 /* Defines for various bits that we will want to toggle. */
591 #define INST_IMMEDIATE 0x02000000
592 #define OFFSET_REG 0x02000000
593 #define HWOFFSET_IMM 0x00400000
594 #define SHIFT_BY_REG 0x00000010
595 #define PRE_INDEX 0x01000000
596 #define INDEX_UP 0x00800000
597 #define WRITE_BACK 0x00200000
598 #define LDM_TYPE_2_OR_3 0x00400000
599 #define CPSI_MMOD 0x00020000
601 #define LITERAL_MASK 0xf000f000
602 #define OPCODE_MASK 0xfe1fffff
603 #define V4_STR_BIT 0x00000020
605 #define T2_SUBS_PC_LR 0xf3de8f00
607 #define DATA_OP_SHIFT 21
609 #define T2_OPCODE_MASK 0xfe1fffff
610 #define T2_DATA_OP_SHIFT 21
612 /* Codes to distinguish the arithmetic instructions. */
623 #define OPCODE_CMP 10
624 #define OPCODE_CMN 11
625 #define OPCODE_ORR 12
626 #define OPCODE_MOV 13
627 #define OPCODE_BIC 14
628 #define OPCODE_MVN 15
630 #define T2_OPCODE_AND 0
631 #define T2_OPCODE_BIC 1
632 #define T2_OPCODE_ORR 2
633 #define T2_OPCODE_ORN 3
634 #define T2_OPCODE_EOR 4
635 #define T2_OPCODE_ADD 8
636 #define T2_OPCODE_ADC 10
637 #define T2_OPCODE_SBC 11
638 #define T2_OPCODE_SUB 13
639 #define T2_OPCODE_RSB 14
641 #define T_OPCODE_MUL 0x4340
642 #define T_OPCODE_TST 0x4200
643 #define T_OPCODE_CMN 0x42c0
644 #define T_OPCODE_NEG 0x4240
645 #define T_OPCODE_MVN 0x43c0
647 #define T_OPCODE_ADD_R3 0x1800
648 #define T_OPCODE_SUB_R3 0x1a00
649 #define T_OPCODE_ADD_HI 0x4400
650 #define T_OPCODE_ADD_ST 0xb000
651 #define T_OPCODE_SUB_ST 0xb080
652 #define T_OPCODE_ADD_SP 0xa800
653 #define T_OPCODE_ADD_PC 0xa000
654 #define T_OPCODE_ADD_I8 0x3000
655 #define T_OPCODE_SUB_I8 0x3800
656 #define T_OPCODE_ADD_I3 0x1c00
657 #define T_OPCODE_SUB_I3 0x1e00
659 #define T_OPCODE_ASR_R 0x4100
660 #define T_OPCODE_LSL_R 0x4080
661 #define T_OPCODE_LSR_R 0x40c0
662 #define T_OPCODE_ROR_R 0x41c0
663 #define T_OPCODE_ASR_I 0x1000
664 #define T_OPCODE_LSL_I 0x0000
665 #define T_OPCODE_LSR_I 0x0800
667 #define T_OPCODE_MOV_I8 0x2000
668 #define T_OPCODE_CMP_I8 0x2800
669 #define T_OPCODE_CMP_LR 0x4280
670 #define T_OPCODE_MOV_HR 0x4600
671 #define T_OPCODE_CMP_HR 0x4500
673 #define T_OPCODE_LDR_PC 0x4800
674 #define T_OPCODE_LDR_SP 0x9800
675 #define T_OPCODE_STR_SP 0x9000
676 #define T_OPCODE_LDR_IW 0x6800
677 #define T_OPCODE_STR_IW 0x6000
678 #define T_OPCODE_LDR_IH 0x8800
679 #define T_OPCODE_STR_IH 0x8000
680 #define T_OPCODE_LDR_IB 0x7800
681 #define T_OPCODE_STR_IB 0x7000
682 #define T_OPCODE_LDR_RW 0x5800
683 #define T_OPCODE_STR_RW 0x5000
684 #define T_OPCODE_LDR_RH 0x5a00
685 #define T_OPCODE_STR_RH 0x5200
686 #define T_OPCODE_LDR_RB 0x5c00
687 #define T_OPCODE_STR_RB 0x5400
689 #define T_OPCODE_PUSH 0xb400
690 #define T_OPCODE_POP 0xbc00
692 #define T_OPCODE_BRANCH 0xe000
694 #define THUMB_SIZE 2 /* Size of thumb instruction. */
695 #define THUMB_PP_PC_LR 0x0100
696 #define THUMB_LOAD_BIT 0x0800
697 #define THUMB2_LOAD_BIT 0x00100000
699 #define BAD_ARGS _("bad arguments to instruction")
700 #define BAD_SP _("r13 not allowed here")
701 #define BAD_PC _("r15 not allowed here")
702 #define BAD_COND _("instruction cannot be conditional")
703 #define BAD_OVERLAP _("registers may not be the same")
704 #define BAD_HIREG _("lo register required")
705 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
706 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
707 #define BAD_BRANCH _("branch must be last instruction in IT block")
708 #define BAD_NOT_IT _("instruction not allowed in IT block")
709 #define BAD_FPU _("selected FPU does not support instruction")
710 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
711 #define BAD_IT_COND _("incorrect condition in IT block")
712 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
713 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
714 #define BAD_PC_ADDRESSING \
715 _("cannot use register index with PC-relative addressing")
716 #define BAD_PC_WRITEBACK \
717 _("cannot use writeback with PC-relative addressing")
719 static struct hash_control
* arm_ops_hsh
;
720 static struct hash_control
* arm_cond_hsh
;
721 static struct hash_control
* arm_shift_hsh
;
722 static struct hash_control
* arm_psr_hsh
;
723 static struct hash_control
* arm_v7m_psr_hsh
;
724 static struct hash_control
* arm_reg_hsh
;
725 static struct hash_control
* arm_reloc_hsh
;
726 static struct hash_control
* arm_barrier_opt_hsh
;
728 /* Stuff needed to resolve the label ambiguity
737 symbolS
* last_label_seen
;
738 static int label_is_thumb_function_name
= FALSE
;
740 /* Literal pool structure. Held on a per-section
741 and per-sub-section basis. */
743 #define MAX_LITERAL_POOL_SIZE 1024
744 typedef struct literal_pool
746 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
747 unsigned int next_free_entry
;
752 struct literal_pool
* next
;
755 /* Pointer to a linked list of literal pools. */
756 literal_pool
* list_of_pools
= NULL
;
759 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
761 static struct current_it now_it
;
765 now_it_compatible (int cond
)
767 return (cond
& ~1) == (now_it
.cc
& ~1);
771 conditional_insn (void)
773 return inst
.cond
!= COND_ALWAYS
;
776 static int in_it_block (void);
778 static int handle_it_state (void);
780 static void force_automatic_it_block_close (void);
782 static void it_fsm_post_encode (void);
784 #define set_it_insn_type(type) \
787 inst.it_insn_type = type; \
788 if (handle_it_state () == FAIL) \
793 #define set_it_insn_type_nonvoid(type, failret) \
796 inst.it_insn_type = type; \
797 if (handle_it_state () == FAIL) \
802 #define set_it_insn_type_last() \
805 if (inst.cond == COND_ALWAYS) \
806 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
808 set_it_insn_type (INSIDE_IT_LAST_INSN); \
814 /* This array holds the chars that always start a comment. If the
815 pre-processor is disabled, these aren't very useful. */
816 const char comment_chars
[] = "@";
818 /* This array holds the chars that only start a comment at the beginning of
819 a line. If the line seems to have the form '# 123 filename'
820 .line and .file directives will appear in the pre-processed output. */
821 /* Note that input_file.c hand checks for '#' at the beginning of the
822 first line of the input file. This is because the compiler outputs
823 #NO_APP at the beginning of its output. */
824 /* Also note that comments like this one will always work. */
825 const char line_comment_chars
[] = "#";
827 const char line_separator_chars
[] = ";";
829 /* Chars that can be used to separate mant
830 from exp in floating point numbers. */
831 const char EXP_CHARS
[] = "eE";
833 /* Chars that mean this number is a floating point constant. */
837 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
839 /* Prefix characters that indicate the start of an immediate
841 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
843 /* Separator character handling. */
845 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
848 skip_past_char (char ** str
, char c
)
859 #define skip_past_comma(str) skip_past_char (str, ',')
861 /* Arithmetic expressions (possibly involving symbols). */
863 /* Return TRUE if anything in the expression is a bignum. */
866 walk_no_bignums (symbolS
* sp
)
868 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
871 if (symbol_get_value_expression (sp
)->X_add_symbol
)
873 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
874 || (symbol_get_value_expression (sp
)->X_op_symbol
875 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
881 static int in_my_get_expression
= 0;
883 /* Third argument to my_get_expression. */
884 #define GE_NO_PREFIX 0
885 #define GE_IMM_PREFIX 1
886 #define GE_OPT_PREFIX 2
887 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
888 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
889 #define GE_OPT_PREFIX_BIG 3
892 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
897 /* In unified syntax, all prefixes are optional. */
899 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
904 case GE_NO_PREFIX
: break;
906 if (!is_immediate_prefix (**str
))
908 inst
.error
= _("immediate expression requires a # prefix");
914 case GE_OPT_PREFIX_BIG
:
915 if (is_immediate_prefix (**str
))
921 memset (ep
, 0, sizeof (expressionS
));
923 save_in
= input_line_pointer
;
924 input_line_pointer
= *str
;
925 in_my_get_expression
= 1;
926 seg
= expression (ep
);
927 in_my_get_expression
= 0;
929 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
931 /* We found a bad or missing expression in md_operand(). */
932 *str
= input_line_pointer
;
933 input_line_pointer
= save_in
;
934 if (inst
.error
== NULL
)
935 inst
.error
= (ep
->X_op
== O_absent
936 ? _("missing expression") :_("bad expression"));
941 if (seg
!= absolute_section
942 && seg
!= text_section
943 && seg
!= data_section
944 && seg
!= bss_section
945 && seg
!= undefined_section
)
947 inst
.error
= _("bad segment");
948 *str
= input_line_pointer
;
949 input_line_pointer
= save_in
;
956 /* Get rid of any bignums now, so that we don't generate an error for which
957 we can't establish a line number later on. Big numbers are never valid
958 in instructions, which is where this routine is always called. */
959 if (prefix_mode
!= GE_OPT_PREFIX_BIG
960 && (ep
->X_op
== O_big
962 && (walk_no_bignums (ep
->X_add_symbol
)
964 && walk_no_bignums (ep
->X_op_symbol
))))))
966 inst
.error
= _("invalid constant");
967 *str
= input_line_pointer
;
968 input_line_pointer
= save_in
;
972 *str
= input_line_pointer
;
973 input_line_pointer
= save_in
;
977 /* Turn a string in input_line_pointer into a floating point constant
978 of type TYPE, and store the appropriate bytes in *LITP. The number
979 of LITTLENUMS emitted is stored in *SIZEP. An error message is
980 returned, or NULL on OK.
982 Note that fp constants aren't represent in the normal way on the ARM.
983 In big endian mode, things are as expected. However, in little endian
984 mode fp constants are big-endian word-wise, and little-endian byte-wise
985 within the words. For example, (double) 1.1 in big endian mode is
986 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
987 the byte sequence 99 99 f1 3f 9a 99 99 99.
989 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
992 md_atof (int type
, char * litP
, int * sizeP
)
995 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1027 return _("Unrecognized or unsupported floating point constant");
1030 t
= atof_ieee (input_line_pointer
, type
, words
);
1032 input_line_pointer
= t
;
1033 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1035 if (target_big_endian
)
1037 for (i
= 0; i
< prec
; i
++)
1039 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1040 litP
+= sizeof (LITTLENUM_TYPE
);
1045 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1046 for (i
= prec
- 1; i
>= 0; i
--)
1048 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1049 litP
+= sizeof (LITTLENUM_TYPE
);
1052 /* For a 4 byte float the order of elements in `words' is 1 0.
1053 For an 8 byte float the order is 1 0 3 2. */
1054 for (i
= 0; i
< prec
; i
+= 2)
1056 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1057 sizeof (LITTLENUM_TYPE
));
1058 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1059 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1060 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1067 /* We handle all bad expressions here, so that we can report the faulty
1068 instruction in the error message. */
1070 md_operand (expressionS
* exp
)
1072 if (in_my_get_expression
)
1073 exp
->X_op
= O_illegal
;
1076 /* Immediate values. */
1078 /* Generic immediate-value read function for use in directives.
1079 Accepts anything that 'expression' can fold to a constant.
1080 *val receives the number. */
1083 immediate_for_directive (int *val
)
1086 exp
.X_op
= O_illegal
;
1088 if (is_immediate_prefix (*input_line_pointer
))
1090 input_line_pointer
++;
1094 if (exp
.X_op
!= O_constant
)
1096 as_bad (_("expected #constant"));
1097 ignore_rest_of_line ();
1100 *val
= exp
.X_add_number
;
1105 /* Register parsing. */
1107 /* Generic register parser. CCP points to what should be the
1108 beginning of a register name. If it is indeed a valid register
1109 name, advance CCP over it and return the reg_entry structure;
1110 otherwise return NULL. Does not issue diagnostics. */
1112 static struct reg_entry
*
1113 arm_reg_parse_multi (char **ccp
)
1117 struct reg_entry
*reg
;
1119 #ifdef REGISTER_PREFIX
1120 if (*start
!= REGISTER_PREFIX
)
1124 #ifdef OPTIONAL_REGISTER_PREFIX
1125 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1130 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1135 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1137 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1147 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1148 enum arm_reg_type type
)
1150 /* Alternative syntaxes are accepted for a few register classes. */
1157 /* Generic coprocessor register names are allowed for these. */
1158 if (reg
&& reg
->type
== REG_TYPE_CN
)
1163 /* For backward compatibility, a bare number is valid here. */
1165 unsigned long processor
= strtoul (start
, ccp
, 10);
1166 if (*ccp
!= start
&& processor
<= 15)
1170 case REG_TYPE_MMXWC
:
1171 /* WC includes WCG. ??? I'm not sure this is true for all
1172 instructions that take WC registers. */
1173 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1184 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1185 return value is the register number or FAIL. */
1188 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1191 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1194 /* Do not allow a scalar (reg+index) to parse as a register. */
1195 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1198 if (reg
&& reg
->type
== type
)
1201 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1208 /* Parse a Neon type specifier. *STR should point at the leading '.'
1209 character. Does no verification at this stage that the type fits the opcode
1216 Can all be legally parsed by this function.
1218 Fills in neon_type struct pointer with parsed information, and updates STR
1219 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1220 type, FAIL if not. */
1223 parse_neon_type (struct neon_type
*type
, char **str
)
1230 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1232 enum neon_el_type thistype
= NT_untyped
;
1233 unsigned thissize
= -1u;
1240 /* Just a size without an explicit type. */
1244 switch (TOLOWER (*ptr
))
1246 case 'i': thistype
= NT_integer
; break;
1247 case 'f': thistype
= NT_float
; break;
1248 case 'p': thistype
= NT_poly
; break;
1249 case 's': thistype
= NT_signed
; break;
1250 case 'u': thistype
= NT_unsigned
; break;
1252 thistype
= NT_float
;
1257 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1263 /* .f is an abbreviation for .f32. */
1264 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1269 thissize
= strtoul (ptr
, &ptr
, 10);
1271 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1274 as_bad (_("bad size %d in type specifier"), thissize
);
1282 type
->el
[type
->elems
].type
= thistype
;
1283 type
->el
[type
->elems
].size
= thissize
;
1288 /* Empty/missing type is not a successful parse. */
1289 if (type
->elems
== 0)
1297 /* Errors may be set multiple times during parsing or bit encoding
1298 (particularly in the Neon bits), but usually the earliest error which is set
1299 will be the most meaningful. Avoid overwriting it with later (cascading)
1300 errors by calling this function. */
1303 first_error (const char *err
)
1309 /* Parse a single type, e.g. ".s32", leading period included. */
1311 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1314 struct neon_type optype
;
1318 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1320 if (optype
.elems
== 1)
1321 *vectype
= optype
.el
[0];
1324 first_error (_("only one type should be specified for operand"));
1330 first_error (_("vector type expected"));
1342 /* Special meanings for indices (which have a range of 0-7), which will fit into
1345 #define NEON_ALL_LANES 15
1346 #define NEON_INTERLEAVE_LANES 14
1348 /* Parse either a register or a scalar, with an optional type. Return the
1349 register number, and optionally fill in the actual type of the register
1350 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1351 type/index information in *TYPEINFO. */
1354 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1355 enum arm_reg_type
*rtype
,
1356 struct neon_typed_alias
*typeinfo
)
1359 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1360 struct neon_typed_alias atype
;
1361 struct neon_type_el parsetype
;
1365 atype
.eltype
.type
= NT_invtype
;
1366 atype
.eltype
.size
= -1;
1368 /* Try alternate syntax for some types of register. Note these are mutually
1369 exclusive with the Neon syntax extensions. */
1372 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1380 /* Undo polymorphism when a set of register types may be accepted. */
1381 if ((type
== REG_TYPE_NDQ
1382 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1383 || (type
== REG_TYPE_VFSD
1384 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1385 || (type
== REG_TYPE_NSDQ
1386 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1387 || reg
->type
== REG_TYPE_NQ
))
1388 || (type
== REG_TYPE_MMXWC
1389 && (reg
->type
== REG_TYPE_MMXWCG
)))
1390 type
= (enum arm_reg_type
) reg
->type
;
1392 if (type
!= reg
->type
)
1398 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1400 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1402 first_error (_("can't redefine type for operand"));
1405 atype
.defined
|= NTA_HASTYPE
;
1406 atype
.eltype
= parsetype
;
1409 if (skip_past_char (&str
, '[') == SUCCESS
)
1411 if (type
!= REG_TYPE_VFD
)
1413 first_error (_("only D registers may be indexed"));
1417 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1419 first_error (_("can't change index for operand"));
1423 atype
.defined
|= NTA_HASINDEX
;
1425 if (skip_past_char (&str
, ']') == SUCCESS
)
1426 atype
.index
= NEON_ALL_LANES
;
1431 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1433 if (exp
.X_op
!= O_constant
)
1435 first_error (_("constant expression required"));
1439 if (skip_past_char (&str
, ']') == FAIL
)
1442 atype
.index
= exp
.X_add_number
;
1457 /* Like arm_reg_parse, but allow allow the following extra features:
1458 - If RTYPE is non-zero, return the (possibly restricted) type of the
1459 register (e.g. Neon double or quad reg when either has been requested).
1460 - If this is a Neon vector type with additional type information, fill
1461 in the struct pointed to by VECTYPE (if non-NULL).
1462 This function will fault on encountering a scalar. */
1465 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1466 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1468 struct neon_typed_alias atype
;
1470 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1475 /* Do not allow regname(... to parse as a register. */
1479 /* Do not allow a scalar (reg+index) to parse as a register. */
1480 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1482 first_error (_("register operand expected, but got scalar"));
1487 *vectype
= atype
.eltype
;
1494 #define NEON_SCALAR_REG(X) ((X) >> 4)
1495 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1497 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1498 have enough information to be able to do a good job bounds-checking. So, we
1499 just do easy checks here, and do further checks later. */
1502 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1506 struct neon_typed_alias atype
;
1508 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1510 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1513 if (atype
.index
== NEON_ALL_LANES
)
1515 first_error (_("scalar must have an index"));
1518 else if (atype
.index
>= 64 / elsize
)
1520 first_error (_("scalar index out of range"));
1525 *type
= atype
.eltype
;
1529 return reg
* 16 + atype
.index
;
1532 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1535 parse_reg_list (char ** strp
)
1537 char * str
= * strp
;
1541 /* We come back here if we get ranges concatenated by '+' or '|'. */
1556 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1558 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1568 first_error (_("bad range in register list"));
1572 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1574 if (range
& (1 << i
))
1576 (_("Warning: duplicated register (r%d) in register list"),
1584 if (range
& (1 << reg
))
1585 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1587 else if (reg
<= cur_reg
)
1588 as_tsktsk (_("Warning: register range not in ascending order"));
1593 while (skip_past_comma (&str
) != FAIL
1594 || (in_range
= 1, *str
++ == '-'));
1599 first_error (_("missing `}'"));
1607 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1610 if (exp
.X_op
== O_constant
)
1612 if (exp
.X_add_number
1613 != (exp
.X_add_number
& 0x0000ffff))
1615 inst
.error
= _("invalid register mask");
1619 if ((range
& exp
.X_add_number
) != 0)
1621 int regno
= range
& exp
.X_add_number
;
1624 regno
= (1 << regno
) - 1;
1626 (_("Warning: duplicated register (r%d) in register list"),
1630 range
|= exp
.X_add_number
;
1634 if (inst
.reloc
.type
!= 0)
1636 inst
.error
= _("expression too complex");
1640 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1641 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1642 inst
.reloc
.pc_rel
= 0;
1646 if (*str
== '|' || *str
== '+')
1652 while (another_range
);
1658 /* Types of registers in a list. */
1667 /* Parse a VFP register list. If the string is invalid return FAIL.
1668 Otherwise return the number of registers, and set PBASE to the first
1669 register. Parses registers of type ETYPE.
1670 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1671 - Q registers can be used to specify pairs of D registers
1672 - { } can be omitted from around a singleton register list
1673 FIXME: This is not implemented, as it would require backtracking in
1676 This could be done (the meaning isn't really ambiguous), but doesn't
1677 fit in well with the current parsing framework.
1678 - 32 D registers may be used (also true for VFPv3).
1679 FIXME: Types are ignored in these register lists, which is probably a
1683 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1688 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1692 unsigned long mask
= 0;
1697 inst
.error
= _("expecting {");
1706 regtype
= REG_TYPE_VFS
;
1711 regtype
= REG_TYPE_VFD
;
1714 case REGLIST_NEON_D
:
1715 regtype
= REG_TYPE_NDQ
;
1719 if (etype
!= REGLIST_VFP_S
)
1721 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1722 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1726 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1729 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1736 base_reg
= max_regs
;
1740 int setmask
= 1, addregs
= 1;
1742 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1744 if (new_base
== FAIL
)
1746 first_error (_(reg_expected_msgs
[regtype
]));
1750 if (new_base
>= max_regs
)
1752 first_error (_("register out of range in list"));
1756 /* Note: a value of 2 * n is returned for the register Q<n>. */
1757 if (regtype
== REG_TYPE_NQ
)
1763 if (new_base
< base_reg
)
1764 base_reg
= new_base
;
1766 if (mask
& (setmask
<< new_base
))
1768 first_error (_("invalid register list"));
1772 if ((mask
>> new_base
) != 0 && ! warned
)
1774 as_tsktsk (_("register list not in ascending order"));
1778 mask
|= setmask
<< new_base
;
1781 if (*str
== '-') /* We have the start of a range expression */
1787 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1790 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1794 if (high_range
>= max_regs
)
1796 first_error (_("register out of range in list"));
1800 if (regtype
== REG_TYPE_NQ
)
1801 high_range
= high_range
+ 1;
1803 if (high_range
<= new_base
)
1805 inst
.error
= _("register range not in ascending order");
1809 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1811 if (mask
& (setmask
<< new_base
))
1813 inst
.error
= _("invalid register list");
1817 mask
|= setmask
<< new_base
;
1822 while (skip_past_comma (&str
) != FAIL
);
1826 /* Sanity check -- should have raised a parse error above. */
1827 if (count
== 0 || count
> max_regs
)
1832 /* Final test -- the registers must be consecutive. */
1834 for (i
= 0; i
< count
; i
++)
1836 if ((mask
& (1u << i
)) == 0)
1838 inst
.error
= _("non-contiguous register range");
1848 /* True if two alias types are the same. */
1851 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1859 if (a
->defined
!= b
->defined
)
1862 if ((a
->defined
& NTA_HASTYPE
) != 0
1863 && (a
->eltype
.type
!= b
->eltype
.type
1864 || a
->eltype
.size
!= b
->eltype
.size
))
1867 if ((a
->defined
& NTA_HASINDEX
) != 0
1868 && (a
->index
!= b
->index
))
1874 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1875 The base register is put in *PBASE.
1876 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1878 The register stride (minus one) is put in bit 4 of the return value.
1879 Bits [6:5] encode the list length (minus one).
1880 The type of the list elements is put in *ELTYPE, if non-NULL. */
1882 #define NEON_LANE(X) ((X) & 0xf)
1883 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1884 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1887 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1888 struct neon_type_el
*eltype
)
1895 int leading_brace
= 0;
1896 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1897 const char *const incr_error
= _("register stride must be 1 or 2");
1898 const char *const type_error
= _("mismatched element/structure types in list");
1899 struct neon_typed_alias firsttype
;
1901 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1906 struct neon_typed_alias atype
;
1907 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1911 first_error (_(reg_expected_msgs
[rtype
]));
1918 if (rtype
== REG_TYPE_NQ
)
1924 else if (reg_incr
== -1)
1926 reg_incr
= getreg
- base_reg
;
1927 if (reg_incr
< 1 || reg_incr
> 2)
1929 first_error (_(incr_error
));
1933 else if (getreg
!= base_reg
+ reg_incr
* count
)
1935 first_error (_(incr_error
));
1939 if (! neon_alias_types_same (&atype
, &firsttype
))
1941 first_error (_(type_error
));
1945 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1949 struct neon_typed_alias htype
;
1950 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1952 lane
= NEON_INTERLEAVE_LANES
;
1953 else if (lane
!= NEON_INTERLEAVE_LANES
)
1955 first_error (_(type_error
));
1960 else if (reg_incr
!= 1)
1962 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1966 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1969 first_error (_(reg_expected_msgs
[rtype
]));
1972 if (! neon_alias_types_same (&htype
, &firsttype
))
1974 first_error (_(type_error
));
1977 count
+= hireg
+ dregs
- getreg
;
1981 /* If we're using Q registers, we can't use [] or [n] syntax. */
1982 if (rtype
== REG_TYPE_NQ
)
1988 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1992 else if (lane
!= atype
.index
)
1994 first_error (_(type_error
));
1998 else if (lane
== -1)
1999 lane
= NEON_INTERLEAVE_LANES
;
2000 else if (lane
!= NEON_INTERLEAVE_LANES
)
2002 first_error (_(type_error
));
2007 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2009 /* No lane set by [x]. We must be interleaving structures. */
2011 lane
= NEON_INTERLEAVE_LANES
;
2014 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2015 || (count
> 1 && reg_incr
== -1))
2017 first_error (_("error parsing element/structure list"));
2021 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2023 first_error (_("expected }"));
2031 *eltype
= firsttype
.eltype
;
2036 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2039 /* Parse an explicit relocation suffix on an expression. This is
2040 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2041 arm_reloc_hsh contains no entries, so this function can only
2042 succeed if there is no () after the word. Returns -1 on error,
2043 BFD_RELOC_UNUSED if there wasn't any suffix. */
2045 parse_reloc (char **str
)
2047 struct reloc_entry
*r
;
2051 return BFD_RELOC_UNUSED
;
2056 while (*q
&& *q
!= ')' && *q
!= ',')
2061 if ((r
= (struct reloc_entry
*)
2062 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2069 /* Directives: register aliases. */
2071 static struct reg_entry
*
2072 insert_reg_alias (char *str
, unsigned number
, int type
)
2074 struct reg_entry
*new_reg
;
2077 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2079 if (new_reg
->builtin
)
2080 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2082 /* Only warn about a redefinition if it's not defined as the
2084 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2085 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2090 name
= xstrdup (str
);
2091 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2093 new_reg
->name
= name
;
2094 new_reg
->number
= number
;
2095 new_reg
->type
= type
;
2096 new_reg
->builtin
= FALSE
;
2097 new_reg
->neon
= NULL
;
2099 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2106 insert_neon_reg_alias (char *str
, int number
, int type
,
2107 struct neon_typed_alias
*atype
)
2109 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2113 first_error (_("attempt to redefine typed alias"));
2119 reg
->neon
= (struct neon_typed_alias
*)
2120 xmalloc (sizeof (struct neon_typed_alias
));
2121 *reg
->neon
= *atype
;
2125 /* Look for the .req directive. This is of the form:
2127 new_register_name .req existing_register_name
2129 If we find one, or if it looks sufficiently like one that we want to
2130 handle any error here, return TRUE. Otherwise return FALSE. */
2133 create_register_alias (char * newname
, char *p
)
2135 struct reg_entry
*old
;
2136 char *oldname
, *nbuf
;
2139 /* The input scrubber ensures that whitespace after the mnemonic is
2140 collapsed to single spaces. */
2142 if (strncmp (oldname
, " .req ", 6) != 0)
2146 if (*oldname
== '\0')
2149 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2152 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2156 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2157 the desired alias name, and p points to its end. If not, then
2158 the desired alias name is in the global original_case_string. */
2159 #ifdef TC_CASE_SENSITIVE
2162 newname
= original_case_string
;
2163 nlen
= strlen (newname
);
2166 nbuf
= (char *) alloca (nlen
+ 1);
2167 memcpy (nbuf
, newname
, nlen
);
2170 /* Create aliases under the new name as stated; an all-lowercase
2171 version of the new name; and an all-uppercase version of the new
2173 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2175 for (p
= nbuf
; *p
; p
++)
2178 if (strncmp (nbuf
, newname
, nlen
))
2180 /* If this attempt to create an additional alias fails, do not bother
2181 trying to create the all-lower case alias. We will fail and issue
2182 a second, duplicate error message. This situation arises when the
2183 programmer does something like:
2186 The second .req creates the "Foo" alias but then fails to create
2187 the artificial FOO alias because it has already been created by the
2189 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2193 for (p
= nbuf
; *p
; p
++)
2196 if (strncmp (nbuf
, newname
, nlen
))
2197 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2203 /* Create a Neon typed/indexed register alias using directives, e.g.:
2208 These typed registers can be used instead of the types specified after the
2209 Neon mnemonic, so long as all operands given have types. Types can also be
2210 specified directly, e.g.:
2211 vadd d0.s32, d1.s32, d2.s32 */
2214 create_neon_reg_alias (char *newname
, char *p
)
2216 enum arm_reg_type basetype
;
2217 struct reg_entry
*basereg
;
2218 struct reg_entry mybasereg
;
2219 struct neon_type ntype
;
2220 struct neon_typed_alias typeinfo
;
2221 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2224 typeinfo
.defined
= 0;
2225 typeinfo
.eltype
.type
= NT_invtype
;
2226 typeinfo
.eltype
.size
= -1;
2227 typeinfo
.index
= -1;
2231 if (strncmp (p
, " .dn ", 5) == 0)
2232 basetype
= REG_TYPE_VFD
;
2233 else if (strncmp (p
, " .qn ", 5) == 0)
2234 basetype
= REG_TYPE_NQ
;
2243 basereg
= arm_reg_parse_multi (&p
);
2245 if (basereg
&& basereg
->type
!= basetype
)
2247 as_bad (_("bad type for register"));
2251 if (basereg
== NULL
)
2254 /* Try parsing as an integer. */
2255 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2256 if (exp
.X_op
!= O_constant
)
2258 as_bad (_("expression must be constant"));
2261 basereg
= &mybasereg
;
2262 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2268 typeinfo
= *basereg
->neon
;
2270 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2272 /* We got a type. */
2273 if (typeinfo
.defined
& NTA_HASTYPE
)
2275 as_bad (_("can't redefine the type of a register alias"));
2279 typeinfo
.defined
|= NTA_HASTYPE
;
2280 if (ntype
.elems
!= 1)
2282 as_bad (_("you must specify a single type only"));
2285 typeinfo
.eltype
= ntype
.el
[0];
2288 if (skip_past_char (&p
, '[') == SUCCESS
)
2291 /* We got a scalar index. */
2293 if (typeinfo
.defined
& NTA_HASINDEX
)
2295 as_bad (_("can't redefine the index of a scalar alias"));
2299 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2301 if (exp
.X_op
!= O_constant
)
2303 as_bad (_("scalar index must be constant"));
2307 typeinfo
.defined
|= NTA_HASINDEX
;
2308 typeinfo
.index
= exp
.X_add_number
;
2310 if (skip_past_char (&p
, ']') == FAIL
)
2312 as_bad (_("expecting ]"));
2317 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2318 the desired alias name, and p points to its end. If not, then
2319 the desired alias name is in the global original_case_string. */
2320 #ifdef TC_CASE_SENSITIVE
2321 namelen
= nameend
- newname
;
2323 newname
= original_case_string
;
2324 namelen
= strlen (newname
);
2327 namebuf
= (char *) alloca (namelen
+ 1);
2328 strncpy (namebuf
, newname
, namelen
);
2329 namebuf
[namelen
] = '\0';
2331 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2332 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2334 /* Insert name in all uppercase. */
2335 for (p
= namebuf
; *p
; p
++)
2338 if (strncmp (namebuf
, newname
, namelen
))
2339 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2340 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2342 /* Insert name in all lowercase. */
2343 for (p
= namebuf
; *p
; p
++)
2346 if (strncmp (namebuf
, newname
, namelen
))
2347 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2348 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2353 /* Should never be called, as .req goes between the alias and the
2354 register name, not at the beginning of the line. */
2357 s_req (int a ATTRIBUTE_UNUSED
)
2359 as_bad (_("invalid syntax for .req directive"));
2363 s_dn (int a ATTRIBUTE_UNUSED
)
2365 as_bad (_("invalid syntax for .dn directive"));
2369 s_qn (int a ATTRIBUTE_UNUSED
)
2371 as_bad (_("invalid syntax for .qn directive"));
2374 /* The .unreq directive deletes an alias which was previously defined
2375 by .req. For example:
2381 s_unreq (int a ATTRIBUTE_UNUSED
)
2386 name
= input_line_pointer
;
2388 while (*input_line_pointer
!= 0
2389 && *input_line_pointer
!= ' '
2390 && *input_line_pointer
!= '\n')
2391 ++input_line_pointer
;
2393 saved_char
= *input_line_pointer
;
2394 *input_line_pointer
= 0;
2397 as_bad (_("invalid syntax for .unreq directive"));
2400 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2404 as_bad (_("unknown register alias '%s'"), name
);
2405 else if (reg
->builtin
)
2406 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2413 hash_delete (arm_reg_hsh
, name
, FALSE
);
2414 free ((char *) reg
->name
);
2419 /* Also locate the all upper case and all lower case versions.
2420 Do not complain if we cannot find one or the other as it
2421 was probably deleted above. */
2423 nbuf
= strdup (name
);
2424 for (p
= nbuf
; *p
; p
++)
2426 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2429 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2430 free ((char *) reg
->name
);
2436 for (p
= nbuf
; *p
; p
++)
2438 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2441 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2442 free ((char *) reg
->name
);
2452 *input_line_pointer
= saved_char
;
2453 demand_empty_rest_of_line ();
2456 /* Directives: Instruction set selection. */
2459 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2460 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2461 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2462 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2464 /* Create a new mapping symbol for the transition to STATE. */
2467 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2470 const char * symname
;
2477 type
= BSF_NO_FLAGS
;
2481 type
= BSF_NO_FLAGS
;
2485 type
= BSF_NO_FLAGS
;
2491 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2492 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2497 THUMB_SET_FUNC (symbolP
, 0);
2498 ARM_SET_THUMB (symbolP
, 0);
2499 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2503 THUMB_SET_FUNC (symbolP
, 1);
2504 ARM_SET_THUMB (symbolP
, 1);
2505 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2513 /* Save the mapping symbols for future reference. Also check that
2514 we do not place two mapping symbols at the same offset within a
2515 frag. We'll handle overlap between frags in
2516 check_mapping_symbols.
2518 If .fill or other data filling directive generates zero sized data,
2519 the mapping symbol for the following code will have the same value
2520 as the one generated for the data filling directive. In this case,
2521 we replace the old symbol with the new one at the same address. */
2524 if (frag
->tc_frag_data
.first_map
!= NULL
)
2526 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2527 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2529 frag
->tc_frag_data
.first_map
= symbolP
;
2531 if (frag
->tc_frag_data
.last_map
!= NULL
)
2533 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2534 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2535 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2537 frag
->tc_frag_data
.last_map
= symbolP
;
2540 /* We must sometimes convert a region marked as code to data during
2541 code alignment, if an odd number of bytes have to be padded. The
2542 code mapping symbol is pushed to an aligned address. */
2545 insert_data_mapping_symbol (enum mstate state
,
2546 valueT value
, fragS
*frag
, offsetT bytes
)
2548 /* If there was already a mapping symbol, remove it. */
2549 if (frag
->tc_frag_data
.last_map
!= NULL
2550 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2552 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2556 know (frag
->tc_frag_data
.first_map
== symp
);
2557 frag
->tc_frag_data
.first_map
= NULL
;
2559 frag
->tc_frag_data
.last_map
= NULL
;
2560 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2563 make_mapping_symbol (MAP_DATA
, value
, frag
);
2564 make_mapping_symbol (state
, value
+ bytes
, frag
);
2567 static void mapping_state_2 (enum mstate state
, int max_chars
);
2569 /* Set the mapping state to STATE. Only call this when about to
2570 emit some STATE bytes to the file. */
2573 mapping_state (enum mstate state
)
2575 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2577 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2579 if (mapstate
== state
)
2580 /* The mapping symbol has already been emitted.
2581 There is nothing else to do. */
2583 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2584 /* This case will be evaluated later in the next else. */
2586 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2587 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2589 /* Only add the symbol if the offset is > 0:
2590 if we're at the first frag, check it's size > 0;
2591 if we're not at the first frag, then for sure
2592 the offset is > 0. */
2593 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2594 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2597 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2600 mapping_state_2 (state
, 0);
2604 /* Same as mapping_state, but MAX_CHARS bytes have already been
2605 allocated. Put the mapping symbol that far back. */
2608 mapping_state_2 (enum mstate state
, int max_chars
)
2610 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2612 if (!SEG_NORMAL (now_seg
))
2615 if (mapstate
== state
)
2616 /* The mapping symbol has already been emitted.
2617 There is nothing else to do. */
2620 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2621 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2624 #define mapping_state(x) ((void)0)
2625 #define mapping_state_2(x, y) ((void)0)
2628 /* Find the real, Thumb encoded start of a Thumb function. */
2632 find_real_start (symbolS
* symbolP
)
2635 const char * name
= S_GET_NAME (symbolP
);
2636 symbolS
* new_target
;
2638 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2639 #define STUB_NAME ".real_start_of"
2644 /* The compiler may generate BL instructions to local labels because
2645 it needs to perform a branch to a far away location. These labels
2646 do not have a corresponding ".real_start_of" label. We check
2647 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2648 the ".real_start_of" convention for nonlocal branches. */
2649 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2652 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2653 new_target
= symbol_find (real_start
);
2655 if (new_target
== NULL
)
2657 as_warn (_("Failed to find real start of function: %s\n"), name
);
2658 new_target
= symbolP
;
2666 opcode_select (int width
)
2673 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2674 as_bad (_("selected processor does not support THUMB opcodes"));
2677 /* No need to force the alignment, since we will have been
2678 coming from ARM mode, which is word-aligned. */
2679 record_alignment (now_seg
, 1);
2686 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2687 as_bad (_("selected processor does not support ARM opcodes"));
2692 frag_align (2, 0, 0);
2694 record_alignment (now_seg
, 1);
2699 as_bad (_("invalid instruction size selected (%d)"), width
);
2704 s_arm (int ignore ATTRIBUTE_UNUSED
)
2707 demand_empty_rest_of_line ();
2711 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2714 demand_empty_rest_of_line ();
2718 s_code (int unused ATTRIBUTE_UNUSED
)
2722 temp
= get_absolute_expression ();
2727 opcode_select (temp
);
2731 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2736 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2738 /* If we are not already in thumb mode go into it, EVEN if
2739 the target processor does not support thumb instructions.
2740 This is used by gcc/config/arm/lib1funcs.asm for example
2741 to compile interworking support functions even if the
2742 target processor should not support interworking. */
2746 record_alignment (now_seg
, 1);
2749 demand_empty_rest_of_line ();
2753 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2757 /* The following label is the name/address of the start of a Thumb function.
2758 We need to know this for the interworking support. */
2759 label_is_thumb_function_name
= TRUE
;
2762 /* Perform a .set directive, but also mark the alias as
2763 being a thumb function. */
2766 s_thumb_set (int equiv
)
2768 /* XXX the following is a duplicate of the code for s_set() in read.c
2769 We cannot just call that code as we need to get at the symbol that
2776 /* Especial apologies for the random logic:
2777 This just grew, and could be parsed much more simply!
2779 name
= input_line_pointer
;
2780 delim
= get_symbol_end ();
2781 end_name
= input_line_pointer
;
2784 if (*input_line_pointer
!= ',')
2787 as_bad (_("expected comma after name \"%s\""), name
);
2789 ignore_rest_of_line ();
2793 input_line_pointer
++;
2796 if (name
[0] == '.' && name
[1] == '\0')
2798 /* XXX - this should not happen to .thumb_set. */
2802 if ((symbolP
= symbol_find (name
)) == NULL
2803 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2806 /* When doing symbol listings, play games with dummy fragments living
2807 outside the normal fragment chain to record the file and line info
2809 if (listing
& LISTING_SYMBOLS
)
2811 extern struct list_info_struct
* listing_tail
;
2812 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2814 memset (dummy_frag
, 0, sizeof (fragS
));
2815 dummy_frag
->fr_type
= rs_fill
;
2816 dummy_frag
->line
= listing_tail
;
2817 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2818 dummy_frag
->fr_symbol
= symbolP
;
2822 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2825 /* "set" symbols are local unless otherwise specified. */
2826 SF_SET_LOCAL (symbolP
);
2827 #endif /* OBJ_COFF */
2828 } /* Make a new symbol. */
2830 symbol_table_insert (symbolP
);
2835 && S_IS_DEFINED (symbolP
)
2836 && S_GET_SEGMENT (symbolP
) != reg_section
)
2837 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2839 pseudo_set (symbolP
);
2841 demand_empty_rest_of_line ();
2843 /* XXX Now we come to the Thumb specific bit of code. */
2845 THUMB_SET_FUNC (symbolP
, 1);
2846 ARM_SET_THUMB (symbolP
, 1);
2847 #if defined OBJ_ELF || defined OBJ_COFF
2848 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2852 /* Directives: Mode selection. */
2854 /* .syntax [unified|divided] - choose the new unified syntax
2855 (same for Arm and Thumb encoding, modulo slight differences in what
2856 can be represented) or the old divergent syntax for each mode. */
2858 s_syntax (int unused ATTRIBUTE_UNUSED
)
2862 name
= input_line_pointer
;
2863 delim
= get_symbol_end ();
2865 if (!strcasecmp (name
, "unified"))
2866 unified_syntax
= TRUE
;
2867 else if (!strcasecmp (name
, "divided"))
2868 unified_syntax
= FALSE
;
2871 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2874 *input_line_pointer
= delim
;
2875 demand_empty_rest_of_line ();
2878 /* Directives: sectioning and alignment. */
2880 /* Same as s_align_ptwo but align 0 => align 2. */
2883 s_align (int unused ATTRIBUTE_UNUSED
)
2888 long max_alignment
= 15;
2890 temp
= get_absolute_expression ();
2891 if (temp
> max_alignment
)
2892 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2895 as_bad (_("alignment negative. 0 assumed."));
2899 if (*input_line_pointer
== ',')
2901 input_line_pointer
++;
2902 temp_fill
= get_absolute_expression ();
2914 /* Only make a frag if we HAVE to. */
2915 if (temp
&& !need_pass_2
)
2917 if (!fill_p
&& subseg_text_p (now_seg
))
2918 frag_align_code (temp
, 0);
2920 frag_align (temp
, (int) temp_fill
, 0);
2922 demand_empty_rest_of_line ();
2924 record_alignment (now_seg
, temp
);
2928 s_bss (int ignore ATTRIBUTE_UNUSED
)
2930 /* We don't support putting frags in the BSS segment, we fake it by
2931 marking in_bss, then looking at s_skip for clues. */
2932 subseg_set (bss_section
, 0);
2933 demand_empty_rest_of_line ();
2935 #ifdef md_elf_section_change_hook
2936 md_elf_section_change_hook ();
2941 s_even (int ignore ATTRIBUTE_UNUSED
)
2943 /* Never make frag if expect extra pass. */
2945 frag_align (1, 0, 0);
2947 record_alignment (now_seg
, 1);
2949 demand_empty_rest_of_line ();
2952 /* Directives: Literal pools. */
2954 static literal_pool
*
2955 find_literal_pool (void)
2957 literal_pool
* pool
;
2959 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2961 if (pool
->section
== now_seg
2962 && pool
->sub_section
== now_subseg
)
2969 static literal_pool
*
2970 find_or_make_literal_pool (void)
2972 /* Next literal pool ID number. */
2973 static unsigned int latest_pool_num
= 1;
2974 literal_pool
* pool
;
2976 pool
= find_literal_pool ();
2980 /* Create a new pool. */
2981 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2985 pool
->next_free_entry
= 0;
2986 pool
->section
= now_seg
;
2987 pool
->sub_section
= now_subseg
;
2988 pool
->next
= list_of_pools
;
2989 pool
->symbol
= NULL
;
2991 /* Add it to the list. */
2992 list_of_pools
= pool
;
2995 /* New pools, and emptied pools, will have a NULL symbol. */
2996 if (pool
->symbol
== NULL
)
2998 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2999 (valueT
) 0, &zero_address_frag
);
3000 pool
->id
= latest_pool_num
++;
3007 /* Add the literal in the global 'inst'
3008 structure to the relevant literal pool. */
3011 add_to_lit_pool (void)
3013 literal_pool
* pool
;
3016 pool
= find_or_make_literal_pool ();
3018 /* Check if this literal value is already in the pool. */
3019 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3021 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3022 && (inst
.reloc
.exp
.X_op
== O_constant
)
3023 && (pool
->literals
[entry
].X_add_number
3024 == inst
.reloc
.exp
.X_add_number
)
3025 && (pool
->literals
[entry
].X_unsigned
3026 == inst
.reloc
.exp
.X_unsigned
))
3029 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3030 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3031 && (pool
->literals
[entry
].X_add_number
3032 == inst
.reloc
.exp
.X_add_number
)
3033 && (pool
->literals
[entry
].X_add_symbol
3034 == inst
.reloc
.exp
.X_add_symbol
)
3035 && (pool
->literals
[entry
].X_op_symbol
3036 == inst
.reloc
.exp
.X_op_symbol
))
3040 /* Do we need to create a new entry? */
3041 if (entry
== pool
->next_free_entry
)
3043 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3045 inst
.error
= _("literal pool overflow");
3049 pool
->literals
[entry
] = inst
.reloc
.exp
;
3050 pool
->next_free_entry
+= 1;
3053 inst
.reloc
.exp
.X_op
= O_symbol
;
3054 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3055 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3060 /* Can't use symbol_new here, so have to create a symbol and then at
3061 a later date assign it a value. Thats what these functions do. */
3064 symbol_locate (symbolS
* symbolP
,
3065 const char * name
, /* It is copied, the caller can modify. */
3066 segT segment
, /* Segment identifier (SEG_<something>). */
3067 valueT valu
, /* Symbol value. */
3068 fragS
* frag
) /* Associated fragment. */
3070 unsigned int name_length
;
3071 char * preserved_copy_of_name
;
3073 name_length
= strlen (name
) + 1; /* +1 for \0. */
3074 obstack_grow (¬es
, name
, name_length
);
3075 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3077 #ifdef tc_canonicalize_symbol_name
3078 preserved_copy_of_name
=
3079 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3082 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3084 S_SET_SEGMENT (symbolP
, segment
);
3085 S_SET_VALUE (symbolP
, valu
);
3086 symbol_clear_list_pointers (symbolP
);
3088 symbol_set_frag (symbolP
, frag
);
3090 /* Link to end of symbol chain. */
3092 extern int symbol_table_frozen
;
3094 if (symbol_table_frozen
)
3098 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3100 obj_symbol_new_hook (symbolP
);
3102 #ifdef tc_symbol_new_hook
3103 tc_symbol_new_hook (symbolP
);
3107 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3108 #endif /* DEBUG_SYMS */
3113 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3116 literal_pool
* pool
;
3119 pool
= find_literal_pool ();
3121 || pool
->symbol
== NULL
3122 || pool
->next_free_entry
== 0)
3125 mapping_state (MAP_DATA
);
3127 /* Align pool as you have word accesses.
3128 Only make a frag if we have to. */
3130 frag_align (2, 0, 0);
3132 record_alignment (now_seg
, 2);
3134 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3136 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3137 (valueT
) frag_now_fix (), frag_now
);
3138 symbol_table_insert (pool
->symbol
);
3140 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3142 #if defined OBJ_COFF || defined OBJ_ELF
3143 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3146 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3147 /* First output the expression in the instruction to the pool. */
3148 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3150 /* Mark the pool as empty. */
3151 pool
->next_free_entry
= 0;
3152 pool
->symbol
= NULL
;
3156 /* Forward declarations for functions below, in the MD interface
3158 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3159 static valueT
create_unwind_entry (int);
3160 static void start_unwind_section (const segT
, int);
3161 static void add_unwind_opcode (valueT
, int);
3162 static void flush_pending_unwind (void);
3164 /* Directives: Data. */
3167 s_arm_elf_cons (int nbytes
)
3171 #ifdef md_flush_pending_output
3172 md_flush_pending_output ();
3175 if (is_it_end_of_statement ())
3177 demand_empty_rest_of_line ();
3181 #ifdef md_cons_align
3182 md_cons_align (nbytes
);
3185 mapping_state (MAP_DATA
);
3189 char *base
= input_line_pointer
;
3193 if (exp
.X_op
!= O_symbol
)
3194 emit_expr (&exp
, (unsigned int) nbytes
);
3197 char *before_reloc
= input_line_pointer
;
3198 reloc
= parse_reloc (&input_line_pointer
);
3201 as_bad (_("unrecognized relocation suffix"));
3202 ignore_rest_of_line ();
3205 else if (reloc
== BFD_RELOC_UNUSED
)
3206 emit_expr (&exp
, (unsigned int) nbytes
);
3209 reloc_howto_type
*howto
= (reloc_howto_type
*)
3210 bfd_reloc_type_lookup (stdoutput
,
3211 (bfd_reloc_code_real_type
) reloc
);
3212 int size
= bfd_get_reloc_size (howto
);
3214 if (reloc
== BFD_RELOC_ARM_PLT32
)
3216 as_bad (_("(plt) is only valid on branch targets"));
3217 reloc
= BFD_RELOC_UNUSED
;
3222 as_bad (_("%s relocations do not fit in %d bytes"),
3223 howto
->name
, nbytes
);
3226 /* We've parsed an expression stopping at O_symbol.
3227 But there may be more expression left now that we
3228 have parsed the relocation marker. Parse it again.
3229 XXX Surely there is a cleaner way to do this. */
3230 char *p
= input_line_pointer
;
3232 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3233 memcpy (save_buf
, base
, input_line_pointer
- base
);
3234 memmove (base
+ (input_line_pointer
- before_reloc
),
3235 base
, before_reloc
- base
);
3237 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3239 memcpy (base
, save_buf
, p
- base
);
3241 offset
= nbytes
- size
;
3242 p
= frag_more ((int) nbytes
);
3243 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3244 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3249 while (*input_line_pointer
++ == ',');
3251 /* Put terminator back into stream. */
3252 input_line_pointer
--;
3253 demand_empty_rest_of_line ();
3256 /* Emit an expression containing a 32-bit thumb instruction.
3257 Implementation based on put_thumb32_insn. */
3260 emit_thumb32_expr (expressionS
* exp
)
3262 expressionS exp_high
= *exp
;
3264 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3265 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3266 exp
->X_add_number
&= 0xffff;
3267 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3270 /* Guess the instruction size based on the opcode. */
3273 thumb_insn_size (int opcode
)
3275 if ((unsigned int) opcode
< 0xe800u
)
3277 else if ((unsigned int) opcode
>= 0xe8000000u
)
3284 emit_insn (expressionS
*exp
, int nbytes
)
3288 if (exp
->X_op
== O_constant
)
3293 size
= thumb_insn_size (exp
->X_add_number
);
3297 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3299 as_bad (_(".inst.n operand too big. "\
3300 "Use .inst.w instead"));
3305 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3306 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3308 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3310 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3311 emit_thumb32_expr (exp
);
3313 emit_expr (exp
, (unsigned int) size
);
3315 it_fsm_post_encode ();
3319 as_bad (_("cannot determine Thumb instruction size. " \
3320 "Use .inst.n/.inst.w instead"));
3323 as_bad (_("constant expression required"));
3328 /* Like s_arm_elf_cons but do not use md_cons_align and
3329 set the mapping state to MAP_ARM/MAP_THUMB. */
3332 s_arm_elf_inst (int nbytes
)
3334 if (is_it_end_of_statement ())
3336 demand_empty_rest_of_line ();
3340 /* Calling mapping_state () here will not change ARM/THUMB,
3341 but will ensure not to be in DATA state. */
3344 mapping_state (MAP_THUMB
);
3349 as_bad (_("width suffixes are invalid in ARM mode"));
3350 ignore_rest_of_line ();
3356 mapping_state (MAP_ARM
);
3365 if (! emit_insn (& exp
, nbytes
))
3367 ignore_rest_of_line ();
3371 while (*input_line_pointer
++ == ',');
3373 /* Put terminator back into stream. */
3374 input_line_pointer
--;
3375 demand_empty_rest_of_line ();
3378 /* Parse a .rel31 directive. */
3381 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3388 if (*input_line_pointer
== '1')
3389 highbit
= 0x80000000;
3390 else if (*input_line_pointer
!= '0')
3391 as_bad (_("expected 0 or 1"));
3393 input_line_pointer
++;
3394 if (*input_line_pointer
!= ',')
3395 as_bad (_("missing comma"));
3396 input_line_pointer
++;
3398 #ifdef md_flush_pending_output
3399 md_flush_pending_output ();
3402 #ifdef md_cons_align
3406 mapping_state (MAP_DATA
);
3411 md_number_to_chars (p
, highbit
, 4);
3412 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3413 BFD_RELOC_ARM_PREL31
);
3415 demand_empty_rest_of_line ();
3418 /* Directives: AEABI stack-unwind tables. */
3420 /* Parse an unwind_fnstart directive. Simply records the current location. */
3423 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3425 demand_empty_rest_of_line ();
3426 if (unwind
.proc_start
)
3428 as_bad (_("duplicate .fnstart directive"));
3432 /* Mark the start of the function. */
3433 unwind
.proc_start
= expr_build_dot ();
3435 /* Reset the rest of the unwind info. */
3436 unwind
.opcode_count
= 0;
3437 unwind
.table_entry
= NULL
;
3438 unwind
.personality_routine
= NULL
;
3439 unwind
.personality_index
= -1;
3440 unwind
.frame_size
= 0;
3441 unwind
.fp_offset
= 0;
3442 unwind
.fp_reg
= REG_SP
;
3444 unwind
.sp_restored
= 0;
3448 /* Parse a handlerdata directive. Creates the exception handling table entry
3449 for the function. */
3452 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3454 demand_empty_rest_of_line ();
3455 if (!unwind
.proc_start
)
3456 as_bad (MISSING_FNSTART
);
3458 if (unwind
.table_entry
)
3459 as_bad (_("duplicate .handlerdata directive"));
3461 create_unwind_entry (1);
3464 /* Parse an unwind_fnend directive. Generates the index table entry. */
3467 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3472 unsigned int marked_pr_dependency
;
3474 demand_empty_rest_of_line ();
3476 if (!unwind
.proc_start
)
3478 as_bad (_(".fnend directive without .fnstart"));
3482 /* Add eh table entry. */
3483 if (unwind
.table_entry
== NULL
)
3484 val
= create_unwind_entry (0);
3488 /* Add index table entry. This is two words. */
3489 start_unwind_section (unwind
.saved_seg
, 1);
3490 frag_align (2, 0, 0);
3491 record_alignment (now_seg
, 2);
3493 ptr
= frag_more (8);
3494 where
= frag_now_fix () - 8;
3496 /* Self relative offset of the function start. */
3497 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3498 BFD_RELOC_ARM_PREL31
);
3500 /* Indicate dependency on EHABI-defined personality routines to the
3501 linker, if it hasn't been done already. */
3502 marked_pr_dependency
3503 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3504 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3505 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3507 static const char *const name
[] =
3509 "__aeabi_unwind_cpp_pr0",
3510 "__aeabi_unwind_cpp_pr1",
3511 "__aeabi_unwind_cpp_pr2"
3513 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3514 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3515 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3516 |= 1 << unwind
.personality_index
;
3520 /* Inline exception table entry. */
3521 md_number_to_chars (ptr
+ 4, val
, 4);
3523 /* Self relative offset of the table entry. */
3524 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3525 BFD_RELOC_ARM_PREL31
);
3527 /* Restore the original section. */
3528 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3530 unwind
.proc_start
= NULL
;
3534 /* Parse an unwind_cantunwind directive. */
3537 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3539 demand_empty_rest_of_line ();
3540 if (!unwind
.proc_start
)
3541 as_bad (MISSING_FNSTART
);
3543 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3544 as_bad (_("personality routine specified for cantunwind frame"));
3546 unwind
.personality_index
= -2;
3550 /* Parse a personalityindex directive. */
3553 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3557 if (!unwind
.proc_start
)
3558 as_bad (MISSING_FNSTART
);
3560 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3561 as_bad (_("duplicate .personalityindex directive"));
3565 if (exp
.X_op
!= O_constant
3566 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3568 as_bad (_("bad personality routine number"));
3569 ignore_rest_of_line ();
3573 unwind
.personality_index
= exp
.X_add_number
;
3575 demand_empty_rest_of_line ();
3579 /* Parse a personality directive. */
3582 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3586 if (!unwind
.proc_start
)
3587 as_bad (MISSING_FNSTART
);
3589 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3590 as_bad (_("duplicate .personality directive"));
3592 name
= input_line_pointer
;
3593 c
= get_symbol_end ();
3594 p
= input_line_pointer
;
3595 unwind
.personality_routine
= symbol_find_or_make (name
);
3597 demand_empty_rest_of_line ();
3601 /* Parse a directive saving core registers. */
3604 s_arm_unwind_save_core (void)
3610 range
= parse_reg_list (&input_line_pointer
);
3613 as_bad (_("expected register list"));
3614 ignore_rest_of_line ();
3618 demand_empty_rest_of_line ();
3620 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3621 into .unwind_save {..., sp...}. We aren't bothered about the value of
3622 ip because it is clobbered by calls. */
3623 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3624 && (range
& 0x3000) == 0x1000)
3626 unwind
.opcode_count
--;
3627 unwind
.sp_restored
= 0;
3628 range
= (range
| 0x2000) & ~0x1000;
3629 unwind
.pending_offset
= 0;
3635 /* See if we can use the short opcodes. These pop a block of up to 8
3636 registers starting with r4, plus maybe r14. */
3637 for (n
= 0; n
< 8; n
++)
3639 /* Break at the first non-saved register. */
3640 if ((range
& (1 << (n
+ 4))) == 0)
3643 /* See if there are any other bits set. */
3644 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3646 /* Use the long form. */
3647 op
= 0x8000 | ((range
>> 4) & 0xfff);
3648 add_unwind_opcode (op
, 2);
3652 /* Use the short form. */
3654 op
= 0xa8; /* Pop r14. */
3656 op
= 0xa0; /* Do not pop r14. */
3658 add_unwind_opcode (op
, 1);
3665 op
= 0xb100 | (range
& 0xf);
3666 add_unwind_opcode (op
, 2);
3669 /* Record the number of bytes pushed. */
3670 for (n
= 0; n
< 16; n
++)
3672 if (range
& (1 << n
))
3673 unwind
.frame_size
+= 4;
3678 /* Parse a directive saving FPA registers. */
3681 s_arm_unwind_save_fpa (int reg
)
3687 /* Get Number of registers to transfer. */
3688 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3691 exp
.X_op
= O_illegal
;
3693 if (exp
.X_op
!= O_constant
)
3695 as_bad (_("expected , <constant>"));
3696 ignore_rest_of_line ();
3700 num_regs
= exp
.X_add_number
;
3702 if (num_regs
< 1 || num_regs
> 4)
3704 as_bad (_("number of registers must be in the range [1:4]"));
3705 ignore_rest_of_line ();
3709 demand_empty_rest_of_line ();
3714 op
= 0xb4 | (num_regs
- 1);
3715 add_unwind_opcode (op
, 1);
3720 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3721 add_unwind_opcode (op
, 2);
3723 unwind
.frame_size
+= num_regs
* 12;
3727 /* Parse a directive saving VFP registers for ARMv6 and above. */
3730 s_arm_unwind_save_vfp_armv6 (void)
3735 int num_vfpv3_regs
= 0;
3736 int num_regs_below_16
;
3738 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3741 as_bad (_("expected register list"));
3742 ignore_rest_of_line ();
3746 demand_empty_rest_of_line ();
3748 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3749 than FSTMX/FLDMX-style ones). */
3751 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3753 num_vfpv3_regs
= count
;
3754 else if (start
+ count
> 16)
3755 num_vfpv3_regs
= start
+ count
- 16;
3757 if (num_vfpv3_regs
> 0)
3759 int start_offset
= start
> 16 ? start
- 16 : 0;
3760 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3761 add_unwind_opcode (op
, 2);
3764 /* Generate opcode for registers numbered in the range 0 .. 15. */
3765 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3766 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3767 if (num_regs_below_16
> 0)
3769 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3770 add_unwind_opcode (op
, 2);
3773 unwind
.frame_size
+= count
* 8;
3777 /* Parse a directive saving VFP registers for pre-ARMv6. */
3780 s_arm_unwind_save_vfp (void)
3786 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3789 as_bad (_("expected register list"));
3790 ignore_rest_of_line ();
3794 demand_empty_rest_of_line ();
3799 op
= 0xb8 | (count
- 1);
3800 add_unwind_opcode (op
, 1);
3805 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3806 add_unwind_opcode (op
, 2);
3808 unwind
.frame_size
+= count
* 8 + 4;
3812 /* Parse a directive saving iWMMXt data registers. */
3815 s_arm_unwind_save_mmxwr (void)
3823 if (*input_line_pointer
== '{')
3824 input_line_pointer
++;
3828 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3832 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3837 as_tsktsk (_("register list not in ascending order"));
3840 if (*input_line_pointer
== '-')
3842 input_line_pointer
++;
3843 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3846 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3849 else if (reg
>= hi_reg
)
3851 as_bad (_("bad register range"));
3854 for (; reg
< hi_reg
; reg
++)
3858 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3860 if (*input_line_pointer
== '}')
3861 input_line_pointer
++;
3863 demand_empty_rest_of_line ();
3865 /* Generate any deferred opcodes because we're going to be looking at
3867 flush_pending_unwind ();
3869 for (i
= 0; i
< 16; i
++)
3871 if (mask
& (1 << i
))
3872 unwind
.frame_size
+= 8;
3875 /* Attempt to combine with a previous opcode. We do this because gcc
3876 likes to output separate unwind directives for a single block of
3878 if (unwind
.opcode_count
> 0)
3880 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3881 if ((i
& 0xf8) == 0xc0)
3884 /* Only merge if the blocks are contiguous. */
3887 if ((mask
& 0xfe00) == (1 << 9))
3889 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3890 unwind
.opcode_count
--;
3893 else if (i
== 6 && unwind
.opcode_count
>= 2)
3895 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3899 op
= 0xffff << (reg
- 1);
3901 && ((mask
& op
) == (1u << (reg
- 1))))
3903 op
= (1 << (reg
+ i
+ 1)) - 1;
3904 op
&= ~((1 << reg
) - 1);
3906 unwind
.opcode_count
-= 2;
3913 /* We want to generate opcodes in the order the registers have been
3914 saved, ie. descending order. */
3915 for (reg
= 15; reg
>= -1; reg
--)
3917 /* Save registers in blocks. */
3919 || !(mask
& (1 << reg
)))
3921 /* We found an unsaved reg. Generate opcodes to save the
3928 op
= 0xc0 | (hi_reg
- 10);
3929 add_unwind_opcode (op
, 1);
3934 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3935 add_unwind_opcode (op
, 2);
3944 ignore_rest_of_line ();
3948 s_arm_unwind_save_mmxwcg (void)
3955 if (*input_line_pointer
== '{')
3956 input_line_pointer
++;
3960 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3964 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3970 as_tsktsk (_("register list not in ascending order"));
3973 if (*input_line_pointer
== '-')
3975 input_line_pointer
++;
3976 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3979 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3982 else if (reg
>= hi_reg
)
3984 as_bad (_("bad register range"));
3987 for (; reg
< hi_reg
; reg
++)
3991 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3993 if (*input_line_pointer
== '}')
3994 input_line_pointer
++;
3996 demand_empty_rest_of_line ();
3998 /* Generate any deferred opcodes because we're going to be looking at
4000 flush_pending_unwind ();
4002 for (reg
= 0; reg
< 16; reg
++)
4004 if (mask
& (1 << reg
))
4005 unwind
.frame_size
+= 4;
4008 add_unwind_opcode (op
, 2);
4011 ignore_rest_of_line ();
4015 /* Parse an unwind_save directive.
4016 If the argument is non-zero, this is a .vsave directive. */
4019 s_arm_unwind_save (int arch_v6
)
4022 struct reg_entry
*reg
;
4023 bfd_boolean had_brace
= FALSE
;
4025 if (!unwind
.proc_start
)
4026 as_bad (MISSING_FNSTART
);
4028 /* Figure out what sort of save we have. */
4029 peek
= input_line_pointer
;
4037 reg
= arm_reg_parse_multi (&peek
);
4041 as_bad (_("register expected"));
4042 ignore_rest_of_line ();
4051 as_bad (_("FPA .unwind_save does not take a register list"));
4052 ignore_rest_of_line ();
4055 input_line_pointer
= peek
;
4056 s_arm_unwind_save_fpa (reg
->number
);
4059 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4062 s_arm_unwind_save_vfp_armv6 ();
4064 s_arm_unwind_save_vfp ();
4066 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4067 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4070 as_bad (_(".unwind_save does not support this kind of register"));
4071 ignore_rest_of_line ();
4076 /* Parse an unwind_movsp directive. */
4079 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4085 if (!unwind
.proc_start
)
4086 as_bad (MISSING_FNSTART
);
4088 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4091 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4092 ignore_rest_of_line ();
4096 /* Optional constant. */
4097 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4099 if (immediate_for_directive (&offset
) == FAIL
)
4105 demand_empty_rest_of_line ();
4107 if (reg
== REG_SP
|| reg
== REG_PC
)
4109 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4113 if (unwind
.fp_reg
!= REG_SP
)
4114 as_bad (_("unexpected .unwind_movsp directive"));
4116 /* Generate opcode to restore the value. */
4118 add_unwind_opcode (op
, 1);
4120 /* Record the information for later. */
4121 unwind
.fp_reg
= reg
;
4122 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4123 unwind
.sp_restored
= 1;
4126 /* Parse an unwind_pad directive. */
4129 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4133 if (!unwind
.proc_start
)
4134 as_bad (MISSING_FNSTART
);
4136 if (immediate_for_directive (&offset
) == FAIL
)
4141 as_bad (_("stack increment must be multiple of 4"));
4142 ignore_rest_of_line ();
4146 /* Don't generate any opcodes, just record the details for later. */
4147 unwind
.frame_size
+= offset
;
4148 unwind
.pending_offset
+= offset
;
4150 demand_empty_rest_of_line ();
4153 /* Parse an unwind_setfp directive. */
4156 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4162 if (!unwind
.proc_start
)
4163 as_bad (MISSING_FNSTART
);
4165 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4166 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4169 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4171 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4173 as_bad (_("expected <reg>, <reg>"));
4174 ignore_rest_of_line ();
4178 /* Optional constant. */
4179 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4181 if (immediate_for_directive (&offset
) == FAIL
)
4187 demand_empty_rest_of_line ();
4189 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4191 as_bad (_("register must be either sp or set by a previous"
4192 "unwind_movsp directive"));
4196 /* Don't generate any opcodes, just record the information for later. */
4197 unwind
.fp_reg
= fp_reg
;
4199 if (sp_reg
== REG_SP
)
4200 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4202 unwind
.fp_offset
-= offset
;
4205 /* Parse an unwind_raw directive. */
4208 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4211 /* This is an arbitrary limit. */
4212 unsigned char op
[16];
4215 if (!unwind
.proc_start
)
4216 as_bad (MISSING_FNSTART
);
4219 if (exp
.X_op
== O_constant
4220 && skip_past_comma (&input_line_pointer
) != FAIL
)
4222 unwind
.frame_size
+= exp
.X_add_number
;
4226 exp
.X_op
= O_illegal
;
4228 if (exp
.X_op
!= O_constant
)
4230 as_bad (_("expected <offset>, <opcode>"));
4231 ignore_rest_of_line ();
4237 /* Parse the opcode. */
4242 as_bad (_("unwind opcode too long"));
4243 ignore_rest_of_line ();
4245 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4247 as_bad (_("invalid unwind opcode"));
4248 ignore_rest_of_line ();
4251 op
[count
++] = exp
.X_add_number
;
4253 /* Parse the next byte. */
4254 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4260 /* Add the opcode bytes in reverse order. */
4262 add_unwind_opcode (op
[count
], 1);
4264 demand_empty_rest_of_line ();
4268 /* Parse a .eabi_attribute directive. */
4271 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4273 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4275 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4276 attributes_set_explicitly
[tag
] = 1;
4279 /* Emit a tls fix for the symbol. */
4282 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4286 #ifdef md_flush_pending_output
4287 md_flush_pending_output ();
4290 #ifdef md_cons_align
4294 /* Since we're just labelling the code, there's no need to define a
4297 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4298 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4299 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4300 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4302 #endif /* OBJ_ELF */
4304 static void s_arm_arch (int);
4305 static void s_arm_object_arch (int);
4306 static void s_arm_cpu (int);
4307 static void s_arm_fpu (int);
4308 static void s_arm_arch_extension (int);
4313 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4320 if (exp
.X_op
== O_symbol
)
4321 exp
.X_op
= O_secrel
;
4323 emit_expr (&exp
, 4);
4325 while (*input_line_pointer
++ == ',');
4327 input_line_pointer
--;
4328 demand_empty_rest_of_line ();
4332 /* This table describes all the machine specific pseudo-ops the assembler
4333 has to support. The fields are:
4334 pseudo-op name without dot
4335 function to call to execute this pseudo-op
4336 Integer arg to pass to the function. */
4338 const pseudo_typeS md_pseudo_table
[] =
4340 /* Never called because '.req' does not start a line. */
4341 { "req", s_req
, 0 },
4342 /* Following two are likewise never called. */
4345 { "unreq", s_unreq
, 0 },
4346 { "bss", s_bss
, 0 },
4347 { "align", s_align
, 0 },
4348 { "arm", s_arm
, 0 },
4349 { "thumb", s_thumb
, 0 },
4350 { "code", s_code
, 0 },
4351 { "force_thumb", s_force_thumb
, 0 },
4352 { "thumb_func", s_thumb_func
, 0 },
4353 { "thumb_set", s_thumb_set
, 0 },
4354 { "even", s_even
, 0 },
4355 { "ltorg", s_ltorg
, 0 },
4356 { "pool", s_ltorg
, 0 },
4357 { "syntax", s_syntax
, 0 },
4358 { "cpu", s_arm_cpu
, 0 },
4359 { "arch", s_arm_arch
, 0 },
4360 { "object_arch", s_arm_object_arch
, 0 },
4361 { "fpu", s_arm_fpu
, 0 },
4362 { "arch_extension", s_arm_arch_extension
, 0 },
4364 { "word", s_arm_elf_cons
, 4 },
4365 { "long", s_arm_elf_cons
, 4 },
4366 { "inst.n", s_arm_elf_inst
, 2 },
4367 { "inst.w", s_arm_elf_inst
, 4 },
4368 { "inst", s_arm_elf_inst
, 0 },
4369 { "rel31", s_arm_rel31
, 0 },
4370 { "fnstart", s_arm_unwind_fnstart
, 0 },
4371 { "fnend", s_arm_unwind_fnend
, 0 },
4372 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4373 { "personality", s_arm_unwind_personality
, 0 },
4374 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4375 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4376 { "save", s_arm_unwind_save
, 0 },
4377 { "vsave", s_arm_unwind_save
, 1 },
4378 { "movsp", s_arm_unwind_movsp
, 0 },
4379 { "pad", s_arm_unwind_pad
, 0 },
4380 { "setfp", s_arm_unwind_setfp
, 0 },
4381 { "unwind_raw", s_arm_unwind_raw
, 0 },
4382 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4383 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4387 /* These are used for dwarf. */
4391 /* These are used for dwarf2. */
4392 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4393 { "loc", dwarf2_directive_loc
, 0 },
4394 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4396 { "extend", float_cons
, 'x' },
4397 { "ldouble", float_cons
, 'x' },
4398 { "packed", float_cons
, 'p' },
4400 {"secrel32", pe_directive_secrel
, 0},
4405 /* Parser functions used exclusively in instruction operands. */
4407 /* Generic immediate-value read function for use in insn parsing.
4408 STR points to the beginning of the immediate (the leading #);
4409 VAL receives the value; if the value is outside [MIN, MAX]
4410 issue an error. PREFIX_OPT is true if the immediate prefix is
4414 parse_immediate (char **str
, int *val
, int min
, int max
,
4415 bfd_boolean prefix_opt
)
4418 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4419 if (exp
.X_op
!= O_constant
)
4421 inst
.error
= _("constant expression required");
4425 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4427 inst
.error
= _("immediate value out of range");
4431 *val
= exp
.X_add_number
;
4435 /* Less-generic immediate-value read function with the possibility of loading a
4436 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4437 instructions. Puts the result directly in inst.operands[i]. */
4440 parse_big_immediate (char **str
, int i
)
4445 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4447 if (exp
.X_op
== O_constant
)
4449 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4450 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4451 O_constant. We have to be careful not to break compilation for
4452 32-bit X_add_number, though. */
4453 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4455 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4456 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4457 inst
.operands
[i
].regisimm
= 1;
4460 else if (exp
.X_op
== O_big
4461 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4463 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4465 /* Bignums have their least significant bits in
4466 generic_bignum[0]. Make sure we put 32 bits in imm and
4467 32 bits in reg, in a (hopefully) portable way. */
4468 gas_assert (parts
!= 0);
4470 /* Make sure that the number is not too big.
4471 PR 11972: Bignums can now be sign-extended to the
4472 size of a .octa so check that the out of range bits
4473 are all zero or all one. */
4474 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4476 LITTLENUM_TYPE m
= -1;
4478 if (generic_bignum
[parts
* 2] != 0
4479 && generic_bignum
[parts
* 2] != m
)
4482 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4483 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4487 inst
.operands
[i
].imm
= 0;
4488 for (j
= 0; j
< parts
; j
++, idx
++)
4489 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4490 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4491 inst
.operands
[i
].reg
= 0;
4492 for (j
= 0; j
< parts
; j
++, idx
++)
4493 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4494 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4495 inst
.operands
[i
].regisimm
= 1;
4505 /* Returns the pseudo-register number of an FPA immediate constant,
4506 or FAIL if there isn't a valid constant here. */
4509 parse_fpa_immediate (char ** str
)
4511 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4517 /* First try and match exact strings, this is to guarantee
4518 that some formats will work even for cross assembly. */
4520 for (i
= 0; fp_const
[i
]; i
++)
4522 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4526 *str
+= strlen (fp_const
[i
]);
4527 if (is_end_of_line
[(unsigned char) **str
])
4533 /* Just because we didn't get a match doesn't mean that the constant
4534 isn't valid, just that it is in a format that we don't
4535 automatically recognize. Try parsing it with the standard
4536 expression routines. */
4538 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4540 /* Look for a raw floating point number. */
4541 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4542 && is_end_of_line
[(unsigned char) *save_in
])
4544 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4546 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4548 if (words
[j
] != fp_values
[i
][j
])
4552 if (j
== MAX_LITTLENUMS
)
4560 /* Try and parse a more complex expression, this will probably fail
4561 unless the code uses a floating point prefix (eg "0f"). */
4562 save_in
= input_line_pointer
;
4563 input_line_pointer
= *str
;
4564 if (expression (&exp
) == absolute_section
4565 && exp
.X_op
== O_big
4566 && exp
.X_add_number
< 0)
4568 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4570 if (gen_to_words (words
, 5, (long) 15) == 0)
4572 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4574 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4576 if (words
[j
] != fp_values
[i
][j
])
4580 if (j
== MAX_LITTLENUMS
)
4582 *str
= input_line_pointer
;
4583 input_line_pointer
= save_in
;
4590 *str
= input_line_pointer
;
4591 input_line_pointer
= save_in
;
4592 inst
.error
= _("invalid FPA immediate expression");
4596 /* Returns 1 if a number has "quarter-precision" float format
4597 0baBbbbbbc defgh000 00000000 00000000. */
4600 is_quarter_float (unsigned imm
)
4602 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4603 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4606 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4607 0baBbbbbbc defgh000 00000000 00000000.
4608 The zero and minus-zero cases need special handling, since they can't be
4609 encoded in the "quarter-precision" float format, but can nonetheless be
4610 loaded as integer constants. */
4613 parse_qfloat_immediate (char **ccp
, int *immed
)
4617 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4618 int found_fpchar
= 0;
4620 skip_past_char (&str
, '#');
4622 /* We must not accidentally parse an integer as a floating-point number. Make
4623 sure that the value we parse is not an integer by checking for special
4624 characters '.' or 'e'.
4625 FIXME: This is a horrible hack, but doing better is tricky because type
4626 information isn't in a very usable state at parse time. */
4628 skip_whitespace (fpnum
);
4630 if (strncmp (fpnum
, "0x", 2) == 0)
4634 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4635 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4645 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4647 unsigned fpword
= 0;
4650 /* Our FP word must be 32 bits (single-precision FP). */
4651 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4653 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4657 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4670 /* Shift operands. */
4673 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4676 struct asm_shift_name
4679 enum shift_kind kind
;
4682 /* Third argument to parse_shift. */
4683 enum parse_shift_mode
4685 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4686 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4687 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4688 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4689 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4692 /* Parse a <shift> specifier on an ARM data processing instruction.
4693 This has three forms:
4695 (LSL|LSR|ASL|ASR|ROR) Rs
4696 (LSL|LSR|ASL|ASR|ROR) #imm
4699 Note that ASL is assimilated to LSL in the instruction encoding, and
4700 RRX to ROR #0 (which cannot be written as such). */
4703 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4705 const struct asm_shift_name
*shift_name
;
4706 enum shift_kind shift
;
4711 for (p
= *str
; ISALPHA (*p
); p
++)
4716 inst
.error
= _("shift expression expected");
4720 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4723 if (shift_name
== NULL
)
4725 inst
.error
= _("shift expression expected");
4729 shift
= shift_name
->kind
;
4733 case NO_SHIFT_RESTRICT
:
4734 case SHIFT_IMMEDIATE
: break;
4736 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4737 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4739 inst
.error
= _("'LSL' or 'ASR' required");
4744 case SHIFT_LSL_IMMEDIATE
:
4745 if (shift
!= SHIFT_LSL
)
4747 inst
.error
= _("'LSL' required");
4752 case SHIFT_ASR_IMMEDIATE
:
4753 if (shift
!= SHIFT_ASR
)
4755 inst
.error
= _("'ASR' required");
4763 if (shift
!= SHIFT_RRX
)
4765 /* Whitespace can appear here if the next thing is a bare digit. */
4766 skip_whitespace (p
);
4768 if (mode
== NO_SHIFT_RESTRICT
4769 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4771 inst
.operands
[i
].imm
= reg
;
4772 inst
.operands
[i
].immisreg
= 1;
4774 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4777 inst
.operands
[i
].shift_kind
= shift
;
4778 inst
.operands
[i
].shifted
= 1;
4783 /* Parse a <shifter_operand> for an ARM data processing instruction:
4786 #<immediate>, <rotate>
4790 where <shift> is defined by parse_shift above, and <rotate> is a
4791 multiple of 2 between 0 and 30. Validation of immediate operands
4792 is deferred to md_apply_fix. */
4795 parse_shifter_operand (char **str
, int i
)
4800 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4802 inst
.operands
[i
].reg
= value
;
4803 inst
.operands
[i
].isreg
= 1;
4805 /* parse_shift will override this if appropriate */
4806 inst
.reloc
.exp
.X_op
= O_constant
;
4807 inst
.reloc
.exp
.X_add_number
= 0;
4809 if (skip_past_comma (str
) == FAIL
)
4812 /* Shift operation on register. */
4813 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4816 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4819 if (skip_past_comma (str
) == SUCCESS
)
4821 /* #x, y -- ie explicit rotation by Y. */
4822 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4825 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4827 inst
.error
= _("constant expression expected");
4831 value
= exp
.X_add_number
;
4832 if (value
< 0 || value
> 30 || value
% 2 != 0)
4834 inst
.error
= _("invalid rotation");
4837 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4839 inst
.error
= _("invalid constant");
4843 /* Convert to decoded value. md_apply_fix will put it back. */
4844 inst
.reloc
.exp
.X_add_number
4845 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4846 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4849 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4850 inst
.reloc
.pc_rel
= 0;
4854 /* Group relocation information. Each entry in the table contains the
4855 textual name of the relocation as may appear in assembler source
4856 and must end with a colon.
4857 Along with this textual name are the relocation codes to be used if
4858 the corresponding instruction is an ALU instruction (ADD or SUB only),
4859 an LDR, an LDRS, or an LDC. */
4861 struct group_reloc_table_entry
4872 /* Varieties of non-ALU group relocation. */
4879 static struct group_reloc_table_entry group_reloc_table
[] =
4880 { /* Program counter relative: */
4882 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4887 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4888 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4889 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4890 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4892 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4897 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4898 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4899 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4900 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4902 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4903 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4904 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4905 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4906 /* Section base relative */
4908 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4913 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4914 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4915 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4916 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4918 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4923 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4924 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4925 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4926 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4928 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4929 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4930 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4931 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4933 /* Given the address of a pointer pointing to the textual name of a group
4934 relocation as may appear in assembler source, attempt to find its details
4935 in group_reloc_table. The pointer will be updated to the character after
4936 the trailing colon. On failure, FAIL will be returned; SUCCESS
4937 otherwise. On success, *entry will be updated to point at the relevant
4938 group_reloc_table entry. */
4941 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4944 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4946 int length
= strlen (group_reloc_table
[i
].name
);
4948 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4949 && (*str
)[length
] == ':')
4951 *out
= &group_reloc_table
[i
];
4952 *str
+= (length
+ 1);
4960 /* Parse a <shifter_operand> for an ARM data processing instruction
4961 (as for parse_shifter_operand) where group relocations are allowed:
4964 #<immediate>, <rotate>
4965 #:<group_reloc>:<expression>
4969 where <group_reloc> is one of the strings defined in group_reloc_table.
4970 The hashes are optional.
4972 Everything else is as for parse_shifter_operand. */
4974 static parse_operand_result
4975 parse_shifter_operand_group_reloc (char **str
, int i
)
4977 /* Determine if we have the sequence of characters #: or just :
4978 coming next. If we do, then we check for a group relocation.
4979 If we don't, punt the whole lot to parse_shifter_operand. */
4981 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4982 || (*str
)[0] == ':')
4984 struct group_reloc_table_entry
*entry
;
4986 if ((*str
)[0] == '#')
4991 /* Try to parse a group relocation. Anything else is an error. */
4992 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4994 inst
.error
= _("unknown group relocation");
4995 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4998 /* We now have the group relocation table entry corresponding to
4999 the name in the assembler source. Next, we parse the expression. */
5000 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5001 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5003 /* Record the relocation type (always the ALU variant here). */
5004 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5005 gas_assert (inst
.reloc
.type
!= 0);
5007 return PARSE_OPERAND_SUCCESS
;
5010 return parse_shifter_operand (str
, i
) == SUCCESS
5011 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5013 /* Never reached. */
5016 /* Parse a Neon alignment expression. Information is written to
5017 inst.operands[i]. We assume the initial ':' has been skipped.
5019 align .imm = align << 8, .immisalign=1, .preind=0 */
5020 static parse_operand_result
5021 parse_neon_alignment (char **str
, int i
)
5026 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5028 if (exp
.X_op
!= O_constant
)
5030 inst
.error
= _("alignment must be constant");
5031 return PARSE_OPERAND_FAIL
;
5034 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5035 inst
.operands
[i
].immisalign
= 1;
5036 /* Alignments are not pre-indexes. */
5037 inst
.operands
[i
].preind
= 0;
5040 return PARSE_OPERAND_SUCCESS
;
5043 /* Parse all forms of an ARM address expression. Information is written
5044 to inst.operands[i] and/or inst.reloc.
5046 Preindexed addressing (.preind=1):
5048 [Rn, #offset] .reg=Rn .reloc.exp=offset
5049 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5050 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5051 .shift_kind=shift .reloc.exp=shift_imm
5053 These three may have a trailing ! which causes .writeback to be set also.
5055 Postindexed addressing (.postind=1, .writeback=1):
5057 [Rn], #offset .reg=Rn .reloc.exp=offset
5058 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5059 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5060 .shift_kind=shift .reloc.exp=shift_imm
5062 Unindexed addressing (.preind=0, .postind=0):
5064 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5068 [Rn]{!} shorthand for [Rn,#0]{!}
5069 =immediate .isreg=0 .reloc.exp=immediate
5070 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5072 It is the caller's responsibility to check for addressing modes not
5073 supported by the instruction, and to set inst.reloc.type. */
5075 static parse_operand_result
5076 parse_address_main (char **str
, int i
, int group_relocations
,
5077 group_reloc_type group_type
)
5082 if (skip_past_char (&p
, '[') == FAIL
)
5084 if (skip_past_char (&p
, '=') == FAIL
)
5086 /* Bare address - translate to PC-relative offset. */
5087 inst
.reloc
.pc_rel
= 1;
5088 inst
.operands
[i
].reg
= REG_PC
;
5089 inst
.operands
[i
].isreg
= 1;
5090 inst
.operands
[i
].preind
= 1;
5092 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5094 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5095 return PARSE_OPERAND_FAIL
;
5098 return PARSE_OPERAND_SUCCESS
;
5101 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5103 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5104 return PARSE_OPERAND_FAIL
;
5106 inst
.operands
[i
].reg
= reg
;
5107 inst
.operands
[i
].isreg
= 1;
5109 if (skip_past_comma (&p
) == SUCCESS
)
5111 inst
.operands
[i
].preind
= 1;
5114 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5116 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5118 inst
.operands
[i
].imm
= reg
;
5119 inst
.operands
[i
].immisreg
= 1;
5121 if (skip_past_comma (&p
) == SUCCESS
)
5122 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5123 return PARSE_OPERAND_FAIL
;
5125 else if (skip_past_char (&p
, ':') == SUCCESS
)
5127 /* FIXME: '@' should be used here, but it's filtered out by generic
5128 code before we get to see it here. This may be subject to
5130 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5132 if (result
!= PARSE_OPERAND_SUCCESS
)
5137 if (inst
.operands
[i
].negative
)
5139 inst
.operands
[i
].negative
= 0;
5143 if (group_relocations
5144 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5146 struct group_reloc_table_entry
*entry
;
5148 /* Skip over the #: or : sequence. */
5154 /* Try to parse a group relocation. Anything else is an
5156 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5158 inst
.error
= _("unknown group relocation");
5159 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5162 /* We now have the group relocation table entry corresponding to
5163 the name in the assembler source. Next, we parse the
5165 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5166 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5168 /* Record the relocation type. */
5172 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5176 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5180 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5187 if (inst
.reloc
.type
== 0)
5189 inst
.error
= _("this group relocation is not allowed on this instruction");
5190 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5194 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5195 return PARSE_OPERAND_FAIL
;
5198 else if (skip_past_char (&p
, ':') == SUCCESS
)
5200 /* FIXME: '@' should be used here, but it's filtered out by generic code
5201 before we get to see it here. This may be subject to change. */
5202 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5204 if (result
!= PARSE_OPERAND_SUCCESS
)
5208 if (skip_past_char (&p
, ']') == FAIL
)
5210 inst
.error
= _("']' expected");
5211 return PARSE_OPERAND_FAIL
;
5214 if (skip_past_char (&p
, '!') == SUCCESS
)
5215 inst
.operands
[i
].writeback
= 1;
5217 else if (skip_past_comma (&p
) == SUCCESS
)
5219 if (skip_past_char (&p
, '{') == SUCCESS
)
5221 /* [Rn], {expr} - unindexed, with option */
5222 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5223 0, 255, TRUE
) == FAIL
)
5224 return PARSE_OPERAND_FAIL
;
5226 if (skip_past_char (&p
, '}') == FAIL
)
5228 inst
.error
= _("'}' expected at end of 'option' field");
5229 return PARSE_OPERAND_FAIL
;
5231 if (inst
.operands
[i
].preind
)
5233 inst
.error
= _("cannot combine index with option");
5234 return PARSE_OPERAND_FAIL
;
5237 return PARSE_OPERAND_SUCCESS
;
5241 inst
.operands
[i
].postind
= 1;
5242 inst
.operands
[i
].writeback
= 1;
5244 if (inst
.operands
[i
].preind
)
5246 inst
.error
= _("cannot combine pre- and post-indexing");
5247 return PARSE_OPERAND_FAIL
;
5251 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5253 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5255 /* We might be using the immediate for alignment already. If we
5256 are, OR the register number into the low-order bits. */
5257 if (inst
.operands
[i
].immisalign
)
5258 inst
.operands
[i
].imm
|= reg
;
5260 inst
.operands
[i
].imm
= reg
;
5261 inst
.operands
[i
].immisreg
= 1;
5263 if (skip_past_comma (&p
) == SUCCESS
)
5264 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5265 return PARSE_OPERAND_FAIL
;
5269 if (inst
.operands
[i
].negative
)
5271 inst
.operands
[i
].negative
= 0;
5274 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5275 return PARSE_OPERAND_FAIL
;
5280 /* If at this point neither .preind nor .postind is set, we have a
5281 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5282 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5284 inst
.operands
[i
].preind
= 1;
5285 inst
.reloc
.exp
.X_op
= O_constant
;
5286 inst
.reloc
.exp
.X_add_number
= 0;
5289 return PARSE_OPERAND_SUCCESS
;
5293 parse_address (char **str
, int i
)
5295 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5299 static parse_operand_result
5300 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5302 return parse_address_main (str
, i
, 1, type
);
5305 /* Parse an operand for a MOVW or MOVT instruction. */
5307 parse_half (char **str
)
5312 skip_past_char (&p
, '#');
5313 if (strncasecmp (p
, ":lower16:", 9) == 0)
5314 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5315 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5316 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5318 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5321 skip_whitespace (p
);
5324 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5327 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5329 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5331 inst
.error
= _("constant expression expected");
5334 if (inst
.reloc
.exp
.X_add_number
< 0
5335 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5337 inst
.error
= _("immediate value out of range");
5345 /* Miscellaneous. */
5347 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5348 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5350 parse_psr (char **str
, bfd_boolean lhs
)
5353 unsigned long psr_field
;
5354 const struct asm_psr
*psr
;
5356 bfd_boolean is_apsr
= FALSE
;
5357 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
);
5359 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5360 feature for ease of use and backwards compatibility. */
5362 if (strncasecmp (p
, "SPSR", 4) == 0)
5365 goto unsupported_psr
;
5367 psr_field
= SPSR_BIT
;
5369 else if (strncasecmp (p
, "CPSR", 4) == 0)
5372 goto unsupported_psr
;
5376 else if (strncasecmp (p
, "APSR", 4) == 0)
5378 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5379 and ARMv7-R architecture CPUs. */
5388 while (ISALNUM (*p
) || *p
== '_');
5390 if (strncasecmp (start
, "iapsr", 5) == 0
5391 || strncasecmp (start
, "eapsr", 5) == 0
5392 || strncasecmp (start
, "xpsr", 4) == 0
5393 || strncasecmp (start
, "psr", 3) == 0)
5394 p
= start
+ strcspn (start
, "rR") + 1;
5396 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5402 /* If APSR is being written, a bitfield may be specified. Note that
5403 APSR itself is handled above. */
5404 if (psr
->field
<= 3)
5406 psr_field
= psr
->field
;
5412 /* M-profile MSR instructions have the mask field set to "10", except
5413 *PSR variants which modify APSR, which may use a different mask (and
5414 have been handled already). Do that by setting the PSR_f field
5416 return psr
->field
| (lhs
? PSR_f
: 0);
5419 goto unsupported_psr
;
5425 /* A suffix follows. */
5431 while (ISALNUM (*p
) || *p
== '_');
5435 /* APSR uses a notation for bits, rather than fields. */
5436 unsigned int nzcvq_bits
= 0;
5437 unsigned int g_bit
= 0;
5440 for (bit
= start
; bit
!= p
; bit
++)
5442 switch (TOLOWER (*bit
))
5445 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5449 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5453 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5457 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5461 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5465 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5469 inst
.error
= _("unexpected bit specified after APSR");
5474 if (nzcvq_bits
== 0x1f)
5479 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5481 inst
.error
= _("selected processor does not "
5482 "support DSP extension");
5489 if ((nzcvq_bits
& 0x20) != 0
5490 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5491 || (g_bit
& 0x2) != 0)
5493 inst
.error
= _("bad bitmask specified after APSR");
5499 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5504 psr_field
|= psr
->field
;
5510 goto error
; /* Garbage after "[CS]PSR". */
5512 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5513 is deprecated, but allow it anyway. */
5517 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5520 else if (!m_profile
)
5521 /* These bits are never right for M-profile devices: don't set them
5522 (only code paths which read/write APSR reach here). */
5523 psr_field
|= (PSR_c
| PSR_f
);
5529 inst
.error
= _("selected processor does not support requested special "
5530 "purpose register");
5534 inst
.error
= _("flag for {c}psr instruction expected");
5538 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5539 value suitable for splatting into the AIF field of the instruction. */
5542 parse_cps_flags (char **str
)
5551 case '\0': case ',':
5554 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5555 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5556 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5559 inst
.error
= _("unrecognized CPS flag");
5564 if (saw_a_flag
== 0)
5566 inst
.error
= _("missing CPS flags");
5574 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5575 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5578 parse_endian_specifier (char **str
)
5583 if (strncasecmp (s
, "BE", 2))
5585 else if (strncasecmp (s
, "LE", 2))
5589 inst
.error
= _("valid endian specifiers are be or le");
5593 if (ISALNUM (s
[2]) || s
[2] == '_')
5595 inst
.error
= _("valid endian specifiers are be or le");
5600 return little_endian
;
5603 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5604 value suitable for poking into the rotate field of an sxt or sxta
5605 instruction, or FAIL on error. */
5608 parse_ror (char **str
)
5613 if (strncasecmp (s
, "ROR", 3) == 0)
5617 inst
.error
= _("missing rotation field after comma");
5621 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5626 case 0: *str
= s
; return 0x0;
5627 case 8: *str
= s
; return 0x1;
5628 case 16: *str
= s
; return 0x2;
5629 case 24: *str
= s
; return 0x3;
5632 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5637 /* Parse a conditional code (from conds[] below). The value returned is in the
5638 range 0 .. 14, or FAIL. */
5640 parse_cond (char **str
)
5643 const struct asm_cond
*c
;
5645 /* Condition codes are always 2 characters, so matching up to
5646 3 characters is sufficient. */
5651 while (ISALPHA (*q
) && n
< 3)
5653 cond
[n
] = TOLOWER (*q
);
5658 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5661 inst
.error
= _("condition required");
5669 /* Parse an option for a barrier instruction. Returns the encoding for the
5672 parse_barrier (char **str
)
5675 const struct asm_barrier_opt
*o
;
5678 while (ISALPHA (*q
))
5681 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5690 /* Parse the operands of a table branch instruction. Similar to a memory
5693 parse_tb (char **str
)
5698 if (skip_past_char (&p
, '[') == FAIL
)
5700 inst
.error
= _("'[' expected");
5704 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5706 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5709 inst
.operands
[0].reg
= reg
;
5711 if (skip_past_comma (&p
) == FAIL
)
5713 inst
.error
= _("',' expected");
5717 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5719 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5722 inst
.operands
[0].imm
= reg
;
5724 if (skip_past_comma (&p
) == SUCCESS
)
5726 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5728 if (inst
.reloc
.exp
.X_add_number
!= 1)
5730 inst
.error
= _("invalid shift");
5733 inst
.operands
[0].shifted
= 1;
5736 if (skip_past_char (&p
, ']') == FAIL
)
5738 inst
.error
= _("']' expected");
5745 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5746 information on the types the operands can take and how they are encoded.
5747 Up to four operands may be read; this function handles setting the
5748 ".present" field for each read operand itself.
5749 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5750 else returns FAIL. */
5753 parse_neon_mov (char **str
, int *which_operand
)
5755 int i
= *which_operand
, val
;
5756 enum arm_reg_type rtype
;
5758 struct neon_type_el optype
;
5760 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5762 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5763 inst
.operands
[i
].reg
= val
;
5764 inst
.operands
[i
].isscalar
= 1;
5765 inst
.operands
[i
].vectype
= optype
;
5766 inst
.operands
[i
++].present
= 1;
5768 if (skip_past_comma (&ptr
) == FAIL
)
5771 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5774 inst
.operands
[i
].reg
= val
;
5775 inst
.operands
[i
].isreg
= 1;
5776 inst
.operands
[i
].present
= 1;
5778 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5781 /* Cases 0, 1, 2, 3, 5 (D only). */
5782 if (skip_past_comma (&ptr
) == FAIL
)
5785 inst
.operands
[i
].reg
= val
;
5786 inst
.operands
[i
].isreg
= 1;
5787 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5788 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5789 inst
.operands
[i
].isvec
= 1;
5790 inst
.operands
[i
].vectype
= optype
;
5791 inst
.operands
[i
++].present
= 1;
5793 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5795 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5796 Case 13: VMOV <Sd>, <Rm> */
5797 inst
.operands
[i
].reg
= val
;
5798 inst
.operands
[i
].isreg
= 1;
5799 inst
.operands
[i
].present
= 1;
5801 if (rtype
== REG_TYPE_NQ
)
5803 first_error (_("can't use Neon quad register here"));
5806 else if (rtype
!= REG_TYPE_VFS
)
5809 if (skip_past_comma (&ptr
) == FAIL
)
5811 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5813 inst
.operands
[i
].reg
= val
;
5814 inst
.operands
[i
].isreg
= 1;
5815 inst
.operands
[i
].present
= 1;
5818 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5821 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5822 Case 1: VMOV<c><q> <Dd>, <Dm>
5823 Case 8: VMOV.F32 <Sd>, <Sm>
5824 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5826 inst
.operands
[i
].reg
= val
;
5827 inst
.operands
[i
].isreg
= 1;
5828 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5829 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5830 inst
.operands
[i
].isvec
= 1;
5831 inst
.operands
[i
].vectype
= optype
;
5832 inst
.operands
[i
].present
= 1;
5834 if (skip_past_comma (&ptr
) == SUCCESS
)
5839 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5842 inst
.operands
[i
].reg
= val
;
5843 inst
.operands
[i
].isreg
= 1;
5844 inst
.operands
[i
++].present
= 1;
5846 if (skip_past_comma (&ptr
) == FAIL
)
5849 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5852 inst
.operands
[i
].reg
= val
;
5853 inst
.operands
[i
].isreg
= 1;
5854 inst
.operands
[i
++].present
= 1;
5857 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5858 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5859 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5860 Case 10: VMOV.F32 <Sd>, #<imm>
5861 Case 11: VMOV.F64 <Dd>, #<imm> */
5862 inst
.operands
[i
].immisfloat
= 1;
5863 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5864 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5865 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5869 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5873 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5876 inst
.operands
[i
].reg
= val
;
5877 inst
.operands
[i
].isreg
= 1;
5878 inst
.operands
[i
++].present
= 1;
5880 if (skip_past_comma (&ptr
) == FAIL
)
5883 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5885 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5886 inst
.operands
[i
].reg
= val
;
5887 inst
.operands
[i
].isscalar
= 1;
5888 inst
.operands
[i
].present
= 1;
5889 inst
.operands
[i
].vectype
= optype
;
5891 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5893 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5894 inst
.operands
[i
].reg
= val
;
5895 inst
.operands
[i
].isreg
= 1;
5896 inst
.operands
[i
++].present
= 1;
5898 if (skip_past_comma (&ptr
) == FAIL
)
5901 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5904 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5908 inst
.operands
[i
].reg
= val
;
5909 inst
.operands
[i
].isreg
= 1;
5910 inst
.operands
[i
].isvec
= 1;
5911 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5912 inst
.operands
[i
].vectype
= optype
;
5913 inst
.operands
[i
].present
= 1;
5915 if (rtype
== REG_TYPE_VFS
)
5919 if (skip_past_comma (&ptr
) == FAIL
)
5921 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5924 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5927 inst
.operands
[i
].reg
= val
;
5928 inst
.operands
[i
].isreg
= 1;
5929 inst
.operands
[i
].isvec
= 1;
5930 inst
.operands
[i
].issingle
= 1;
5931 inst
.operands
[i
].vectype
= optype
;
5932 inst
.operands
[i
].present
= 1;
5935 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5939 inst
.operands
[i
].reg
= val
;
5940 inst
.operands
[i
].isreg
= 1;
5941 inst
.operands
[i
].isvec
= 1;
5942 inst
.operands
[i
].issingle
= 1;
5943 inst
.operands
[i
].vectype
= optype
;
5944 inst
.operands
[i
++].present
= 1;
5949 first_error (_("parse error"));
5953 /* Successfully parsed the operands. Update args. */
5959 first_error (_("expected comma"));
5963 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5967 /* Use this macro when the operand constraints are different
5968 for ARM and THUMB (e.g. ldrd). */
5969 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5970 ((arm_operand) | ((thumb_operand) << 16))
5972 /* Matcher codes for parse_operands. */
5973 enum operand_parse_code
5975 OP_stop
, /* end of line */
5977 OP_RR
, /* ARM register */
5978 OP_RRnpc
, /* ARM register, not r15 */
5979 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5980 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5981 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5982 optional trailing ! */
5983 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5984 OP_RCP
, /* Coprocessor number */
5985 OP_RCN
, /* Coprocessor register */
5986 OP_RF
, /* FPA register */
5987 OP_RVS
, /* VFP single precision register */
5988 OP_RVD
, /* VFP double precision register (0..15) */
5989 OP_RND
, /* Neon double precision register (0..31) */
5990 OP_RNQ
, /* Neon quad precision register */
5991 OP_RVSD
, /* VFP single or double precision register */
5992 OP_RNDQ
, /* Neon double or quad precision register */
5993 OP_RNSDQ
, /* Neon single, double or quad precision register */
5994 OP_RNSC
, /* Neon scalar D[X] */
5995 OP_RVC
, /* VFP control register */
5996 OP_RMF
, /* Maverick F register */
5997 OP_RMD
, /* Maverick D register */
5998 OP_RMFX
, /* Maverick FX register */
5999 OP_RMDX
, /* Maverick DX register */
6000 OP_RMAX
, /* Maverick AX register */
6001 OP_RMDS
, /* Maverick DSPSC register */
6002 OP_RIWR
, /* iWMMXt wR register */
6003 OP_RIWC
, /* iWMMXt wC register */
6004 OP_RIWG
, /* iWMMXt wCG register */
6005 OP_RXA
, /* XScale accumulator register */
6007 OP_REGLST
, /* ARM register list */
6008 OP_VRSLST
, /* VFP single-precision register list */
6009 OP_VRDLST
, /* VFP double-precision register list */
6010 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6011 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6012 OP_NSTRLST
, /* Neon element/structure list */
6014 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6015 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6016 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6017 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6018 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6019 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6020 OP_VMOV
, /* Neon VMOV operands. */
6021 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6022 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6023 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6025 OP_I0
, /* immediate zero */
6026 OP_I7
, /* immediate value 0 .. 7 */
6027 OP_I15
, /* 0 .. 15 */
6028 OP_I16
, /* 1 .. 16 */
6029 OP_I16z
, /* 0 .. 16 */
6030 OP_I31
, /* 0 .. 31 */
6031 OP_I31w
, /* 0 .. 31, optional trailing ! */
6032 OP_I32
, /* 1 .. 32 */
6033 OP_I32z
, /* 0 .. 32 */
6034 OP_I63
, /* 0 .. 63 */
6035 OP_I63s
, /* -64 .. 63 */
6036 OP_I64
, /* 1 .. 64 */
6037 OP_I64z
, /* 0 .. 64 */
6038 OP_I255
, /* 0 .. 255 */
6040 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6041 OP_I7b
, /* 0 .. 7 */
6042 OP_I15b
, /* 0 .. 15 */
6043 OP_I31b
, /* 0 .. 31 */
6045 OP_SH
, /* shifter operand */
6046 OP_SHG
, /* shifter operand with possible group relocation */
6047 OP_ADDR
, /* Memory address expression (any mode) */
6048 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6049 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6050 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6051 OP_EXP
, /* arbitrary expression */
6052 OP_EXPi
, /* same, with optional immediate prefix */
6053 OP_EXPr
, /* same, with optional relocation suffix */
6054 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6056 OP_CPSF
, /* CPS flags */
6057 OP_ENDI
, /* Endianness specifier */
6058 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6059 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6060 OP_COND
, /* conditional code */
6061 OP_TB
, /* Table branch. */
6063 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6065 OP_RRnpc_I0
, /* ARM register or literal 0 */
6066 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6067 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6068 OP_RF_IF
, /* FPA register or immediate */
6069 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6070 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6072 /* Optional operands. */
6073 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6074 OP_oI31b
, /* 0 .. 31 */
6075 OP_oI32b
, /* 1 .. 32 */
6076 OP_oIffffb
, /* 0 .. 65535 */
6077 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6079 OP_oRR
, /* ARM register */
6080 OP_oRRnpc
, /* ARM register, not the PC */
6081 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6082 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6083 OP_oRND
, /* Optional Neon double precision register */
6084 OP_oRNQ
, /* Optional Neon quad precision register */
6085 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6086 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6087 OP_oSHll
, /* LSL immediate */
6088 OP_oSHar
, /* ASR immediate */
6089 OP_oSHllar
, /* LSL or ASR immediate */
6090 OP_oROR
, /* ROR 0/8/16/24 */
6091 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6093 /* Some pre-defined mixed (ARM/THUMB) operands. */
6094 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6095 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6096 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6098 OP_FIRST_OPTIONAL
= OP_oI7b
6101 /* Generic instruction operand parser. This does no encoding and no
6102 semantic validation; it merely squirrels values away in the inst
6103 structure. Returns SUCCESS or FAIL depending on whether the
6104 specified grammar matched. */
6106 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6108 unsigned const int *upat
= pattern
;
6109 char *backtrack_pos
= 0;
6110 const char *backtrack_error
= 0;
6111 int i
, val
, backtrack_index
= 0;
6112 enum arm_reg_type rtype
;
6113 parse_operand_result result
;
6114 unsigned int op_parse_code
;
6116 #define po_char_or_fail(chr) \
6119 if (skip_past_char (&str, chr) == FAIL) \
6124 #define po_reg_or_fail(regtype) \
6127 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6128 & inst.operands[i].vectype); \
6131 first_error (_(reg_expected_msgs[regtype])); \
6134 inst.operands[i].reg = val; \
6135 inst.operands[i].isreg = 1; \
6136 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6137 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6138 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6139 || rtype == REG_TYPE_VFD \
6140 || rtype == REG_TYPE_NQ); \
6144 #define po_reg_or_goto(regtype, label) \
6147 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6148 & inst.operands[i].vectype); \
6152 inst.operands[i].reg = val; \
6153 inst.operands[i].isreg = 1; \
6154 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6155 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6156 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6157 || rtype == REG_TYPE_VFD \
6158 || rtype == REG_TYPE_NQ); \
6162 #define po_imm_or_fail(min, max, popt) \
6165 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6167 inst.operands[i].imm = val; \
6171 #define po_scalar_or_goto(elsz, label) \
6174 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6177 inst.operands[i].reg = val; \
6178 inst.operands[i].isscalar = 1; \
6182 #define po_misc_or_fail(expr) \
6190 #define po_misc_or_fail_no_backtrack(expr) \
6194 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6195 backtrack_pos = 0; \
6196 if (result != PARSE_OPERAND_SUCCESS) \
6201 #define po_barrier_or_imm(str) \
6204 val = parse_barrier (&str); \
6207 if (ISALPHA (*str)) \
6214 if ((inst.instruction & 0xf0) == 0x60 \
6217 /* ISB can only take SY as an option. */ \
6218 inst.error = _("invalid barrier type"); \
6225 skip_whitespace (str
);
6227 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6229 op_parse_code
= upat
[i
];
6230 if (op_parse_code
>= 1<<16)
6231 op_parse_code
= thumb
? (op_parse_code
>> 16)
6232 : (op_parse_code
& ((1<<16)-1));
6234 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6236 /* Remember where we are in case we need to backtrack. */
6237 gas_assert (!backtrack_pos
);
6238 backtrack_pos
= str
;
6239 backtrack_error
= inst
.error
;
6240 backtrack_index
= i
;
6243 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6244 po_char_or_fail (',');
6246 switch (op_parse_code
)
6254 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6255 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6256 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6257 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6258 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6259 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6261 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6263 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6265 /* Also accept generic coprocessor regs for unknown registers. */
6267 po_reg_or_fail (REG_TYPE_CN
);
6269 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6270 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6271 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6272 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6273 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6274 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6275 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6276 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6277 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6278 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6280 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6282 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6283 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6285 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6287 /* Neon scalar. Using an element size of 8 means that some invalid
6288 scalars are accepted here, so deal with those in later code. */
6289 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6293 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6296 po_imm_or_fail (0, 0, TRUE
);
6301 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6306 po_scalar_or_goto (8, try_rr
);
6309 po_reg_or_fail (REG_TYPE_RN
);
6315 po_scalar_or_goto (8, try_nsdq
);
6318 po_reg_or_fail (REG_TYPE_NSDQ
);
6324 po_scalar_or_goto (8, try_ndq
);
6327 po_reg_or_fail (REG_TYPE_NDQ
);
6333 po_scalar_or_goto (8, try_vfd
);
6336 po_reg_or_fail (REG_TYPE_VFD
);
6341 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6342 not careful then bad things might happen. */
6343 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6348 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6351 /* There's a possibility of getting a 64-bit immediate here, so
6352 we need special handling. */
6353 if (parse_big_immediate (&str
, i
) == FAIL
)
6355 inst
.error
= _("immediate value is out of range");
6363 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6366 po_imm_or_fail (0, 63, TRUE
);
6371 po_char_or_fail ('[');
6372 po_reg_or_fail (REG_TYPE_RN
);
6373 po_char_or_fail (']');
6379 po_reg_or_fail (REG_TYPE_RN
);
6380 if (skip_past_char (&str
, '!') == SUCCESS
)
6381 inst
.operands
[i
].writeback
= 1;
6385 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6386 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6387 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6388 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6389 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6390 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6391 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6392 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6393 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6394 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6395 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6396 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6398 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6400 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6401 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6403 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6404 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6405 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6407 /* Immediate variants */
6409 po_char_or_fail ('{');
6410 po_imm_or_fail (0, 255, TRUE
);
6411 po_char_or_fail ('}');
6415 /* The expression parser chokes on a trailing !, so we have
6416 to find it first and zap it. */
6419 while (*s
&& *s
!= ',')
6424 inst
.operands
[i
].writeback
= 1;
6426 po_imm_or_fail (0, 31, TRUE
);
6434 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6439 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6444 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6446 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6448 val
= parse_reloc (&str
);
6451 inst
.error
= _("unrecognized relocation suffix");
6454 else if (val
!= BFD_RELOC_UNUSED
)
6456 inst
.operands
[i
].imm
= val
;
6457 inst
.operands
[i
].hasreloc
= 1;
6462 /* Operand for MOVW or MOVT. */
6464 po_misc_or_fail (parse_half (&str
));
6467 /* Register or expression. */
6468 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6469 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6471 /* Register or immediate. */
6472 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6473 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6475 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6477 if (!is_immediate_prefix (*str
))
6480 val
= parse_fpa_immediate (&str
);
6483 /* FPA immediates are encoded as registers 8-15.
6484 parse_fpa_immediate has already applied the offset. */
6485 inst
.operands
[i
].reg
= val
;
6486 inst
.operands
[i
].isreg
= 1;
6489 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6490 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6492 /* Two kinds of register. */
6495 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6497 || (rege
->type
!= REG_TYPE_MMXWR
6498 && rege
->type
!= REG_TYPE_MMXWC
6499 && rege
->type
!= REG_TYPE_MMXWCG
))
6501 inst
.error
= _("iWMMXt data or control register expected");
6504 inst
.operands
[i
].reg
= rege
->number
;
6505 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6511 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6513 || (rege
->type
!= REG_TYPE_MMXWC
6514 && rege
->type
!= REG_TYPE_MMXWCG
))
6516 inst
.error
= _("iWMMXt control register expected");
6519 inst
.operands
[i
].reg
= rege
->number
;
6520 inst
.operands
[i
].isreg
= 1;
6525 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6526 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6527 case OP_oROR
: val
= parse_ror (&str
); break;
6528 case OP_COND
: val
= parse_cond (&str
); break;
6529 case OP_oBARRIER_I15
:
6530 po_barrier_or_imm (str
); break;
6532 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6538 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6539 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6541 inst
.error
= _("Banked registers are not available with this "
6547 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6551 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6554 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6556 if (strncasecmp (str
, "APSR_", 5) == 0)
6563 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6564 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6565 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6566 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6567 default: found
= 16;
6571 inst
.operands
[i
].isvec
= 1;
6572 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6573 inst
.operands
[i
].reg
= REG_PC
;
6580 po_misc_or_fail (parse_tb (&str
));
6583 /* Register lists. */
6585 val
= parse_reg_list (&str
);
6588 inst
.operands
[1].writeback
= 1;
6594 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6598 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6602 /* Allow Q registers too. */
6603 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6608 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6610 inst
.operands
[i
].issingle
= 1;
6615 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6620 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6621 &inst
.operands
[i
].vectype
);
6624 /* Addressing modes */
6626 po_misc_or_fail (parse_address (&str
, i
));
6630 po_misc_or_fail_no_backtrack (
6631 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6635 po_misc_or_fail_no_backtrack (
6636 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6640 po_misc_or_fail_no_backtrack (
6641 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6645 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6649 po_misc_or_fail_no_backtrack (
6650 parse_shifter_operand_group_reloc (&str
, i
));
6654 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6658 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6662 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6666 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6669 /* Various value-based sanity checks and shared operations. We
6670 do not signal immediate failures for the register constraints;
6671 this allows a syntax error to take precedence. */
6672 switch (op_parse_code
)
6680 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6681 inst
.error
= BAD_PC
;
6686 if (inst
.operands
[i
].isreg
)
6688 if (inst
.operands
[i
].reg
== REG_PC
)
6689 inst
.error
= BAD_PC
;
6690 else if (inst
.operands
[i
].reg
== REG_SP
)
6691 inst
.error
= BAD_SP
;
6696 if (inst
.operands
[i
].isreg
6697 && inst
.operands
[i
].reg
== REG_PC
6698 && (inst
.operands
[i
].writeback
|| thumb
))
6699 inst
.error
= BAD_PC
;
6708 case OP_oBARRIER_I15
:
6717 inst
.operands
[i
].imm
= val
;
6724 /* If we get here, this operand was successfully parsed. */
6725 inst
.operands
[i
].present
= 1;
6729 inst
.error
= BAD_ARGS
;
6734 /* The parse routine should already have set inst.error, but set a
6735 default here just in case. */
6737 inst
.error
= _("syntax error");
6741 /* Do not backtrack over a trailing optional argument that
6742 absorbed some text. We will only fail again, with the
6743 'garbage following instruction' error message, which is
6744 probably less helpful than the current one. */
6745 if (backtrack_index
== i
&& backtrack_pos
!= str
6746 && upat
[i
+1] == OP_stop
)
6749 inst
.error
= _("syntax error");
6753 /* Try again, skipping the optional argument at backtrack_pos. */
6754 str
= backtrack_pos
;
6755 inst
.error
= backtrack_error
;
6756 inst
.operands
[backtrack_index
].present
= 0;
6757 i
= backtrack_index
;
6761 /* Check that we have parsed all the arguments. */
6762 if (*str
!= '\0' && !inst
.error
)
6763 inst
.error
= _("garbage following instruction");
6765 return inst
.error
? FAIL
: SUCCESS
;
6768 #undef po_char_or_fail
6769 #undef po_reg_or_fail
6770 #undef po_reg_or_goto
6771 #undef po_imm_or_fail
6772 #undef po_scalar_or_fail
6773 #undef po_barrier_or_imm
6775 /* Shorthand macro for instruction encoding functions issuing errors. */
6776 #define constraint(expr, err) \
6787 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6788 instructions are unpredictable if these registers are used. This
6789 is the BadReg predicate in ARM's Thumb-2 documentation. */
6790 #define reject_bad_reg(reg) \
6792 if (reg == REG_SP || reg == REG_PC) \
6794 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6799 /* If REG is R13 (the stack pointer), warn that its use is
6801 #define warn_deprecated_sp(reg) \
6803 if (warn_on_deprecated && reg == REG_SP) \
6804 as_warn (_("use of r13 is deprecated")); \
6807 /* Functions for operand encoding. ARM, then Thumb. */
6809 #define rotate_left(v, n) (v << n | v >> (32 - n))
6811 /* If VAL can be encoded in the immediate field of an ARM instruction,
6812 return the encoded form. Otherwise, return FAIL. */
6815 encode_arm_immediate (unsigned int val
)
6819 for (i
= 0; i
< 32; i
+= 2)
6820 if ((a
= rotate_left (val
, i
)) <= 0xff)
6821 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6826 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6827 return the encoded form. Otherwise, return FAIL. */
6829 encode_thumb32_immediate (unsigned int val
)
6836 for (i
= 1; i
<= 24; i
++)
6839 if ((val
& ~(0xff << i
)) == 0)
6840 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6844 if (val
== ((a
<< 16) | a
))
6846 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6850 if (val
== ((a
<< 16) | a
))
6851 return 0x200 | (a
>> 8);
6855 /* Encode a VFP SP or DP register number into inst.instruction. */
6858 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6860 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6863 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6866 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6869 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6874 first_error (_("D register out of range for selected VFP version"));
6882 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6886 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6890 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6894 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6898 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6902 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6910 /* Encode a <shift> in an ARM-format instruction. The immediate,
6911 if any, is handled by md_apply_fix. */
6913 encode_arm_shift (int i
)
6915 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6916 inst
.instruction
|= SHIFT_ROR
<< 5;
6919 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6920 if (inst
.operands
[i
].immisreg
)
6922 inst
.instruction
|= SHIFT_BY_REG
;
6923 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6926 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6931 encode_arm_shifter_operand (int i
)
6933 if (inst
.operands
[i
].isreg
)
6935 inst
.instruction
|= inst
.operands
[i
].reg
;
6936 encode_arm_shift (i
);
6939 inst
.instruction
|= INST_IMMEDIATE
;
6942 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6944 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6946 gas_assert (inst
.operands
[i
].isreg
);
6947 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6949 if (inst
.operands
[i
].preind
)
6953 inst
.error
= _("instruction does not accept preindexed addressing");
6956 inst
.instruction
|= PRE_INDEX
;
6957 if (inst
.operands
[i
].writeback
)
6958 inst
.instruction
|= WRITE_BACK
;
6961 else if (inst
.operands
[i
].postind
)
6963 gas_assert (inst
.operands
[i
].writeback
);
6965 inst
.instruction
|= WRITE_BACK
;
6967 else /* unindexed - only for coprocessor */
6969 inst
.error
= _("instruction does not accept unindexed addressing");
6973 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6974 && (((inst
.instruction
& 0x000f0000) >> 16)
6975 == ((inst
.instruction
& 0x0000f000) >> 12)))
6976 as_warn ((inst
.instruction
& LOAD_BIT
)
6977 ? _("destination register same as write-back base")
6978 : _("source register same as write-back base"));
6981 /* inst.operands[i] was set up by parse_address. Encode it into an
6982 ARM-format mode 2 load or store instruction. If is_t is true,
6983 reject forms that cannot be used with a T instruction (i.e. not
6986 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6988 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6990 encode_arm_addr_mode_common (i
, is_t
);
6992 if (inst
.operands
[i
].immisreg
)
6994 constraint ((inst
.operands
[i
].imm
== REG_PC
6995 || (is_pc
&& inst
.operands
[i
].writeback
)),
6997 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6998 inst
.instruction
|= inst
.operands
[i
].imm
;
6999 if (!inst
.operands
[i
].negative
)
7000 inst
.instruction
|= INDEX_UP
;
7001 if (inst
.operands
[i
].shifted
)
7003 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7004 inst
.instruction
|= SHIFT_ROR
<< 5;
7007 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7008 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7012 else /* immediate offset in inst.reloc */
7014 if (is_pc
&& !inst
.reloc
.pc_rel
)
7016 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7018 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7019 cannot use PC in addressing.
7020 PC cannot be used in writeback addressing, either. */
7021 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7024 /* Use of PC in str is deprecated for ARMv7. */
7025 if (warn_on_deprecated
7027 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7028 as_warn (_("use of PC in this instruction is deprecated"));
7031 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7032 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7036 /* inst.operands[i] was set up by parse_address. Encode it into an
7037 ARM-format mode 3 load or store instruction. Reject forms that
7038 cannot be used with such instructions. If is_t is true, reject
7039 forms that cannot be used with a T instruction (i.e. not
7042 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7044 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7046 inst
.error
= _("instruction does not accept scaled register index");
7050 encode_arm_addr_mode_common (i
, is_t
);
7052 if (inst
.operands
[i
].immisreg
)
7054 constraint ((inst
.operands
[i
].imm
== REG_PC
7055 || inst
.operands
[i
].reg
== REG_PC
),
7057 inst
.instruction
|= inst
.operands
[i
].imm
;
7058 if (!inst
.operands
[i
].negative
)
7059 inst
.instruction
|= INDEX_UP
;
7061 else /* immediate offset in inst.reloc */
7063 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7064 && inst
.operands
[i
].writeback
),
7066 inst
.instruction
|= HWOFFSET_IMM
;
7067 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7068 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7072 /* inst.operands[i] was set up by parse_address. Encode it into an
7073 ARM-format instruction. Reject all forms which cannot be encoded
7074 into a coprocessor load/store instruction. If wb_ok is false,
7075 reject use of writeback; if unind_ok is false, reject use of
7076 unindexed addressing. If reloc_override is not 0, use it instead
7077 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7078 (in which case it is preserved). */
7081 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7083 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7085 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7087 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7089 gas_assert (!inst
.operands
[i
].writeback
);
7092 inst
.error
= _("instruction does not support unindexed addressing");
7095 inst
.instruction
|= inst
.operands
[i
].imm
;
7096 inst
.instruction
|= INDEX_UP
;
7100 if (inst
.operands
[i
].preind
)
7101 inst
.instruction
|= PRE_INDEX
;
7103 if (inst
.operands
[i
].writeback
)
7105 if (inst
.operands
[i
].reg
== REG_PC
)
7107 inst
.error
= _("pc may not be used with write-back");
7112 inst
.error
= _("instruction does not support writeback");
7115 inst
.instruction
|= WRITE_BACK
;
7119 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7120 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7121 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7122 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7125 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7127 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7133 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7134 Determine whether it can be performed with a move instruction; if
7135 it can, convert inst.instruction to that move instruction and
7136 return TRUE; if it can't, convert inst.instruction to a literal-pool
7137 load and return FALSE. If this is not a valid thing to do in the
7138 current context, set inst.error and return TRUE.
7140 inst.operands[i] describes the destination register. */
7143 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7148 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7152 if ((inst
.instruction
& tbit
) == 0)
7154 inst
.error
= _("invalid pseudo operation");
7157 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7159 inst
.error
= _("constant expression expected");
7162 if (inst
.reloc
.exp
.X_op
== O_constant
)
7166 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7168 /* This can be done with a mov(1) instruction. */
7169 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7170 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7176 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7179 /* This can be done with a mov instruction. */
7180 inst
.instruction
&= LITERAL_MASK
;
7181 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7182 inst
.instruction
|= value
& 0xfff;
7186 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7189 /* This can be done with a mvn instruction. */
7190 inst
.instruction
&= LITERAL_MASK
;
7191 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7192 inst
.instruction
|= value
& 0xfff;
7198 if (add_to_lit_pool () == FAIL
)
7200 inst
.error
= _("literal pool insertion failed");
7203 inst
.operands
[1].reg
= REG_PC
;
7204 inst
.operands
[1].isreg
= 1;
7205 inst
.operands
[1].preind
= 1;
7206 inst
.reloc
.pc_rel
= 1;
7207 inst
.reloc
.type
= (thumb_p
7208 ? BFD_RELOC_ARM_THUMB_OFFSET
7210 ? BFD_RELOC_ARM_HWLITERAL
7211 : BFD_RELOC_ARM_LITERAL
));
7215 /* Functions for instruction encoding, sorted by sub-architecture.
7216 First some generics; their names are taken from the conventional
7217 bit positions for register arguments in ARM format instructions. */
7227 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7233 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7234 inst
.instruction
|= inst
.operands
[1].reg
;
7240 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7241 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7247 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7248 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7254 unsigned Rn
= inst
.operands
[2].reg
;
7255 /* Enforce restrictions on SWP instruction. */
7256 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7258 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7259 _("Rn must not overlap other operands"));
7261 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7262 if (warn_on_deprecated
7263 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7264 as_warn (_("swp{b} use is deprecated for this architecture"));
7267 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7268 inst
.instruction
|= inst
.operands
[1].reg
;
7269 inst
.instruction
|= Rn
<< 16;
7275 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7276 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7277 inst
.instruction
|= inst
.operands
[2].reg
;
7283 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7284 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7285 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7286 || inst
.reloc
.exp
.X_add_number
!= 0),
7288 inst
.instruction
|= inst
.operands
[0].reg
;
7289 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7290 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7296 inst
.instruction
|= inst
.operands
[0].imm
;
7302 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7303 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7306 /* ARM instructions, in alphabetical order by function name (except
7307 that wrapper functions appear immediately after the function they
7310 /* This is a pseudo-op of the form "adr rd, label" to be converted
7311 into a relative address of the form "add rd, pc, #label-.-8". */
7316 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7318 /* Frag hacking will turn this into a sub instruction if the offset turns
7319 out to be negative. */
7320 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7321 inst
.reloc
.pc_rel
= 1;
7322 inst
.reloc
.exp
.X_add_number
-= 8;
7325 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7326 into a relative address of the form:
7327 add rd, pc, #low(label-.-8)"
7328 add rd, rd, #high(label-.-8)" */
7333 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7335 /* Frag hacking will turn this into a sub instruction if the offset turns
7336 out to be negative. */
7337 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7338 inst
.reloc
.pc_rel
= 1;
7339 inst
.size
= INSN_SIZE
* 2;
7340 inst
.reloc
.exp
.X_add_number
-= 8;
7346 if (!inst
.operands
[1].present
)
7347 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7348 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7349 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7350 encode_arm_shifter_operand (2);
7356 if (inst
.operands
[0].present
)
7358 constraint ((inst
.instruction
& 0xf0) != 0x40
7359 && inst
.operands
[0].imm
> 0xf
7360 && inst
.operands
[0].imm
< 0x0,
7361 _("bad barrier type"));
7362 inst
.instruction
|= inst
.operands
[0].imm
;
7365 inst
.instruction
|= 0xf;
7371 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7372 constraint (msb
> 32, _("bit-field extends past end of register"));
7373 /* The instruction encoding stores the LSB and MSB,
7374 not the LSB and width. */
7375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7376 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7377 inst
.instruction
|= (msb
- 1) << 16;
7385 /* #0 in second position is alternative syntax for bfc, which is
7386 the same instruction but with REG_PC in the Rm field. */
7387 if (!inst
.operands
[1].isreg
)
7388 inst
.operands
[1].reg
= REG_PC
;
7390 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7391 constraint (msb
> 32, _("bit-field extends past end of register"));
7392 /* The instruction encoding stores the LSB and MSB,
7393 not the LSB and width. */
7394 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7395 inst
.instruction
|= inst
.operands
[1].reg
;
7396 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7397 inst
.instruction
|= (msb
- 1) << 16;
7403 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7404 _("bit-field extends past end of register"));
7405 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7406 inst
.instruction
|= inst
.operands
[1].reg
;
7407 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7408 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7411 /* ARM V5 breakpoint instruction (argument parse)
7412 BKPT <16 bit unsigned immediate>
7413 Instruction is not conditional.
7414 The bit pattern given in insns[] has the COND_ALWAYS condition,
7415 and it is an error if the caller tried to override that. */
7420 /* Top 12 of 16 bits to bits 19:8. */
7421 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7423 /* Bottom 4 of 16 bits to bits 3:0. */
7424 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7428 encode_branch (int default_reloc
)
7430 if (inst
.operands
[0].hasreloc
)
7432 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7433 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7434 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7435 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7436 ? BFD_RELOC_ARM_PLT32
7437 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7440 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7441 inst
.reloc
.pc_rel
= 1;
7448 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7449 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7452 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7459 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7461 if (inst
.cond
== COND_ALWAYS
)
7462 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7464 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7468 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7471 /* ARM V5 branch-link-exchange instruction (argument parse)
7472 BLX <target_addr> ie BLX(1)
7473 BLX{<condition>} <Rm> ie BLX(2)
7474 Unfortunately, there are two different opcodes for this mnemonic.
7475 So, the insns[].value is not used, and the code here zaps values
7476 into inst.instruction.
7477 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7482 if (inst
.operands
[0].isreg
)
7484 /* Arg is a register; the opcode provided by insns[] is correct.
7485 It is not illegal to do "blx pc", just useless. */
7486 if (inst
.operands
[0].reg
== REG_PC
)
7487 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7489 inst
.instruction
|= inst
.operands
[0].reg
;
7493 /* Arg is an address; this instruction cannot be executed
7494 conditionally, and the opcode must be adjusted.
7495 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7496 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7497 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7498 inst
.instruction
= 0xfa000000;
7499 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7506 bfd_boolean want_reloc
;
7508 if (inst
.operands
[0].reg
== REG_PC
)
7509 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7511 inst
.instruction
|= inst
.operands
[0].reg
;
7512 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7513 it is for ARMv4t or earlier. */
7514 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7515 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7519 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7524 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7528 /* ARM v5TEJ. Jump to Jazelle code. */
7533 if (inst
.operands
[0].reg
== REG_PC
)
7534 as_tsktsk (_("use of r15 in bxj is not really useful"));
7536 inst
.instruction
|= inst
.operands
[0].reg
;
7539 /* Co-processor data operation:
7540 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7541 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7545 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7546 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7547 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7548 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7549 inst
.instruction
|= inst
.operands
[4].reg
;
7550 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7556 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7557 encode_arm_shifter_operand (1);
7560 /* Transfer between coprocessor and ARM registers.
7561 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7566 No special properties. */
7573 Rd
= inst
.operands
[2].reg
;
7576 if (inst
.instruction
== 0xee000010
7577 || inst
.instruction
== 0xfe000010)
7579 reject_bad_reg (Rd
);
7582 constraint (Rd
== REG_SP
, BAD_SP
);
7587 if (inst
.instruction
== 0xe000010)
7588 constraint (Rd
== REG_PC
, BAD_PC
);
7592 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7593 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7594 inst
.instruction
|= Rd
<< 12;
7595 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7596 inst
.instruction
|= inst
.operands
[4].reg
;
7597 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7600 /* Transfer between coprocessor register and pair of ARM registers.
7601 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7606 Two XScale instructions are special cases of these:
7608 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7609 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7611 Result unpredictable if Rd or Rn is R15. */
7618 Rd
= inst
.operands
[2].reg
;
7619 Rn
= inst
.operands
[3].reg
;
7623 reject_bad_reg (Rd
);
7624 reject_bad_reg (Rn
);
7628 constraint (Rd
== REG_PC
, BAD_PC
);
7629 constraint (Rn
== REG_PC
, BAD_PC
);
7632 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7633 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7634 inst
.instruction
|= Rd
<< 12;
7635 inst
.instruction
|= Rn
<< 16;
7636 inst
.instruction
|= inst
.operands
[4].reg
;
7642 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7643 if (inst
.operands
[1].present
)
7645 inst
.instruction
|= CPSI_MMOD
;
7646 inst
.instruction
|= inst
.operands
[1].imm
;
7653 inst
.instruction
|= inst
.operands
[0].imm
;
7659 unsigned Rd
, Rn
, Rm
;
7661 Rd
= inst
.operands
[0].reg
;
7662 Rn
= (inst
.operands
[1].present
7663 ? inst
.operands
[1].reg
: Rd
);
7664 Rm
= inst
.operands
[2].reg
;
7666 constraint ((Rd
== REG_PC
), BAD_PC
);
7667 constraint ((Rn
== REG_PC
), BAD_PC
);
7668 constraint ((Rm
== REG_PC
), BAD_PC
);
7670 inst
.instruction
|= Rd
<< 16;
7671 inst
.instruction
|= Rn
<< 0;
7672 inst
.instruction
|= Rm
<< 8;
7678 /* There is no IT instruction in ARM mode. We
7679 process it to do the validation as if in
7680 thumb mode, just in case the code gets
7681 assembled for thumb using the unified syntax. */
7686 set_it_insn_type (IT_INSN
);
7687 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7688 now_it
.cc
= inst
.operands
[0].imm
;
7695 int base_reg
= inst
.operands
[0].reg
;
7696 int range
= inst
.operands
[1].imm
;
7698 inst
.instruction
|= base_reg
<< 16;
7699 inst
.instruction
|= range
;
7701 if (inst
.operands
[1].writeback
)
7702 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7704 if (inst
.operands
[0].writeback
)
7706 inst
.instruction
|= WRITE_BACK
;
7707 /* Check for unpredictable uses of writeback. */
7708 if (inst
.instruction
& LOAD_BIT
)
7710 /* Not allowed in LDM type 2. */
7711 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7712 && ((range
& (1 << REG_PC
)) == 0))
7713 as_warn (_("writeback of base register is UNPREDICTABLE"));
7714 /* Only allowed if base reg not in list for other types. */
7715 else if (range
& (1 << base_reg
))
7716 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7720 /* Not allowed for type 2. */
7721 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7722 as_warn (_("writeback of base register is UNPREDICTABLE"));
7723 /* Only allowed if base reg not in list, or first in list. */
7724 else if ((range
& (1 << base_reg
))
7725 && (range
& ((1 << base_reg
) - 1)))
7726 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7731 /* ARMv5TE load-consecutive (argument parse)
7740 constraint (inst
.operands
[0].reg
% 2 != 0,
7741 _("first destination register must be even"));
7742 constraint (inst
.operands
[1].present
7743 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7744 _("can only load two consecutive registers"));
7745 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7746 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7748 if (!inst
.operands
[1].present
)
7749 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7751 if (inst
.instruction
& LOAD_BIT
)
7753 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7754 register and the first register written; we have to diagnose
7755 overlap between the base and the second register written here. */
7757 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7758 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7759 as_warn (_("base register written back, and overlaps "
7760 "second destination register"));
7762 /* For an index-register load, the index register must not overlap the
7763 destination (even if not write-back). */
7764 else if (inst
.operands
[2].immisreg
7765 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7766 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7767 as_warn (_("index register overlaps destination register"));
7770 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7771 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7777 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7778 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7779 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7780 || inst
.operands
[1].negative
7781 /* This can arise if the programmer has written
7783 or if they have mistakenly used a register name as the last
7786 It is very difficult to distinguish between these two cases
7787 because "rX" might actually be a label. ie the register
7788 name has been occluded by a symbol of the same name. So we
7789 just generate a general 'bad addressing mode' type error
7790 message and leave it up to the programmer to discover the
7791 true cause and fix their mistake. */
7792 || (inst
.operands
[1].reg
== REG_PC
),
7795 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7796 || inst
.reloc
.exp
.X_add_number
!= 0,
7797 _("offset must be zero in ARM encoding"));
7799 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7801 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7802 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7803 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7809 constraint (inst
.operands
[0].reg
% 2 != 0,
7810 _("even register required"));
7811 constraint (inst
.operands
[1].present
7812 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7813 _("can only load two consecutive registers"));
7814 /* If op 1 were present and equal to PC, this function wouldn't
7815 have been called in the first place. */
7816 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7818 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7819 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7825 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7826 if (!inst
.operands
[1].isreg
)
7827 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7829 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7835 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7837 if (inst
.operands
[1].preind
)
7839 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7840 || inst
.reloc
.exp
.X_add_number
!= 0,
7841 _("this instruction requires a post-indexed address"));
7843 inst
.operands
[1].preind
= 0;
7844 inst
.operands
[1].postind
= 1;
7845 inst
.operands
[1].writeback
= 1;
7847 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7848 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7851 /* Halfword and signed-byte load/store operations. */
7856 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7857 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7858 if (!inst
.operands
[1].isreg
)
7859 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7861 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7867 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7869 if (inst
.operands
[1].preind
)
7871 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7872 || inst
.reloc
.exp
.X_add_number
!= 0,
7873 _("this instruction requires a post-indexed address"));
7875 inst
.operands
[1].preind
= 0;
7876 inst
.operands
[1].postind
= 1;
7877 inst
.operands
[1].writeback
= 1;
7879 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7880 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7883 /* Co-processor register load/store.
7884 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7888 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7889 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7890 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7896 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7897 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7898 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7899 && !(inst
.instruction
& 0x00400000))
7900 as_tsktsk (_("Rd and Rm should be different in mla"));
7902 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7903 inst
.instruction
|= inst
.operands
[1].reg
;
7904 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7905 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7912 encode_arm_shifter_operand (1);
7915 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7922 top
= (inst
.instruction
& 0x00400000) != 0;
7923 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7924 _(":lower16: not allowed this instruction"));
7925 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7926 _(":upper16: not allowed instruction"));
7927 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7928 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7930 imm
= inst
.reloc
.exp
.X_add_number
;
7931 /* The value is in two pieces: 0:11, 16:19. */
7932 inst
.instruction
|= (imm
& 0x00000fff);
7933 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7937 static void do_vfp_nsyn_opcode (const char *);
7940 do_vfp_nsyn_mrs (void)
7942 if (inst
.operands
[0].isvec
)
7944 if (inst
.operands
[1].reg
!= 1)
7945 first_error (_("operand 1 must be FPSCR"));
7946 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7947 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7948 do_vfp_nsyn_opcode ("fmstat");
7950 else if (inst
.operands
[1].isvec
)
7951 do_vfp_nsyn_opcode ("fmrx");
7959 do_vfp_nsyn_msr (void)
7961 if (inst
.operands
[0].isvec
)
7962 do_vfp_nsyn_opcode ("fmxr");
7972 unsigned Rt
= inst
.operands
[0].reg
;
7974 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7976 inst
.error
= BAD_SP
;
7980 /* APSR_ sets isvec. All other refs to PC are illegal. */
7981 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7983 inst
.error
= BAD_PC
;
7987 if (inst
.operands
[1].reg
!= 1)
7988 first_error (_("operand 1 must be FPSCR"));
7990 inst
.instruction
|= (Rt
<< 12);
7996 unsigned Rt
= inst
.operands
[1].reg
;
7999 reject_bad_reg (Rt
);
8000 else if (Rt
== REG_PC
)
8002 inst
.error
= BAD_PC
;
8006 if (inst
.operands
[0].reg
!= 1)
8007 first_error (_("operand 0 must be FPSCR"));
8009 inst
.instruction
|= (Rt
<< 12);
8017 if (do_vfp_nsyn_mrs () == SUCCESS
)
8020 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8023 if (inst
.operands
[1].isreg
)
8025 br
= inst
.operands
[1].reg
;
8026 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8027 as_bad (_("bad register for mrs"));
8031 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8032 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8034 _("'APSR', 'CPSR' or 'SPSR' expected"));
8035 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8038 inst
.instruction
|= br
;
8041 /* Two possible forms:
8042 "{C|S}PSR_<field>, Rm",
8043 "{C|S}PSR_f, #expression". */
8048 if (do_vfp_nsyn_msr () == SUCCESS
)
8051 inst
.instruction
|= inst
.operands
[0].imm
;
8052 if (inst
.operands
[1].isreg
)
8053 inst
.instruction
|= inst
.operands
[1].reg
;
8056 inst
.instruction
|= INST_IMMEDIATE
;
8057 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8058 inst
.reloc
.pc_rel
= 0;
8065 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8067 if (!inst
.operands
[2].present
)
8068 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8069 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8070 inst
.instruction
|= inst
.operands
[1].reg
;
8071 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8073 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8074 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8075 as_tsktsk (_("Rd and Rm should be different in mul"));
8078 /* Long Multiply Parser
8079 UMULL RdLo, RdHi, Rm, Rs
8080 SMULL RdLo, RdHi, Rm, Rs
8081 UMLAL RdLo, RdHi, Rm, Rs
8082 SMLAL RdLo, RdHi, Rm, Rs. */
8087 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8088 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8089 inst
.instruction
|= inst
.operands
[2].reg
;
8090 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8092 /* rdhi and rdlo must be different. */
8093 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8094 as_tsktsk (_("rdhi and rdlo must be different"));
8096 /* rdhi, rdlo and rm must all be different before armv6. */
8097 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8098 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8099 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8100 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8106 if (inst
.operands
[0].present
8107 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8109 /* Architectural NOP hints are CPSR sets with no bits selected. */
8110 inst
.instruction
&= 0xf0000000;
8111 inst
.instruction
|= 0x0320f000;
8112 if (inst
.operands
[0].present
)
8113 inst
.instruction
|= inst
.operands
[0].imm
;
8117 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8118 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8119 Condition defaults to COND_ALWAYS.
8120 Error if Rd, Rn or Rm are R15. */
8125 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8126 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8127 inst
.instruction
|= inst
.operands
[2].reg
;
8128 if (inst
.operands
[3].present
)
8129 encode_arm_shift (3);
8132 /* ARM V6 PKHTB (Argument Parse). */
8137 if (!inst
.operands
[3].present
)
8139 /* If the shift specifier is omitted, turn the instruction
8140 into pkhbt rd, rm, rn. */
8141 inst
.instruction
&= 0xfff00010;
8142 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8143 inst
.instruction
|= inst
.operands
[1].reg
;
8144 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8148 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8149 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8150 inst
.instruction
|= inst
.operands
[2].reg
;
8151 encode_arm_shift (3);
8155 /* ARMv5TE: Preload-Cache
8156 MP Extensions: Preload for write
8160 Syntactically, like LDR with B=1, W=0, L=1. */
8165 constraint (!inst
.operands
[0].isreg
,
8166 _("'[' expected after PLD mnemonic"));
8167 constraint (inst
.operands
[0].postind
,
8168 _("post-indexed expression used in preload instruction"));
8169 constraint (inst
.operands
[0].writeback
,
8170 _("writeback used in preload instruction"));
8171 constraint (!inst
.operands
[0].preind
,
8172 _("unindexed addressing used in preload instruction"));
8173 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8176 /* ARMv7: PLI <addr_mode> */
8180 constraint (!inst
.operands
[0].isreg
,
8181 _("'[' expected after PLI mnemonic"));
8182 constraint (inst
.operands
[0].postind
,
8183 _("post-indexed expression used in preload instruction"));
8184 constraint (inst
.operands
[0].writeback
,
8185 _("writeback used in preload instruction"));
8186 constraint (!inst
.operands
[0].preind
,
8187 _("unindexed addressing used in preload instruction"));
8188 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8189 inst
.instruction
&= ~PRE_INDEX
;
8195 inst
.operands
[1] = inst
.operands
[0];
8196 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8197 inst
.operands
[0].isreg
= 1;
8198 inst
.operands
[0].writeback
= 1;
8199 inst
.operands
[0].reg
= REG_SP
;
8203 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8204 word at the specified address and the following word
8206 Unconditionally executed.
8207 Error if Rn is R15. */
8212 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8213 if (inst
.operands
[0].writeback
)
8214 inst
.instruction
|= WRITE_BACK
;
8217 /* ARM V6 ssat (argument parse). */
8222 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8223 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8224 inst
.instruction
|= inst
.operands
[2].reg
;
8226 if (inst
.operands
[3].present
)
8227 encode_arm_shift (3);
8230 /* ARM V6 usat (argument parse). */
8235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8236 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8237 inst
.instruction
|= inst
.operands
[2].reg
;
8239 if (inst
.operands
[3].present
)
8240 encode_arm_shift (3);
8243 /* ARM V6 ssat16 (argument parse). */
8248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8249 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8250 inst
.instruction
|= inst
.operands
[2].reg
;
8256 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8257 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8258 inst
.instruction
|= inst
.operands
[2].reg
;
8261 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8262 preserving the other bits.
8264 setend <endian_specifier>, where <endian_specifier> is either
8270 if (inst
.operands
[0].imm
)
8271 inst
.instruction
|= 0x200;
8277 unsigned int Rm
= (inst
.operands
[1].present
8278 ? inst
.operands
[1].reg
8279 : inst
.operands
[0].reg
);
8281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8282 inst
.instruction
|= Rm
;
8283 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8285 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8286 inst
.instruction
|= SHIFT_BY_REG
;
8289 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8295 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8296 inst
.reloc
.pc_rel
= 0;
8302 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8303 inst
.reloc
.pc_rel
= 0;
8309 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8310 inst
.reloc
.pc_rel
= 0;
8313 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8314 SMLAxy{cond} Rd,Rm,Rs,Rn
8315 SMLAWy{cond} Rd,Rm,Rs,Rn
8316 Error if any register is R15. */
8321 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8322 inst
.instruction
|= inst
.operands
[1].reg
;
8323 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8324 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8327 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8328 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8329 Error if any register is R15.
8330 Warning if Rdlo == Rdhi. */
8335 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8336 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8337 inst
.instruction
|= inst
.operands
[2].reg
;
8338 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8340 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8341 as_tsktsk (_("rdhi and rdlo must be different"));
8344 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8345 SMULxy{cond} Rd,Rm,Rs
8346 Error if any register is R15. */
8351 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8352 inst
.instruction
|= inst
.operands
[1].reg
;
8353 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8356 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8357 the same for both ARM and Thumb-2. */
8364 if (inst
.operands
[0].present
)
8366 reg
= inst
.operands
[0].reg
;
8367 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8372 inst
.instruction
|= reg
<< 16;
8373 inst
.instruction
|= inst
.operands
[1].imm
;
8374 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8375 inst
.instruction
|= WRITE_BACK
;
8378 /* ARM V6 strex (argument parse). */
8383 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8384 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8385 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8386 || inst
.operands
[2].negative
8387 /* See comment in do_ldrex(). */
8388 || (inst
.operands
[2].reg
== REG_PC
),
8391 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8392 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8394 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8395 || inst
.reloc
.exp
.X_add_number
!= 0,
8396 _("offset must be zero in ARM encoding"));
8398 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8399 inst
.instruction
|= inst
.operands
[1].reg
;
8400 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8401 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8407 constraint (inst
.operands
[1].reg
% 2 != 0,
8408 _("even register required"));
8409 constraint (inst
.operands
[2].present
8410 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8411 _("can only store two consecutive registers"));
8412 /* If op 2 were present and equal to PC, this function wouldn't
8413 have been called in the first place. */
8414 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8416 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8417 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8418 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8421 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8422 inst
.instruction
|= inst
.operands
[1].reg
;
8423 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8426 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8427 extends it to 32-bits, and adds the result to a value in another
8428 register. You can specify a rotation by 0, 8, 16, or 24 bits
8429 before extracting the 16-bit value.
8430 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8431 Condition defaults to COND_ALWAYS.
8432 Error if any register uses R15. */
8437 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8438 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8439 inst
.instruction
|= inst
.operands
[2].reg
;
8440 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8445 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8446 Condition defaults to COND_ALWAYS.
8447 Error if any register uses R15. */
8452 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8453 inst
.instruction
|= inst
.operands
[1].reg
;
8454 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8457 /* VFP instructions. In a logical order: SP variant first, monad
8458 before dyad, arithmetic then move then load/store. */
8461 do_vfp_sp_monadic (void)
8463 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8464 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8468 do_vfp_sp_dyadic (void)
8470 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8471 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8472 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8476 do_vfp_sp_compare_z (void)
8478 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8482 do_vfp_dp_sp_cvt (void)
8484 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8485 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8489 do_vfp_sp_dp_cvt (void)
8491 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8492 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8496 do_vfp_reg_from_sp (void)
8498 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8499 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8503 do_vfp_reg2_from_sp2 (void)
8505 constraint (inst
.operands
[2].imm
!= 2,
8506 _("only two consecutive VFP SP registers allowed here"));
8507 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8508 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8509 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8513 do_vfp_sp_from_reg (void)
8515 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8516 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8520 do_vfp_sp2_from_reg2 (void)
8522 constraint (inst
.operands
[0].imm
!= 2,
8523 _("only two consecutive VFP SP registers allowed here"));
8524 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8525 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8526 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8530 do_vfp_sp_ldst (void)
8532 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8533 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8537 do_vfp_dp_ldst (void)
8539 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8540 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8545 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8547 if (inst
.operands
[0].writeback
)
8548 inst
.instruction
|= WRITE_BACK
;
8550 constraint (ldstm_type
!= VFP_LDSTMIA
,
8551 _("this addressing mode requires base-register writeback"));
8552 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8553 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8554 inst
.instruction
|= inst
.operands
[1].imm
;
8558 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8562 if (inst
.operands
[0].writeback
)
8563 inst
.instruction
|= WRITE_BACK
;
8565 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8566 _("this addressing mode requires base-register writeback"));
8568 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8569 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8571 count
= inst
.operands
[1].imm
<< 1;
8572 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8575 inst
.instruction
|= count
;
8579 do_vfp_sp_ldstmia (void)
8581 vfp_sp_ldstm (VFP_LDSTMIA
);
8585 do_vfp_sp_ldstmdb (void)
8587 vfp_sp_ldstm (VFP_LDSTMDB
);
8591 do_vfp_dp_ldstmia (void)
8593 vfp_dp_ldstm (VFP_LDSTMIA
);
8597 do_vfp_dp_ldstmdb (void)
8599 vfp_dp_ldstm (VFP_LDSTMDB
);
8603 do_vfp_xp_ldstmia (void)
8605 vfp_dp_ldstm (VFP_LDSTMIAX
);
8609 do_vfp_xp_ldstmdb (void)
8611 vfp_dp_ldstm (VFP_LDSTMDBX
);
8615 do_vfp_dp_rd_rm (void)
8617 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8618 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8622 do_vfp_dp_rn_rd (void)
8624 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8625 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8629 do_vfp_dp_rd_rn (void)
8631 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8632 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8636 do_vfp_dp_rd_rn_rm (void)
8638 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8639 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8640 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8646 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8650 do_vfp_dp_rm_rd_rn (void)
8652 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8653 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8654 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8657 /* VFPv3 instructions. */
8659 do_vfp_sp_const (void)
8661 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8662 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8663 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8667 do_vfp_dp_const (void)
8669 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8670 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8671 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8675 vfp_conv (int srcsize
)
8677 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8678 inst
.instruction
|= (immbits
& 1) << 5;
8679 inst
.instruction
|= (immbits
>> 1);
8683 do_vfp_sp_conv_16 (void)
8685 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8690 do_vfp_dp_conv_16 (void)
8692 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8697 do_vfp_sp_conv_32 (void)
8699 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8704 do_vfp_dp_conv_32 (void)
8706 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8710 /* FPA instructions. Also in a logical order. */
8715 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8716 inst
.instruction
|= inst
.operands
[1].reg
;
8720 do_fpa_ldmstm (void)
8722 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8723 switch (inst
.operands
[1].imm
)
8725 case 1: inst
.instruction
|= CP_T_X
; break;
8726 case 2: inst
.instruction
|= CP_T_Y
; break;
8727 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8732 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8734 /* The instruction specified "ea" or "fd", so we can only accept
8735 [Rn]{!}. The instruction does not really support stacking or
8736 unstacking, so we have to emulate these by setting appropriate
8737 bits and offsets. */
8738 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8739 || inst
.reloc
.exp
.X_add_number
!= 0,
8740 _("this instruction does not support indexing"));
8742 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8743 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8745 if (!(inst
.instruction
& INDEX_UP
))
8746 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8748 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8750 inst
.operands
[2].preind
= 0;
8751 inst
.operands
[2].postind
= 1;
8755 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8758 /* iWMMXt instructions: strictly in alphabetical order. */
8761 do_iwmmxt_tandorc (void)
8763 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8767 do_iwmmxt_textrc (void)
8769 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8770 inst
.instruction
|= inst
.operands
[1].imm
;
8774 do_iwmmxt_textrm (void)
8776 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8777 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8778 inst
.instruction
|= inst
.operands
[2].imm
;
8782 do_iwmmxt_tinsr (void)
8784 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8785 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8786 inst
.instruction
|= inst
.operands
[2].imm
;
8790 do_iwmmxt_tmia (void)
8792 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8793 inst
.instruction
|= inst
.operands
[1].reg
;
8794 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8798 do_iwmmxt_waligni (void)
8800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8801 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8802 inst
.instruction
|= inst
.operands
[2].reg
;
8803 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8807 do_iwmmxt_wmerge (void)
8809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8810 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8811 inst
.instruction
|= inst
.operands
[2].reg
;
8812 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8816 do_iwmmxt_wmov (void)
8818 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8819 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8820 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8821 inst
.instruction
|= inst
.operands
[1].reg
;
8825 do_iwmmxt_wldstbh (void)
8828 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8830 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8832 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8833 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8837 do_iwmmxt_wldstw (void)
8839 /* RIWR_RIWC clears .isreg for a control register. */
8840 if (!inst
.operands
[0].isreg
)
8842 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8843 inst
.instruction
|= 0xf0000000;
8846 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8847 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8851 do_iwmmxt_wldstd (void)
8853 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8854 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8855 && inst
.operands
[1].immisreg
)
8857 inst
.instruction
&= ~0x1a000ff;
8858 inst
.instruction
|= (0xf << 28);
8859 if (inst
.operands
[1].preind
)
8860 inst
.instruction
|= PRE_INDEX
;
8861 if (!inst
.operands
[1].negative
)
8862 inst
.instruction
|= INDEX_UP
;
8863 if (inst
.operands
[1].writeback
)
8864 inst
.instruction
|= WRITE_BACK
;
8865 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8866 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8867 inst
.instruction
|= inst
.operands
[1].imm
;
8870 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8874 do_iwmmxt_wshufh (void)
8876 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8877 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8878 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8879 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8883 do_iwmmxt_wzero (void)
8885 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8886 inst
.instruction
|= inst
.operands
[0].reg
;
8887 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8888 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8892 do_iwmmxt_wrwrwr_or_imm5 (void)
8894 if (inst
.operands
[2].isreg
)
8897 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8898 _("immediate operand requires iWMMXt2"));
8900 if (inst
.operands
[2].imm
== 0)
8902 switch ((inst
.instruction
>> 20) & 0xf)
8908 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8909 inst
.operands
[2].imm
= 16;
8910 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8916 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8917 inst
.operands
[2].imm
= 32;
8918 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8925 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8927 wrn
= (inst
.instruction
>> 16) & 0xf;
8928 inst
.instruction
&= 0xff0fff0f;
8929 inst
.instruction
|= wrn
;
8930 /* Bail out here; the instruction is now assembled. */
8935 /* Map 32 -> 0, etc. */
8936 inst
.operands
[2].imm
&= 0x1f;
8937 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8941 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8942 operations first, then control, shift, and load/store. */
8944 /* Insns like "foo X,Y,Z". */
8947 do_mav_triple (void)
8949 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8950 inst
.instruction
|= inst
.operands
[1].reg
;
8951 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8954 /* Insns like "foo W,X,Y,Z".
8955 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8960 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8961 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8962 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8963 inst
.instruction
|= inst
.operands
[3].reg
;
8966 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8970 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8973 /* Maverick shift immediate instructions.
8974 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8975 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8980 int imm
= inst
.operands
[2].imm
;
8982 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8983 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8985 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8986 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8987 Bit 4 should be 0. */
8988 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8990 inst
.instruction
|= imm
;
8993 /* XScale instructions. Also sorted arithmetic before move. */
8995 /* Xscale multiply-accumulate (argument parse)
8998 MIAxycc acc0,Rm,Rs. */
9003 inst
.instruction
|= inst
.operands
[1].reg
;
9004 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9007 /* Xscale move-accumulator-register (argument parse)
9009 MARcc acc0,RdLo,RdHi. */
9014 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9015 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9018 /* Xscale move-register-accumulator (argument parse)
9020 MRAcc RdLo,RdHi,acc0. */
9025 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9026 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9027 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9030 /* Encoding functions relevant only to Thumb. */
9032 /* inst.operands[i] is a shifted-register operand; encode
9033 it into inst.instruction in the format used by Thumb32. */
9036 encode_thumb32_shifted_operand (int i
)
9038 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9039 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9041 constraint (inst
.operands
[i
].immisreg
,
9042 _("shift by register not allowed in thumb mode"));
9043 inst
.instruction
|= inst
.operands
[i
].reg
;
9044 if (shift
== SHIFT_RRX
)
9045 inst
.instruction
|= SHIFT_ROR
<< 4;
9048 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9049 _("expression too complex"));
9051 constraint (value
> 32
9052 || (value
== 32 && (shift
== SHIFT_LSL
9053 || shift
== SHIFT_ROR
)),
9054 _("shift expression is too large"));
9058 else if (value
== 32)
9061 inst
.instruction
|= shift
<< 4;
9062 inst
.instruction
|= (value
& 0x1c) << 10;
9063 inst
.instruction
|= (value
& 0x03) << 6;
9068 /* inst.operands[i] was set up by parse_address. Encode it into a
9069 Thumb32 format load or store instruction. Reject forms that cannot
9070 be used with such instructions. If is_t is true, reject forms that
9071 cannot be used with a T instruction; if is_d is true, reject forms
9072 that cannot be used with a D instruction. If it is a store insn,
9076 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9078 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9080 constraint (!inst
.operands
[i
].isreg
,
9081 _("Instruction does not support =N addresses"));
9083 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9084 if (inst
.operands
[i
].immisreg
)
9086 constraint (is_pc
, BAD_PC_ADDRESSING
);
9087 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9088 constraint (inst
.operands
[i
].negative
,
9089 _("Thumb does not support negative register indexing"));
9090 constraint (inst
.operands
[i
].postind
,
9091 _("Thumb does not support register post-indexing"));
9092 constraint (inst
.operands
[i
].writeback
,
9093 _("Thumb does not support register indexing with writeback"));
9094 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9095 _("Thumb supports only LSL in shifted register indexing"));
9097 inst
.instruction
|= inst
.operands
[i
].imm
;
9098 if (inst
.operands
[i
].shifted
)
9100 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9101 _("expression too complex"));
9102 constraint (inst
.reloc
.exp
.X_add_number
< 0
9103 || inst
.reloc
.exp
.X_add_number
> 3,
9104 _("shift out of range"));
9105 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9107 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9109 else if (inst
.operands
[i
].preind
)
9111 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9112 constraint (is_t
&& inst
.operands
[i
].writeback
,
9113 _("cannot use writeback with this instruction"));
9114 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
9115 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
9119 inst
.instruction
|= 0x01000000;
9120 if (inst
.operands
[i
].writeback
)
9121 inst
.instruction
|= 0x00200000;
9125 inst
.instruction
|= 0x00000c00;
9126 if (inst
.operands
[i
].writeback
)
9127 inst
.instruction
|= 0x00000100;
9129 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9131 else if (inst
.operands
[i
].postind
)
9133 gas_assert (inst
.operands
[i
].writeback
);
9134 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9135 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9138 inst
.instruction
|= 0x00200000;
9140 inst
.instruction
|= 0x00000900;
9141 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9143 else /* unindexed - only for coprocessor */
9144 inst
.error
= _("instruction does not accept unindexed addressing");
9147 /* Table of Thumb instructions which exist in both 16- and 32-bit
9148 encodings (the latter only in post-V6T2 cores). The index is the
9149 value used in the insns table below. When there is more than one
9150 possible 16-bit encoding for the instruction, this table always
9152 Also contains several pseudo-instructions used during relaxation. */
9153 #define T16_32_TAB \
9154 X(_adc, 4140, eb400000), \
9155 X(_adcs, 4140, eb500000), \
9156 X(_add, 1c00, eb000000), \
9157 X(_adds, 1c00, eb100000), \
9158 X(_addi, 0000, f1000000), \
9159 X(_addis, 0000, f1100000), \
9160 X(_add_pc,000f, f20f0000), \
9161 X(_add_sp,000d, f10d0000), \
9162 X(_adr, 000f, f20f0000), \
9163 X(_and, 4000, ea000000), \
9164 X(_ands, 4000, ea100000), \
9165 X(_asr, 1000, fa40f000), \
9166 X(_asrs, 1000, fa50f000), \
9167 X(_b, e000, f000b000), \
9168 X(_bcond, d000, f0008000), \
9169 X(_bic, 4380, ea200000), \
9170 X(_bics, 4380, ea300000), \
9171 X(_cmn, 42c0, eb100f00), \
9172 X(_cmp, 2800, ebb00f00), \
9173 X(_cpsie, b660, f3af8400), \
9174 X(_cpsid, b670, f3af8600), \
9175 X(_cpy, 4600, ea4f0000), \
9176 X(_dec_sp,80dd, f1ad0d00), \
9177 X(_eor, 4040, ea800000), \
9178 X(_eors, 4040, ea900000), \
9179 X(_inc_sp,00dd, f10d0d00), \
9180 X(_ldmia, c800, e8900000), \
9181 X(_ldr, 6800, f8500000), \
9182 X(_ldrb, 7800, f8100000), \
9183 X(_ldrh, 8800, f8300000), \
9184 X(_ldrsb, 5600, f9100000), \
9185 X(_ldrsh, 5e00, f9300000), \
9186 X(_ldr_pc,4800, f85f0000), \
9187 X(_ldr_pc2,4800, f85f0000), \
9188 X(_ldr_sp,9800, f85d0000), \
9189 X(_lsl, 0000, fa00f000), \
9190 X(_lsls, 0000, fa10f000), \
9191 X(_lsr, 0800, fa20f000), \
9192 X(_lsrs, 0800, fa30f000), \
9193 X(_mov, 2000, ea4f0000), \
9194 X(_movs, 2000, ea5f0000), \
9195 X(_mul, 4340, fb00f000), \
9196 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9197 X(_mvn, 43c0, ea6f0000), \
9198 X(_mvns, 43c0, ea7f0000), \
9199 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9200 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9201 X(_orr, 4300, ea400000), \
9202 X(_orrs, 4300, ea500000), \
9203 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9204 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9205 X(_rev, ba00, fa90f080), \
9206 X(_rev16, ba40, fa90f090), \
9207 X(_revsh, bac0, fa90f0b0), \
9208 X(_ror, 41c0, fa60f000), \
9209 X(_rors, 41c0, fa70f000), \
9210 X(_sbc, 4180, eb600000), \
9211 X(_sbcs, 4180, eb700000), \
9212 X(_stmia, c000, e8800000), \
9213 X(_str, 6000, f8400000), \
9214 X(_strb, 7000, f8000000), \
9215 X(_strh, 8000, f8200000), \
9216 X(_str_sp,9000, f84d0000), \
9217 X(_sub, 1e00, eba00000), \
9218 X(_subs, 1e00, ebb00000), \
9219 X(_subi, 8000, f1a00000), \
9220 X(_subis, 8000, f1b00000), \
9221 X(_sxtb, b240, fa4ff080), \
9222 X(_sxth, b200, fa0ff080), \
9223 X(_tst, 4200, ea100f00), \
9224 X(_uxtb, b2c0, fa5ff080), \
9225 X(_uxth, b280, fa1ff080), \
9226 X(_nop, bf00, f3af8000), \
9227 X(_yield, bf10, f3af8001), \
9228 X(_wfe, bf20, f3af8002), \
9229 X(_wfi, bf30, f3af8003), \
9230 X(_sev, bf40, f3af8004),
9232 /* To catch errors in encoding functions, the codes are all offset by
9233 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9234 as 16-bit instructions. */
9235 #define X(a,b,c) T_MNEM##a
9236 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9239 #define X(a,b,c) 0x##b
9240 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9241 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9244 #define X(a,b,c) 0x##c
9245 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9246 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9247 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9251 /* Thumb instruction encoders, in alphabetical order. */
9256 do_t_add_sub_w (void)
9260 Rd
= inst
.operands
[0].reg
;
9261 Rn
= inst
.operands
[1].reg
;
9263 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9264 is the SP-{plus,minus}-immediate form of the instruction. */
9266 constraint (Rd
== REG_PC
, BAD_PC
);
9268 reject_bad_reg (Rd
);
9270 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9271 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9274 /* Parse an add or subtract instruction. We get here with inst.instruction
9275 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9282 Rd
= inst
.operands
[0].reg
;
9283 Rs
= (inst
.operands
[1].present
9284 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9285 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9288 set_it_insn_type_last ();
9296 flags
= (inst
.instruction
== T_MNEM_adds
9297 || inst
.instruction
== T_MNEM_subs
);
9299 narrow
= !in_it_block ();
9301 narrow
= in_it_block ();
9302 if (!inst
.operands
[2].isreg
)
9306 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9308 add
= (inst
.instruction
== T_MNEM_add
9309 || inst
.instruction
== T_MNEM_adds
);
9311 if (inst
.size_req
!= 4)
9313 /* Attempt to use a narrow opcode, with relaxation if
9315 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9316 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9317 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9318 opcode
= T_MNEM_add_sp
;
9319 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9320 opcode
= T_MNEM_add_pc
;
9321 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9324 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9326 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9330 inst
.instruction
= THUMB_OP16(opcode
);
9331 inst
.instruction
|= (Rd
<< 4) | Rs
;
9332 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9333 if (inst
.size_req
!= 2)
9334 inst
.relax
= opcode
;
9337 constraint (inst
.size_req
== 2, BAD_HIREG
);
9339 if (inst
.size_req
== 4
9340 || (inst
.size_req
!= 2 && !opcode
))
9344 constraint (add
, BAD_PC
);
9345 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9346 _("only SUBS PC, LR, #const allowed"));
9347 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9348 _("expression too complex"));
9349 constraint (inst
.reloc
.exp
.X_add_number
< 0
9350 || inst
.reloc
.exp
.X_add_number
> 0xff,
9351 _("immediate value out of range"));
9352 inst
.instruction
= T2_SUBS_PC_LR
9353 | inst
.reloc
.exp
.X_add_number
;
9354 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9357 else if (Rs
== REG_PC
)
9359 /* Always use addw/subw. */
9360 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9361 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9365 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9366 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9369 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9371 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9373 inst
.instruction
|= Rd
<< 8;
9374 inst
.instruction
|= Rs
<< 16;
9379 Rn
= inst
.operands
[2].reg
;
9380 /* See if we can do this with a 16-bit instruction. */
9381 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9383 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9388 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9389 || inst
.instruction
== T_MNEM_add
)
9392 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9396 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9398 /* Thumb-1 cores (except v6-M) require at least one high
9399 register in a narrow non flag setting add. */
9400 if (Rd
> 7 || Rn
> 7
9401 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9402 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9409 inst
.instruction
= T_OPCODE_ADD_HI
;
9410 inst
.instruction
|= (Rd
& 8) << 4;
9411 inst
.instruction
|= (Rd
& 7);
9412 inst
.instruction
|= Rn
<< 3;
9418 constraint (Rd
== REG_PC
, BAD_PC
);
9419 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9420 constraint (Rs
== REG_PC
, BAD_PC
);
9421 reject_bad_reg (Rn
);
9423 /* If we get here, it can't be done in 16 bits. */
9424 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9425 _("shift must be constant"));
9426 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9427 inst
.instruction
|= Rd
<< 8;
9428 inst
.instruction
|= Rs
<< 16;
9429 encode_thumb32_shifted_operand (2);
9434 constraint (inst
.instruction
== T_MNEM_adds
9435 || inst
.instruction
== T_MNEM_subs
,
9438 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9440 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9441 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9444 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9446 inst
.instruction
|= (Rd
<< 4) | Rs
;
9447 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9451 Rn
= inst
.operands
[2].reg
;
9452 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9454 /* We now have Rd, Rs, and Rn set to registers. */
9455 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9457 /* Can't do this for SUB. */
9458 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9459 inst
.instruction
= T_OPCODE_ADD_HI
;
9460 inst
.instruction
|= (Rd
& 8) << 4;
9461 inst
.instruction
|= (Rd
& 7);
9463 inst
.instruction
|= Rn
<< 3;
9465 inst
.instruction
|= Rs
<< 3;
9467 constraint (1, _("dest must overlap one source register"));
9471 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9472 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9473 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9483 Rd
= inst
.operands
[0].reg
;
9484 reject_bad_reg (Rd
);
9486 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9488 /* Defer to section relaxation. */
9489 inst
.relax
= inst
.instruction
;
9490 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9491 inst
.instruction
|= Rd
<< 4;
9493 else if (unified_syntax
&& inst
.size_req
!= 2)
9495 /* Generate a 32-bit opcode. */
9496 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9497 inst
.instruction
|= Rd
<< 8;
9498 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9499 inst
.reloc
.pc_rel
= 1;
9503 /* Generate a 16-bit opcode. */
9504 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9505 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9506 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9507 inst
.reloc
.pc_rel
= 1;
9509 inst
.instruction
|= Rd
<< 4;
9513 /* Arithmetic instructions for which there is just one 16-bit
9514 instruction encoding, and it allows only two low registers.
9515 For maximal compatibility with ARM syntax, we allow three register
9516 operands even when Thumb-32 instructions are not available, as long
9517 as the first two are identical. For instance, both "sbc r0,r1" and
9518 "sbc r0,r0,r1" are allowed. */
9524 Rd
= inst
.operands
[0].reg
;
9525 Rs
= (inst
.operands
[1].present
9526 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9527 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9528 Rn
= inst
.operands
[2].reg
;
9530 reject_bad_reg (Rd
);
9531 reject_bad_reg (Rs
);
9532 if (inst
.operands
[2].isreg
)
9533 reject_bad_reg (Rn
);
9537 if (!inst
.operands
[2].isreg
)
9539 /* For an immediate, we always generate a 32-bit opcode;
9540 section relaxation will shrink it later if possible. */
9541 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9542 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9543 inst
.instruction
|= Rd
<< 8;
9544 inst
.instruction
|= Rs
<< 16;
9545 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9551 /* See if we can do this with a 16-bit instruction. */
9552 if (THUMB_SETS_FLAGS (inst
.instruction
))
9553 narrow
= !in_it_block ();
9555 narrow
= in_it_block ();
9557 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9559 if (inst
.operands
[2].shifted
)
9561 if (inst
.size_req
== 4)
9567 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9568 inst
.instruction
|= Rd
;
9569 inst
.instruction
|= Rn
<< 3;
9573 /* If we get here, it can't be done in 16 bits. */
9574 constraint (inst
.operands
[2].shifted
9575 && inst
.operands
[2].immisreg
,
9576 _("shift must be constant"));
9577 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9578 inst
.instruction
|= Rd
<< 8;
9579 inst
.instruction
|= Rs
<< 16;
9580 encode_thumb32_shifted_operand (2);
9585 /* On its face this is a lie - the instruction does set the
9586 flags. However, the only supported mnemonic in this mode
9588 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9590 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9591 _("unshifted register required"));
9592 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9593 constraint (Rd
!= Rs
,
9594 _("dest and source1 must be the same register"));
9596 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9597 inst
.instruction
|= Rd
;
9598 inst
.instruction
|= Rn
<< 3;
9602 /* Similarly, but for instructions where the arithmetic operation is
9603 commutative, so we can allow either of them to be different from
9604 the destination operand in a 16-bit instruction. For instance, all
9605 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9612 Rd
= inst
.operands
[0].reg
;
9613 Rs
= (inst
.operands
[1].present
9614 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9615 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9616 Rn
= inst
.operands
[2].reg
;
9618 reject_bad_reg (Rd
);
9619 reject_bad_reg (Rs
);
9620 if (inst
.operands
[2].isreg
)
9621 reject_bad_reg (Rn
);
9625 if (!inst
.operands
[2].isreg
)
9627 /* For an immediate, we always generate a 32-bit opcode;
9628 section relaxation will shrink it later if possible. */
9629 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9630 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9631 inst
.instruction
|= Rd
<< 8;
9632 inst
.instruction
|= Rs
<< 16;
9633 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9639 /* See if we can do this with a 16-bit instruction. */
9640 if (THUMB_SETS_FLAGS (inst
.instruction
))
9641 narrow
= !in_it_block ();
9643 narrow
= in_it_block ();
9645 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9647 if (inst
.operands
[2].shifted
)
9649 if (inst
.size_req
== 4)
9656 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9657 inst
.instruction
|= Rd
;
9658 inst
.instruction
|= Rn
<< 3;
9663 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9664 inst
.instruction
|= Rd
;
9665 inst
.instruction
|= Rs
<< 3;
9670 /* If we get here, it can't be done in 16 bits. */
9671 constraint (inst
.operands
[2].shifted
9672 && inst
.operands
[2].immisreg
,
9673 _("shift must be constant"));
9674 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9675 inst
.instruction
|= Rd
<< 8;
9676 inst
.instruction
|= Rs
<< 16;
9677 encode_thumb32_shifted_operand (2);
9682 /* On its face this is a lie - the instruction does set the
9683 flags. However, the only supported mnemonic in this mode
9685 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9687 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9688 _("unshifted register required"));
9689 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9691 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9692 inst
.instruction
|= Rd
;
9695 inst
.instruction
|= Rn
<< 3;
9697 inst
.instruction
|= Rs
<< 3;
9699 constraint (1, _("dest must overlap one source register"));
9706 if (inst
.operands
[0].present
)
9708 constraint ((inst
.instruction
& 0xf0) != 0x40
9709 && inst
.operands
[0].imm
> 0xf
9710 && inst
.operands
[0].imm
< 0x0,
9711 _("bad barrier type"));
9712 inst
.instruction
|= inst
.operands
[0].imm
;
9715 inst
.instruction
|= 0xf;
9722 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9723 constraint (msb
> 32, _("bit-field extends past end of register"));
9724 /* The instruction encoding stores the LSB and MSB,
9725 not the LSB and width. */
9726 Rd
= inst
.operands
[0].reg
;
9727 reject_bad_reg (Rd
);
9728 inst
.instruction
|= Rd
<< 8;
9729 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9730 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9731 inst
.instruction
|= msb
- 1;
9740 Rd
= inst
.operands
[0].reg
;
9741 reject_bad_reg (Rd
);
9743 /* #0 in second position is alternative syntax for bfc, which is
9744 the same instruction but with REG_PC in the Rm field. */
9745 if (!inst
.operands
[1].isreg
)
9749 Rn
= inst
.operands
[1].reg
;
9750 reject_bad_reg (Rn
);
9753 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9754 constraint (msb
> 32, _("bit-field extends past end of register"));
9755 /* The instruction encoding stores the LSB and MSB,
9756 not the LSB and width. */
9757 inst
.instruction
|= Rd
<< 8;
9758 inst
.instruction
|= Rn
<< 16;
9759 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9760 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9761 inst
.instruction
|= msb
- 1;
9769 Rd
= inst
.operands
[0].reg
;
9770 Rn
= inst
.operands
[1].reg
;
9772 reject_bad_reg (Rd
);
9773 reject_bad_reg (Rn
);
9775 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9776 _("bit-field extends past end of register"));
9777 inst
.instruction
|= Rd
<< 8;
9778 inst
.instruction
|= Rn
<< 16;
9779 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9780 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9781 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9784 /* ARM V5 Thumb BLX (argument parse)
9785 BLX <target_addr> which is BLX(1)
9786 BLX <Rm> which is BLX(2)
9787 Unfortunately, there are two different opcodes for this mnemonic.
9788 So, the insns[].value is not used, and the code here zaps values
9789 into inst.instruction.
9791 ??? How to take advantage of the additional two bits of displacement
9792 available in Thumb32 mode? Need new relocation? */
9797 set_it_insn_type_last ();
9799 if (inst
.operands
[0].isreg
)
9801 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9802 /* We have a register, so this is BLX(2). */
9803 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9807 /* No register. This must be BLX(1). */
9808 inst
.instruction
= 0xf000e800;
9809 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
9821 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9825 /* Conditional branches inside IT blocks are encoded as unconditional
9832 if (cond
!= COND_ALWAYS
)
9833 opcode
= T_MNEM_bcond
;
9835 opcode
= inst
.instruction
;
9838 && (inst
.size_req
== 4
9839 || (inst
.size_req
!= 2 && inst
.operands
[0].hasreloc
)))
9841 inst
.instruction
= THUMB_OP32(opcode
);
9842 if (cond
== COND_ALWAYS
)
9843 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9846 gas_assert (cond
!= 0xF);
9847 inst
.instruction
|= cond
<< 22;
9848 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9853 inst
.instruction
= THUMB_OP16(opcode
);
9854 if (cond
== COND_ALWAYS
)
9855 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9858 inst
.instruction
|= cond
<< 8;
9859 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9861 /* Allow section relaxation. */
9862 if (unified_syntax
&& inst
.size_req
!= 2)
9863 inst
.relax
= opcode
;
9865 inst
.reloc
.type
= reloc
;
9866 inst
.reloc
.pc_rel
= 1;
9872 constraint (inst
.cond
!= COND_ALWAYS
,
9873 _("instruction is always unconditional"));
9874 if (inst
.operands
[0].present
)
9876 constraint (inst
.operands
[0].imm
> 255,
9877 _("immediate value out of range"));
9878 inst
.instruction
|= inst
.operands
[0].imm
;
9879 set_it_insn_type (NEUTRAL_IT_INSN
);
9884 do_t_branch23 (void)
9886 set_it_insn_type_last ();
9887 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
9889 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
9890 this file. We used to simply ignore the PLT reloc type here --
9891 the branch encoding is now needed to deal with TLSCALL relocs.
9892 So if we see a PLT reloc now, put it back to how it used to be to
9893 keep the preexisting behaviour. */
9894 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
9895 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9897 #if defined(OBJ_COFF)
9898 /* If the destination of the branch is a defined symbol which does not have
9899 the THUMB_FUNC attribute, then we must be calling a function which has
9900 the (interfacearm) attribute. We look for the Thumb entry point to that
9901 function and change the branch to refer to that function instead. */
9902 if ( inst
.reloc
.exp
.X_op
== O_symbol
9903 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9904 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9905 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9906 inst
.reloc
.exp
.X_add_symbol
=
9907 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9914 set_it_insn_type_last ();
9915 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9916 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9917 should cause the alignment to be checked once it is known. This is
9918 because BX PC only works if the instruction is word aligned. */
9926 set_it_insn_type_last ();
9927 Rm
= inst
.operands
[0].reg
;
9928 reject_bad_reg (Rm
);
9929 inst
.instruction
|= Rm
<< 16;
9938 Rd
= inst
.operands
[0].reg
;
9939 Rm
= inst
.operands
[1].reg
;
9941 reject_bad_reg (Rd
);
9942 reject_bad_reg (Rm
);
9944 inst
.instruction
|= Rd
<< 8;
9945 inst
.instruction
|= Rm
<< 16;
9946 inst
.instruction
|= Rm
;
9952 set_it_insn_type (OUTSIDE_IT_INSN
);
9953 inst
.instruction
|= inst
.operands
[0].imm
;
9959 set_it_insn_type (OUTSIDE_IT_INSN
);
9961 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9962 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9964 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9965 inst
.instruction
= 0xf3af8000;
9966 inst
.instruction
|= imod
<< 9;
9967 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9968 if (inst
.operands
[1].present
)
9969 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9973 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9974 && (inst
.operands
[0].imm
& 4),
9975 _("selected processor does not support 'A' form "
9976 "of this instruction"));
9977 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9978 _("Thumb does not support the 2-argument "
9979 "form of this instruction"));
9980 inst
.instruction
|= inst
.operands
[0].imm
;
9984 /* THUMB CPY instruction (argument parse). */
9989 if (inst
.size_req
== 4)
9991 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9992 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9993 inst
.instruction
|= inst
.operands
[1].reg
;
9997 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9998 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9999 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10006 set_it_insn_type (OUTSIDE_IT_INSN
);
10007 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10008 inst
.instruction
|= inst
.operands
[0].reg
;
10009 inst
.reloc
.pc_rel
= 1;
10010 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10016 inst
.instruction
|= inst
.operands
[0].imm
;
10022 unsigned Rd
, Rn
, Rm
;
10024 Rd
= inst
.operands
[0].reg
;
10025 Rn
= (inst
.operands
[1].present
10026 ? inst
.operands
[1].reg
: Rd
);
10027 Rm
= inst
.operands
[2].reg
;
10029 reject_bad_reg (Rd
);
10030 reject_bad_reg (Rn
);
10031 reject_bad_reg (Rm
);
10033 inst
.instruction
|= Rd
<< 8;
10034 inst
.instruction
|= Rn
<< 16;
10035 inst
.instruction
|= Rm
;
10041 if (unified_syntax
&& inst
.size_req
== 4)
10042 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10044 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10050 unsigned int cond
= inst
.operands
[0].imm
;
10052 set_it_insn_type (IT_INSN
);
10053 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10056 /* If the condition is a negative condition, invert the mask. */
10057 if ((cond
& 0x1) == 0x0)
10059 unsigned int mask
= inst
.instruction
& 0x000f;
10061 if ((mask
& 0x7) == 0)
10062 /* no conversion needed */;
10063 else if ((mask
& 0x3) == 0)
10065 else if ((mask
& 0x1) == 0)
10070 inst
.instruction
&= 0xfff0;
10071 inst
.instruction
|= mask
;
10074 inst
.instruction
|= cond
<< 4;
10077 /* Helper function used for both push/pop and ldm/stm. */
10079 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10083 load
= (inst
.instruction
& (1 << 20)) != 0;
10085 if (mask
& (1 << 13))
10086 inst
.error
= _("SP not allowed in register list");
10088 if ((mask
& (1 << base
)) != 0
10090 inst
.error
= _("having the base register in the register list when "
10091 "using write back is UNPREDICTABLE");
10095 if (mask
& (1 << 15))
10097 if (mask
& (1 << 14))
10098 inst
.error
= _("LR and PC should not both be in register list");
10100 set_it_insn_type_last ();
10105 if (mask
& (1 << 15))
10106 inst
.error
= _("PC not allowed in register list");
10109 if ((mask
& (mask
- 1)) == 0)
10111 /* Single register transfers implemented as str/ldr. */
10114 if (inst
.instruction
& (1 << 23))
10115 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10117 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10121 if (inst
.instruction
& (1 << 23))
10122 inst
.instruction
= 0x00800000; /* ia -> [base] */
10124 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10127 inst
.instruction
|= 0xf8400000;
10129 inst
.instruction
|= 0x00100000;
10131 mask
= ffs (mask
) - 1;
10134 else if (writeback
)
10135 inst
.instruction
|= WRITE_BACK
;
10137 inst
.instruction
|= mask
;
10138 inst
.instruction
|= base
<< 16;
10144 /* This really doesn't seem worth it. */
10145 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10146 _("expression too complex"));
10147 constraint (inst
.operands
[1].writeback
,
10148 _("Thumb load/store multiple does not support {reglist}^"));
10150 if (unified_syntax
)
10152 bfd_boolean narrow
;
10156 /* See if we can use a 16-bit instruction. */
10157 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10158 && inst
.size_req
!= 4
10159 && !(inst
.operands
[1].imm
& ~0xff))
10161 mask
= 1 << inst
.operands
[0].reg
;
10163 if (inst
.operands
[0].reg
<= 7)
10165 if (inst
.instruction
== T_MNEM_stmia
10166 ? inst
.operands
[0].writeback
10167 : (inst
.operands
[0].writeback
10168 == !(inst
.operands
[1].imm
& mask
)))
10170 if (inst
.instruction
== T_MNEM_stmia
10171 && (inst
.operands
[1].imm
& mask
)
10172 && (inst
.operands
[1].imm
& (mask
- 1)))
10173 as_warn (_("value stored for r%d is UNKNOWN"),
10174 inst
.operands
[0].reg
);
10176 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10177 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10178 inst
.instruction
|= inst
.operands
[1].imm
;
10181 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10183 /* This means 1 register in reg list one of 3 situations:
10184 1. Instruction is stmia, but without writeback.
10185 2. lmdia without writeback, but with Rn not in
10187 3. ldmia with writeback, but with Rn in reglist.
10188 Case 3 is UNPREDICTABLE behaviour, so we handle
10189 case 1 and 2 which can be converted into a 16-bit
10190 str or ldr. The SP cases are handled below. */
10191 unsigned long opcode
;
10192 /* First, record an error for Case 3. */
10193 if (inst
.operands
[1].imm
& mask
10194 && inst
.operands
[0].writeback
)
10196 _("having the base register in the register list when "
10197 "using write back is UNPREDICTABLE");
10199 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10201 inst
.instruction
= THUMB_OP16 (opcode
);
10202 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10203 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10207 else if (inst
.operands
[0] .reg
== REG_SP
)
10209 if (inst
.operands
[0].writeback
)
10212 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10213 ? T_MNEM_push
: T_MNEM_pop
);
10214 inst
.instruction
|= inst
.operands
[1].imm
;
10217 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10220 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10221 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10222 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10230 if (inst
.instruction
< 0xffff)
10231 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10233 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10234 inst
.operands
[0].writeback
);
10239 constraint (inst
.operands
[0].reg
> 7
10240 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10241 constraint (inst
.instruction
!= T_MNEM_ldmia
10242 && inst
.instruction
!= T_MNEM_stmia
,
10243 _("Thumb-2 instruction only valid in unified syntax"));
10244 if (inst
.instruction
== T_MNEM_stmia
)
10246 if (!inst
.operands
[0].writeback
)
10247 as_warn (_("this instruction will write back the base register"));
10248 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10249 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10250 as_warn (_("value stored for r%d is UNKNOWN"),
10251 inst
.operands
[0].reg
);
10255 if (!inst
.operands
[0].writeback
10256 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10257 as_warn (_("this instruction will write back the base register"));
10258 else if (inst
.operands
[0].writeback
10259 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10260 as_warn (_("this instruction will not write back the base register"));
10263 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10264 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10265 inst
.instruction
|= inst
.operands
[1].imm
;
10272 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10273 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10274 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10275 || inst
.operands
[1].negative
,
10278 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10280 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10281 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10282 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10288 if (!inst
.operands
[1].present
)
10290 constraint (inst
.operands
[0].reg
== REG_LR
,
10291 _("r14 not allowed as first register "
10292 "when second register is omitted"));
10293 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10295 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10298 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10299 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10300 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10306 unsigned long opcode
;
10309 if (inst
.operands
[0].isreg
10310 && !inst
.operands
[0].preind
10311 && inst
.operands
[0].reg
== REG_PC
)
10312 set_it_insn_type_last ();
10314 opcode
= inst
.instruction
;
10315 if (unified_syntax
)
10317 if (!inst
.operands
[1].isreg
)
10319 if (opcode
<= 0xffff)
10320 inst
.instruction
= THUMB_OP32 (opcode
);
10321 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10324 if (inst
.operands
[1].isreg
10325 && !inst
.operands
[1].writeback
10326 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10327 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10328 && opcode
<= 0xffff
10329 && inst
.size_req
!= 4)
10331 /* Insn may have a 16-bit form. */
10332 Rn
= inst
.operands
[1].reg
;
10333 if (inst
.operands
[1].immisreg
)
10335 inst
.instruction
= THUMB_OP16 (opcode
);
10337 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10339 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10340 reject_bad_reg (inst
.operands
[1].imm
);
10342 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10343 && opcode
!= T_MNEM_ldrsb
)
10344 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10345 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10352 if (inst
.reloc
.pc_rel
)
10353 opcode
= T_MNEM_ldr_pc2
;
10355 opcode
= T_MNEM_ldr_pc
;
10359 if (opcode
== T_MNEM_ldr
)
10360 opcode
= T_MNEM_ldr_sp
;
10362 opcode
= T_MNEM_str_sp
;
10364 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10368 inst
.instruction
= inst
.operands
[0].reg
;
10369 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10371 inst
.instruction
|= THUMB_OP16 (opcode
);
10372 if (inst
.size_req
== 2)
10373 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10375 inst
.relax
= opcode
;
10379 /* Definitely a 32-bit variant. */
10381 /* Do some validations regarding addressing modes. */
10382 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10383 && opcode
!= T_MNEM_str
)
10384 reject_bad_reg (inst
.operands
[1].imm
);
10386 inst
.instruction
= THUMB_OP32 (opcode
);
10387 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10388 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10392 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10394 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10396 /* Only [Rn,Rm] is acceptable. */
10397 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10398 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10399 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10400 || inst
.operands
[1].negative
,
10401 _("Thumb does not support this addressing mode"));
10402 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10406 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10407 if (!inst
.operands
[1].isreg
)
10408 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10411 constraint (!inst
.operands
[1].preind
10412 || inst
.operands
[1].shifted
10413 || inst
.operands
[1].writeback
,
10414 _("Thumb does not support this addressing mode"));
10415 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10417 constraint (inst
.instruction
& 0x0600,
10418 _("byte or halfword not valid for base register"));
10419 constraint (inst
.operands
[1].reg
== REG_PC
10420 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10421 _("r15 based store not allowed"));
10422 constraint (inst
.operands
[1].immisreg
,
10423 _("invalid base register for register offset"));
10425 if (inst
.operands
[1].reg
== REG_PC
)
10426 inst
.instruction
= T_OPCODE_LDR_PC
;
10427 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10428 inst
.instruction
= T_OPCODE_LDR_SP
;
10430 inst
.instruction
= T_OPCODE_STR_SP
;
10432 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10433 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10437 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10438 if (!inst
.operands
[1].immisreg
)
10440 /* Immediate offset. */
10441 inst
.instruction
|= inst
.operands
[0].reg
;
10442 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10443 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10447 /* Register offset. */
10448 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10449 constraint (inst
.operands
[1].negative
,
10450 _("Thumb does not support this addressing mode"));
10453 switch (inst
.instruction
)
10455 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10456 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10457 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10458 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10459 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10460 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10461 case 0x5600 /* ldrsb */:
10462 case 0x5e00 /* ldrsh */: break;
10466 inst
.instruction
|= inst
.operands
[0].reg
;
10467 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10468 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10474 if (!inst
.operands
[1].present
)
10476 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10477 constraint (inst
.operands
[0].reg
== REG_LR
,
10478 _("r14 not allowed here"));
10480 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10481 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10482 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10488 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10489 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10495 unsigned Rd
, Rn
, Rm
, Ra
;
10497 Rd
= inst
.operands
[0].reg
;
10498 Rn
= inst
.operands
[1].reg
;
10499 Rm
= inst
.operands
[2].reg
;
10500 Ra
= inst
.operands
[3].reg
;
10502 reject_bad_reg (Rd
);
10503 reject_bad_reg (Rn
);
10504 reject_bad_reg (Rm
);
10505 reject_bad_reg (Ra
);
10507 inst
.instruction
|= Rd
<< 8;
10508 inst
.instruction
|= Rn
<< 16;
10509 inst
.instruction
|= Rm
;
10510 inst
.instruction
|= Ra
<< 12;
10516 unsigned RdLo
, RdHi
, Rn
, Rm
;
10518 RdLo
= inst
.operands
[0].reg
;
10519 RdHi
= inst
.operands
[1].reg
;
10520 Rn
= inst
.operands
[2].reg
;
10521 Rm
= inst
.operands
[3].reg
;
10523 reject_bad_reg (RdLo
);
10524 reject_bad_reg (RdHi
);
10525 reject_bad_reg (Rn
);
10526 reject_bad_reg (Rm
);
10528 inst
.instruction
|= RdLo
<< 12;
10529 inst
.instruction
|= RdHi
<< 8;
10530 inst
.instruction
|= Rn
<< 16;
10531 inst
.instruction
|= Rm
;
10535 do_t_mov_cmp (void)
10539 Rn
= inst
.operands
[0].reg
;
10540 Rm
= inst
.operands
[1].reg
;
10543 set_it_insn_type_last ();
10545 if (unified_syntax
)
10547 int r0off
= (inst
.instruction
== T_MNEM_mov
10548 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10549 unsigned long opcode
;
10550 bfd_boolean narrow
;
10551 bfd_boolean low_regs
;
10553 low_regs
= (Rn
<= 7 && Rm
<= 7);
10554 opcode
= inst
.instruction
;
10555 if (in_it_block ())
10556 narrow
= opcode
!= T_MNEM_movs
;
10558 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10559 if (inst
.size_req
== 4
10560 || inst
.operands
[1].shifted
)
10563 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10564 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10565 && !inst
.operands
[1].shifted
10569 inst
.instruction
= T2_SUBS_PC_LR
;
10573 if (opcode
== T_MNEM_cmp
)
10575 constraint (Rn
== REG_PC
, BAD_PC
);
10578 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10580 warn_deprecated_sp (Rm
);
10581 /* R15 was documented as a valid choice for Rm in ARMv6,
10582 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10583 tools reject R15, so we do too. */
10584 constraint (Rm
== REG_PC
, BAD_PC
);
10587 reject_bad_reg (Rm
);
10589 else if (opcode
== T_MNEM_mov
10590 || opcode
== T_MNEM_movs
)
10592 if (inst
.operands
[1].isreg
)
10594 if (opcode
== T_MNEM_movs
)
10596 reject_bad_reg (Rn
);
10597 reject_bad_reg (Rm
);
10601 /* This is mov.n. */
10602 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10603 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10605 as_warn (_("Use of r%u as a source register is "
10606 "deprecated when r%u is the destination "
10607 "register."), Rm
, Rn
);
10612 /* This is mov.w. */
10613 constraint (Rn
== REG_PC
, BAD_PC
);
10614 constraint (Rm
== REG_PC
, BAD_PC
);
10615 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10619 reject_bad_reg (Rn
);
10622 if (!inst
.operands
[1].isreg
)
10624 /* Immediate operand. */
10625 if (!in_it_block () && opcode
== T_MNEM_mov
)
10627 if (low_regs
&& narrow
)
10629 inst
.instruction
= THUMB_OP16 (opcode
);
10630 inst
.instruction
|= Rn
<< 8;
10631 if (inst
.size_req
== 2)
10632 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10634 inst
.relax
= opcode
;
10638 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10639 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10640 inst
.instruction
|= Rn
<< r0off
;
10641 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10644 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10645 && (inst
.instruction
== T_MNEM_mov
10646 || inst
.instruction
== T_MNEM_movs
))
10648 /* Register shifts are encoded as separate shift instructions. */
10649 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10651 if (in_it_block ())
10656 if (inst
.size_req
== 4)
10659 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10665 switch (inst
.operands
[1].shift_kind
)
10668 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10671 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10674 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10677 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10683 inst
.instruction
= opcode
;
10686 inst
.instruction
|= Rn
;
10687 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10692 inst
.instruction
|= CONDS_BIT
;
10694 inst
.instruction
|= Rn
<< 8;
10695 inst
.instruction
|= Rm
<< 16;
10696 inst
.instruction
|= inst
.operands
[1].imm
;
10701 /* Some mov with immediate shift have narrow variants.
10702 Register shifts are handled above. */
10703 if (low_regs
&& inst
.operands
[1].shifted
10704 && (inst
.instruction
== T_MNEM_mov
10705 || inst
.instruction
== T_MNEM_movs
))
10707 if (in_it_block ())
10708 narrow
= (inst
.instruction
== T_MNEM_mov
);
10710 narrow
= (inst
.instruction
== T_MNEM_movs
);
10715 switch (inst
.operands
[1].shift_kind
)
10717 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10718 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10719 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10720 default: narrow
= FALSE
; break;
10726 inst
.instruction
|= Rn
;
10727 inst
.instruction
|= Rm
<< 3;
10728 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10732 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10733 inst
.instruction
|= Rn
<< r0off
;
10734 encode_thumb32_shifted_operand (1);
10738 switch (inst
.instruction
)
10741 inst
.instruction
= T_OPCODE_MOV_HR
;
10742 inst
.instruction
|= (Rn
& 0x8) << 4;
10743 inst
.instruction
|= (Rn
& 0x7);
10744 inst
.instruction
|= Rm
<< 3;
10748 /* We know we have low registers at this point.
10749 Generate LSLS Rd, Rs, #0. */
10750 inst
.instruction
= T_OPCODE_LSL_I
;
10751 inst
.instruction
|= Rn
;
10752 inst
.instruction
|= Rm
<< 3;
10758 inst
.instruction
= T_OPCODE_CMP_LR
;
10759 inst
.instruction
|= Rn
;
10760 inst
.instruction
|= Rm
<< 3;
10764 inst
.instruction
= T_OPCODE_CMP_HR
;
10765 inst
.instruction
|= (Rn
& 0x8) << 4;
10766 inst
.instruction
|= (Rn
& 0x7);
10767 inst
.instruction
|= Rm
<< 3;
10774 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10776 /* PR 10443: Do not silently ignore shifted operands. */
10777 constraint (inst
.operands
[1].shifted
,
10778 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10780 if (inst
.operands
[1].isreg
)
10782 if (Rn
< 8 && Rm
< 8)
10784 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10785 since a MOV instruction produces unpredictable results. */
10786 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10787 inst
.instruction
= T_OPCODE_ADD_I3
;
10789 inst
.instruction
= T_OPCODE_CMP_LR
;
10791 inst
.instruction
|= Rn
;
10792 inst
.instruction
|= Rm
<< 3;
10796 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10797 inst
.instruction
= T_OPCODE_MOV_HR
;
10799 inst
.instruction
= T_OPCODE_CMP_HR
;
10805 constraint (Rn
> 7,
10806 _("only lo regs allowed with immediate"));
10807 inst
.instruction
|= Rn
<< 8;
10808 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10819 top
= (inst
.instruction
& 0x00800000) != 0;
10820 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10822 constraint (top
, _(":lower16: not allowed this instruction"));
10823 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10825 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10827 constraint (!top
, _(":upper16: not allowed this instruction"));
10828 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10831 Rd
= inst
.operands
[0].reg
;
10832 reject_bad_reg (Rd
);
10834 inst
.instruction
|= Rd
<< 8;
10835 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10837 imm
= inst
.reloc
.exp
.X_add_number
;
10838 inst
.instruction
|= (imm
& 0xf000) << 4;
10839 inst
.instruction
|= (imm
& 0x0800) << 15;
10840 inst
.instruction
|= (imm
& 0x0700) << 4;
10841 inst
.instruction
|= (imm
& 0x00ff);
10846 do_t_mvn_tst (void)
10850 Rn
= inst
.operands
[0].reg
;
10851 Rm
= inst
.operands
[1].reg
;
10853 if (inst
.instruction
== T_MNEM_cmp
10854 || inst
.instruction
== T_MNEM_cmn
)
10855 constraint (Rn
== REG_PC
, BAD_PC
);
10857 reject_bad_reg (Rn
);
10858 reject_bad_reg (Rm
);
10860 if (unified_syntax
)
10862 int r0off
= (inst
.instruction
== T_MNEM_mvn
10863 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10864 bfd_boolean narrow
;
10866 if (inst
.size_req
== 4
10867 || inst
.instruction
> 0xffff
10868 || inst
.operands
[1].shifted
10869 || Rn
> 7 || Rm
> 7)
10871 else if (inst
.instruction
== T_MNEM_cmn
)
10873 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10874 narrow
= !in_it_block ();
10876 narrow
= in_it_block ();
10878 if (!inst
.operands
[1].isreg
)
10880 /* For an immediate, we always generate a 32-bit opcode;
10881 section relaxation will shrink it later if possible. */
10882 if (inst
.instruction
< 0xffff)
10883 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10884 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10885 inst
.instruction
|= Rn
<< r0off
;
10886 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10890 /* See if we can do this with a 16-bit instruction. */
10893 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10894 inst
.instruction
|= Rn
;
10895 inst
.instruction
|= Rm
<< 3;
10899 constraint (inst
.operands
[1].shifted
10900 && inst
.operands
[1].immisreg
,
10901 _("shift must be constant"));
10902 if (inst
.instruction
< 0xffff)
10903 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10904 inst
.instruction
|= Rn
<< r0off
;
10905 encode_thumb32_shifted_operand (1);
10911 constraint (inst
.instruction
> 0xffff
10912 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10913 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10914 _("unshifted register required"));
10915 constraint (Rn
> 7 || Rm
> 7,
10918 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10919 inst
.instruction
|= Rn
;
10920 inst
.instruction
|= Rm
<< 3;
10929 if (do_vfp_nsyn_mrs () == SUCCESS
)
10932 Rd
= inst
.operands
[0].reg
;
10933 reject_bad_reg (Rd
);
10934 inst
.instruction
|= Rd
<< 8;
10936 if (inst
.operands
[1].isreg
)
10938 unsigned br
= inst
.operands
[1].reg
;
10939 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
10940 as_bad (_("bad register for mrs"));
10942 inst
.instruction
|= br
& (0xf << 16);
10943 inst
.instruction
|= (br
& 0x300) >> 4;
10944 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
10948 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10950 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
10951 constraint (flags
!= 0, _("selected processor does not support "
10952 "requested special purpose register"));
10954 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
10956 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10957 _("'APSR', 'CPSR' or 'SPSR' expected"));
10959 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10960 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10961 inst
.instruction
|= 0xf0000;
10971 if (do_vfp_nsyn_msr () == SUCCESS
)
10974 constraint (!inst
.operands
[1].isreg
,
10975 _("Thumb encoding does not support an immediate here"));
10977 if (inst
.operands
[0].isreg
)
10978 flags
= (int)(inst
.operands
[0].reg
);
10980 flags
= inst
.operands
[0].imm
;
10982 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
10984 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10986 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
10987 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
10988 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
10990 _("selected processor does not support requested special "
10991 "purpose register"));
10994 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
10995 "requested special purpose register"));
10997 Rn
= inst
.operands
[1].reg
;
10998 reject_bad_reg (Rn
);
11000 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11001 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11002 inst
.instruction
|= (flags
& 0x300) >> 4;
11003 inst
.instruction
|= (flags
& 0xff);
11004 inst
.instruction
|= Rn
<< 16;
11010 bfd_boolean narrow
;
11011 unsigned Rd
, Rn
, Rm
;
11013 if (!inst
.operands
[2].present
)
11014 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11016 Rd
= inst
.operands
[0].reg
;
11017 Rn
= inst
.operands
[1].reg
;
11018 Rm
= inst
.operands
[2].reg
;
11020 if (unified_syntax
)
11022 if (inst
.size_req
== 4
11028 else if (inst
.instruction
== T_MNEM_muls
)
11029 narrow
= !in_it_block ();
11031 narrow
= in_it_block ();
11035 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11036 constraint (Rn
> 7 || Rm
> 7,
11043 /* 16-bit MULS/Conditional MUL. */
11044 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11045 inst
.instruction
|= Rd
;
11048 inst
.instruction
|= Rm
<< 3;
11050 inst
.instruction
|= Rn
<< 3;
11052 constraint (1, _("dest must overlap one source register"));
11056 constraint (inst
.instruction
!= T_MNEM_mul
,
11057 _("Thumb-2 MUL must not set flags"));
11059 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11060 inst
.instruction
|= Rd
<< 8;
11061 inst
.instruction
|= Rn
<< 16;
11062 inst
.instruction
|= Rm
<< 0;
11064 reject_bad_reg (Rd
);
11065 reject_bad_reg (Rn
);
11066 reject_bad_reg (Rm
);
11073 unsigned RdLo
, RdHi
, Rn
, Rm
;
11075 RdLo
= inst
.operands
[0].reg
;
11076 RdHi
= inst
.operands
[1].reg
;
11077 Rn
= inst
.operands
[2].reg
;
11078 Rm
= inst
.operands
[3].reg
;
11080 reject_bad_reg (RdLo
);
11081 reject_bad_reg (RdHi
);
11082 reject_bad_reg (Rn
);
11083 reject_bad_reg (Rm
);
11085 inst
.instruction
|= RdLo
<< 12;
11086 inst
.instruction
|= RdHi
<< 8;
11087 inst
.instruction
|= Rn
<< 16;
11088 inst
.instruction
|= Rm
;
11091 as_tsktsk (_("rdhi and rdlo must be different"));
11097 set_it_insn_type (NEUTRAL_IT_INSN
);
11099 if (unified_syntax
)
11101 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11103 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11104 inst
.instruction
|= inst
.operands
[0].imm
;
11108 /* PR9722: Check for Thumb2 availability before
11109 generating a thumb2 nop instruction. */
11110 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11112 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11113 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11116 inst
.instruction
= 0x46c0;
11121 constraint (inst
.operands
[0].present
,
11122 _("Thumb does not support NOP with hints"));
11123 inst
.instruction
= 0x46c0;
11130 if (unified_syntax
)
11132 bfd_boolean narrow
;
11134 if (THUMB_SETS_FLAGS (inst
.instruction
))
11135 narrow
= !in_it_block ();
11137 narrow
= in_it_block ();
11138 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11140 if (inst
.size_req
== 4)
11145 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11146 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11147 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11151 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11152 inst
.instruction
|= inst
.operands
[0].reg
;
11153 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11158 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11160 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11162 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11163 inst
.instruction
|= inst
.operands
[0].reg
;
11164 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11173 Rd
= inst
.operands
[0].reg
;
11174 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11176 reject_bad_reg (Rd
);
11177 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11178 reject_bad_reg (Rn
);
11180 inst
.instruction
|= Rd
<< 8;
11181 inst
.instruction
|= Rn
<< 16;
11183 if (!inst
.operands
[2].isreg
)
11185 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11186 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11192 Rm
= inst
.operands
[2].reg
;
11193 reject_bad_reg (Rm
);
11195 constraint (inst
.operands
[2].shifted
11196 && inst
.operands
[2].immisreg
,
11197 _("shift must be constant"));
11198 encode_thumb32_shifted_operand (2);
11205 unsigned Rd
, Rn
, Rm
;
11207 Rd
= inst
.operands
[0].reg
;
11208 Rn
= inst
.operands
[1].reg
;
11209 Rm
= inst
.operands
[2].reg
;
11211 reject_bad_reg (Rd
);
11212 reject_bad_reg (Rn
);
11213 reject_bad_reg (Rm
);
11215 inst
.instruction
|= Rd
<< 8;
11216 inst
.instruction
|= Rn
<< 16;
11217 inst
.instruction
|= Rm
;
11218 if (inst
.operands
[3].present
)
11220 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11221 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11222 _("expression too complex"));
11223 inst
.instruction
|= (val
& 0x1c) << 10;
11224 inst
.instruction
|= (val
& 0x03) << 6;
11231 if (!inst
.operands
[3].present
)
11235 inst
.instruction
&= ~0x00000020;
11237 /* PR 10168. Swap the Rm and Rn registers. */
11238 Rtmp
= inst
.operands
[1].reg
;
11239 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11240 inst
.operands
[2].reg
= Rtmp
;
11248 if (inst
.operands
[0].immisreg
)
11249 reject_bad_reg (inst
.operands
[0].imm
);
11251 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11255 do_t_push_pop (void)
11259 constraint (inst
.operands
[0].writeback
,
11260 _("push/pop do not support {reglist}^"));
11261 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11262 _("expression too complex"));
11264 mask
= inst
.operands
[0].imm
;
11265 if ((mask
& ~0xff) == 0)
11266 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11267 else if ((inst
.instruction
== T_MNEM_push
11268 && (mask
& ~0xff) == 1 << REG_LR
)
11269 || (inst
.instruction
== T_MNEM_pop
11270 && (mask
& ~0xff) == 1 << REG_PC
))
11272 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11273 inst
.instruction
|= THUMB_PP_PC_LR
;
11274 inst
.instruction
|= mask
& 0xff;
11276 else if (unified_syntax
)
11278 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11279 encode_thumb2_ldmstm (13, mask
, TRUE
);
11283 inst
.error
= _("invalid register list to push/pop instruction");
11293 Rd
= inst
.operands
[0].reg
;
11294 Rm
= inst
.operands
[1].reg
;
11296 reject_bad_reg (Rd
);
11297 reject_bad_reg (Rm
);
11299 inst
.instruction
|= Rd
<< 8;
11300 inst
.instruction
|= Rm
<< 16;
11301 inst
.instruction
|= Rm
;
11309 Rd
= inst
.operands
[0].reg
;
11310 Rm
= inst
.operands
[1].reg
;
11312 reject_bad_reg (Rd
);
11313 reject_bad_reg (Rm
);
11315 if (Rd
<= 7 && Rm
<= 7
11316 && inst
.size_req
!= 4)
11318 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11319 inst
.instruction
|= Rd
;
11320 inst
.instruction
|= Rm
<< 3;
11322 else if (unified_syntax
)
11324 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11325 inst
.instruction
|= Rd
<< 8;
11326 inst
.instruction
|= Rm
<< 16;
11327 inst
.instruction
|= Rm
;
11330 inst
.error
= BAD_HIREG
;
11338 Rd
= inst
.operands
[0].reg
;
11339 Rm
= inst
.operands
[1].reg
;
11341 reject_bad_reg (Rd
);
11342 reject_bad_reg (Rm
);
11344 inst
.instruction
|= Rd
<< 8;
11345 inst
.instruction
|= Rm
;
11353 Rd
= inst
.operands
[0].reg
;
11354 Rs
= (inst
.operands
[1].present
11355 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11356 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11358 reject_bad_reg (Rd
);
11359 reject_bad_reg (Rs
);
11360 if (inst
.operands
[2].isreg
)
11361 reject_bad_reg (inst
.operands
[2].reg
);
11363 inst
.instruction
|= Rd
<< 8;
11364 inst
.instruction
|= Rs
<< 16;
11365 if (!inst
.operands
[2].isreg
)
11367 bfd_boolean narrow
;
11369 if ((inst
.instruction
& 0x00100000) != 0)
11370 narrow
= !in_it_block ();
11372 narrow
= in_it_block ();
11374 if (Rd
> 7 || Rs
> 7)
11377 if (inst
.size_req
== 4 || !unified_syntax
)
11380 if (inst
.reloc
.exp
.X_op
!= O_constant
11381 || inst
.reloc
.exp
.X_add_number
!= 0)
11384 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11385 relaxation, but it doesn't seem worth the hassle. */
11388 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11389 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11390 inst
.instruction
|= Rs
<< 3;
11391 inst
.instruction
|= Rd
;
11395 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11396 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11400 encode_thumb32_shifted_operand (2);
11406 set_it_insn_type (OUTSIDE_IT_INSN
);
11407 if (inst
.operands
[0].imm
)
11408 inst
.instruction
|= 0x8;
11414 if (!inst
.operands
[1].present
)
11415 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11417 if (unified_syntax
)
11419 bfd_boolean narrow
;
11422 switch (inst
.instruction
)
11425 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11427 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11429 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11431 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11435 if (THUMB_SETS_FLAGS (inst
.instruction
))
11436 narrow
= !in_it_block ();
11438 narrow
= in_it_block ();
11439 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11441 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11443 if (inst
.operands
[2].isreg
11444 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11445 || inst
.operands
[2].reg
> 7))
11447 if (inst
.size_req
== 4)
11450 reject_bad_reg (inst
.operands
[0].reg
);
11451 reject_bad_reg (inst
.operands
[1].reg
);
11455 if (inst
.operands
[2].isreg
)
11457 reject_bad_reg (inst
.operands
[2].reg
);
11458 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11459 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11460 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11461 inst
.instruction
|= inst
.operands
[2].reg
;
11465 inst
.operands
[1].shifted
= 1;
11466 inst
.operands
[1].shift_kind
= shift_kind
;
11467 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11468 ? T_MNEM_movs
: T_MNEM_mov
);
11469 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11470 encode_thumb32_shifted_operand (1);
11471 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11472 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11477 if (inst
.operands
[2].isreg
)
11479 switch (shift_kind
)
11481 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11482 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11483 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11484 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11488 inst
.instruction
|= inst
.operands
[0].reg
;
11489 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11493 switch (shift_kind
)
11495 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11496 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11497 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11500 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11501 inst
.instruction
|= inst
.operands
[0].reg
;
11502 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11508 constraint (inst
.operands
[0].reg
> 7
11509 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11510 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11512 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11514 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11515 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11516 _("source1 and dest must be same register"));
11518 switch (inst
.instruction
)
11520 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11521 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11522 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11523 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11527 inst
.instruction
|= inst
.operands
[0].reg
;
11528 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11532 switch (inst
.instruction
)
11534 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11535 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11536 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11537 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11540 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11541 inst
.instruction
|= inst
.operands
[0].reg
;
11542 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11550 unsigned Rd
, Rn
, Rm
;
11552 Rd
= inst
.operands
[0].reg
;
11553 Rn
= inst
.operands
[1].reg
;
11554 Rm
= inst
.operands
[2].reg
;
11556 reject_bad_reg (Rd
);
11557 reject_bad_reg (Rn
);
11558 reject_bad_reg (Rm
);
11560 inst
.instruction
|= Rd
<< 8;
11561 inst
.instruction
|= Rn
<< 16;
11562 inst
.instruction
|= Rm
;
11568 unsigned Rd
, Rn
, Rm
;
11570 Rd
= inst
.operands
[0].reg
;
11571 Rm
= inst
.operands
[1].reg
;
11572 Rn
= inst
.operands
[2].reg
;
11574 reject_bad_reg (Rd
);
11575 reject_bad_reg (Rn
);
11576 reject_bad_reg (Rm
);
11578 inst
.instruction
|= Rd
<< 8;
11579 inst
.instruction
|= Rn
<< 16;
11580 inst
.instruction
|= Rm
;
11586 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11587 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11588 _("SMC is not permitted on this architecture"));
11589 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11590 _("expression too complex"));
11591 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11592 inst
.instruction
|= (value
& 0xf000) >> 12;
11593 inst
.instruction
|= (value
& 0x0ff0);
11594 inst
.instruction
|= (value
& 0x000f) << 16;
11600 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11602 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11603 inst
.instruction
|= (value
& 0x0fff);
11604 inst
.instruction
|= (value
& 0xf000) << 4;
11608 do_t_ssat_usat (int bias
)
11612 Rd
= inst
.operands
[0].reg
;
11613 Rn
= inst
.operands
[2].reg
;
11615 reject_bad_reg (Rd
);
11616 reject_bad_reg (Rn
);
11618 inst
.instruction
|= Rd
<< 8;
11619 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11620 inst
.instruction
|= Rn
<< 16;
11622 if (inst
.operands
[3].present
)
11624 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11626 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11628 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11629 _("expression too complex"));
11631 if (shift_amount
!= 0)
11633 constraint (shift_amount
> 31,
11634 _("shift expression is too large"));
11636 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11637 inst
.instruction
|= 0x00200000; /* sh bit. */
11639 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11640 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11648 do_t_ssat_usat (1);
11656 Rd
= inst
.operands
[0].reg
;
11657 Rn
= inst
.operands
[2].reg
;
11659 reject_bad_reg (Rd
);
11660 reject_bad_reg (Rn
);
11662 inst
.instruction
|= Rd
<< 8;
11663 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11664 inst
.instruction
|= Rn
<< 16;
11670 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11671 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11672 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11673 || inst
.operands
[2].negative
,
11676 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11678 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11679 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11680 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11681 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11687 if (!inst
.operands
[2].present
)
11688 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11690 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11691 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11692 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11695 inst
.instruction
|= inst
.operands
[0].reg
;
11696 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11697 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11698 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11704 unsigned Rd
, Rn
, Rm
;
11706 Rd
= inst
.operands
[0].reg
;
11707 Rn
= inst
.operands
[1].reg
;
11708 Rm
= inst
.operands
[2].reg
;
11710 reject_bad_reg (Rd
);
11711 reject_bad_reg (Rn
);
11712 reject_bad_reg (Rm
);
11714 inst
.instruction
|= Rd
<< 8;
11715 inst
.instruction
|= Rn
<< 16;
11716 inst
.instruction
|= Rm
;
11717 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11725 Rd
= inst
.operands
[0].reg
;
11726 Rm
= inst
.operands
[1].reg
;
11728 reject_bad_reg (Rd
);
11729 reject_bad_reg (Rm
);
11731 if (inst
.instruction
<= 0xffff
11732 && inst
.size_req
!= 4
11733 && Rd
<= 7 && Rm
<= 7
11734 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11736 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11737 inst
.instruction
|= Rd
;
11738 inst
.instruction
|= Rm
<< 3;
11740 else if (unified_syntax
)
11742 if (inst
.instruction
<= 0xffff)
11743 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11744 inst
.instruction
|= Rd
<< 8;
11745 inst
.instruction
|= Rm
;
11746 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11750 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11751 _("Thumb encoding does not support rotation"));
11752 constraint (1, BAD_HIREG
);
11759 /* We have to do the following check manually as ARM_EXT_OS only applies
11761 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11763 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
))
11764 as_bad (_("SVC is not permitted on this architecture"));
11765 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11768 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11777 half
= (inst
.instruction
& 0x10) != 0;
11778 set_it_insn_type_last ();
11779 constraint (inst
.operands
[0].immisreg
,
11780 _("instruction requires register index"));
11782 Rn
= inst
.operands
[0].reg
;
11783 Rm
= inst
.operands
[0].imm
;
11785 constraint (Rn
== REG_SP
, BAD_SP
);
11786 reject_bad_reg (Rm
);
11788 constraint (!half
&& inst
.operands
[0].shifted
,
11789 _("instruction does not allow shifted index"));
11790 inst
.instruction
|= (Rn
<< 16) | Rm
;
11796 do_t_ssat_usat (0);
11804 Rd
= inst
.operands
[0].reg
;
11805 Rn
= inst
.operands
[2].reg
;
11807 reject_bad_reg (Rd
);
11808 reject_bad_reg (Rn
);
11810 inst
.instruction
|= Rd
<< 8;
11811 inst
.instruction
|= inst
.operands
[1].imm
;
11812 inst
.instruction
|= Rn
<< 16;
11815 /* Neon instruction encoder helpers. */
11817 /* Encodings for the different types for various Neon opcodes. */
11819 /* An "invalid" code for the following tables. */
11822 struct neon_tab_entry
11825 unsigned float_or_poly
;
11826 unsigned scalar_or_imm
;
11829 /* Map overloaded Neon opcodes to their respective encodings. */
11830 #define NEON_ENC_TAB \
11831 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11832 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11833 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11834 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11835 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11836 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11837 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11838 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11839 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11840 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11841 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11842 /* Register variants of the following two instructions are encoded as
11843 vcge / vcgt with the operands reversed. */ \
11844 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11845 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11846 X(vfma, N_INV, 0x0000c10, N_INV), \
11847 X(vfms, N_INV, 0x0200c10, N_INV), \
11848 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11849 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11850 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11851 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11852 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11853 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11854 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11855 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11856 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11857 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11858 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11859 X(vshl, 0x0000400, N_INV, 0x0800510), \
11860 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11861 X(vand, 0x0000110, N_INV, 0x0800030), \
11862 X(vbic, 0x0100110, N_INV, 0x0800030), \
11863 X(veor, 0x1000110, N_INV, N_INV), \
11864 X(vorn, 0x0300110, N_INV, 0x0800010), \
11865 X(vorr, 0x0200110, N_INV, 0x0800010), \
11866 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11867 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11868 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11869 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11870 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11871 X(vst1, 0x0000000, 0x0800000, N_INV), \
11872 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11873 X(vst2, 0x0000100, 0x0800100, N_INV), \
11874 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11875 X(vst3, 0x0000200, 0x0800200, N_INV), \
11876 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11877 X(vst4, 0x0000300, 0x0800300, N_INV), \
11878 X(vmovn, 0x1b20200, N_INV, N_INV), \
11879 X(vtrn, 0x1b20080, N_INV, N_INV), \
11880 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11881 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11882 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11883 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11884 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11885 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11886 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11887 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11888 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11889 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11890 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11894 #define X(OPC,I,F,S) N_MNEM_##OPC
11899 static const struct neon_tab_entry neon_enc_tab
[] =
11901 #define X(OPC,I,F,S) { (I), (F), (S) }
11906 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11907 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11908 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11909 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11910 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11911 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11912 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11913 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11914 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11915 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11916 #define NEON_ENC_SINGLE_(X) \
11917 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11918 #define NEON_ENC_DOUBLE_(X) \
11919 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11921 #define NEON_ENCODE(type, inst) \
11924 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11925 inst.is_neon = 1; \
11929 #define check_neon_suffixes \
11932 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11934 as_bad (_("invalid neon suffix for non neon instruction")); \
11940 /* Define shapes for instruction operands. The following mnemonic characters
11941 are used in this table:
11943 F - VFP S<n> register
11944 D - Neon D<n> register
11945 Q - Neon Q<n> register
11949 L - D<n> register list
11951 This table is used to generate various data:
11952 - enumerations of the form NS_DDR to be used as arguments to
11954 - a table classifying shapes into single, double, quad, mixed.
11955 - a table used to drive neon_select_shape. */
11957 #define NEON_SHAPE_DEF \
11958 X(3, (D, D, D), DOUBLE), \
11959 X(3, (Q, Q, Q), QUAD), \
11960 X(3, (D, D, I), DOUBLE), \
11961 X(3, (Q, Q, I), QUAD), \
11962 X(3, (D, D, S), DOUBLE), \
11963 X(3, (Q, Q, S), QUAD), \
11964 X(2, (D, D), DOUBLE), \
11965 X(2, (Q, Q), QUAD), \
11966 X(2, (D, S), DOUBLE), \
11967 X(2, (Q, S), QUAD), \
11968 X(2, (D, R), DOUBLE), \
11969 X(2, (Q, R), QUAD), \
11970 X(2, (D, I), DOUBLE), \
11971 X(2, (Q, I), QUAD), \
11972 X(3, (D, L, D), DOUBLE), \
11973 X(2, (D, Q), MIXED), \
11974 X(2, (Q, D), MIXED), \
11975 X(3, (D, Q, I), MIXED), \
11976 X(3, (Q, D, I), MIXED), \
11977 X(3, (Q, D, D), MIXED), \
11978 X(3, (D, Q, Q), MIXED), \
11979 X(3, (Q, Q, D), MIXED), \
11980 X(3, (Q, D, S), MIXED), \
11981 X(3, (D, Q, S), MIXED), \
11982 X(4, (D, D, D, I), DOUBLE), \
11983 X(4, (Q, Q, Q, I), QUAD), \
11984 X(2, (F, F), SINGLE), \
11985 X(3, (F, F, F), SINGLE), \
11986 X(2, (F, I), SINGLE), \
11987 X(2, (F, D), MIXED), \
11988 X(2, (D, F), MIXED), \
11989 X(3, (F, F, I), MIXED), \
11990 X(4, (R, R, F, F), SINGLE), \
11991 X(4, (F, F, R, R), SINGLE), \
11992 X(3, (D, R, R), DOUBLE), \
11993 X(3, (R, R, D), DOUBLE), \
11994 X(2, (S, R), SINGLE), \
11995 X(2, (R, S), SINGLE), \
11996 X(2, (F, R), SINGLE), \
11997 X(2, (R, F), SINGLE)
11999 #define S2(A,B) NS_##A##B
12000 #define S3(A,B,C) NS_##A##B##C
12001 #define S4(A,B,C,D) NS_##A##B##C##D
12003 #define X(N, L, C) S##N L
12016 enum neon_shape_class
12024 #define X(N, L, C) SC_##C
12026 static enum neon_shape_class neon_shape_class
[] =
12044 /* Register widths of above. */
12045 static unsigned neon_shape_el_size
[] =
12056 struct neon_shape_info
12059 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12062 #define S2(A,B) { SE_##A, SE_##B }
12063 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12064 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12066 #define X(N, L, C) { N, S##N L }
12068 static struct neon_shape_info neon_shape_tab
[] =
12078 /* Bit masks used in type checking given instructions.
12079 'N_EQK' means the type must be the same as (or based on in some way) the key
12080 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12081 set, various other bits can be set as well in order to modify the meaning of
12082 the type constraint. */
12084 enum neon_type_mask
12107 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12108 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12109 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12110 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12111 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12112 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12113 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12114 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12115 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12116 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12118 N_MAX_NONSPECIAL
= N_F64
12121 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12123 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12124 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12125 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12126 #define N_SUF_32 (N_SU_32 | N_F32)
12127 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12128 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12130 /* Pass this as the first type argument to neon_check_type to ignore types
12132 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12134 /* Select a "shape" for the current instruction (describing register types or
12135 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12136 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12137 function of operand parsing, so this function doesn't need to be called.
12138 Shapes should be listed in order of decreasing length. */
12140 static enum neon_shape
12141 neon_select_shape (enum neon_shape shape
, ...)
12144 enum neon_shape first_shape
= shape
;
12146 /* Fix missing optional operands. FIXME: we don't know at this point how
12147 many arguments we should have, so this makes the assumption that we have
12148 > 1. This is true of all current Neon opcodes, I think, but may not be
12149 true in the future. */
12150 if (!inst
.operands
[1].present
)
12151 inst
.operands
[1] = inst
.operands
[0];
12153 va_start (ap
, shape
);
12155 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12160 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12162 if (!inst
.operands
[j
].present
)
12168 switch (neon_shape_tab
[shape
].el
[j
])
12171 if (!(inst
.operands
[j
].isreg
12172 && inst
.operands
[j
].isvec
12173 && inst
.operands
[j
].issingle
12174 && !inst
.operands
[j
].isquad
))
12179 if (!(inst
.operands
[j
].isreg
12180 && inst
.operands
[j
].isvec
12181 && !inst
.operands
[j
].isquad
12182 && !inst
.operands
[j
].issingle
))
12187 if (!(inst
.operands
[j
].isreg
12188 && !inst
.operands
[j
].isvec
))
12193 if (!(inst
.operands
[j
].isreg
12194 && inst
.operands
[j
].isvec
12195 && inst
.operands
[j
].isquad
12196 && !inst
.operands
[j
].issingle
))
12201 if (!(!inst
.operands
[j
].isreg
12202 && !inst
.operands
[j
].isscalar
))
12207 if (!(!inst
.operands
[j
].isreg
12208 && inst
.operands
[j
].isscalar
))
12224 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12225 first_error (_("invalid instruction shape"));
12230 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12231 means the Q bit should be set). */
12234 neon_quad (enum neon_shape shape
)
12236 return neon_shape_class
[shape
] == SC_QUAD
;
12240 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12243 /* Allow modification to be made to types which are constrained to be
12244 based on the key element, based on bits set alongside N_EQK. */
12245 if ((typebits
& N_EQK
) != 0)
12247 if ((typebits
& N_HLF
) != 0)
12249 else if ((typebits
& N_DBL
) != 0)
12251 if ((typebits
& N_SGN
) != 0)
12252 *g_type
= NT_signed
;
12253 else if ((typebits
& N_UNS
) != 0)
12254 *g_type
= NT_unsigned
;
12255 else if ((typebits
& N_INT
) != 0)
12256 *g_type
= NT_integer
;
12257 else if ((typebits
& N_FLT
) != 0)
12258 *g_type
= NT_float
;
12259 else if ((typebits
& N_SIZ
) != 0)
12260 *g_type
= NT_untyped
;
12264 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12265 operand type, i.e. the single type specified in a Neon instruction when it
12266 is the only one given. */
12268 static struct neon_type_el
12269 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12271 struct neon_type_el dest
= *key
;
12273 gas_assert ((thisarg
& N_EQK
) != 0);
12275 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12280 /* Convert Neon type and size into compact bitmask representation. */
12282 static enum neon_type_mask
12283 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12290 case 8: return N_8
;
12291 case 16: return N_16
;
12292 case 32: return N_32
;
12293 case 64: return N_64
;
12301 case 8: return N_I8
;
12302 case 16: return N_I16
;
12303 case 32: return N_I32
;
12304 case 64: return N_I64
;
12312 case 16: return N_F16
;
12313 case 32: return N_F32
;
12314 case 64: return N_F64
;
12322 case 8: return N_P8
;
12323 case 16: return N_P16
;
12331 case 8: return N_S8
;
12332 case 16: return N_S16
;
12333 case 32: return N_S32
;
12334 case 64: return N_S64
;
12342 case 8: return N_U8
;
12343 case 16: return N_U16
;
12344 case 32: return N_U32
;
12345 case 64: return N_U64
;
12356 /* Convert compact Neon bitmask type representation to a type and size. Only
12357 handles the case where a single bit is set in the mask. */
12360 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12361 enum neon_type_mask mask
)
12363 if ((mask
& N_EQK
) != 0)
12366 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12368 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12370 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12372 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12377 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12379 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12380 *type
= NT_unsigned
;
12381 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12382 *type
= NT_integer
;
12383 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12384 *type
= NT_untyped
;
12385 else if ((mask
& (N_P8
| N_P16
)) != 0)
12387 else if ((mask
& (N_F32
| N_F64
)) != 0)
12395 /* Modify a bitmask of allowed types. This is only needed for type
12399 modify_types_allowed (unsigned allowed
, unsigned mods
)
12402 enum neon_el_type type
;
12408 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12410 if (el_type_of_type_chk (&type
, &size
,
12411 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12413 neon_modify_type_size (mods
, &type
, &size
);
12414 destmask
|= type_chk_of_el_type (type
, size
);
12421 /* Check type and return type classification.
12422 The manual states (paraphrase): If one datatype is given, it indicates the
12424 - the second operand, if there is one
12425 - the operand, if there is no second operand
12426 - the result, if there are no operands.
12427 This isn't quite good enough though, so we use a concept of a "key" datatype
12428 which is set on a per-instruction basis, which is the one which matters when
12429 only one data type is written.
12430 Note: this function has side-effects (e.g. filling in missing operands). All
12431 Neon instructions should call it before performing bit encoding. */
12433 static struct neon_type_el
12434 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12437 unsigned i
, pass
, key_el
= 0;
12438 unsigned types
[NEON_MAX_TYPE_ELS
];
12439 enum neon_el_type k_type
= NT_invtype
;
12440 unsigned k_size
= -1u;
12441 struct neon_type_el badtype
= {NT_invtype
, -1};
12442 unsigned key_allowed
= 0;
12444 /* Optional registers in Neon instructions are always (not) in operand 1.
12445 Fill in the missing operand here, if it was omitted. */
12446 if (els
> 1 && !inst
.operands
[1].present
)
12447 inst
.operands
[1] = inst
.operands
[0];
12449 /* Suck up all the varargs. */
12451 for (i
= 0; i
< els
; i
++)
12453 unsigned thisarg
= va_arg (ap
, unsigned);
12454 if (thisarg
== N_IGNORE_TYPE
)
12459 types
[i
] = thisarg
;
12460 if ((thisarg
& N_KEY
) != 0)
12465 if (inst
.vectype
.elems
> 0)
12466 for (i
= 0; i
< els
; i
++)
12467 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12469 first_error (_("types specified in both the mnemonic and operands"));
12473 /* Duplicate inst.vectype elements here as necessary.
12474 FIXME: No idea if this is exactly the same as the ARM assembler,
12475 particularly when an insn takes one register and one non-register
12477 if (inst
.vectype
.elems
== 1 && els
> 1)
12480 inst
.vectype
.elems
= els
;
12481 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12482 for (j
= 0; j
< els
; j
++)
12484 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12487 else if (inst
.vectype
.elems
== 0 && els
> 0)
12490 /* No types were given after the mnemonic, so look for types specified
12491 after each operand. We allow some flexibility here; as long as the
12492 "key" operand has a type, we can infer the others. */
12493 for (j
= 0; j
< els
; j
++)
12494 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12495 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12497 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12499 for (j
= 0; j
< els
; j
++)
12500 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12501 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12506 first_error (_("operand types can't be inferred"));
12510 else if (inst
.vectype
.elems
!= els
)
12512 first_error (_("type specifier has the wrong number of parts"));
12516 for (pass
= 0; pass
< 2; pass
++)
12518 for (i
= 0; i
< els
; i
++)
12520 unsigned thisarg
= types
[i
];
12521 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12522 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12523 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12524 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12526 /* Decay more-specific signed & unsigned types to sign-insensitive
12527 integer types if sign-specific variants are unavailable. */
12528 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12529 && (types_allowed
& N_SU_ALL
) == 0)
12530 g_type
= NT_integer
;
12532 /* If only untyped args are allowed, decay any more specific types to
12533 them. Some instructions only care about signs for some element
12534 sizes, so handle that properly. */
12535 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12536 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12537 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12538 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12539 g_type
= NT_untyped
;
12543 if ((thisarg
& N_KEY
) != 0)
12547 key_allowed
= thisarg
& ~N_KEY
;
12552 if ((thisarg
& N_VFP
) != 0)
12554 enum neon_shape_el regshape
;
12555 unsigned regwidth
, match
;
12557 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12560 first_error (_("invalid instruction shape"));
12563 regshape
= neon_shape_tab
[ns
].el
[i
];
12564 regwidth
= neon_shape_el_size
[regshape
];
12566 /* In VFP mode, operands must match register widths. If we
12567 have a key operand, use its width, else use the width of
12568 the current operand. */
12574 if (regwidth
!= match
)
12576 first_error (_("operand size must match register width"));
12581 if ((thisarg
& N_EQK
) == 0)
12583 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12585 if ((given_type
& types_allowed
) == 0)
12587 first_error (_("bad type in Neon instruction"));
12593 enum neon_el_type mod_k_type
= k_type
;
12594 unsigned mod_k_size
= k_size
;
12595 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12596 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12598 first_error (_("inconsistent types in Neon instruction"));
12606 return inst
.vectype
.el
[key_el
];
12609 /* Neon-style VFP instruction forwarding. */
12611 /* Thumb VFP instructions have 0xE in the condition field. */
12614 do_vfp_cond_or_thumb (void)
12619 inst
.instruction
|= 0xe0000000;
12621 inst
.instruction
|= inst
.cond
<< 28;
12624 /* Look up and encode a simple mnemonic, for use as a helper function for the
12625 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12626 etc. It is assumed that operand parsing has already been done, and that the
12627 operands are in the form expected by the given opcode (this isn't necessarily
12628 the same as the form in which they were parsed, hence some massaging must
12629 take place before this function is called).
12630 Checks current arch version against that in the looked-up opcode. */
12633 do_vfp_nsyn_opcode (const char *opname
)
12635 const struct asm_opcode
*opcode
;
12637 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12642 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12643 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12650 inst
.instruction
= opcode
->tvalue
;
12651 opcode
->tencode ();
12655 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12656 opcode
->aencode ();
12661 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12663 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12668 do_vfp_nsyn_opcode ("fadds");
12670 do_vfp_nsyn_opcode ("fsubs");
12675 do_vfp_nsyn_opcode ("faddd");
12677 do_vfp_nsyn_opcode ("fsubd");
12681 /* Check operand types to see if this is a VFP instruction, and if so call
12685 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12687 enum neon_shape rs
;
12688 struct neon_type_el et
;
12693 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12694 et
= neon_check_type (2, rs
,
12695 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12699 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12700 et
= neon_check_type (3, rs
,
12701 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12708 if (et
.type
!= NT_invtype
)
12719 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12721 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12726 do_vfp_nsyn_opcode ("fmacs");
12728 do_vfp_nsyn_opcode ("fnmacs");
12733 do_vfp_nsyn_opcode ("fmacd");
12735 do_vfp_nsyn_opcode ("fnmacd");
12740 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12742 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12747 do_vfp_nsyn_opcode ("ffmas");
12749 do_vfp_nsyn_opcode ("ffnmas");
12754 do_vfp_nsyn_opcode ("ffmad");
12756 do_vfp_nsyn_opcode ("ffnmad");
12761 do_vfp_nsyn_mul (enum neon_shape rs
)
12764 do_vfp_nsyn_opcode ("fmuls");
12766 do_vfp_nsyn_opcode ("fmuld");
12770 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12772 int is_neg
= (inst
.instruction
& 0x80) != 0;
12773 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12778 do_vfp_nsyn_opcode ("fnegs");
12780 do_vfp_nsyn_opcode ("fabss");
12785 do_vfp_nsyn_opcode ("fnegd");
12787 do_vfp_nsyn_opcode ("fabsd");
12791 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12792 insns belong to Neon, and are handled elsewhere. */
12795 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12797 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12801 do_vfp_nsyn_opcode ("fldmdbs");
12803 do_vfp_nsyn_opcode ("fldmias");
12808 do_vfp_nsyn_opcode ("fstmdbs");
12810 do_vfp_nsyn_opcode ("fstmias");
12815 do_vfp_nsyn_sqrt (void)
12817 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12818 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12821 do_vfp_nsyn_opcode ("fsqrts");
12823 do_vfp_nsyn_opcode ("fsqrtd");
12827 do_vfp_nsyn_div (void)
12829 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12830 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12831 N_F32
| N_F64
| N_KEY
| N_VFP
);
12834 do_vfp_nsyn_opcode ("fdivs");
12836 do_vfp_nsyn_opcode ("fdivd");
12840 do_vfp_nsyn_nmul (void)
12842 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12843 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12844 N_F32
| N_F64
| N_KEY
| N_VFP
);
12848 NEON_ENCODE (SINGLE
, inst
);
12849 do_vfp_sp_dyadic ();
12853 NEON_ENCODE (DOUBLE
, inst
);
12854 do_vfp_dp_rd_rn_rm ();
12856 do_vfp_cond_or_thumb ();
12860 do_vfp_nsyn_cmp (void)
12862 if (inst
.operands
[1].isreg
)
12864 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12865 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12869 NEON_ENCODE (SINGLE
, inst
);
12870 do_vfp_sp_monadic ();
12874 NEON_ENCODE (DOUBLE
, inst
);
12875 do_vfp_dp_rd_rm ();
12880 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12881 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12883 switch (inst
.instruction
& 0x0fffffff)
12886 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12889 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12897 NEON_ENCODE (SINGLE
, inst
);
12898 do_vfp_sp_compare_z ();
12902 NEON_ENCODE (DOUBLE
, inst
);
12906 do_vfp_cond_or_thumb ();
12910 nsyn_insert_sp (void)
12912 inst
.operands
[1] = inst
.operands
[0];
12913 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12914 inst
.operands
[0].reg
= REG_SP
;
12915 inst
.operands
[0].isreg
= 1;
12916 inst
.operands
[0].writeback
= 1;
12917 inst
.operands
[0].present
= 1;
12921 do_vfp_nsyn_push (void)
12924 if (inst
.operands
[1].issingle
)
12925 do_vfp_nsyn_opcode ("fstmdbs");
12927 do_vfp_nsyn_opcode ("fstmdbd");
12931 do_vfp_nsyn_pop (void)
12934 if (inst
.operands
[1].issingle
)
12935 do_vfp_nsyn_opcode ("fldmias");
12937 do_vfp_nsyn_opcode ("fldmiad");
12940 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12941 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12944 neon_dp_fixup (struct arm_it
* insn
)
12946 unsigned int i
= insn
->instruction
;
12951 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12962 insn
->instruction
= i
;
12965 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12969 neon_logbits (unsigned x
)
12971 return ffs (x
) - 4;
12974 #define LOW4(R) ((R) & 0xf)
12975 #define HI1(R) (((R) >> 4) & 1)
12977 /* Encode insns with bit pattern:
12979 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12980 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12982 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12983 different meaning for some instruction. */
12986 neon_three_same (int isquad
, int ubit
, int size
)
12988 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12989 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12990 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12991 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12992 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12993 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12994 inst
.instruction
|= (isquad
!= 0) << 6;
12995 inst
.instruction
|= (ubit
!= 0) << 24;
12997 inst
.instruction
|= neon_logbits (size
) << 20;
12999 neon_dp_fixup (&inst
);
13002 /* Encode instructions of the form:
13004 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13005 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13007 Don't write size if SIZE == -1. */
13010 neon_two_same (int qbit
, int ubit
, int size
)
13012 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13013 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13014 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13015 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13016 inst
.instruction
|= (qbit
!= 0) << 6;
13017 inst
.instruction
|= (ubit
!= 0) << 24;
13020 inst
.instruction
|= neon_logbits (size
) << 18;
13022 neon_dp_fixup (&inst
);
13025 /* Neon instruction encoders, in approximate order of appearance. */
13028 do_neon_dyadic_i_su (void)
13030 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13031 struct neon_type_el et
= neon_check_type (3, rs
,
13032 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13033 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13037 do_neon_dyadic_i64_su (void)
13039 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13040 struct neon_type_el et
= neon_check_type (3, rs
,
13041 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13042 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13046 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13049 unsigned size
= et
.size
>> 3;
13050 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13051 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13052 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13053 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13054 inst
.instruction
|= (isquad
!= 0) << 6;
13055 inst
.instruction
|= immbits
<< 16;
13056 inst
.instruction
|= (size
>> 3) << 7;
13057 inst
.instruction
|= (size
& 0x7) << 19;
13059 inst
.instruction
|= (uval
!= 0) << 24;
13061 neon_dp_fixup (&inst
);
13065 do_neon_shl_imm (void)
13067 if (!inst
.operands
[2].isreg
)
13069 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13070 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13071 NEON_ENCODE (IMMED
, inst
);
13072 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13076 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13077 struct neon_type_el et
= neon_check_type (3, rs
,
13078 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13081 /* VSHL/VQSHL 3-register variants have syntax such as:
13083 whereas other 3-register operations encoded by neon_three_same have
13086 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13088 tmp
= inst
.operands
[2].reg
;
13089 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13090 inst
.operands
[1].reg
= tmp
;
13091 NEON_ENCODE (INTEGER
, inst
);
13092 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13097 do_neon_qshl_imm (void)
13099 if (!inst
.operands
[2].isreg
)
13101 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13102 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13104 NEON_ENCODE (IMMED
, inst
);
13105 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13106 inst
.operands
[2].imm
);
13110 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13111 struct neon_type_el et
= neon_check_type (3, rs
,
13112 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13115 /* See note in do_neon_shl_imm. */
13116 tmp
= inst
.operands
[2].reg
;
13117 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13118 inst
.operands
[1].reg
= tmp
;
13119 NEON_ENCODE (INTEGER
, inst
);
13120 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13125 do_neon_rshl (void)
13127 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13128 struct neon_type_el et
= neon_check_type (3, rs
,
13129 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13132 tmp
= inst
.operands
[2].reg
;
13133 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13134 inst
.operands
[1].reg
= tmp
;
13135 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13139 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13141 /* Handle .I8 pseudo-instructions. */
13144 /* Unfortunately, this will make everything apart from zero out-of-range.
13145 FIXME is this the intended semantics? There doesn't seem much point in
13146 accepting .I8 if so. */
13147 immediate
|= immediate
<< 8;
13153 if (immediate
== (immediate
& 0x000000ff))
13155 *immbits
= immediate
;
13158 else if (immediate
== (immediate
& 0x0000ff00))
13160 *immbits
= immediate
>> 8;
13163 else if (immediate
== (immediate
& 0x00ff0000))
13165 *immbits
= immediate
>> 16;
13168 else if (immediate
== (immediate
& 0xff000000))
13170 *immbits
= immediate
>> 24;
13173 if ((immediate
& 0xffff) != (immediate
>> 16))
13174 goto bad_immediate
;
13175 immediate
&= 0xffff;
13178 if (immediate
== (immediate
& 0x000000ff))
13180 *immbits
= immediate
;
13183 else if (immediate
== (immediate
& 0x0000ff00))
13185 *immbits
= immediate
>> 8;
13190 first_error (_("immediate value out of range"));
13194 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13198 neon_bits_same_in_bytes (unsigned imm
)
13200 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13201 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13202 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13203 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13206 /* For immediate of above form, return 0bABCD. */
13209 neon_squash_bits (unsigned imm
)
13211 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13212 | ((imm
& 0x01000000) >> 21);
13215 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13218 neon_qfloat_bits (unsigned imm
)
13220 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13223 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13224 the instruction. *OP is passed as the initial value of the op field, and
13225 may be set to a different value depending on the constant (i.e.
13226 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13227 MVN). If the immediate looks like a repeated pattern then also
13228 try smaller element sizes. */
13231 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13232 unsigned *immbits
, int *op
, int size
,
13233 enum neon_el_type type
)
13235 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13237 if (type
== NT_float
&& !float_p
)
13240 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13242 if (size
!= 32 || *op
== 1)
13244 *immbits
= neon_qfloat_bits (immlo
);
13250 if (neon_bits_same_in_bytes (immhi
)
13251 && neon_bits_same_in_bytes (immlo
))
13255 *immbits
= (neon_squash_bits (immhi
) << 4)
13256 | neon_squash_bits (immlo
);
13261 if (immhi
!= immlo
)
13267 if (immlo
== (immlo
& 0x000000ff))
13272 else if (immlo
== (immlo
& 0x0000ff00))
13274 *immbits
= immlo
>> 8;
13277 else if (immlo
== (immlo
& 0x00ff0000))
13279 *immbits
= immlo
>> 16;
13282 else if (immlo
== (immlo
& 0xff000000))
13284 *immbits
= immlo
>> 24;
13287 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13289 *immbits
= (immlo
>> 8) & 0xff;
13292 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13294 *immbits
= (immlo
>> 16) & 0xff;
13298 if ((immlo
& 0xffff) != (immlo
>> 16))
13305 if (immlo
== (immlo
& 0x000000ff))
13310 else if (immlo
== (immlo
& 0x0000ff00))
13312 *immbits
= immlo
>> 8;
13316 if ((immlo
& 0xff) != (immlo
>> 8))
13321 if (immlo
== (immlo
& 0x000000ff))
13323 /* Don't allow MVN with 8-bit immediate. */
13333 /* Write immediate bits [7:0] to the following locations:
13335 |28/24|23 19|18 16|15 4|3 0|
13336 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13338 This function is used by VMOV/VMVN/VORR/VBIC. */
13341 neon_write_immbits (unsigned immbits
)
13343 inst
.instruction
|= immbits
& 0xf;
13344 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13345 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13348 /* Invert low-order SIZE bits of XHI:XLO. */
13351 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13353 unsigned immlo
= xlo
? *xlo
: 0;
13354 unsigned immhi
= xhi
? *xhi
: 0;
13359 immlo
= (~immlo
) & 0xff;
13363 immlo
= (~immlo
) & 0xffff;
13367 immhi
= (~immhi
) & 0xffffffff;
13368 /* fall through. */
13371 immlo
= (~immlo
) & 0xffffffff;
13386 do_neon_logic (void)
13388 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13390 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13391 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13392 /* U bit and size field were set as part of the bitmask. */
13393 NEON_ENCODE (INTEGER
, inst
);
13394 neon_three_same (neon_quad (rs
), 0, -1);
13398 const int three_ops_form
= (inst
.operands
[2].present
13399 && !inst
.operands
[2].isreg
);
13400 const int immoperand
= (three_ops_form
? 2 : 1);
13401 enum neon_shape rs
= (three_ops_form
13402 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13403 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13404 struct neon_type_el et
= neon_check_type (2, rs
,
13405 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13406 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13410 if (et
.type
== NT_invtype
)
13413 if (three_ops_form
)
13414 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13415 _("first and second operands shall be the same register"));
13417 NEON_ENCODE (IMMED
, inst
);
13419 immbits
= inst
.operands
[immoperand
].imm
;
13422 /* .i64 is a pseudo-op, so the immediate must be a repeating
13424 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13425 inst
.operands
[immoperand
].reg
: 0))
13427 /* Set immbits to an invalid constant. */
13428 immbits
= 0xdeadbeef;
13435 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13439 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13443 /* Pseudo-instruction for VBIC. */
13444 neon_invert_size (&immbits
, 0, et
.size
);
13445 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13449 /* Pseudo-instruction for VORR. */
13450 neon_invert_size (&immbits
, 0, et
.size
);
13451 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13461 inst
.instruction
|= neon_quad (rs
) << 6;
13462 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13463 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13464 inst
.instruction
|= cmode
<< 8;
13465 neon_write_immbits (immbits
);
13467 neon_dp_fixup (&inst
);
13472 do_neon_bitfield (void)
13474 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13475 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13476 neon_three_same (neon_quad (rs
), 0, -1);
13480 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13483 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13484 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13486 if (et
.type
== NT_float
)
13488 NEON_ENCODE (FLOAT
, inst
);
13489 neon_three_same (neon_quad (rs
), 0, -1);
13493 NEON_ENCODE (INTEGER
, inst
);
13494 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13499 do_neon_dyadic_if_su (void)
13501 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13505 do_neon_dyadic_if_su_d (void)
13507 /* This version only allow D registers, but that constraint is enforced during
13508 operand parsing so we don't need to do anything extra here. */
13509 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13513 do_neon_dyadic_if_i_d (void)
13515 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13516 affected if we specify unsigned args. */
13517 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13520 enum vfp_or_neon_is_neon_bits
13523 NEON_CHECK_ARCH
= 2
13526 /* Call this function if an instruction which may have belonged to the VFP or
13527 Neon instruction sets, but turned out to be a Neon instruction (due to the
13528 operand types involved, etc.). We have to check and/or fix-up a couple of
13531 - Make sure the user hasn't attempted to make a Neon instruction
13533 - Alter the value in the condition code field if necessary.
13534 - Make sure that the arch supports Neon instructions.
13536 Which of these operations take place depends on bits from enum
13537 vfp_or_neon_is_neon_bits.
13539 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13540 current instruction's condition is COND_ALWAYS, the condition field is
13541 changed to inst.uncond_value. This is necessary because instructions shared
13542 between VFP and Neon may be conditional for the VFP variants only, and the
13543 unconditional Neon version must have, e.g., 0xF in the condition field. */
13546 vfp_or_neon_is_neon (unsigned check
)
13548 /* Conditions are always legal in Thumb mode (IT blocks). */
13549 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13551 if (inst
.cond
!= COND_ALWAYS
)
13553 first_error (_(BAD_COND
));
13556 if (inst
.uncond_value
!= -1)
13557 inst
.instruction
|= inst
.uncond_value
<< 28;
13560 if ((check
& NEON_CHECK_ARCH
)
13561 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13563 first_error (_(BAD_FPU
));
13571 do_neon_addsub_if_i (void)
13573 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13576 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13579 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13580 affected if we specify unsigned args. */
13581 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13584 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13586 V<op> A,B (A is operand 0, B is operand 2)
13591 so handle that case specially. */
13594 neon_exchange_operands (void)
13596 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13597 if (inst
.operands
[1].present
)
13599 /* Swap operands[1] and operands[2]. */
13600 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13601 inst
.operands
[1] = inst
.operands
[2];
13602 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13606 inst
.operands
[1] = inst
.operands
[2];
13607 inst
.operands
[2] = inst
.operands
[0];
13612 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13614 if (inst
.operands
[2].isreg
)
13617 neon_exchange_operands ();
13618 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13622 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13623 struct neon_type_el et
= neon_check_type (2, rs
,
13624 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13626 NEON_ENCODE (IMMED
, inst
);
13627 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13628 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13629 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13630 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13631 inst
.instruction
|= neon_quad (rs
) << 6;
13632 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13633 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13635 neon_dp_fixup (&inst
);
13642 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13646 do_neon_cmp_inv (void)
13648 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13654 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13657 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13658 scalars, which are encoded in 5 bits, M : Rm.
13659 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13660 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13664 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13666 unsigned regno
= NEON_SCALAR_REG (scalar
);
13667 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13672 if (regno
> 7 || elno
> 3)
13674 return regno
| (elno
<< 3);
13677 if (regno
> 15 || elno
> 1)
13679 return regno
| (elno
<< 4);
13683 first_error (_("scalar out of range for multiply instruction"));
13689 /* Encode multiply / multiply-accumulate scalar instructions. */
13692 neon_mul_mac (struct neon_type_el et
, int ubit
)
13696 /* Give a more helpful error message if we have an invalid type. */
13697 if (et
.type
== NT_invtype
)
13700 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13701 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13702 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13703 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13704 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13705 inst
.instruction
|= LOW4 (scalar
);
13706 inst
.instruction
|= HI1 (scalar
) << 5;
13707 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13708 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13709 inst
.instruction
|= (ubit
!= 0) << 24;
13711 neon_dp_fixup (&inst
);
13715 do_neon_mac_maybe_scalar (void)
13717 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13720 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13723 if (inst
.operands
[2].isscalar
)
13725 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13726 struct neon_type_el et
= neon_check_type (3, rs
,
13727 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13728 NEON_ENCODE (SCALAR
, inst
);
13729 neon_mul_mac (et
, neon_quad (rs
));
13733 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13734 affected if we specify unsigned args. */
13735 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13740 do_neon_fmac (void)
13742 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13745 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13748 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13754 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13755 struct neon_type_el et
= neon_check_type (3, rs
,
13756 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13757 neon_three_same (neon_quad (rs
), 0, et
.size
);
13760 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13761 same types as the MAC equivalents. The polynomial type for this instruction
13762 is encoded the same as the integer type. */
13767 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13770 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13773 if (inst
.operands
[2].isscalar
)
13774 do_neon_mac_maybe_scalar ();
13776 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13780 do_neon_qdmulh (void)
13782 if (inst
.operands
[2].isscalar
)
13784 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13785 struct neon_type_el et
= neon_check_type (3, rs
,
13786 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13787 NEON_ENCODE (SCALAR
, inst
);
13788 neon_mul_mac (et
, neon_quad (rs
));
13792 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13793 struct neon_type_el et
= neon_check_type (3, rs
,
13794 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13795 NEON_ENCODE (INTEGER
, inst
);
13796 /* The U bit (rounding) comes from bit mask. */
13797 neon_three_same (neon_quad (rs
), 0, et
.size
);
13802 do_neon_fcmp_absolute (void)
13804 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13805 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13806 /* Size field comes from bit mask. */
13807 neon_three_same (neon_quad (rs
), 1, -1);
13811 do_neon_fcmp_absolute_inv (void)
13813 neon_exchange_operands ();
13814 do_neon_fcmp_absolute ();
13818 do_neon_step (void)
13820 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13821 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13822 neon_three_same (neon_quad (rs
), 0, -1);
13826 do_neon_abs_neg (void)
13828 enum neon_shape rs
;
13829 struct neon_type_el et
;
13831 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13834 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13837 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13838 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13840 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13841 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13842 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13843 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13844 inst
.instruction
|= neon_quad (rs
) << 6;
13845 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13846 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13848 neon_dp_fixup (&inst
);
13854 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13855 struct neon_type_el et
= neon_check_type (2, rs
,
13856 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13857 int imm
= inst
.operands
[2].imm
;
13858 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13859 _("immediate out of range for insert"));
13860 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13866 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13867 struct neon_type_el et
= neon_check_type (2, rs
,
13868 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13869 int imm
= inst
.operands
[2].imm
;
13870 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13871 _("immediate out of range for insert"));
13872 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13876 do_neon_qshlu_imm (void)
13878 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13879 struct neon_type_el et
= neon_check_type (2, rs
,
13880 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13881 int imm
= inst
.operands
[2].imm
;
13882 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13883 _("immediate out of range for shift"));
13884 /* Only encodes the 'U present' variant of the instruction.
13885 In this case, signed types have OP (bit 8) set to 0.
13886 Unsigned types have OP set to 1. */
13887 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13888 /* The rest of the bits are the same as other immediate shifts. */
13889 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13893 do_neon_qmovn (void)
13895 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13896 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13897 /* Saturating move where operands can be signed or unsigned, and the
13898 destination has the same signedness. */
13899 NEON_ENCODE (INTEGER
, inst
);
13900 if (et
.type
== NT_unsigned
)
13901 inst
.instruction
|= 0xc0;
13903 inst
.instruction
|= 0x80;
13904 neon_two_same (0, 1, et
.size
/ 2);
13908 do_neon_qmovun (void)
13910 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13911 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13912 /* Saturating move with unsigned results. Operands must be signed. */
13913 NEON_ENCODE (INTEGER
, inst
);
13914 neon_two_same (0, 1, et
.size
/ 2);
13918 do_neon_rshift_sat_narrow (void)
13920 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13921 or unsigned. If operands are unsigned, results must also be unsigned. */
13922 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13923 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13924 int imm
= inst
.operands
[2].imm
;
13925 /* This gets the bounds check, size encoding and immediate bits calculation
13929 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13930 VQMOVN.I<size> <Dd>, <Qm>. */
13933 inst
.operands
[2].present
= 0;
13934 inst
.instruction
= N_MNEM_vqmovn
;
13939 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13940 _("immediate out of range"));
13941 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13945 do_neon_rshift_sat_narrow_u (void)
13947 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13948 or unsigned. If operands are unsigned, results must also be unsigned. */
13949 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13950 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13951 int imm
= inst
.operands
[2].imm
;
13952 /* This gets the bounds check, size encoding and immediate bits calculation
13956 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13957 VQMOVUN.I<size> <Dd>, <Qm>. */
13960 inst
.operands
[2].present
= 0;
13961 inst
.instruction
= N_MNEM_vqmovun
;
13966 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13967 _("immediate out of range"));
13968 /* FIXME: The manual is kind of unclear about what value U should have in
13969 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13971 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13975 do_neon_movn (void)
13977 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13978 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13979 NEON_ENCODE (INTEGER
, inst
);
13980 neon_two_same (0, 1, et
.size
/ 2);
13984 do_neon_rshift_narrow (void)
13986 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13987 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13988 int imm
= inst
.operands
[2].imm
;
13989 /* This gets the bounds check, size encoding and immediate bits calculation
13993 /* If immediate is zero then we are a pseudo-instruction for
13994 VMOVN.I<size> <Dd>, <Qm> */
13997 inst
.operands
[2].present
= 0;
13998 inst
.instruction
= N_MNEM_vmovn
;
14003 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14004 _("immediate out of range for narrowing operation"));
14005 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14009 do_neon_shll (void)
14011 /* FIXME: Type checking when lengthening. */
14012 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14013 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14014 unsigned imm
= inst
.operands
[2].imm
;
14016 if (imm
== et
.size
)
14018 /* Maximum shift variant. */
14019 NEON_ENCODE (INTEGER
, inst
);
14020 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14021 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14022 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14023 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14024 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14026 neon_dp_fixup (&inst
);
14030 /* A more-specific type check for non-max versions. */
14031 et
= neon_check_type (2, NS_QDI
,
14032 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14033 NEON_ENCODE (IMMED
, inst
);
14034 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14038 /* Check the various types for the VCVT instruction, and return which version
14039 the current instruction is. */
14042 neon_cvt_flavour (enum neon_shape rs
)
14044 #define CVT_VAR(C,X,Y) \
14045 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14046 if (et.type != NT_invtype) \
14048 inst.error = NULL; \
14051 struct neon_type_el et
;
14052 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14053 || rs
== NS_FF
) ? N_VFP
: 0;
14054 /* The instruction versions which take an immediate take one register
14055 argument, which is extended to the width of the full register. Thus the
14056 "source" and "destination" registers must have the same width. Hack that
14057 here by making the size equal to the key (wider, in this case) operand. */
14058 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14060 CVT_VAR (0, N_S32
, N_F32
);
14061 CVT_VAR (1, N_U32
, N_F32
);
14062 CVT_VAR (2, N_F32
, N_S32
);
14063 CVT_VAR (3, N_F32
, N_U32
);
14064 /* Half-precision conversions. */
14065 CVT_VAR (4, N_F32
, N_F16
);
14066 CVT_VAR (5, N_F16
, N_F32
);
14070 /* VFP instructions. */
14071 CVT_VAR (6, N_F32
, N_F64
);
14072 CVT_VAR (7, N_F64
, N_F32
);
14073 CVT_VAR (8, N_S32
, N_F64
| key
);
14074 CVT_VAR (9, N_U32
, N_F64
| key
);
14075 CVT_VAR (10, N_F64
| key
, N_S32
);
14076 CVT_VAR (11, N_F64
| key
, N_U32
);
14077 /* VFP instructions with bitshift. */
14078 CVT_VAR (12, N_F32
| key
, N_S16
);
14079 CVT_VAR (13, N_F32
| key
, N_U16
);
14080 CVT_VAR (14, N_F64
| key
, N_S16
);
14081 CVT_VAR (15, N_F64
| key
, N_U16
);
14082 CVT_VAR (16, N_S16
, N_F32
| key
);
14083 CVT_VAR (17, N_U16
, N_F32
| key
);
14084 CVT_VAR (18, N_S16
, N_F64
| key
);
14085 CVT_VAR (19, N_U16
, N_F64
| key
);
14091 /* Neon-syntax VFP conversions. */
14094 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
14096 const char *opname
= 0;
14098 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14100 /* Conversions with immediate bitshift. */
14101 const char *enc
[] =
14125 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14127 opname
= enc
[flavour
];
14128 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14129 _("operands 0 and 1 must be the same register"));
14130 inst
.operands
[1] = inst
.operands
[2];
14131 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14136 /* Conversions without bitshift. */
14137 const char *enc
[] =
14153 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14154 opname
= enc
[flavour
];
14158 do_vfp_nsyn_opcode (opname
);
14162 do_vfp_nsyn_cvtz (void)
14164 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14165 int flavour
= neon_cvt_flavour (rs
);
14166 const char *enc
[] =
14180 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14181 do_vfp_nsyn_opcode (enc
[flavour
]);
14185 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14187 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14188 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14189 int flavour
= neon_cvt_flavour (rs
);
14191 /* PR11109: Handle round-to-zero for VCVT conversions. */
14193 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14194 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14195 && (rs
== NS_FD
|| rs
== NS_FF
))
14197 do_vfp_nsyn_cvtz ();
14201 /* VFP rather than Neon conversions. */
14204 do_vfp_nsyn_cvt (rs
, flavour
);
14214 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14216 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14219 /* Fixed-point conversion with #0 immediate is encoded as an
14220 integer conversion. */
14221 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14223 immbits
= 32 - inst
.operands
[2].imm
;
14224 NEON_ENCODE (IMMED
, inst
);
14226 inst
.instruction
|= enctab
[flavour
];
14227 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14228 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14229 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14230 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14231 inst
.instruction
|= neon_quad (rs
) << 6;
14232 inst
.instruction
|= 1 << 21;
14233 inst
.instruction
|= immbits
<< 16;
14235 neon_dp_fixup (&inst
);
14243 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14245 NEON_ENCODE (INTEGER
, inst
);
14247 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14251 inst
.instruction
|= enctab
[flavour
];
14253 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14254 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14255 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14256 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14257 inst
.instruction
|= neon_quad (rs
) << 6;
14258 inst
.instruction
|= 2 << 18;
14260 neon_dp_fixup (&inst
);
14264 /* Half-precision conversions for Advanced SIMD -- neon. */
14269 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14271 as_bad (_("operand size must match register width"));
14276 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14278 as_bad (_("operand size must match register width"));
14283 inst
.instruction
= 0x3b60600;
14285 inst
.instruction
= 0x3b60700;
14287 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14288 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14289 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14290 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14291 neon_dp_fixup (&inst
);
14295 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14296 do_vfp_nsyn_cvt (rs
, flavour
);
14301 do_neon_cvtr (void)
14303 do_neon_cvt_1 (FALSE
);
14309 do_neon_cvt_1 (TRUE
);
14313 do_neon_cvtb (void)
14315 inst
.instruction
= 0xeb20a40;
14317 /* The sizes are attached to the mnemonic. */
14318 if (inst
.vectype
.el
[0].type
!= NT_invtype
14319 && inst
.vectype
.el
[0].size
== 16)
14320 inst
.instruction
|= 0x00010000;
14322 /* Programmer's syntax: the sizes are attached to the operands. */
14323 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14324 && inst
.operands
[0].vectype
.size
== 16)
14325 inst
.instruction
|= 0x00010000;
14327 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14328 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14329 do_vfp_cond_or_thumb ();
14334 do_neon_cvtt (void)
14337 inst
.instruction
|= 0x80;
14341 neon_move_immediate (void)
14343 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14344 struct neon_type_el et
= neon_check_type (2, rs
,
14345 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14346 unsigned immlo
, immhi
= 0, immbits
;
14347 int op
, cmode
, float_p
;
14349 constraint (et
.type
== NT_invtype
,
14350 _("operand size must be specified for immediate VMOV"));
14352 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14353 op
= (inst
.instruction
& (1 << 5)) != 0;
14355 immlo
= inst
.operands
[1].imm
;
14356 if (inst
.operands
[1].regisimm
)
14357 immhi
= inst
.operands
[1].reg
;
14359 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14360 _("immediate has bits set outside the operand size"));
14362 float_p
= inst
.operands
[1].immisfloat
;
14364 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14365 et
.size
, et
.type
)) == FAIL
)
14367 /* Invert relevant bits only. */
14368 neon_invert_size (&immlo
, &immhi
, et
.size
);
14369 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14370 with one or the other; those cases are caught by
14371 neon_cmode_for_move_imm. */
14373 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14374 &op
, et
.size
, et
.type
)) == FAIL
)
14376 first_error (_("immediate out of range"));
14381 inst
.instruction
&= ~(1 << 5);
14382 inst
.instruction
|= op
<< 5;
14384 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14385 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14386 inst
.instruction
|= neon_quad (rs
) << 6;
14387 inst
.instruction
|= cmode
<< 8;
14389 neon_write_immbits (immbits
);
14395 if (inst
.operands
[1].isreg
)
14397 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14399 NEON_ENCODE (INTEGER
, inst
);
14400 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14401 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14402 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14403 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14404 inst
.instruction
|= neon_quad (rs
) << 6;
14408 NEON_ENCODE (IMMED
, inst
);
14409 neon_move_immediate ();
14412 neon_dp_fixup (&inst
);
14415 /* Encode instructions of form:
14417 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14418 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14421 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14423 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14424 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14425 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14426 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14427 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14428 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14429 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14430 inst
.instruction
|= neon_logbits (size
) << 20;
14432 neon_dp_fixup (&inst
);
14436 do_neon_dyadic_long (void)
14438 /* FIXME: Type checking for lengthening op. */
14439 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14440 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14441 neon_mixed_length (et
, et
.size
);
14445 do_neon_abal (void)
14447 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14448 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14449 neon_mixed_length (et
, et
.size
);
14453 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14455 if (inst
.operands
[2].isscalar
)
14457 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14458 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14459 NEON_ENCODE (SCALAR
, inst
);
14460 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14464 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14465 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14466 NEON_ENCODE (INTEGER
, inst
);
14467 neon_mixed_length (et
, et
.size
);
14472 do_neon_mac_maybe_scalar_long (void)
14474 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14478 do_neon_dyadic_wide (void)
14480 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14481 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14482 neon_mixed_length (et
, et
.size
);
14486 do_neon_dyadic_narrow (void)
14488 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14489 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14490 /* Operand sign is unimportant, and the U bit is part of the opcode,
14491 so force the operand type to integer. */
14492 et
.type
= NT_integer
;
14493 neon_mixed_length (et
, et
.size
/ 2);
14497 do_neon_mul_sat_scalar_long (void)
14499 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14503 do_neon_vmull (void)
14505 if (inst
.operands
[2].isscalar
)
14506 do_neon_mac_maybe_scalar_long ();
14509 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14510 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14511 if (et
.type
== NT_poly
)
14512 NEON_ENCODE (POLY
, inst
);
14514 NEON_ENCODE (INTEGER
, inst
);
14515 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14516 zero. Should be OK as-is. */
14517 neon_mixed_length (et
, et
.size
);
14524 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14525 struct neon_type_el et
= neon_check_type (3, rs
,
14526 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14527 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14529 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14530 _("shift out of range"));
14531 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14532 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14533 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14534 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14535 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14536 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14537 inst
.instruction
|= neon_quad (rs
) << 6;
14538 inst
.instruction
|= imm
<< 8;
14540 neon_dp_fixup (&inst
);
14546 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14547 struct neon_type_el et
= neon_check_type (2, rs
,
14548 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14549 unsigned op
= (inst
.instruction
>> 7) & 3;
14550 /* N (width of reversed regions) is encoded as part of the bitmask. We
14551 extract it here to check the elements to be reversed are smaller.
14552 Otherwise we'd get a reserved instruction. */
14553 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14554 gas_assert (elsize
!= 0);
14555 constraint (et
.size
>= elsize
,
14556 _("elements must be smaller than reversal region"));
14557 neon_two_same (neon_quad (rs
), 1, et
.size
);
14563 if (inst
.operands
[1].isscalar
)
14565 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14566 struct neon_type_el et
= neon_check_type (2, rs
,
14567 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14568 unsigned sizebits
= et
.size
>> 3;
14569 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14570 int logsize
= neon_logbits (et
.size
);
14571 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14573 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14576 NEON_ENCODE (SCALAR
, inst
);
14577 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14578 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14579 inst
.instruction
|= LOW4 (dm
);
14580 inst
.instruction
|= HI1 (dm
) << 5;
14581 inst
.instruction
|= neon_quad (rs
) << 6;
14582 inst
.instruction
|= x
<< 17;
14583 inst
.instruction
|= sizebits
<< 16;
14585 neon_dp_fixup (&inst
);
14589 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14590 struct neon_type_el et
= neon_check_type (2, rs
,
14591 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14592 /* Duplicate ARM register to lanes of vector. */
14593 NEON_ENCODE (ARMREG
, inst
);
14596 case 8: inst
.instruction
|= 0x400000; break;
14597 case 16: inst
.instruction
|= 0x000020; break;
14598 case 32: inst
.instruction
|= 0x000000; break;
14601 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14602 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14603 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14604 inst
.instruction
|= neon_quad (rs
) << 21;
14605 /* The encoding for this instruction is identical for the ARM and Thumb
14606 variants, except for the condition field. */
14607 do_vfp_cond_or_thumb ();
14611 /* VMOV has particularly many variations. It can be one of:
14612 0. VMOV<c><q> <Qd>, <Qm>
14613 1. VMOV<c><q> <Dd>, <Dm>
14614 (Register operations, which are VORR with Rm = Rn.)
14615 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14616 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14618 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14619 (ARM register to scalar.)
14620 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14621 (Two ARM registers to vector.)
14622 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14623 (Scalar to ARM register.)
14624 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14625 (Vector to two ARM registers.)
14626 8. VMOV.F32 <Sd>, <Sm>
14627 9. VMOV.F64 <Dd>, <Dm>
14628 (VFP register moves.)
14629 10. VMOV.F32 <Sd>, #imm
14630 11. VMOV.F64 <Dd>, #imm
14631 (VFP float immediate load.)
14632 12. VMOV <Rd>, <Sm>
14633 (VFP single to ARM reg.)
14634 13. VMOV <Sd>, <Rm>
14635 (ARM reg to VFP single.)
14636 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14637 (Two ARM regs to two VFP singles.)
14638 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14639 (Two VFP singles to two ARM regs.)
14641 These cases can be disambiguated using neon_select_shape, except cases 1/9
14642 and 3/11 which depend on the operand type too.
14644 All the encoded bits are hardcoded by this function.
14646 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14647 Cases 5, 7 may be used with VFPv2 and above.
14649 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14650 can specify a type where it doesn't make sense to, and is ignored). */
14655 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14656 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14658 struct neon_type_el et
;
14659 const char *ldconst
= 0;
14663 case NS_DD
: /* case 1/9. */
14664 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14665 /* It is not an error here if no type is given. */
14667 if (et
.type
== NT_float
&& et
.size
== 64)
14669 do_vfp_nsyn_opcode ("fcpyd");
14672 /* fall through. */
14674 case NS_QQ
: /* case 0/1. */
14676 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14678 /* The architecture manual I have doesn't explicitly state which
14679 value the U bit should have for register->register moves, but
14680 the equivalent VORR instruction has U = 0, so do that. */
14681 inst
.instruction
= 0x0200110;
14682 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14683 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14684 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14685 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14686 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14687 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14688 inst
.instruction
|= neon_quad (rs
) << 6;
14690 neon_dp_fixup (&inst
);
14694 case NS_DI
: /* case 3/11. */
14695 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14697 if (et
.type
== NT_float
&& et
.size
== 64)
14699 /* case 11 (fconstd). */
14700 ldconst
= "fconstd";
14701 goto encode_fconstd
;
14703 /* fall through. */
14705 case NS_QI
: /* case 2/3. */
14706 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14708 inst
.instruction
= 0x0800010;
14709 neon_move_immediate ();
14710 neon_dp_fixup (&inst
);
14713 case NS_SR
: /* case 4. */
14715 unsigned bcdebits
= 0;
14717 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14718 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14720 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14721 logsize
= neon_logbits (et
.size
);
14723 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14725 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14726 && et
.size
!= 32, _(BAD_FPU
));
14727 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14728 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14732 case 8: bcdebits
= 0x8; break;
14733 case 16: bcdebits
= 0x1; break;
14734 case 32: bcdebits
= 0x0; break;
14738 bcdebits
|= x
<< logsize
;
14740 inst
.instruction
= 0xe000b10;
14741 do_vfp_cond_or_thumb ();
14742 inst
.instruction
|= LOW4 (dn
) << 16;
14743 inst
.instruction
|= HI1 (dn
) << 7;
14744 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14745 inst
.instruction
|= (bcdebits
& 3) << 5;
14746 inst
.instruction
|= (bcdebits
>> 2) << 21;
14750 case NS_DRR
: /* case 5 (fmdrr). */
14751 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14754 inst
.instruction
= 0xc400b10;
14755 do_vfp_cond_or_thumb ();
14756 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14757 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14758 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14759 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14762 case NS_RS
: /* case 6. */
14765 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14766 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14767 unsigned abcdebits
= 0;
14769 et
= neon_check_type (2, NS_NULL
,
14770 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14771 logsize
= neon_logbits (et
.size
);
14773 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14775 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14776 && et
.size
!= 32, _(BAD_FPU
));
14777 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14778 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14782 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14783 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14784 case 32: abcdebits
= 0x00; break;
14788 abcdebits
|= x
<< logsize
;
14789 inst
.instruction
= 0xe100b10;
14790 do_vfp_cond_or_thumb ();
14791 inst
.instruction
|= LOW4 (dn
) << 16;
14792 inst
.instruction
|= HI1 (dn
) << 7;
14793 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14794 inst
.instruction
|= (abcdebits
& 3) << 5;
14795 inst
.instruction
|= (abcdebits
>> 2) << 21;
14799 case NS_RRD
: /* case 7 (fmrrd). */
14800 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14803 inst
.instruction
= 0xc500b10;
14804 do_vfp_cond_or_thumb ();
14805 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14806 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14807 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14808 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14811 case NS_FF
: /* case 8 (fcpys). */
14812 do_vfp_nsyn_opcode ("fcpys");
14815 case NS_FI
: /* case 10 (fconsts). */
14816 ldconst
= "fconsts";
14818 if (is_quarter_float (inst
.operands
[1].imm
))
14820 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14821 do_vfp_nsyn_opcode (ldconst
);
14824 first_error (_("immediate out of range"));
14827 case NS_RF
: /* case 12 (fmrs). */
14828 do_vfp_nsyn_opcode ("fmrs");
14831 case NS_FR
: /* case 13 (fmsr). */
14832 do_vfp_nsyn_opcode ("fmsr");
14835 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14836 (one of which is a list), but we have parsed four. Do some fiddling to
14837 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14839 case NS_RRFF
: /* case 14 (fmrrs). */
14840 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14841 _("VFP registers must be adjacent"));
14842 inst
.operands
[2].imm
= 2;
14843 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14844 do_vfp_nsyn_opcode ("fmrrs");
14847 case NS_FFRR
: /* case 15 (fmsrr). */
14848 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14849 _("VFP registers must be adjacent"));
14850 inst
.operands
[1] = inst
.operands
[2];
14851 inst
.operands
[2] = inst
.operands
[3];
14852 inst
.operands
[0].imm
= 2;
14853 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14854 do_vfp_nsyn_opcode ("fmsrr");
14863 do_neon_rshift_round_imm (void)
14865 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14866 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14867 int imm
= inst
.operands
[2].imm
;
14869 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14872 inst
.operands
[2].present
= 0;
14877 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14878 _("immediate out of range for shift"));
14879 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14884 do_neon_movl (void)
14886 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14887 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14888 unsigned sizebits
= et
.size
>> 3;
14889 inst
.instruction
|= sizebits
<< 19;
14890 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14896 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14897 struct neon_type_el et
= neon_check_type (2, rs
,
14898 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14899 NEON_ENCODE (INTEGER
, inst
);
14900 neon_two_same (neon_quad (rs
), 1, et
.size
);
14904 do_neon_zip_uzp (void)
14906 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14907 struct neon_type_el et
= neon_check_type (2, rs
,
14908 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14909 if (rs
== NS_DD
&& et
.size
== 32)
14911 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14912 inst
.instruction
= N_MNEM_vtrn
;
14916 neon_two_same (neon_quad (rs
), 1, et
.size
);
14920 do_neon_sat_abs_neg (void)
14922 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14923 struct neon_type_el et
= neon_check_type (2, rs
,
14924 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14925 neon_two_same (neon_quad (rs
), 1, et
.size
);
14929 do_neon_pair_long (void)
14931 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14932 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14933 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14934 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14935 neon_two_same (neon_quad (rs
), 1, et
.size
);
14939 do_neon_recip_est (void)
14941 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14942 struct neon_type_el et
= neon_check_type (2, rs
,
14943 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14944 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14945 neon_two_same (neon_quad (rs
), 1, et
.size
);
14951 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14952 struct neon_type_el et
= neon_check_type (2, rs
,
14953 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14954 neon_two_same (neon_quad (rs
), 1, et
.size
);
14960 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14961 struct neon_type_el et
= neon_check_type (2, rs
,
14962 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14963 neon_two_same (neon_quad (rs
), 1, et
.size
);
14969 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14970 struct neon_type_el et
= neon_check_type (2, rs
,
14971 N_EQK
| N_INT
, N_8
| N_KEY
);
14972 neon_two_same (neon_quad (rs
), 1, et
.size
);
14978 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14979 neon_two_same (neon_quad (rs
), 1, -1);
14983 do_neon_tbl_tbx (void)
14985 unsigned listlenbits
;
14986 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14988 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14990 first_error (_("bad list length for table lookup"));
14994 listlenbits
= inst
.operands
[1].imm
- 1;
14995 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14996 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14997 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14998 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14999 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15000 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15001 inst
.instruction
|= listlenbits
<< 8;
15003 neon_dp_fixup (&inst
);
15007 do_neon_ldm_stm (void)
15009 /* P, U and L bits are part of bitmask. */
15010 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15011 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15013 if (inst
.operands
[1].issingle
)
15015 do_vfp_nsyn_ldm_stm (is_dbmode
);
15019 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15020 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15022 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15023 _("register list must contain at least 1 and at most 16 "
15026 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15027 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15028 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15029 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15031 inst
.instruction
|= offsetbits
;
15033 do_vfp_cond_or_thumb ();
15037 do_neon_ldr_str (void)
15039 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15041 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15042 And is UNPREDICTABLE in thumb mode. */
15044 && inst
.operands
[1].reg
== REG_PC
15045 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
15047 if (!thumb_mode
&& warn_on_deprecated
)
15048 as_warn (_("Use of PC here is deprecated"));
15050 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15053 if (inst
.operands
[0].issingle
)
15056 do_vfp_nsyn_opcode ("flds");
15058 do_vfp_nsyn_opcode ("fsts");
15063 do_vfp_nsyn_opcode ("fldd");
15065 do_vfp_nsyn_opcode ("fstd");
15069 /* "interleave" version also handles non-interleaving register VLD1/VST1
15073 do_neon_ld_st_interleave (void)
15075 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15076 N_8
| N_16
| N_32
| N_64
);
15077 unsigned alignbits
= 0;
15079 /* The bits in this table go:
15080 0: register stride of one (0) or two (1)
15081 1,2: register list length, minus one (1, 2, 3, 4).
15082 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15083 We use -1 for invalid entries. */
15084 const int typetable
[] =
15086 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15087 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15088 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15089 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15093 if (et
.type
== NT_invtype
)
15096 if (inst
.operands
[1].immisalign
)
15097 switch (inst
.operands
[1].imm
>> 8)
15099 case 64: alignbits
= 1; break;
15101 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15102 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15103 goto bad_alignment
;
15107 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15108 goto bad_alignment
;
15113 first_error (_("bad alignment"));
15117 inst
.instruction
|= alignbits
<< 4;
15118 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15120 /* Bits [4:6] of the immediate in a list specifier encode register stride
15121 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15122 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15123 up the right value for "type" in a table based on this value and the given
15124 list style, then stick it back. */
15125 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15126 | (((inst
.instruction
>> 8) & 3) << 3);
15128 typebits
= typetable
[idx
];
15130 constraint (typebits
== -1, _("bad list type for instruction"));
15132 inst
.instruction
&= ~0xf00;
15133 inst
.instruction
|= typebits
<< 8;
15136 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15137 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15138 otherwise. The variable arguments are a list of pairs of legal (size, align)
15139 values, terminated with -1. */
15142 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15145 int result
= FAIL
, thissize
, thisalign
;
15147 if (!inst
.operands
[1].immisalign
)
15153 va_start (ap
, do_align
);
15157 thissize
= va_arg (ap
, int);
15158 if (thissize
== -1)
15160 thisalign
= va_arg (ap
, int);
15162 if (size
== thissize
&& align
== thisalign
)
15165 while (result
!= SUCCESS
);
15169 if (result
== SUCCESS
)
15172 first_error (_("unsupported alignment for instruction"));
15178 do_neon_ld_st_lane (void)
15180 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15181 int align_good
, do_align
= 0;
15182 int logsize
= neon_logbits (et
.size
);
15183 int align
= inst
.operands
[1].imm
>> 8;
15184 int n
= (inst
.instruction
>> 8) & 3;
15185 int max_el
= 64 / et
.size
;
15187 if (et
.type
== NT_invtype
)
15190 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15191 _("bad list length"));
15192 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15193 _("scalar index out of range"));
15194 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15196 _("stride of 2 unavailable when element size is 8"));
15200 case 0: /* VLD1 / VST1. */
15201 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15203 if (align_good
== FAIL
)
15207 unsigned alignbits
= 0;
15210 case 16: alignbits
= 0x1; break;
15211 case 32: alignbits
= 0x3; break;
15214 inst
.instruction
|= alignbits
<< 4;
15218 case 1: /* VLD2 / VST2. */
15219 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15221 if (align_good
== FAIL
)
15224 inst
.instruction
|= 1 << 4;
15227 case 2: /* VLD3 / VST3. */
15228 constraint (inst
.operands
[1].immisalign
,
15229 _("can't use alignment with this instruction"));
15232 case 3: /* VLD4 / VST4. */
15233 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15234 16, 64, 32, 64, 32, 128, -1);
15235 if (align_good
== FAIL
)
15239 unsigned alignbits
= 0;
15242 case 8: alignbits
= 0x1; break;
15243 case 16: alignbits
= 0x1; break;
15244 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15247 inst
.instruction
|= alignbits
<< 4;
15254 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15255 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15256 inst
.instruction
|= 1 << (4 + logsize
);
15258 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15259 inst
.instruction
|= logsize
<< 10;
15262 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15265 do_neon_ld_dup (void)
15267 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15268 int align_good
, do_align
= 0;
15270 if (et
.type
== NT_invtype
)
15273 switch ((inst
.instruction
>> 8) & 3)
15275 case 0: /* VLD1. */
15276 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15277 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15278 &do_align
, 16, 16, 32, 32, -1);
15279 if (align_good
== FAIL
)
15281 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15284 case 2: inst
.instruction
|= 1 << 5; break;
15285 default: first_error (_("bad list length")); return;
15287 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15290 case 1: /* VLD2. */
15291 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15292 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15293 if (align_good
== FAIL
)
15295 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15296 _("bad list length"));
15297 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15298 inst
.instruction
|= 1 << 5;
15299 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15302 case 2: /* VLD3. */
15303 constraint (inst
.operands
[1].immisalign
,
15304 _("can't use alignment with this instruction"));
15305 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15306 _("bad list length"));
15307 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15308 inst
.instruction
|= 1 << 5;
15309 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15312 case 3: /* VLD4. */
15314 int align
= inst
.operands
[1].imm
>> 8;
15315 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15316 16, 64, 32, 64, 32, 128, -1);
15317 if (align_good
== FAIL
)
15319 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15320 _("bad list length"));
15321 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15322 inst
.instruction
|= 1 << 5;
15323 if (et
.size
== 32 && align
== 128)
15324 inst
.instruction
|= 0x3 << 6;
15326 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15333 inst
.instruction
|= do_align
<< 4;
15336 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15337 apart from bits [11:4]. */
15340 do_neon_ldx_stx (void)
15342 if (inst
.operands
[1].isreg
)
15343 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15345 switch (NEON_LANE (inst
.operands
[0].imm
))
15347 case NEON_INTERLEAVE_LANES
:
15348 NEON_ENCODE (INTERLV
, inst
);
15349 do_neon_ld_st_interleave ();
15352 case NEON_ALL_LANES
:
15353 NEON_ENCODE (DUP
, inst
);
15358 NEON_ENCODE (LANE
, inst
);
15359 do_neon_ld_st_lane ();
15362 /* L bit comes from bit mask. */
15363 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15364 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15365 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15367 if (inst
.operands
[1].postind
)
15369 int postreg
= inst
.operands
[1].imm
& 0xf;
15370 constraint (!inst
.operands
[1].immisreg
,
15371 _("post-index must be a register"));
15372 constraint (postreg
== 0xd || postreg
== 0xf,
15373 _("bad register for post-index"));
15374 inst
.instruction
|= postreg
;
15376 else if (inst
.operands
[1].writeback
)
15378 inst
.instruction
|= 0xd;
15381 inst
.instruction
|= 0xf;
15384 inst
.instruction
|= 0xf9000000;
15386 inst
.instruction
|= 0xf4000000;
15389 /* Overall per-instruction processing. */
15391 /* We need to be able to fix up arbitrary expressions in some statements.
15392 This is so that we can handle symbols that are an arbitrary distance from
15393 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15394 which returns part of an address in a form which will be valid for
15395 a data instruction. We do this by pushing the expression into a symbol
15396 in the expr_section, and creating a fix for that. */
15399 fix_new_arm (fragS
* frag
,
15414 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15415 (enum bfd_reloc_code_real
) reloc
);
15419 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15420 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15424 /* Mark whether the fix is to a THUMB instruction, or an ARM
15426 new_fix
->tc_fix_data
= thumb_mode
;
15429 /* Create a frg for an instruction requiring relaxation. */
15431 output_relax_insn (void)
15437 /* The size of the instruction is unknown, so tie the debug info to the
15438 start of the instruction. */
15439 dwarf2_emit_insn (0);
15441 switch (inst
.reloc
.exp
.X_op
)
15444 sym
= inst
.reloc
.exp
.X_add_symbol
;
15445 offset
= inst
.reloc
.exp
.X_add_number
;
15449 offset
= inst
.reloc
.exp
.X_add_number
;
15452 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15456 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15457 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15458 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15461 /* Write a 32-bit thumb instruction to buf. */
15463 put_thumb32_insn (char * buf
, unsigned long insn
)
15465 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15466 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15470 output_inst (const char * str
)
15476 as_bad ("%s -- `%s'", inst
.error
, str
);
15481 output_relax_insn ();
15484 if (inst
.size
== 0)
15487 to
= frag_more (inst
.size
);
15488 /* PR 9814: Record the thumb mode into the current frag so that we know
15489 what type of NOP padding to use, if necessary. We override any previous
15490 setting so that if the mode has changed then the NOPS that we use will
15491 match the encoding of the last instruction in the frag. */
15492 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15494 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15496 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15497 put_thumb32_insn (to
, inst
.instruction
);
15499 else if (inst
.size
> INSN_SIZE
)
15501 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15502 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15503 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15506 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15508 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15509 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15510 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15513 dwarf2_emit_insn (inst
.size
);
15517 output_it_inst (int cond
, int mask
, char * to
)
15519 unsigned long instruction
= 0xbf00;
15522 instruction
|= mask
;
15523 instruction
|= cond
<< 4;
15527 to
= frag_more (2);
15529 dwarf2_emit_insn (2);
15533 md_number_to_chars (to
, instruction
, 2);
15538 /* Tag values used in struct asm_opcode's tag field. */
15541 OT_unconditional
, /* Instruction cannot be conditionalized.
15542 The ARM condition field is still 0xE. */
15543 OT_unconditionalF
, /* Instruction cannot be conditionalized
15544 and carries 0xF in its ARM condition field. */
15545 OT_csuffix
, /* Instruction takes a conditional suffix. */
15546 OT_csuffixF
, /* Some forms of the instruction take a conditional
15547 suffix, others place 0xF where the condition field
15549 OT_cinfix3
, /* Instruction takes a conditional infix,
15550 beginning at character index 3. (In
15551 unified mode, it becomes a suffix.) */
15552 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15553 tsts, cmps, cmns, and teqs. */
15554 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15555 character index 3, even in unified mode. Used for
15556 legacy instructions where suffix and infix forms
15557 may be ambiguous. */
15558 OT_csuf_or_in3
, /* Instruction takes either a conditional
15559 suffix or an infix at character index 3. */
15560 OT_odd_infix_unc
, /* This is the unconditional variant of an
15561 instruction that takes a conditional infix
15562 at an unusual position. In unified mode,
15563 this variant will accept a suffix. */
15564 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15565 are the conditional variants of instructions that
15566 take conditional infixes in unusual positions.
15567 The infix appears at character index
15568 (tag - OT_odd_infix_0). These are not accepted
15569 in unified mode. */
15572 /* Subroutine of md_assemble, responsible for looking up the primary
15573 opcode from the mnemonic the user wrote. STR points to the
15574 beginning of the mnemonic.
15576 This is not simply a hash table lookup, because of conditional
15577 variants. Most instructions have conditional variants, which are
15578 expressed with a _conditional affix_ to the mnemonic. If we were
15579 to encode each conditional variant as a literal string in the opcode
15580 table, it would have approximately 20,000 entries.
15582 Most mnemonics take this affix as a suffix, and in unified syntax,
15583 'most' is upgraded to 'all'. However, in the divided syntax, some
15584 instructions take the affix as an infix, notably the s-variants of
15585 the arithmetic instructions. Of those instructions, all but six
15586 have the infix appear after the third character of the mnemonic.
15588 Accordingly, the algorithm for looking up primary opcodes given
15591 1. Look up the identifier in the opcode table.
15592 If we find a match, go to step U.
15594 2. Look up the last two characters of the identifier in the
15595 conditions table. If we find a match, look up the first N-2
15596 characters of the identifier in the opcode table. If we
15597 find a match, go to step CE.
15599 3. Look up the fourth and fifth characters of the identifier in
15600 the conditions table. If we find a match, extract those
15601 characters from the identifier, and look up the remaining
15602 characters in the opcode table. If we find a match, go
15607 U. Examine the tag field of the opcode structure, in case this is
15608 one of the six instructions with its conditional infix in an
15609 unusual place. If it is, the tag tells us where to find the
15610 infix; look it up in the conditions table and set inst.cond
15611 accordingly. Otherwise, this is an unconditional instruction.
15612 Again set inst.cond accordingly. Return the opcode structure.
15614 CE. Examine the tag field to make sure this is an instruction that
15615 should receive a conditional suffix. If it is not, fail.
15616 Otherwise, set inst.cond from the suffix we already looked up,
15617 and return the opcode structure.
15619 CM. Examine the tag field to make sure this is an instruction that
15620 should receive a conditional infix after the third character.
15621 If it is not, fail. Otherwise, undo the edits to the current
15622 line of input and proceed as for case CE. */
15624 static const struct asm_opcode
*
15625 opcode_lookup (char **str
)
15629 const struct asm_opcode
*opcode
;
15630 const struct asm_cond
*cond
;
15633 /* Scan up to the end of the mnemonic, which must end in white space,
15634 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15635 for (base
= end
= *str
; *end
!= '\0'; end
++)
15636 if (*end
== ' ' || *end
== '.')
15642 /* Handle a possible width suffix and/or Neon type suffix. */
15647 /* The .w and .n suffixes are only valid if the unified syntax is in
15649 if (unified_syntax
&& end
[1] == 'w')
15651 else if (unified_syntax
&& end
[1] == 'n')
15656 inst
.vectype
.elems
= 0;
15658 *str
= end
+ offset
;
15660 if (end
[offset
] == '.')
15662 /* See if we have a Neon type suffix (possible in either unified or
15663 non-unified ARM syntax mode). */
15664 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15667 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15673 /* Look for unaffixed or special-case affixed mnemonic. */
15674 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15679 if (opcode
->tag
< OT_odd_infix_0
)
15681 inst
.cond
= COND_ALWAYS
;
15685 if (warn_on_deprecated
&& unified_syntax
)
15686 as_warn (_("conditional infixes are deprecated in unified syntax"));
15687 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15688 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15691 inst
.cond
= cond
->value
;
15695 /* Cannot have a conditional suffix on a mnemonic of less than two
15697 if (end
- base
< 3)
15700 /* Look for suffixed mnemonic. */
15702 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15703 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15705 if (opcode
&& cond
)
15708 switch (opcode
->tag
)
15710 case OT_cinfix3_legacy
:
15711 /* Ignore conditional suffixes matched on infix only mnemonics. */
15715 case OT_cinfix3_deprecated
:
15716 case OT_odd_infix_unc
:
15717 if (!unified_syntax
)
15719 /* else fall through */
15723 case OT_csuf_or_in3
:
15724 inst
.cond
= cond
->value
;
15727 case OT_unconditional
:
15728 case OT_unconditionalF
:
15730 inst
.cond
= cond
->value
;
15733 /* Delayed diagnostic. */
15734 inst
.error
= BAD_COND
;
15735 inst
.cond
= COND_ALWAYS
;
15744 /* Cannot have a usual-position infix on a mnemonic of less than
15745 six characters (five would be a suffix). */
15746 if (end
- base
< 6)
15749 /* Look for infixed mnemonic in the usual position. */
15751 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15755 memcpy (save
, affix
, 2);
15756 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15757 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15759 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15760 memcpy (affix
, save
, 2);
15763 && (opcode
->tag
== OT_cinfix3
15764 || opcode
->tag
== OT_cinfix3_deprecated
15765 || opcode
->tag
== OT_csuf_or_in3
15766 || opcode
->tag
== OT_cinfix3_legacy
))
15769 if (warn_on_deprecated
&& unified_syntax
15770 && (opcode
->tag
== OT_cinfix3
15771 || opcode
->tag
== OT_cinfix3_deprecated
))
15772 as_warn (_("conditional infixes are deprecated in unified syntax"));
15774 inst
.cond
= cond
->value
;
15781 /* This function generates an initial IT instruction, leaving its block
15782 virtually open for the new instructions. Eventually,
15783 the mask will be updated by now_it_add_mask () each time
15784 a new instruction needs to be included in the IT block.
15785 Finally, the block is closed with close_automatic_it_block ().
15786 The block closure can be requested either from md_assemble (),
15787 a tencode (), or due to a label hook. */
15790 new_automatic_it_block (int cond
)
15792 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15793 now_it
.mask
= 0x18;
15795 now_it
.block_length
= 1;
15796 mapping_state (MAP_THUMB
);
15797 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15800 /* Close an automatic IT block.
15801 See comments in new_automatic_it_block (). */
15804 close_automatic_it_block (void)
15806 now_it
.mask
= 0x10;
15807 now_it
.block_length
= 0;
15810 /* Update the mask of the current automatically-generated IT
15811 instruction. See comments in new_automatic_it_block (). */
15814 now_it_add_mask (int cond
)
15816 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15817 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15818 | ((bitvalue) << (nbit)))
15819 const int resulting_bit
= (cond
& 1);
15821 now_it
.mask
&= 0xf;
15822 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15824 (5 - now_it
.block_length
));
15825 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15827 ((5 - now_it
.block_length
) - 1) );
15828 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15831 #undef SET_BIT_VALUE
15834 /* The IT blocks handling machinery is accessed through the these functions:
15835 it_fsm_pre_encode () from md_assemble ()
15836 set_it_insn_type () optional, from the tencode functions
15837 set_it_insn_type_last () ditto
15838 in_it_block () ditto
15839 it_fsm_post_encode () from md_assemble ()
15840 force_automatic_it_block_close () from label habdling functions
15843 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15844 initializing the IT insn type with a generic initial value depending
15845 on the inst.condition.
15846 2) During the tencode function, two things may happen:
15847 a) The tencode function overrides the IT insn type by
15848 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15849 b) The tencode function queries the IT block state by
15850 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15852 Both set_it_insn_type and in_it_block run the internal FSM state
15853 handling function (handle_it_state), because: a) setting the IT insn
15854 type may incur in an invalid state (exiting the function),
15855 and b) querying the state requires the FSM to be updated.
15856 Specifically we want to avoid creating an IT block for conditional
15857 branches, so it_fsm_pre_encode is actually a guess and we can't
15858 determine whether an IT block is required until the tencode () routine
15859 has decided what type of instruction this actually it.
15860 Because of this, if set_it_insn_type and in_it_block have to be used,
15861 set_it_insn_type has to be called first.
15863 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15864 determines the insn IT type depending on the inst.cond code.
15865 When a tencode () routine encodes an instruction that can be
15866 either outside an IT block, or, in the case of being inside, has to be
15867 the last one, set_it_insn_type_last () will determine the proper
15868 IT instruction type based on the inst.cond code. Otherwise,
15869 set_it_insn_type can be called for overriding that logic or
15870 for covering other cases.
15872 Calling handle_it_state () may not transition the IT block state to
15873 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15874 still queried. Instead, if the FSM determines that the state should
15875 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15876 after the tencode () function: that's what it_fsm_post_encode () does.
15878 Since in_it_block () calls the state handling function to get an
15879 updated state, an error may occur (due to invalid insns combination).
15880 In that case, inst.error is set.
15881 Therefore, inst.error has to be checked after the execution of
15882 the tencode () routine.
15884 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15885 any pending state change (if any) that didn't take place in
15886 handle_it_state () as explained above. */
15889 it_fsm_pre_encode (void)
15891 if (inst
.cond
!= COND_ALWAYS
)
15892 inst
.it_insn_type
= INSIDE_IT_INSN
;
15894 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15896 now_it
.state_handled
= 0;
15899 /* IT state FSM handling function. */
15902 handle_it_state (void)
15904 now_it
.state_handled
= 1;
15906 switch (now_it
.state
)
15908 case OUTSIDE_IT_BLOCK
:
15909 switch (inst
.it_insn_type
)
15911 case OUTSIDE_IT_INSN
:
15914 case INSIDE_IT_INSN
:
15915 case INSIDE_IT_LAST_INSN
:
15916 if (thumb_mode
== 0)
15919 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15920 as_tsktsk (_("Warning: conditional outside an IT block"\
15925 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15926 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15928 /* Automatically generate the IT instruction. */
15929 new_automatic_it_block (inst
.cond
);
15930 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15931 close_automatic_it_block ();
15935 inst
.error
= BAD_OUT_IT
;
15941 case IF_INSIDE_IT_LAST_INSN
:
15942 case NEUTRAL_IT_INSN
:
15946 now_it
.state
= MANUAL_IT_BLOCK
;
15947 now_it
.block_length
= 0;
15952 case AUTOMATIC_IT_BLOCK
:
15953 /* Three things may happen now:
15954 a) We should increment current it block size;
15955 b) We should close current it block (closing insn or 4 insns);
15956 c) We should close current it block and start a new one (due
15957 to incompatible conditions or
15958 4 insns-length block reached). */
15960 switch (inst
.it_insn_type
)
15962 case OUTSIDE_IT_INSN
:
15963 /* The closure of the block shall happen immediatelly,
15964 so any in_it_block () call reports the block as closed. */
15965 force_automatic_it_block_close ();
15968 case INSIDE_IT_INSN
:
15969 case INSIDE_IT_LAST_INSN
:
15970 case IF_INSIDE_IT_LAST_INSN
:
15971 now_it
.block_length
++;
15973 if (now_it
.block_length
> 4
15974 || !now_it_compatible (inst
.cond
))
15976 force_automatic_it_block_close ();
15977 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15978 new_automatic_it_block (inst
.cond
);
15982 now_it_add_mask (inst
.cond
);
15985 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15986 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15987 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15988 close_automatic_it_block ();
15991 case NEUTRAL_IT_INSN
:
15992 now_it
.block_length
++;
15994 if (now_it
.block_length
> 4)
15995 force_automatic_it_block_close ();
15997 now_it_add_mask (now_it
.cc
& 1);
16001 close_automatic_it_block ();
16002 now_it
.state
= MANUAL_IT_BLOCK
;
16007 case MANUAL_IT_BLOCK
:
16009 /* Check conditional suffixes. */
16010 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
16013 now_it
.mask
&= 0x1f;
16014 is_last
= (now_it
.mask
== 0x10);
16016 switch (inst
.it_insn_type
)
16018 case OUTSIDE_IT_INSN
:
16019 inst
.error
= BAD_NOT_IT
;
16022 case INSIDE_IT_INSN
:
16023 if (cond
!= inst
.cond
)
16025 inst
.error
= BAD_IT_COND
;
16030 case INSIDE_IT_LAST_INSN
:
16031 case IF_INSIDE_IT_LAST_INSN
:
16032 if (cond
!= inst
.cond
)
16034 inst
.error
= BAD_IT_COND
;
16039 inst
.error
= BAD_BRANCH
;
16044 case NEUTRAL_IT_INSN
:
16045 /* The BKPT instruction is unconditional even in an IT block. */
16049 inst
.error
= BAD_IT_IT
;
16060 it_fsm_post_encode (void)
16064 if (!now_it
.state_handled
)
16065 handle_it_state ();
16067 is_last
= (now_it
.mask
== 0x10);
16070 now_it
.state
= OUTSIDE_IT_BLOCK
;
16076 force_automatic_it_block_close (void)
16078 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
16080 close_automatic_it_block ();
16081 now_it
.state
= OUTSIDE_IT_BLOCK
;
16089 if (!now_it
.state_handled
)
16090 handle_it_state ();
16092 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
16096 md_assemble (char *str
)
16099 const struct asm_opcode
* opcode
;
16101 /* Align the previous label if needed. */
16102 if (last_label_seen
!= NULL
)
16104 symbol_set_frag (last_label_seen
, frag_now
);
16105 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
16106 S_SET_SEGMENT (last_label_seen
, now_seg
);
16109 memset (&inst
, '\0', sizeof (inst
));
16110 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
16112 opcode
= opcode_lookup (&p
);
16115 /* It wasn't an instruction, but it might be a register alias of
16116 the form alias .req reg, or a Neon .dn/.qn directive. */
16117 if (! create_register_alias (str
, p
)
16118 && ! create_neon_reg_alias (str
, p
))
16119 as_bad (_("bad instruction `%s'"), str
);
16124 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
16125 as_warn (_("s suffix on comparison instruction is deprecated"));
16127 /* The value which unconditional instructions should have in place of the
16128 condition field. */
16129 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
16133 arm_feature_set variant
;
16135 variant
= cpu_variant
;
16136 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16137 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
16138 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
16139 /* Check that this instruction is supported for this CPU. */
16140 if (!opcode
->tvariant
16141 || (thumb_mode
== 1
16142 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
16144 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
16147 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
16148 && opcode
->tencode
!= do_t_branch
)
16150 as_bad (_("Thumb does not support conditional execution"));
16154 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16156 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16157 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16158 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16160 /* Two things are addressed here.
16161 1) Implicit require narrow instructions on Thumb-1.
16162 This avoids relaxation accidentally introducing Thumb-2
16164 2) Reject wide instructions in non Thumb-2 cores. */
16165 if (inst
.size_req
== 0)
16167 else if (inst
.size_req
== 4)
16169 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16175 inst
.instruction
= opcode
->tvalue
;
16177 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16179 /* Prepare the it_insn_type for those encodings that don't set
16181 it_fsm_pre_encode ();
16183 opcode
->tencode ();
16185 it_fsm_post_encode ();
16188 if (!(inst
.error
|| inst
.relax
))
16190 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16191 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16192 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16194 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16199 /* Something has gone badly wrong if we try to relax a fixed size
16201 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16203 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16204 *opcode
->tvariant
);
16205 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16206 set those bits when Thumb-2 32-bit instructions are seen. ie.
16207 anything other than bl/blx and v6-M instructions.
16208 This is overly pessimistic for relaxable instructions. */
16209 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16211 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16212 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16213 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16216 check_neon_suffixes
;
16220 mapping_state (MAP_THUMB
);
16223 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16227 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16228 is_bx
= (opcode
->aencode
== do_bx
);
16230 /* Check that this instruction is supported for this CPU. */
16231 if (!(is_bx
&& fix_v4bx
)
16232 && !(opcode
->avariant
&&
16233 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16235 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16240 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16244 inst
.instruction
= opcode
->avalue
;
16245 if (opcode
->tag
== OT_unconditionalF
)
16246 inst
.instruction
|= 0xF << 28;
16248 inst
.instruction
|= inst
.cond
<< 28;
16249 inst
.size
= INSN_SIZE
;
16250 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16252 it_fsm_pre_encode ();
16253 opcode
->aencode ();
16254 it_fsm_post_encode ();
16256 /* Arm mode bx is marked as both v4T and v5 because it's still required
16257 on a hypothetical non-thumb v5 core. */
16259 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16261 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16262 *opcode
->avariant
);
16264 check_neon_suffixes
;
16268 mapping_state (MAP_ARM
);
16273 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16281 check_it_blocks_finished (void)
16286 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16287 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16288 == MANUAL_IT_BLOCK
)
16290 as_warn (_("section '%s' finished with an open IT block."),
16294 if (now_it
.state
== MANUAL_IT_BLOCK
)
16295 as_warn (_("file finished with an open IT block."));
16299 /* Various frobbings of labels and their addresses. */
16302 arm_start_line_hook (void)
16304 last_label_seen
= NULL
;
16308 arm_frob_label (symbolS
* sym
)
16310 last_label_seen
= sym
;
16312 ARM_SET_THUMB (sym
, thumb_mode
);
16314 #if defined OBJ_COFF || defined OBJ_ELF
16315 ARM_SET_INTERWORK (sym
, support_interwork
);
16318 force_automatic_it_block_close ();
16320 /* Note - do not allow local symbols (.Lxxx) to be labelled
16321 as Thumb functions. This is because these labels, whilst
16322 they exist inside Thumb code, are not the entry points for
16323 possible ARM->Thumb calls. Also, these labels can be used
16324 as part of a computed goto or switch statement. eg gcc
16325 can generate code that looks like this:
16327 ldr r2, [pc, .Laaa]
16337 The first instruction loads the address of the jump table.
16338 The second instruction converts a table index into a byte offset.
16339 The third instruction gets the jump address out of the table.
16340 The fourth instruction performs the jump.
16342 If the address stored at .Laaa is that of a symbol which has the
16343 Thumb_Func bit set, then the linker will arrange for this address
16344 to have the bottom bit set, which in turn would mean that the
16345 address computation performed by the third instruction would end
16346 up with the bottom bit set. Since the ARM is capable of unaligned
16347 word loads, the instruction would then load the incorrect address
16348 out of the jump table, and chaos would ensue. */
16349 if (label_is_thumb_function_name
16350 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16351 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16353 /* When the address of a Thumb function is taken the bottom
16354 bit of that address should be set. This will allow
16355 interworking between Arm and Thumb functions to work
16358 THUMB_SET_FUNC (sym
, 1);
16360 label_is_thumb_function_name
= FALSE
;
16363 dwarf2_emit_label (sym
);
16367 arm_data_in_code (void)
16369 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16371 *input_line_pointer
= '/';
16372 input_line_pointer
+= 5;
16373 *input_line_pointer
= 0;
16381 arm_canonicalize_symbol_name (char * name
)
16385 if (thumb_mode
&& (len
= strlen (name
)) > 5
16386 && streq (name
+ len
- 5, "/data"))
16387 *(name
+ len
- 5) = 0;
16392 /* Table of all register names defined by default. The user can
16393 define additional names with .req. Note that all register names
16394 should appear in both upper and lowercase variants. Some registers
16395 also have mixed-case names. */
16397 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16398 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16399 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16400 #define REGSET(p,t) \
16401 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16402 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16403 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16404 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16405 #define REGSETH(p,t) \
16406 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16407 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16408 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16409 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16410 #define REGSET2(p,t) \
16411 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16412 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16413 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16414 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16415 #define SPLRBANK(base,bank,t) \
16416 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16417 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16418 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16419 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16420 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16421 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16423 static const struct reg_entry reg_names
[] =
16425 /* ARM integer registers. */
16426 REGSET(r
, RN
), REGSET(R
, RN
),
16428 /* ATPCS synonyms. */
16429 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16430 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16431 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16433 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16434 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16435 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16437 /* Well-known aliases. */
16438 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16439 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16441 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16442 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16444 /* Coprocessor numbers. */
16445 REGSET(p
, CP
), REGSET(P
, CP
),
16447 /* Coprocessor register numbers. The "cr" variants are for backward
16449 REGSET(c
, CN
), REGSET(C
, CN
),
16450 REGSET(cr
, CN
), REGSET(CR
, CN
),
16452 /* ARM banked registers. */
16453 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16454 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16455 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16456 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16457 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16458 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16459 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16461 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16462 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16463 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16464 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16465 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16466 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16467 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16468 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16470 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16471 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16472 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16473 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16474 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16475 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16476 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16477 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16478 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16480 /* FPA registers. */
16481 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16482 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16484 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16485 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16487 /* VFP SP registers. */
16488 REGSET(s
,VFS
), REGSET(S
,VFS
),
16489 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16491 /* VFP DP Registers. */
16492 REGSET(d
,VFD
), REGSET(D
,VFD
),
16493 /* Extra Neon DP registers. */
16494 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16496 /* Neon QP registers. */
16497 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16499 /* VFP control registers. */
16500 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16501 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16502 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16503 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16504 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16505 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16507 /* Maverick DSP coprocessor registers. */
16508 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16509 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16511 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16512 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16513 REGDEF(dspsc
,0,DSPSC
),
16515 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16516 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16517 REGDEF(DSPSC
,0,DSPSC
),
16519 /* iWMMXt data registers - p0, c0-15. */
16520 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16522 /* iWMMXt control registers - p1, c0-3. */
16523 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16524 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16525 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16526 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16528 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16529 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16530 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16531 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16532 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16534 /* XScale accumulator registers. */
16535 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16541 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16542 within psr_required_here. */
16543 static const struct asm_psr psrs
[] =
16545 /* Backward compatibility notation. Note that "all" is no longer
16546 truly all possible PSR bits. */
16547 {"all", PSR_c
| PSR_f
},
16551 /* Individual flags. */
16557 /* Combinations of flags. */
16558 {"fs", PSR_f
| PSR_s
},
16559 {"fx", PSR_f
| PSR_x
},
16560 {"fc", PSR_f
| PSR_c
},
16561 {"sf", PSR_s
| PSR_f
},
16562 {"sx", PSR_s
| PSR_x
},
16563 {"sc", PSR_s
| PSR_c
},
16564 {"xf", PSR_x
| PSR_f
},
16565 {"xs", PSR_x
| PSR_s
},
16566 {"xc", PSR_x
| PSR_c
},
16567 {"cf", PSR_c
| PSR_f
},
16568 {"cs", PSR_c
| PSR_s
},
16569 {"cx", PSR_c
| PSR_x
},
16570 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16571 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16572 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16573 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16574 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16575 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16576 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16577 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16578 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16579 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16580 {"scf", PSR_s
| PSR_c
| PSR_f
},
16581 {"scx", PSR_s
| PSR_c
| PSR_x
},
16582 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16583 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16584 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16585 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16586 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16587 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16588 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16589 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16590 {"csf", PSR_c
| PSR_s
| PSR_f
},
16591 {"csx", PSR_c
| PSR_s
| PSR_x
},
16592 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16593 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16594 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16595 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16596 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16597 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16598 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16599 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16600 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16601 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16602 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16603 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16604 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16605 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16606 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16607 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16608 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16609 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16610 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16611 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16612 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16613 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16614 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16615 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16616 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16617 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16620 /* Table of V7M psr names. */
16621 static const struct asm_psr v7m_psrs
[] =
16623 {"apsr", 0 }, {"APSR", 0 },
16624 {"iapsr", 1 }, {"IAPSR", 1 },
16625 {"eapsr", 2 }, {"EAPSR", 2 },
16626 {"psr", 3 }, {"PSR", 3 },
16627 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16628 {"ipsr", 5 }, {"IPSR", 5 },
16629 {"epsr", 6 }, {"EPSR", 6 },
16630 {"iepsr", 7 }, {"IEPSR", 7 },
16631 {"msp", 8 }, {"MSP", 8 },
16632 {"psp", 9 }, {"PSP", 9 },
16633 {"primask", 16}, {"PRIMASK", 16},
16634 {"basepri", 17}, {"BASEPRI", 17},
16635 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16636 {"faultmask", 19}, {"FAULTMASK", 19},
16637 {"control", 20}, {"CONTROL", 20}
16640 /* Table of all shift-in-operand names. */
16641 static const struct asm_shift_name shift_names
[] =
16643 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16644 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16645 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16646 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16647 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16648 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16651 /* Table of all explicit relocation names. */
16653 static struct reloc_entry reloc_names
[] =
16655 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16656 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16657 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16658 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16659 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16660 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16661 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16662 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16663 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16664 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16665 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16666 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
16667 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
16668 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
16669 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
16670 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
16671 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
16672 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
16676 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16677 static const struct asm_cond conds
[] =
16681 {"cs", 0x2}, {"hs", 0x2},
16682 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16696 static struct asm_barrier_opt barrier_opt_names
[] =
16698 { "sy", 0xf }, { "SY", 0xf },
16699 { "un", 0x7 }, { "UN", 0x7 },
16700 { "st", 0xe }, { "ST", 0xe },
16701 { "unst", 0x6 }, { "UNST", 0x6 },
16702 { "ish", 0xb }, { "ISH", 0xb },
16703 { "sh", 0xb }, { "SH", 0xb },
16704 { "ishst", 0xa }, { "ISHST", 0xa },
16705 { "shst", 0xa }, { "SHST", 0xa },
16706 { "nsh", 0x7 }, { "NSH", 0x7 },
16707 { "nshst", 0x6 }, { "NSHST", 0x6 },
16708 { "osh", 0x3 }, { "OSH", 0x3 },
16709 { "oshst", 0x2 }, { "OSHST", 0x2 }
16712 /* Table of ARM-format instructions. */
16714 /* Macros for gluing together operand strings. N.B. In all cases
16715 other than OPS0, the trailing OP_stop comes from default
16716 zero-initialization of the unspecified elements of the array. */
16717 #define OPS0() { OP_stop, }
16718 #define OPS1(a) { OP_##a, }
16719 #define OPS2(a,b) { OP_##a,OP_##b, }
16720 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16721 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16722 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16723 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16725 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16726 This is useful when mixing operands for ARM and THUMB, i.e. using the
16727 MIX_ARM_THUMB_OPERANDS macro.
16728 In order to use these macros, prefix the number of operands with _
16730 #define OPS_1(a) { a, }
16731 #define OPS_2(a,b) { a,b, }
16732 #define OPS_3(a,b,c) { a,b,c, }
16733 #define OPS_4(a,b,c,d) { a,b,c,d, }
16734 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16735 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16737 /* These macros abstract out the exact format of the mnemonic table and
16738 save some repeated characters. */
16740 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16741 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16742 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16743 THUMB_VARIANT, do_##ae, do_##te }
16745 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16746 a T_MNEM_xyz enumerator. */
16747 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16748 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16749 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16750 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16752 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16753 infix after the third character. */
16754 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16755 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16756 THUMB_VARIANT, do_##ae, do_##te }
16757 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16758 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16759 THUMB_VARIANT, do_##ae, do_##te }
16760 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16761 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16762 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16763 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16764 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16765 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16766 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16767 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16769 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16770 appear in the condition table. */
16771 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16772 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16773 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16775 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16776 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16777 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16778 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16779 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16780 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16781 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16782 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16783 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16784 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16785 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16786 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16787 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16788 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16789 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16790 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16791 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16792 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16793 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16794 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16796 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16797 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16798 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16799 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16801 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16802 field is still 0xE. Many of the Thumb variants can be executed
16803 conditionally, so this is checked separately. */
16804 #define TUE(mnem, op, top, nops, ops, ae, te) \
16805 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16806 THUMB_VARIANT, do_##ae, do_##te }
16808 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16809 condition code field. */
16810 #define TUF(mnem, op, top, nops, ops, ae, te) \
16811 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16812 THUMB_VARIANT, do_##ae, do_##te }
16814 /* ARM-only variants of all the above. */
16815 #define CE(mnem, op, nops, ops, ae) \
16816 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16818 #define C3(mnem, op, nops, ops, ae) \
16819 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16821 /* Legacy mnemonics that always have conditional infix after the third
16823 #define CL(mnem, op, nops, ops, ae) \
16824 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16825 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16827 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16828 #define cCE(mnem, op, nops, ops, ae) \
16829 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16831 /* Legacy coprocessor instructions where conditional infix and conditional
16832 suffix are ambiguous. For consistency this includes all FPA instructions,
16833 not just the potentially ambiguous ones. */
16834 #define cCL(mnem, op, nops, ops, ae) \
16835 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16836 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16838 /* Coprocessor, takes either a suffix or a position-3 infix
16839 (for an FPA corner case). */
16840 #define C3E(mnem, op, nops, ops, ae) \
16841 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16842 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16844 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16845 { m1 #m2 m3, OPS##nops ops, \
16846 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16847 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16849 #define CM(m1, m2, op, nops, ops, ae) \
16850 xCM_ (m1, , m2, op, nops, ops, ae), \
16851 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16852 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16853 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16854 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16855 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16856 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16857 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16858 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16859 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16860 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16861 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16862 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16863 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16864 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16865 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16866 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16867 xCM_ (m1, le, m2, op, nops, ops, ae), \
16868 xCM_ (m1, al, m2, op, nops, ops, ae)
16870 #define UE(mnem, op, nops, ops, ae) \
16871 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16873 #define UF(mnem, op, nops, ops, ae) \
16874 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16876 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16877 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16878 use the same encoding function for each. */
16879 #define NUF(mnem, op, nops, ops, enc) \
16880 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16881 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16883 /* Neon data processing, version which indirects through neon_enc_tab for
16884 the various overloaded versions of opcodes. */
16885 #define nUF(mnem, op, nops, ops, enc) \
16886 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16887 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16889 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16891 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16892 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16893 THUMB_VARIANT, do_##enc, do_##enc }
16895 #define NCE(mnem, op, nops, ops, enc) \
16896 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16898 #define NCEF(mnem, op, nops, ops, enc) \
16899 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16901 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16902 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16903 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16904 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16906 #define nCE(mnem, op, nops, ops, enc) \
16907 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16909 #define nCEF(mnem, op, nops, ops, enc) \
16910 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16914 static const struct asm_opcode insns
[] =
16916 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16917 #define THUMB_VARIANT &arm_ext_v4t
16918 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16919 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16920 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16921 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16922 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16923 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16924 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16925 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16926 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16927 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16928 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16929 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16930 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16931 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16932 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16933 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16935 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16936 for setting PSR flag bits. They are obsolete in V6 and do not
16937 have Thumb equivalents. */
16938 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16939 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16940 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16941 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16942 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16943 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16944 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16945 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16946 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16948 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16949 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16950 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16951 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16953 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16954 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16955 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16957 OP_ADDRGLDR
),ldst
, t_ldst
),
16958 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16960 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16961 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16962 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16963 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16964 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16965 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16967 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16968 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16969 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16970 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16973 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16974 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16975 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16977 /* Thumb-compatibility pseudo ops. */
16978 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16979 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16980 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16981 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16982 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16983 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16984 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16985 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16986 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16987 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16988 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16989 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16991 /* These may simplify to neg. */
16992 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16993 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16995 #undef THUMB_VARIANT
16996 #define THUMB_VARIANT & arm_ext_v6
16998 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
17000 /* V1 instructions with no Thumb analogue prior to V6T2. */
17001 #undef THUMB_VARIANT
17002 #define THUMB_VARIANT & arm_ext_v6t2
17004 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17005 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17006 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
17008 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17009 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17010 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
17011 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17013 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17014 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17016 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17017 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17019 /* V1 instructions with no Thumb analogue at all. */
17020 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
17021 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
17023 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17024 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17025 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17026 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17027 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17028 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17029 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17030 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17033 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17034 #undef THUMB_VARIANT
17035 #define THUMB_VARIANT & arm_ext_v4t
17037 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17038 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17040 #undef THUMB_VARIANT
17041 #define THUMB_VARIANT & arm_ext_v6t2
17043 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17044 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
17046 /* Generic coprocessor instructions. */
17047 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17048 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17049 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17050 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17051 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17052 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17053 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17056 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17058 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17059 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17062 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17063 #undef THUMB_VARIANT
17064 #define THUMB_VARIANT & arm_ext_msr
17066 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
17067 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
17070 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17071 #undef THUMB_VARIANT
17072 #define THUMB_VARIANT & arm_ext_v6t2
17074 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17075 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17076 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17077 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17078 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17079 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17080 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17081 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17084 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17085 #undef THUMB_VARIANT
17086 #define THUMB_VARIANT & arm_ext_v4t
17088 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17089 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17090 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17091 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17092 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17093 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17096 #define ARM_VARIANT & arm_ext_v4t_5
17098 /* ARM Architecture 4T. */
17099 /* Note: bx (and blx) are required on V5, even if the processor does
17100 not support Thumb. */
17101 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
17104 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17105 #undef THUMB_VARIANT
17106 #define THUMB_VARIANT & arm_ext_v5t
17108 /* Note: blx has 2 variants; the .value coded here is for
17109 BLX(2). Only this variant has conditional execution. */
17110 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
17111 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
17113 #undef THUMB_VARIANT
17114 #define THUMB_VARIANT & arm_ext_v6t2
17116 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
17117 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17118 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17119 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17120 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17121 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17122 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17123 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17126 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17127 #undef THUMB_VARIANT
17128 #define THUMB_VARIANT &arm_ext_v5exp
17130 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17131 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17132 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17133 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17135 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17136 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17138 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17139 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17140 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17141 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17143 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17144 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17145 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17146 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17148 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17149 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17151 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17152 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17153 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17154 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17157 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17158 #undef THUMB_VARIANT
17159 #define THUMB_VARIANT &arm_ext_v6t2
17161 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17162 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17164 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17165 ADDRGLDRS
), ldrd
, t_ldstd
),
17167 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17168 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17171 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17173 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17176 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17177 #undef THUMB_VARIANT
17178 #define THUMB_VARIANT & arm_ext_v6
17180 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17181 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17182 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17183 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17184 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17185 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17186 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17187 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17188 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17189 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17191 #undef THUMB_VARIANT
17192 #define THUMB_VARIANT & arm_ext_v6t2
17194 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17195 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17197 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17198 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17200 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17201 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17203 /* ARM V6 not included in V7M. */
17204 #undef THUMB_VARIANT
17205 #define THUMB_VARIANT & arm_ext_v6_notm
17206 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17207 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17208 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17209 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17210 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17211 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17212 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17213 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17214 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17215 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17216 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17217 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17219 /* ARM V6 not included in V7M (eg. integer SIMD). */
17220 #undef THUMB_VARIANT
17221 #define THUMB_VARIANT & arm_ext_v6_dsp
17222 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17223 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17224 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17225 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17226 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17227 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17228 /* Old name for QASX. */
17229 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17230 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17231 /* Old name for QSAX. */
17232 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17233 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17234 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17235 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17236 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17237 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17238 /* Old name for SASX. */
17239 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17240 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17241 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17242 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17243 /* Old name for SHASX. */
17244 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17245 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17246 /* Old name for SHSAX. */
17247 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17248 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17249 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17250 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17251 /* Old name for SSAX. */
17252 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17253 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17254 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17255 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17256 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17257 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17258 /* Old name for UASX. */
17259 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17260 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17261 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17262 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17263 /* Old name for UHASX. */
17264 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17265 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17266 /* Old name for UHSAX. */
17267 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17268 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17269 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17270 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17271 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17272 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17273 /* Old name for UQASX. */
17274 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17275 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17276 /* Old name for UQSAX. */
17277 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17278 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17279 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17280 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17281 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17282 /* Old name for USAX. */
17283 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17284 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17285 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17286 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17287 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17288 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17289 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17290 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17291 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17292 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17293 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17294 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17295 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17296 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17297 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17298 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17299 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17300 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17301 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17302 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17303 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17304 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17305 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17306 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17307 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17308 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17309 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17310 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17311 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17312 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17313 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17314 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17315 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17316 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17319 #define ARM_VARIANT & arm_ext_v6k
17320 #undef THUMB_VARIANT
17321 #define THUMB_VARIANT & arm_ext_v6k
17323 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17324 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17325 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17326 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17328 #undef THUMB_VARIANT
17329 #define THUMB_VARIANT & arm_ext_v6_notm
17330 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17332 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17333 RRnpcb
), strexd
, t_strexd
),
17335 #undef THUMB_VARIANT
17336 #define THUMB_VARIANT & arm_ext_v6t2
17337 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17339 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17341 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17343 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17345 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17348 #define ARM_VARIANT & arm_ext_sec
17349 #undef THUMB_VARIANT
17350 #define THUMB_VARIANT & arm_ext_sec
17352 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17355 #define ARM_VARIANT & arm_ext_virt
17356 #undef THUMB_VARIANT
17357 #define THUMB_VARIANT & arm_ext_virt
17359 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17360 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17363 #define ARM_VARIANT & arm_ext_v6t2
17364 #undef THUMB_VARIANT
17365 #define THUMB_VARIANT & arm_ext_v6t2
17367 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17368 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17369 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17370 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17372 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17373 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17374 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17375 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17377 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17378 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17379 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17380 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17382 /* Thumb-only instructions. */
17384 #define ARM_VARIANT NULL
17385 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17386 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17388 /* ARM does not really have an IT instruction, so always allow it.
17389 The opcode is copied from Thumb in order to allow warnings in
17390 -mimplicit-it=[never | arm] modes. */
17392 #define ARM_VARIANT & arm_ext_v1
17394 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17395 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17396 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17397 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17398 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17399 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17400 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17401 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17402 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17403 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17404 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17405 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17406 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17407 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17408 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17409 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17410 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17411 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17413 /* Thumb2 only instructions. */
17415 #define ARM_VARIANT NULL
17417 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17418 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17419 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17420 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17421 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17422 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17424 /* Hardware division instructions. */
17426 #define ARM_VARIANT & arm_ext_adiv
17427 #undef THUMB_VARIANT
17428 #define THUMB_VARIANT & arm_ext_div
17430 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17431 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17433 /* ARM V6M/V7 instructions. */
17435 #define ARM_VARIANT & arm_ext_barrier
17436 #undef THUMB_VARIANT
17437 #define THUMB_VARIANT & arm_ext_barrier
17439 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17440 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17441 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17443 /* ARM V7 instructions. */
17445 #define ARM_VARIANT & arm_ext_v7
17446 #undef THUMB_VARIANT
17447 #define THUMB_VARIANT & arm_ext_v7
17449 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17450 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17453 #define ARM_VARIANT & arm_ext_mp
17454 #undef THUMB_VARIANT
17455 #define THUMB_VARIANT & arm_ext_mp
17457 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17460 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17462 cCE("wfs", e200110
, 1, (RR
), rd
),
17463 cCE("rfs", e300110
, 1, (RR
), rd
),
17464 cCE("wfc", e400110
, 1, (RR
), rd
),
17465 cCE("rfc", e500110
, 1, (RR
), rd
),
17467 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17468 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17469 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17470 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17472 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17473 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17474 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17475 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17477 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17478 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17479 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17480 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17481 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17482 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17483 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17484 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17485 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17486 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17487 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17488 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17490 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17491 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17492 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17493 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17494 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17495 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17496 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17497 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17498 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17499 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17500 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17501 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17503 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17504 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17505 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17506 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17507 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17508 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17509 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17510 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17511 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17512 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17513 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17514 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17516 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17517 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17518 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17519 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17520 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17521 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17522 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17523 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17524 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17525 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17526 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17527 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17529 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17530 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17531 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17532 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17533 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17534 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17535 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17536 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17537 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17538 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17539 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17540 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17542 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17543 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17544 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17545 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17546 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17547 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17548 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17549 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17550 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17551 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17552 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17553 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17555 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17556 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17557 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17558 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17559 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17560 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17561 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17562 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17563 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17564 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17565 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17566 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17568 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17569 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17570 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17571 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17572 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17573 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17574 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17575 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17576 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17577 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17578 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17579 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17581 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17582 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17583 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17584 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17585 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17586 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17587 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17588 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17589 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17590 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17591 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17592 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17594 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17595 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17596 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17597 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17598 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17599 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17600 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17601 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17602 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17603 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17604 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17605 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17607 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17608 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17609 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17610 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17611 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17612 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17613 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17614 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17615 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17616 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17617 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17618 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17620 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17621 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17622 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17623 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17624 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17625 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17626 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17627 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17628 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17629 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17630 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17631 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17633 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17634 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17635 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17636 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17637 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17638 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17639 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17640 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17641 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17642 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17643 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17644 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17646 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17647 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17648 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17649 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17650 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17651 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17652 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17653 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17654 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17655 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17656 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17657 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17659 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17660 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17661 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17662 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17663 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17664 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17665 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17666 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17667 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17668 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17669 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17670 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17672 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17673 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17674 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17675 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17676 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17677 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17678 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17679 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17680 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17681 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17682 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17683 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17685 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17686 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17687 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17688 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17689 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17690 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17691 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17692 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17693 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17694 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17695 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17696 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17698 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17699 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17700 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17701 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17702 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17703 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17704 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17705 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17706 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17707 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17708 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17709 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17711 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17712 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17713 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17714 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17715 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17716 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17717 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17718 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17719 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17720 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17721 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17722 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17724 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17725 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17726 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17727 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17728 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17729 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17730 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17731 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17732 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17733 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17734 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17735 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17737 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17738 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17739 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17740 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17741 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17742 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17743 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17744 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17745 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17746 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17747 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17748 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17750 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17751 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17752 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17753 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17754 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17755 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17756 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17757 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17758 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17759 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17760 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17761 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17763 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17764 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17765 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17766 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17767 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17768 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17769 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17770 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17771 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17772 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17773 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17774 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17776 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17777 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17778 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17779 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17780 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17781 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17782 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17783 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17784 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17785 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17786 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17787 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17789 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17790 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17791 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17792 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17793 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17794 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17795 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17796 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17797 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17798 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17799 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17800 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17802 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17803 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17804 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17805 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17806 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17807 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17808 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17809 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17810 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17811 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17812 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17813 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17815 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17816 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17817 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17818 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17819 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17820 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17821 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17822 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17823 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17824 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17825 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17826 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17828 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17829 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17830 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17831 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17832 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17833 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17834 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17835 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17836 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17837 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17838 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17839 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17841 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17842 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17843 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17844 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17845 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17846 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17847 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17848 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17849 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17850 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17851 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17852 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17854 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17855 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17856 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17857 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17859 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17860 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17861 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17862 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17863 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17864 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17865 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17866 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17867 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17868 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17869 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17870 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17872 /* The implementation of the FIX instruction is broken on some
17873 assemblers, in that it accepts a precision specifier as well as a
17874 rounding specifier, despite the fact that this is meaningless.
17875 To be more compatible, we accept it as well, though of course it
17876 does not set any bits. */
17877 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17878 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17879 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17880 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17881 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17882 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17883 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17884 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17885 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17886 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17887 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17888 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17889 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17891 /* Instructions that were new with the real FPA, call them V2. */
17893 #define ARM_VARIANT & fpu_fpa_ext_v2
17895 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17896 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17897 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17898 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17899 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17900 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17903 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17905 /* Moves and type conversions. */
17906 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17907 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17908 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17909 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17910 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17911 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17912 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17913 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17914 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17915 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17916 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17917 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17918 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17919 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17921 /* Memory operations. */
17922 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17923 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17924 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17925 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17926 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17927 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17928 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17929 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17930 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17931 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17932 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17933 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17934 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17935 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17936 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17937 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17938 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17939 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17941 /* Monadic operations. */
17942 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17943 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17944 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17946 /* Dyadic operations. */
17947 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17948 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17949 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17950 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17951 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17952 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17953 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17954 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17955 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17958 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17959 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17960 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17961 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17963 /* Double precision load/store are still present on single precision
17964 implementations. */
17965 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17966 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17967 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17968 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17969 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17970 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17971 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17972 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17973 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17974 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17977 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17979 /* Moves and type conversions. */
17980 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17981 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17982 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17983 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17984 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17985 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17986 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17987 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17988 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17989 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17990 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17991 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17992 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17994 /* Monadic operations. */
17995 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17996 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17997 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17999 /* Dyadic operations. */
18000 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18001 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18002 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18003 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18004 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18005 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18006 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18007 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18008 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18011 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18012 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
18013 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18014 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
18017 #define ARM_VARIANT & fpu_vfp_ext_v2
18019 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
18020 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
18021 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
18022 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
18024 /* Instructions which may belong to either the Neon or VFP instruction sets.
18025 Individual encoder functions perform additional architecture checks. */
18027 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18028 #undef THUMB_VARIANT
18029 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18031 /* These mnemonics are unique to VFP. */
18032 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
18033 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
18034 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18035 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18036 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18037 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18038 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18039 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
18040 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
18041 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
18043 /* Mnemonics shared by Neon and VFP. */
18044 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
18045 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18046 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18048 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18049 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18051 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18052 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18054 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18055 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18056 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18057 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18058 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18059 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18060 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18061 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18063 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
18064 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
18065 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
18066 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
18069 /* NOTE: All VMOV encoding is special-cased! */
18070 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
18071 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
18073 #undef THUMB_VARIANT
18074 #define THUMB_VARIANT & fpu_neon_ext_v1
18076 #define ARM_VARIANT & fpu_neon_ext_v1
18078 /* Data processing with three registers of the same length. */
18079 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18080 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
18081 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
18082 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18083 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18084 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18085 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18086 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18087 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18088 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18089 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18090 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18091 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18092 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18093 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18094 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18095 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18096 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18097 /* If not immediate, fall back to neon_dyadic_i64_su.
18098 shl_imm should accept I8 I16 I32 I64,
18099 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18100 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
18101 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
18102 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
18103 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
18104 /* Logic ops, types optional & ignored. */
18105 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18106 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18107 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18108 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18109 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18110 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18111 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18112 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18113 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
18114 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
18115 /* Bitfield ops, untyped. */
18116 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18117 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18118 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18119 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18120 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18121 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18122 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18123 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18124 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18125 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18126 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18127 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18128 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18129 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18130 back to neon_dyadic_if_su. */
18131 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18132 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18133 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18134 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18135 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18136 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18137 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18138 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18139 /* Comparison. Type I8 I16 I32 F32. */
18140 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
18141 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
18142 /* As above, D registers only. */
18143 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18144 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18145 /* Int and float variants, signedness unimportant. */
18146 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18147 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18148 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
18149 /* Add/sub take types I8 I16 I32 I64 F32. */
18150 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18151 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18152 /* vtst takes sizes 8, 16, 32. */
18153 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18154 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18155 /* VMUL takes I8 I16 I32 F32 P8. */
18156 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18157 /* VQD{R}MULH takes S16 S32. */
18158 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18159 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18160 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18161 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18162 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18163 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18164 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18165 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18166 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18167 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18168 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18169 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18170 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18171 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18172 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18173 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18175 /* Two address, int/float. Types S8 S16 S32 F32. */
18176 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18177 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18179 /* Data processing with two registers and a shift amount. */
18180 /* Right shifts, and variants with rounding.
18181 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18182 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18183 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18184 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18185 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18186 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18187 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18188 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18189 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18190 /* Shift and insert. Sizes accepted 8 16 32 64. */
18191 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18192 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18193 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18194 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18195 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18196 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18197 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18198 /* Right shift immediate, saturating & narrowing, with rounding variants.
18199 Types accepted S16 S32 S64 U16 U32 U64. */
18200 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18201 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18202 /* As above, unsigned. Types accepted S16 S32 S64. */
18203 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18204 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18205 /* Right shift narrowing. Types accepted I16 I32 I64. */
18206 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18207 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18208 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18209 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18210 /* CVT with optional immediate for fixed-point variant. */
18211 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18213 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18214 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18216 /* Data processing, three registers of different lengths. */
18217 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18218 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18219 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18220 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18221 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18222 /* If not scalar, fall back to neon_dyadic_long.
18223 Vector types as above, scalar types S16 S32 U16 U32. */
18224 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18225 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18226 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18227 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18228 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18229 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18230 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18231 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18232 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18233 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18234 /* Saturating doubling multiplies. Types S16 S32. */
18235 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18236 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18237 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18238 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18239 S16 S32 U16 U32. */
18240 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18242 /* Extract. Size 8. */
18243 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18244 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18246 /* Two registers, miscellaneous. */
18247 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18248 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18249 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18250 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18251 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18252 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18253 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18254 /* Vector replicate. Sizes 8 16 32. */
18255 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18256 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18257 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18258 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18259 /* VMOVN. Types I16 I32 I64. */
18260 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18261 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18262 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18263 /* VQMOVUN. Types S16 S32 S64. */
18264 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18265 /* VZIP / VUZP. Sizes 8 16 32. */
18266 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18267 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18268 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18269 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18270 /* VQABS / VQNEG. Types S8 S16 S32. */
18271 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18272 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18273 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18274 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18275 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18276 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18277 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18278 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18279 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18280 /* Reciprocal estimates. Types U32 F32. */
18281 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18282 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18283 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18284 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18285 /* VCLS. Types S8 S16 S32. */
18286 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18287 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18288 /* VCLZ. Types I8 I16 I32. */
18289 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18290 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18291 /* VCNT. Size 8. */
18292 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18293 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18294 /* Two address, untyped. */
18295 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18296 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18297 /* VTRN. Sizes 8 16 32. */
18298 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18299 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18301 /* Table lookup. Size 8. */
18302 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18303 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18305 #undef THUMB_VARIANT
18306 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18308 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18310 /* Neon element/structure load/store. */
18311 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18312 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18313 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18314 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18315 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18316 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18317 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18318 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18320 #undef THUMB_VARIANT
18321 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18323 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18324 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18325 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18326 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18327 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18328 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18329 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18330 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18331 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18332 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18334 #undef THUMB_VARIANT
18335 #define THUMB_VARIANT & fpu_vfp_ext_v3
18337 #define ARM_VARIANT & fpu_vfp_ext_v3
18339 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18340 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18341 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18342 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18343 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18344 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18345 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18346 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18347 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18350 #define ARM_VARIANT &fpu_vfp_ext_fma
18351 #undef THUMB_VARIANT
18352 #define THUMB_VARIANT &fpu_vfp_ext_fma
18353 /* Mnemonics shared by Neon and VFP. These are included in the
18354 VFP FMA variant; NEON and VFP FMA always includes the NEON
18355 FMA instructions. */
18356 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18357 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18358 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18359 the v form should always be used. */
18360 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18361 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18362 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18363 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18364 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18365 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18367 #undef THUMB_VARIANT
18369 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18371 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18372 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18373 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18374 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18375 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18376 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18377 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18378 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18381 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18383 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18384 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18385 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18386 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18387 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18388 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18389 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18390 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18391 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18392 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18393 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18394 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18395 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18396 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18397 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18398 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18399 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18400 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18401 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18402 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18403 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18404 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18405 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18406 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18407 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18408 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18409 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18410 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18411 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18412 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18413 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18414 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18415 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18416 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18417 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18418 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18419 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18420 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18421 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18422 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18423 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18424 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18425 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18426 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18427 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18428 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18429 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18430 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18431 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18432 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18433 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18434 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18435 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18436 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18437 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18438 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18439 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18440 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18441 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18442 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18443 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18444 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18445 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18446 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18447 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18448 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18449 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18450 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18451 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18452 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18453 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18454 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18455 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18456 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18457 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18458 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18459 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18460 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18461 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18462 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18463 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18464 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18465 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18466 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18467 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18468 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18469 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18470 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18471 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18472 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18473 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18474 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18475 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18476 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18477 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18478 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18479 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18480 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18481 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18482 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18483 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18484 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18485 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18486 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18487 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18488 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18489 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18490 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18491 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18492 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18493 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18494 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18495 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18496 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18497 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18498 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18499 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18500 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18501 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18502 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18503 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18504 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18505 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18506 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18507 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18508 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18509 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18510 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18511 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18512 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18513 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18514 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18515 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18516 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18517 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18518 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18519 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18520 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18521 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18522 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18523 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18524 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18525 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18526 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18527 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18528 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18529 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18530 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18531 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18532 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18533 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18534 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18535 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18536 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18537 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18538 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18539 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18540 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18541 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18542 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18543 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18544 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18547 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18549 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18550 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18551 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18552 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18553 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18554 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18555 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18556 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18557 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18558 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18559 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18560 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18561 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18562 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18563 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18564 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18565 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18566 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18567 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18568 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18569 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18570 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18571 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18572 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18573 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18574 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18575 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18576 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18577 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18578 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18579 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18580 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18581 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18582 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18583 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18584 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18585 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18586 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18587 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18588 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18589 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18590 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18591 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18592 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18593 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18594 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18595 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18596 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18597 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18598 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18599 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18600 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18601 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18602 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18603 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18604 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18605 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18608 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18610 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18611 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18612 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18613 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18614 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18615 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18616 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18617 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18618 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18619 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18620 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18621 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18622 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18623 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18624 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18625 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18626 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18627 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18628 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18629 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18630 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18631 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18632 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18633 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18634 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18635 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18636 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18637 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18638 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18639 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18640 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18641 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18642 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18643 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18644 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18645 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18646 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18647 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18648 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18649 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18650 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18651 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18652 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18653 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18654 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18655 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18656 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18657 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18658 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18659 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18660 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18661 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18662 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18663 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18664 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18665 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18666 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18667 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18668 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18669 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18670 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18671 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18672 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18673 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18674 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18675 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18676 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18677 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18678 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18679 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18680 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18681 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18682 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18683 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18684 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18685 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18688 #undef THUMB_VARIANT
18715 /* MD interface: bits in the object file. */
18717 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18718 for use in the a.out file, and stores them in the array pointed to by buf.
18719 This knows about the endian-ness of the target machine and does
18720 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18721 2 (short) and 4 (long) Floating numbers are put out as a series of
18722 LITTLENUMS (shorts, here at least). */
18725 md_number_to_chars (char * buf
, valueT val
, int n
)
18727 if (target_big_endian
)
18728 number_to_chars_bigendian (buf
, val
, n
);
18730 number_to_chars_littleendian (buf
, val
, n
);
18734 md_chars_to_number (char * buf
, int n
)
18737 unsigned char * where
= (unsigned char *) buf
;
18739 if (target_big_endian
)
18744 result
|= (*where
++ & 255);
18752 result
|= (where
[n
] & 255);
18759 /* MD interface: Sections. */
18761 /* Estimate the size of a frag before relaxing. Assume everything fits in
18765 md_estimate_size_before_relax (fragS
* fragp
,
18766 segT segtype ATTRIBUTE_UNUSED
)
18772 /* Convert a machine dependent frag. */
18775 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18777 unsigned long insn
;
18778 unsigned long old_op
;
18786 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18788 old_op
= bfd_get_16(abfd
, buf
);
18789 if (fragp
->fr_symbol
)
18791 exp
.X_op
= O_symbol
;
18792 exp
.X_add_symbol
= fragp
->fr_symbol
;
18796 exp
.X_op
= O_constant
;
18798 exp
.X_add_number
= fragp
->fr_offset
;
18799 opcode
= fragp
->fr_subtype
;
18802 case T_MNEM_ldr_pc
:
18803 case T_MNEM_ldr_pc2
:
18804 case T_MNEM_ldr_sp
:
18805 case T_MNEM_str_sp
:
18812 if (fragp
->fr_var
== 4)
18814 insn
= THUMB_OP32 (opcode
);
18815 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18817 insn
|= (old_op
& 0x700) << 4;
18821 insn
|= (old_op
& 7) << 12;
18822 insn
|= (old_op
& 0x38) << 13;
18824 insn
|= 0x00000c00;
18825 put_thumb32_insn (buf
, insn
);
18826 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18830 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18832 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18835 if (fragp
->fr_var
== 4)
18837 insn
= THUMB_OP32 (opcode
);
18838 insn
|= (old_op
& 0xf0) << 4;
18839 put_thumb32_insn (buf
, insn
);
18840 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18844 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18845 exp
.X_add_number
-= 4;
18853 if (fragp
->fr_var
== 4)
18855 int r0off
= (opcode
== T_MNEM_mov
18856 || opcode
== T_MNEM_movs
) ? 0 : 8;
18857 insn
= THUMB_OP32 (opcode
);
18858 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18859 insn
|= (old_op
& 0x700) << r0off
;
18860 put_thumb32_insn (buf
, insn
);
18861 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18865 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18870 if (fragp
->fr_var
== 4)
18872 insn
= THUMB_OP32(opcode
);
18873 put_thumb32_insn (buf
, insn
);
18874 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18877 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18881 if (fragp
->fr_var
== 4)
18883 insn
= THUMB_OP32(opcode
);
18884 insn
|= (old_op
& 0xf00) << 14;
18885 put_thumb32_insn (buf
, insn
);
18886 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18889 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18892 case T_MNEM_add_sp
:
18893 case T_MNEM_add_pc
:
18894 case T_MNEM_inc_sp
:
18895 case T_MNEM_dec_sp
:
18896 if (fragp
->fr_var
== 4)
18898 /* ??? Choose between add and addw. */
18899 insn
= THUMB_OP32 (opcode
);
18900 insn
|= (old_op
& 0xf0) << 4;
18901 put_thumb32_insn (buf
, insn
);
18902 if (opcode
== T_MNEM_add_pc
)
18903 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18905 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18908 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18916 if (fragp
->fr_var
== 4)
18918 insn
= THUMB_OP32 (opcode
);
18919 insn
|= (old_op
& 0xf0) << 4;
18920 insn
|= (old_op
& 0xf) << 16;
18921 put_thumb32_insn (buf
, insn
);
18922 if (insn
& (1 << 20))
18923 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18925 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18928 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18934 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18935 (enum bfd_reloc_code_real
) reloc_type
);
18936 fixp
->fx_file
= fragp
->fr_file
;
18937 fixp
->fx_line
= fragp
->fr_line
;
18938 fragp
->fr_fix
+= fragp
->fr_var
;
18941 /* Return the size of a relaxable immediate operand instruction.
18942 SHIFT and SIZE specify the form of the allowable immediate. */
18944 relax_immediate (fragS
*fragp
, int size
, int shift
)
18950 /* ??? Should be able to do better than this. */
18951 if (fragp
->fr_symbol
)
18954 low
= (1 << shift
) - 1;
18955 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18956 offset
= fragp
->fr_offset
;
18957 /* Force misaligned offsets to 32-bit variant. */
18960 if (offset
& ~mask
)
18965 /* Get the address of a symbol during relaxation. */
18967 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18973 sym
= fragp
->fr_symbol
;
18974 sym_frag
= symbol_get_frag (sym
);
18975 know (S_GET_SEGMENT (sym
) != absolute_section
18976 || sym_frag
== &zero_address_frag
);
18977 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18979 /* If frag has yet to be reached on this pass, assume it will
18980 move by STRETCH just as we did. If this is not so, it will
18981 be because some frag between grows, and that will force
18985 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18989 /* Adjust stretch for any alignment frag. Note that if have
18990 been expanding the earlier code, the symbol may be
18991 defined in what appears to be an earlier frag. FIXME:
18992 This doesn't handle the fr_subtype field, which specifies
18993 a maximum number of bytes to skip when doing an
18995 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18997 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
19000 stretch
= - ((- stretch
)
19001 & ~ ((1 << (int) f
->fr_offset
) - 1));
19003 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
19015 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19018 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
19023 /* Assume worst case for symbols not known to be in the same section. */
19024 if (fragp
->fr_symbol
== NULL
19025 || !S_IS_DEFINED (fragp
->fr_symbol
)
19026 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19027 || S_IS_WEAK (fragp
->fr_symbol
))
19030 val
= relaxed_symbol_addr (fragp
, stretch
);
19031 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
19032 addr
= (addr
+ 4) & ~3;
19033 /* Force misaligned targets to 32-bit variant. */
19037 if (val
< 0 || val
> 1020)
19042 /* Return the size of a relaxable add/sub immediate instruction. */
19044 relax_addsub (fragS
*fragp
, asection
*sec
)
19049 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19050 op
= bfd_get_16(sec
->owner
, buf
);
19051 if ((op
& 0xf) == ((op
>> 4) & 0xf))
19052 return relax_immediate (fragp
, 8, 0);
19054 return relax_immediate (fragp
, 3, 0);
19058 /* Return the size of a relaxable branch instruction. BITS is the
19059 size of the offset field in the narrow instruction. */
19062 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
19068 /* Assume worst case for symbols not known to be in the same section. */
19069 if (!S_IS_DEFINED (fragp
->fr_symbol
)
19070 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19071 || S_IS_WEAK (fragp
->fr_symbol
))
19075 if (S_IS_DEFINED (fragp
->fr_symbol
)
19076 && ARM_IS_FUNC (fragp
->fr_symbol
))
19080 val
= relaxed_symbol_addr (fragp
, stretch
);
19081 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
19084 /* Offset is a signed value *2 */
19086 if (val
>= limit
|| val
< -limit
)
19092 /* Relax a machine dependent frag. This returns the amount by which
19093 the current size of the frag should change. */
19096 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
19101 oldsize
= fragp
->fr_var
;
19102 switch (fragp
->fr_subtype
)
19104 case T_MNEM_ldr_pc2
:
19105 newsize
= relax_adr (fragp
, sec
, stretch
);
19107 case T_MNEM_ldr_pc
:
19108 case T_MNEM_ldr_sp
:
19109 case T_MNEM_str_sp
:
19110 newsize
= relax_immediate (fragp
, 8, 2);
19114 newsize
= relax_immediate (fragp
, 5, 2);
19118 newsize
= relax_immediate (fragp
, 5, 1);
19122 newsize
= relax_immediate (fragp
, 5, 0);
19125 newsize
= relax_adr (fragp
, sec
, stretch
);
19131 newsize
= relax_immediate (fragp
, 8, 0);
19134 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
19137 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
19139 case T_MNEM_add_sp
:
19140 case T_MNEM_add_pc
:
19141 newsize
= relax_immediate (fragp
, 8, 2);
19143 case T_MNEM_inc_sp
:
19144 case T_MNEM_dec_sp
:
19145 newsize
= relax_immediate (fragp
, 7, 2);
19151 newsize
= relax_addsub (fragp
, sec
);
19157 fragp
->fr_var
= newsize
;
19158 /* Freeze wide instructions that are at or before the same location as
19159 in the previous pass. This avoids infinite loops.
19160 Don't freeze them unconditionally because targets may be artificially
19161 misaligned by the expansion of preceding frags. */
19162 if (stretch
<= 0 && newsize
> 2)
19164 md_convert_frag (sec
->owner
, sec
, fragp
);
19168 return newsize
- oldsize
;
19171 /* Round up a section size to the appropriate boundary. */
19174 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19177 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19178 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19180 /* For a.out, force the section size to be aligned. If we don't do
19181 this, BFD will align it for us, but it will not write out the
19182 final bytes of the section. This may be a bug in BFD, but it is
19183 easier to fix it here since that is how the other a.out targets
19187 align
= bfd_get_section_alignment (stdoutput
, segment
);
19188 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19195 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19196 of an rs_align_code fragment. */
19199 arm_handle_align (fragS
* fragP
)
19201 static char const arm_noop
[2][2][4] =
19204 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19205 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19208 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19209 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19212 static char const thumb_noop
[2][2][2] =
19215 {0xc0, 0x46}, /* LE */
19216 {0x46, 0xc0}, /* BE */
19219 {0x00, 0xbf}, /* LE */
19220 {0xbf, 0x00} /* BE */
19223 static char const wide_thumb_noop
[2][4] =
19224 { /* Wide Thumb-2 */
19225 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19226 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19229 unsigned bytes
, fix
, noop_size
;
19232 const char *narrow_noop
= NULL
;
19237 if (fragP
->fr_type
!= rs_align_code
)
19240 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19241 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19244 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19245 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19247 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19249 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19251 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19253 narrow_noop
= thumb_noop
[1][target_big_endian
];
19254 noop
= wide_thumb_noop
[target_big_endian
];
19257 noop
= thumb_noop
[0][target_big_endian
];
19265 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19266 [target_big_endian
];
19273 fragP
->fr_var
= noop_size
;
19275 if (bytes
& (noop_size
- 1))
19277 fix
= bytes
& (noop_size
- 1);
19279 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19281 memset (p
, 0, fix
);
19288 if (bytes
& noop_size
)
19290 /* Insert a narrow noop. */
19291 memcpy (p
, narrow_noop
, noop_size
);
19293 bytes
-= noop_size
;
19297 /* Use wide noops for the remainder */
19301 while (bytes
>= noop_size
)
19303 memcpy (p
, noop
, noop_size
);
19305 bytes
-= noop_size
;
19309 fragP
->fr_fix
+= fix
;
19312 /* Called from md_do_align. Used to create an alignment
19313 frag in a code section. */
19316 arm_frag_align_code (int n
, int max
)
19320 /* We assume that there will never be a requirement
19321 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19322 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19327 _("alignments greater than %d bytes not supported in .text sections."),
19328 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19329 as_fatal ("%s", err_msg
);
19332 p
= frag_var (rs_align_code
,
19333 MAX_MEM_FOR_RS_ALIGN_CODE
,
19335 (relax_substateT
) max
,
19342 /* Perform target specific initialisation of a frag.
19343 Note - despite the name this initialisation is not done when the frag
19344 is created, but only when its type is assigned. A frag can be created
19345 and used a long time before its type is set, so beware of assuming that
19346 this initialisationis performed first. */
19350 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19352 /* Record whether this frag is in an ARM or a THUMB area. */
19353 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19356 #else /* OBJ_ELF is defined. */
19358 arm_init_frag (fragS
* fragP
, int max_chars
)
19360 /* If the current ARM vs THUMB mode has not already
19361 been recorded into this frag then do so now. */
19362 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19364 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19366 /* Record a mapping symbol for alignment frags. We will delete this
19367 later if the alignment ends up empty. */
19368 switch (fragP
->fr_type
)
19371 case rs_align_test
:
19373 mapping_state_2 (MAP_DATA
, max_chars
);
19375 case rs_align_code
:
19376 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19384 /* When we change sections we need to issue a new mapping symbol. */
19387 arm_elf_change_section (void)
19389 /* Link an unlinked unwind index table section to the .text section. */
19390 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19391 && elf_linked_to_section (now_seg
) == NULL
)
19392 elf_linked_to_section (now_seg
) = text_section
;
19396 arm_elf_section_type (const char * str
, size_t len
)
19398 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19399 return SHT_ARM_EXIDX
;
19404 /* Code to deal with unwinding tables. */
19406 static void add_unwind_adjustsp (offsetT
);
19408 /* Generate any deferred unwind frame offset. */
19411 flush_pending_unwind (void)
19415 offset
= unwind
.pending_offset
;
19416 unwind
.pending_offset
= 0;
19418 add_unwind_adjustsp (offset
);
19421 /* Add an opcode to this list for this function. Two-byte opcodes should
19422 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19426 add_unwind_opcode (valueT op
, int length
)
19428 /* Add any deferred stack adjustment. */
19429 if (unwind
.pending_offset
)
19430 flush_pending_unwind ();
19432 unwind
.sp_restored
= 0;
19434 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19436 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19437 if (unwind
.opcodes
)
19438 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19439 unwind
.opcode_alloc
);
19441 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19446 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19448 unwind
.opcode_count
++;
19452 /* Add unwind opcodes to adjust the stack pointer. */
19455 add_unwind_adjustsp (offsetT offset
)
19459 if (offset
> 0x200)
19461 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19466 /* Long form: 0xb2, uleb128. */
19467 /* This might not fit in a word so add the individual bytes,
19468 remembering the list is built in reverse order. */
19469 o
= (valueT
) ((offset
- 0x204) >> 2);
19471 add_unwind_opcode (0, 1);
19473 /* Calculate the uleb128 encoding of the offset. */
19477 bytes
[n
] = o
& 0x7f;
19483 /* Add the insn. */
19485 add_unwind_opcode (bytes
[n
- 1], 1);
19486 add_unwind_opcode (0xb2, 1);
19488 else if (offset
> 0x100)
19490 /* Two short opcodes. */
19491 add_unwind_opcode (0x3f, 1);
19492 op
= (offset
- 0x104) >> 2;
19493 add_unwind_opcode (op
, 1);
19495 else if (offset
> 0)
19497 /* Short opcode. */
19498 op
= (offset
- 4) >> 2;
19499 add_unwind_opcode (op
, 1);
19501 else if (offset
< 0)
19504 while (offset
> 0x100)
19506 add_unwind_opcode (0x7f, 1);
19509 op
= ((offset
- 4) >> 2) | 0x40;
19510 add_unwind_opcode (op
, 1);
19514 /* Finish the list of unwind opcodes for this function. */
19516 finish_unwind_opcodes (void)
19520 if (unwind
.fp_used
)
19522 /* Adjust sp as necessary. */
19523 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19524 flush_pending_unwind ();
19526 /* After restoring sp from the frame pointer. */
19527 op
= 0x90 | unwind
.fp_reg
;
19528 add_unwind_opcode (op
, 1);
19531 flush_pending_unwind ();
19535 /* Start an exception table entry. If idx is nonzero this is an index table
19539 start_unwind_section (const segT text_seg
, int idx
)
19541 const char * text_name
;
19542 const char * prefix
;
19543 const char * prefix_once
;
19544 const char * group_name
;
19548 size_t sec_name_len
;
19555 prefix
= ELF_STRING_ARM_unwind
;
19556 prefix_once
= ELF_STRING_ARM_unwind_once
;
19557 type
= SHT_ARM_EXIDX
;
19561 prefix
= ELF_STRING_ARM_unwind_info
;
19562 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19563 type
= SHT_PROGBITS
;
19566 text_name
= segment_name (text_seg
);
19567 if (streq (text_name
, ".text"))
19570 if (strncmp (text_name
, ".gnu.linkonce.t.",
19571 strlen (".gnu.linkonce.t.")) == 0)
19573 prefix
= prefix_once
;
19574 text_name
+= strlen (".gnu.linkonce.t.");
19577 prefix_len
= strlen (prefix
);
19578 text_len
= strlen (text_name
);
19579 sec_name_len
= prefix_len
+ text_len
;
19580 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19581 memcpy (sec_name
, prefix
, prefix_len
);
19582 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19583 sec_name
[prefix_len
+ text_len
] = '\0';
19589 /* Handle COMDAT group. */
19590 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19592 group_name
= elf_group_name (text_seg
);
19593 if (group_name
== NULL
)
19595 as_bad (_("Group section `%s' has no group signature"),
19596 segment_name (text_seg
));
19597 ignore_rest_of_line ();
19600 flags
|= SHF_GROUP
;
19604 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19606 /* Set the section link for index tables. */
19608 elf_linked_to_section (now_seg
) = text_seg
;
19612 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19613 personality routine data. Returns zero, or the index table value for
19614 and inline entry. */
19617 create_unwind_entry (int have_data
)
19622 /* The current word of data. */
19624 /* The number of bytes left in this word. */
19627 finish_unwind_opcodes ();
19629 /* Remember the current text section. */
19630 unwind
.saved_seg
= now_seg
;
19631 unwind
.saved_subseg
= now_subseg
;
19633 start_unwind_section (now_seg
, 0);
19635 if (unwind
.personality_routine
== NULL
)
19637 if (unwind
.personality_index
== -2)
19640 as_bad (_("handlerdata in cantunwind frame"));
19641 return 1; /* EXIDX_CANTUNWIND. */
19644 /* Use a default personality routine if none is specified. */
19645 if (unwind
.personality_index
== -1)
19647 if (unwind
.opcode_count
> 3)
19648 unwind
.personality_index
= 1;
19650 unwind
.personality_index
= 0;
19653 /* Space for the personality routine entry. */
19654 if (unwind
.personality_index
== 0)
19656 if (unwind
.opcode_count
> 3)
19657 as_bad (_("too many unwind opcodes for personality routine 0"));
19661 /* All the data is inline in the index table. */
19664 while (unwind
.opcode_count
> 0)
19666 unwind
.opcode_count
--;
19667 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19671 /* Pad with "finish" opcodes. */
19673 data
= (data
<< 8) | 0xb0;
19680 /* We get two opcodes "free" in the first word. */
19681 size
= unwind
.opcode_count
- 2;
19684 /* An extra byte is required for the opcode count. */
19685 size
= unwind
.opcode_count
+ 1;
19687 size
= (size
+ 3) >> 2;
19689 as_bad (_("too many unwind opcodes"));
19691 frag_align (2, 0, 0);
19692 record_alignment (now_seg
, 2);
19693 unwind
.table_entry
= expr_build_dot ();
19695 /* Allocate the table entry. */
19696 ptr
= frag_more ((size
<< 2) + 4);
19697 where
= frag_now_fix () - ((size
<< 2) + 4);
19699 switch (unwind
.personality_index
)
19702 /* ??? Should this be a PLT generating relocation? */
19703 /* Custom personality routine. */
19704 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19705 BFD_RELOC_ARM_PREL31
);
19710 /* Set the first byte to the number of additional words. */
19715 /* ABI defined personality routines. */
19717 /* Three opcodes bytes are packed into the first word. */
19724 /* The size and first two opcode bytes go in the first word. */
19725 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19730 /* Should never happen. */
19734 /* Pack the opcodes into words (MSB first), reversing the list at the same
19736 while (unwind
.opcode_count
> 0)
19740 md_number_to_chars (ptr
, data
, 4);
19745 unwind
.opcode_count
--;
19747 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19750 /* Finish off the last word. */
19753 /* Pad with "finish" opcodes. */
19755 data
= (data
<< 8) | 0xb0;
19757 md_number_to_chars (ptr
, data
, 4);
19762 /* Add an empty descriptor if there is no user-specified data. */
19763 ptr
= frag_more (4);
19764 md_number_to_chars (ptr
, 0, 4);
19771 /* Initialize the DWARF-2 unwind information for this procedure. */
19774 tc_arm_frame_initial_instructions (void)
19776 cfi_add_CFA_def_cfa (REG_SP
, 0);
19778 #endif /* OBJ_ELF */
19780 /* Convert REGNAME to a DWARF-2 register number. */
19783 tc_arm_regname_to_dw2regnum (char *regname
)
19785 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19795 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19799 exp
.X_op
= O_secrel
;
19800 exp
.X_add_symbol
= symbol
;
19801 exp
.X_add_number
= 0;
19802 emit_expr (&exp
, size
);
19806 /* MD interface: Symbol and relocation handling. */
19808 /* Return the address within the segment that a PC-relative fixup is
19809 relative to. For ARM, PC-relative fixups applied to instructions
19810 are generally relative to the location of the fixup plus 8 bytes.
19811 Thumb branches are offset by 4, and Thumb loads relative to PC
19812 require special handling. */
19815 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19817 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19819 /* If this is pc-relative and we are going to emit a relocation
19820 then we just want to put out any pipeline compensation that the linker
19821 will need. Otherwise we want to use the calculated base.
19822 For WinCE we skip the bias for externals as well, since this
19823 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19825 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19826 || (arm_force_relocation (fixP
)
19828 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19834 switch (fixP
->fx_r_type
)
19836 /* PC relative addressing on the Thumb is slightly odd as the
19837 bottom two bits of the PC are forced to zero for the
19838 calculation. This happens *after* application of the
19839 pipeline offset. However, Thumb adrl already adjusts for
19840 this, so we need not do it again. */
19841 case BFD_RELOC_ARM_THUMB_ADD
:
19844 case BFD_RELOC_ARM_THUMB_OFFSET
:
19845 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19846 case BFD_RELOC_ARM_T32_ADD_PC12
:
19847 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19848 return (base
+ 4) & ~3;
19850 /* Thumb branches are simply offset by +4. */
19851 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19852 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19853 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19854 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19855 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19858 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19860 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19861 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19862 && ARM_IS_FUNC (fixP
->fx_addsy
)
19863 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19864 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19867 /* BLX is like branches above, but forces the low two bits of PC to
19869 case BFD_RELOC_THUMB_PCREL_BLX
:
19871 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19872 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19873 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19874 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19875 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19876 return (base
+ 4) & ~3;
19878 /* ARM mode branches are offset by +8. However, the Windows CE
19879 loader expects the relocation not to take this into account. */
19880 case BFD_RELOC_ARM_PCREL_BLX
:
19882 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19883 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19884 && ARM_IS_FUNC (fixP
->fx_addsy
)
19885 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19886 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19889 case BFD_RELOC_ARM_PCREL_CALL
:
19891 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19892 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19893 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19894 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19895 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19898 case BFD_RELOC_ARM_PCREL_BRANCH
:
19899 case BFD_RELOC_ARM_PCREL_JUMP
:
19900 case BFD_RELOC_ARM_PLT32
:
19902 /* When handling fixups immediately, because we have already
19903 discovered the value of a symbol, or the address of the frag involved
19904 we must account for the offset by +8, as the OS loader will never see the reloc.
19905 see fixup_segment() in write.c
19906 The S_IS_EXTERNAL test handles the case of global symbols.
19907 Those need the calculated base, not just the pipe compensation the linker will need. */
19909 && fixP
->fx_addsy
!= NULL
19910 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19911 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19919 /* ARM mode loads relative to PC are also offset by +8. Unlike
19920 branches, the Windows CE loader *does* expect the relocation
19921 to take this into account. */
19922 case BFD_RELOC_ARM_OFFSET_IMM
:
19923 case BFD_RELOC_ARM_OFFSET_IMM8
:
19924 case BFD_RELOC_ARM_HWLITERAL
:
19925 case BFD_RELOC_ARM_LITERAL
:
19926 case BFD_RELOC_ARM_CP_OFF_IMM
:
19930 /* Other PC-relative relocations are un-offset. */
19936 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19937 Otherwise we have no need to default values of symbols. */
19940 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19943 if (name
[0] == '_' && name
[1] == 'G'
19944 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19948 if (symbol_find (name
))
19949 as_bad (_("GOT already in the symbol table"));
19951 GOT_symbol
= symbol_new (name
, undefined_section
,
19952 (valueT
) 0, & zero_address_frag
);
19962 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19963 computed as two separate immediate values, added together. We
19964 already know that this value cannot be computed by just one ARM
19967 static unsigned int
19968 validate_immediate_twopart (unsigned int val
,
19969 unsigned int * highpart
)
19974 for (i
= 0; i
< 32; i
+= 2)
19975 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19981 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19983 else if (a
& 0xff0000)
19985 if (a
& 0xff000000)
19987 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19991 gas_assert (a
& 0xff000000);
19992 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19995 return (a
& 0xff) | (i
<< 7);
20002 validate_offset_imm (unsigned int val
, int hwse
)
20004 if ((hwse
&& val
> 255) || val
> 4095)
20009 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20010 negative immediate constant by altering the instruction. A bit of
20015 by inverting the second operand, and
20018 by negating the second operand. */
20021 negate_data_op (unsigned long * instruction
,
20022 unsigned long value
)
20025 unsigned long negated
, inverted
;
20027 negated
= encode_arm_immediate (-value
);
20028 inverted
= encode_arm_immediate (~value
);
20030 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
20033 /* First negates. */
20034 case OPCODE_SUB
: /* ADD <-> SUB */
20035 new_inst
= OPCODE_ADD
;
20040 new_inst
= OPCODE_SUB
;
20044 case OPCODE_CMP
: /* CMP <-> CMN */
20045 new_inst
= OPCODE_CMN
;
20050 new_inst
= OPCODE_CMP
;
20054 /* Now Inverted ops. */
20055 case OPCODE_MOV
: /* MOV <-> MVN */
20056 new_inst
= OPCODE_MVN
;
20061 new_inst
= OPCODE_MOV
;
20065 case OPCODE_AND
: /* AND <-> BIC */
20066 new_inst
= OPCODE_BIC
;
20071 new_inst
= OPCODE_AND
;
20075 case OPCODE_ADC
: /* ADC <-> SBC */
20076 new_inst
= OPCODE_SBC
;
20081 new_inst
= OPCODE_ADC
;
20085 /* We cannot do anything. */
20090 if (value
== (unsigned) FAIL
)
20093 *instruction
&= OPCODE_MASK
;
20094 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
20098 /* Like negate_data_op, but for Thumb-2. */
20100 static unsigned int
20101 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
20105 unsigned int negated
, inverted
;
20107 negated
= encode_thumb32_immediate (-value
);
20108 inverted
= encode_thumb32_immediate (~value
);
20110 rd
= (*instruction
>> 8) & 0xf;
20111 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
20114 /* ADD <-> SUB. Includes CMP <-> CMN. */
20115 case T2_OPCODE_SUB
:
20116 new_inst
= T2_OPCODE_ADD
;
20120 case T2_OPCODE_ADD
:
20121 new_inst
= T2_OPCODE_SUB
;
20125 /* ORR <-> ORN. Includes MOV <-> MVN. */
20126 case T2_OPCODE_ORR
:
20127 new_inst
= T2_OPCODE_ORN
;
20131 case T2_OPCODE_ORN
:
20132 new_inst
= T2_OPCODE_ORR
;
20136 /* AND <-> BIC. TST has no inverted equivalent. */
20137 case T2_OPCODE_AND
:
20138 new_inst
= T2_OPCODE_BIC
;
20145 case T2_OPCODE_BIC
:
20146 new_inst
= T2_OPCODE_AND
;
20151 case T2_OPCODE_ADC
:
20152 new_inst
= T2_OPCODE_SBC
;
20156 case T2_OPCODE_SBC
:
20157 new_inst
= T2_OPCODE_ADC
;
20161 /* We cannot do anything. */
20166 if (value
== (unsigned int)FAIL
)
20169 *instruction
&= T2_OPCODE_MASK
;
20170 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20174 /* Read a 32-bit thumb instruction from buf. */
20175 static unsigned long
20176 get_thumb32_insn (char * buf
)
20178 unsigned long insn
;
20179 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20180 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20186 /* We usually want to set the low bit on the address of thumb function
20187 symbols. In particular .word foo - . should have the low bit set.
20188 Generic code tries to fold the difference of two symbols to
20189 a constant. Prevent this and force a relocation when the first symbols
20190 is a thumb function. */
20193 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20195 if (op
== O_subtract
20196 && l
->X_op
== O_symbol
20197 && r
->X_op
== O_symbol
20198 && THUMB_IS_FUNC (l
->X_add_symbol
))
20200 l
->X_op
= O_subtract
;
20201 l
->X_op_symbol
= r
->X_add_symbol
;
20202 l
->X_add_number
-= r
->X_add_number
;
20206 /* Process as normal. */
20210 /* Encode Thumb2 unconditional branches and calls. The encoding
20211 for the 2 are identical for the immediate values. */
20214 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20216 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20219 addressT S
, I1
, I2
, lo
, hi
;
20221 S
= (value
>> 24) & 0x01;
20222 I1
= (value
>> 23) & 0x01;
20223 I2
= (value
>> 22) & 0x01;
20224 hi
= (value
>> 12) & 0x3ff;
20225 lo
= (value
>> 1) & 0x7ff;
20226 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20227 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20228 newval
|= (S
<< 10) | hi
;
20229 newval2
&= ~T2I1I2MASK
;
20230 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20231 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20232 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20236 md_apply_fix (fixS
* fixP
,
20240 offsetT value
= * valP
;
20242 unsigned int newimm
;
20243 unsigned long temp
;
20245 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20247 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20249 /* Note whether this will delete the relocation. */
20251 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20254 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20255 consistency with the behaviour on 32-bit hosts. Remember value
20257 value
&= 0xffffffff;
20258 value
^= 0x80000000;
20259 value
-= 0x80000000;
20262 fixP
->fx_addnumber
= value
;
20264 /* Same treatment for fixP->fx_offset. */
20265 fixP
->fx_offset
&= 0xffffffff;
20266 fixP
->fx_offset
^= 0x80000000;
20267 fixP
->fx_offset
-= 0x80000000;
20269 switch (fixP
->fx_r_type
)
20271 case BFD_RELOC_NONE
:
20272 /* This will need to go in the object file. */
20276 case BFD_RELOC_ARM_IMMEDIATE
:
20277 /* We claim that this fixup has been processed here,
20278 even if in fact we generate an error because we do
20279 not have a reloc for it, so tc_gen_reloc will reject it. */
20282 if (fixP
->fx_addsy
)
20284 const char *msg
= 0;
20286 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20287 msg
= _("undefined symbol %s used as an immediate value");
20288 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20289 msg
= _("symbol %s is in a different section");
20290 else if (S_IS_WEAK (fixP
->fx_addsy
))
20291 msg
= _("symbol %s is weak and may be overridden later");
20295 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20296 msg
, S_GET_NAME (fixP
->fx_addsy
));
20301 newimm
= encode_arm_immediate (value
);
20302 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20304 /* If the instruction will fail, see if we can fix things up by
20305 changing the opcode. */
20306 if (newimm
== (unsigned int) FAIL
20307 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20309 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20310 _("invalid constant (%lx) after fixup"),
20311 (unsigned long) value
);
20315 newimm
|= (temp
& 0xfffff000);
20316 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20319 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20321 unsigned int highpart
= 0;
20322 unsigned int newinsn
= 0xe1a00000; /* nop. */
20324 if (fixP
->fx_addsy
)
20326 const char *msg
= 0;
20328 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20329 msg
= _("undefined symbol %s used as an immediate value");
20330 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20331 msg
= _("symbol %s is in a different section");
20332 else if (S_IS_WEAK (fixP
->fx_addsy
))
20333 msg
= _("symbol %s is weak and may be overridden later");
20337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20338 msg
, S_GET_NAME (fixP
->fx_addsy
));
20343 newimm
= encode_arm_immediate (value
);
20344 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20346 /* If the instruction will fail, see if we can fix things up by
20347 changing the opcode. */
20348 if (newimm
== (unsigned int) FAIL
20349 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20351 /* No ? OK - try using two ADD instructions to generate
20353 newimm
= validate_immediate_twopart (value
, & highpart
);
20355 /* Yes - then make sure that the second instruction is
20357 if (newimm
!= (unsigned int) FAIL
)
20359 /* Still No ? Try using a negated value. */
20360 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20361 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20362 /* Otherwise - give up. */
20365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20366 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20371 /* Replace the first operand in the 2nd instruction (which
20372 is the PC) with the destination register. We have
20373 already added in the PC in the first instruction and we
20374 do not want to do it again. */
20375 newinsn
&= ~ 0xf0000;
20376 newinsn
|= ((newinsn
& 0x0f000) << 4);
20379 newimm
|= (temp
& 0xfffff000);
20380 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20382 highpart
|= (newinsn
& 0xfffff000);
20383 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20387 case BFD_RELOC_ARM_OFFSET_IMM
:
20388 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20391 case BFD_RELOC_ARM_LITERAL
:
20397 if (validate_offset_imm (value
, 0) == FAIL
)
20399 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20401 _("invalid literal constant: pool needs to be closer"));
20403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20404 _("bad immediate value for offset (%ld)"),
20409 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20410 newval
&= 0xff7ff000;
20411 newval
|= value
| (sign
? INDEX_UP
: 0);
20412 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20415 case BFD_RELOC_ARM_OFFSET_IMM8
:
20416 case BFD_RELOC_ARM_HWLITERAL
:
20422 if (validate_offset_imm (value
, 1) == FAIL
)
20424 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20426 _("invalid literal constant: pool needs to be closer"));
20428 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20433 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20434 newval
&= 0xff7ff0f0;
20435 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20436 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20439 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20440 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20441 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20442 _("bad immediate value for offset (%ld)"), (long) value
);
20445 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20447 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20450 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20451 /* This is a complicated relocation used for all varieties of Thumb32
20452 load/store instruction with immediate offset:
20454 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20455 *4, optional writeback(W)
20456 (doubleword load/store)
20458 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20459 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20460 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20461 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20462 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20464 Uppercase letters indicate bits that are already encoded at
20465 this point. Lowercase letters are our problem. For the
20466 second block of instructions, the secondary opcode nybble
20467 (bits 8..11) is present, and bit 23 is zero, even if this is
20468 a PC-relative operation. */
20469 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20471 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20473 if ((newval
& 0xf0000000) == 0xe0000000)
20475 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20477 newval
|= (1 << 23);
20480 if (value
% 4 != 0)
20482 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20483 _("offset not a multiple of 4"));
20489 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20490 _("offset out of range"));
20495 else if ((newval
& 0x000f0000) == 0x000f0000)
20497 /* PC-relative, 12-bit offset. */
20499 newval
|= (1 << 23);
20504 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20505 _("offset out of range"));
20510 else if ((newval
& 0x00000100) == 0x00000100)
20512 /* Writeback: 8-bit, +/- offset. */
20514 newval
|= (1 << 9);
20519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20520 _("offset out of range"));
20525 else if ((newval
& 0x00000f00) == 0x00000e00)
20527 /* T-instruction: positive 8-bit offset. */
20528 if (value
< 0 || value
> 0xff)
20530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20531 _("offset out of range"));
20539 /* Positive 12-bit or negative 8-bit offset. */
20543 newval
|= (1 << 23);
20553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20554 _("offset out of range"));
20561 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20562 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20565 case BFD_RELOC_ARM_SHIFT_IMM
:
20566 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20567 if (((unsigned long) value
) > 32
20569 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20572 _("shift expression is too large"));
20577 /* Shifts of zero must be done as lsl. */
20579 else if (value
== 32)
20581 newval
&= 0xfffff07f;
20582 newval
|= (value
& 0x1f) << 7;
20583 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20586 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20587 case BFD_RELOC_ARM_T32_ADD_IMM
:
20588 case BFD_RELOC_ARM_T32_IMM12
:
20589 case BFD_RELOC_ARM_T32_ADD_PC12
:
20590 /* We claim that this fixup has been processed here,
20591 even if in fact we generate an error because we do
20592 not have a reloc for it, so tc_gen_reloc will reject it. */
20596 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20599 _("undefined symbol %s used as an immediate value"),
20600 S_GET_NAME (fixP
->fx_addsy
));
20604 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20606 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20609 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20610 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20612 newimm
= encode_thumb32_immediate (value
);
20613 if (newimm
== (unsigned int) FAIL
)
20614 newimm
= thumb32_negate_data_op (&newval
, value
);
20616 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20617 && newimm
== (unsigned int) FAIL
)
20619 /* Turn add/sum into addw/subw. */
20620 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20621 newval
= (newval
& 0xfeffffff) | 0x02000000;
20622 /* No flat 12-bit imm encoding for addsw/subsw. */
20623 if ((newval
& 0x00100000) == 0)
20625 /* 12 bit immediate for addw/subw. */
20629 newval
^= 0x00a00000;
20632 newimm
= (unsigned int) FAIL
;
20638 if (newimm
== (unsigned int)FAIL
)
20640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20641 _("invalid constant (%lx) after fixup"),
20642 (unsigned long) value
);
20646 newval
|= (newimm
& 0x800) << 15;
20647 newval
|= (newimm
& 0x700) << 4;
20648 newval
|= (newimm
& 0x0ff);
20650 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20651 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20654 case BFD_RELOC_ARM_SMC
:
20655 if (((unsigned long) value
) > 0xffff)
20656 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20657 _("invalid smc expression"));
20658 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20659 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20660 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20663 case BFD_RELOC_ARM_HVC
:
20664 if (((unsigned long) value
) > 0xffff)
20665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20666 _("invalid hvc expression"));
20667 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20668 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20669 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20672 case BFD_RELOC_ARM_SWI
:
20673 if (fixP
->tc_fix_data
!= 0)
20675 if (((unsigned long) value
) > 0xff)
20676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20677 _("invalid swi expression"));
20678 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20680 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20684 if (((unsigned long) value
) > 0x00ffffff)
20685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20686 _("invalid swi expression"));
20687 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20689 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20693 case BFD_RELOC_ARM_MULTI
:
20694 if (((unsigned long) value
) > 0xffff)
20695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20696 _("invalid expression in load/store multiple"));
20697 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20698 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20702 case BFD_RELOC_ARM_PCREL_CALL
:
20704 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20706 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20707 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20708 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20709 /* Flip the bl to blx. This is a simple flip
20710 bit here because we generate PCREL_CALL for
20711 unconditional bls. */
20713 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20714 newval
= newval
| 0x10000000;
20715 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20721 goto arm_branch_common
;
20723 case BFD_RELOC_ARM_PCREL_JUMP
:
20724 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20726 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20727 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20728 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20730 /* This would map to a bl<cond>, b<cond>,
20731 b<always> to a Thumb function. We
20732 need to force a relocation for this particular
20734 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20738 case BFD_RELOC_ARM_PLT32
:
20740 case BFD_RELOC_ARM_PCREL_BRANCH
:
20742 goto arm_branch_common
;
20744 case BFD_RELOC_ARM_PCREL_BLX
:
20747 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20749 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20750 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20751 && ARM_IS_FUNC (fixP
->fx_addsy
))
20753 /* Flip the blx to a bl and warn. */
20754 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20755 newval
= 0xeb000000;
20756 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20757 _("blx to '%s' an ARM ISA state function changed to bl"),
20759 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20765 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20766 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20770 /* We are going to store value (shifted right by two) in the
20771 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20772 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20773 also be be clear. */
20775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20776 _("misaligned branch destination"));
20777 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20778 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20779 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20780 _("branch out of range"));
20782 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20784 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20785 newval
|= (value
>> 2) & 0x00ffffff;
20786 /* Set the H bit on BLX instructions. */
20790 newval
|= 0x01000000;
20792 newval
&= ~0x01000000;
20794 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20798 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20799 /* CBZ can only branch forward. */
20801 /* Attempts to use CBZ to branch to the next instruction
20802 (which, strictly speaking, are prohibited) will be turned into
20805 FIXME: It may be better to remove the instruction completely and
20806 perform relaxation. */
20809 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20810 newval
= 0xbf00; /* NOP encoding T1 */
20811 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20817 _("branch out of range"));
20819 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20821 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20822 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20823 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20828 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20829 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20830 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20831 _("branch out of range"));
20833 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20835 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20836 newval
|= (value
& 0x1ff) >> 1;
20837 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20841 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20842 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20844 _("branch out of range"));
20846 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20848 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20849 newval
|= (value
& 0xfff) >> 1;
20850 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20854 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20856 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20857 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20858 && ARM_IS_FUNC (fixP
->fx_addsy
)
20859 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20861 /* Force a relocation for a branch 20 bits wide. */
20864 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20866 _("conditional branch out of range"));
20868 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20871 addressT S
, J1
, J2
, lo
, hi
;
20873 S
= (value
& 0x00100000) >> 20;
20874 J2
= (value
& 0x00080000) >> 19;
20875 J1
= (value
& 0x00040000) >> 18;
20876 hi
= (value
& 0x0003f000) >> 12;
20877 lo
= (value
& 0x00000ffe) >> 1;
20879 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20880 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20881 newval
|= (S
<< 10) | hi
;
20882 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20883 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20884 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20888 case BFD_RELOC_THUMB_PCREL_BLX
:
20890 /* If there is a blx from a thumb state function to
20891 another thumb function flip this to a bl and warn
20895 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20896 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20897 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20899 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20900 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20901 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20903 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20904 newval
= newval
| 0x1000;
20905 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20906 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20911 goto thumb_bl_common
;
20913 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20915 /* A bl from Thumb state ISA to an internal ARM state function
20916 is converted to a blx. */
20918 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20919 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20920 && ARM_IS_FUNC (fixP
->fx_addsy
)
20921 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20923 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20924 newval
= newval
& ~0x1000;
20925 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20926 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20933 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20934 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20935 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20938 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20939 /* For a BLX instruction, make sure that the relocation is rounded up
20940 to a word boundary. This follows the semantics of the instruction
20941 which specifies that bit 1 of the target address will come from bit
20942 1 of the base address. */
20943 value
= (value
+ 1) & ~ 1;
20946 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20948 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20951 _("branch out of range"));
20953 else if ((value
& ~0x1ffffff)
20954 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20957 _("Thumb2 branch out of range"));
20961 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20962 encode_thumb2_b_bl_offset (buf
, value
);
20966 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20967 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20969 _("branch out of range"));
20971 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20972 encode_thumb2_b_bl_offset (buf
, value
);
20977 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20978 md_number_to_chars (buf
, value
, 1);
20982 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20983 md_number_to_chars (buf
, value
, 2);
20987 case BFD_RELOC_ARM_TLS_CALL
:
20988 case BFD_RELOC_ARM_THM_TLS_CALL
:
20989 case BFD_RELOC_ARM_TLS_DESCSEQ
:
20990 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
20991 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20994 case BFD_RELOC_ARM_TLS_GOTDESC
:
20995 case BFD_RELOC_ARM_TLS_GD32
:
20996 case BFD_RELOC_ARM_TLS_LE32
:
20997 case BFD_RELOC_ARM_TLS_IE32
:
20998 case BFD_RELOC_ARM_TLS_LDM32
:
20999 case BFD_RELOC_ARM_TLS_LDO32
:
21000 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21003 case BFD_RELOC_ARM_GOT32
:
21004 case BFD_RELOC_ARM_GOTOFF
:
21005 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21006 md_number_to_chars (buf
, 0, 4);
21009 case BFD_RELOC_ARM_GOT_PREL
:
21010 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21011 md_number_to_chars (buf
, value
, 4);
21014 case BFD_RELOC_ARM_TARGET2
:
21015 /* TARGET2 is not partial-inplace, so we need to write the
21016 addend here for REL targets, because it won't be written out
21017 during reloc processing later. */
21018 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21019 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
21023 case BFD_RELOC_RVA
:
21025 case BFD_RELOC_ARM_TARGET1
:
21026 case BFD_RELOC_ARM_ROSEGREL32
:
21027 case BFD_RELOC_ARM_SBREL32
:
21028 case BFD_RELOC_32_PCREL
:
21030 case BFD_RELOC_32_SECREL
:
21032 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21034 /* For WinCE we only do this for pcrel fixups. */
21035 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
21037 md_number_to_chars (buf
, value
, 4);
21041 case BFD_RELOC_ARM_PREL31
:
21042 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21044 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
21045 if ((value
^ (value
>> 1)) & 0x40000000)
21047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21048 _("rel31 relocation overflow"));
21050 newval
|= value
& 0x7fffffff;
21051 md_number_to_chars (buf
, newval
, 4);
21056 case BFD_RELOC_ARM_CP_OFF_IMM
:
21057 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21058 if (value
< -1023 || value
> 1023 || (value
& 3))
21059 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21060 _("co-processor offset out of range"));
21065 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21066 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21067 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21069 newval
= get_thumb32_insn (buf
);
21070 newval
&= 0xff7fff00;
21071 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
21072 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21073 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21074 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21076 put_thumb32_insn (buf
, newval
);
21079 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
21080 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
21081 if (value
< -255 || value
> 255)
21082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21083 _("co-processor offset out of range"));
21085 goto cp_off_common
;
21087 case BFD_RELOC_ARM_THUMB_OFFSET
:
21088 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21089 /* Exactly what ranges, and where the offset is inserted depends
21090 on the type of instruction, we can establish this from the
21092 switch (newval
>> 12)
21094 case 4: /* PC load. */
21095 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21096 forced to zero for these loads; md_pcrel_from has already
21097 compensated for this. */
21099 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21100 _("invalid offset, target not word aligned (0x%08lX)"),
21101 (((unsigned long) fixP
->fx_frag
->fr_address
21102 + (unsigned long) fixP
->fx_where
) & ~3)
21103 + (unsigned long) value
);
21105 if (value
& ~0x3fc)
21106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21107 _("invalid offset, value too big (0x%08lX)"),
21110 newval
|= value
>> 2;
21113 case 9: /* SP load/store. */
21114 if (value
& ~0x3fc)
21115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21116 _("invalid offset, value too big (0x%08lX)"),
21118 newval
|= value
>> 2;
21121 case 6: /* Word load/store. */
21123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21124 _("invalid offset, value too big (0x%08lX)"),
21126 newval
|= value
<< 4; /* 6 - 2. */
21129 case 7: /* Byte load/store. */
21131 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21132 _("invalid offset, value too big (0x%08lX)"),
21134 newval
|= value
<< 6;
21137 case 8: /* Halfword load/store. */
21139 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21140 _("invalid offset, value too big (0x%08lX)"),
21142 newval
|= value
<< 5; /* 6 - 1. */
21146 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21147 "Unable to process relocation for thumb opcode: %lx",
21148 (unsigned long) newval
);
21151 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21154 case BFD_RELOC_ARM_THUMB_ADD
:
21155 /* This is a complicated relocation, since we use it for all of
21156 the following immediate relocations:
21160 9bit ADD/SUB SP word-aligned
21161 10bit ADD PC/SP word-aligned
21163 The type of instruction being processed is encoded in the
21170 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21172 int rd
= (newval
>> 4) & 0xf;
21173 int rs
= newval
& 0xf;
21174 int subtract
= !!(newval
& 0x8000);
21176 /* Check for HI regs, only very restricted cases allowed:
21177 Adjusting SP, and using PC or SP to get an address. */
21178 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21179 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21181 _("invalid Hi register with immediate"));
21183 /* If value is negative, choose the opposite instruction. */
21187 subtract
= !subtract
;
21189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21190 _("immediate value out of range"));
21195 if (value
& ~0x1fc)
21196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21197 _("invalid immediate for stack address calculation"));
21198 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21199 newval
|= value
>> 2;
21201 else if (rs
== REG_PC
|| rs
== REG_SP
)
21203 if (subtract
|| value
& ~0x3fc)
21204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21205 _("invalid immediate for address calculation (value = 0x%08lX)"),
21206 (unsigned long) value
);
21207 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21209 newval
|= value
>> 2;
21214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21215 _("immediate value out of range"));
21216 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21217 newval
|= (rd
<< 8) | value
;
21222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21223 _("immediate value out of range"));
21224 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21225 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21228 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21231 case BFD_RELOC_ARM_THUMB_IMM
:
21232 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21233 if (value
< 0 || value
> 255)
21234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21235 _("invalid immediate: %ld is out of range"),
21238 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21241 case BFD_RELOC_ARM_THUMB_SHIFT
:
21242 /* 5bit shift value (0..32). LSL cannot take 32. */
21243 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21244 temp
= newval
& 0xf800;
21245 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21247 _("invalid shift value: %ld"), (long) value
);
21248 /* Shifts of zero must be encoded as LSL. */
21250 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21251 /* Shifts of 32 are encoded as zero. */
21252 else if (value
== 32)
21254 newval
|= value
<< 6;
21255 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21258 case BFD_RELOC_VTABLE_INHERIT
:
21259 case BFD_RELOC_VTABLE_ENTRY
:
21263 case BFD_RELOC_ARM_MOVW
:
21264 case BFD_RELOC_ARM_MOVT
:
21265 case BFD_RELOC_ARM_THUMB_MOVW
:
21266 case BFD_RELOC_ARM_THUMB_MOVT
:
21267 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21269 /* REL format relocations are limited to a 16-bit addend. */
21270 if (!fixP
->fx_done
)
21272 if (value
< -0x8000 || value
> 0x7fff)
21273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21274 _("offset out of range"));
21276 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21277 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21282 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21283 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21285 newval
= get_thumb32_insn (buf
);
21286 newval
&= 0xfbf08f00;
21287 newval
|= (value
& 0xf000) << 4;
21288 newval
|= (value
& 0x0800) << 15;
21289 newval
|= (value
& 0x0700) << 4;
21290 newval
|= (value
& 0x00ff);
21291 put_thumb32_insn (buf
, newval
);
21295 newval
= md_chars_to_number (buf
, 4);
21296 newval
&= 0xfff0f000;
21297 newval
|= value
& 0x0fff;
21298 newval
|= (value
& 0xf000) << 4;
21299 md_number_to_chars (buf
, newval
, 4);
21304 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21305 case BFD_RELOC_ARM_ALU_PC_G0
:
21306 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21307 case BFD_RELOC_ARM_ALU_PC_G1
:
21308 case BFD_RELOC_ARM_ALU_PC_G2
:
21309 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21310 case BFD_RELOC_ARM_ALU_SB_G0
:
21311 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21312 case BFD_RELOC_ARM_ALU_SB_G1
:
21313 case BFD_RELOC_ARM_ALU_SB_G2
:
21314 gas_assert (!fixP
->fx_done
);
21315 if (!seg
->use_rela_p
)
21318 bfd_vma encoded_addend
;
21319 bfd_vma addend_abs
= abs (value
);
21321 /* Check that the absolute value of the addend can be
21322 expressed as an 8-bit constant plus a rotation. */
21323 encoded_addend
= encode_arm_immediate (addend_abs
);
21324 if (encoded_addend
== (unsigned int) FAIL
)
21325 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21326 _("the offset 0x%08lX is not representable"),
21327 (unsigned long) addend_abs
);
21329 /* Extract the instruction. */
21330 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21332 /* If the addend is positive, use an ADD instruction.
21333 Otherwise use a SUB. Take care not to destroy the S bit. */
21334 insn
&= 0xff1fffff;
21340 /* Place the encoded addend into the first 12 bits of the
21342 insn
&= 0xfffff000;
21343 insn
|= encoded_addend
;
21345 /* Update the instruction. */
21346 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21350 case BFD_RELOC_ARM_LDR_PC_G0
:
21351 case BFD_RELOC_ARM_LDR_PC_G1
:
21352 case BFD_RELOC_ARM_LDR_PC_G2
:
21353 case BFD_RELOC_ARM_LDR_SB_G0
:
21354 case BFD_RELOC_ARM_LDR_SB_G1
:
21355 case BFD_RELOC_ARM_LDR_SB_G2
:
21356 gas_assert (!fixP
->fx_done
);
21357 if (!seg
->use_rela_p
)
21360 bfd_vma addend_abs
= abs (value
);
21362 /* Check that the absolute value of the addend can be
21363 encoded in 12 bits. */
21364 if (addend_abs
>= 0x1000)
21365 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21366 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21367 (unsigned long) addend_abs
);
21369 /* Extract the instruction. */
21370 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21372 /* If the addend is negative, clear bit 23 of the instruction.
21373 Otherwise set it. */
21375 insn
&= ~(1 << 23);
21379 /* Place the absolute value of the addend into the first 12 bits
21380 of the instruction. */
21381 insn
&= 0xfffff000;
21382 insn
|= addend_abs
;
21384 /* Update the instruction. */
21385 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21389 case BFD_RELOC_ARM_LDRS_PC_G0
:
21390 case BFD_RELOC_ARM_LDRS_PC_G1
:
21391 case BFD_RELOC_ARM_LDRS_PC_G2
:
21392 case BFD_RELOC_ARM_LDRS_SB_G0
:
21393 case BFD_RELOC_ARM_LDRS_SB_G1
:
21394 case BFD_RELOC_ARM_LDRS_SB_G2
:
21395 gas_assert (!fixP
->fx_done
);
21396 if (!seg
->use_rela_p
)
21399 bfd_vma addend_abs
= abs (value
);
21401 /* Check that the absolute value of the addend can be
21402 encoded in 8 bits. */
21403 if (addend_abs
>= 0x100)
21404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21405 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21406 (unsigned long) addend_abs
);
21408 /* Extract the instruction. */
21409 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21411 /* If the addend is negative, clear bit 23 of the instruction.
21412 Otherwise set it. */
21414 insn
&= ~(1 << 23);
21418 /* Place the first four bits of the absolute value of the addend
21419 into the first 4 bits of the instruction, and the remaining
21420 four into bits 8 .. 11. */
21421 insn
&= 0xfffff0f0;
21422 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21424 /* Update the instruction. */
21425 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21429 case BFD_RELOC_ARM_LDC_PC_G0
:
21430 case BFD_RELOC_ARM_LDC_PC_G1
:
21431 case BFD_RELOC_ARM_LDC_PC_G2
:
21432 case BFD_RELOC_ARM_LDC_SB_G0
:
21433 case BFD_RELOC_ARM_LDC_SB_G1
:
21434 case BFD_RELOC_ARM_LDC_SB_G2
:
21435 gas_assert (!fixP
->fx_done
);
21436 if (!seg
->use_rela_p
)
21439 bfd_vma addend_abs
= abs (value
);
21441 /* Check that the absolute value of the addend is a multiple of
21442 four and, when divided by four, fits in 8 bits. */
21443 if (addend_abs
& 0x3)
21444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21445 _("bad offset 0x%08lX (must be word-aligned)"),
21446 (unsigned long) addend_abs
);
21448 if ((addend_abs
>> 2) > 0xff)
21449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21450 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21451 (unsigned long) addend_abs
);
21453 /* Extract the instruction. */
21454 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21456 /* If the addend is negative, clear bit 23 of the instruction.
21457 Otherwise set it. */
21459 insn
&= ~(1 << 23);
21463 /* Place the addend (divided by four) into the first eight
21464 bits of the instruction. */
21465 insn
&= 0xfffffff0;
21466 insn
|= addend_abs
>> 2;
21468 /* Update the instruction. */
21469 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21473 case BFD_RELOC_ARM_V4BX
:
21474 /* This will need to go in the object file. */
21478 case BFD_RELOC_UNUSED
:
21480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21481 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21485 /* Translate internal representation of relocation info to BFD target
21489 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21492 bfd_reloc_code_real_type code
;
21494 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21496 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21497 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21498 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21500 if (fixp
->fx_pcrel
)
21502 if (section
->use_rela_p
)
21503 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21505 fixp
->fx_offset
= reloc
->address
;
21507 reloc
->addend
= fixp
->fx_offset
;
21509 switch (fixp
->fx_r_type
)
21512 if (fixp
->fx_pcrel
)
21514 code
= BFD_RELOC_8_PCREL
;
21519 if (fixp
->fx_pcrel
)
21521 code
= BFD_RELOC_16_PCREL
;
21526 if (fixp
->fx_pcrel
)
21528 code
= BFD_RELOC_32_PCREL
;
21532 case BFD_RELOC_ARM_MOVW
:
21533 if (fixp
->fx_pcrel
)
21535 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21539 case BFD_RELOC_ARM_MOVT
:
21540 if (fixp
->fx_pcrel
)
21542 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21546 case BFD_RELOC_ARM_THUMB_MOVW
:
21547 if (fixp
->fx_pcrel
)
21549 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21553 case BFD_RELOC_ARM_THUMB_MOVT
:
21554 if (fixp
->fx_pcrel
)
21556 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21560 case BFD_RELOC_NONE
:
21561 case BFD_RELOC_ARM_PCREL_BRANCH
:
21562 case BFD_RELOC_ARM_PCREL_BLX
:
21563 case BFD_RELOC_RVA
:
21564 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21565 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21566 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21567 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21568 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21569 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21570 case BFD_RELOC_VTABLE_ENTRY
:
21571 case BFD_RELOC_VTABLE_INHERIT
:
21573 case BFD_RELOC_32_SECREL
:
21575 code
= fixp
->fx_r_type
;
21578 case BFD_RELOC_THUMB_PCREL_BLX
:
21580 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21581 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21584 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21587 case BFD_RELOC_ARM_LITERAL
:
21588 case BFD_RELOC_ARM_HWLITERAL
:
21589 /* If this is called then the a literal has
21590 been referenced across a section boundary. */
21591 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21592 _("literal referenced across section boundary"));
21596 case BFD_RELOC_ARM_TLS_CALL
:
21597 case BFD_RELOC_ARM_THM_TLS_CALL
:
21598 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21599 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21600 case BFD_RELOC_ARM_GOT32
:
21601 case BFD_RELOC_ARM_GOTOFF
:
21602 case BFD_RELOC_ARM_GOT_PREL
:
21603 case BFD_RELOC_ARM_PLT32
:
21604 case BFD_RELOC_ARM_TARGET1
:
21605 case BFD_RELOC_ARM_ROSEGREL32
:
21606 case BFD_RELOC_ARM_SBREL32
:
21607 case BFD_RELOC_ARM_PREL31
:
21608 case BFD_RELOC_ARM_TARGET2
:
21609 case BFD_RELOC_ARM_TLS_LE32
:
21610 case BFD_RELOC_ARM_TLS_LDO32
:
21611 case BFD_RELOC_ARM_PCREL_CALL
:
21612 case BFD_RELOC_ARM_PCREL_JUMP
:
21613 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21614 case BFD_RELOC_ARM_ALU_PC_G0
:
21615 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21616 case BFD_RELOC_ARM_ALU_PC_G1
:
21617 case BFD_RELOC_ARM_ALU_PC_G2
:
21618 case BFD_RELOC_ARM_LDR_PC_G0
:
21619 case BFD_RELOC_ARM_LDR_PC_G1
:
21620 case BFD_RELOC_ARM_LDR_PC_G2
:
21621 case BFD_RELOC_ARM_LDRS_PC_G0
:
21622 case BFD_RELOC_ARM_LDRS_PC_G1
:
21623 case BFD_RELOC_ARM_LDRS_PC_G2
:
21624 case BFD_RELOC_ARM_LDC_PC_G0
:
21625 case BFD_RELOC_ARM_LDC_PC_G1
:
21626 case BFD_RELOC_ARM_LDC_PC_G2
:
21627 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21628 case BFD_RELOC_ARM_ALU_SB_G0
:
21629 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21630 case BFD_RELOC_ARM_ALU_SB_G1
:
21631 case BFD_RELOC_ARM_ALU_SB_G2
:
21632 case BFD_RELOC_ARM_LDR_SB_G0
:
21633 case BFD_RELOC_ARM_LDR_SB_G1
:
21634 case BFD_RELOC_ARM_LDR_SB_G2
:
21635 case BFD_RELOC_ARM_LDRS_SB_G0
:
21636 case BFD_RELOC_ARM_LDRS_SB_G1
:
21637 case BFD_RELOC_ARM_LDRS_SB_G2
:
21638 case BFD_RELOC_ARM_LDC_SB_G0
:
21639 case BFD_RELOC_ARM_LDC_SB_G1
:
21640 case BFD_RELOC_ARM_LDC_SB_G2
:
21641 case BFD_RELOC_ARM_V4BX
:
21642 code
= fixp
->fx_r_type
;
21645 case BFD_RELOC_ARM_TLS_GOTDESC
:
21646 case BFD_RELOC_ARM_TLS_GD32
:
21647 case BFD_RELOC_ARM_TLS_IE32
:
21648 case BFD_RELOC_ARM_TLS_LDM32
:
21649 /* BFD will include the symbol's address in the addend.
21650 But we don't want that, so subtract it out again here. */
21651 if (!S_IS_COMMON (fixp
->fx_addsy
))
21652 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21653 code
= fixp
->fx_r_type
;
21657 case BFD_RELOC_ARM_IMMEDIATE
:
21658 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21659 _("internal relocation (type: IMMEDIATE) not fixed up"));
21662 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21663 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21664 _("ADRL used for a symbol not defined in the same file"));
21667 case BFD_RELOC_ARM_OFFSET_IMM
:
21668 if (section
->use_rela_p
)
21670 code
= fixp
->fx_r_type
;
21674 if (fixp
->fx_addsy
!= NULL
21675 && !S_IS_DEFINED (fixp
->fx_addsy
)
21676 && S_IS_LOCAL (fixp
->fx_addsy
))
21678 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21679 _("undefined local label `%s'"),
21680 S_GET_NAME (fixp
->fx_addsy
));
21684 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21685 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21692 switch (fixp
->fx_r_type
)
21694 case BFD_RELOC_NONE
: type
= "NONE"; break;
21695 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21696 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21697 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21698 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21699 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21700 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21701 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21702 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21703 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21704 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21705 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21706 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21707 default: type
= _("<unknown>"); break;
21709 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21710 _("cannot represent %s relocation in this object file format"),
21717 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21719 && fixp
->fx_addsy
== GOT_symbol
)
21721 code
= BFD_RELOC_ARM_GOTPC
;
21722 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21726 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21728 if (reloc
->howto
== NULL
)
21730 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21731 _("cannot represent %s relocation in this object file format"),
21732 bfd_get_reloc_code_name (code
));
21736 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21737 vtable entry to be used in the relocation's section offset. */
21738 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21739 reloc
->address
= fixp
->fx_offset
;
21744 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21747 cons_fix_new_arm (fragS
* frag
,
21752 bfd_reloc_code_real_type type
;
21756 FIXME: @@ Should look at CPU word size. */
21760 type
= BFD_RELOC_8
;
21763 type
= BFD_RELOC_16
;
21767 type
= BFD_RELOC_32
;
21770 type
= BFD_RELOC_64
;
21775 if (exp
->X_op
== O_secrel
)
21777 exp
->X_op
= O_symbol
;
21778 type
= BFD_RELOC_32_SECREL
;
21782 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21785 #if defined (OBJ_COFF)
21787 arm_validate_fix (fixS
* fixP
)
21789 /* If the destination of the branch is a defined symbol which does not have
21790 the THUMB_FUNC attribute, then we must be calling a function which has
21791 the (interfacearm) attribute. We look for the Thumb entry point to that
21792 function and change the branch to refer to that function instead. */
21793 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21794 && fixP
->fx_addsy
!= NULL
21795 && S_IS_DEFINED (fixP
->fx_addsy
)
21796 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21798 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21805 arm_force_relocation (struct fix
* fixp
)
21807 #if defined (OBJ_COFF) && defined (TE_PE)
21808 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21812 /* In case we have a call or a branch to a function in ARM ISA mode from
21813 a thumb function or vice-versa force the relocation. These relocations
21814 are cleared off for some cores that might have blx and simple transformations
21818 switch (fixp
->fx_r_type
)
21820 case BFD_RELOC_ARM_PCREL_JUMP
:
21821 case BFD_RELOC_ARM_PCREL_CALL
:
21822 case BFD_RELOC_THUMB_PCREL_BLX
:
21823 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21827 case BFD_RELOC_ARM_PCREL_BLX
:
21828 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21829 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21830 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21831 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21840 /* Resolve these relocations even if the symbol is extern or weak. */
21841 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21842 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21843 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21844 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21845 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21846 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21847 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21850 /* Always leave these relocations for the linker. */
21851 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21852 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21853 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21856 /* Always generate relocations against function symbols. */
21857 if (fixp
->fx_r_type
== BFD_RELOC_32
21859 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21862 return generic_force_reloc (fixp
);
21865 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21866 /* Relocations against function names must be left unadjusted,
21867 so that the linker can use this information to generate interworking
21868 stubs. The MIPS version of this function
21869 also prevents relocations that are mips-16 specific, but I do not
21870 know why it does this.
21873 There is one other problem that ought to be addressed here, but
21874 which currently is not: Taking the address of a label (rather
21875 than a function) and then later jumping to that address. Such
21876 addresses also ought to have their bottom bit set (assuming that
21877 they reside in Thumb code), but at the moment they will not. */
21880 arm_fix_adjustable (fixS
* fixP
)
21882 if (fixP
->fx_addsy
== NULL
)
21885 /* Preserve relocations against symbols with function type. */
21886 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21889 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21890 && fixP
->fx_subsy
== NULL
)
21893 /* We need the symbol name for the VTABLE entries. */
21894 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21895 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21898 /* Don't allow symbols to be discarded on GOT related relocs. */
21899 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21900 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21901 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21902 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21903 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21904 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21905 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21906 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21907 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
21908 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
21909 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
21910 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
21911 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
21912 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21915 /* Similarly for group relocations. */
21916 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21917 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21918 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21921 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21922 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21923 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21924 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21925 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21926 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21927 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21928 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21929 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21934 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21939 elf32_arm_target_format (void)
21942 return (target_big_endian
21943 ? "elf32-bigarm-symbian"
21944 : "elf32-littlearm-symbian");
21945 #elif defined (TE_VXWORKS)
21946 return (target_big_endian
21947 ? "elf32-bigarm-vxworks"
21948 : "elf32-littlearm-vxworks");
21950 if (target_big_endian
)
21951 return "elf32-bigarm";
21953 return "elf32-littlearm";
21958 armelf_frob_symbol (symbolS
* symp
,
21961 elf_frob_symbol (symp
, puntp
);
21965 /* MD interface: Finalization. */
21970 literal_pool
* pool
;
21972 /* Ensure that all the IT blocks are properly closed. */
21973 check_it_blocks_finished ();
21975 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21977 /* Put it at the end of the relevant section. */
21978 subseg_set (pool
->section
, pool
->sub_section
);
21980 arm_elf_change_section ();
21987 /* Remove any excess mapping symbols generated for alignment frags in
21988 SEC. We may have created a mapping symbol before a zero byte
21989 alignment; remove it if there's a mapping symbol after the
21992 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21993 void *dummy ATTRIBUTE_UNUSED
)
21995 segment_info_type
*seginfo
= seg_info (sec
);
21998 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
22001 for (fragp
= seginfo
->frchainP
->frch_root
;
22003 fragp
= fragp
->fr_next
)
22005 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
22006 fragS
*next
= fragp
->fr_next
;
22008 /* Variable-sized frags have been converted to fixed size by
22009 this point. But if this was variable-sized to start with,
22010 there will be a fixed-size frag after it. So don't handle
22012 if (sym
== NULL
|| next
== NULL
)
22015 if (S_GET_VALUE (sym
) < next
->fr_address
)
22016 /* Not at the end of this frag. */
22018 know (S_GET_VALUE (sym
) == next
->fr_address
);
22022 if (next
->tc_frag_data
.first_map
!= NULL
)
22024 /* Next frag starts with a mapping symbol. Discard this
22026 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22030 if (next
->fr_next
== NULL
)
22032 /* This mapping symbol is at the end of the section. Discard
22034 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
22035 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22039 /* As long as we have empty frags without any mapping symbols,
22041 /* If the next frag is non-empty and does not start with a
22042 mapping symbol, then this mapping symbol is required. */
22043 if (next
->fr_address
!= next
->fr_next
->fr_address
)
22046 next
= next
->fr_next
;
22048 while (next
!= NULL
);
22053 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22057 arm_adjust_symtab (void)
22062 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22064 if (ARM_IS_THUMB (sym
))
22066 if (THUMB_IS_FUNC (sym
))
22068 /* Mark the symbol as a Thumb function. */
22069 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
22070 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
22071 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
22073 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
22074 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
22076 as_bad (_("%s: unexpected function type: %d"),
22077 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
22079 else switch (S_GET_STORAGE_CLASS (sym
))
22082 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
22085 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
22088 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
22096 if (ARM_IS_INTERWORK (sym
))
22097 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
22104 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22106 if (ARM_IS_THUMB (sym
))
22108 elf_symbol_type
* elf_sym
;
22110 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
22111 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
22113 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
22114 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
22116 /* If it's a .thumb_func, declare it as so,
22117 otherwise tag label as .code 16. */
22118 if (THUMB_IS_FUNC (sym
))
22119 elf_sym
->internal_elf_sym
.st_target_internal
22120 = ST_BRANCH_TO_THUMB
;
22121 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22122 elf_sym
->internal_elf_sym
.st_info
=
22123 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
22128 /* Remove any overlapping mapping symbols generated by alignment frags. */
22129 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
22130 /* Now do generic ELF adjustments. */
22131 elf_adjust_symtab ();
22135 /* MD interface: Initialization. */
22138 set_constant_flonums (void)
22142 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
22143 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
22147 /* Auto-select Thumb mode if it's the only available instruction set for the
22148 given architecture. */
22151 autoselect_thumb_from_cpu_variant (void)
22153 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22154 opcode_select (16);
22163 if ( (arm_ops_hsh
= hash_new ()) == NULL
22164 || (arm_cond_hsh
= hash_new ()) == NULL
22165 || (arm_shift_hsh
= hash_new ()) == NULL
22166 || (arm_psr_hsh
= hash_new ()) == NULL
22167 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22168 || (arm_reg_hsh
= hash_new ()) == NULL
22169 || (arm_reloc_hsh
= hash_new ()) == NULL
22170 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22171 as_fatal (_("virtual memory exhausted"));
22173 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22174 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22175 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22176 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22177 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22178 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22179 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22180 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22181 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22182 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22183 (void *) (v7m_psrs
+ i
));
22184 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22185 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22187 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22189 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22190 (void *) (barrier_opt_names
+ i
));
22192 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
22193 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
22196 set_constant_flonums ();
22198 /* Set the cpu variant based on the command-line options. We prefer
22199 -mcpu= over -march= if both are set (as for GCC); and we prefer
22200 -mfpu= over any other way of setting the floating point unit.
22201 Use of legacy options with new options are faulted. */
22204 if (mcpu_cpu_opt
|| march_cpu_opt
)
22205 as_bad (_("use of old and new-style options to set CPU type"));
22207 mcpu_cpu_opt
= legacy_cpu
;
22209 else if (!mcpu_cpu_opt
)
22210 mcpu_cpu_opt
= march_cpu_opt
;
22215 as_bad (_("use of old and new-style options to set FPU type"));
22217 mfpu_opt
= legacy_fpu
;
22219 else if (!mfpu_opt
)
22221 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22222 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22223 /* Some environments specify a default FPU. If they don't, infer it
22224 from the processor. */
22226 mfpu_opt
= mcpu_fpu_opt
;
22228 mfpu_opt
= march_fpu_opt
;
22230 mfpu_opt
= &fpu_default
;
22236 if (mcpu_cpu_opt
!= NULL
)
22237 mfpu_opt
= &fpu_default
;
22238 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22239 mfpu_opt
= &fpu_arch_vfp_v2
;
22241 mfpu_opt
= &fpu_arch_fpa
;
22247 mcpu_cpu_opt
= &cpu_default
;
22248 selected_cpu
= cpu_default
;
22252 selected_cpu
= *mcpu_cpu_opt
;
22254 mcpu_cpu_opt
= &arm_arch_any
;
22257 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22259 autoselect_thumb_from_cpu_variant ();
22261 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22263 #if defined OBJ_COFF || defined OBJ_ELF
22265 unsigned int flags
= 0;
22267 #if defined OBJ_ELF
22268 flags
= meabi_flags
;
22270 switch (meabi_flags
)
22272 case EF_ARM_EABI_UNKNOWN
:
22274 /* Set the flags in the private structure. */
22275 if (uses_apcs_26
) flags
|= F_APCS26
;
22276 if (support_interwork
) flags
|= F_INTERWORK
;
22277 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22278 if (pic_code
) flags
|= F_PIC
;
22279 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22280 flags
|= F_SOFT_FLOAT
;
22282 switch (mfloat_abi_opt
)
22284 case ARM_FLOAT_ABI_SOFT
:
22285 case ARM_FLOAT_ABI_SOFTFP
:
22286 flags
|= F_SOFT_FLOAT
;
22289 case ARM_FLOAT_ABI_HARD
:
22290 if (flags
& F_SOFT_FLOAT
)
22291 as_bad (_("hard-float conflicts with specified fpu"));
22295 /* Using pure-endian doubles (even if soft-float). */
22296 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22297 flags
|= F_VFP_FLOAT
;
22299 #if defined OBJ_ELF
22300 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22301 flags
|= EF_ARM_MAVERICK_FLOAT
;
22304 case EF_ARM_EABI_VER4
:
22305 case EF_ARM_EABI_VER5
:
22306 /* No additional flags to set. */
22313 bfd_set_private_flags (stdoutput
, flags
);
22315 /* We have run out flags in the COFF header to encode the
22316 status of ATPCS support, so instead we create a dummy,
22317 empty, debug section called .arm.atpcs. */
22322 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22326 bfd_set_section_flags
22327 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22328 bfd_set_section_size (stdoutput
, sec
, 0);
22329 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22335 /* Record the CPU type as well. */
22336 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22337 mach
= bfd_mach_arm_iWMMXt2
;
22338 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22339 mach
= bfd_mach_arm_iWMMXt
;
22340 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22341 mach
= bfd_mach_arm_XScale
;
22342 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22343 mach
= bfd_mach_arm_ep9312
;
22344 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22345 mach
= bfd_mach_arm_5TE
;
22346 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22348 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22349 mach
= bfd_mach_arm_5T
;
22351 mach
= bfd_mach_arm_5
;
22353 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22355 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22356 mach
= bfd_mach_arm_4T
;
22358 mach
= bfd_mach_arm_4
;
22360 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22361 mach
= bfd_mach_arm_3M
;
22362 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22363 mach
= bfd_mach_arm_3
;
22364 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22365 mach
= bfd_mach_arm_2a
;
22366 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22367 mach
= bfd_mach_arm_2
;
22369 mach
= bfd_mach_arm_unknown
;
22371 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22374 /* Command line processing. */
22377 Invocation line includes a switch not recognized by the base assembler.
22378 See if it's a processor-specific option.
22380 This routine is somewhat complicated by the need for backwards
22381 compatibility (since older releases of gcc can't be changed).
22382 The new options try to make the interface as compatible as
22385 New options (supported) are:
22387 -mcpu=<cpu name> Assemble for selected processor
22388 -march=<architecture name> Assemble for selected architecture
22389 -mfpu=<fpu architecture> Assemble for selected FPU.
22390 -EB/-mbig-endian Big-endian
22391 -EL/-mlittle-endian Little-endian
22392 -k Generate PIC code
22393 -mthumb Start in Thumb mode
22394 -mthumb-interwork Code supports ARM/Thumb interworking
22396 -m[no-]warn-deprecated Warn about deprecated features
22398 For now we will also provide support for:
22400 -mapcs-32 32-bit Program counter
22401 -mapcs-26 26-bit Program counter
22402 -macps-float Floats passed in FP registers
22403 -mapcs-reentrant Reentrant code
22405 (sometime these will probably be replaced with -mapcs=<list of options>
22406 and -matpcs=<list of options>)
22408 The remaining options are only supported for back-wards compatibility.
22409 Cpu variants, the arm part is optional:
22410 -m[arm]1 Currently not supported.
22411 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22412 -m[arm]3 Arm 3 processor
22413 -m[arm]6[xx], Arm 6 processors
22414 -m[arm]7[xx][t][[d]m] Arm 7 processors
22415 -m[arm]8[10] Arm 8 processors
22416 -m[arm]9[20][tdmi] Arm 9 processors
22417 -mstrongarm[110[0]] StrongARM processors
22418 -mxscale XScale processors
22419 -m[arm]v[2345[t[e]]] Arm architectures
22420 -mall All (except the ARM1)
22422 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22423 -mfpe-old (No float load/store multiples)
22424 -mvfpxd VFP Single precision
22426 -mno-fpu Disable all floating point instructions
22428 The following CPU names are recognized:
22429 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22430 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22431 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22432 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22433 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22434 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22435 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22439 const char * md_shortopts
= "m:k";
22441 #ifdef ARM_BI_ENDIAN
22442 #define OPTION_EB (OPTION_MD_BASE + 0)
22443 #define OPTION_EL (OPTION_MD_BASE + 1)
22445 #if TARGET_BYTES_BIG_ENDIAN
22446 #define OPTION_EB (OPTION_MD_BASE + 0)
22448 #define OPTION_EL (OPTION_MD_BASE + 1)
22451 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22453 struct option md_longopts
[] =
22456 {"EB", no_argument
, NULL
, OPTION_EB
},
22459 {"EL", no_argument
, NULL
, OPTION_EL
},
22461 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22462 {NULL
, no_argument
, NULL
, 0}
22465 size_t md_longopts_size
= sizeof (md_longopts
);
22467 struct arm_option_table
22469 char *option
; /* Option name to match. */
22470 char *help
; /* Help information. */
22471 int *var
; /* Variable to change. */
22472 int value
; /* What to change it to. */
22473 char *deprecated
; /* If non-null, print this message. */
22476 struct arm_option_table arm_opts
[] =
22478 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22479 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22480 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22481 &support_interwork
, 1, NULL
},
22482 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22483 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22484 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22486 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22487 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22488 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22489 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22492 /* These are recognized by the assembler, but have no affect on code. */
22493 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22494 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22496 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22497 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22498 &warn_on_deprecated
, 0, NULL
},
22499 {NULL
, NULL
, NULL
, 0, NULL
}
22502 struct arm_legacy_option_table
22504 char *option
; /* Option name to match. */
22505 const arm_feature_set
**var
; /* Variable to change. */
22506 const arm_feature_set value
; /* What to change it to. */
22507 char *deprecated
; /* If non-null, print this message. */
22510 const struct arm_legacy_option_table arm_legacy_opts
[] =
22512 /* DON'T add any new processors to this list -- we want the whole list
22513 to go away... Add them to the processors table instead. */
22514 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22515 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22516 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22517 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22518 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22519 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22520 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22521 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22522 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22523 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22524 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22525 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22526 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22527 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22528 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22529 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22530 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22531 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22532 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22533 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22534 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22535 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22536 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22537 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22538 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22539 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22540 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22541 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22542 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22543 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22544 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22545 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22546 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22547 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22548 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22549 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22550 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22551 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22552 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22553 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22554 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22555 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22556 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22557 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22558 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22559 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22560 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22561 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22562 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22563 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22564 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22565 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22566 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22567 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22568 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22569 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22570 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22571 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22572 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22573 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22574 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22575 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22576 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22577 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22578 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22579 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22580 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22581 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22582 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22583 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22584 N_("use -mcpu=strongarm110")},
22585 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22586 N_("use -mcpu=strongarm1100")},
22587 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22588 N_("use -mcpu=strongarm1110")},
22589 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22590 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22591 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22593 /* Architecture variants -- don't add any more to this list either. */
22594 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22595 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22596 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22597 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22598 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22599 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22600 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22601 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22602 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22603 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22604 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22605 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22606 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22607 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22608 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22609 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22610 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22611 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22613 /* Floating point variants -- don't add any more to this list either. */
22614 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22615 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22616 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22617 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22618 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22620 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22623 struct arm_cpu_option_table
22626 const arm_feature_set value
;
22627 /* For some CPUs we assume an FPU unless the user explicitly sets
22629 const arm_feature_set default_fpu
;
22630 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22632 const char *canonical_name
;
22635 /* This list should, at a minimum, contain all the cpu names
22636 recognized by GCC. */
22637 static const struct arm_cpu_option_table arm_cpus
[] =
22639 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22640 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22641 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22642 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22643 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22644 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22645 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22646 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22647 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22648 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22649 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22650 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22651 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22652 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22653 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22654 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22655 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22656 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22657 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22658 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22659 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22660 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22661 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22662 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22663 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22664 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22665 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22666 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22667 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22668 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22669 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22670 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22671 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22672 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22673 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22674 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22675 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22676 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22677 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22678 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22679 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22680 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22681 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22682 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22683 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22684 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22685 /* For V5 or later processors we default to using VFP; but the user
22686 should really set the FPU type explicitly. */
22687 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22688 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22689 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22690 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22691 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22692 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22693 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22694 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22695 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22696 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22697 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22698 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22699 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22700 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22701 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22702 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22703 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22704 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22705 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22706 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22707 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22708 {"fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22709 {"fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22710 {"fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22711 {"fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22712 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22713 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22714 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22715 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22716 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22717 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22718 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22719 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22720 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22721 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22722 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22723 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22724 FPU_NONE
, "Cortex-A5"},
22725 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22726 ARM_FEATURE (0, FPU_VFP_V3
22727 | FPU_NEON_EXT_V1
),
22729 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22730 ARM_FEATURE (0, FPU_VFP_V3
22731 | FPU_NEON_EXT_V1
),
22733 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22734 FPU_ARCH_NEON_VFP_V4
,
22736 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22737 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22739 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22740 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22741 {"cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"},
22742 {"cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"},
22743 /* ??? XSCALE is really an architecture. */
22744 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22745 /* ??? iwmmxt is not a processor. */
22746 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22747 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22748 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22750 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22751 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22754 struct arm_arch_option_table
22757 const arm_feature_set value
;
22758 const arm_feature_set default_fpu
;
22761 /* This list should, at a minimum, contain all the architecture names
22762 recognized by GCC. */
22763 static const struct arm_arch_option_table arm_archs
[] =
22765 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22766 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22767 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22768 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22769 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22770 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22771 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22772 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22773 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22774 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22775 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22776 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22777 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22778 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22779 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22780 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22781 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22782 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22783 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22784 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22785 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22786 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22787 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22788 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22789 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22790 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22791 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22792 {"armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
},
22793 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22794 /* The official spelling of the ARMv7 profile variants is the dashed form.
22795 Accept the non-dashed form for compatibility with old toolchains. */
22796 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22797 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22798 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22799 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22800 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22801 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22802 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22803 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22804 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22805 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22806 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22809 /* ISA extensions in the co-processor and main instruction set space. */
22810 struct arm_option_extension_value_table
22813 const arm_feature_set value
;
22814 const arm_feature_set allowed_archs
;
22817 /* The following table must be in alphabetical order with a NULL last entry.
22819 static const struct arm_option_extension_value_table arm_extensions
[] =
22821 {"idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22822 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22823 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
22824 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
22825 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
22826 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
22827 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22828 {"os", ARM_FEATURE (ARM_EXT_OS
, 0),
22829 ARM_FEATURE (ARM_EXT_V6M
, 0)},
22830 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
22831 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
22832 {"virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22833 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22834 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
22835 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22838 /* ISA floating-point and Advanced SIMD extensions. */
22839 struct arm_option_fpu_value_table
22842 const arm_feature_set value
;
22845 /* This list should, at a minimum, contain all the fpu names
22846 recognized by GCC. */
22847 static const struct arm_option_fpu_value_table arm_fpus
[] =
22849 {"softfpa", FPU_NONE
},
22850 {"fpe", FPU_ARCH_FPE
},
22851 {"fpe2", FPU_ARCH_FPE
},
22852 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22853 {"fpa", FPU_ARCH_FPA
},
22854 {"fpa10", FPU_ARCH_FPA
},
22855 {"fpa11", FPU_ARCH_FPA
},
22856 {"arm7500fe", FPU_ARCH_FPA
},
22857 {"softvfp", FPU_ARCH_VFP
},
22858 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22859 {"vfp", FPU_ARCH_VFP_V2
},
22860 {"vfp9", FPU_ARCH_VFP_V2
},
22861 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22862 {"vfp10", FPU_ARCH_VFP_V2
},
22863 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22864 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22865 {"vfpv2", FPU_ARCH_VFP_V2
},
22866 {"vfpv3", FPU_ARCH_VFP_V3
},
22867 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22868 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22869 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22870 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22871 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22872 {"arm1020t", FPU_ARCH_VFP_V1
},
22873 {"arm1020e", FPU_ARCH_VFP_V2
},
22874 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22875 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22876 {"maverick", FPU_ARCH_MAVERICK
},
22877 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22878 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22879 {"vfpv4", FPU_ARCH_VFP_V4
},
22880 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22881 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22882 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22883 {NULL
, ARM_ARCH_NONE
}
22886 struct arm_option_value_table
22892 static const struct arm_option_value_table arm_float_abis
[] =
22894 {"hard", ARM_FLOAT_ABI_HARD
},
22895 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22896 {"soft", ARM_FLOAT_ABI_SOFT
},
22901 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22902 static const struct arm_option_value_table arm_eabis
[] =
22904 {"gnu", EF_ARM_EABI_UNKNOWN
},
22905 {"4", EF_ARM_EABI_VER4
},
22906 {"5", EF_ARM_EABI_VER5
},
22911 struct arm_long_option_table
22913 char * option
; /* Substring to match. */
22914 char * help
; /* Help information. */
22915 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22916 char * deprecated
; /* If non-null, print this message. */
22920 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22922 arm_feature_set
*ext_set
= (arm_feature_set
*)
22923 xmalloc (sizeof (arm_feature_set
));
22925 /* We insist on extensions being specified in alphabetical order, and with
22926 extensions being added before being removed. We achieve this by having
22927 the global ARM_EXTENSIONS table in alphabetical order, and using the
22928 ADDING_VALUE variable to indicate whether we are adding an extension (1)
22929 or removing it (0) and only allowing it to change in the order
22931 const struct arm_option_extension_value_table
* opt
= NULL
;
22932 int adding_value
= -1;
22934 /* Copy the feature set, so that we can modify it. */
22935 *ext_set
= **opt_p
;
22938 while (str
!= NULL
&& *str
!= 0)
22945 as_bad (_("invalid architectural extension"));
22950 ext
= strchr (str
, '+');
22953 optlen
= ext
- str
;
22955 optlen
= strlen (str
);
22958 && strncmp (str
, "no", 2) == 0)
22960 if (adding_value
!= 0)
22963 opt
= arm_extensions
;
22969 else if (optlen
> 0)
22971 if (adding_value
== -1)
22974 opt
= arm_extensions
;
22976 else if (adding_value
!= 1)
22978 as_bad (_("must specify extensions to add before specifying "
22979 "those to remove"));
22986 as_bad (_("missing architectural extension"));
22990 gas_assert (adding_value
!= -1);
22991 gas_assert (opt
!= NULL
);
22993 /* Scan over the options table trying to find an exact match. */
22994 for (; opt
->name
!= NULL
; opt
++)
22995 if (strncmp (opt
->name
, str
, optlen
) == 0
22996 && strlen (opt
->name
) == optlen
)
22998 /* Check we can apply the extension to this architecture. */
22999 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
23001 as_bad (_("extension does not apply to the base architecture"));
23005 /* Add or remove the extension. */
23007 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
23009 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
23014 if (opt
->name
== NULL
)
23016 /* Did we fail to find an extension because it wasn't specified in
23017 alphabetical order, or because it does not exist? */
23019 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23020 if (strncmp (opt
->name
, str
, optlen
) == 0)
23023 if (opt
->name
== NULL
)
23024 as_bad (_("unknown architectural extension `%s'"), str
);
23026 as_bad (_("architectural extensions must be specified in "
23027 "alphabetical order"));
23033 /* We should skip the extension we've just matched the next time
23045 arm_parse_cpu (char * str
)
23047 const struct arm_cpu_option_table
* opt
;
23048 char * ext
= strchr (str
, '+');
23052 optlen
= ext
- str
;
23054 optlen
= strlen (str
);
23058 as_bad (_("missing cpu name `%s'"), str
);
23062 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
23063 if (strncmp (opt
->name
, str
, optlen
) == 0)
23065 mcpu_cpu_opt
= &opt
->value
;
23066 mcpu_fpu_opt
= &opt
->default_fpu
;
23067 if (opt
->canonical_name
)
23068 strcpy (selected_cpu_name
, opt
->canonical_name
);
23073 for (i
= 0; i
< optlen
; i
++)
23074 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23075 selected_cpu_name
[i
] = 0;
23079 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
23084 as_bad (_("unknown cpu `%s'"), str
);
23089 arm_parse_arch (char * str
)
23091 const struct arm_arch_option_table
*opt
;
23092 char *ext
= strchr (str
, '+');
23096 optlen
= ext
- str
;
23098 optlen
= strlen (str
);
23102 as_bad (_("missing architecture name `%s'"), str
);
23106 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
23107 if (strncmp (opt
->name
, str
, optlen
) == 0)
23109 march_cpu_opt
= &opt
->value
;
23110 march_fpu_opt
= &opt
->default_fpu
;
23111 strcpy (selected_cpu_name
, opt
->name
);
23114 return arm_parse_extension (ext
, &march_cpu_opt
);
23119 as_bad (_("unknown architecture `%s'\n"), str
);
23124 arm_parse_fpu (char * str
)
23126 const struct arm_option_fpu_value_table
* opt
;
23128 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23129 if (streq (opt
->name
, str
))
23131 mfpu_opt
= &opt
->value
;
23135 as_bad (_("unknown floating point format `%s'\n"), str
);
23140 arm_parse_float_abi (char * str
)
23142 const struct arm_option_value_table
* opt
;
23144 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
23145 if (streq (opt
->name
, str
))
23147 mfloat_abi_opt
= opt
->value
;
23151 as_bad (_("unknown floating point abi `%s'\n"), str
);
23157 arm_parse_eabi (char * str
)
23159 const struct arm_option_value_table
*opt
;
23161 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
23162 if (streq (opt
->name
, str
))
23164 meabi_flags
= opt
->value
;
23167 as_bad (_("unknown EABI `%s'\n"), str
);
23173 arm_parse_it_mode (char * str
)
23175 bfd_boolean ret
= TRUE
;
23177 if (streq ("arm", str
))
23178 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23179 else if (streq ("thumb", str
))
23180 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23181 else if (streq ("always", str
))
23182 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23183 else if (streq ("never", str
))
23184 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23187 as_bad (_("unknown implicit IT mode `%s', should be "\
23188 "arm, thumb, always, or never."), str
);
23195 struct arm_long_option_table arm_long_opts
[] =
23197 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23198 arm_parse_cpu
, NULL
},
23199 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23200 arm_parse_arch
, NULL
},
23201 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23202 arm_parse_fpu
, NULL
},
23203 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23204 arm_parse_float_abi
, NULL
},
23206 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23207 arm_parse_eabi
, NULL
},
23209 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23210 arm_parse_it_mode
, NULL
},
23211 {NULL
, NULL
, 0, NULL
}
23215 md_parse_option (int c
, char * arg
)
23217 struct arm_option_table
*opt
;
23218 const struct arm_legacy_option_table
*fopt
;
23219 struct arm_long_option_table
*lopt
;
23225 target_big_endian
= 1;
23231 target_big_endian
= 0;
23235 case OPTION_FIX_V4BX
:
23240 /* Listing option. Just ignore these, we don't support additional
23245 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23247 if (c
== opt
->option
[0]
23248 && ((arg
== NULL
&& opt
->option
[1] == 0)
23249 || streq (arg
, opt
->option
+ 1)))
23251 /* If the option is deprecated, tell the user. */
23252 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23253 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23254 arg
? arg
: "", _(opt
->deprecated
));
23256 if (opt
->var
!= NULL
)
23257 *opt
->var
= opt
->value
;
23263 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23265 if (c
== fopt
->option
[0]
23266 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23267 || streq (arg
, fopt
->option
+ 1)))
23269 /* If the option is deprecated, tell the user. */
23270 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23271 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23272 arg
? arg
: "", _(fopt
->deprecated
));
23274 if (fopt
->var
!= NULL
)
23275 *fopt
->var
= &fopt
->value
;
23281 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23283 /* These options are expected to have an argument. */
23284 if (c
== lopt
->option
[0]
23286 && strncmp (arg
, lopt
->option
+ 1,
23287 strlen (lopt
->option
+ 1)) == 0)
23289 /* If the option is deprecated, tell the user. */
23290 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23291 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23292 _(lopt
->deprecated
));
23294 /* Call the sup-option parser. */
23295 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23306 md_show_usage (FILE * fp
)
23308 struct arm_option_table
*opt
;
23309 struct arm_long_option_table
*lopt
;
23311 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23313 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23314 if (opt
->help
!= NULL
)
23315 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23317 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23318 if (lopt
->help
!= NULL
)
23319 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23323 -EB assemble code for a big-endian cpu\n"));
23328 -EL assemble code for a little-endian cpu\n"));
23332 --fix-v4bx Allow BX in ARMv4 code\n"));
23340 arm_feature_set flags
;
23341 } cpu_arch_ver_table
;
23343 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23344 least features first. */
23345 static const cpu_arch_ver_table cpu_arch_ver
[] =
23351 {4, ARM_ARCH_V5TE
},
23352 {5, ARM_ARCH_V5TEJ
},
23356 {11, ARM_ARCH_V6M
},
23357 {12, ARM_ARCH_V6SM
},
23358 {8, ARM_ARCH_V6T2
},
23359 {10, ARM_ARCH_V7A
},
23360 {10, ARM_ARCH_V7R
},
23361 {10, ARM_ARCH_V7M
},
23365 /* Set an attribute if it has not already been set by the user. */
23367 aeabi_set_attribute_int (int tag
, int value
)
23370 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23371 || !attributes_set_explicitly
[tag
])
23372 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23376 aeabi_set_attribute_string (int tag
, const char *value
)
23379 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23380 || !attributes_set_explicitly
[tag
])
23381 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23384 /* Set the public EABI object attributes. */
23386 aeabi_set_public_attributes (void)
23390 arm_feature_set flags
;
23391 arm_feature_set tmp
;
23392 const cpu_arch_ver_table
*p
;
23394 /* Choose the architecture based on the capabilities of the requested cpu
23395 (if any) and/or the instructions actually used. */
23396 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23397 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23398 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23399 /*Allow the user to override the reported architecture. */
23402 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23403 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23406 /* We need to make sure that the attributes do not identify us as v6S-M
23407 when the only v6S-M feature in use is the Operating System Extensions. */
23408 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
23409 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
23410 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
23414 for (p
= cpu_arch_ver
; p
->val
; p
++)
23416 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23419 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23423 /* The table lookup above finds the last architecture to contribute
23424 a new feature. Unfortunately, Tag13 is a subset of the union of
23425 v6T2 and v7-M, so it is never seen as contributing a new feature.
23426 We can not search for the last entry which is entirely used,
23427 because if no CPU is specified we build up only those flags
23428 actually used. Perhaps we should separate out the specified
23429 and implicit cases. Avoid taking this path for -march=all by
23430 checking for contradictory v7-A / v7-M features. */
23432 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23433 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23434 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23437 /* Tag_CPU_name. */
23438 if (selected_cpu_name
[0])
23442 q
= selected_cpu_name
;
23443 if (strncmp (q
, "armv", 4) == 0)
23448 for (i
= 0; q
[i
]; i
++)
23449 q
[i
] = TOUPPER (q
[i
]);
23451 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23454 /* Tag_CPU_arch. */
23455 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23457 /* Tag_CPU_arch_profile. */
23458 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23459 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23460 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23461 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23462 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23463 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23465 /* Tag_ARM_ISA_use. */
23466 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23468 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23470 /* Tag_THUMB_ISA_use. */
23471 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23473 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23474 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23476 /* Tag_VFP_arch. */
23477 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23478 aeabi_set_attribute_int (Tag_VFP_arch
,
23479 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23481 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23482 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23483 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23484 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23485 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23486 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23487 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23488 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23489 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23491 /* Tag_ABI_HardFP_use. */
23492 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23493 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23494 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23496 /* Tag_WMMX_arch. */
23497 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23498 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23499 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23500 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23502 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23503 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23504 aeabi_set_attribute_int
23505 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23508 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23509 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23510 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23513 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
))
23514 aeabi_set_attribute_int (Tag_DIV_use
, 2);
23515 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23516 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23518 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23520 /* Tag_MP_extension_use. */
23521 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23522 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23524 /* Tag Virtualization_use. */
23525 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23527 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
23530 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
23533 /* Add the default contents for the .ARM.attributes section. */
23537 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23540 aeabi_set_public_attributes ();
23542 #endif /* OBJ_ELF */
23545 /* Parse a .cpu directive. */
23548 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23550 const struct arm_cpu_option_table
*opt
;
23554 name
= input_line_pointer
;
23555 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23556 input_line_pointer
++;
23557 saved_char
= *input_line_pointer
;
23558 *input_line_pointer
= 0;
23560 /* Skip the first "all" entry. */
23561 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23562 if (streq (opt
->name
, name
))
23564 mcpu_cpu_opt
= &opt
->value
;
23565 selected_cpu
= opt
->value
;
23566 if (opt
->canonical_name
)
23567 strcpy (selected_cpu_name
, opt
->canonical_name
);
23571 for (i
= 0; opt
->name
[i
]; i
++)
23572 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23573 selected_cpu_name
[i
] = 0;
23575 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23576 *input_line_pointer
= saved_char
;
23577 demand_empty_rest_of_line ();
23580 as_bad (_("unknown cpu `%s'"), name
);
23581 *input_line_pointer
= saved_char
;
23582 ignore_rest_of_line ();
23586 /* Parse a .arch directive. */
23589 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23591 const struct arm_arch_option_table
*opt
;
23595 name
= input_line_pointer
;
23596 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23597 input_line_pointer
++;
23598 saved_char
= *input_line_pointer
;
23599 *input_line_pointer
= 0;
23601 /* Skip the first "all" entry. */
23602 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23603 if (streq (opt
->name
, name
))
23605 mcpu_cpu_opt
= &opt
->value
;
23606 selected_cpu
= opt
->value
;
23607 strcpy (selected_cpu_name
, opt
->name
);
23608 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23609 *input_line_pointer
= saved_char
;
23610 demand_empty_rest_of_line ();
23614 as_bad (_("unknown architecture `%s'\n"), name
);
23615 *input_line_pointer
= saved_char
;
23616 ignore_rest_of_line ();
23620 /* Parse a .object_arch directive. */
23623 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23625 const struct arm_arch_option_table
*opt
;
23629 name
= input_line_pointer
;
23630 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23631 input_line_pointer
++;
23632 saved_char
= *input_line_pointer
;
23633 *input_line_pointer
= 0;
23635 /* Skip the first "all" entry. */
23636 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23637 if (streq (opt
->name
, name
))
23639 object_arch
= &opt
->value
;
23640 *input_line_pointer
= saved_char
;
23641 demand_empty_rest_of_line ();
23645 as_bad (_("unknown architecture `%s'\n"), name
);
23646 *input_line_pointer
= saved_char
;
23647 ignore_rest_of_line ();
23650 /* Parse a .arch_extension directive. */
23653 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23655 const struct arm_option_extension_value_table
*opt
;
23658 int adding_value
= 1;
23660 name
= input_line_pointer
;
23661 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23662 input_line_pointer
++;
23663 saved_char
= *input_line_pointer
;
23664 *input_line_pointer
= 0;
23666 if (strlen (name
) >= 2
23667 && strncmp (name
, "no", 2) == 0)
23673 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23674 if (streq (opt
->name
, name
))
23676 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23678 as_bad (_("architectural extension `%s' is not allowed for the "
23679 "current base architecture"), name
);
23684 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23686 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23688 mcpu_cpu_opt
= &selected_cpu
;
23689 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23690 *input_line_pointer
= saved_char
;
23691 demand_empty_rest_of_line ();
23695 if (opt
->name
== NULL
)
23696 as_bad (_("unknown architecture `%s'\n"), name
);
23698 *input_line_pointer
= saved_char
;
23699 ignore_rest_of_line ();
23702 /* Parse a .fpu directive. */
23705 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23707 const struct arm_option_fpu_value_table
*opt
;
23711 name
= input_line_pointer
;
23712 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23713 input_line_pointer
++;
23714 saved_char
= *input_line_pointer
;
23715 *input_line_pointer
= 0;
23717 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23718 if (streq (opt
->name
, name
))
23720 mfpu_opt
= &opt
->value
;
23721 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23722 *input_line_pointer
= saved_char
;
23723 demand_empty_rest_of_line ();
23727 as_bad (_("unknown floating point format `%s'\n"), name
);
23728 *input_line_pointer
= saved_char
;
23729 ignore_rest_of_line ();
23732 /* Copy symbol information. */
23735 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23737 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23741 /* Given a symbolic attribute NAME, return the proper integer value.
23742 Returns -1 if the attribute is not known. */
23745 arm_convert_symbolic_attribute (const char *name
)
23747 static const struct
23752 attribute_table
[] =
23754 /* When you modify this table you should
23755 also modify the list in doc/c-arm.texi. */
23756 #define T(tag) {#tag, tag}
23757 T (Tag_CPU_raw_name
),
23760 T (Tag_CPU_arch_profile
),
23761 T (Tag_ARM_ISA_use
),
23762 T (Tag_THUMB_ISA_use
),
23766 T (Tag_Advanced_SIMD_arch
),
23767 T (Tag_PCS_config
),
23768 T (Tag_ABI_PCS_R9_use
),
23769 T (Tag_ABI_PCS_RW_data
),
23770 T (Tag_ABI_PCS_RO_data
),
23771 T (Tag_ABI_PCS_GOT_use
),
23772 T (Tag_ABI_PCS_wchar_t
),
23773 T (Tag_ABI_FP_rounding
),
23774 T (Tag_ABI_FP_denormal
),
23775 T (Tag_ABI_FP_exceptions
),
23776 T (Tag_ABI_FP_user_exceptions
),
23777 T (Tag_ABI_FP_number_model
),
23778 T (Tag_ABI_align_needed
),
23779 T (Tag_ABI_align8_needed
),
23780 T (Tag_ABI_align_preserved
),
23781 T (Tag_ABI_align8_preserved
),
23782 T (Tag_ABI_enum_size
),
23783 T (Tag_ABI_HardFP_use
),
23784 T (Tag_ABI_VFP_args
),
23785 T (Tag_ABI_WMMX_args
),
23786 T (Tag_ABI_optimization_goals
),
23787 T (Tag_ABI_FP_optimization_goals
),
23788 T (Tag_compatibility
),
23789 T (Tag_CPU_unaligned_access
),
23790 T (Tag_FP_HP_extension
),
23791 T (Tag_VFP_HP_extension
),
23792 T (Tag_ABI_FP_16bit_format
),
23793 T (Tag_MPextension_use
),
23795 T (Tag_nodefaults
),
23796 T (Tag_also_compatible_with
),
23797 T (Tag_conformance
),
23799 T (Tag_Virtualization_use
),
23800 /* We deliberately do not include Tag_MPextension_use_legacy. */
23808 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23809 if (streq (name
, attribute_table
[i
].name
))
23810 return attribute_table
[i
].tag
;
23816 /* Apply sym value for relocations only in the case that
23817 they are for local symbols and you have the respective
23818 architectural feature for blx and simple switches. */
23820 arm_apply_sym_value (struct fix
* fixP
)
23823 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23824 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
23826 switch (fixP
->fx_r_type
)
23828 case BFD_RELOC_ARM_PCREL_BLX
:
23829 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23830 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23834 case BFD_RELOC_ARM_PCREL_CALL
:
23835 case BFD_RELOC_THUMB_PCREL_BLX
:
23836 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23847 #endif /* OBJ_ELF */