1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
40 #include "opcode/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
60 symbolS
* table_entry
;
61 symbolS
* personality_routine
;
62 int personality_index
;
63 /* The segment containing the function. */
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes
;
70 /* The number of bytes pushed to the stack. */
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset
;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
80 /* Nonzero if an unwind_setfp directive has been seen. */
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored
:1;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency
= 0;
100 /* Types of processor to assemble for. */
102 #if defined __XSCALE__
103 #define CPU_DEFAULT ARM_ARCH_XSCALE
105 #if defined __thumb__
106 #define CPU_DEFAULT ARM_ARCH_V5T
113 # define FPU_DEFAULT FPU_ARCH_FPA
114 # elif defined (TE_NetBSD)
116 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
118 /* Legacy a.out format. */
119 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
121 # elif defined (TE_VXWORKS)
122 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
124 /* For backwards compatibility, default to FPA. */
125 # define FPU_DEFAULT FPU_ARCH_FPA
127 #endif /* ifndef FPU_DEFAULT */
129 #define streq(a, b) (strcmp (a, b) == 0)
131 static arm_feature_set cpu_variant
;
132 static arm_feature_set arm_arch_used
;
133 static arm_feature_set thumb_arch_used
;
135 /* Flags stored in private area of BFD structure. */
136 static int uses_apcs_26
= FALSE
;
137 static int atpcs
= FALSE
;
138 static int support_interwork
= FALSE
;
139 static int uses_apcs_float
= FALSE
;
140 static int pic_code
= FALSE
;
142 /* Variables that we set while parsing command-line options. Once all
143 options have been read we re-process these values to set the real
145 static const arm_feature_set
*legacy_cpu
= NULL
;
146 static const arm_feature_set
*legacy_fpu
= NULL
;
148 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
149 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
150 static const arm_feature_set
*march_cpu_opt
= NULL
;
151 static const arm_feature_set
*march_fpu_opt
= NULL
;
152 static const arm_feature_set
*mfpu_opt
= NULL
;
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
156 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
157 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
158 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
159 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
160 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
161 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
164 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
167 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
168 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
169 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
170 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
171 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
172 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
173 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
174 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
175 static const arm_feature_set arm_ext_v4t_5
=
176 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
177 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
178 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
179 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
180 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
181 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
182 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
183 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
184 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
186 static const arm_feature_set arm_arch_any
= ARM_ANY
;
187 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
188 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
189 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
191 static const arm_feature_set arm_cext_iwmmxt
=
192 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
193 static const arm_feature_set arm_cext_xscale
=
194 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
195 static const arm_feature_set arm_cext_maverick
=
196 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
197 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
198 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
199 static const arm_feature_set fpu_vfp_ext_v1xd
=
200 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
201 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
202 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
204 static int mfloat_abi_opt
= -1;
205 /* Record user cpu selection for object attributes. */
206 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
207 /* Must be long enough to hold any of the names in arm_cpus. */
208 static char selected_cpu_name
[16];
211 static int meabi_flags
= EABI_DEFAULT
;
213 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
218 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
219 symbolS
* GOT_symbol
;
222 /* 0: assemble for ARM,
223 1: assemble for Thumb,
224 2: assemble for Thumb even though target CPU does not support thumb
226 static int thumb_mode
= 0;
228 /* If unified_syntax is true, we are processing the new unified
229 ARM/Thumb syntax. Important differences from the old ARM mode:
231 - Immediate operands do not require a # prefix.
232 - Conditional affixes always appear at the end of the
233 instruction. (For backward compatibility, those instructions
234 that formerly had them in the middle, continue to accept them
236 - The IT instruction may appear, and if it does is validated
237 against subsequent conditional affixes. It does not generate
240 Important differences from the old Thumb mode:
242 - Immediate operands do not require a # prefix.
243 - Most of the V6T2 instructions are only available in unified mode.
244 - The .N and .W suffixes are recognized and honored (it is an error
245 if they cannot be honored).
246 - All instructions set the flags if and only if they have an 's' affix.
247 - Conditional affixes may be used. They are validated against
248 preceding IT instructions. Unlike ARM mode, you cannot use a
249 conditional affix except in the scope of an IT instruction. */
251 static bfd_boolean unified_syntax
= FALSE
;
256 unsigned long instruction
;
260 /* Set to the opcode if the instruction needs relaxation.
261 Zero if the instruction is not relaxed. */
265 bfd_reloc_code_real_type type
;
274 unsigned present
: 1; /* Operand present. */
275 unsigned isreg
: 1; /* Operand was a register. */
276 unsigned immisreg
: 1; /* .imm field is a second register. */
277 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
278 unsigned writeback
: 1; /* Operand has trailing ! */
279 unsigned preind
: 1; /* Preindexed address. */
280 unsigned postind
: 1; /* Postindexed address. */
281 unsigned negative
: 1; /* Index register was negated. */
282 unsigned shifted
: 1; /* Shift applied to operation. */
283 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
287 static struct arm_it inst
;
289 #define NUM_FLOAT_VALS 8
291 const char * fp_const
[] =
293 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
296 /* Number of littlenums required to hold an extended precision number. */
297 #define MAX_LITTLENUMS 6
299 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
309 #define CP_T_X 0x00008000
310 #define CP_T_Y 0x00400000
312 #define CONDS_BIT 0x00100000
313 #define LOAD_BIT 0x00100000
315 #define DOUBLE_LOAD_FLAG 0x00000001
319 const char * template;
323 #define COND_ALWAYS 0xE
327 const char *template;
331 /* The bit that distinguishes CPSR and SPSR. */
332 #define SPSR_BIT (1 << 22)
334 /* The individual PSR flag bits. */
335 #define PSR_c (1 << 16)
336 #define PSR_x (1 << 17)
337 #define PSR_s (1 << 18)
338 #define PSR_f (1 << 19)
343 bfd_reloc_code_real_type reloc
;
348 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
353 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
356 /* ARM register categories. This includes coprocessor numbers and various
357 architecture extensions' registers. */
379 /* Structure for a hash table entry for a register. */
383 unsigned char number
;
385 unsigned char builtin
;
388 /* Diagnostics used when we don't get a register of the expected type. */
389 const char *const reg_expected_msgs
[] =
391 N_("ARM register expected"),
392 N_("bad or missing co-processor number"),
393 N_("co-processor register expected"),
394 N_("FPA register expected"),
395 N_("VFP single precision register expected"),
396 N_("VFP double precision register expected"),
397 N_("VFP system register expected"),
398 N_("Maverick MVF register expected"),
399 N_("Maverick MVD register expected"),
400 N_("Maverick MVFX register expected"),
401 N_("Maverick MVDX register expected"),
402 N_("Maverick MVAX register expected"),
403 N_("Maverick DSPSC register expected"),
404 N_("iWMMXt data register expected"),
405 N_("iWMMXt control register expected"),
406 N_("iWMMXt scalar register expected"),
407 N_("XScale accumulator register expected"),
410 /* Some well known registers that we refer to directly elsewhere. */
415 /* ARM instructions take 4bytes in the object file, Thumb instructions
421 /* Basic string to match. */
422 const char *template;
424 /* Parameters to instruction. */
425 unsigned char operands
[8];
427 /* Conditional tag - see opcode_lookup. */
428 unsigned int tag
: 4;
430 /* Basic instruction code. */
431 unsigned int avalue
: 28;
433 /* Thumb-format instruction code. */
436 /* Which architecture variant provides this instruction. */
437 const arm_feature_set
*avariant
;
438 const arm_feature_set
*tvariant
;
440 /* Function to call to encode instruction in ARM format. */
441 void (* aencode
) (void);
443 /* Function to call to encode instruction in Thumb format. */
444 void (* tencode
) (void);
447 /* Defines for various bits that we will want to toggle. */
448 #define INST_IMMEDIATE 0x02000000
449 #define OFFSET_REG 0x02000000
450 #define HWOFFSET_IMM 0x00400000
451 #define SHIFT_BY_REG 0x00000010
452 #define PRE_INDEX 0x01000000
453 #define INDEX_UP 0x00800000
454 #define WRITE_BACK 0x00200000
455 #define LDM_TYPE_2_OR_3 0x00400000
457 #define LITERAL_MASK 0xf000f000
458 #define OPCODE_MASK 0xfe1fffff
459 #define V4_STR_BIT 0x00000020
461 #define DATA_OP_SHIFT 21
463 /* Codes to distinguish the arithmetic instructions. */
474 #define OPCODE_CMP 10
475 #define OPCODE_CMN 11
476 #define OPCODE_ORR 12
477 #define OPCODE_MOV 13
478 #define OPCODE_BIC 14
479 #define OPCODE_MVN 15
481 #define T_OPCODE_MUL 0x4340
482 #define T_OPCODE_TST 0x4200
483 #define T_OPCODE_CMN 0x42c0
484 #define T_OPCODE_NEG 0x4240
485 #define T_OPCODE_MVN 0x43c0
487 #define T_OPCODE_ADD_R3 0x1800
488 #define T_OPCODE_SUB_R3 0x1a00
489 #define T_OPCODE_ADD_HI 0x4400
490 #define T_OPCODE_ADD_ST 0xb000
491 #define T_OPCODE_SUB_ST 0xb080
492 #define T_OPCODE_ADD_SP 0xa800
493 #define T_OPCODE_ADD_PC 0xa000
494 #define T_OPCODE_ADD_I8 0x3000
495 #define T_OPCODE_SUB_I8 0x3800
496 #define T_OPCODE_ADD_I3 0x1c00
497 #define T_OPCODE_SUB_I3 0x1e00
499 #define T_OPCODE_ASR_R 0x4100
500 #define T_OPCODE_LSL_R 0x4080
501 #define T_OPCODE_LSR_R 0x40c0
502 #define T_OPCODE_ROR_R 0x41c0
503 #define T_OPCODE_ASR_I 0x1000
504 #define T_OPCODE_LSL_I 0x0000
505 #define T_OPCODE_LSR_I 0x0800
507 #define T_OPCODE_MOV_I8 0x2000
508 #define T_OPCODE_CMP_I8 0x2800
509 #define T_OPCODE_CMP_LR 0x4280
510 #define T_OPCODE_MOV_HR 0x4600
511 #define T_OPCODE_CMP_HR 0x4500
513 #define T_OPCODE_LDR_PC 0x4800
514 #define T_OPCODE_LDR_SP 0x9800
515 #define T_OPCODE_STR_SP 0x9000
516 #define T_OPCODE_LDR_IW 0x6800
517 #define T_OPCODE_STR_IW 0x6000
518 #define T_OPCODE_LDR_IH 0x8800
519 #define T_OPCODE_STR_IH 0x8000
520 #define T_OPCODE_LDR_IB 0x7800
521 #define T_OPCODE_STR_IB 0x7000
522 #define T_OPCODE_LDR_RW 0x5800
523 #define T_OPCODE_STR_RW 0x5000
524 #define T_OPCODE_LDR_RH 0x5a00
525 #define T_OPCODE_STR_RH 0x5200
526 #define T_OPCODE_LDR_RB 0x5c00
527 #define T_OPCODE_STR_RB 0x5400
529 #define T_OPCODE_PUSH 0xb400
530 #define T_OPCODE_POP 0xbc00
532 #define T_OPCODE_BRANCH 0xe000
534 #define THUMB_SIZE 2 /* Size of thumb instruction. */
535 #define THUMB_PP_PC_LR 0x0100
536 #define THUMB_LOAD_BIT 0x0800
538 #define BAD_ARGS _("bad arguments to instruction")
539 #define BAD_PC _("r15 not allowed here")
540 #define BAD_COND _("instruction cannot be conditional")
541 #define BAD_OVERLAP _("registers may not be the same")
542 #define BAD_HIREG _("lo register required")
543 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
544 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
546 static struct hash_control
*arm_ops_hsh
;
547 static struct hash_control
*arm_cond_hsh
;
548 static struct hash_control
*arm_shift_hsh
;
549 static struct hash_control
*arm_psr_hsh
;
550 static struct hash_control
*arm_reg_hsh
;
551 static struct hash_control
*arm_reloc_hsh
;
553 /* Stuff needed to resolve the label ambiguity
563 symbolS
* last_label_seen
;
564 static int label_is_thumb_function_name
= FALSE
;
566 /* Literal pool structure. Held on a per-section
567 and per-sub-section basis. */
569 #define MAX_LITERAL_POOL_SIZE 1024
570 typedef struct literal_pool
572 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
573 unsigned int next_free_entry
;
578 struct literal_pool
* next
;
581 /* Pointer to a linked list of literal pools. */
582 literal_pool
* list_of_pools
= NULL
;
584 /* State variables for IT block handling. */
585 static bfd_boolean current_it_mask
= 0;
586 static int current_cc
;
591 /* This array holds the chars that always start a comment. If the
592 pre-processor is disabled, these aren't very useful. */
593 const char comment_chars
[] = "@";
595 /* This array holds the chars that only start a comment at the beginning of
596 a line. If the line seems to have the form '# 123 filename'
597 .line and .file directives will appear in the pre-processed output. */
598 /* Note that input_file.c hand checks for '#' at the beginning of the
599 first line of the input file. This is because the compiler outputs
600 #NO_APP at the beginning of its output. */
601 /* Also note that comments like this one will always work. */
602 const char line_comment_chars
[] = "#";
604 const char line_separator_chars
[] = ";";
606 /* Chars that can be used to separate mant
607 from exp in floating point numbers. */
608 const char EXP_CHARS
[] = "eE";
610 /* Chars that mean this number is a floating point constant. */
614 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
616 /* Prefix characters that indicate the start of an immediate
618 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
620 /* Separator character handling. */
622 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
625 skip_past_char (char ** str
, char c
)
635 #define skip_past_comma(str) skip_past_char (str, ',')
637 /* Arithmetic expressions (possibly involving symbols). */
639 /* Return TRUE if anything in the expression is a bignum. */
642 walk_no_bignums (symbolS
* sp
)
644 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
647 if (symbol_get_value_expression (sp
)->X_add_symbol
)
649 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
650 || (symbol_get_value_expression (sp
)->X_op_symbol
651 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
657 static int in_my_get_expression
= 0;
659 /* Third argument to my_get_expression. */
660 #define GE_NO_PREFIX 0
661 #define GE_IMM_PREFIX 1
662 #define GE_OPT_PREFIX 2
665 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
670 /* In unified syntax, all prefixes are optional. */
672 prefix_mode
= GE_OPT_PREFIX
;
676 case GE_NO_PREFIX
: break;
678 if (!is_immediate_prefix (**str
))
680 inst
.error
= _("immediate expression requires a # prefix");
686 if (is_immediate_prefix (**str
))
692 memset (ep
, 0, sizeof (expressionS
));
694 save_in
= input_line_pointer
;
695 input_line_pointer
= *str
;
696 in_my_get_expression
= 1;
697 seg
= expression (ep
);
698 in_my_get_expression
= 0;
700 if (ep
->X_op
== O_illegal
)
702 /* We found a bad expression in md_operand(). */
703 *str
= input_line_pointer
;
704 input_line_pointer
= save_in
;
705 if (inst
.error
== NULL
)
706 inst
.error
= _("bad expression");
711 if (seg
!= absolute_section
712 && seg
!= text_section
713 && seg
!= data_section
714 && seg
!= bss_section
715 && seg
!= undefined_section
)
717 inst
.error
= _("bad segment");
718 *str
= input_line_pointer
;
719 input_line_pointer
= save_in
;
724 /* Get rid of any bignums now, so that we don't generate an error for which
725 we can't establish a line number later on. Big numbers are never valid
726 in instructions, which is where this routine is always called. */
727 if (ep
->X_op
== O_big
729 && (walk_no_bignums (ep
->X_add_symbol
)
731 && walk_no_bignums (ep
->X_op_symbol
)))))
733 inst
.error
= _("invalid constant");
734 *str
= input_line_pointer
;
735 input_line_pointer
= save_in
;
739 *str
= input_line_pointer
;
740 input_line_pointer
= save_in
;
744 /* Turn a string in input_line_pointer into a floating point constant
745 of type TYPE, and store the appropriate bytes in *LITP. The number
746 of LITTLENUMS emitted is stored in *SIZEP. An error message is
747 returned, or NULL on OK.
749 Note that fp constants aren't represent in the normal way on the ARM.
750 In big endian mode, things are as expected. However, in little endian
751 mode fp constants are big-endian word-wise, and little-endian byte-wise
752 within the words. For example, (double) 1.1 in big endian mode is
753 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
754 the byte sequence 99 99 f1 3f 9a 99 99 99.
756 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
759 md_atof (int type
, char * litP
, int * sizeP
)
762 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
794 return _("bad call to MD_ATOF()");
797 t
= atof_ieee (input_line_pointer
, type
, words
);
799 input_line_pointer
= t
;
802 if (target_big_endian
)
804 for (i
= 0; i
< prec
; i
++)
806 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
812 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
813 for (i
= prec
- 1; i
>= 0; i
--)
815 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
819 /* For a 4 byte float the order of elements in `words' is 1 0.
820 For an 8 byte float the order is 1 0 3 2. */
821 for (i
= 0; i
< prec
; i
+= 2)
823 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
824 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
832 /* We handle all bad expressions here, so that we can report the faulty
833 instruction in the error message. */
835 md_operand (expressionS
* expr
)
837 if (in_my_get_expression
)
838 expr
->X_op
= O_illegal
;
841 /* Immediate values. */
843 /* Generic immediate-value read function for use in directives.
844 Accepts anything that 'expression' can fold to a constant.
845 *val receives the number. */
848 immediate_for_directive (int *val
)
851 exp
.X_op
= O_illegal
;
853 if (is_immediate_prefix (*input_line_pointer
))
855 input_line_pointer
++;
859 if (exp
.X_op
!= O_constant
)
861 as_bad (_("expected #constant"));
862 ignore_rest_of_line ();
865 *val
= exp
.X_add_number
;
870 /* Register parsing. */
872 /* Generic register parser. CCP points to what should be the
873 beginning of a register name. If it is indeed a valid register
874 name, advance CCP over it and return the reg_entry structure;
875 otherwise return NULL. Does not issue diagnostics. */
877 static struct reg_entry
*
878 arm_reg_parse_multi (char **ccp
)
882 struct reg_entry
*reg
;
884 #ifdef REGISTER_PREFIX
885 if (*start
!= REGISTER_PREFIX
)
889 #ifdef OPTIONAL_REGISTER_PREFIX
890 if (*start
== OPTIONAL_REGISTER_PREFIX
)
895 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
900 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
902 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
911 /* As above, but the register must be of type TYPE, and the return
912 value is the register number or FAIL. */
915 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
918 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
920 if (reg
&& reg
->type
== type
)
923 /* Alternative syntaxes are accepted for a few register classes. */
930 /* Generic coprocessor register names are allowed for these. */
931 if (reg
->type
== REG_TYPE_CN
)
936 /* For backward compatibility, a bare number is valid here. */
938 unsigned long processor
= strtoul (start
, ccp
, 10);
939 if (*ccp
!= start
&& processor
<= 15)
944 /* WC includes WCG. ??? I'm not sure this is true for all
945 instructions that take WC registers. */
946 if (reg
->type
== REG_TYPE_MMXWCG
)
958 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
960 parse_reg_list (char ** strp
)
966 /* We come back here if we get ranges concatenated by '+' or '|'. */
981 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
983 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
993 inst
.error
= _("bad range in register list");
997 for (i
= cur_reg
+ 1; i
< reg
; i
++)
999 if (range
& (1 << i
))
1001 (_("Warning: duplicated register (r%d) in register list"),
1009 if (range
& (1 << reg
))
1010 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1012 else if (reg
<= cur_reg
)
1013 as_tsktsk (_("Warning: register range not in ascending order"));
1018 while (skip_past_comma (&str
) != FAIL
1019 || (in_range
= 1, *str
++ == '-'));
1024 inst
.error
= _("missing `}'");
1032 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1035 if (expr
.X_op
== O_constant
)
1037 if (expr
.X_add_number
1038 != (expr
.X_add_number
& 0x0000ffff))
1040 inst
.error
= _("invalid register mask");
1044 if ((range
& expr
.X_add_number
) != 0)
1046 int regno
= range
& expr
.X_add_number
;
1049 regno
= (1 << regno
) - 1;
1051 (_("Warning: duplicated register (r%d) in register list"),
1055 range
|= expr
.X_add_number
;
1059 if (inst
.reloc
.type
!= 0)
1061 inst
.error
= _("expression too complex");
1065 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1066 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1067 inst
.reloc
.pc_rel
= 0;
1071 if (*str
== '|' || *str
== '+')
1077 while (another_range
);
1083 /* Parse a VFP register list. If the string is invalid return FAIL.
1084 Otherwise return the number of registers, and set PBASE to the first
1085 register. Double precision registers are matched if DP is nonzero. */
1088 parse_vfp_reg_list (char **str
, unsigned int *pbase
, int dp
)
1096 unsigned long mask
= 0;
1106 regtype
= REG_TYPE_VFD
;
1111 regtype
= REG_TYPE_VFS
;
1115 base_reg
= max_regs
;
1119 new_base
= arm_reg_parse (str
, regtype
);
1120 if (new_base
== FAIL
)
1122 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1126 if (new_base
< base_reg
)
1127 base_reg
= new_base
;
1129 if (mask
& (1 << new_base
))
1131 inst
.error
= _("invalid register list");
1135 if ((mask
>> new_base
) != 0 && ! warned
)
1137 as_tsktsk (_("register list not in ascending order"));
1141 mask
|= 1 << new_base
;
1144 if (**str
== '-') /* We have the start of a range expression */
1150 if ((high_range
= arm_reg_parse (str
, regtype
)) == FAIL
)
1152 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1156 if (high_range
<= new_base
)
1158 inst
.error
= _("register range not in ascending order");
1162 for (new_base
++; new_base
<= high_range
; new_base
++)
1164 if (mask
& (1 << new_base
))
1166 inst
.error
= _("invalid register list");
1170 mask
|= 1 << new_base
;
1175 while (skip_past_comma (str
) != FAIL
);
1179 /* Sanity check -- should have raised a parse error above. */
1180 if (count
== 0 || count
> max_regs
)
1185 /* Final test -- the registers must be consecutive. */
1187 for (i
= 0; i
< count
; i
++)
1189 if ((mask
& (1u << i
)) == 0)
1191 inst
.error
= _("non-contiguous register range");
1199 /* Parse an explicit relocation suffix on an expression. This is
1200 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1201 arm_reloc_hsh contains no entries, so this function can only
1202 succeed if there is no () after the word. Returns -1 on error,
1203 BFD_RELOC_UNUSED if there wasn't any suffix. */
1205 parse_reloc (char **str
)
1207 struct reloc_entry
*r
;
1211 return BFD_RELOC_UNUSED
;
1216 while (*q
&& *q
!= ')' && *q
!= ',')
1221 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1228 /* Directives: register aliases. */
1231 insert_reg_alias (char *str
, int number
, int type
)
1233 struct reg_entry
*new;
1236 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1239 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1241 /* Only warn about a redefinition if it's not defined as the
1243 else if (new->number
!= number
|| new->type
!= type
)
1244 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1249 name
= xstrdup (str
);
1250 new = xmalloc (sizeof (struct reg_entry
));
1253 new->number
= number
;
1255 new->builtin
= FALSE
;
1257 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1261 /* Look for the .req directive. This is of the form:
1263 new_register_name .req existing_register_name
1265 If we find one, or if it looks sufficiently like one that we want to
1266 handle any error here, return non-zero. Otherwise return zero. */
1269 create_register_alias (char * newname
, char *p
)
1271 struct reg_entry
*old
;
1272 char *oldname
, *nbuf
;
1275 /* The input scrubber ensures that whitespace after the mnemonic is
1276 collapsed to single spaces. */
1278 if (strncmp (oldname
, " .req ", 6) != 0)
1282 if (*oldname
== '\0')
1285 old
= hash_find (arm_reg_hsh
, oldname
);
1288 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1292 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1293 the desired alias name, and p points to its end. If not, then
1294 the desired alias name is in the global original_case_string. */
1295 #ifdef TC_CASE_SENSITIVE
1298 newname
= original_case_string
;
1299 nlen
= strlen (newname
);
1302 nbuf
= alloca (nlen
+ 1);
1303 memcpy (nbuf
, newname
, nlen
);
1306 /* Create aliases under the new name as stated; an all-lowercase
1307 version of the new name; and an all-uppercase version of the new
1309 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1311 for (p
= nbuf
; *p
; p
++)
1314 if (strncmp (nbuf
, newname
, nlen
))
1315 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1317 for (p
= nbuf
; *p
; p
++)
1320 if (strncmp (nbuf
, newname
, nlen
))
1321 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1326 /* Should never be called, as .req goes between the alias and the
1327 register name, not at the beginning of the line. */
1329 s_req (int a ATTRIBUTE_UNUSED
)
1331 as_bad (_("invalid syntax for .req directive"));
1334 /* The .unreq directive deletes an alias which was previously defined
1335 by .req. For example:
1341 s_unreq (int a ATTRIBUTE_UNUSED
)
1346 name
= input_line_pointer
;
1348 while (*input_line_pointer
!= 0
1349 && *input_line_pointer
!= ' '
1350 && *input_line_pointer
!= '\n')
1351 ++input_line_pointer
;
1353 saved_char
= *input_line_pointer
;
1354 *input_line_pointer
= 0;
1357 as_bad (_("invalid syntax for .unreq directive"));
1360 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
1363 as_bad (_("unknown register alias '%s'"), name
);
1364 else if (reg
->builtin
)
1365 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1369 hash_delete (arm_reg_hsh
, name
);
1370 free ((char *) reg
->name
);
1375 *input_line_pointer
= saved_char
;
1376 demand_empty_rest_of_line ();
1379 /* Directives: Instruction set selection. */
1382 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1383 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1384 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1385 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1387 static enum mstate mapstate
= MAP_UNDEFINED
;
1390 mapping_state (enum mstate state
)
1393 const char * symname
;
1396 if (mapstate
== state
)
1397 /* The mapping symbol has already been emitted.
1398 There is nothing else to do. */
1407 type
= BSF_NO_FLAGS
;
1411 type
= BSF_NO_FLAGS
;
1415 type
= BSF_NO_FLAGS
;
1423 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1425 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
1426 symbol_table_insert (symbolP
);
1427 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1432 THUMB_SET_FUNC (symbolP
, 0);
1433 ARM_SET_THUMB (symbolP
, 0);
1434 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1438 THUMB_SET_FUNC (symbolP
, 1);
1439 ARM_SET_THUMB (symbolP
, 1);
1440 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1449 #define mapping_state(x) /* nothing */
1452 /* Find the real, Thumb encoded start of a Thumb function. */
1455 find_real_start (symbolS
* symbolP
)
1458 const char * name
= S_GET_NAME (symbolP
);
1459 symbolS
* new_target
;
1461 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1462 #define STUB_NAME ".real_start_of"
1467 /* The compiler may generate BL instructions to local labels because
1468 it needs to perform a branch to a far away location. These labels
1469 do not have a corresponding ".real_start_of" label. We check
1470 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1471 the ".real_start_of" convention for nonlocal branches. */
1472 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
1475 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
1476 new_target
= symbol_find (real_start
);
1478 if (new_target
== NULL
)
1480 as_warn ("Failed to find real start of function: %s\n", name
);
1481 new_target
= symbolP
;
1488 opcode_select (int width
)
1495 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
1496 as_bad (_("selected processor does not support THUMB opcodes"));
1499 /* No need to force the alignment, since we will have been
1500 coming from ARM mode, which is word-aligned. */
1501 record_alignment (now_seg
, 1);
1503 mapping_state (MAP_THUMB
);
1509 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
1510 as_bad (_("selected processor does not support ARM opcodes"));
1515 frag_align (2, 0, 0);
1517 record_alignment (now_seg
, 1);
1519 mapping_state (MAP_ARM
);
1523 as_bad (_("invalid instruction size selected (%d)"), width
);
1528 s_arm (int ignore ATTRIBUTE_UNUSED
)
1531 demand_empty_rest_of_line ();
1535 s_thumb (int ignore ATTRIBUTE_UNUSED
)
1538 demand_empty_rest_of_line ();
1542 s_code (int unused ATTRIBUTE_UNUSED
)
1546 temp
= get_absolute_expression ();
1551 opcode_select (temp
);
1555 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
1560 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
1562 /* If we are not already in thumb mode go into it, EVEN if
1563 the target processor does not support thumb instructions.
1564 This is used by gcc/config/arm/lib1funcs.asm for example
1565 to compile interworking support functions even if the
1566 target processor should not support interworking. */
1570 record_alignment (now_seg
, 1);
1573 demand_empty_rest_of_line ();
1577 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
1581 /* The following label is the name/address of the start of a Thumb function.
1582 We need to know this for the interworking support. */
1583 label_is_thumb_function_name
= TRUE
;
1586 /* Perform a .set directive, but also mark the alias as
1587 being a thumb function. */
1590 s_thumb_set (int equiv
)
1592 /* XXX the following is a duplicate of the code for s_set() in read.c
1593 We cannot just call that code as we need to get at the symbol that
1600 /* Especial apologies for the random logic:
1601 This just grew, and could be parsed much more simply!
1603 name
= input_line_pointer
;
1604 delim
= get_symbol_end ();
1605 end_name
= input_line_pointer
;
1608 if (*input_line_pointer
!= ',')
1611 as_bad (_("expected comma after name \"%s\""), name
);
1613 ignore_rest_of_line ();
1617 input_line_pointer
++;
1620 if (name
[0] == '.' && name
[1] == '\0')
1622 /* XXX - this should not happen to .thumb_set. */
1626 if ((symbolP
= symbol_find (name
)) == NULL
1627 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
1630 /* When doing symbol listings, play games with dummy fragments living
1631 outside the normal fragment chain to record the file and line info
1633 if (listing
& LISTING_SYMBOLS
)
1635 extern struct list_info_struct
* listing_tail
;
1636 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
1638 memset (dummy_frag
, 0, sizeof (fragS
));
1639 dummy_frag
->fr_type
= rs_fill
;
1640 dummy_frag
->line
= listing_tail
;
1641 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
1642 dummy_frag
->fr_symbol
= symbolP
;
1646 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
1649 /* "set" symbols are local unless otherwise specified. */
1650 SF_SET_LOCAL (symbolP
);
1651 #endif /* OBJ_COFF */
1652 } /* Make a new symbol. */
1654 symbol_table_insert (symbolP
);
1659 && S_IS_DEFINED (symbolP
)
1660 && S_GET_SEGMENT (symbolP
) != reg_section
)
1661 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
1663 pseudo_set (symbolP
);
1665 demand_empty_rest_of_line ();
1667 /* XXX Now we come to the Thumb specific bit of code. */
1669 THUMB_SET_FUNC (symbolP
, 1);
1670 ARM_SET_THUMB (symbolP
, 1);
1671 #if defined OBJ_ELF || defined OBJ_COFF
1672 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1676 /* Directives: Mode selection. */
1678 /* .syntax [unified|divided] - choose the new unified syntax
1679 (same for Arm and Thumb encoding, modulo slight differences in what
1680 can be represented) or the old divergent syntax for each mode. */
1682 s_syntax (int unused ATTRIBUTE_UNUSED
)
1686 name
= input_line_pointer
;
1687 delim
= get_symbol_end ();
1689 if (!strcasecmp (name
, "unified"))
1690 unified_syntax
= TRUE
;
1691 else if (!strcasecmp (name
, "divided"))
1692 unified_syntax
= FALSE
;
1695 as_bad (_("unrecognized syntax mode \"%s\""), name
);
1698 *input_line_pointer
= delim
;
1699 demand_empty_rest_of_line ();
1702 /* Directives: sectioning and alignment. */
1704 /* Same as s_align_ptwo but align 0 => align 2. */
1707 s_align (int unused ATTRIBUTE_UNUSED
)
1711 long max_alignment
= 15;
1713 temp
= get_absolute_expression ();
1714 if (temp
> max_alignment
)
1715 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
1718 as_bad (_("alignment negative. 0 assumed."));
1722 if (*input_line_pointer
== ',')
1724 input_line_pointer
++;
1725 temp_fill
= get_absolute_expression ();
1733 /* Only make a frag if we HAVE to. */
1734 if (temp
&& !need_pass_2
)
1735 frag_align (temp
, (int) temp_fill
, 0);
1736 demand_empty_rest_of_line ();
1738 record_alignment (now_seg
, temp
);
1742 s_bss (int ignore ATTRIBUTE_UNUSED
)
1744 /* We don't support putting frags in the BSS segment, we fake it by
1745 marking in_bss, then looking at s_skip for clues. */
1746 subseg_set (bss_section
, 0);
1747 demand_empty_rest_of_line ();
1748 mapping_state (MAP_DATA
);
1752 s_even (int ignore ATTRIBUTE_UNUSED
)
1754 /* Never make frag if expect extra pass. */
1756 frag_align (1, 0, 0);
1758 record_alignment (now_seg
, 1);
1760 demand_empty_rest_of_line ();
1763 /* Directives: Literal pools. */
1765 static literal_pool
*
1766 find_literal_pool (void)
1768 literal_pool
* pool
;
1770 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1772 if (pool
->section
== now_seg
1773 && pool
->sub_section
== now_subseg
)
1780 static literal_pool
*
1781 find_or_make_literal_pool (void)
1783 /* Next literal pool ID number. */
1784 static unsigned int latest_pool_num
= 1;
1785 literal_pool
* pool
;
1787 pool
= find_literal_pool ();
1791 /* Create a new pool. */
1792 pool
= xmalloc (sizeof (* pool
));
1796 pool
->next_free_entry
= 0;
1797 pool
->section
= now_seg
;
1798 pool
->sub_section
= now_subseg
;
1799 pool
->next
= list_of_pools
;
1800 pool
->symbol
= NULL
;
1802 /* Add it to the list. */
1803 list_of_pools
= pool
;
1806 /* New pools, and emptied pools, will have a NULL symbol. */
1807 if (pool
->symbol
== NULL
)
1809 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1810 (valueT
) 0, &zero_address_frag
);
1811 pool
->id
= latest_pool_num
++;
1818 /* Add the literal in the global 'inst'
1819 structure to the relevent literal pool. */
1822 add_to_lit_pool (void)
1824 literal_pool
* pool
;
1827 pool
= find_or_make_literal_pool ();
1829 /* Check if this literal value is already in the pool. */
1830 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1832 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
1833 && (inst
.reloc
.exp
.X_op
== O_constant
)
1834 && (pool
->literals
[entry
].X_add_number
1835 == inst
.reloc
.exp
.X_add_number
)
1836 && (pool
->literals
[entry
].X_unsigned
1837 == inst
.reloc
.exp
.X_unsigned
))
1840 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
1841 && (inst
.reloc
.exp
.X_op
== O_symbol
)
1842 && (pool
->literals
[entry
].X_add_number
1843 == inst
.reloc
.exp
.X_add_number
)
1844 && (pool
->literals
[entry
].X_add_symbol
1845 == inst
.reloc
.exp
.X_add_symbol
)
1846 && (pool
->literals
[entry
].X_op_symbol
1847 == inst
.reloc
.exp
.X_op_symbol
))
1851 /* Do we need to create a new entry? */
1852 if (entry
== pool
->next_free_entry
)
1854 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1856 inst
.error
= _("literal pool overflow");
1860 pool
->literals
[entry
] = inst
.reloc
.exp
;
1861 pool
->next_free_entry
+= 1;
1864 inst
.reloc
.exp
.X_op
= O_symbol
;
1865 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
1866 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
1871 /* Can't use symbol_new here, so have to create a symbol and then at
1872 a later date assign it a value. Thats what these functions do. */
1875 symbol_locate (symbolS
* symbolP
,
1876 const char * name
, /* It is copied, the caller can modify. */
1877 segT segment
, /* Segment identifier (SEG_<something>). */
1878 valueT valu
, /* Symbol value. */
1879 fragS
* frag
) /* Associated fragment. */
1881 unsigned int name_length
;
1882 char * preserved_copy_of_name
;
1884 name_length
= strlen (name
) + 1; /* +1 for \0. */
1885 obstack_grow (¬es
, name
, name_length
);
1886 preserved_copy_of_name
= obstack_finish (¬es
);
1888 #ifdef tc_canonicalize_symbol_name
1889 preserved_copy_of_name
=
1890 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1893 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1895 S_SET_SEGMENT (symbolP
, segment
);
1896 S_SET_VALUE (symbolP
, valu
);
1897 symbol_clear_list_pointers (symbolP
);
1899 symbol_set_frag (symbolP
, frag
);
1901 /* Link to end of symbol chain. */
1903 extern int symbol_table_frozen
;
1905 if (symbol_table_frozen
)
1909 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
1911 obj_symbol_new_hook (symbolP
);
1913 #ifdef tc_symbol_new_hook
1914 tc_symbol_new_hook (symbolP
);
1918 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1919 #endif /* DEBUG_SYMS */
1924 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1927 literal_pool
* pool
;
1930 pool
= find_literal_pool ();
1932 || pool
->symbol
== NULL
1933 || pool
->next_free_entry
== 0)
1936 mapping_state (MAP_DATA
);
1938 /* Align pool as you have word accesses.
1939 Only make a frag if we have to. */
1941 frag_align (2, 0, 0);
1943 record_alignment (now_seg
, 2);
1945 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1947 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1948 (valueT
) frag_now_fix (), frag_now
);
1949 symbol_table_insert (pool
->symbol
);
1951 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
1953 #if defined OBJ_COFF || defined OBJ_ELF
1954 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
1957 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1958 /* First output the expression in the instruction to the pool. */
1959 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
1961 /* Mark the pool as empty. */
1962 pool
->next_free_entry
= 0;
1963 pool
->symbol
= NULL
;
1967 /* Forward declarations for functions below, in the MD interface
1969 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
1970 static valueT
create_unwind_entry (int);
1971 static void start_unwind_section (const segT
, int);
1972 static void add_unwind_opcode (valueT
, int);
1973 static void flush_pending_unwind (void);
1975 /* Directives: Data. */
1978 s_arm_elf_cons (int nbytes
)
1982 #ifdef md_flush_pending_output
1983 md_flush_pending_output ();
1986 if (is_it_end_of_statement ())
1988 demand_empty_rest_of_line ();
1992 #ifdef md_cons_align
1993 md_cons_align (nbytes
);
1996 mapping_state (MAP_DATA
);
2000 char *base
= input_line_pointer
;
2004 if (exp
.X_op
!= O_symbol
)
2005 emit_expr (&exp
, (unsigned int) nbytes
);
2008 char *before_reloc
= input_line_pointer
;
2009 reloc
= parse_reloc (&input_line_pointer
);
2012 as_bad (_("unrecognized relocation suffix"));
2013 ignore_rest_of_line ();
2016 else if (reloc
== BFD_RELOC_UNUSED
)
2017 emit_expr (&exp
, (unsigned int) nbytes
);
2020 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2021 int size
= bfd_get_reloc_size (howto
);
2023 if (reloc
== BFD_RELOC_ARM_PLT32
)
2025 as_bad (_("(plt) is only valid on branch targets"));
2026 reloc
= BFD_RELOC_UNUSED
;
2031 as_bad (_("%s relocations do not fit in %d bytes"),
2032 howto
->name
, nbytes
);
2035 /* We've parsed an expression stopping at O_symbol.
2036 But there may be more expression left now that we
2037 have parsed the relocation marker. Parse it again.
2038 XXX Surely there is a cleaner way to do this. */
2039 char *p
= input_line_pointer
;
2041 char *save_buf
= alloca (input_line_pointer
- base
);
2042 memcpy (save_buf
, base
, input_line_pointer
- base
);
2043 memmove (base
+ (input_line_pointer
- before_reloc
),
2044 base
, before_reloc
- base
);
2046 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2048 memcpy (base
, save_buf
, p
- base
);
2050 offset
= nbytes
- size
;
2051 p
= frag_more ((int) nbytes
);
2052 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2053 size
, &exp
, 0, reloc
);
2058 while (*input_line_pointer
++ == ',');
2060 /* Put terminator back into stream. */
2061 input_line_pointer
--;
2062 demand_empty_rest_of_line ();
2066 /* Parse a .rel31 directive. */
2069 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2076 if (*input_line_pointer
== '1')
2077 highbit
= 0x80000000;
2078 else if (*input_line_pointer
!= '0')
2079 as_bad (_("expected 0 or 1"));
2081 input_line_pointer
++;
2082 if (*input_line_pointer
!= ',')
2083 as_bad (_("missing comma"));
2084 input_line_pointer
++;
2086 #ifdef md_flush_pending_output
2087 md_flush_pending_output ();
2090 #ifdef md_cons_align
2094 mapping_state (MAP_DATA
);
2099 md_number_to_chars (p
, highbit
, 4);
2100 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2101 BFD_RELOC_ARM_PREL31
);
2103 demand_empty_rest_of_line ();
2106 /* Directives: AEABI stack-unwind tables. */
2108 /* Parse an unwind_fnstart directive. Simply records the current location. */
2111 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
2113 demand_empty_rest_of_line ();
2114 /* Mark the start of the function. */
2115 unwind
.proc_start
= expr_build_dot ();
2117 /* Reset the rest of the unwind info. */
2118 unwind
.opcode_count
= 0;
2119 unwind
.table_entry
= NULL
;
2120 unwind
.personality_routine
= NULL
;
2121 unwind
.personality_index
= -1;
2122 unwind
.frame_size
= 0;
2123 unwind
.fp_offset
= 0;
2126 unwind
.sp_restored
= 0;
2130 /* Parse a handlerdata directive. Creates the exception handling table entry
2131 for the function. */
2134 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
2136 demand_empty_rest_of_line ();
2137 if (unwind
.table_entry
)
2138 as_bad (_("dupicate .handlerdata directive"));
2140 create_unwind_entry (1);
2143 /* Parse an unwind_fnend directive. Generates the index table entry. */
2146 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
2152 demand_empty_rest_of_line ();
2154 /* Add eh table entry. */
2155 if (unwind
.table_entry
== NULL
)
2156 val
= create_unwind_entry (0);
2160 /* Add index table entry. This is two words. */
2161 start_unwind_section (unwind
.saved_seg
, 1);
2162 frag_align (2, 0, 0);
2163 record_alignment (now_seg
, 2);
2165 ptr
= frag_more (8);
2166 where
= frag_now_fix () - 8;
2168 /* Self relative offset of the function start. */
2169 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
2170 BFD_RELOC_ARM_PREL31
);
2172 /* Indicate dependency on EHABI-defined personality routines to the
2173 linker, if it hasn't been done already. */
2174 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
2175 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
2177 static const char *const name
[] = {
2178 "__aeabi_unwind_cpp_pr0",
2179 "__aeabi_unwind_cpp_pr1",
2180 "__aeabi_unwind_cpp_pr2"
2182 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
2183 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
2184 marked_pr_dependency
|= 1 << unwind
.personality_index
;
2185 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
2186 = marked_pr_dependency
;
2190 /* Inline exception table entry. */
2191 md_number_to_chars (ptr
+ 4, val
, 4);
2193 /* Self relative offset of the table entry. */
2194 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
2195 BFD_RELOC_ARM_PREL31
);
2197 /* Restore the original section. */
2198 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
2202 /* Parse an unwind_cantunwind directive. */
2205 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
2207 demand_empty_rest_of_line ();
2208 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2209 as_bad (_("personality routine specified for cantunwind frame"));
2211 unwind
.personality_index
= -2;
2215 /* Parse a personalityindex directive. */
2218 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
2222 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2223 as_bad (_("duplicate .personalityindex directive"));
2227 if (exp
.X_op
!= O_constant
2228 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
2230 as_bad (_("bad personality routine number"));
2231 ignore_rest_of_line ();
2235 unwind
.personality_index
= exp
.X_add_number
;
2237 demand_empty_rest_of_line ();
2241 /* Parse a personality directive. */
2244 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
2248 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
2249 as_bad (_("duplicate .personality directive"));
2251 name
= input_line_pointer
;
2252 c
= get_symbol_end ();
2253 p
= input_line_pointer
;
2254 unwind
.personality_routine
= symbol_find_or_make (name
);
2256 demand_empty_rest_of_line ();
2260 /* Parse a directive saving core registers. */
2263 s_arm_unwind_save_core (void)
2269 range
= parse_reg_list (&input_line_pointer
);
2272 as_bad (_("expected register list"));
2273 ignore_rest_of_line ();
2277 demand_empty_rest_of_line ();
2279 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2280 into .unwind_save {..., sp...}. We aren't bothered about the value of
2281 ip because it is clobbered by calls. */
2282 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
2283 && (range
& 0x3000) == 0x1000)
2285 unwind
.opcode_count
--;
2286 unwind
.sp_restored
= 0;
2287 range
= (range
| 0x2000) & ~0x1000;
2288 unwind
.pending_offset
= 0;
2294 /* See if we can use the short opcodes. These pop a block of up to 8
2295 registers starting with r4, plus maybe r14. */
2296 for (n
= 0; n
< 8; n
++)
2298 /* Break at the first non-saved register. */
2299 if ((range
& (1 << (n
+ 4))) == 0)
2302 /* See if there are any other bits set. */
2303 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
2305 /* Use the long form. */
2306 op
= 0x8000 | ((range
>> 4) & 0xfff);
2307 add_unwind_opcode (op
, 2);
2311 /* Use the short form. */
2313 op
= 0xa8; /* Pop r14. */
2315 op
= 0xa0; /* Do not pop r14. */
2317 add_unwind_opcode (op
, 1);
2324 op
= 0xb100 | (range
& 0xf);
2325 add_unwind_opcode (op
, 2);
2328 /* Record the number of bytes pushed. */
2329 for (n
= 0; n
< 16; n
++)
2331 if (range
& (1 << n
))
2332 unwind
.frame_size
+= 4;
2337 /* Parse a directive saving FPA registers. */
2340 s_arm_unwind_save_fpa (int reg
)
2346 /* Get Number of registers to transfer. */
2347 if (skip_past_comma (&input_line_pointer
) != FAIL
)
2350 exp
.X_op
= O_illegal
;
2352 if (exp
.X_op
!= O_constant
)
2354 as_bad (_("expected , <constant>"));
2355 ignore_rest_of_line ();
2359 num_regs
= exp
.X_add_number
;
2361 if (num_regs
< 1 || num_regs
> 4)
2363 as_bad (_("number of registers must be in the range [1:4]"));
2364 ignore_rest_of_line ();
2368 demand_empty_rest_of_line ();
2373 op
= 0xb4 | (num_regs
- 1);
2374 add_unwind_opcode (op
, 1);
2379 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
2380 add_unwind_opcode (op
, 2);
2382 unwind
.frame_size
+= num_regs
* 12;
2386 /* Parse a directive saving VFP registers. */
2389 s_arm_unwind_save_vfp (void)
2395 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, 1);
2398 as_bad (_("expected register list"));
2399 ignore_rest_of_line ();
2403 demand_empty_rest_of_line ();
2408 op
= 0xb8 | (count
- 1);
2409 add_unwind_opcode (op
, 1);
2414 op
= 0xb300 | (reg
<< 4) | (count
- 1);
2415 add_unwind_opcode (op
, 2);
2417 unwind
.frame_size
+= count
* 8 + 4;
2421 /* Parse a directive saving iWMMXt data registers. */
2424 s_arm_unwind_save_mmxwr (void)
2432 if (*input_line_pointer
== '{')
2433 input_line_pointer
++;
2437 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
2441 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
2446 as_tsktsk (_("register list not in ascending order"));
2449 if (*input_line_pointer
== '-')
2451 input_line_pointer
++;
2452 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
2455 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
2458 else if (reg
>= hi_reg
)
2460 as_bad (_("bad register range"));
2463 for (; reg
< hi_reg
; reg
++)
2467 while (skip_past_comma (&input_line_pointer
) != FAIL
);
2469 if (*input_line_pointer
== '}')
2470 input_line_pointer
++;
2472 demand_empty_rest_of_line ();
2474 /* Generate any deferred opcodes becuuse we're going to be looking at
2476 flush_pending_unwind ();
2478 for (i
= 0; i
< 16; i
++)
2480 if (mask
& (1 << i
))
2481 unwind
.frame_size
+= 8;
2484 /* Attempt to combine with a previous opcode. We do this because gcc
2485 likes to output separate unwind directives for a single block of
2487 if (unwind
.opcode_count
> 0)
2489 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
2490 if ((i
& 0xf8) == 0xc0)
2493 /* Only merge if the blocks are contiguous. */
2496 if ((mask
& 0xfe00) == (1 << 9))
2498 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
2499 unwind
.opcode_count
--;
2502 else if (i
== 6 && unwind
.opcode_count
>= 2)
2504 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
2508 op
= 0xffff << (reg
- 1);
2510 || ((mask
& op
) == (1u << (reg
- 1))))
2512 op
= (1 << (reg
+ i
+ 1)) - 1;
2513 op
&= ~((1 << reg
) - 1);
2515 unwind
.opcode_count
-= 2;
2522 /* We want to generate opcodes in the order the registers have been
2523 saved, ie. descending order. */
2524 for (reg
= 15; reg
>= -1; reg
--)
2526 /* Save registers in blocks. */
2528 || !(mask
& (1 << reg
)))
2530 /* We found an unsaved reg. Generate opcodes to save the
2531 preceeding block. */
2537 op
= 0xc0 | (hi_reg
- 10);
2538 add_unwind_opcode (op
, 1);
2543 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
2544 add_unwind_opcode (op
, 2);
2553 ignore_rest_of_line ();
2557 s_arm_unwind_save_mmxwcg (void)
2564 if (*input_line_pointer
== '{')
2565 input_line_pointer
++;
2569 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
2573 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
2579 as_tsktsk (_("register list not in ascending order"));
2582 if (*input_line_pointer
== '-')
2584 input_line_pointer
++;
2585 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
2588 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
2591 else if (reg
>= hi_reg
)
2593 as_bad (_("bad register range"));
2596 for (; reg
< hi_reg
; reg
++)
2600 while (skip_past_comma (&input_line_pointer
) != FAIL
);
2602 if (*input_line_pointer
== '}')
2603 input_line_pointer
++;
2605 demand_empty_rest_of_line ();
2607 /* Generate any deferred opcodes becuuse we're going to be looking at
2609 flush_pending_unwind ();
2611 for (reg
= 0; reg
< 16; reg
++)
2613 if (mask
& (1 << reg
))
2614 unwind
.frame_size
+= 4;
2617 add_unwind_opcode (op
, 2);
2620 ignore_rest_of_line ();
2624 /* Parse an unwind_save directive. */
2627 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED
)
2630 struct reg_entry
*reg
;
2631 bfd_boolean had_brace
= FALSE
;
2633 /* Figure out what sort of save we have. */
2634 peek
= input_line_pointer
;
2642 reg
= arm_reg_parse_multi (&peek
);
2646 as_bad (_("register expected"));
2647 ignore_rest_of_line ();
2656 as_bad (_("FPA .unwind_save does not take a register list"));
2657 ignore_rest_of_line ();
2660 s_arm_unwind_save_fpa (reg
->number
);
2663 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
2664 case REG_TYPE_VFD
: s_arm_unwind_save_vfp (); return;
2665 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
2666 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
2669 as_bad (_(".unwind_save does not support this kind of register"));
2670 ignore_rest_of_line ();
2675 /* Parse an unwind_movsp directive. */
2678 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
2683 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2686 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
2687 ignore_rest_of_line ();
2690 demand_empty_rest_of_line ();
2692 if (reg
== REG_SP
|| reg
== REG_PC
)
2694 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2698 if (unwind
.fp_reg
!= REG_SP
)
2699 as_bad (_("unexpected .unwind_movsp directive"));
2701 /* Generate opcode to restore the value. */
2703 add_unwind_opcode (op
, 1);
2705 /* Record the information for later. */
2706 unwind
.fp_reg
= reg
;
2707 unwind
.fp_offset
= unwind
.frame_size
;
2708 unwind
.sp_restored
= 1;
2711 /* Parse an unwind_pad directive. */
2714 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
2718 if (immediate_for_directive (&offset
) == FAIL
)
2723 as_bad (_("stack increment must be multiple of 4"));
2724 ignore_rest_of_line ();
2728 /* Don't generate any opcodes, just record the details for later. */
2729 unwind
.frame_size
+= offset
;
2730 unwind
.pending_offset
+= offset
;
2732 demand_empty_rest_of_line ();
2735 /* Parse an unwind_setfp directive. */
2738 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
2744 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2745 if (skip_past_comma (&input_line_pointer
) == FAIL
)
2748 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
2750 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
2752 as_bad (_("expected <reg>, <reg>"));
2753 ignore_rest_of_line ();
2757 /* Optional constant. */
2758 if (skip_past_comma (&input_line_pointer
) != FAIL
)
2760 if (immediate_for_directive (&offset
) == FAIL
)
2766 demand_empty_rest_of_line ();
2768 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
2770 as_bad (_("register must be either sp or set by a previous"
2771 "unwind_movsp directive"));
2775 /* Don't generate any opcodes, just record the information for later. */
2776 unwind
.fp_reg
= fp_reg
;
2779 unwind
.fp_offset
= unwind
.frame_size
- offset
;
2781 unwind
.fp_offset
-= offset
;
2784 /* Parse an unwind_raw directive. */
2787 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
2790 /* This is an arbitary limit. */
2791 unsigned char op
[16];
2795 if (exp
.X_op
== O_constant
2796 && skip_past_comma (&input_line_pointer
) != FAIL
)
2798 unwind
.frame_size
+= exp
.X_add_number
;
2802 exp
.X_op
= O_illegal
;
2804 if (exp
.X_op
!= O_constant
)
2806 as_bad (_("expected <offset>, <opcode>"));
2807 ignore_rest_of_line ();
2813 /* Parse the opcode. */
2818 as_bad (_("unwind opcode too long"));
2819 ignore_rest_of_line ();
2821 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
2823 as_bad (_("invalid unwind opcode"));
2824 ignore_rest_of_line ();
2827 op
[count
++] = exp
.X_add_number
;
2829 /* Parse the next byte. */
2830 if (skip_past_comma (&input_line_pointer
) == FAIL
)
2836 /* Add the opcode bytes in reverse order. */
2838 add_unwind_opcode (op
[count
], 1);
2840 demand_empty_rest_of_line ();
2844 /* Parse a .eabi_attribute directive. */
2847 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
2850 bfd_boolean is_string
;
2857 if (exp
.X_op
!= O_constant
)
2860 tag
= exp
.X_add_number
;
2861 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
2866 if (skip_past_comma (&input_line_pointer
) == FAIL
)
2868 if (tag
== 32 || !is_string
)
2871 if (exp
.X_op
!= O_constant
)
2873 as_bad (_("expected numeric constant"));
2874 ignore_rest_of_line ();
2877 i
= exp
.X_add_number
;
2879 if (tag
== Tag_compatibility
2880 && skip_past_comma (&input_line_pointer
) == FAIL
)
2882 as_bad (_("expected comma"));
2883 ignore_rest_of_line ();
2888 skip_whitespace(input_line_pointer
);
2889 if (*input_line_pointer
!= '"')
2891 input_line_pointer
++;
2892 s
= input_line_pointer
;
2893 while (*input_line_pointer
&& *input_line_pointer
!= '"')
2894 input_line_pointer
++;
2895 if (*input_line_pointer
!= '"')
2897 saved_char
= *input_line_pointer
;
2898 *input_line_pointer
= 0;
2906 if (tag
== Tag_compatibility
)
2907 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
2909 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
2911 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
2915 *input_line_pointer
= saved_char
;
2916 input_line_pointer
++;
2918 demand_empty_rest_of_line ();
2921 as_bad (_("bad string constant"));
2922 ignore_rest_of_line ();
2925 as_bad (_("expected <tag> , <value>"));
2926 ignore_rest_of_line ();
2929 static void s_arm_arch (int);
2930 static void s_arm_cpu (int);
2931 static void s_arm_fpu (int);
2932 #endif /* OBJ_ELF */
2934 /* This table describes all the machine specific pseudo-ops the assembler
2935 has to support. The fields are:
2936 pseudo-op name without dot
2937 function to call to execute this pseudo-op
2938 Integer arg to pass to the function. */
2940 const pseudo_typeS md_pseudo_table
[] =
2942 /* Never called because '.req' does not start a line. */
2943 { "req", s_req
, 0 },
2944 { "unreq", s_unreq
, 0 },
2945 { "bss", s_bss
, 0 },
2946 { "align", s_align
, 0 },
2947 { "arm", s_arm
, 0 },
2948 { "thumb", s_thumb
, 0 },
2949 { "code", s_code
, 0 },
2950 { "force_thumb", s_force_thumb
, 0 },
2951 { "thumb_func", s_thumb_func
, 0 },
2952 { "thumb_set", s_thumb_set
, 0 },
2953 { "even", s_even
, 0 },
2954 { "ltorg", s_ltorg
, 0 },
2955 { "pool", s_ltorg
, 0 },
2956 { "syntax", s_syntax
, 0 },
2958 { "word", s_arm_elf_cons
, 4 },
2959 { "long", s_arm_elf_cons
, 4 },
2960 { "rel31", s_arm_rel31
, 0 },
2961 { "fnstart", s_arm_unwind_fnstart
, 0 },
2962 { "fnend", s_arm_unwind_fnend
, 0 },
2963 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
2964 { "personality", s_arm_unwind_personality
, 0 },
2965 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
2966 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
2967 { "save", s_arm_unwind_save
, 0 },
2968 { "movsp", s_arm_unwind_movsp
, 0 },
2969 { "pad", s_arm_unwind_pad
, 0 },
2970 { "setfp", s_arm_unwind_setfp
, 0 },
2971 { "unwind_raw", s_arm_unwind_raw
, 0 },
2972 { "cpu", s_arm_cpu
, 0 },
2973 { "arch", s_arm_arch
, 0 },
2974 { "fpu", s_arm_fpu
, 0 },
2975 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
2979 { "extend", float_cons
, 'x' },
2980 { "ldouble", float_cons
, 'x' },
2981 { "packed", float_cons
, 'p' },
2985 /* Parser functions used exclusively in instruction operands. */
2987 /* Generic immediate-value read function for use in insn parsing.
2988 STR points to the beginning of the immediate (the leading #);
2989 VAL receives the value; if the value is outside [MIN, MAX]
2990 issue an error. PREFIX_OPT is true if the immediate prefix is
2994 parse_immediate (char **str
, int *val
, int min
, int max
,
2995 bfd_boolean prefix_opt
)
2998 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
2999 if (exp
.X_op
!= O_constant
)
3001 inst
.error
= _("constant expression required");
3005 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
3007 inst
.error
= _("immediate value out of range");
3011 *val
= exp
.X_add_number
;
3015 /* Returns the pseudo-register number of an FPA immediate constant,
3016 or FAIL if there isn't a valid constant here. */
3019 parse_fpa_immediate (char ** str
)
3021 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3027 /* First try and match exact strings, this is to guarantee
3028 that some formats will work even for cross assembly. */
3030 for (i
= 0; fp_const
[i
]; i
++)
3032 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
3036 *str
+= strlen (fp_const
[i
]);
3037 if (is_end_of_line
[(unsigned char) **str
])
3043 /* Just because we didn't get a match doesn't mean that the constant
3044 isn't valid, just that it is in a format that we don't
3045 automatically recognize. Try parsing it with the standard
3046 expression routines. */
3048 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
3050 /* Look for a raw floating point number. */
3051 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
3052 && is_end_of_line
[(unsigned char) *save_in
])
3054 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
3056 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
3058 if (words
[j
] != fp_values
[i
][j
])
3062 if (j
== MAX_LITTLENUMS
)
3070 /* Try and parse a more complex expression, this will probably fail
3071 unless the code uses a floating point prefix (eg "0f"). */
3072 save_in
= input_line_pointer
;
3073 input_line_pointer
= *str
;
3074 if (expression (&exp
) == absolute_section
3075 && exp
.X_op
== O_big
3076 && exp
.X_add_number
< 0)
3078 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3080 if (gen_to_words (words
, 5, (long) 15) == 0)
3082 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
3084 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
3086 if (words
[j
] != fp_values
[i
][j
])
3090 if (j
== MAX_LITTLENUMS
)
3092 *str
= input_line_pointer
;
3093 input_line_pointer
= save_in
;
3100 *str
= input_line_pointer
;
3101 input_line_pointer
= save_in
;
3102 inst
.error
= _("invalid FPA immediate expression");
3106 /* Shift operands. */
3109 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
3112 struct asm_shift_name
3115 enum shift_kind kind
;
3118 /* Third argument to parse_shift. */
3119 enum parse_shift_mode
3121 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
3122 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
3123 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
3124 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
3125 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
3128 /* Parse a <shift> specifier on an ARM data processing instruction.
3129 This has three forms:
3131 (LSL|LSR|ASL|ASR|ROR) Rs
3132 (LSL|LSR|ASL|ASR|ROR) #imm
3135 Note that ASL is assimilated to LSL in the instruction encoding, and
3136 RRX to ROR #0 (which cannot be written as such). */
3139 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
3141 const struct asm_shift_name
*shift_name
;
3142 enum shift_kind shift
;
3147 for (p
= *str
; ISALPHA (*p
); p
++)
3152 inst
.error
= _("shift expression expected");
3156 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
3158 if (shift_name
== NULL
)
3160 inst
.error
= _("shift expression expected");
3164 shift
= shift_name
->kind
;
3168 case NO_SHIFT_RESTRICT
:
3169 case SHIFT_IMMEDIATE
: break;
3171 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
3172 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
3174 inst
.error
= _("'LSL' or 'ASR' required");
3179 case SHIFT_LSL_IMMEDIATE
:
3180 if (shift
!= SHIFT_LSL
)
3182 inst
.error
= _("'LSL' required");
3187 case SHIFT_ASR_IMMEDIATE
:
3188 if (shift
!= SHIFT_ASR
)
3190 inst
.error
= _("'ASR' required");
3198 if (shift
!= SHIFT_RRX
)
3200 /* Whitespace can appear here if the next thing is a bare digit. */
3201 skip_whitespace (p
);
3203 if (mode
== NO_SHIFT_RESTRICT
3204 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3206 inst
.operands
[i
].imm
= reg
;
3207 inst
.operands
[i
].immisreg
= 1;
3209 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3212 inst
.operands
[i
].shift_kind
= shift
;
3213 inst
.operands
[i
].shifted
= 1;
3218 /* Parse a <shifter_operand> for an ARM data processing instruction:
3221 #<immediate>, <rotate>
3225 where <shift> is defined by parse_shift above, and <rotate> is a
3226 multiple of 2 between 0 and 30. Validation of immediate operands
3227 is deferred to md_apply_fix. */
3230 parse_shifter_operand (char **str
, int i
)
3235 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
3237 inst
.operands
[i
].reg
= value
;
3238 inst
.operands
[i
].isreg
= 1;
3240 /* parse_shift will override this if appropriate */
3241 inst
.reloc
.exp
.X_op
= O_constant
;
3242 inst
.reloc
.exp
.X_add_number
= 0;
3244 if (skip_past_comma (str
) == FAIL
)
3247 /* Shift operation on register. */
3248 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
3251 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
3254 if (skip_past_comma (str
) == SUCCESS
)
3256 /* #x, y -- ie explicit rotation by Y. */
3257 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
3260 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
3262 inst
.error
= _("constant expression expected");
3266 value
= expr
.X_add_number
;
3267 if (value
< 0 || value
> 30 || value
% 2 != 0)
3269 inst
.error
= _("invalid rotation");
3272 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
3274 inst
.error
= _("invalid constant");
3278 /* Convert to decoded value. md_apply_fix will put it back. */
3279 inst
.reloc
.exp
.X_add_number
3280 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
3281 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
3284 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
3285 inst
.reloc
.pc_rel
= 0;
3289 /* Parse all forms of an ARM address expression. Information is written
3290 to inst.operands[i] and/or inst.reloc.
3292 Preindexed addressing (.preind=1):
3294 [Rn, #offset] .reg=Rn .reloc.exp=offset
3295 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3296 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3297 .shift_kind=shift .reloc.exp=shift_imm
3299 These three may have a trailing ! which causes .writeback to be set also.
3301 Postindexed addressing (.postind=1, .writeback=1):
3303 [Rn], #offset .reg=Rn .reloc.exp=offset
3304 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3305 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3306 .shift_kind=shift .reloc.exp=shift_imm
3308 Unindexed addressing (.preind=0, .postind=0):
3310 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3314 [Rn]{!} shorthand for [Rn,#0]{!}
3315 =immediate .isreg=0 .reloc.exp=immediate
3316 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3318 It is the caller's responsibility to check for addressing modes not
3319 supported by the instruction, and to set inst.reloc.type. */
3322 parse_address (char **str
, int i
)
3327 if (skip_past_char (&p
, '[') == FAIL
)
3329 if (skip_past_char (&p
, '=') == FAIL
)
3331 /* bare address - translate to PC-relative offset */
3332 inst
.reloc
.pc_rel
= 1;
3333 inst
.operands
[i
].reg
= REG_PC
;
3334 inst
.operands
[i
].isreg
= 1;
3335 inst
.operands
[i
].preind
= 1;
3337 /* else a load-constant pseudo op, no special treatment needed here */
3339 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
3346 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
3348 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
3351 inst
.operands
[i
].reg
= reg
;
3352 inst
.operands
[i
].isreg
= 1;
3354 if (skip_past_comma (&p
) == SUCCESS
)
3356 inst
.operands
[i
].preind
= 1;
3359 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
3361 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3363 inst
.operands
[i
].imm
= reg
;
3364 inst
.operands
[i
].immisreg
= 1;
3366 if (skip_past_comma (&p
) == SUCCESS
)
3367 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
3372 if (inst
.operands
[i
].negative
)
3374 inst
.operands
[i
].negative
= 0;
3377 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3382 if (skip_past_char (&p
, ']') == FAIL
)
3384 inst
.error
= _("']' expected");
3388 if (skip_past_char (&p
, '!') == SUCCESS
)
3389 inst
.operands
[i
].writeback
= 1;
3391 else if (skip_past_comma (&p
) == SUCCESS
)
3393 if (skip_past_char (&p
, '{') == SUCCESS
)
3395 /* [Rn], {expr} - unindexed, with option */
3396 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
3397 0, 255, TRUE
) == FAIL
)
3400 if (skip_past_char (&p
, '}') == FAIL
)
3402 inst
.error
= _("'}' expected at end of 'option' field");
3405 if (inst
.operands
[i
].preind
)
3407 inst
.error
= _("cannot combine index with option");
3415 inst
.operands
[i
].postind
= 1;
3416 inst
.operands
[i
].writeback
= 1;
3418 if (inst
.operands
[i
].preind
)
3420 inst
.error
= _("cannot combine pre- and post-indexing");
3425 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
3427 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
3429 inst
.operands
[i
].imm
= reg
;
3430 inst
.operands
[i
].immisreg
= 1;
3432 if (skip_past_comma (&p
) == SUCCESS
)
3433 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
3438 if (inst
.operands
[i
].negative
)
3440 inst
.operands
[i
].negative
= 0;
3443 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
3449 /* If at this point neither .preind nor .postind is set, we have a
3450 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3451 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
3453 inst
.operands
[i
].preind
= 1;
3454 inst
.reloc
.exp
.X_op
= O_constant
;
3455 inst
.reloc
.exp
.X_add_number
= 0;
3461 /* Miscellaneous. */
3463 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3464 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3466 parse_psr (char **str
)
3469 unsigned long psr_field
;
3471 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3472 feature for ease of use and backwards compatibility. */
3474 if (*p
== 's' || *p
== 'S')
3475 psr_field
= SPSR_BIT
;
3476 else if (*p
== 'c' || *p
== 'C')
3482 if (strncasecmp (p
, "PSR", 3) != 0)
3488 /* A suffix follows. */
3489 const struct asm_psr
*psr
;
3497 while (ISALNUM (*p
) || *p
== '_');
3499 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
3503 psr_field
|= psr
->field
;
3508 goto error
; /* Garbage after "[CS]PSR". */
3510 psr_field
|= (PSR_c
| PSR_f
);
3516 inst
.error
= _("flag for {c}psr instruction expected");
3520 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3521 value suitable for splatting into the AIF field of the instruction. */
3524 parse_cps_flags (char **str
)
3533 case '\0': case ',':
3536 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
3537 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
3538 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
3541 inst
.error
= _("unrecognized CPS flag");
3546 if (saw_a_flag
== 0)
3548 inst
.error
= _("missing CPS flags");
3556 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3557 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3560 parse_endian_specifier (char **str
)
3565 if (strncasecmp (s
, "BE", 2))
3567 else if (strncasecmp (s
, "LE", 2))
3571 inst
.error
= _("valid endian specifiers are be or le");
3575 if (ISALNUM (s
[2]) || s
[2] == '_')
3577 inst
.error
= _("valid endian specifiers are be or le");
3582 return little_endian
;
3585 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3586 value suitable for poking into the rotate field of an sxt or sxta
3587 instruction, or FAIL on error. */
3590 parse_ror (char **str
)
3595 if (strncasecmp (s
, "ROR", 3) == 0)
3599 inst
.error
= _("missing rotation field after comma");
3603 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
3608 case 0: *str
= s
; return 0x0;
3609 case 8: *str
= s
; return 0x1;
3610 case 16: *str
= s
; return 0x2;
3611 case 24: *str
= s
; return 0x3;
3614 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
3619 /* Parse a conditional code (from conds[] below). The value returned is in the
3620 range 0 .. 14, or FAIL. */
3622 parse_cond (char **str
)
3625 const struct asm_cond
*c
;
3628 while (ISALPHA (*q
))
3631 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
3634 inst
.error
= _("condition required");
3642 /* Parse the operands of a table branch instruction. Similar to a memory
3645 parse_tb (char **str
)
3650 if (skip_past_char (&p
, '[') == FAIL
)
3653 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
3655 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
3658 inst
.operands
[0].reg
= reg
;
3660 if (skip_past_comma (&p
) == FAIL
)
3663 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
3665 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
3668 inst
.operands
[0].imm
= reg
;
3670 if (skip_past_comma (&p
) == SUCCESS
)
3672 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
3674 if (inst
.reloc
.exp
.X_add_number
!= 1)
3676 inst
.error
= _("invalid shift");
3679 inst
.operands
[0].shifted
= 1;
3682 if (skip_past_char (&p
, ']') == FAIL
)
3684 inst
.error
= _("']' expected");
3691 /* Matcher codes for parse_operands. */
3692 enum operand_parse_code
3694 OP_stop
, /* end of line */
3696 OP_RR
, /* ARM register */
3697 OP_RRnpc
, /* ARM register, not r15 */
3698 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
3699 OP_RRw
, /* ARM register, not r15, optional trailing ! */
3700 OP_RCP
, /* Coprocessor number */
3701 OP_RCN
, /* Coprocessor register */
3702 OP_RF
, /* FPA register */
3703 OP_RVS
, /* VFP single precision register */
3704 OP_RVD
, /* VFP double precision register */
3705 OP_RVC
, /* VFP control register */
3706 OP_RMF
, /* Maverick F register */
3707 OP_RMD
, /* Maverick D register */
3708 OP_RMFX
, /* Maverick FX register */
3709 OP_RMDX
, /* Maverick DX register */
3710 OP_RMAX
, /* Maverick AX register */
3711 OP_RMDS
, /* Maverick DSPSC register */
3712 OP_RIWR
, /* iWMMXt wR register */
3713 OP_RIWC
, /* iWMMXt wC register */
3714 OP_RIWG
, /* iWMMXt wCG register */
3715 OP_RXA
, /* XScale accumulator register */
3717 OP_REGLST
, /* ARM register list */
3718 OP_VRSLST
, /* VFP single-precision register list */
3719 OP_VRDLST
, /* VFP double-precision register list */
3721 OP_I7
, /* immediate value 0 .. 7 */
3722 OP_I15
, /* 0 .. 15 */
3723 OP_I16
, /* 1 .. 16 */
3724 OP_I31
, /* 0 .. 31 */
3725 OP_I31w
, /* 0 .. 31, optional trailing ! */
3726 OP_I32
, /* 1 .. 32 */
3727 OP_I63s
, /* -64 .. 63 */
3728 OP_I255
, /* 0 .. 255 */
3729 OP_Iffff
, /* 0 .. 65535 */
3731 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
3732 OP_I7b
, /* 0 .. 7 */
3733 OP_I15b
, /* 0 .. 15 */
3734 OP_I31b
, /* 0 .. 31 */
3736 OP_SH
, /* shifter operand */
3737 OP_ADDR
, /* Memory address expression (any mode) */
3738 OP_EXP
, /* arbitrary expression */
3739 OP_EXPi
, /* same, with optional immediate prefix */
3740 OP_EXPr
, /* same, with optional relocation suffix */
3742 OP_CPSF
, /* CPS flags */
3743 OP_ENDI
, /* Endianness specifier */
3744 OP_PSR
, /* CPSR/SPSR mask for msr */
3745 OP_COND
, /* conditional code */
3746 OP_TB
, /* Table branch. */
3748 OP_RRnpc_I0
, /* ARM register or literal 0 */
3749 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
3750 OP_RR_EXi
, /* ARM register or expression with imm prefix */
3751 OP_RF_IF
, /* FPA register or immediate */
3752 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
3754 /* Optional operands. */
3755 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
3756 OP_oI31b
, /* 0 .. 31 */
3757 OP_oIffffb
, /* 0 .. 65535 */
3758 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
3760 OP_oRR
, /* ARM register */
3761 OP_oRRnpc
, /* ARM register, not the PC */
3762 OP_oSHll
, /* LSL immediate */
3763 OP_oSHar
, /* ASR immediate */
3764 OP_oSHllar
, /* LSL or ASR immediate */
3765 OP_oROR
, /* ROR 0/8/16/24 */
3767 OP_FIRST_OPTIONAL
= OP_oI7b
3770 /* Generic instruction operand parser. This does no encoding and no
3771 semantic validation; it merely squirrels values away in the inst
3772 structure. Returns SUCCESS or FAIL depending on whether the
3773 specified grammar matched. */
3775 parse_operands (char *str
, const unsigned char *pattern
)
3777 unsigned const char *upat
= pattern
;
3778 char *backtrack_pos
= 0;
3779 const char *backtrack_error
= 0;
3780 int i
, val
, backtrack_index
= 0;
3782 #define po_char_or_fail(chr) do { \
3783 if (skip_past_char (&str, chr) == FAIL) \
3787 #define po_reg_or_fail(regtype) do { \
3788 val = arm_reg_parse (&str, regtype); \
3791 inst.error = _(reg_expected_msgs[regtype]); \
3794 inst.operands[i].reg = val; \
3795 inst.operands[i].isreg = 1; \
3798 #define po_reg_or_goto(regtype, label) do { \
3799 val = arm_reg_parse (&str, regtype); \
3803 inst.operands[i].reg = val; \
3804 inst.operands[i].isreg = 1; \
3807 #define po_imm_or_fail(min, max, popt) do { \
3808 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3810 inst.operands[i].imm = val; \
3813 #define po_misc_or_fail(expr) do { \
3818 skip_whitespace (str
);
3820 for (i
= 0; upat
[i
] != OP_stop
; i
++)
3822 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
3824 /* Remember where we are in case we need to backtrack. */
3825 assert (!backtrack_pos
);
3826 backtrack_pos
= str
;
3827 backtrack_error
= inst
.error
;
3828 backtrack_index
= i
;
3832 po_char_or_fail (',');
3840 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
3841 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
3842 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
3843 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
3844 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
3845 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
3846 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
3847 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
3848 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
3849 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
3850 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
3851 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
3852 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
3853 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
3854 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
3855 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
3856 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
3859 po_char_or_fail ('[');
3860 po_reg_or_fail (REG_TYPE_RN
);
3861 po_char_or_fail (']');
3865 po_reg_or_fail (REG_TYPE_RN
);
3866 if (skip_past_char (&str
, '!') == SUCCESS
)
3867 inst
.operands
[i
].writeback
= 1;
3871 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
3872 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
3873 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
3874 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
3875 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
3876 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
3877 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
3878 case OP_Iffff
: po_imm_or_fail ( 0, 0xffff, FALSE
); break;
3880 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
3882 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
3883 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
3885 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
3886 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
3888 /* Immediate variants */
3890 po_char_or_fail ('{');
3891 po_imm_or_fail (0, 255, TRUE
);
3892 po_char_or_fail ('}');
3896 /* The expression parser chokes on a trailing !, so we have
3897 to find it first and zap it. */
3900 while (*s
&& *s
!= ',')
3905 inst
.operands
[i
].writeback
= 1;
3907 po_imm_or_fail (0, 31, TRUE
);
3915 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3920 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3925 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
3927 if (inst
.reloc
.exp
.X_op
== O_symbol
)
3929 val
= parse_reloc (&str
);
3932 inst
.error
= _("unrecognized relocation suffix");
3935 else if (val
!= BFD_RELOC_UNUSED
)
3937 inst
.operands
[i
].imm
= val
;
3938 inst
.operands
[i
].hasreloc
= 1;
3943 /* Register or expression */
3944 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
3945 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
3947 /* Register or immediate */
3948 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
3949 I0
: po_imm_or_fail (0, 0, FALSE
); break;
3951 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
3953 if (!is_immediate_prefix (*str
))
3956 val
= parse_fpa_immediate (&str
);
3959 /* FPA immediates are encoded as registers 8-15.
3960 parse_fpa_immediate has already applied the offset. */
3961 inst
.operands
[i
].reg
= val
;
3962 inst
.operands
[i
].isreg
= 1;
3965 /* Two kinds of register */
3968 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
3969 if (rege
->type
!= REG_TYPE_MMXWR
3970 && rege
->type
!= REG_TYPE_MMXWC
3971 && rege
->type
!= REG_TYPE_MMXWCG
)
3973 inst
.error
= _("iWMMXt data or control register expected");
3976 inst
.operands
[i
].reg
= rege
->number
;
3977 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
3982 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
3983 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
3984 case OP_oROR
: val
= parse_ror (&str
); break;
3985 case OP_PSR
: val
= parse_psr (&str
); break;
3986 case OP_COND
: val
= parse_cond (&str
); break;
3989 po_misc_or_fail (parse_tb (&str
));
3992 /* Register lists */
3994 val
= parse_reg_list (&str
);
3997 inst
.operands
[1].writeback
= 1;
4003 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, 0);
4007 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, 1);
4010 /* Addressing modes */
4012 po_misc_or_fail (parse_address (&str
, i
));
4016 po_misc_or_fail (parse_shifter_operand (&str
, i
));
4020 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
4024 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
4028 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
4032 as_fatal ("unhandled operand code %d", upat
[i
]);
4035 /* Various value-based sanity checks and shared operations. We
4036 do not signal immediate failures for the register constraints;
4037 this allows a syntax error to take precedence. */
4045 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
4046 inst
.error
= BAD_PC
;
4059 inst
.operands
[i
].imm
= val
;
4066 /* If we get here, this operand was successfully parsed. */
4067 inst
.operands
[i
].present
= 1;
4071 inst
.error
= BAD_ARGS
;
4077 /* Do not backtrack over a trailing optional argument that
4078 absorbed some text. We will only fail again, with the
4079 'garbage following instruction' error message, which is
4080 probably less helpful than the current one. */
4081 if (backtrack_index
== i
&& backtrack_pos
!= str
4082 && upat
[i
+1] == OP_stop
)
4085 /* Try again, skipping the optional argument at backtrack_pos. */
4086 str
= backtrack_pos
;
4087 inst
.error
= backtrack_error
;
4088 inst
.operands
[backtrack_index
].present
= 0;
4089 i
= backtrack_index
;
4093 /* Check that we have parsed all the arguments. */
4094 if (*str
!= '\0' && !inst
.error
)
4095 inst
.error
= _("garbage following instruction");
4097 return inst
.error
? FAIL
: SUCCESS
;
4100 #undef po_char_or_fail
4101 #undef po_reg_or_fail
4102 #undef po_reg_or_goto
4103 #undef po_imm_or_fail
4105 /* Shorthand macro for instruction encoding functions issuing errors. */
4106 #define constraint(expr, err) do { \
4114 /* Functions for operand encoding. ARM, then Thumb. */
4116 #define rotate_left(v, n) (v << n | v >> (32 - n))
4118 /* If VAL can be encoded in the immediate field of an ARM instruction,
4119 return the encoded form. Otherwise, return FAIL. */
4122 encode_arm_immediate (unsigned int val
)
4126 for (i
= 0; i
< 32; i
+= 2)
4127 if ((a
= rotate_left (val
, i
)) <= 0xff)
4128 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
4133 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
4134 return the encoded form. Otherwise, return FAIL. */
4136 encode_thumb32_immediate (unsigned int val
)
4143 for (i
= 1; i
<= 24; i
++)
4146 if ((val
& ~(0xff << i
)) == 0)
4147 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
4151 if (val
== ((a
<< 16) | a
))
4153 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
4157 if (val
== ((a
<< 16) | a
))
4158 return 0x200 | (a
>> 8);
4162 /* Encode a VFP SP register number into inst.instruction. */
4165 encode_arm_vfp_sp_reg (int reg
, enum vfp_sp_reg_pos pos
)
4170 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
4174 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
4178 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
4186 /* Encode a <shift> in an ARM-format instruction. The immediate,
4187 if any, is handled by md_apply_fix. */
4189 encode_arm_shift (int i
)
4191 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
4192 inst
.instruction
|= SHIFT_ROR
<< 5;
4195 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
4196 if (inst
.operands
[i
].immisreg
)
4198 inst
.instruction
|= SHIFT_BY_REG
;
4199 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
4202 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
4207 encode_arm_shifter_operand (int i
)
4209 if (inst
.operands
[i
].isreg
)
4211 inst
.instruction
|= inst
.operands
[i
].reg
;
4212 encode_arm_shift (i
);
4215 inst
.instruction
|= INST_IMMEDIATE
;
4218 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4220 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
4222 assert (inst
.operands
[i
].isreg
);
4223 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
4225 if (inst
.operands
[i
].preind
)
4229 inst
.error
= _("instruction does not accept preindexed addressing");
4232 inst
.instruction
|= PRE_INDEX
;
4233 if (inst
.operands
[i
].writeback
)
4234 inst
.instruction
|= WRITE_BACK
;
4237 else if (inst
.operands
[i
].postind
)
4239 assert (inst
.operands
[i
].writeback
);
4241 inst
.instruction
|= WRITE_BACK
;
4243 else /* unindexed - only for coprocessor */
4245 inst
.error
= _("instruction does not accept unindexed addressing");
4249 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
4250 && (((inst
.instruction
& 0x000f0000) >> 16)
4251 == ((inst
.instruction
& 0x0000f000) >> 12)))
4252 as_warn ((inst
.instruction
& LOAD_BIT
)
4253 ? _("destination register same as write-back base")
4254 : _("source register same as write-back base"));
4257 /* inst.operands[i] was set up by parse_address. Encode it into an
4258 ARM-format mode 2 load or store instruction. If is_t is true,
4259 reject forms that cannot be used with a T instruction (i.e. not
4262 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
4264 encode_arm_addr_mode_common (i
, is_t
);
4266 if (inst
.operands
[i
].immisreg
)
4268 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
4269 inst
.instruction
|= inst
.operands
[i
].imm
;
4270 if (!inst
.operands
[i
].negative
)
4271 inst
.instruction
|= INDEX_UP
;
4272 if (inst
.operands
[i
].shifted
)
4274 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
4275 inst
.instruction
|= SHIFT_ROR
<< 5;
4278 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
4279 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
4283 else /* immediate offset in inst.reloc */
4285 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4286 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
4290 /* inst.operands[i] was set up by parse_address. Encode it into an
4291 ARM-format mode 3 load or store instruction. Reject forms that
4292 cannot be used with such instructions. If is_t is true, reject
4293 forms that cannot be used with a T instruction (i.e. not
4296 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
4298 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
4300 inst
.error
= _("instruction does not accept scaled register index");
4304 encode_arm_addr_mode_common (i
, is_t
);
4306 if (inst
.operands
[i
].immisreg
)
4308 inst
.instruction
|= inst
.operands
[i
].imm
;
4309 if (!inst
.operands
[i
].negative
)
4310 inst
.instruction
|= INDEX_UP
;
4312 else /* immediate offset in inst.reloc */
4314 inst
.instruction
|= HWOFFSET_IMM
;
4315 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4316 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
4320 /* inst.operands[i] was set up by parse_address. Encode it into an
4321 ARM-format instruction. Reject all forms which cannot be encoded
4322 into a coprocessor load/store instruction. If wb_ok is false,
4323 reject use of writeback; if unind_ok is false, reject use of
4324 unindexed addressing. If reloc_override is not 0, use it instead
4325 of BFD_ARM_CP_OFF_IMM. */
4328 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
4330 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
4332 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
4334 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
4336 assert (!inst
.operands
[i
].writeback
);
4339 inst
.error
= _("instruction does not support unindexed addressing");
4342 inst
.instruction
|= inst
.operands
[i
].imm
;
4343 inst
.instruction
|= INDEX_UP
;
4347 if (inst
.operands
[i
].preind
)
4348 inst
.instruction
|= PRE_INDEX
;
4350 if (inst
.operands
[i
].writeback
)
4352 if (inst
.operands
[i
].reg
== REG_PC
)
4354 inst
.error
= _("pc may not be used with write-back");
4359 inst
.error
= _("instruction does not support writeback");
4362 inst
.instruction
|= WRITE_BACK
;
4366 inst
.reloc
.type
= reloc_override
;
4367 else if (thumb_mode
)
4368 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
4370 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
4374 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4375 Determine whether it can be performed with a move instruction; if
4376 it can, convert inst.instruction to that move instruction and
4377 return 1; if it can't, convert inst.instruction to a literal-pool
4378 load and return 0. If this is not a valid thing to do in the
4379 current context, set inst.error and return 1.
4381 inst.operands[i] describes the destination register. */
4384 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
4386 if ((inst
.instruction
& (thumb_p
? THUMB_LOAD_BIT
: LOAD_BIT
)) == 0)
4388 inst
.error
= _("invalid pseudo operation");
4391 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
4393 inst
.error
= _("constant expression expected");
4396 if (inst
.reloc
.exp
.X_op
== O_constant
)
4400 if ((inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
4402 /* This can be done with a mov(1) instruction. */
4403 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
4404 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
4410 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
4413 /* This can be done with a mov instruction. */
4414 inst
.instruction
&= LITERAL_MASK
;
4415 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
4416 inst
.instruction
|= value
& 0xfff;
4420 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
4423 /* This can be done with a mvn instruction. */
4424 inst
.instruction
&= LITERAL_MASK
;
4425 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
4426 inst
.instruction
|= value
& 0xfff;
4432 if (add_to_lit_pool () == FAIL
)
4434 inst
.error
= _("literal pool insertion failed");
4437 inst
.operands
[1].reg
= REG_PC
;
4438 inst
.operands
[1].isreg
= 1;
4439 inst
.operands
[1].preind
= 1;
4440 inst
.reloc
.pc_rel
= 1;
4441 inst
.reloc
.type
= (thumb_p
4442 ? BFD_RELOC_ARM_THUMB_OFFSET
4444 ? BFD_RELOC_ARM_HWLITERAL
4445 : BFD_RELOC_ARM_LITERAL
));
4449 /* Functions for instruction encoding, sorted by subarchitecture.
4450 First some generics; their names are taken from the conventional
4451 bit positions for register arguments in ARM format instructions. */
4461 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4467 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4468 inst
.instruction
|= inst
.operands
[1].reg
;
4474 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4475 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4481 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4482 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
4488 unsigned Rn
= inst
.operands
[2].reg
;
4489 /* Enforce resutrictions on SWP instruction. */
4490 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
4491 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
4492 _("Rn must not overlap other operands"));
4493 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4494 inst
.instruction
|= inst
.operands
[1].reg
;
4495 inst
.instruction
|= Rn
<< 16;
4501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4502 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4503 inst
.instruction
|= inst
.operands
[2].reg
;
4509 inst
.instruction
|= inst
.operands
[0].reg
;
4510 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
4511 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4517 inst
.instruction
|= inst
.operands
[0].imm
;
4523 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4524 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
4527 /* ARM instructions, in alphabetical order by function name (except
4528 that wrapper functions appear immediately after the function they
4531 /* This is a pseudo-op of the form "adr rd, label" to be converted
4532 into a relative address of the form "add rd, pc, #label-.-8". */
4537 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
4539 /* Frag hacking will turn this into a sub instruction if the offset turns
4540 out to be negative. */
4541 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4542 inst
.reloc
.pc_rel
= 1;
4543 inst
.reloc
.exp
.X_add_number
-= 8;
4546 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4547 into a relative address of the form:
4548 add rd, pc, #low(label-.-8)"
4549 add rd, rd, #high(label-.-8)" */
4554 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
4556 /* Frag hacking will turn this into a sub instruction if the offset turns
4557 out to be negative. */
4558 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
4559 inst
.reloc
.pc_rel
= 1;
4560 inst
.size
= INSN_SIZE
* 2;
4561 inst
.reloc
.exp
.X_add_number
-= 8;
4567 if (!inst
.operands
[1].present
)
4568 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
4569 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4570 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4571 encode_arm_shifter_operand (2);
4577 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
4578 constraint (msb
> 32, _("bit-field extends past end of register"));
4579 /* The instruction encoding stores the LSB and MSB,
4580 not the LSB and width. */
4581 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4582 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
4583 inst
.instruction
|= (msb
- 1) << 16;
4591 /* #0 in second position is alternative syntax for bfc, which is
4592 the same instruction but with REG_PC in the Rm field. */
4593 if (!inst
.operands
[1].isreg
)
4594 inst
.operands
[1].reg
= REG_PC
;
4596 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
4597 constraint (msb
> 32, _("bit-field extends past end of register"));
4598 /* The instruction encoding stores the LSB and MSB,
4599 not the LSB and width. */
4600 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4601 inst
.instruction
|= inst
.operands
[1].reg
;
4602 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
4603 inst
.instruction
|= (msb
- 1) << 16;
4609 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
4610 _("bit-field extends past end of register"));
4611 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4612 inst
.instruction
|= inst
.operands
[1].reg
;
4613 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
4614 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
4617 /* ARM V5 breakpoint instruction (argument parse)
4618 BKPT <16 bit unsigned immediate>
4619 Instruction is not conditional.
4620 The bit pattern given in insns[] has the COND_ALWAYS condition,
4621 and it is an error if the caller tried to override that. */
4626 /* Top 12 of 16 bits to bits 19:8. */
4627 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
4629 /* Bottom 4 of 16 bits to bits 3:0. */
4630 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
4634 encode_branch (int default_reloc
)
4636 if (inst
.operands
[0].hasreloc
)
4638 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
4639 _("the only suffix valid here is '(plt)'"));
4640 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
4644 inst
.reloc
.type
= default_reloc
;
4646 inst
.reloc
.pc_rel
= 1;
4653 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
4654 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
4657 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
4664 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
4666 if (inst
.cond
== COND_ALWAYS
)
4667 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
4669 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
4673 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
4676 /* ARM V5 branch-link-exchange instruction (argument parse)
4677 BLX <target_addr> ie BLX(1)
4678 BLX{<condition>} <Rm> ie BLX(2)
4679 Unfortunately, there are two different opcodes for this mnemonic.
4680 So, the insns[].value is not used, and the code here zaps values
4681 into inst.instruction.
4682 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4687 if (inst
.operands
[0].isreg
)
4689 /* Arg is a register; the opcode provided by insns[] is correct.
4690 It is not illegal to do "blx pc", just useless. */
4691 if (inst
.operands
[0].reg
== REG_PC
)
4692 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4694 inst
.instruction
|= inst
.operands
[0].reg
;
4698 /* Arg is an address; this instruction cannot be executed
4699 conditionally, and the opcode must be adjusted. */
4700 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
4701 inst
.instruction
= 0xfa000000;
4703 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
4704 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
4707 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
4714 if (inst
.operands
[0].reg
== REG_PC
)
4715 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4717 inst
.instruction
|= inst
.operands
[0].reg
;
4721 /* ARM v5TEJ. Jump to Jazelle code. */
4726 if (inst
.operands
[0].reg
== REG_PC
)
4727 as_tsktsk (_("use of r15 in bxj is not really useful"));
4729 inst
.instruction
|= inst
.operands
[0].reg
;
4732 /* Co-processor data operation:
4733 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4734 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4738 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4739 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
4740 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4741 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4742 inst
.instruction
|= inst
.operands
[4].reg
;
4743 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
4749 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
4750 encode_arm_shifter_operand (1);
4753 /* Transfer between coprocessor and ARM registers.
4754 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4759 No special properties. */
4764 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4765 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
4766 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4767 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4768 inst
.instruction
|= inst
.operands
[4].reg
;
4769 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
4772 /* Transfer between coprocessor register and pair of ARM registers.
4773 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4778 Two XScale instructions are special cases of these:
4780 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4781 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4783 Result unpredicatable if Rd or Rn is R15. */
4788 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
4789 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
4790 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
4791 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
4792 inst
.instruction
|= inst
.operands
[4].reg
;
4798 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
4799 inst
.instruction
|= inst
.operands
[1].imm
;
4805 /* There is no IT instruction in ARM mode. We
4806 process it but do not generate code for it. */
4813 int base_reg
= inst
.operands
[0].reg
;
4814 int range
= inst
.operands
[1].imm
;
4816 inst
.instruction
|= base_reg
<< 16;
4817 inst
.instruction
|= range
;
4819 if (inst
.operands
[1].writeback
)
4820 inst
.instruction
|= LDM_TYPE_2_OR_3
;
4822 if (inst
.operands
[0].writeback
)
4824 inst
.instruction
|= WRITE_BACK
;
4825 /* Check for unpredictable uses of writeback. */
4826 if (inst
.instruction
& LOAD_BIT
)
4828 /* Not allowed in LDM type 2. */
4829 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
4830 && ((range
& (1 << REG_PC
)) == 0))
4831 as_warn (_("writeback of base register is UNPREDICTABLE"));
4832 /* Only allowed if base reg not in list for other types. */
4833 else if (range
& (1 << base_reg
))
4834 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4838 /* Not allowed for type 2. */
4839 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
4840 as_warn (_("writeback of base register is UNPREDICTABLE"));
4841 /* Only allowed if base reg not in list, or first in list. */
4842 else if ((range
& (1 << base_reg
))
4843 && (range
& ((1 << base_reg
) - 1)))
4844 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4849 /* ARMv5TE load-consecutive (argument parse)
4858 constraint (inst
.operands
[0].reg
% 2 != 0,
4859 _("first destination register must be even"));
4860 constraint (inst
.operands
[1].present
4861 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
4862 _("can only load two consecutive registers"));
4863 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
4864 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
4866 if (!inst
.operands
[1].present
)
4867 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
4869 if (inst
.instruction
& LOAD_BIT
)
4871 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4872 register and the first register written; we have to diagnose
4873 overlap between the base and the second register written here. */
4875 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
4876 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
4877 as_warn (_("base register written back, and overlaps "
4878 "second destination register"));
4880 /* For an index-register load, the index register must not overlap the
4881 destination (even if not write-back). */
4882 else if (inst
.operands
[2].immisreg
4883 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
4884 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
4885 as_warn (_("index register overlaps destination register"));
4888 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4889 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
4895 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
4896 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
4897 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
4898 || inst
.operands
[1].negative
4899 /* This can arise if the programmer has written
4901 or if they have mistakenly used a register name as the last
4904 It is very difficult to distinguish between these two cases
4905 because "rX" might actually be a label. ie the register
4906 name has been occluded by a symbol of the same name. So we
4907 just generate a general 'bad addressing mode' type error
4908 message and leave it up to the programmer to discover the
4909 true cause and fix their mistake. */
4910 || (inst
.operands
[1].reg
== REG_PC
),
4913 constraint (inst
.reloc
.exp
.X_op
!= O_constant
4914 || inst
.reloc
.exp
.X_add_number
!= 0,
4915 _("offset must be zero in ARM encoding"));
4917 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4918 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
4919 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4925 constraint (inst
.operands
[0].reg
% 2 != 0,
4926 _("even register required"));
4927 constraint (inst
.operands
[1].present
4928 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
4929 _("can only load two consecutive registers"));
4930 /* If op 1 were present and equal to PC, this function wouldn't
4931 have been called in the first place. */
4932 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
4934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4935 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
4941 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4942 if (!inst
.operands
[1].isreg
)
4943 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
4945 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
4951 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4953 if (inst
.operands
[1].preind
)
4955 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
4956 inst
.reloc
.exp
.X_add_number
!= 0,
4957 _("this instruction requires a post-indexed address"));
4959 inst
.operands
[1].preind
= 0;
4960 inst
.operands
[1].postind
= 1;
4961 inst
.operands
[1].writeback
= 1;
4963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4964 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
4967 /* Halfword and signed-byte load/store operations. */
4972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4973 if (!inst
.operands
[1].isreg
)
4974 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
4976 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
4982 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4984 if (inst
.operands
[1].preind
)
4986 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
4987 inst
.reloc
.exp
.X_add_number
!= 0,
4988 _("this instruction requires a post-indexed address"));
4990 inst
.operands
[1].preind
= 0;
4991 inst
.operands
[1].postind
= 1;
4992 inst
.operands
[1].writeback
= 1;
4994 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
4995 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
4998 /* Co-processor register load/store.
4999 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
5003 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
5004 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5005 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
5011 /* This restriction does not apply to mls (nor to mla in v6, but
5012 that's hard to detect at present). */
5013 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
5014 && !(inst
.instruction
& 0x00400000))
5015 as_tsktsk (_("rd and rm should be different in mla"));
5017 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5018 inst
.instruction
|= inst
.operands
[1].reg
;
5019 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5020 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
5027 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5028 encode_arm_shifter_operand (1);
5031 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
5035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5036 /* The value is in two pieces: 0:11, 16:19. */
5037 inst
.instruction
|= (inst
.operands
[1].imm
& 0x00000fff);
5038 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0000f000) << 4;
5044 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
5045 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
5047 _("'CPSR' or 'SPSR' expected"));
5048 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5049 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
5052 /* Two possible forms:
5053 "{C|S}PSR_<field>, Rm",
5054 "{C|S}PSR_f, #expression". */
5059 inst
.instruction
|= inst
.operands
[0].imm
;
5060 if (inst
.operands
[1].isreg
)
5061 inst
.instruction
|= inst
.operands
[1].reg
;
5064 inst
.instruction
|= INST_IMMEDIATE
;
5065 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5066 inst
.reloc
.pc_rel
= 0;
5073 if (!inst
.operands
[2].present
)
5074 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
5075 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5076 inst
.instruction
|= inst
.operands
[1].reg
;
5077 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5079 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
5080 as_tsktsk (_("rd and rm should be different in mul"));
5083 /* Long Multiply Parser
5084 UMULL RdLo, RdHi, Rm, Rs
5085 SMULL RdLo, RdHi, Rm, Rs
5086 UMLAL RdLo, RdHi, Rm, Rs
5087 SMLAL RdLo, RdHi, Rm, Rs. */
5092 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5093 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5094 inst
.instruction
|= inst
.operands
[2].reg
;
5095 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
5097 /* rdhi, rdlo and rm must all be different. */
5098 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
5099 || inst
.operands
[0].reg
== inst
.operands
[2].reg
5100 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
5101 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
5107 if (inst
.operands
[0].present
)
5109 /* Architectural NOP hints are CPSR sets with no bits selected. */
5110 inst
.instruction
&= 0xf0000000;
5111 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
5115 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
5116 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
5117 Condition defaults to COND_ALWAYS.
5118 Error if Rd, Rn or Rm are R15. */
5123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5124 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5125 inst
.instruction
|= inst
.operands
[2].reg
;
5126 if (inst
.operands
[3].present
)
5127 encode_arm_shift (3);
5130 /* ARM V6 PKHTB (Argument Parse). */
5135 if (!inst
.operands
[3].present
)
5137 /* If the shift specifier is omitted, turn the instruction
5138 into pkhbt rd, rm, rn. */
5139 inst
.instruction
&= 0xfff00010;
5140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5141 inst
.instruction
|= inst
.operands
[1].reg
;
5142 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5146 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5147 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5148 inst
.instruction
|= inst
.operands
[2].reg
;
5149 encode_arm_shift (3);
5153 /* ARMv5TE: Preload-Cache
5157 Syntactically, like LDR with B=1, W=0, L=1. */
5162 constraint (!inst
.operands
[0].isreg
,
5163 _("'[' expected after PLD mnemonic"));
5164 constraint (inst
.operands
[0].postind
,
5165 _("post-indexed expression used in preload instruction"));
5166 constraint (inst
.operands
[0].writeback
,
5167 _("writeback used in preload instruction"));
5168 constraint (!inst
.operands
[0].preind
,
5169 _("unindexed addressing used in preload instruction"));
5170 inst
.instruction
|= inst
.operands
[0].reg
;
5171 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
5177 inst
.operands
[1] = inst
.operands
[0];
5178 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
5179 inst
.operands
[0].isreg
= 1;
5180 inst
.operands
[0].writeback
= 1;
5181 inst
.operands
[0].reg
= REG_SP
;
5185 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
5186 word at the specified address and the following word
5188 Unconditionally executed.
5189 Error if Rn is R15. */
5194 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5195 if (inst
.operands
[0].writeback
)
5196 inst
.instruction
|= WRITE_BACK
;
5199 /* ARM V6 ssat (argument parse). */
5204 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5205 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
5206 inst
.instruction
|= inst
.operands
[2].reg
;
5208 if (inst
.operands
[3].present
)
5209 encode_arm_shift (3);
5212 /* ARM V6 usat (argument parse). */
5217 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5218 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
5219 inst
.instruction
|= inst
.operands
[2].reg
;
5221 if (inst
.operands
[3].present
)
5222 encode_arm_shift (3);
5225 /* ARM V6 ssat16 (argument parse). */
5230 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5231 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
5232 inst
.instruction
|= inst
.operands
[2].reg
;
5238 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5239 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
5240 inst
.instruction
|= inst
.operands
[2].reg
;
5243 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5244 preserving the other bits.
5246 setend <endian_specifier>, where <endian_specifier> is either
5252 if (inst
.operands
[0].imm
)
5253 inst
.instruction
|= 0x200;
5259 unsigned int Rm
= (inst
.operands
[1].present
5260 ? inst
.operands
[1].reg
5261 : inst
.operands
[0].reg
);
5263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5264 inst
.instruction
|= Rm
;
5265 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
5267 constraint (inst
.operands
[0].reg
!= Rm
,
5268 _("source1 and dest must be same register"));
5269 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5270 inst
.instruction
|= SHIFT_BY_REG
;
5273 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
5279 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
5280 inst
.reloc
.pc_rel
= 0;
5286 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
5287 inst
.reloc
.pc_rel
= 0;
5290 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5291 SMLAxy{cond} Rd,Rm,Rs,Rn
5292 SMLAWy{cond} Rd,Rm,Rs,Rn
5293 Error if any register is R15. */
5298 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5299 inst
.instruction
|= inst
.operands
[1].reg
;
5300 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5301 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
5304 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5305 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5306 Error if any register is R15.
5307 Warning if Rdlo == Rdhi. */
5312 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5313 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5314 inst
.instruction
|= inst
.operands
[2].reg
;
5315 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
5317 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
5318 as_tsktsk (_("rdhi and rdlo must be different"));
5321 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5322 SMULxy{cond} Rd,Rm,Rs
5323 Error if any register is R15. */
5328 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5329 inst
.instruction
|= inst
.operands
[1].reg
;
5330 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
5333 /* ARM V6 srs (argument parse). */
5338 inst
.instruction
|= inst
.operands
[0].imm
;
5339 if (inst
.operands
[0].writeback
)
5340 inst
.instruction
|= WRITE_BACK
;
5343 /* ARM V6 strex (argument parse). */
5348 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
5349 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
5350 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
5351 || inst
.operands
[2].negative
5352 /* See comment in do_ldrex(). */
5353 || (inst
.operands
[2].reg
== REG_PC
),
5356 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
5357 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
5359 constraint (inst
.reloc
.exp
.X_op
!= O_constant
5360 || inst
.reloc
.exp
.X_add_number
!= 0,
5361 _("offset must be zero in ARM encoding"));
5363 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5364 inst
.instruction
|= inst
.operands
[1].reg
;
5365 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5366 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5372 constraint (inst
.operands
[1].reg
% 2 != 0,
5373 _("even register required"));
5374 constraint (inst
.operands
[2].present
5375 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
5376 _("can only store two consecutive registers"));
5377 /* If op 2 were present and equal to PC, this function wouldn't
5378 have been called in the first place. */
5379 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
5381 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
5382 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
5383 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
5386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5387 inst
.instruction
|= inst
.operands
[1].reg
;
5388 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
5391 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5392 extends it to 32-bits, and adds the result to a value in another
5393 register. You can specify a rotation by 0, 8, 16, or 24 bits
5394 before extracting the 16-bit value.
5395 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5396 Condition defaults to COND_ALWAYS.
5397 Error if any register uses R15. */
5402 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5403 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5404 inst
.instruction
|= inst
.operands
[2].reg
;
5405 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
5410 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5411 Condition defaults to COND_ALWAYS.
5412 Error if any register uses R15. */
5417 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5418 inst
.instruction
|= inst
.operands
[1].reg
;
5419 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
5422 /* VFP instructions. In a logical order: SP variant first, monad
5423 before dyad, arithmetic then move then load/store. */
5426 do_vfp_sp_monadic (void)
5428 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5429 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
5433 do_vfp_sp_dyadic (void)
5435 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5436 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
5437 encode_arm_vfp_sp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
5441 do_vfp_sp_compare_z (void)
5443 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5447 do_vfp_dp_sp_cvt (void)
5449 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5450 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
5454 do_vfp_sp_dp_cvt (void)
5456 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5457 inst
.instruction
|= inst
.operands
[1].reg
;
5461 do_vfp_reg_from_sp (void)
5463 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5464 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
5468 do_vfp_reg2_from_sp2 (void)
5470 constraint (inst
.operands
[2].imm
!= 2,
5471 _("only two consecutive VFP SP registers allowed here"));
5472 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5473 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5474 encode_arm_vfp_sp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
5478 do_vfp_sp_from_reg (void)
5480 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
5481 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5485 do_vfp_sp2_from_reg2 (void)
5487 constraint (inst
.operands
[0].imm
!= 2,
5488 _("only two consecutive VFP SP registers allowed here"));
5489 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
5490 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5491 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5495 do_vfp_sp_ldst (void)
5497 encode_arm_vfp_sp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
5498 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
5502 do_vfp_dp_ldst (void)
5504 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5505 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
5510 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
5512 if (inst
.operands
[0].writeback
)
5513 inst
.instruction
|= WRITE_BACK
;
5515 constraint (ldstm_type
!= VFP_LDSTMIA
,
5516 _("this addressing mode requires base-register writeback"));
5517 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5518 encode_arm_vfp_sp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
5519 inst
.instruction
|= inst
.operands
[1].imm
;
5523 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
5527 if (inst
.operands
[0].writeback
)
5528 inst
.instruction
|= WRITE_BACK
;
5530 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
5531 _("this addressing mode requires base-register writeback"));
5533 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5534 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5536 count
= inst
.operands
[1].imm
<< 1;
5537 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
5540 inst
.instruction
|= count
;
5544 do_vfp_sp_ldstmia (void)
5546 vfp_sp_ldstm (VFP_LDSTMIA
);
5550 do_vfp_sp_ldstmdb (void)
5552 vfp_sp_ldstm (VFP_LDSTMDB
);
5556 do_vfp_dp_ldstmia (void)
5558 vfp_dp_ldstm (VFP_LDSTMIA
);
5562 do_vfp_dp_ldstmdb (void)
5564 vfp_dp_ldstm (VFP_LDSTMDB
);
5568 do_vfp_xp_ldstmia (void)
5570 vfp_dp_ldstm (VFP_LDSTMIAX
);
5574 do_vfp_xp_ldstmdb (void)
5576 vfp_dp_ldstm (VFP_LDSTMDBX
);
5579 /* FPA instructions. Also in a logical order. */
5584 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5585 inst
.instruction
|= inst
.operands
[1].reg
;
5589 do_fpa_ldmstm (void)
5591 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5592 switch (inst
.operands
[1].imm
)
5594 case 1: inst
.instruction
|= CP_T_X
; break;
5595 case 2: inst
.instruction
|= CP_T_Y
; break;
5596 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
5601 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
5603 /* The instruction specified "ea" or "fd", so we can only accept
5604 [Rn]{!}. The instruction does not really support stacking or
5605 unstacking, so we have to emulate these by setting appropriate
5606 bits and offsets. */
5607 constraint (inst
.reloc
.exp
.X_op
!= O_constant
5608 || inst
.reloc
.exp
.X_add_number
!= 0,
5609 _("this instruction does not support indexing"));
5611 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
5612 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
5614 if (!(inst
.instruction
& INDEX_UP
))
5615 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
5617 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
5619 inst
.operands
[2].preind
= 0;
5620 inst
.operands
[2].postind
= 1;
5624 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
5627 /* iWMMXt instructions: strictly in alphabetical order. */
5630 do_iwmmxt_tandorc (void)
5632 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
5636 do_iwmmxt_textrc (void)
5638 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5639 inst
.instruction
|= inst
.operands
[1].imm
;
5643 do_iwmmxt_textrm (void)
5645 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5646 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5647 inst
.instruction
|= inst
.operands
[2].imm
;
5651 do_iwmmxt_tinsr (void)
5653 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5654 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5655 inst
.instruction
|= inst
.operands
[2].imm
;
5659 do_iwmmxt_tmia (void)
5661 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
5662 inst
.instruction
|= inst
.operands
[1].reg
;
5663 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5667 do_iwmmxt_waligni (void)
5669 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5670 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5671 inst
.instruction
|= inst
.operands
[2].reg
;
5672 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
5676 do_iwmmxt_wmov (void)
5678 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5679 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5680 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5681 inst
.instruction
|= inst
.operands
[1].reg
;
5685 do_iwmmxt_wldstbh (void)
5688 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5689 inst
.reloc
.exp
.X_add_number
*= 4;
5691 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
5693 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
5694 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
5698 do_iwmmxt_wldstw (void)
5700 /* RIWR_RIWC clears .isreg for a control register. */
5701 if (!inst
.operands
[0].isreg
)
5703 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
5704 inst
.instruction
|= 0xf0000000;
5707 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5708 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
5712 do_iwmmxt_wldstd (void)
5714 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5715 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
5719 do_iwmmxt_wshufh (void)
5721 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5722 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5723 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
5724 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
5728 do_iwmmxt_wzero (void)
5730 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5731 inst
.instruction
|= inst
.operands
[0].reg
;
5732 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5733 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5736 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5737 operations first, then control, shift, and load/store. */
5739 /* Insns like "foo X,Y,Z". */
5742 do_mav_triple (void)
5744 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
5745 inst
.instruction
|= inst
.operands
[1].reg
;
5746 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5749 /* Insns like "foo W,X,Y,Z".
5750 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5755 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
5756 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5757 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5758 inst
.instruction
|= inst
.operands
[3].reg
;
5761 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5765 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5768 /* Maverick shift immediate instructions.
5769 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5770 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5775 int imm
= inst
.operands
[2].imm
;
5777 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5778 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5780 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5781 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5782 Bit 4 should be 0. */
5783 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
5785 inst
.instruction
|= imm
;
5788 /* XScale instructions. Also sorted arithmetic before move. */
5790 /* Xscale multiply-accumulate (argument parse)
5793 MIAxycc acc0,Rm,Rs. */
5798 inst
.instruction
|= inst
.operands
[1].reg
;
5799 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
5802 /* Xscale move-accumulator-register (argument parse)
5804 MARcc acc0,RdLo,RdHi. */
5809 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
5810 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
5813 /* Xscale move-register-accumulator (argument parse)
5815 MRAcc RdLo,RdHi,acc0. */
5820 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
5821 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
5822 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
5825 /* Encoding functions relevant only to Thumb. */
5827 /* inst.operands[i] is a shifted-register operand; encode
5828 it into inst.instruction in the format used by Thumb32. */
5831 encode_thumb32_shifted_operand (int i
)
5833 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
5834 unsigned int shift
= inst
.operands
[i
].shift_kind
;
5836 constraint (inst
.operands
[i
].immisreg
,
5837 _("shift by register not allowed in thumb mode"));
5838 inst
.instruction
|= inst
.operands
[i
].reg
;
5839 if (shift
== SHIFT_RRX
)
5840 inst
.instruction
|= SHIFT_ROR
<< 4;
5843 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
5844 _("expression too complex"));
5846 constraint (value
> 32
5847 || (value
== 32 && (shift
== SHIFT_LSL
5848 || shift
== SHIFT_ROR
)),
5849 _("shift expression is too large"));
5853 else if (value
== 32)
5856 inst
.instruction
|= shift
<< 4;
5857 inst
.instruction
|= (value
& 0x1c) << 10;
5858 inst
.instruction
|= (value
& 0x03) << 6;
5863 /* inst.operands[i] was set up by parse_address. Encode it into a
5864 Thumb32 format load or store instruction. Reject forms that cannot
5865 be used with such instructions. If is_t is true, reject forms that
5866 cannot be used with a T instruction; if is_d is true, reject forms
5867 that cannot be used with a D instruction. */
5870 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
5872 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
5874 constraint (!inst
.operands
[i
].isreg
,
5875 _("Thumb does not support the ldr =N pseudo-operation"));
5877 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
5878 if (inst
.operands
[i
].immisreg
)
5880 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
5881 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
5882 constraint (inst
.operands
[i
].negative
,
5883 _("Thumb does not support negative register indexing"));
5884 constraint (inst
.operands
[i
].postind
,
5885 _("Thumb does not support register post-indexing"));
5886 constraint (inst
.operands
[i
].writeback
,
5887 _("Thumb does not support register indexing with writeback"));
5888 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
5889 _("Thumb supports only LSL in shifted register indexing"));
5891 inst
.instruction
|= inst
.operands
[1].imm
;
5892 if (inst
.operands
[i
].shifted
)
5894 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
5895 _("expression too complex"));
5896 constraint (inst
.reloc
.exp
.X_add_number
< 0
5897 || inst
.reloc
.exp
.X_add_number
> 3,
5898 _("shift out of range"));
5899 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
5901 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5903 else if (inst
.operands
[i
].preind
)
5905 constraint (is_pc
&& inst
.operands
[i
].writeback
,
5906 _("cannot use writeback with PC-relative addressing"));
5907 constraint (is_t
&& inst
.operands
[1].writeback
,
5908 _("cannot use writeback with this instruction"));
5912 inst
.instruction
|= 0x01000000;
5913 if (inst
.operands
[i
].writeback
)
5914 inst
.instruction
|= 0x00200000;
5918 inst
.instruction
|= 0x00000c00;
5919 if (inst
.operands
[i
].writeback
)
5920 inst
.instruction
|= 0x00000100;
5922 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
5924 else if (inst
.operands
[i
].postind
)
5926 assert (inst
.operands
[i
].writeback
);
5927 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
5928 constraint (is_t
, _("cannot use post-indexing with this instruction"));
5931 inst
.instruction
|= 0x00200000;
5933 inst
.instruction
|= 0x00000900;
5934 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
5936 else /* unindexed - only for coprocessor */
5937 inst
.error
= _("instruction does not accept unindexed addressing");
5940 /* Table of Thumb instructions which exist in both 16- and 32-bit
5941 encodings (the latter only in post-V6T2 cores). The index is the
5942 value used in the insns table below. When there is more than one
5943 possible 16-bit encoding for the instruction, this table always
5945 Also contains several pseudo-instructions used during relaxation. */
5946 #define T16_32_TAB \
5947 X(adc, 4140, eb400000), \
5948 X(adcs, 4140, eb500000), \
5949 X(add, 1c00, eb000000), \
5950 X(adds, 1c00, eb100000), \
5951 X(addi, 0000, f1000000), \
5952 X(addis, 0000, f1100000), \
5953 X(add_pc,000f, f20f0000), \
5954 X(add_sp,000d, f10d0000), \
5955 X(adr, 000f, f20f0000), \
5956 X(and, 4000, ea000000), \
5957 X(ands, 4000, ea100000), \
5958 X(asr, 1000, fa40f000), \
5959 X(asrs, 1000, fa50f000), \
5960 X(b, e000, f000b000), \
5961 X(bcond, d000, f0008000), \
5962 X(bic, 4380, ea200000), \
5963 X(bics, 4380, ea300000), \
5964 X(cmn, 42c0, eb100f00), \
5965 X(cmp, 2800, ebb00f00), \
5966 X(cpsie, b660, f3af8400), \
5967 X(cpsid, b670, f3af8600), \
5968 X(cpy, 4600, ea4f0000), \
5969 X(dec_sp,80dd, f1bd0d00), \
5970 X(eor, 4040, ea800000), \
5971 X(eors, 4040, ea900000), \
5972 X(inc_sp,00dd, f10d0d00), \
5973 X(ldmia, c800, e8900000), \
5974 X(ldr, 6800, f8500000), \
5975 X(ldrb, 7800, f8100000), \
5976 X(ldrh, 8800, f8300000), \
5977 X(ldrsb, 5600, f9100000), \
5978 X(ldrsh, 5e00, f9300000), \
5979 X(ldr_pc,4800, f85f0000), \
5980 X(ldr_pc2,4800, f85f0000), \
5981 X(ldr_sp,9800, f85d0000), \
5982 X(lsl, 0000, fa00f000), \
5983 X(lsls, 0000, fa10f000), \
5984 X(lsr, 0800, fa20f000), \
5985 X(lsrs, 0800, fa30f000), \
5986 X(mov, 2000, ea4f0000), \
5987 X(movs, 2000, ea5f0000), \
5988 X(mul, 4340, fb00f000), \
5989 X(muls, 4340, ffffffff), /* no 32b muls */ \
5990 X(mvn, 43c0, ea6f0000), \
5991 X(mvns, 43c0, ea7f0000), \
5992 X(neg, 4240, f1c00000), /* rsb #0 */ \
5993 X(negs, 4240, f1d00000), /* rsbs #0 */ \
5994 X(orr, 4300, ea400000), \
5995 X(orrs, 4300, ea500000), \
5996 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
5997 X(push, b400, e92d0000), /* stmdb sp!,... */ \
5998 X(rev, ba00, fa90f080), \
5999 X(rev16, ba40, fa90f090), \
6000 X(revsh, bac0, fa90f0b0), \
6001 X(ror, 41c0, fa60f000), \
6002 X(rors, 41c0, fa70f000), \
6003 X(sbc, 4180, eb600000), \
6004 X(sbcs, 4180, eb700000), \
6005 X(stmia, c000, e8800000), \
6006 X(str, 6000, f8400000), \
6007 X(strb, 7000, f8000000), \
6008 X(strh, 8000, f8200000), \
6009 X(str_sp,9000, f84d0000), \
6010 X(sub, 1e00, eba00000), \
6011 X(subs, 1e00, ebb00000), \
6012 X(subi, 8000, f1a00000), \
6013 X(subis, 8000, f1b00000), \
6014 X(sxtb, b240, fa4ff080), \
6015 X(sxth, b200, fa0ff080), \
6016 X(tst, 4200, ea100f00), \
6017 X(uxtb, b2c0, fa5ff080), \
6018 X(uxth, b280, fa1ff080), \
6019 X(nop, bf00, f3af8000), \
6020 X(yield, bf10, f3af8001), \
6021 X(wfe, bf20, f3af8002), \
6022 X(wfi, bf30, f3af8003), \
6023 X(sev, bf40, f3af9004), /* typo, 8004? */
6025 /* To catch errors in encoding functions, the codes are all offset by
6026 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
6027 as 16-bit instructions. */
6028 #define X(a,b,c) T_MNEM_##a
6029 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
6032 #define X(a,b,c) 0x##b
6033 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
6034 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
6037 #define X(a,b,c) 0x##c
6038 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
6039 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
6040 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
6044 /* Thumb instruction encoders, in alphabetical order. */
6048 do_t_add_sub_w (void)
6052 Rd
= inst
.operands
[0].reg
;
6053 Rn
= inst
.operands
[1].reg
;
6055 constraint (Rd
== 15, _("PC not allowed as destination"));
6056 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
6057 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
6060 /* Parse an add or subtract instruction. We get here with inst.instruction
6061 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
6068 Rd
= inst
.operands
[0].reg
;
6069 Rs
= (inst
.operands
[1].present
6070 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
6071 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
6079 flags
= (inst
.instruction
== T_MNEM_adds
6080 || inst
.instruction
== T_MNEM_subs
);
6082 narrow
= (current_it_mask
== 0);
6084 narrow
= (current_it_mask
!= 0);
6085 if (!inst
.operands
[2].isreg
)
6088 if (inst
.size_req
!= 4)
6092 add
= (inst
.instruction
== T_MNEM_add
6093 || inst
.instruction
== T_MNEM_adds
);
6094 /* Attempt to use a narrow opcode, with relaxation if
6096 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
6097 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
6098 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
6099 opcode
= T_MNEM_add_sp
;
6100 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
6101 opcode
= T_MNEM_add_pc
;
6102 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
6105 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
6107 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
6111 inst
.instruction
= THUMB_OP16(opcode
);
6112 inst
.instruction
|= (Rd
<< 4) | Rs
;
6113 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
6114 if (inst
.size_req
!= 2)
6115 inst
.relax
= opcode
;
6118 constraint (inst
.size_req
== 2, BAD_HIREG
);
6120 if (inst
.size_req
== 4
6121 || (inst
.size_req
!= 2 && !opcode
))
6123 /* ??? Convert large immediates to addw/subw. */
6124 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6125 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6126 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6127 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6128 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6133 Rn
= inst
.operands
[2].reg
;
6134 /* See if we can do this with a 16-bit instruction. */
6135 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
6137 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
6142 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
6143 || inst
.instruction
== T_MNEM_add
)
6146 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
6150 if (inst
.instruction
== T_MNEM_add
)
6154 inst
.instruction
= T_OPCODE_ADD_HI
;
6155 inst
.instruction
|= (Rd
& 8) << 4;
6156 inst
.instruction
|= (Rd
& 7);
6157 inst
.instruction
|= Rn
<< 3;
6160 /* ... because addition is commutative! */
6163 inst
.instruction
= T_OPCODE_ADD_HI
;
6164 inst
.instruction
|= (Rd
& 8) << 4;
6165 inst
.instruction
|= (Rd
& 7);
6166 inst
.instruction
|= Rs
<< 3;
6171 /* If we get here, it can't be done in 16 bits. */
6172 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
6173 _("shift must be constant"));
6174 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6175 inst
.instruction
|= Rd
<< 8;
6176 inst
.instruction
|= Rs
<< 16;
6177 encode_thumb32_shifted_operand (2);
6182 constraint (inst
.instruction
== T_MNEM_adds
6183 || inst
.instruction
== T_MNEM_subs
,
6186 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
6188 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
6189 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
6192 inst
.instruction
= (inst
.instruction
== T_MNEM_add
6194 inst
.instruction
|= (Rd
<< 4) | Rs
;
6195 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
6199 Rn
= inst
.operands
[2].reg
;
6200 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
6202 /* We now have Rd, Rs, and Rn set to registers. */
6203 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
6205 /* Can't do this for SUB. */
6206 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
6207 inst
.instruction
= T_OPCODE_ADD_HI
;
6208 inst
.instruction
|= (Rd
& 8) << 4;
6209 inst
.instruction
|= (Rd
& 7);
6211 inst
.instruction
|= Rn
<< 3;
6213 inst
.instruction
|= Rs
<< 3;
6215 constraint (1, _("dest must overlap one source register"));
6219 inst
.instruction
= (inst
.instruction
== T_MNEM_add
6220 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
6221 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
6229 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
6231 /* Defer to section relaxation. */
6232 inst
.relax
= inst
.instruction
;
6233 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6234 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
6236 else if (unified_syntax
&& inst
.size_req
!= 2)
6238 /* Generate a 32-bit opcode. */
6239 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6240 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6241 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
6242 inst
.reloc
.pc_rel
= 1;
6246 /* Generate a 16-bit opcode. */
6247 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6248 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
6249 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
6250 inst
.reloc
.pc_rel
= 1;
6252 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
6256 /* Arithmetic instructions for which there is just one 16-bit
6257 instruction encoding, and it allows only two low registers.
6258 For maximal compatibility with ARM syntax, we allow three register
6259 operands even when Thumb-32 instructions are not available, as long
6260 as the first two are identical. For instance, both "sbc r0,r1" and
6261 "sbc r0,r0,r1" are allowed. */
6267 Rd
= inst
.operands
[0].reg
;
6268 Rs
= (inst
.operands
[1].present
6269 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
6270 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
6271 Rn
= inst
.operands
[2].reg
;
6275 if (!inst
.operands
[2].isreg
)
6277 /* For an immediate, we always generate a 32-bit opcode;
6278 section relaxation will shrink it later if possible. */
6279 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6280 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6281 inst
.instruction
|= Rd
<< 8;
6282 inst
.instruction
|= Rs
<< 16;
6283 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6289 /* See if we can do this with a 16-bit instruction. */
6290 if (THUMB_SETS_FLAGS (inst
.instruction
))
6291 narrow
= current_it_mask
== 0;
6293 narrow
= current_it_mask
!= 0;
6295 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
6297 if (inst
.operands
[2].shifted
)
6299 if (inst
.size_req
== 4)
6305 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6306 inst
.instruction
|= Rd
;
6307 inst
.instruction
|= Rn
<< 3;
6311 /* If we get here, it can't be done in 16 bits. */
6312 constraint (inst
.operands
[2].shifted
6313 && inst
.operands
[2].immisreg
,
6314 _("shift must be constant"));
6315 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6316 inst
.instruction
|= Rd
<< 8;
6317 inst
.instruction
|= Rs
<< 16;
6318 encode_thumb32_shifted_operand (2);
6323 /* On its face this is a lie - the instruction does set the
6324 flags. However, the only supported mnemonic in this mode
6326 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
6328 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
6329 _("unshifted register required"));
6330 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
6331 constraint (Rd
!= Rs
,
6332 _("dest and source1 must be the same register"));
6334 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6335 inst
.instruction
|= Rd
;
6336 inst
.instruction
|= Rn
<< 3;
6340 /* Similarly, but for instructions where the arithmetic operation is
6341 commutative, so we can allow either of them to be different from
6342 the destination operand in a 16-bit instruction. For instance, all
6343 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6350 Rd
= inst
.operands
[0].reg
;
6351 Rs
= (inst
.operands
[1].present
6352 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
6353 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
6354 Rn
= inst
.operands
[2].reg
;
6358 if (!inst
.operands
[2].isreg
)
6360 /* For an immediate, we always generate a 32-bit opcode;
6361 section relaxation will shrink it later if possible. */
6362 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6363 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
6364 inst
.instruction
|= Rd
<< 8;
6365 inst
.instruction
|= Rs
<< 16;
6366 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
6372 /* See if we can do this with a 16-bit instruction. */
6373 if (THUMB_SETS_FLAGS (inst
.instruction
))
6374 narrow
= current_it_mask
== 0;
6376 narrow
= current_it_mask
!= 0;
6378 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
6380 if (inst
.operands
[2].shifted
)
6382 if (inst
.size_req
== 4)
6389 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6390 inst
.instruction
|= Rd
;
6391 inst
.instruction
|= Rn
<< 3;
6396 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6397 inst
.instruction
|= Rd
;
6398 inst
.instruction
|= Rs
<< 3;
6403 /* If we get here, it can't be done in 16 bits. */
6404 constraint (inst
.operands
[2].shifted
6405 && inst
.operands
[2].immisreg
,
6406 _("shift must be constant"));
6407 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6408 inst
.instruction
|= Rd
<< 8;
6409 inst
.instruction
|= Rs
<< 16;
6410 encode_thumb32_shifted_operand (2);
6415 /* On its face this is a lie - the instruction does set the
6416 flags. However, the only supported mnemonic in this mode
6418 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
6420 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
6421 _("unshifted register required"));
6422 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
6424 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6425 inst
.instruction
|= Rd
;
6428 inst
.instruction
|= Rn
<< 3;
6430 inst
.instruction
|= Rs
<< 3;
6432 constraint (1, _("dest must overlap one source register"));
6439 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6440 constraint (msb
> 32, _("bit-field extends past end of register"));
6441 /* The instruction encoding stores the LSB and MSB,
6442 not the LSB and width. */
6443 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6444 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
6445 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
6446 inst
.instruction
|= msb
- 1;
6454 /* #0 in second position is alternative syntax for bfc, which is
6455 the same instruction but with REG_PC in the Rm field. */
6456 if (!inst
.operands
[1].isreg
)
6457 inst
.operands
[1].reg
= REG_PC
;
6459 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6460 constraint (msb
> 32, _("bit-field extends past end of register"));
6461 /* The instruction encoding stores the LSB and MSB,
6462 not the LSB and width. */
6463 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6464 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6465 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
6466 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
6467 inst
.instruction
|= msb
- 1;
6473 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6474 _("bit-field extends past end of register"));
6475 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6476 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6477 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
6478 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
6479 inst
.instruction
|= inst
.operands
[3].imm
- 1;
6482 /* ARM V5 Thumb BLX (argument parse)
6483 BLX <target_addr> which is BLX(1)
6484 BLX <Rm> which is BLX(2)
6485 Unfortunately, there are two different opcodes for this mnemonic.
6486 So, the insns[].value is not used, and the code here zaps values
6487 into inst.instruction.
6489 ??? How to take advantage of the additional two bits of displacement
6490 available in Thumb32 mode? Need new relocation? */
6495 if (inst
.operands
[0].isreg
)
6496 /* We have a register, so this is BLX(2). */
6497 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
6500 /* No register. This must be BLX(1). */
6501 inst
.instruction
= 0xf000e800;
6503 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6504 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
6507 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
6508 inst
.reloc
.pc_rel
= 1;
6516 if (inst
.cond
!= COND_ALWAYS
)
6517 opcode
= T_MNEM_bcond
;
6519 opcode
= inst
.instruction
;
6521 if (unified_syntax
&& inst
.size_req
== 4)
6523 inst
.instruction
= THUMB_OP32(opcode
);
6524 if (inst
.cond
== COND_ALWAYS
)
6525 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
6528 assert (inst
.cond
!= 0xF);
6529 inst
.instruction
|= inst
.cond
<< 22;
6530 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
6535 inst
.instruction
= THUMB_OP16(opcode
);
6536 if (inst
.cond
== COND_ALWAYS
)
6537 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
6540 inst
.instruction
|= inst
.cond
<< 8;
6541 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
6543 /* Allow section relaxation. */
6544 if (unified_syntax
&& inst
.size_req
!= 2)
6545 inst
.relax
= opcode
;
6548 inst
.reloc
.pc_rel
= 1;
6554 if (inst
.operands
[0].present
)
6556 constraint (inst
.operands
[0].imm
> 255,
6557 _("immediate value out of range"));
6558 inst
.instruction
|= inst
.operands
[0].imm
;
6563 do_t_branch23 (void)
6565 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
6566 inst
.reloc
.pc_rel
= 1;
6568 /* If the destination of the branch is a defined symbol which does not have
6569 the THUMB_FUNC attribute, then we must be calling a function which has
6570 the (interfacearm) attribute. We look for the Thumb entry point to that
6571 function and change the branch to refer to that function instead. */
6572 if ( inst
.reloc
.exp
.X_op
== O_symbol
6573 && inst
.reloc
.exp
.X_add_symbol
!= NULL
6574 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
6575 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
6576 inst
.reloc
.exp
.X_add_symbol
=
6577 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
6583 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
6584 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6585 should cause the alignment to be checked once it is known. This is
6586 because BX PC only works if the instruction is word aligned. */
6592 if (inst
.operands
[0].reg
== REG_PC
)
6593 as_tsktsk (_("use of r15 in bxj is not really useful"));
6595 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6601 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6602 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6603 inst
.instruction
|= inst
.operands
[1].reg
;
6610 && (inst
.operands
[1].present
|| inst
.size_req
== 4))
6612 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
6613 inst
.instruction
= 0xf3af8000;
6614 inst
.instruction
|= imod
<< 9;
6615 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
6616 if (inst
.operands
[1].present
)
6617 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
6621 constraint (inst
.operands
[1].present
,
6622 _("Thumb does not support the 2-argument "
6623 "form of this instruction"));
6624 inst
.instruction
|= inst
.operands
[0].imm
;
6628 /* THUMB CPY instruction (argument parse). */
6633 if (inst
.size_req
== 4)
6635 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
6636 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6637 inst
.instruction
|= inst
.operands
[1].reg
;
6641 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
6642 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
6643 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6650 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
6651 inst
.instruction
|= inst
.operands
[0].reg
;
6652 inst
.reloc
.pc_rel
= 1;
6653 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
6659 if (unified_syntax
&& inst
.size_req
== 4)
6660 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6662 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6668 unsigned int cond
= inst
.operands
[0].imm
;
6670 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
6673 /* If the condition is a negative condition, invert the mask. */
6674 if ((cond
& 0x1) == 0x0)
6676 unsigned int mask
= inst
.instruction
& 0x000f;
6678 if ((mask
& 0x7) == 0)
6679 /* no conversion needed */;
6680 else if ((mask
& 0x3) == 0)
6682 else if ((mask
& 0x1) == 0)
6687 inst
.instruction
&= 0xfff0;
6688 inst
.instruction
|= mask
;
6691 inst
.instruction
|= cond
<< 4;
6697 /* This really doesn't seem worth it. */
6698 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
6699 _("expression too complex"));
6700 constraint (inst
.operands
[1].writeback
,
6701 _("Thumb load/store multiple does not support {reglist}^"));
6705 /* See if we can use a 16-bit instruction. */
6706 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
6707 && inst
.size_req
!= 4
6708 && inst
.operands
[0].reg
<= 7
6709 && !(inst
.operands
[1].imm
& ~0xff)
6710 && (inst
.instruction
== T_MNEM_stmia
6711 ? inst
.operands
[0].writeback
6712 : (inst
.operands
[0].writeback
6713 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
6715 if (inst
.instruction
== T_MNEM_stmia
6716 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6717 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
6718 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6719 inst
.operands
[0].reg
);
6721 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6722 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6723 inst
.instruction
|= inst
.operands
[1].imm
;
6727 if (inst
.operands
[1].imm
& (1 << 13))
6728 as_warn (_("SP should not be in register list"));
6729 if (inst
.instruction
== T_MNEM_stmia
)
6731 if (inst
.operands
[1].imm
& (1 << 15))
6732 as_warn (_("PC should not be in register list"));
6733 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6734 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6735 inst
.operands
[0].reg
);
6739 if (inst
.operands
[1].imm
& (1 << 14)
6740 && inst
.operands
[1].imm
& (1 << 15))
6741 as_warn (_("LR and PC should not both be in register list"));
6742 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6743 && inst
.operands
[0].writeback
)
6744 as_warn (_("base register should not be in register list "
6745 "when written back"));
6747 if (inst
.instruction
< 0xffff)
6748 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
6749 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6750 inst
.instruction
|= inst
.operands
[1].imm
;
6751 if (inst
.operands
[0].writeback
)
6752 inst
.instruction
|= WRITE_BACK
;
6757 constraint (inst
.operands
[0].reg
> 7
6758 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
6759 if (inst
.instruction
== T_MNEM_stmia
)
6761 if (!inst
.operands
[0].writeback
)
6762 as_warn (_("this instruction will write back the base register"));
6763 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
6764 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
6765 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6766 inst
.operands
[0].reg
);
6770 if (!inst
.operands
[0].writeback
6771 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
6772 as_warn (_("this instruction will write back the base register"));
6773 else if (inst
.operands
[0].writeback
6774 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
6775 as_warn (_("this instruction will not write back the base register"));
6778 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6779 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6780 inst
.instruction
|= inst
.operands
[1].imm
;
6787 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6788 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6789 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6790 || inst
.operands
[1].negative
,
6793 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6794 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6795 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
6801 if (!inst
.operands
[1].present
)
6803 constraint (inst
.operands
[0].reg
== REG_LR
,
6804 _("r14 not allowed as first register "
6805 "when second register is omitted"));
6806 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6808 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
6811 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6812 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6813 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6819 unsigned long opcode
;
6822 opcode
= inst
.instruction
;
6825 if (inst
.operands
[1].isreg
6826 && !inst
.operands
[1].writeback
6827 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
6828 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
6830 && inst
.size_req
!= 4)
6832 /* Insn may have a 16-bit form. */
6833 Rn
= inst
.operands
[1].reg
;
6834 if (inst
.operands
[1].immisreg
)
6836 inst
.instruction
= THUMB_OP16 (opcode
);
6838 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
6841 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
6842 && opcode
!= T_MNEM_ldrsb
)
6843 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
6844 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
6851 if (inst
.reloc
.pc_rel
)
6852 opcode
= T_MNEM_ldr_pc2
;
6854 opcode
= T_MNEM_ldr_pc
;
6858 if (opcode
== T_MNEM_ldr
)
6859 opcode
= T_MNEM_ldr_sp
;
6861 opcode
= T_MNEM_str_sp
;
6863 inst
.instruction
= inst
.operands
[0].reg
<< 8;
6867 inst
.instruction
= inst
.operands
[0].reg
;
6868 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6870 inst
.instruction
|= THUMB_OP16 (opcode
);
6871 if (inst
.size_req
== 2)
6872 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
6874 inst
.relax
= opcode
;
6878 /* Definitely a 32-bit variant. */
6879 inst
.instruction
= THUMB_OP32 (opcode
);
6880 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6881 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
6885 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
6887 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
6889 /* Only [Rn,Rm] is acceptable. */
6890 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
6891 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
6892 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
6893 || inst
.operands
[1].negative
,
6894 _("Thumb does not support this addressing mode"));
6895 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6899 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
6900 if (!inst
.operands
[1].isreg
)
6901 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
6904 constraint (!inst
.operands
[1].preind
6905 || inst
.operands
[1].shifted
6906 || inst
.operands
[1].writeback
,
6907 _("Thumb does not support this addressing mode"));
6908 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
6910 constraint (inst
.instruction
& 0x0600,
6911 _("byte or halfword not valid for base register"));
6912 constraint (inst
.operands
[1].reg
== REG_PC
6913 && !(inst
.instruction
& THUMB_LOAD_BIT
),
6914 _("r15 based store not allowed"));
6915 constraint (inst
.operands
[1].immisreg
,
6916 _("invalid base register for register offset"));
6918 if (inst
.operands
[1].reg
== REG_PC
)
6919 inst
.instruction
= T_OPCODE_LDR_PC
;
6920 else if (inst
.instruction
& THUMB_LOAD_BIT
)
6921 inst
.instruction
= T_OPCODE_LDR_SP
;
6923 inst
.instruction
= T_OPCODE_STR_SP
;
6925 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6926 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
6930 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
6931 if (!inst
.operands
[1].immisreg
)
6933 /* Immediate offset. */
6934 inst
.instruction
|= inst
.operands
[0].reg
;
6935 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6936 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
6940 /* Register offset. */
6941 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
6942 constraint (inst
.operands
[1].negative
,
6943 _("Thumb does not support this addressing mode"));
6946 switch (inst
.instruction
)
6948 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
6949 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
6950 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
6951 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
6952 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
6953 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
6954 case 0x5600 /* ldrsb */:
6955 case 0x5e00 /* ldrsh */: break;
6959 inst
.instruction
|= inst
.operands
[0].reg
;
6960 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
6961 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
6967 if (!inst
.operands
[1].present
)
6969 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6970 constraint (inst
.operands
[0].reg
== REG_LR
,
6971 _("r14 not allowed here"));
6973 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6974 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
6975 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
6982 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6983 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
6989 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6990 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6991 inst
.instruction
|= inst
.operands
[2].reg
;
6992 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
6998 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6999 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
7000 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7001 inst
.instruction
|= inst
.operands
[3].reg
;
7009 int r0off
= (inst
.instruction
== T_MNEM_mov
7010 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
7011 unsigned long opcode
;
7013 bfd_boolean low_regs
;
7015 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
7016 opcode
= inst
.instruction
;
7017 if (current_it_mask
)
7018 narrow
= opcode
!= T_MNEM_movs
;
7020 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
7021 if (inst
.size_req
== 4
7022 || inst
.operands
[1].shifted
)
7025 if (!inst
.operands
[1].isreg
)
7027 /* Immediate operand. */
7028 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
7030 if (low_regs
&& narrow
)
7032 inst
.instruction
= THUMB_OP16 (opcode
);
7033 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7034 if (inst
.size_req
== 2)
7035 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
7037 inst
.relax
= opcode
;
7041 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7042 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
7043 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
7044 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
7049 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7050 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
7051 encode_thumb32_shifted_operand (1);
7054 switch (inst
.instruction
)
7057 inst
.instruction
= T_OPCODE_MOV_HR
;
7058 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
7059 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
7060 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7064 /* We know we have low registers at this point.
7065 Generate ADD Rd, Rs, #0. */
7066 inst
.instruction
= T_OPCODE_ADD_I3
;
7067 inst
.instruction
|= inst
.operands
[0].reg
;
7068 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7074 inst
.instruction
= T_OPCODE_CMP_LR
;
7075 inst
.instruction
|= inst
.operands
[0].reg
;
7076 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7080 inst
.instruction
= T_OPCODE_CMP_HR
;
7081 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
7082 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
7083 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7090 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7091 if (inst
.operands
[1].isreg
)
7093 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
7095 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
7096 since a MOV instruction produces unpredictable results. */
7097 if (inst
.instruction
== T_OPCODE_MOV_I8
)
7098 inst
.instruction
= T_OPCODE_ADD_I3
;
7100 inst
.instruction
= T_OPCODE_CMP_LR
;
7102 inst
.instruction
|= inst
.operands
[0].reg
;
7103 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7107 if (inst
.instruction
== T_OPCODE_MOV_I8
)
7108 inst
.instruction
= T_OPCODE_MOV_HR
;
7110 inst
.instruction
= T_OPCODE_CMP_HR
;
7116 constraint (inst
.operands
[0].reg
> 7,
7117 _("only lo regs allowed with immediate"));
7118 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7119 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
7126 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7127 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf000) << 4;
7128 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0800) << 15;
7129 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0700) << 4;
7130 inst
.instruction
|= (inst
.operands
[1].imm
& 0x00ff);
7138 int r0off
= (inst
.instruction
== T_MNEM_mvn
7139 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
7142 if (inst
.size_req
== 4
7143 || inst
.instruction
> 0xffff
7144 || inst
.operands
[1].shifted
7145 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
7147 else if (inst
.instruction
== T_MNEM_cmn
)
7149 else if (THUMB_SETS_FLAGS (inst
.instruction
))
7150 narrow
= (current_it_mask
== 0);
7152 narrow
= (current_it_mask
!= 0);
7154 if (!inst
.operands
[1].isreg
)
7156 /* For an immediate, we always generate a 32-bit opcode;
7157 section relaxation will shrink it later if possible. */
7158 if (inst
.instruction
< 0xffff)
7159 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7160 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
7161 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
7162 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
7166 /* See if we can do this with a 16-bit instruction. */
7169 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7170 inst
.instruction
|= inst
.operands
[0].reg
;
7171 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7175 constraint (inst
.operands
[1].shifted
7176 && inst
.operands
[1].immisreg
,
7177 _("shift must be constant"));
7178 if (inst
.instruction
< 0xffff)
7179 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7180 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
7181 encode_thumb32_shifted_operand (1);
7187 constraint (inst
.instruction
> 0xffff
7188 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
7189 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
7190 _("unshifted register required"));
7191 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
7194 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7195 inst
.instruction
|= inst
.operands
[0].reg
;
7196 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7203 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7204 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7206 _("'CPSR' or 'SPSR' expected"));
7207 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7208 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
) >> 2;
7214 constraint (!inst
.operands
[1].isreg
,
7215 _("Thumb encoding does not support an immediate here"));
7216 inst
.instruction
|= (inst
.operands
[0].imm
& SPSR_BIT
) >> 2;
7217 inst
.instruction
|= (inst
.operands
[0].imm
& ~SPSR_BIT
) >> 8;
7218 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7224 if (!inst
.operands
[2].present
)
7225 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7227 /* There is no 32-bit MULS and no 16-bit MUL. */
7228 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
7230 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7231 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7232 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7233 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
7237 constraint (!unified_syntax
7238 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
7239 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
7242 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7243 inst
.instruction
|= inst
.operands
[0].reg
;
7245 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7246 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
7247 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
7248 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7250 constraint (1, _("dest must overlap one source register"));
7257 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7258 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
7259 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7260 inst
.instruction
|= inst
.operands
[3].reg
;
7262 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7263 as_tsktsk (_("rdhi and rdlo must be different"));
7271 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
7273 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7274 inst
.instruction
|= inst
.operands
[0].imm
;
7278 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7279 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
7284 constraint (inst
.operands
[0].present
,
7285 _("Thumb does not support NOP with hints"));
7286 inst
.instruction
= 0x46c0;
7297 if (THUMB_SETS_FLAGS (inst
.instruction
))
7298 narrow
= (current_it_mask
== 0);
7300 narrow
= (current_it_mask
!= 0);
7301 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
7303 if (inst
.size_req
== 4)
7308 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7309 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7310 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7314 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7315 inst
.instruction
|= inst
.operands
[0].reg
;
7316 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7321 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
7323 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
7325 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7326 inst
.instruction
|= inst
.operands
[0].reg
;
7327 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7334 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7335 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7336 inst
.instruction
|= inst
.operands
[2].reg
;
7337 if (inst
.operands
[3].present
)
7339 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
7340 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7341 _("expression too complex"));
7342 inst
.instruction
|= (val
& 0x1c) << 10;
7343 inst
.instruction
|= (val
& 0x03) << 6;
7350 if (!inst
.operands
[3].present
)
7351 inst
.instruction
&= ~0x00000020;
7358 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
7362 do_t_push_pop (void)
7366 constraint (inst
.operands
[0].writeback
,
7367 _("push/pop do not support {reglist}^"));
7368 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
7369 _("expression too complex"));
7371 mask
= inst
.operands
[0].imm
;
7372 if ((mask
& ~0xff) == 0)
7373 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7374 else if ((inst
.instruction
== T_MNEM_push
7375 && (mask
& ~0xff) == 1 << REG_LR
)
7376 || (inst
.instruction
== T_MNEM_pop
7377 && (mask
& ~0xff) == 1 << REG_PC
))
7379 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7380 inst
.instruction
|= THUMB_PP_PC_LR
;
7383 else if (unified_syntax
)
7385 if (mask
& (1 << 13))
7386 inst
.error
= _("SP not allowed in register list");
7387 if (inst
.instruction
== T_MNEM_push
)
7389 if (mask
& (1 << 15))
7390 inst
.error
= _("PC not allowed in register list");
7394 if (mask
& (1 << 14)
7395 && mask
& (1 << 15))
7396 inst
.error
= _("LR and PC should not both be in register list");
7398 if ((mask
& (mask
- 1)) == 0)
7400 /* Single register push/pop implemented as str/ldr. */
7401 if (inst
.instruction
== T_MNEM_push
)
7402 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
7404 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
7405 mask
= ffs(mask
) - 1;
7409 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7413 inst
.error
= _("invalid register list to push/pop instruction");
7417 inst
.instruction
|= mask
;
7423 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7424 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7430 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
7431 && inst
.size_req
!= 4)
7433 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7434 inst
.instruction
|= inst
.operands
[0].reg
;
7435 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7437 else if (unified_syntax
)
7439 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7440 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7441 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7442 inst
.instruction
|= inst
.operands
[1].reg
;
7445 inst
.error
= BAD_HIREG
;
7453 Rd
= inst
.operands
[0].reg
;
7454 Rs
= (inst
.operands
[1].present
7455 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
7456 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
7458 inst
.instruction
|= Rd
<< 8;
7459 inst
.instruction
|= Rs
<< 16;
7460 if (!inst
.operands
[2].isreg
)
7462 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
7463 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
7466 encode_thumb32_shifted_operand (2);
7472 if (inst
.operands
[0].imm
)
7473 inst
.instruction
|= 0x8;
7479 if (!inst
.operands
[1].present
)
7480 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7487 switch (inst
.instruction
)
7490 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
7492 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
7494 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
7496 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
7500 if (THUMB_SETS_FLAGS (inst
.instruction
))
7501 narrow
= (current_it_mask
== 0);
7503 narrow
= (current_it_mask
!= 0);
7504 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
7506 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
7508 if (inst
.operands
[2].isreg
7509 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
7510 || inst
.operands
[2].reg
> 7))
7512 if (inst
.size_req
== 4)
7517 if (inst
.operands
[2].isreg
)
7519 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7520 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7521 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7522 inst
.instruction
|= inst
.operands
[2].reg
;
7526 inst
.operands
[1].shifted
= 1;
7527 inst
.operands
[1].shift_kind
= shift_kind
;
7528 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
7529 ? T_MNEM_movs
: T_MNEM_mov
);
7530 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7531 encode_thumb32_shifted_operand (1);
7532 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7533 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7538 if (inst
.operands
[2].isreg
)
7542 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
7543 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
7544 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
7545 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
7549 inst
.instruction
|= inst
.operands
[0].reg
;
7550 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
7556 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
7557 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
7558 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
7561 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
7562 inst
.instruction
|= inst
.operands
[0].reg
;
7563 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7569 constraint (inst
.operands
[0].reg
> 7
7570 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
7571 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
7573 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
7575 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
7576 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
7577 _("source1 and dest must be same register"));
7579 switch (inst
.instruction
)
7581 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
7582 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
7583 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
7584 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
7588 inst
.instruction
|= inst
.operands
[0].reg
;
7589 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
7593 switch (inst
.instruction
)
7595 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
7596 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
7597 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
7598 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
7601 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
7602 inst
.instruction
|= inst
.operands
[0].reg
;
7603 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7611 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7612 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7613 inst
.instruction
|= inst
.operands
[2].reg
;
7619 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
7620 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7621 _("expression too complex"));
7622 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7623 inst
.instruction
|= (value
& 0xf000) >> 12;
7624 inst
.instruction
|= (value
& 0x0ff0);
7625 inst
.instruction
|= (value
& 0x000f) << 16;
7631 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7632 inst
.instruction
|= inst
.operands
[1].imm
- 1;
7633 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7635 if (inst
.operands
[3].present
)
7637 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7638 _("expression too complex"));
7640 if (inst
.reloc
.exp
.X_add_number
!= 0)
7642 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
7643 inst
.instruction
|= 0x00200000; /* sh bit */
7644 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
7645 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
7647 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7654 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7655 inst
.instruction
|= inst
.operands
[1].imm
- 1;
7656 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7662 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7663 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7664 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7665 || inst
.operands
[2].negative
,
7668 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7669 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7670 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7671 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
7677 if (!inst
.operands
[2].present
)
7678 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
7680 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7681 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7682 || inst
.operands
[0].reg
== inst
.operands
[3].reg
7683 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
7686 inst
.instruction
|= inst
.operands
[0].reg
;
7687 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7688 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7689 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7695 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7696 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7697 inst
.instruction
|= inst
.operands
[2].reg
;
7698 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
7704 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
7705 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
7706 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
7708 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
7709 inst
.instruction
|= inst
.operands
[0].reg
;
7710 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
7712 else if (unified_syntax
)
7714 if (inst
.instruction
<= 0xffff)
7715 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
7716 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7717 inst
.instruction
|= inst
.operands
[1].reg
;
7718 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
7722 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
7723 _("Thumb encoding does not support rotation"));
7724 constraint (1, BAD_HIREG
);
7731 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7739 half
= (inst
.instruction
& 0x10) != 0;
7740 constraint (inst
.operands
[0].imm
== 15,
7741 _("PC is not a valid index register"));
7742 constraint (!half
&& inst
.operands
[0].shifted
,
7743 _("instruction does not allow shifted index"));
7744 constraint (half
&& !inst
.operands
[0].shifted
,
7745 _("instruction requires shifted index"));
7746 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
7752 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7753 inst
.instruction
|= inst
.operands
[1].imm
;
7754 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7756 if (inst
.operands
[3].present
)
7758 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7759 _("expression too complex"));
7760 if (inst
.reloc
.exp
.X_add_number
!= 0)
7762 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
7763 inst
.instruction
|= 0x00200000; /* sh bit */
7765 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
7766 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
7768 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7775 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7776 inst
.instruction
|= inst
.operands
[1].imm
;
7777 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7780 /* Overall per-instruction processing. */
7782 /* We need to be able to fix up arbitrary expressions in some statements.
7783 This is so that we can handle symbols that are an arbitrary distance from
7784 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7785 which returns part of an address in a form which will be valid for
7786 a data instruction. We do this by pushing the expression into a symbol
7787 in the expr_section, and creating a fix for that. */
7790 fix_new_arm (fragS
* frag
,
7805 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
7809 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
7814 /* Mark whether the fix is to a THUMB instruction, or an ARM
7816 new_fix
->tc_fix_data
= thumb_mode
;
7819 /* Create a frg for an instruction requiring relaxation. */
7821 output_relax_insn (void)
7827 switch (inst
.reloc
.exp
.X_op
)
7830 sym
= inst
.reloc
.exp
.X_add_symbol
;
7831 offset
= inst
.reloc
.exp
.X_add_number
;
7835 offset
= inst
.reloc
.exp
.X_add_number
;
7838 sym
= make_expr_symbol (&inst
.reloc
.exp
);
7842 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
7843 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
7844 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
7847 dwarf2_emit_insn (INSN_SIZE
);
7851 /* Write a 32-bit thumb instruction to buf. */
7853 put_thumb32_insn (char * buf
, unsigned long insn
)
7855 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
7856 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
7860 output_inst (const char * str
)
7866 as_bad ("%s -- `%s'", inst
.error
, str
);
7870 output_relax_insn();
7876 to
= frag_more (inst
.size
);
7878 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
7880 assert (inst
.size
== (2 * THUMB_SIZE
));
7881 put_thumb32_insn (to
, inst
.instruction
);
7883 else if (inst
.size
> INSN_SIZE
)
7885 assert (inst
.size
== (2 * INSN_SIZE
));
7886 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
7887 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
7890 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
7892 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
7893 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
7894 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
7898 dwarf2_emit_insn (inst
.size
);
7902 /* Tag values used in struct asm_opcode's tag field. */
7905 OT_unconditional
, /* Instruction cannot be conditionalized.
7906 The ARM condition field is still 0xE. */
7907 OT_unconditionalF
, /* Instruction cannot be conditionalized
7908 and carries 0xF in its ARM condition field. */
7909 OT_csuffix
, /* Instruction takes a conditional suffix. */
7910 OT_cinfix3
, /* Instruction takes a conditional infix,
7911 beginning at character index 3. (In
7912 unified mode, it becomes a suffix.) */
7913 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
7914 character index 3, even in unified mode. Used for
7915 legacy instructions where suffix and infix forms
7916 may be ambiguous. */
7917 OT_csuf_or_in3
, /* Instruction takes either a conditional
7918 suffix or an infix at character index 3. */
7919 OT_odd_infix_unc
, /* This is the unconditional variant of an
7920 instruction that takes a conditional infix
7921 at an unusual position. In unified mode,
7922 this variant will accept a suffix. */
7923 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
7924 are the conditional variants of instructions that
7925 take conditional infixes in unusual positions.
7926 The infix appears at character index
7927 (tag - OT_odd_infix_0). These are not accepted
7931 /* Subroutine of md_assemble, responsible for looking up the primary
7932 opcode from the mnemonic the user wrote. STR points to the
7933 beginning of the mnemonic.
7935 This is not simply a hash table lookup, because of conditional
7936 variants. Most instructions have conditional variants, which are
7937 expressed with a _conditional affix_ to the mnemonic. If we were
7938 to encode each conditional variant as a literal string in the opcode
7939 table, it would have approximately 20,000 entries.
7941 Most mnemonics take this affix as a suffix, and in unified syntax,
7942 'most' is upgraded to 'all'. However, in the divided syntax, some
7943 instructions take the affix as an infix, notably the s-variants of
7944 the arithmetic instructions. Of those instructions, all but six
7945 have the infix appear after the third character of the mnemonic.
7947 Accordingly, the algorithm for looking up primary opcodes given
7950 1. Look up the identifier in the opcode table.
7951 If we find a match, go to step U.
7953 2. Look up the last two characters of the identifier in the
7954 conditions table. If we find a match, look up the first N-2
7955 characters of the identifier in the opcode table. If we
7956 find a match, go to step CE.
7958 3. Look up the fourth and fifth characters of the identifier in
7959 the conditions table. If we find a match, extract those
7960 characters from the identifier, and look up the remaining
7961 characters in the opcode table. If we find a match, go
7966 U. Examine the tag field of the opcode structure, in case this is
7967 one of the six instructions with its conditional infix in an
7968 unusual place. If it is, the tag tells us where to find the
7969 infix; look it up in the conditions table and set inst.cond
7970 accordingly. Otherwise, this is an unconditional instruction.
7971 Again set inst.cond accordingly. Return the opcode structure.
7973 CE. Examine the tag field to make sure this is an instruction that
7974 should receive a conditional suffix. If it is not, fail.
7975 Otherwise, set inst.cond from the suffix we already looked up,
7976 and return the opcode structure.
7978 CM. Examine the tag field to make sure this is an instruction that
7979 should receive a conditional infix after the third character.
7980 If it is not, fail. Otherwise, undo the edits to the current
7981 line of input and proceed as for case CE. */
7983 static const struct asm_opcode
*
7984 opcode_lookup (char **str
)
7988 const struct asm_opcode
*opcode
;
7989 const struct asm_cond
*cond
;
7992 /* Scan up to the end of the mnemonic, which must end in white space,
7993 '.' (in unified mode only), or end of string. */
7994 for (base
= end
= *str
; *end
!= '\0'; end
++)
7995 if (*end
== ' ' || (unified_syntax
&& *end
== '.'))
8001 /* Handle a possible width suffix. */
8004 if (end
[1] == 'w' && (end
[2] == ' ' || end
[2] == '\0'))
8006 else if (end
[1] == 'n' && (end
[2] == ' ' || end
[2] == '\0'))
8016 /* Look for unaffixed or special-case affixed mnemonic. */
8017 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
8021 if (opcode
->tag
< OT_odd_infix_0
)
8023 inst
.cond
= COND_ALWAYS
;
8028 as_warn (_("conditional infixes are deprecated in unified syntax"));
8029 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
8030 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
8033 inst
.cond
= cond
->value
;
8037 /* Cannot have a conditional suffix on a mnemonic of less than two
8042 /* Look for suffixed mnemonic. */
8044 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
8045 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
8049 switch (opcode
->tag
)
8051 case OT_cinfix3_legacy
:
8052 /* Ignore conditional suffixes matched on infix only mnemonics. */
8056 case OT_odd_infix_unc
:
8057 if (!unified_syntax
)
8059 /* else fall through */
8062 case OT_csuf_or_in3
:
8063 inst
.cond
= cond
->value
;
8066 case OT_unconditional
:
8067 case OT_unconditionalF
:
8068 /* delayed diagnostic */
8069 inst
.error
= BAD_COND
;
8070 inst
.cond
= COND_ALWAYS
;
8078 /* Cannot have a usual-position infix on a mnemonic of less than
8079 six characters (five would be a suffix). */
8083 /* Look for infixed mnemonic in the usual position. */
8085 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
8089 memcpy (save
, affix
, 2);
8090 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
8091 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
8092 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
8093 memcpy (affix
, save
, 2);
8095 if (opcode
&& (opcode
->tag
== OT_cinfix3
|| opcode
->tag
== OT_csuf_or_in3
8096 || opcode
->tag
== OT_cinfix3_legacy
))
8099 if (unified_syntax
&& opcode
->tag
== OT_cinfix3
)
8100 as_warn (_("conditional infixes are deprecated in unified syntax"));
8102 inst
.cond
= cond
->value
;
8110 md_assemble (char *str
)
8113 const struct asm_opcode
* opcode
;
8115 /* Align the previous label if needed. */
8116 if (last_label_seen
!= NULL
)
8118 symbol_set_frag (last_label_seen
, frag_now
);
8119 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
8120 S_SET_SEGMENT (last_label_seen
, now_seg
);
8123 memset (&inst
, '\0', sizeof (inst
));
8124 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8126 opcode
= opcode_lookup (&p
);
8129 /* It wasn't an instruction, but it might be a register alias of
8130 the form alias .req reg. */
8131 if (!create_register_alias (str
, p
))
8132 as_bad (_("bad instruction `%s'"), str
);
8139 arm_feature_set variant
;
8141 variant
= cpu_variant
;
8142 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
8143 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
8144 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
8145 /* Check that this instruction is supported for this CPU. */
8147 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
))
8149 as_bad (_("selected processor does not support `%s'"), str
);
8152 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
8153 && opcode
->tencode
!= do_t_branch
)
8155 as_bad (_("Thumb does not support conditional execution"));
8159 /* Check conditional suffixes. */
8160 if (current_it_mask
)
8163 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
8164 if (cond
!= inst
.cond
)
8166 as_bad (_("incorrect condition in IT block"));
8169 current_it_mask
<<= 1;
8170 current_it_mask
&= 0x1f;
8172 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
8174 as_bad (_("thumb conditional instrunction not in IT block"));
8178 mapping_state (MAP_THUMB
);
8179 inst
.instruction
= opcode
->tvalue
;
8181 if (!parse_operands (p
, opcode
->operands
))
8184 /* Clear current_it_mask at the end of an IT block. */
8185 if (current_it_mask
== 0x10)
8186 current_it_mask
= 0;
8188 if (!(inst
.error
|| inst
.relax
))
8190 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
8191 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
8192 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
8194 as_bad (_("cannot honor width suffix -- `%s'"), str
);
8198 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8200 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
8201 set those bits when Thumb-2 32-bit instuctions are seen. ie.
8202 anything other than bl/blx.
8203 This is overly pessimistic for relaxable instructions. */
8204 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
8206 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8211 /* Check that this instruction is supported for this CPU. */
8212 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
8214 as_bad (_("selected processor does not support `%s'"), str
);
8219 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
8223 mapping_state (MAP_ARM
);
8224 inst
.instruction
= opcode
->avalue
;
8225 if (opcode
->tag
== OT_unconditionalF
)
8226 inst
.instruction
|= 0xF << 28;
8228 inst
.instruction
|= inst
.cond
<< 28;
8229 inst
.size
= INSN_SIZE
;
8230 if (!parse_operands (p
, opcode
->operands
))
8232 /* Arm mode bx is marked as both v4T and v5 because it's still required
8233 on a hypothetical non-thumb v5 core. */
8234 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
8235 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
8236 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
8238 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8244 /* Various frobbings of labels and their addresses. */
8247 arm_start_line_hook (void)
8249 last_label_seen
= NULL
;
8253 arm_frob_label (symbolS
* sym
)
8255 last_label_seen
= sym
;
8257 ARM_SET_THUMB (sym
, thumb_mode
);
8259 #if defined OBJ_COFF || defined OBJ_ELF
8260 ARM_SET_INTERWORK (sym
, support_interwork
);
8263 /* Note - do not allow local symbols (.Lxxx) to be labeled
8264 as Thumb functions. This is because these labels, whilst
8265 they exist inside Thumb code, are not the entry points for
8266 possible ARM->Thumb calls. Also, these labels can be used
8267 as part of a computed goto or switch statement. eg gcc
8268 can generate code that looks like this:
8280 The first instruction loads the address of the jump table.
8281 The second instruction converts a table index into a byte offset.
8282 The third instruction gets the jump address out of the table.
8283 The fourth instruction performs the jump.
8285 If the address stored at .Laaa is that of a symbol which has the
8286 Thumb_Func bit set, then the linker will arrange for this address
8287 to have the bottom bit set, which in turn would mean that the
8288 address computation performed by the third instruction would end
8289 up with the bottom bit set. Since the ARM is capable of unaligned
8290 word loads, the instruction would then load the incorrect address
8291 out of the jump table, and chaos would ensue. */
8292 if (label_is_thumb_function_name
8293 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
8294 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
8296 /* When the address of a Thumb function is taken the bottom
8297 bit of that address should be set. This will allow
8298 interworking between Arm and Thumb functions to work
8301 THUMB_SET_FUNC (sym
, 1);
8303 label_is_thumb_function_name
= FALSE
;
8307 dwarf2_emit_label (sym
);
8312 arm_data_in_code (void)
8314 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
8316 *input_line_pointer
= '/';
8317 input_line_pointer
+= 5;
8318 *input_line_pointer
= 0;
8326 arm_canonicalize_symbol_name (char * name
)
8330 if (thumb_mode
&& (len
= strlen (name
)) > 5
8331 && streq (name
+ len
- 5, "/data"))
8332 *(name
+ len
- 5) = 0;
8337 /* Table of all register names defined by default. The user can
8338 define additional names with .req. Note that all register names
8339 should appear in both upper and lowercase variants. Some registers
8340 also have mixed-case names. */
8342 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
8343 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8344 #define REGSET(p,t) \
8345 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8346 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8347 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8348 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8350 static const struct reg_entry reg_names
[] =
8352 /* ARM integer registers. */
8353 REGSET(r
, RN
), REGSET(R
, RN
),
8355 /* ATPCS synonyms. */
8356 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
8357 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
8358 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
8360 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
8361 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
8362 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
8364 /* Well-known aliases. */
8365 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
8366 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
8368 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
8369 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
8371 /* Coprocessor numbers. */
8372 REGSET(p
, CP
), REGSET(P
, CP
),
8374 /* Coprocessor register numbers. The "cr" variants are for backward
8376 REGSET(c
, CN
), REGSET(C
, CN
),
8377 REGSET(cr
, CN
), REGSET(CR
, CN
),
8379 /* FPA registers. */
8380 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
8381 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
8383 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
8384 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
8386 /* VFP SP registers. */
8388 REGNUM(s
,16,VFS
), REGNUM(s
,17,VFS
), REGNUM(s
,18,VFS
), REGNUM(s
,19,VFS
),
8389 REGNUM(s
,20,VFS
), REGNUM(s
,21,VFS
), REGNUM(s
,22,VFS
), REGNUM(s
,23,VFS
),
8390 REGNUM(s
,24,VFS
), REGNUM(s
,25,VFS
), REGNUM(s
,26,VFS
), REGNUM(s
,27,VFS
),
8391 REGNUM(s
,28,VFS
), REGNUM(s
,29,VFS
), REGNUM(s
,30,VFS
), REGNUM(s
,31,VFS
),
8394 REGNUM(S
,16,VFS
), REGNUM(S
,17,VFS
), REGNUM(S
,18,VFS
), REGNUM(S
,19,VFS
),
8395 REGNUM(S
,20,VFS
), REGNUM(S
,21,VFS
), REGNUM(S
,22,VFS
), REGNUM(S
,23,VFS
),
8396 REGNUM(S
,24,VFS
), REGNUM(S
,25,VFS
), REGNUM(S
,26,VFS
), REGNUM(S
,27,VFS
),
8397 REGNUM(S
,28,VFS
), REGNUM(S
,29,VFS
), REGNUM(S
,30,VFS
), REGNUM(S
,31,VFS
),
8399 /* VFP DP Registers. */
8400 REGSET(d
,VFD
), REGSET(D
,VFS
),
8402 /* VFP control registers. */
8403 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
8404 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
8406 /* Maverick DSP coprocessor registers. */
8407 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
8408 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
8410 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
8411 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
8412 REGDEF(dspsc
,0,DSPSC
),
8414 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
8415 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
8416 REGDEF(DSPSC
,0,DSPSC
),
8418 /* iWMMXt data registers - p0, c0-15. */
8419 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
8421 /* iWMMXt control registers - p1, c0-3. */
8422 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
8423 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
8424 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
8425 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
8427 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
8428 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
8429 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
8430 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
8431 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
8433 /* XScale accumulator registers. */
8434 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
8440 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
8441 within psr_required_here. */
8442 static const struct asm_psr psrs
[] =
8444 /* Backward compatibility notation. Note that "all" is no longer
8445 truly all possible PSR bits. */
8446 {"all", PSR_c
| PSR_f
},
8450 /* Individual flags. */
8455 /* Combinations of flags. */
8456 {"fs", PSR_f
| PSR_s
},
8457 {"fx", PSR_f
| PSR_x
},
8458 {"fc", PSR_f
| PSR_c
},
8459 {"sf", PSR_s
| PSR_f
},
8460 {"sx", PSR_s
| PSR_x
},
8461 {"sc", PSR_s
| PSR_c
},
8462 {"xf", PSR_x
| PSR_f
},
8463 {"xs", PSR_x
| PSR_s
},
8464 {"xc", PSR_x
| PSR_c
},
8465 {"cf", PSR_c
| PSR_f
},
8466 {"cs", PSR_c
| PSR_s
},
8467 {"cx", PSR_c
| PSR_x
},
8468 {"fsx", PSR_f
| PSR_s
| PSR_x
},
8469 {"fsc", PSR_f
| PSR_s
| PSR_c
},
8470 {"fxs", PSR_f
| PSR_x
| PSR_s
},
8471 {"fxc", PSR_f
| PSR_x
| PSR_c
},
8472 {"fcs", PSR_f
| PSR_c
| PSR_s
},
8473 {"fcx", PSR_f
| PSR_c
| PSR_x
},
8474 {"sfx", PSR_s
| PSR_f
| PSR_x
},
8475 {"sfc", PSR_s
| PSR_f
| PSR_c
},
8476 {"sxf", PSR_s
| PSR_x
| PSR_f
},
8477 {"sxc", PSR_s
| PSR_x
| PSR_c
},
8478 {"scf", PSR_s
| PSR_c
| PSR_f
},
8479 {"scx", PSR_s
| PSR_c
| PSR_x
},
8480 {"xfs", PSR_x
| PSR_f
| PSR_s
},
8481 {"xfc", PSR_x
| PSR_f
| PSR_c
},
8482 {"xsf", PSR_x
| PSR_s
| PSR_f
},
8483 {"xsc", PSR_x
| PSR_s
| PSR_c
},
8484 {"xcf", PSR_x
| PSR_c
| PSR_f
},
8485 {"xcs", PSR_x
| PSR_c
| PSR_s
},
8486 {"cfs", PSR_c
| PSR_f
| PSR_s
},
8487 {"cfx", PSR_c
| PSR_f
| PSR_x
},
8488 {"csf", PSR_c
| PSR_s
| PSR_f
},
8489 {"csx", PSR_c
| PSR_s
| PSR_x
},
8490 {"cxf", PSR_c
| PSR_x
| PSR_f
},
8491 {"cxs", PSR_c
| PSR_x
| PSR_s
},
8492 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
8493 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
8494 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
8495 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
8496 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
8497 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
8498 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
8499 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
8500 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
8501 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
8502 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
8503 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
8504 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
8505 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
8506 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
8507 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
8508 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
8509 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
8510 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
8511 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
8512 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
8513 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
8514 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
8515 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
8518 /* Table of all shift-in-operand names. */
8519 static const struct asm_shift_name shift_names
[] =
8521 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
8522 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
8523 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
8524 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
8525 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
8526 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
8529 /* Table of all explicit relocation names. */
8531 static struct reloc_entry reloc_names
[] =
8533 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
8534 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
8535 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
8536 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
8537 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
8538 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
8539 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
8540 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
8541 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
8542 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
8543 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
8547 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
8548 static const struct asm_cond conds
[] =
8552 {"cs", 0x2}, {"hs", 0x2},
8553 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8567 /* Table of ARM-format instructions. */
8569 /* Macros for gluing together operand strings. N.B. In all cases
8570 other than OPS0, the trailing OP_stop comes from default
8571 zero-initialization of the unspecified elements of the array. */
8572 #define OPS0() { OP_stop, }
8573 #define OPS1(a) { OP_##a, }
8574 #define OPS2(a,b) { OP_##a,OP_##b, }
8575 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8576 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8577 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8578 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8580 /* These macros abstract out the exact format of the mnemonic table and
8581 save some repeated characters. */
8583 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8584 #define TxCE(mnem, op, top, nops, ops, ae, te) \
8585 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
8586 THUMB_VARIANT, do_##ae, do_##te }
8588 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8589 a T_MNEM_xyz enumerator. */
8590 #define TCE(mnem, aop, top, nops, ops, ae, te) \
8591 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8592 #define tCE(mnem, aop, top, nops, ops, ae, te) \
8593 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8595 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8596 infix after the third character. */
8597 #define TxC3(mnem, op, top, nops, ops, ae, te) \
8598 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
8599 THUMB_VARIANT, do_##ae, do_##te }
8600 #define TC3(mnem, aop, top, nops, ops, ae, te) \
8601 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8602 #define tC3(mnem, aop, top, nops, ops, ae, te) \
8603 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8605 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8606 appear in the condition table. */
8607 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8608 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8609 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
8611 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8612 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8613 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8614 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8615 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8616 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8617 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8618 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8619 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8620 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8621 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8622 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8623 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8624 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8625 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8626 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8627 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8628 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8629 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8630 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8632 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8633 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8634 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8635 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8637 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8638 field is still 0xE. */
8639 #define TUE(mnem, op, top, nops, ops, ae, te) \
8640 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8641 THUMB_VARIANT, do_##ae, do_##te }
8643 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8644 condition code field. */
8645 #define TUF(mnem, op, top, nops, ops, ae, te) \
8646 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8647 THUMB_VARIANT, do_##ae, do_##te }
8649 /* ARM-only variants of all the above. */
8650 #define CE(mnem, op, nops, ops, ae) \
8651 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8653 #define C3(mnem, op, nops, ops, ae) \
8654 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8656 /* Legacy mnemonics that always have conditional infix after the third
8658 #define CL(mnem, op, nops, ops, ae) \
8659 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8660 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8662 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
8663 #define cCE(mnem, op, nops, ops, ae) \
8664 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8666 /* Legacy coprocessor instructions where conditional infix and conditional
8667 suffix are ambiguous. For consistency this includes all FPA instructions,
8668 not just the potentially ambiguous ones. */
8669 #define cCL(mnem, op, nops, ops, ae) \
8670 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8671 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8673 /* Coprocessor, takes either a suffix or a position-3 infix
8674 (for an FPA corner case). */
8675 #define C3E(mnem, op, nops, ops, ae) \
8676 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
8677 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8679 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8680 { #m1 #m2 #m3, OPS##nops ops, \
8681 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8682 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8684 #define CM(m1, m2, op, nops, ops, ae) \
8685 xCM_(m1, , m2, op, nops, ops, ae), \
8686 xCM_(m1, eq, m2, op, nops, ops, ae), \
8687 xCM_(m1, ne, m2, op, nops, ops, ae), \
8688 xCM_(m1, cs, m2, op, nops, ops, ae), \
8689 xCM_(m1, hs, m2, op, nops, ops, ae), \
8690 xCM_(m1, cc, m2, op, nops, ops, ae), \
8691 xCM_(m1, ul, m2, op, nops, ops, ae), \
8692 xCM_(m1, lo, m2, op, nops, ops, ae), \
8693 xCM_(m1, mi, m2, op, nops, ops, ae), \
8694 xCM_(m1, pl, m2, op, nops, ops, ae), \
8695 xCM_(m1, vs, m2, op, nops, ops, ae), \
8696 xCM_(m1, vc, m2, op, nops, ops, ae), \
8697 xCM_(m1, hi, m2, op, nops, ops, ae), \
8698 xCM_(m1, ls, m2, op, nops, ops, ae), \
8699 xCM_(m1, ge, m2, op, nops, ops, ae), \
8700 xCM_(m1, lt, m2, op, nops, ops, ae), \
8701 xCM_(m1, gt, m2, op, nops, ops, ae), \
8702 xCM_(m1, le, m2, op, nops, ops, ae), \
8703 xCM_(m1, al, m2, op, nops, ops, ae)
8705 #define UE(mnem, op, nops, ops, ae) \
8706 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8708 #define UF(mnem, op, nops, ops, ae) \
8709 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8713 /* Thumb-only, unconditional. */
8714 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8716 static const struct asm_opcode insns
[] =
8718 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
8719 #define THUMB_VARIANT &arm_ext_v4t
8720 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8721 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8722 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8723 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8724 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8725 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8726 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8727 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
8728 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8729 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8730 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8731 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8732 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8733 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
8734 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8735 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
8737 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8738 for setting PSR flag bits. They are obsolete in V6 and do not
8739 have Thumb equivalents. */
8740 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8741 tC3(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8742 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
8743 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
8744 tC3(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
8745 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
8746 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8747 tC3(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8748 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
8750 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
8751 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
8752 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
8753 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
8755 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8756 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8757 tCE(str
, 4000000, str
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8758 tC3(strb
, 4400000, strb
, 2, (RR
, ADDR
), ldst
, t_ldst
),
8760 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8761 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8762 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8763 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8765 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
8766 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
8767 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
8770 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
8771 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
8772 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
8774 /* Thumb-compatibility pseudo ops. */
8775 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8776 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8777 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8778 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8779 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8780 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8781 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8782 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
8783 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
8784 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
8785 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
8786 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
8788 #undef THUMB_VARIANT
8789 #define THUMB_VARIANT &arm_ext_v6
8790 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
8792 /* V1 instructions with no Thumb analogue prior to V6T2. */
8793 #undef THUMB_VARIANT
8794 #define THUMB_VARIANT &arm_ext_v6t2
8795 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
8796 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
8797 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8798 TC3(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
8799 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
8801 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8802 TC3(ldrbt
, 4700000, f8300e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8803 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8804 TC3(strbt
, 4600000, f8200e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
8806 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8807 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8809 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8810 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
8812 /* V1 instructions with no Thumb analogue at all. */
8813 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
8814 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
8816 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
8817 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
8818 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
8819 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
8820 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
8821 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
8822 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
8823 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
8826 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
8827 #undef THUMB_VARIANT
8828 #define THUMB_VARIANT &arm_ext_v4t
8829 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
8830 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
8832 #undef THUMB_VARIANT
8833 #define THUMB_VARIANT &arm_ext_v6t2
8834 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
8835 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
8837 /* Generic coprocessor instructions. */
8838 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
8839 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8840 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8841 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8842 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8843 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8844 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8847 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
8848 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
8849 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
8852 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
8853 TCE(mrs
, 10f0000
, f3ef8000
, 2, (RR
, PSR
), mrs
, t_mrs
),
8854 TCE(msr
, 120f000
, f3808000
, 2, (PSR
, RR_EXi
), msr
, t_msr
),
8857 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
8858 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8859 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8860 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8861 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8862 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8863 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8864 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
8865 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
8868 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
8869 #undef THUMB_VARIANT
8870 #define THUMB_VARIANT &arm_ext_v4t
8871 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8872 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8873 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8874 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8875 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8876 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDR
), ldstv4
, t_ldst
),
8879 #define ARM_VARIANT &arm_ext_v4t_5
8880 /* ARM Architecture 4T. */
8881 /* Note: bx (and blx) are required on V5, even if the processor does
8882 not support Thumb. */
8883 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
8886 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
8887 #undef THUMB_VARIANT
8888 #define THUMB_VARIANT &arm_ext_v5t
8889 /* Note: blx has 2 variants; the .value coded here is for
8890 BLX(2). Only this variant has conditional execution. */
8891 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
8892 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
8894 #undef THUMB_VARIANT
8895 #define THUMB_VARIANT &arm_ext_v6t2
8896 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
8897 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8898 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8899 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8900 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDR
), lstc
, lstc
),
8901 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
8902 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8903 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
8906 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
8907 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8908 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8909 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8910 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8912 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8913 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
8915 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8916 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8917 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8918 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
8920 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8921 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8922 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8923 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8925 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8926 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
8928 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8929 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8930 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8931 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
8934 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
8935 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
8936 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDR
), ldrd
, t_ldstd
),
8937 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDR
), ldrd
, t_ldstd
),
8939 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8940 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8943 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
8944 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
8947 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
8948 #undef THUMB_VARIANT
8949 #define THUMB_VARIANT &arm_ext_v6
8950 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
8951 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
8952 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
8953 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
8954 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
8955 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8956 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8957 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8958 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
8959 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
8961 #undef THUMB_VARIANT
8962 #define THUMB_VARIANT &arm_ext_v6t2
8963 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, imm0
),
8964 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
8965 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8966 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
8967 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
8968 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
8969 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8970 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8971 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8972 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8973 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8974 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8975 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8976 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8977 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8978 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8979 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8980 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8981 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8982 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8983 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8984 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8985 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8986 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8987 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8988 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8989 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8990 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8991 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8992 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8993 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8994 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8995 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8996 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8997 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8998 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
8999 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9000 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9001 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9002 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9003 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9004 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9005 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
9006 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
9007 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
9008 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
9009 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
9010 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
9011 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
9012 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
9013 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9014 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9015 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9016 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
9017 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9018 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9019 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
9020 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
9021 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
9022 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9023 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9024 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
9025 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
9026 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9027 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9028 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
9029 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
9030 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9031 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9032 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9033 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9034 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9035 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9036 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9037 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9038 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9039 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9040 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
9041 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
9042 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
9043 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
9044 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
9045 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
9046 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
9047 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
9048 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
9049 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
9050 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
9051 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
9054 #define ARM_VARIANT &arm_ext_v6k
9055 #undef THUMB_VARIANT
9056 #define THUMB_VARIANT &arm_ext_v6k
9057 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
9058 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
9059 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
9060 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
9062 #undef THUMB_VARIANT
9063 #define THUMB_VARIANT &arm_ext_v6t2
9064 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
9065 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
9066 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
9067 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
9068 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
9069 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
9070 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
9073 #define ARM_VARIANT &arm_ext_v6z
9074 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
9077 #define ARM_VARIANT &arm_ext_v6t2
9078 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
9079 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
9080 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
9081 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
9083 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
9084 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, Iffff
), mov16
, t_mov16
),
9085 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, Iffff
), mov16
, t_mov16
),
9086 TCE(rbit
, 3ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
9088 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
9089 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
9090 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
9091 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
9093 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
9094 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
9095 /* ARM does not really have an IT instruction. */
9096 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
9097 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
9098 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
9099 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
9100 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
9101 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
9102 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
9103 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
9104 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
9105 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
9106 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
9107 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
9108 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
9109 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
9110 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
9112 /* Thumb2 only instructions. */
9114 #define ARM_VARIANT NULL
9116 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
9117 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
9118 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
9119 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
9122 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
9123 cCE(wfs
, e200110
, 1, (RR
), rd
),
9124 cCE(rfs
, e300110
, 1, (RR
), rd
),
9125 cCE(wfc
, e400110
, 1, (RR
), rd
),
9126 cCE(rfc
, e500110
, 1, (RR
), rd
),
9128 cCL(ldfs
, c100100
, 2, (RF
, ADDR
), rd_cpaddr
),
9129 cCL(ldfd
, c108100
, 2, (RF
, ADDR
), rd_cpaddr
),
9130 cCL(ldfe
, c500100
, 2, (RF
, ADDR
), rd_cpaddr
),
9131 cCL(ldfp
, c508100
, 2, (RF
, ADDR
), rd_cpaddr
),
9133 cCL(stfs
, c000100
, 2, (RF
, ADDR
), rd_cpaddr
),
9134 cCL(stfd
, c008100
, 2, (RF
, ADDR
), rd_cpaddr
),
9135 cCL(stfe
, c400100
, 2, (RF
, ADDR
), rd_cpaddr
),
9136 cCL(stfp
, c408100
, 2, (RF
, ADDR
), rd_cpaddr
),
9138 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
9139 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
9140 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
9141 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
9142 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
9143 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
9144 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
9145 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
9146 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
9147 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
9148 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
9149 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
9151 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
9152 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
9153 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
9154 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
9155 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
9156 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
9157 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
9158 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
9159 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
9160 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
9161 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
9162 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
9164 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
9165 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
9166 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
9167 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
9168 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
9169 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
9170 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
9171 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
9172 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
9173 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
9174 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
9175 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
9177 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
9178 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
9179 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
9180 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
9181 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
9182 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
9183 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
9184 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
9185 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
9186 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
9187 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
9188 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
9190 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
9191 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
9192 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
9193 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
9194 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
9195 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
9196 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
9197 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
9198 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
9199 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
9200 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
9201 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
9203 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
9204 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
9205 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
9206 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
9207 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
9208 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
9209 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
9210 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
9211 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
9212 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
9213 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
9214 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
9216 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
9217 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
9218 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
9219 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
9220 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
9221 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
9222 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
9223 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
9224 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
9225 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
9226 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
9227 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
9229 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
9230 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
9231 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
9232 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
9233 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
9234 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
9235 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
9236 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
9237 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
9238 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
9239 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
9240 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
9242 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
9243 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
9244 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
9245 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
9246 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
9247 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
9248 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
9249 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
9250 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
9251 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
9252 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
9253 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
9255 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
9256 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
9257 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
9258 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
9259 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
9260 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
9261 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
9262 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
9263 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
9264 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
9265 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
9266 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
9268 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
9269 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
9270 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
9271 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
9272 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
9273 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
9274 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
9275 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
9276 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
9277 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
9278 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
9279 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
9281 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
9282 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
9283 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
9284 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
9285 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
9286 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
9287 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
9288 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
9289 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
9290 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
9291 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
9292 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
9294 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
9295 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
9296 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
9297 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
9298 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
9299 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
9300 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
9301 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
9302 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
9303 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
9304 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
9305 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
9307 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
9308 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
9309 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
9310 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
9311 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
9312 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
9313 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
9314 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
9315 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
9316 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
9317 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
9318 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
9320 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
9321 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
9322 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
9323 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
9324 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
9325 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
9326 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
9327 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
9328 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
9329 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
9330 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
9331 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
9333 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
9334 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
9335 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
9336 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
9337 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
9338 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
9339 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
9340 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
9341 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
9342 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
9343 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
9344 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
9346 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9347 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9348 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9349 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9350 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9351 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9352 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9353 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9354 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9355 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9356 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9357 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9359 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9360 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9361 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9362 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9363 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9364 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9365 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9366 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9367 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9368 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9369 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9370 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9372 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9373 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9374 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9375 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9376 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9377 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9378 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9379 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9380 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9381 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9382 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9383 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9385 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9386 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9387 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9388 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9389 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9390 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9391 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9392 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9393 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9394 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9395 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9396 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9398 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9399 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9400 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9401 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9402 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9403 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9404 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9405 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9406 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9407 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9408 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9409 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9411 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9412 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9413 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9414 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9415 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9416 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9417 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9418 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9419 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9420 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9421 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9422 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9424 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9425 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9426 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9427 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9428 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9429 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9430 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9431 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9432 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9433 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9434 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9435 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9437 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9438 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9439 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9440 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9441 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9442 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9443 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9444 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9445 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9446 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9447 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9448 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9450 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9451 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9452 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9453 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9454 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9455 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9456 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9457 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9458 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9459 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9460 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9461 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9463 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9464 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9465 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9466 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9467 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9468 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9469 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9470 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9471 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9472 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9473 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9474 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9476 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9477 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9478 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9479 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9480 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9481 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9482 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9483 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9484 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9485 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9486 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9487 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9489 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9490 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9491 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9492 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9493 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9494 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9495 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9496 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9497 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9498 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9499 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9500 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9502 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9503 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9504 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9505 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9506 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9507 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9508 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9509 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9510 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9511 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9512 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9513 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
9515 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9516 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9517 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9518 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
9520 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
9521 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
9522 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
9523 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
9524 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
9525 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
9526 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
9527 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
9528 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
9529 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
9530 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
9531 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
9533 /* The implementation of the FIX instruction is broken on some
9534 assemblers, in that it accepts a precision specifier as well as a
9535 rounding specifier, despite the fact that this is meaningless.
9536 To be more compatible, we accept it as well, though of course it
9537 does not set any bits. */
9538 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
9539 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
9540 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
9541 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
9542 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
9543 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
9544 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
9545 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
9546 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
9547 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
9548 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
9549 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
9550 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
9552 /* Instructions that were new with the real FPA, call them V2. */
9554 #define ARM_VARIANT &fpu_fpa_ext_v2
9555 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9556 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9557 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9558 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9559 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9560 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
9563 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
9564 /* Moves and type conversions. */
9565 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9566 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
9567 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
9568 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
9569 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9570 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9571 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9572 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9573 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9574 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9575 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
9576 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
9578 /* Memory operations. */
9579 cCE(flds
, d100a00
, 2, (RVS
, ADDR
), vfp_sp_ldst
),
9580 cCE(fsts
, d000a00
, 2, (RVS
, ADDR
), vfp_sp_ldst
),
9581 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9582 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9583 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9584 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9585 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9586 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9587 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9588 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9589 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9590 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
9591 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9592 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
9593 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9594 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
9595 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9596 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
9598 /* Monadic operations. */
9599 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9600 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9601 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9603 /* Dyadic operations. */
9604 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9605 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9606 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9607 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9608 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9609 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9610 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9611 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9612 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
9615 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9616 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
9617 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
9618 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
9621 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
9622 /* Moves and type conversions. */
9623 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), rd_rm
),
9624 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
9625 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9626 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), rn_rd
),
9627 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), rn_rd
),
9628 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), rd_rn
),
9629 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), rd_rn
),
9630 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
9631 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
9632 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9633 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9634 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9635 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
9637 /* Memory operations. */
9638 cCE(fldd
, d100b00
, 2, (RVD
, ADDR
), vfp_dp_ldst
),
9639 cCE(fstd
, d000b00
, 2, (RVD
, ADDR
), vfp_dp_ldst
),
9640 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9641 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9642 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9643 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9644 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9645 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
9646 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9647 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
9649 /* Monadic operations. */
9650 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), rd_rm
),
9651 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), rd_rm
),
9652 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), rd_rm
),
9654 /* Dyadic operations. */
9655 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9656 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9657 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9658 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9659 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9660 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9661 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9662 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9663 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), rd_rn_rm
),
9666 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), rd_rm
),
9667 cCE(fcmpzd
, eb50b40
, 1, (RVD
), rd
),
9668 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), rd_rm
),
9669 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), rd
),
9672 #define ARM_VARIANT &fpu_vfp_ext_v2
9673 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
9674 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
9675 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), rm_rd_rn
),
9676 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), rd_rn_rm
),
9679 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
9680 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9681 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9682 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9683 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9684 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9685 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
9686 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
9687 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
9690 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
9691 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
9692 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
9693 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
9694 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
9695 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
9696 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
9697 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
9698 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
9699 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
9700 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9701 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9702 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9703 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9704 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9705 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
9706 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9707 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9708 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
9709 cCE(tmcr
, e000110
, 2, (RIWC
, RR
), rn_rd
),
9710 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
9711 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9712 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9713 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9714 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9715 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9716 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
9717 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
9718 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
9719 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
9720 cCE(tmrc
, e100110
, 2, (RR
, RIWC
), rd_rn
),
9721 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
9722 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
9723 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
9724 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
9725 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9726 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9727 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
9728 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9729 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9730 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9731 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9732 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9733 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9734 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9735 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9736 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9737 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
9738 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9739 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9740 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9741 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9742 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9743 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9744 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9745 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9746 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9747 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9748 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9749 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9750 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9751 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9752 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9753 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9754 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9755 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9756 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9757 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9758 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9759 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
9760 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
9761 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9762 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9763 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9764 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9765 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9766 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9767 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9768 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9769 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9770 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9771 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9772 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9773 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9774 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9775 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9776 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9777 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9778 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9779 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
9780 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9781 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9782 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9783 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9784 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9785 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9786 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9787 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9788 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9789 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9790 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9791 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9792 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9793 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9794 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9795 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9796 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9797 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9798 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9799 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9800 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9801 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
9802 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9803 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9804 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9805 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9806 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9807 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9808 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9809 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9810 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9811 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9812 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9813 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9814 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9815 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9816 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9817 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9818 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9819 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
9820 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9821 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
9822 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
9823 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
9824 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9825 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9826 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9827 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9828 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9829 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9830 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9831 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9832 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9833 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9834 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9835 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9836 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9837 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9838 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
9839 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9840 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9841 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9842 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9843 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9844 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9845 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9846 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9847 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
9848 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9849 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9850 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9851 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
9852 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
9855 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
9856 cCE(cfldrs
, c100400
, 2, (RMF
, ADDR
), rd_cpaddr
),
9857 cCE(cfldrd
, c500400
, 2, (RMD
, ADDR
), rd_cpaddr
),
9858 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDR
), rd_cpaddr
),
9859 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDR
), rd_cpaddr
),
9860 cCE(cfstrs
, c000400
, 2, (RMF
, ADDR
), rd_cpaddr
),
9861 cCE(cfstrd
, c400400
, 2, (RMD
, ADDR
), rd_cpaddr
),
9862 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDR
), rd_cpaddr
),
9863 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDR
), rd_cpaddr
),
9864 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
9865 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
9866 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
9867 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
9868 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
9869 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
9870 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
9871 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
9872 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
9873 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
9874 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
9875 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
9876 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
9877 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
9878 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
9879 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
9880 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
9881 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
9882 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
9883 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
9884 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
9885 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
9886 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
9887 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
9888 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
9889 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
9890 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
9891 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
9892 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
9893 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
9894 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
9895 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
9896 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
9897 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
9898 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
9899 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
9900 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
9901 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
9902 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
9903 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
9904 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
9905 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
9906 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
9907 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
9908 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
9909 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
9910 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
9911 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
9912 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
9913 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
9914 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
9915 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
9916 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
9917 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
9918 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
9919 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
9920 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9921 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
9922 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9923 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
9924 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9925 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
9926 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9927 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
9928 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
9929 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
9930 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
9931 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
9934 #undef THUMB_VARIANT
9957 /* MD interface: bits in the object file. */
9959 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9960 for use in the a.out file, and stores them in the array pointed to by buf.
9961 This knows about the endian-ness of the target machine and does
9962 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9963 2 (short) and 4 (long) Floating numbers are put out as a series of
9964 LITTLENUMS (shorts, here at least). */
9967 md_number_to_chars (char * buf
, valueT val
, int n
)
9969 if (target_big_endian
)
9970 number_to_chars_bigendian (buf
, val
, n
);
9972 number_to_chars_littleendian (buf
, val
, n
);
9976 md_chars_to_number (char * buf
, int n
)
9979 unsigned char * where
= (unsigned char *) buf
;
9981 if (target_big_endian
)
9986 result
|= (*where
++ & 255);
9994 result
|= (where
[n
] & 255);
10001 /* MD interface: Sections. */
10003 /* Estimate the size of a frag before relaxing. Assume everything fits in
10007 md_estimate_size_before_relax (fragS
* fragp
,
10008 segT segtype ATTRIBUTE_UNUSED
)
10014 /* Convert a machine dependent frag. */
10017 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
10019 unsigned long insn
;
10020 unsigned long old_op
;
10028 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10030 old_op
= bfd_get_16(abfd
, buf
);
10031 if (fragp
->fr_symbol
) {
10032 exp
.X_op
= O_symbol
;
10033 exp
.X_add_symbol
= fragp
->fr_symbol
;
10035 exp
.X_op
= O_constant
;
10037 exp
.X_add_number
= fragp
->fr_offset
;
10038 opcode
= fragp
->fr_subtype
;
10041 case T_MNEM_ldr_pc
:
10042 case T_MNEM_ldr_pc2
:
10043 case T_MNEM_ldr_sp
:
10044 case T_MNEM_str_sp
:
10051 if (fragp
->fr_var
== 4)
10053 insn
= THUMB_OP32(opcode
);
10054 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
10056 insn
|= (old_op
& 0x700) << 4;
10060 insn
|= (old_op
& 7) << 12;
10061 insn
|= (old_op
& 0x38) << 13;
10063 insn
|= 0x00000c00;
10064 put_thumb32_insn (buf
, insn
);
10065 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10069 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10071 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
10074 if (fragp
->fr_var
== 4)
10076 insn
= THUMB_OP32 (opcode
);
10077 insn
|= (old_op
& 0xf0) << 4;
10078 put_thumb32_insn (buf
, insn
);
10079 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10083 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
10084 exp
.X_add_number
-= 4;
10092 if (fragp
->fr_var
== 4)
10094 int r0off
= (opcode
== T_MNEM_mov
10095 || opcode
== T_MNEM_movs
) ? 0 : 8;
10096 insn
= THUMB_OP32 (opcode
);
10097 insn
= (insn
& 0xe1ffffff) | 0x10000000;
10098 insn
|= (old_op
& 0x700) << r0off
;
10099 put_thumb32_insn (buf
, insn
);
10100 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10104 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
10109 if (fragp
->fr_var
== 4)
10111 insn
= THUMB_OP32(opcode
);
10112 put_thumb32_insn (buf
, insn
);
10113 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10116 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10120 if (fragp
->fr_var
== 4)
10122 insn
= THUMB_OP32(opcode
);
10123 insn
|= (old_op
& 0xf00) << 14;
10124 put_thumb32_insn (buf
, insn
);
10125 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10128 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10131 case T_MNEM_add_sp
:
10132 case T_MNEM_add_pc
:
10133 case T_MNEM_inc_sp
:
10134 case T_MNEM_dec_sp
:
10135 if (fragp
->fr_var
== 4)
10137 /* ??? Choose between add and addw. */
10138 insn
= THUMB_OP32 (opcode
);
10139 insn
|= (old_op
& 0xf0) << 4;
10140 put_thumb32_insn (buf
, insn
);
10141 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10144 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
10152 if (fragp
->fr_var
== 4)
10154 insn
= THUMB_OP32 (opcode
);
10155 insn
|= (old_op
& 0xf0) << 4;
10156 insn
|= (old_op
& 0xf) << 16;
10157 put_thumb32_insn (buf
, insn
);
10158 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10161 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
10167 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
10169 fixp
->fx_file
= fragp
->fr_file
;
10170 fixp
->fx_line
= fragp
->fr_line
;
10171 fragp
->fr_fix
+= fragp
->fr_var
;
10174 /* Return the size of a relaxable immediate operand instruction.
10175 SHIFT and SIZE specify the form of the allowable immediate. */
10177 relax_immediate (fragS
*fragp
, int size
, int shift
)
10183 /* ??? Should be able to do better than this. */
10184 if (fragp
->fr_symbol
)
10187 low
= (1 << shift
) - 1;
10188 mask
= (1 << (shift
+ size
)) - (1 << shift
);
10189 offset
= fragp
->fr_offset
;
10190 /* Force misaligned offsets to 32-bit variant. */
10193 if (offset
& ~mask
)
10198 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
10201 relax_adr (fragS
*fragp
, asection
*sec
)
10206 /* Assume worst case for symbols not known to be in the same section. */
10207 if (!S_IS_DEFINED(fragp
->fr_symbol
)
10208 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
10211 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
10212 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10213 addr
= (addr
+ 4) & ~3;
10214 /* Fix the insn as the 4-byte version if the target address is not
10215 sufficiently aligned. This is prevents an infinite loop when two
10216 instructions have contradictory range/alignment requirements. */
10220 if (val
< 0 || val
> 1020)
10225 /* Return the size of a relaxable add/sub immediate instruction. */
10227 relax_addsub (fragS
*fragp
, asection
*sec
)
10232 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10233 op
= bfd_get_16(sec
->owner
, buf
);
10234 if ((op
& 0xf) == ((op
>> 4) & 0xf))
10235 return relax_immediate (fragp
, 8, 0);
10237 return relax_immediate (fragp
, 3, 0);
10241 /* Return the size of a relaxable branch instruction. BITS is the
10242 size of the offset field in the narrow instruction. */
10245 relax_branch (fragS
*fragp
, asection
*sec
, int bits
)
10251 /* Assume worst case for symbols not known to be in the same section. */
10252 if (!S_IS_DEFINED(fragp
->fr_symbol
)
10253 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
10256 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
10257 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
10260 /* Offset is a signed value *2 */
10262 if (val
>= limit
|| val
< -limit
)
10268 /* Relax a machine dependent frag. This returns the amount by which
10269 the current size of the frag should change. */
10272 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
10277 oldsize
= fragp
->fr_var
;
10278 switch (fragp
->fr_subtype
)
10280 case T_MNEM_ldr_pc2
:
10281 newsize
= relax_adr(fragp
, sec
);
10283 case T_MNEM_ldr_pc
:
10284 case T_MNEM_ldr_sp
:
10285 case T_MNEM_str_sp
:
10286 newsize
= relax_immediate(fragp
, 8, 2);
10290 newsize
= relax_immediate(fragp
, 5, 2);
10294 newsize
= relax_immediate(fragp
, 5, 1);
10298 newsize
= relax_immediate(fragp
, 5, 0);
10301 newsize
= relax_adr(fragp
, sec
);
10307 newsize
= relax_immediate(fragp
, 8, 0);
10310 newsize
= relax_branch(fragp
, sec
, 11);
10313 newsize
= relax_branch(fragp
, sec
, 8);
10315 case T_MNEM_add_sp
:
10316 case T_MNEM_add_pc
:
10317 newsize
= relax_immediate (fragp
, 8, 2);
10319 case T_MNEM_inc_sp
:
10320 case T_MNEM_dec_sp
:
10321 newsize
= relax_immediate (fragp
, 7, 2);
10327 newsize
= relax_addsub (fragp
, sec
);
10334 fragp
->fr_var
= -newsize
;
10335 md_convert_frag (sec
->owner
, sec
, fragp
);
10337 return -(newsize
+ oldsize
);
10339 fragp
->fr_var
= newsize
;
10340 return newsize
- oldsize
;
10343 /* Round up a section size to the appropriate boundary. */
10346 md_section_align (segT segment ATTRIBUTE_UNUSED
,
10352 /* Round all sects to multiple of 4. */
10353 return (size
+ 3) & ~3;
10357 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10358 of an rs_align_code fragment. */
10361 arm_handle_align (fragS
* fragP
)
10363 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
10364 static char const thumb_noop
[2] = { 0xc0, 0x46 };
10365 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
10366 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
10368 int bytes
, fix
, noop_size
;
10372 if (fragP
->fr_type
!= rs_align_code
)
10375 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
10376 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
10379 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
10380 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
10382 if (fragP
->tc_frag_data
)
10384 if (target_big_endian
)
10385 noop
= thumb_bigend_noop
;
10388 noop_size
= sizeof (thumb_noop
);
10392 if (target_big_endian
)
10393 noop
= arm_bigend_noop
;
10396 noop_size
= sizeof (arm_noop
);
10399 if (bytes
& (noop_size
- 1))
10401 fix
= bytes
& (noop_size
- 1);
10402 memset (p
, 0, fix
);
10407 while (bytes
>= noop_size
)
10409 memcpy (p
, noop
, noop_size
);
10411 bytes
-= noop_size
;
10415 fragP
->fr_fix
+= fix
;
10416 fragP
->fr_var
= noop_size
;
10419 /* Called from md_do_align. Used to create an alignment
10420 frag in a code section. */
10423 arm_frag_align_code (int n
, int max
)
10427 /* We assume that there will never be a requirement
10428 to support alignments greater than 32 bytes. */
10429 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
10430 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
10432 p
= frag_var (rs_align_code
,
10433 MAX_MEM_FOR_RS_ALIGN_CODE
,
10435 (relax_substateT
) max
,
10442 /* Perform target specific initialisation of a frag. */
10445 arm_init_frag (fragS
* fragP
)
10447 /* Record whether this frag is in an ARM or a THUMB area. */
10448 fragP
->tc_frag_data
= thumb_mode
;
10452 /* When we change sections we need to issue a new mapping symbol. */
10455 arm_elf_change_section (void)
10458 segment_info_type
*seginfo
;
10460 /* Link an unlinked unwind index table section to the .text section. */
10461 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
10462 && elf_linked_to_section (now_seg
) == NULL
)
10463 elf_linked_to_section (now_seg
) = text_section
;
10465 if (!SEG_NORMAL (now_seg
))
10468 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
10470 /* We can ignore sections that only contain debug info. */
10471 if ((flags
& SEC_ALLOC
) == 0)
10474 seginfo
= seg_info (now_seg
);
10475 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
10476 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
10480 arm_elf_section_type (const char * str
, size_t len
)
10482 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
10483 return SHT_ARM_EXIDX
;
10488 /* Code to deal with unwinding tables. */
10490 static void add_unwind_adjustsp (offsetT
);
10492 /* Cenerate and deferred unwind frame offset. */
10495 flush_pending_unwind (void)
10499 offset
= unwind
.pending_offset
;
10500 unwind
.pending_offset
= 0;
10502 add_unwind_adjustsp (offset
);
10505 /* Add an opcode to this list for this function. Two-byte opcodes should
10506 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
10510 add_unwind_opcode (valueT op
, int length
)
10512 /* Add any deferred stack adjustment. */
10513 if (unwind
.pending_offset
)
10514 flush_pending_unwind ();
10516 unwind
.sp_restored
= 0;
10518 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
10520 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
10521 if (unwind
.opcodes
)
10522 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
10523 unwind
.opcode_alloc
);
10525 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
10530 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
10532 unwind
.opcode_count
++;
10536 /* Add unwind opcodes to adjust the stack pointer. */
10539 add_unwind_adjustsp (offsetT offset
)
10543 if (offset
> 0x200)
10545 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
10550 /* Long form: 0xb2, uleb128. */
10551 /* This might not fit in a word so add the individual bytes,
10552 remembering the list is built in reverse order. */
10553 o
= (valueT
) ((offset
- 0x204) >> 2);
10555 add_unwind_opcode (0, 1);
10557 /* Calculate the uleb128 encoding of the offset. */
10561 bytes
[n
] = o
& 0x7f;
10567 /* Add the insn. */
10569 add_unwind_opcode (bytes
[n
- 1], 1);
10570 add_unwind_opcode (0xb2, 1);
10572 else if (offset
> 0x100)
10574 /* Two short opcodes. */
10575 add_unwind_opcode (0x3f, 1);
10576 op
= (offset
- 0x104) >> 2;
10577 add_unwind_opcode (op
, 1);
10579 else if (offset
> 0)
10581 /* Short opcode. */
10582 op
= (offset
- 4) >> 2;
10583 add_unwind_opcode (op
, 1);
10585 else if (offset
< 0)
10588 while (offset
> 0x100)
10590 add_unwind_opcode (0x7f, 1);
10593 op
= ((offset
- 4) >> 2) | 0x40;
10594 add_unwind_opcode (op
, 1);
10598 /* Finish the list of unwind opcodes for this function. */
10600 finish_unwind_opcodes (void)
10604 if (unwind
.fp_used
)
10606 /* Adjust sp as neccessary. */
10607 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
10608 flush_pending_unwind ();
10610 /* After restoring sp from the frame pointer. */
10611 op
= 0x90 | unwind
.fp_reg
;
10612 add_unwind_opcode (op
, 1);
10615 flush_pending_unwind ();
10619 /* Start an exception table entry. If idx is nonzero this is an index table
10623 start_unwind_section (const segT text_seg
, int idx
)
10625 const char * text_name
;
10626 const char * prefix
;
10627 const char * prefix_once
;
10628 const char * group_name
;
10632 size_t sec_name_len
;
10639 prefix
= ELF_STRING_ARM_unwind
;
10640 prefix_once
= ELF_STRING_ARM_unwind_once
;
10641 type
= SHT_ARM_EXIDX
;
10645 prefix
= ELF_STRING_ARM_unwind_info
;
10646 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
10647 type
= SHT_PROGBITS
;
10650 text_name
= segment_name (text_seg
);
10651 if (streq (text_name
, ".text"))
10654 if (strncmp (text_name
, ".gnu.linkonce.t.",
10655 strlen (".gnu.linkonce.t.")) == 0)
10657 prefix
= prefix_once
;
10658 text_name
+= strlen (".gnu.linkonce.t.");
10661 prefix_len
= strlen (prefix
);
10662 text_len
= strlen (text_name
);
10663 sec_name_len
= prefix_len
+ text_len
;
10664 sec_name
= xmalloc (sec_name_len
+ 1);
10665 memcpy (sec_name
, prefix
, prefix_len
);
10666 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
10667 sec_name
[prefix_len
+ text_len
] = '\0';
10673 /* Handle COMDAT group. */
10674 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
10676 group_name
= elf_group_name (text_seg
);
10677 if (group_name
== NULL
)
10679 as_bad ("Group section `%s' has no group signature",
10680 segment_name (text_seg
));
10681 ignore_rest_of_line ();
10684 flags
|= SHF_GROUP
;
10688 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
10690 /* Set the setion link for index tables. */
10692 elf_linked_to_section (now_seg
) = text_seg
;
10696 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
10697 personality routine data. Returns zero, or the index table value for
10698 and inline entry. */
10701 create_unwind_entry (int have_data
)
10706 /* The current word of data. */
10708 /* The number of bytes left in this word. */
10711 finish_unwind_opcodes ();
10713 /* Remember the current text section. */
10714 unwind
.saved_seg
= now_seg
;
10715 unwind
.saved_subseg
= now_subseg
;
10717 start_unwind_section (now_seg
, 0);
10719 if (unwind
.personality_routine
== NULL
)
10721 if (unwind
.personality_index
== -2)
10724 as_bad (_("handerdata in cantunwind frame"));
10725 return 1; /* EXIDX_CANTUNWIND. */
10728 /* Use a default personality routine if none is specified. */
10729 if (unwind
.personality_index
== -1)
10731 if (unwind
.opcode_count
> 3)
10732 unwind
.personality_index
= 1;
10734 unwind
.personality_index
= 0;
10737 /* Space for the personality routine entry. */
10738 if (unwind
.personality_index
== 0)
10740 if (unwind
.opcode_count
> 3)
10741 as_bad (_("too many unwind opcodes for personality routine 0"));
10745 /* All the data is inline in the index table. */
10748 while (unwind
.opcode_count
> 0)
10750 unwind
.opcode_count
--;
10751 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
10755 /* Pad with "finish" opcodes. */
10757 data
= (data
<< 8) | 0xb0;
10764 /* We get two opcodes "free" in the first word. */
10765 size
= unwind
.opcode_count
- 2;
10768 /* An extra byte is required for the opcode count. */
10769 size
= unwind
.opcode_count
+ 1;
10771 size
= (size
+ 3) >> 2;
10773 as_bad (_("too many unwind opcodes"));
10775 frag_align (2, 0, 0);
10776 record_alignment (now_seg
, 2);
10777 unwind
.table_entry
= expr_build_dot ();
10779 /* Allocate the table entry. */
10780 ptr
= frag_more ((size
<< 2) + 4);
10781 where
= frag_now_fix () - ((size
<< 2) + 4);
10783 switch (unwind
.personality_index
)
10786 /* ??? Should this be a PLT generating relocation? */
10787 /* Custom personality routine. */
10788 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
10789 BFD_RELOC_ARM_PREL31
);
10794 /* Set the first byte to the number of additional words. */
10799 /* ABI defined personality routines. */
10801 /* Three opcodes bytes are packed into the first word. */
10808 /* The size and first two opcode bytes go in the first word. */
10809 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
10814 /* Should never happen. */
10818 /* Pack the opcodes into words (MSB first), reversing the list at the same
10820 while (unwind
.opcode_count
> 0)
10824 md_number_to_chars (ptr
, data
, 4);
10829 unwind
.opcode_count
--;
10831 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
10834 /* Finish off the last word. */
10837 /* Pad with "finish" opcodes. */
10839 data
= (data
<< 8) | 0xb0;
10841 md_number_to_chars (ptr
, data
, 4);
10846 /* Add an empty descriptor if there is no user-specified data. */
10847 ptr
= frag_more (4);
10848 md_number_to_chars (ptr
, 0, 4);
10854 /* Convert REGNAME to a DWARF-2 register number. */
10857 tc_arm_regname_to_dw2regnum (const char *regname
)
10859 int reg
= arm_reg_parse ((char **) ®name
, REG_TYPE_RN
);
10867 /* Initialize the DWARF-2 unwind information for this procedure. */
10870 tc_arm_frame_initial_instructions (void)
10872 cfi_add_CFA_def_cfa (REG_SP
, 0);
10874 #endif /* OBJ_ELF */
10877 /* MD interface: Symbol and relocation handling. */
10879 /* Return the address within the segment that a PC-relative fixup is
10880 relative to. For ARM, PC-relative fixups applied to instructions
10881 are generally relative to the location of the fixup plus 8 bytes.
10882 Thumb branches are offset by 4, and Thumb loads relative to PC
10883 require special handling. */
10886 md_pcrel_from_section (fixS
* fixP
, segT seg
)
10888 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10890 /* If this is pc-relative and we are going to emit a relocation
10891 then we just want to put out any pipeline compensation that the linker
10892 will need. Otherwise we want to use the calculated base. */
10894 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10895 || arm_force_relocation (fixP
)))
10898 switch (fixP
->fx_r_type
)
10900 /* PC relative addressing on the Thumb is slightly odd as the
10901 bottom two bits of the PC are forced to zero for the
10902 calculation. This happens *after* application of the
10903 pipeline offset. However, Thumb adrl already adjusts for
10904 this, so we need not do it again. */
10905 case BFD_RELOC_ARM_THUMB_ADD
:
10908 case BFD_RELOC_ARM_THUMB_OFFSET
:
10909 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
10910 case BFD_RELOC_ARM_T32_ADD_PC12
:
10911 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
10912 return (base
+ 4) & ~3;
10914 /* Thumb branches are simply offset by +4. */
10915 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
10916 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
10917 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
10918 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
10919 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
10920 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
10921 case BFD_RELOC_THUMB_PCREL_BLX
:
10924 /* ARM mode branches are offset by +8. However, the Windows CE
10925 loader expects the relocation not to take this into account. */
10926 case BFD_RELOC_ARM_PCREL_BRANCH
:
10927 case BFD_RELOC_ARM_PCREL_CALL
:
10928 case BFD_RELOC_ARM_PCREL_JUMP
:
10929 case BFD_RELOC_ARM_PCREL_BLX
:
10930 case BFD_RELOC_ARM_PLT32
:
10937 /* ARM mode loads relative to PC are also offset by +8. Unlike
10938 branches, the Windows CE loader *does* expect the relocation
10939 to take this into account. */
10940 case BFD_RELOC_ARM_OFFSET_IMM
:
10941 case BFD_RELOC_ARM_OFFSET_IMM8
:
10942 case BFD_RELOC_ARM_HWLITERAL
:
10943 case BFD_RELOC_ARM_LITERAL
:
10944 case BFD_RELOC_ARM_CP_OFF_IMM
:
10948 /* Other PC-relative relocations are un-offset. */
10954 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
10955 Otherwise we have no need to default values of symbols. */
10958 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
10961 if (name
[0] == '_' && name
[1] == 'G'
10962 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
10966 if (symbol_find (name
))
10967 as_bad ("GOT already in the symbol table");
10969 GOT_symbol
= symbol_new (name
, undefined_section
,
10970 (valueT
) 0, & zero_address_frag
);
10980 /* Subroutine of md_apply_fix. Check to see if an immediate can be
10981 computed as two separate immediate values, added together. We
10982 already know that this value cannot be computed by just one ARM
10985 static unsigned int
10986 validate_immediate_twopart (unsigned int val
,
10987 unsigned int * highpart
)
10992 for (i
= 0; i
< 32; i
+= 2)
10993 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
10999 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
11001 else if (a
& 0xff0000)
11003 if (a
& 0xff000000)
11005 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
11009 assert (a
& 0xff000000);
11010 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
11013 return (a
& 0xff) | (i
<< 7);
11020 validate_offset_imm (unsigned int val
, int hwse
)
11022 if ((hwse
&& val
> 255) || val
> 4095)
11027 /* Subroutine of md_apply_fix. Do those data_ops which can take a
11028 negative immediate constant by altering the instruction. A bit of
11033 by inverting the second operand, and
11036 by negating the second operand. */
11039 negate_data_op (unsigned long * instruction
,
11040 unsigned long value
)
11043 unsigned long negated
, inverted
;
11045 negated
= encode_arm_immediate (-value
);
11046 inverted
= encode_arm_immediate (~value
);
11048 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
11051 /* First negates. */
11052 case OPCODE_SUB
: /* ADD <-> SUB */
11053 new_inst
= OPCODE_ADD
;
11058 new_inst
= OPCODE_SUB
;
11062 case OPCODE_CMP
: /* CMP <-> CMN */
11063 new_inst
= OPCODE_CMN
;
11068 new_inst
= OPCODE_CMP
;
11072 /* Now Inverted ops. */
11073 case OPCODE_MOV
: /* MOV <-> MVN */
11074 new_inst
= OPCODE_MVN
;
11079 new_inst
= OPCODE_MOV
;
11083 case OPCODE_AND
: /* AND <-> BIC */
11084 new_inst
= OPCODE_BIC
;
11089 new_inst
= OPCODE_AND
;
11093 case OPCODE_ADC
: /* ADC <-> SBC */
11094 new_inst
= OPCODE_SBC
;
11099 new_inst
= OPCODE_ADC
;
11103 /* We cannot do anything. */
11108 if (value
== (unsigned) FAIL
)
11111 *instruction
&= OPCODE_MASK
;
11112 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
11116 /* Read a 32-bit thumb instruction from buf. */
11117 static unsigned long
11118 get_thumb32_insn (char * buf
)
11120 unsigned long insn
;
11121 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
11122 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
11128 md_apply_fix (fixS
* fixP
,
11132 offsetT value
= * valP
;
11134 unsigned int newimm
;
11135 unsigned long temp
;
11137 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11139 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
11141 /* Note whether this will delete the relocation. */
11142 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
11145 /* On a 64-bit host, silently truncate 'value' to 32 bits for
11146 consistency with the behavior on 32-bit hosts. Remember value
11148 value
&= 0xffffffff;
11149 value
^= 0x80000000;
11150 value
-= 0x80000000;
11153 fixP
->fx_addnumber
= value
;
11155 /* Same treatment for fixP->fx_offset. */
11156 fixP
->fx_offset
&= 0xffffffff;
11157 fixP
->fx_offset
^= 0x80000000;
11158 fixP
->fx_offset
-= 0x80000000;
11160 switch (fixP
->fx_r_type
)
11162 case BFD_RELOC_NONE
:
11163 /* This will need to go in the object file. */
11167 case BFD_RELOC_ARM_IMMEDIATE
:
11168 /* We claim that this fixup has been processed here,
11169 even if in fact we generate an error because we do
11170 not have a reloc for it, so tc_gen_reloc will reject it. */
11174 && ! S_IS_DEFINED (fixP
->fx_addsy
))
11176 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11177 _("undefined symbol %s used as an immediate value"),
11178 S_GET_NAME (fixP
->fx_addsy
));
11182 newimm
= encode_arm_immediate (value
);
11183 temp
= md_chars_to_number (buf
, INSN_SIZE
);
11185 /* If the instruction will fail, see if we can fix things up by
11186 changing the opcode. */
11187 if (newimm
== (unsigned int) FAIL
11188 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
11190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11191 _("invalid constant (%lx) after fixup"),
11192 (unsigned long) value
);
11196 newimm
|= (temp
& 0xfffff000);
11197 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
11200 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
11202 unsigned int highpart
= 0;
11203 unsigned int newinsn
= 0xe1a00000; /* nop. */
11205 newimm
= encode_arm_immediate (value
);
11206 temp
= md_chars_to_number (buf
, INSN_SIZE
);
11208 /* If the instruction will fail, see if we can fix things up by
11209 changing the opcode. */
11210 if (newimm
== (unsigned int) FAIL
11211 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
11213 /* No ? OK - try using two ADD instructions to generate
11215 newimm
= validate_immediate_twopart (value
, & highpart
);
11217 /* Yes - then make sure that the second instruction is
11219 if (newimm
!= (unsigned int) FAIL
)
11221 /* Still No ? Try using a negated value. */
11222 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
11223 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
11224 /* Otherwise - give up. */
11227 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11228 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
11233 /* Replace the first operand in the 2nd instruction (which
11234 is the PC) with the destination register. We have
11235 already added in the PC in the first instruction and we
11236 do not want to do it again. */
11237 newinsn
&= ~ 0xf0000;
11238 newinsn
|= ((newinsn
& 0x0f000) << 4);
11241 newimm
|= (temp
& 0xfffff000);
11242 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
11244 highpart
|= (newinsn
& 0xfffff000);
11245 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
11249 case BFD_RELOC_ARM_OFFSET_IMM
:
11250 case BFD_RELOC_ARM_LITERAL
:
11256 if (validate_offset_imm (value
, 0) == FAIL
)
11258 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
11259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11260 _("invalid literal constant: pool needs to be closer"));
11262 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11263 _("bad immediate value for offset (%ld)"),
11268 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11269 newval
&= 0xff7ff000;
11270 newval
|= value
| (sign
? INDEX_UP
: 0);
11271 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11274 case BFD_RELOC_ARM_OFFSET_IMM8
:
11275 case BFD_RELOC_ARM_HWLITERAL
:
11281 if (validate_offset_imm (value
, 1) == FAIL
)
11283 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
11284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11285 _("invalid literal constant: pool needs to be closer"));
11287 as_bad (_("bad immediate value for half-word offset (%ld)"),
11292 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11293 newval
&= 0xff7ff0f0;
11294 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
11295 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11298 case BFD_RELOC_ARM_T32_OFFSET_U8
:
11299 if (value
< 0 || value
> 1020 || value
% 4 != 0)
11300 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11301 _("bad immediate value for offset (%ld)"), (long) value
);
11304 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
11306 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
11309 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
11310 /* This is a complicated relocation used for all varieties of Thumb32
11311 load/store instruction with immediate offset:
11313 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
11314 *4, optional writeback(W)
11315 (doubleword load/store)
11317 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
11318 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
11319 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
11320 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
11321 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
11323 Uppercase letters indicate bits that are already encoded at
11324 this point. Lowercase letters are our problem. For the
11325 second block of instructions, the secondary opcode nybble
11326 (bits 8..11) is present, and bit 23 is zero, even if this is
11327 a PC-relative operation. */
11328 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11330 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
11332 if ((newval
& 0xf0000000) == 0xe0000000)
11334 /* Doubleword load/store: 8-bit offset, scaled by 4. */
11336 newval
|= (1 << 23);
11339 if (value
% 4 != 0)
11341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11342 _("offset not a multiple of 4"));
11348 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11349 _("offset out of range"));
11354 else if ((newval
& 0x000f0000) == 0x000f0000)
11356 /* PC-relative, 12-bit offset. */
11358 newval
|= (1 << 23);
11361 if (value
>= 0xfff)
11363 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11364 _("offset out of range"));
11369 else if ((newval
& 0x00000100) == 0x00000100)
11371 /* Writeback: 8-bit, +/- offset. */
11373 newval
|= (1 << 9);
11378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11379 _("offset out of range"));
11384 else if ((newval
& 0x00000f00) == 0x00000e00)
11386 /* T-instruction: positive 8-bit offset. */
11387 if (value
< 0 || value
>= 0xff)
11389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11390 _("offset out of range"));
11398 /* Positive 12-bit or negative 8-bit offset. */
11402 newval
|= (1 << 23);
11412 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11413 _("offset out of range"));
11420 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
11421 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
11424 case BFD_RELOC_ARM_SHIFT_IMM
:
11425 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11426 if (((unsigned long) value
) > 32
11428 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
11430 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11431 _("shift expression is too large"));
11436 /* Shifts of zero must be done as lsl. */
11438 else if (value
== 32)
11440 newval
&= 0xfffff07f;
11441 newval
|= (value
& 0x1f) << 7;
11442 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11445 case BFD_RELOC_ARM_T32_IMMEDIATE
:
11446 case BFD_RELOC_ARM_T32_IMM12
:
11447 case BFD_RELOC_ARM_T32_ADD_PC12
:
11448 /* We claim that this fixup has been processed here,
11449 even if in fact we generate an error because we do
11450 not have a reloc for it, so tc_gen_reloc will reject it. */
11454 && ! S_IS_DEFINED (fixP
->fx_addsy
))
11456 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11457 _("undefined symbol %s used as an immediate value"),
11458 S_GET_NAME (fixP
->fx_addsy
));
11462 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11464 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
11466 /* FUTURE: Implement analogue of negate_data_op for T32. */
11467 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
)
11468 newimm
= encode_thumb32_immediate (value
);
11471 /* 12 bit immediate for addw/subw. */
11475 newval
^= 0x00a00000;
11478 newimm
= (unsigned int) FAIL
;
11483 if (newimm
== (unsigned int)FAIL
)
11485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11486 _("invalid constant (%lx) after fixup"),
11487 (unsigned long) value
);
11491 newval
|= (newimm
& 0x800) << 15;
11492 newval
|= (newimm
& 0x700) << 4;
11493 newval
|= (newimm
& 0x0ff);
11495 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
11496 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
11499 case BFD_RELOC_ARM_SMC
:
11500 if (((unsigned long) value
) > 0xffff)
11501 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11502 _("invalid smc expression"));
11503 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11504 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
11505 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11508 case BFD_RELOC_ARM_SWI
:
11509 if (fixP
->tc_fix_data
!= 0)
11511 if (((unsigned long) value
) > 0xff)
11512 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11513 _("invalid swi expression"));
11514 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11516 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11520 if (((unsigned long) value
) > 0x00ffffff)
11521 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11522 _("invalid swi expression"));
11523 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11525 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11529 case BFD_RELOC_ARM_MULTI
:
11530 if (((unsigned long) value
) > 0xffff)
11531 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11532 _("invalid expression in load/store multiple"));
11533 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
11534 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11538 case BFD_RELOC_ARM_PCREL_CALL
:
11539 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11540 if ((newval
& 0xf0000000) == 0xf0000000)
11544 goto arm_branch_common
;
11546 case BFD_RELOC_ARM_PCREL_JUMP
:
11547 case BFD_RELOC_ARM_PLT32
:
11549 case BFD_RELOC_ARM_PCREL_BRANCH
:
11551 goto arm_branch_common
;
11553 case BFD_RELOC_ARM_PCREL_BLX
:
11556 /* We are going to store value (shifted right by two) in the
11557 instruction, in a 24 bit, signed field. Bits 26 through 32 either
11558 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
11559 also be be clear. */
11561 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11562 _("misaligned branch destination"));
11563 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
11564 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
11565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11566 _("branch out of range"));
11568 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11570 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11571 newval
|= (value
>> 2) & 0x00ffffff;
11572 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11576 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
11577 /* CZB can only branch forward. */
11579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11580 _("branch out of range"));
11582 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11584 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11585 newval
|= ((value
& 0x2e) << 2) | ((value
& 0x40) << 3);
11586 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11590 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
11591 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
11592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11593 _("branch out of range"));
11595 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11597 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11598 newval
|= (value
& 0x1ff) >> 1;
11599 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11603 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
11604 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
11605 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11606 _("branch out of range"));
11608 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11610 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11611 newval
|= (value
& 0xfff) >> 1;
11612 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11616 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
11617 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
11618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11619 _("conditional branch out of range"));
11621 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11624 addressT S
, J1
, J2
, lo
, hi
;
11626 S
= (value
& 0x00100000) >> 20;
11627 J2
= (value
& 0x00080000) >> 19;
11628 J1
= (value
& 0x00040000) >> 18;
11629 hi
= (value
& 0x0003f000) >> 12;
11630 lo
= (value
& 0x00000ffe) >> 1;
11632 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11633 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
11634 newval
|= (S
<< 10) | hi
;
11635 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
11636 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11637 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
11641 case BFD_RELOC_THUMB_PCREL_BLX
:
11642 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
11643 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
11644 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11645 _("branch out of range"));
11647 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
11648 /* For a BLX instruction, make sure that the relocation is rounded up
11649 to a word boundary. This follows the semantics of the instruction
11650 which specifies that bit 1 of the target address will come from bit
11651 1 of the base address. */
11652 value
= (value
+ 1) & ~ 1;
11654 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11658 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11659 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
11660 newval
|= (value
& 0x7fffff) >> 12;
11661 newval2
|= (value
& 0xfff) >> 1;
11662 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11663 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
11667 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
11668 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
11669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11670 _("branch out of range"));
11672 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11675 addressT S
, I1
, I2
, lo
, hi
;
11677 S
= (value
& 0x01000000) >> 24;
11678 I1
= (value
& 0x00800000) >> 23;
11679 I2
= (value
& 0x00400000) >> 22;
11680 hi
= (value
& 0x003ff000) >> 12;
11681 lo
= (value
& 0x00000ffe) >> 1;
11686 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11687 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
11688 newval
|= (S
<< 10) | hi
;
11689 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
11690 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11691 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
11696 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11697 md_number_to_chars (buf
, value
, 1);
11701 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11702 md_number_to_chars (buf
, value
, 2);
11706 case BFD_RELOC_ARM_TLS_GD32
:
11707 case BFD_RELOC_ARM_TLS_LE32
:
11708 case BFD_RELOC_ARM_TLS_IE32
:
11709 case BFD_RELOC_ARM_TLS_LDM32
:
11710 case BFD_RELOC_ARM_TLS_LDO32
:
11711 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11714 case BFD_RELOC_ARM_GOT32
:
11715 case BFD_RELOC_ARM_GOTOFF
:
11716 case BFD_RELOC_ARM_TARGET2
:
11717 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11718 md_number_to_chars (buf
, 0, 4);
11722 case BFD_RELOC_RVA
:
11724 case BFD_RELOC_ARM_TARGET1
:
11725 case BFD_RELOC_ARM_ROSEGREL32
:
11726 case BFD_RELOC_ARM_SBREL32
:
11727 case BFD_RELOC_32_PCREL
:
11728 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11729 md_number_to_chars (buf
, value
, 4);
11733 case BFD_RELOC_ARM_PREL31
:
11734 if (fixP
->fx_done
|| !seg
->use_rela_p
)
11736 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
11737 if ((value
^ (value
>> 1)) & 0x40000000)
11739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11740 _("rel31 relocation overflow"));
11742 newval
|= value
& 0x7fffffff;
11743 md_number_to_chars (buf
, newval
, 4);
11748 case BFD_RELOC_ARM_CP_OFF_IMM
:
11749 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
11750 if (value
< -1023 || value
> 1023 || (value
& 3))
11751 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11752 _("co-processor offset out of range"));
11757 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
11758 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
11759 newval
= md_chars_to_number (buf
, INSN_SIZE
);
11761 newval
= get_thumb32_insn (buf
);
11762 newval
&= 0xff7fff00;
11763 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
11765 newval
&= ~WRITE_BACK
;
11766 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
11767 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
11768 md_number_to_chars (buf
, newval
, INSN_SIZE
);
11770 put_thumb32_insn (buf
, newval
);
11773 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
11774 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
11775 if (value
< -255 || value
> 255)
11776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11777 _("co-processor offset out of range"));
11778 goto cp_off_common
;
11780 case BFD_RELOC_ARM_THUMB_OFFSET
:
11781 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11782 /* Exactly what ranges, and where the offset is inserted depends
11783 on the type of instruction, we can establish this from the
11785 switch (newval
>> 12)
11787 case 4: /* PC load. */
11788 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
11789 forced to zero for these loads; md_pcrel_from has already
11790 compensated for this. */
11792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11793 _("invalid offset, target not word aligned (0x%08lX)"),
11794 (((unsigned long) fixP
->fx_frag
->fr_address
11795 + (unsigned long) fixP
->fx_where
) & ~3)
11796 + (unsigned long) value
);
11798 if (value
& ~0x3fc)
11799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11800 _("invalid offset, value too big (0x%08lX)"),
11803 newval
|= value
>> 2;
11806 case 9: /* SP load/store. */
11807 if (value
& ~0x3fc)
11808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11809 _("invalid offset, value too big (0x%08lX)"),
11811 newval
|= value
>> 2;
11814 case 6: /* Word load/store. */
11816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11817 _("invalid offset, value too big (0x%08lX)"),
11819 newval
|= value
<< 4; /* 6 - 2. */
11822 case 7: /* Byte load/store. */
11824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11825 _("invalid offset, value too big (0x%08lX)"),
11827 newval
|= value
<< 6;
11830 case 8: /* Halfword load/store. */
11832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11833 _("invalid offset, value too big (0x%08lX)"),
11835 newval
|= value
<< 5; /* 6 - 1. */
11839 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11840 "Unable to process relocation for thumb opcode: %lx",
11841 (unsigned long) newval
);
11844 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11847 case BFD_RELOC_ARM_THUMB_ADD
:
11848 /* This is a complicated relocation, since we use it for all of
11849 the following immediate relocations:
11853 9bit ADD/SUB SP word-aligned
11854 10bit ADD PC/SP word-aligned
11856 The type of instruction being processed is encoded in the
11863 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11865 int rd
= (newval
>> 4) & 0xf;
11866 int rs
= newval
& 0xf;
11867 int subtract
= !!(newval
& 0x8000);
11869 /* Check for HI regs, only very restricted cases allowed:
11870 Adjusting SP, and using PC or SP to get an address. */
11871 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
11872 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
11873 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11874 _("invalid Hi register with immediate"));
11876 /* If value is negative, choose the opposite instruction. */
11880 subtract
= !subtract
;
11882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11883 _("immediate value out of range"));
11888 if (value
& ~0x1fc)
11889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11890 _("invalid immediate for stack address calculation"));
11891 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
11892 newval
|= value
>> 2;
11894 else if (rs
== REG_PC
|| rs
== REG_SP
)
11896 if (subtract
|| value
& ~0x3fc)
11897 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11898 _("invalid immediate for address calculation (value = 0x%08lX)"),
11899 (unsigned long) value
);
11900 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
11902 newval
|= value
>> 2;
11907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11908 _("immediate value out of range"));
11909 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
11910 newval
|= (rd
<< 8) | value
;
11915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11916 _("immediate value out of range"));
11917 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
11918 newval
|= rd
| (rs
<< 3) | (value
<< 6);
11921 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11924 case BFD_RELOC_ARM_THUMB_IMM
:
11925 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
11926 if (value
< 0 || value
> 255)
11927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11928 _("invalid immediate: %ld is too large"),
11931 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11934 case BFD_RELOC_ARM_THUMB_SHIFT
:
11935 /* 5bit shift value (0..32). LSL cannot take 32. */
11936 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
11937 temp
= newval
& 0xf800;
11938 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
11939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11940 _("invalid shift value: %ld"), (long) value
);
11941 /* Shifts of zero must be encoded as LSL. */
11943 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
11944 /* Shifts of 32 are encoded as zero. */
11945 else if (value
== 32)
11947 newval
|= value
<< 6;
11948 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
11951 case BFD_RELOC_VTABLE_INHERIT
:
11952 case BFD_RELOC_VTABLE_ENTRY
:
11956 case BFD_RELOC_UNUSED
:
11958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11959 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
11963 /* Translate internal representation of relocation info to BFD target
11967 tc_gen_reloc (asection
* section ATTRIBUTE_UNUSED
,
11971 bfd_reloc_code_real_type code
;
11973 reloc
= xmalloc (sizeof (arelent
));
11975 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
11976 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11977 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11979 if (fixp
->fx_pcrel
)
11980 fixp
->fx_offset
= reloc
->address
;
11981 reloc
->addend
= fixp
->fx_offset
;
11983 switch (fixp
->fx_r_type
)
11986 if (fixp
->fx_pcrel
)
11988 code
= BFD_RELOC_8_PCREL
;
11993 if (fixp
->fx_pcrel
)
11995 code
= BFD_RELOC_16_PCREL
;
12000 if (fixp
->fx_pcrel
)
12002 code
= BFD_RELOC_32_PCREL
;
12006 case BFD_RELOC_NONE
:
12007 case BFD_RELOC_ARM_PCREL_BRANCH
:
12008 case BFD_RELOC_ARM_PCREL_BLX
:
12009 case BFD_RELOC_RVA
:
12010 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
12011 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
12012 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
12013 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
12014 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
12015 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
12016 case BFD_RELOC_THUMB_PCREL_BLX
:
12017 case BFD_RELOC_VTABLE_ENTRY
:
12018 case BFD_RELOC_VTABLE_INHERIT
:
12019 code
= fixp
->fx_r_type
;
12022 case BFD_RELOC_ARM_LITERAL
:
12023 case BFD_RELOC_ARM_HWLITERAL
:
12024 /* If this is called then the a literal has
12025 been referenced across a section boundary. */
12026 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12027 _("literal referenced across section boundary"));
12031 case BFD_RELOC_ARM_GOT32
:
12032 case BFD_RELOC_ARM_GOTOFF
:
12033 case BFD_RELOC_ARM_PLT32
:
12034 case BFD_RELOC_ARM_TARGET1
:
12035 case BFD_RELOC_ARM_ROSEGREL32
:
12036 case BFD_RELOC_ARM_SBREL32
:
12037 case BFD_RELOC_ARM_PREL31
:
12038 case BFD_RELOC_ARM_TARGET2
:
12039 case BFD_RELOC_ARM_TLS_LE32
:
12040 case BFD_RELOC_ARM_TLS_LDO32
:
12041 case BFD_RELOC_ARM_PCREL_CALL
:
12042 case BFD_RELOC_ARM_PCREL_JUMP
:
12043 code
= fixp
->fx_r_type
;
12046 case BFD_RELOC_ARM_TLS_GD32
:
12047 case BFD_RELOC_ARM_TLS_IE32
:
12048 case BFD_RELOC_ARM_TLS_LDM32
:
12049 /* BFD will include the symbol's address in the addend.
12050 But we don't want that, so subtract it out again here. */
12051 if (!S_IS_COMMON (fixp
->fx_addsy
))
12052 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
12053 code
= fixp
->fx_r_type
;
12057 case BFD_RELOC_ARM_IMMEDIATE
:
12058 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12059 _("internal relocation (type: IMMEDIATE) not fixed up"));
12062 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
12063 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12064 _("ADRL used for a symbol not defined in the same file"));
12067 case BFD_RELOC_ARM_OFFSET_IMM
:
12068 if (fixp
->fx_addsy
!= NULL
12069 && !S_IS_DEFINED (fixp
->fx_addsy
)
12070 && S_IS_LOCAL (fixp
->fx_addsy
))
12072 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12073 _("undefined local label `%s'"),
12074 S_GET_NAME (fixp
->fx_addsy
));
12078 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12079 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
12086 switch (fixp
->fx_r_type
)
12088 case BFD_RELOC_NONE
: type
= "NONE"; break;
12089 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
12090 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
12091 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
12092 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
12093 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
12094 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
12095 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
12096 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
12097 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
12098 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
12099 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
12100 default: type
= _("<unknown>"); break;
12102 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12103 _("cannot represent %s relocation in this object file format"),
12110 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
12112 && fixp
->fx_addsy
== GOT_symbol
)
12114 code
= BFD_RELOC_ARM_GOTPC
;
12115 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
12119 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12121 if (reloc
->howto
== NULL
)
12123 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12124 _("cannot represent %s relocation in this object file format"),
12125 bfd_get_reloc_code_name (code
));
12129 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
12130 vtable entry to be used in the relocation's section offset. */
12131 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12132 reloc
->address
= fixp
->fx_offset
;
12137 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
12140 cons_fix_new_arm (fragS
* frag
,
12145 bfd_reloc_code_real_type type
;
12149 FIXME: @@ Should look at CPU word size. */
12153 type
= BFD_RELOC_8
;
12156 type
= BFD_RELOC_16
;
12160 type
= BFD_RELOC_32
;
12163 type
= BFD_RELOC_64
;
12167 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
12170 #if defined OBJ_COFF || defined OBJ_ELF
12172 arm_validate_fix (fixS
* fixP
)
12174 /* If the destination of the branch is a defined symbol which does not have
12175 the THUMB_FUNC attribute, then we must be calling a function which has
12176 the (interfacearm) attribute. We look for the Thumb entry point to that
12177 function and change the branch to refer to that function instead. */
12178 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
12179 && fixP
->fx_addsy
!= NULL
12180 && S_IS_DEFINED (fixP
->fx_addsy
)
12181 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
12183 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
12189 arm_force_relocation (struct fix
* fixp
)
12191 #if defined (OBJ_COFF) && defined (TE_PE)
12192 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
12196 /* Resolve these relocations even if the symbol is extern or weak. */
12197 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
12198 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
12199 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
12200 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
12201 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
12202 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
12205 return generic_force_reloc (fixp
);
12209 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
12210 local labels from being added to the output symbol table when they
12211 are used with the ADRL pseudo op. The ADRL relocation should always
12212 be resolved before the binbary is emitted, so it is safe to say that
12213 it is adjustable. */
12216 arm_fix_adjustable (fixS
* fixP
)
12218 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
12225 /* Relocations against Thumb function names must be left unadjusted,
12226 so that the linker can use this information to correctly set the
12227 bottom bit of their addresses. The MIPS version of this function
12228 also prevents relocations that are mips-16 specific, but I do not
12229 know why it does this.
12232 There is one other problem that ought to be addressed here, but
12233 which currently is not: Taking the address of a label (rather
12234 than a function) and then later jumping to that address. Such
12235 addresses also ought to have their bottom bit set (assuming that
12236 they reside in Thumb code), but at the moment they will not. */
12239 arm_fix_adjustable (fixS
* fixP
)
12241 if (fixP
->fx_addsy
== NULL
)
12244 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
12245 && fixP
->fx_subsy
== NULL
)
12248 /* We need the symbol name for the VTABLE entries. */
12249 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12250 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12253 /* Don't allow symbols to be discarded on GOT related relocs. */
12254 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
12255 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
12256 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
12257 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
12258 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
12259 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
12260 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
12261 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
12262 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
12269 elf32_arm_target_format (void)
12272 return (target_big_endian
12273 ? "elf32-bigarm-symbian"
12274 : "elf32-littlearm-symbian");
12275 #elif defined (TE_VXWORKS)
12276 return (target_big_endian
12277 ? "elf32-bigarm-vxworks"
12278 : "elf32-littlearm-vxworks");
12280 if (target_big_endian
)
12281 return "elf32-bigarm";
12283 return "elf32-littlearm";
12288 armelf_frob_symbol (symbolS
* symp
,
12291 elf_frob_symbol (symp
, puntp
);
12295 /* MD interface: Finalization. */
12297 /* A good place to do this, although this was probably not intended
12298 for this kind of use. We need to dump the literal pool before
12299 references are made to a null symbol pointer. */
12304 literal_pool
* pool
;
12306 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
12308 /* Put it at the end of the relevent section. */
12309 subseg_set (pool
->section
, pool
->sub_section
);
12311 arm_elf_change_section ();
12317 /* Adjust the symbol table. This marks Thumb symbols as distinct from
12321 arm_adjust_symtab (void)
12326 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
12328 if (ARM_IS_THUMB (sym
))
12330 if (THUMB_IS_FUNC (sym
))
12332 /* Mark the symbol as a Thumb function. */
12333 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
12334 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
12335 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
12337 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
12338 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
12340 as_bad (_("%s: unexpected function type: %d"),
12341 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
12343 else switch (S_GET_STORAGE_CLASS (sym
))
12346 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
12349 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
12352 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
12360 if (ARM_IS_INTERWORK (sym
))
12361 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
12368 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
12370 if (ARM_IS_THUMB (sym
))
12372 elf_symbol_type
* elf_sym
;
12374 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
12375 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
12377 if (! bfd_is_arm_mapping_symbol_name (elf_sym
->symbol
.name
))
12379 /* If it's a .thumb_func, declare it as so,
12380 otherwise tag label as .code 16. */
12381 if (THUMB_IS_FUNC (sym
))
12382 elf_sym
->internal_elf_sym
.st_info
=
12383 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
12385 elf_sym
->internal_elf_sym
.st_info
=
12386 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
12393 /* MD interface: Initialization. */
12396 set_constant_flonums (void)
12400 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
12401 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
12411 if ( (arm_ops_hsh
= hash_new ()) == NULL
12412 || (arm_cond_hsh
= hash_new ()) == NULL
12413 || (arm_shift_hsh
= hash_new ()) == NULL
12414 || (arm_psr_hsh
= hash_new ()) == NULL
12415 || (arm_reg_hsh
= hash_new ()) == NULL
12416 || (arm_reloc_hsh
= hash_new ()) == NULL
)
12417 as_fatal (_("virtual memory exhausted"));
12419 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
12420 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
12421 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
12422 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
12423 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
12424 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
12425 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
12426 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
12427 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
12428 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
12430 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
12431 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
12434 set_constant_flonums ();
12436 /* Set the cpu variant based on the command-line options. We prefer
12437 -mcpu= over -march= if both are set (as for GCC); and we prefer
12438 -mfpu= over any other way of setting the floating point unit.
12439 Use of legacy options with new options are faulted. */
12442 if (mcpu_cpu_opt
|| march_cpu_opt
)
12443 as_bad (_("use of old and new-style options to set CPU type"));
12445 mcpu_cpu_opt
= legacy_cpu
;
12447 else if (!mcpu_cpu_opt
)
12448 mcpu_cpu_opt
= march_cpu_opt
;
12453 as_bad (_("use of old and new-style options to set FPU type"));
12455 mfpu_opt
= legacy_fpu
;
12457 else if (!mfpu_opt
)
12459 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
12460 /* Some environments specify a default FPU. If they don't, infer it
12461 from the processor. */
12463 mfpu_opt
= mcpu_fpu_opt
;
12465 mfpu_opt
= march_fpu_opt
;
12467 mfpu_opt
= &fpu_default
;
12474 mfpu_opt
= &fpu_default
;
12475 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
12476 mfpu_opt
= &fpu_arch_vfp_v2
;
12478 mfpu_opt
= &fpu_arch_fpa
;
12484 mcpu_cpu_opt
= &cpu_default
;
12485 selected_cpu
= cpu_default
;
12489 selected_cpu
= *mcpu_cpu_opt
;
12491 mcpu_cpu_opt
= &arm_arch_any
;
12494 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
12496 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
12498 #if defined OBJ_COFF || defined OBJ_ELF
12500 unsigned int flags
= 0;
12502 #if defined OBJ_ELF
12503 flags
= meabi_flags
;
12505 switch (meabi_flags
)
12507 case EF_ARM_EABI_UNKNOWN
:
12509 /* Set the flags in the private structure. */
12510 if (uses_apcs_26
) flags
|= F_APCS26
;
12511 if (support_interwork
) flags
|= F_INTERWORK
;
12512 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
12513 if (pic_code
) flags
|= F_PIC
;
12514 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
12515 flags
|= F_SOFT_FLOAT
;
12517 switch (mfloat_abi_opt
)
12519 case ARM_FLOAT_ABI_SOFT
:
12520 case ARM_FLOAT_ABI_SOFTFP
:
12521 flags
|= F_SOFT_FLOAT
;
12524 case ARM_FLOAT_ABI_HARD
:
12525 if (flags
& F_SOFT_FLOAT
)
12526 as_bad (_("hard-float conflicts with specified fpu"));
12530 /* Using pure-endian doubles (even if soft-float). */
12531 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
12532 flags
|= F_VFP_FLOAT
;
12534 #if defined OBJ_ELF
12535 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
12536 flags
|= EF_ARM_MAVERICK_FLOAT
;
12539 case EF_ARM_EABI_VER4
:
12540 /* No additional flags to set. */
12547 bfd_set_private_flags (stdoutput
, flags
);
12549 /* We have run out flags in the COFF header to encode the
12550 status of ATPCS support, so instead we create a dummy,
12551 empty, debug section called .arm.atpcs. */
12556 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
12560 bfd_set_section_flags
12561 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
12562 bfd_set_section_size (stdoutput
, sec
, 0);
12563 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
12569 /* Record the CPU type as well. */
12570 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
12571 mach
= bfd_mach_arm_iWMMXt
;
12572 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
12573 mach
= bfd_mach_arm_XScale
;
12574 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
12575 mach
= bfd_mach_arm_ep9312
;
12576 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
12577 mach
= bfd_mach_arm_5TE
;
12578 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
12580 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
12581 mach
= bfd_mach_arm_5T
;
12583 mach
= bfd_mach_arm_5
;
12585 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
12587 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
12588 mach
= bfd_mach_arm_4T
;
12590 mach
= bfd_mach_arm_4
;
12592 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
12593 mach
= bfd_mach_arm_3M
;
12594 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
12595 mach
= bfd_mach_arm_3
;
12596 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
12597 mach
= bfd_mach_arm_2a
;
12598 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
12599 mach
= bfd_mach_arm_2
;
12601 mach
= bfd_mach_arm_unknown
;
12603 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
12606 /* Command line processing. */
12609 Invocation line includes a switch not recognized by the base assembler.
12610 See if it's a processor-specific option.
12612 This routine is somewhat complicated by the need for backwards
12613 compatibility (since older releases of gcc can't be changed).
12614 The new options try to make the interface as compatible as
12617 New options (supported) are:
12619 -mcpu=<cpu name> Assemble for selected processor
12620 -march=<architecture name> Assemble for selected architecture
12621 -mfpu=<fpu architecture> Assemble for selected FPU.
12622 -EB/-mbig-endian Big-endian
12623 -EL/-mlittle-endian Little-endian
12624 -k Generate PIC code
12625 -mthumb Start in Thumb mode
12626 -mthumb-interwork Code supports ARM/Thumb interworking
12628 For now we will also provide support for:
12630 -mapcs-32 32-bit Program counter
12631 -mapcs-26 26-bit Program counter
12632 -macps-float Floats passed in FP registers
12633 -mapcs-reentrant Reentrant code
12635 (sometime these will probably be replaced with -mapcs=<list of options>
12636 and -matpcs=<list of options>)
12638 The remaining options are only supported for back-wards compatibility.
12639 Cpu variants, the arm part is optional:
12640 -m[arm]1 Currently not supported.
12641 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
12642 -m[arm]3 Arm 3 processor
12643 -m[arm]6[xx], Arm 6 processors
12644 -m[arm]7[xx][t][[d]m] Arm 7 processors
12645 -m[arm]8[10] Arm 8 processors
12646 -m[arm]9[20][tdmi] Arm 9 processors
12647 -mstrongarm[110[0]] StrongARM processors
12648 -mxscale XScale processors
12649 -m[arm]v[2345[t[e]]] Arm architectures
12650 -mall All (except the ARM1)
12652 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
12653 -mfpe-old (No float load/store multiples)
12654 -mvfpxd VFP Single precision
12656 -mno-fpu Disable all floating point instructions
12658 The following CPU names are recognized:
12659 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
12660 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
12661 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
12662 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
12663 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
12664 arm10t arm10e, arm1020t, arm1020e, arm10200e,
12665 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
12669 const char * md_shortopts
= "m:k";
12671 #ifdef ARM_BI_ENDIAN
12672 #define OPTION_EB (OPTION_MD_BASE + 0)
12673 #define OPTION_EL (OPTION_MD_BASE + 1)
12675 #if TARGET_BYTES_BIG_ENDIAN
12676 #define OPTION_EB (OPTION_MD_BASE + 0)
12678 #define OPTION_EL (OPTION_MD_BASE + 1)
12682 struct option md_longopts
[] =
12685 {"EB", no_argument
, NULL
, OPTION_EB
},
12688 {"EL", no_argument
, NULL
, OPTION_EL
},
12690 {NULL
, no_argument
, NULL
, 0}
12693 size_t md_longopts_size
= sizeof (md_longopts
);
12695 struct arm_option_table
12697 char *option
; /* Option name to match. */
12698 char *help
; /* Help information. */
12699 int *var
; /* Variable to change. */
12700 int value
; /* What to change it to. */
12701 char *deprecated
; /* If non-null, print this message. */
12704 struct arm_option_table arm_opts
[] =
12706 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
12707 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
12708 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
12709 &support_interwork
, 1, NULL
},
12710 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
12711 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
12712 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
12714 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
12715 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
12716 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
12717 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
12720 /* These are recognized by the assembler, but have no affect on code. */
12721 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
12722 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
12723 {NULL
, NULL
, NULL
, 0, NULL
}
12726 struct arm_legacy_option_table
12728 char *option
; /* Option name to match. */
12729 const arm_feature_set
**var
; /* Variable to change. */
12730 const arm_feature_set value
; /* What to change it to. */
12731 char *deprecated
; /* If non-null, print this message. */
12734 const struct arm_legacy_option_table arm_legacy_opts
[] =
12736 /* DON'T add any new processors to this list -- we want the whole list
12737 to go away... Add them to the processors table instead. */
12738 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
12739 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
12740 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
12741 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
12742 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
12743 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
12744 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
12745 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
12746 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
12747 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
12748 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
12749 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
12750 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
12751 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
12752 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
12753 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
12754 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
12755 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
12756 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
12757 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
12758 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
12759 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
12760 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
12761 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
12762 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
12763 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
12764 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
12765 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
12766 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
12767 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
12768 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
12769 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
12770 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
12771 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
12772 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
12773 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
12774 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
12775 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
12776 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
12777 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
12778 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
12779 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
12780 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
12781 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
12782 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
12783 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
12784 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
12785 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
12786 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
12787 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
12788 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
12789 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
12790 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
12791 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
12792 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
12793 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
12794 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
12795 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
12796 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
12797 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
12798 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
12799 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
12800 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
12801 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
12802 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
12803 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
12804 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
12805 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
12806 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
12807 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
12808 N_("use -mcpu=strongarm110")},
12809 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
12810 N_("use -mcpu=strongarm1100")},
12811 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
12812 N_("use -mcpu=strongarm1110")},
12813 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
12814 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
12815 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
12817 /* Architecture variants -- don't add any more to this list either. */
12818 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
12819 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
12820 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
12821 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
12822 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
12823 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
12824 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
12825 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
12826 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
12827 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
12828 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
12829 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
12830 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
12831 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
12832 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
12833 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
12834 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
12835 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
12837 /* Floating point variants -- don't add any more to this list either. */
12838 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
12839 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
12840 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
12841 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
12842 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
12844 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
12847 struct arm_cpu_option_table
12850 const arm_feature_set value
;
12851 /* For some CPUs we assume an FPU unless the user explicitly sets
12853 const arm_feature_set default_fpu
;
12854 /* The canonical name of the CPU, or NULL to use NAME converted to upper
12856 const char *canonical_name
;
12859 /* This list should, at a minimum, contain all the cpu names
12860 recognized by GCC. */
12861 static const struct arm_cpu_option_table arm_cpus
[] =
12863 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
12864 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
12865 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
12866 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
12867 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
12868 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12869 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12870 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12871 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12872 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12873 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12874 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
12875 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12876 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
12877 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12878 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
12879 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12880 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12881 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12882 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12883 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12884 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12885 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12886 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12887 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12888 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12889 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12890 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
12891 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12892 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12893 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12894 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
12895 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
12896 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
12897 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
12898 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
12899 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
12900 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
12901 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12902 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
12903 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12904 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12905 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12906 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
12907 /* For V5 or later processors we default to using VFP; but the user
12908 should really set the FPU type explicitly. */
12909 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
12910 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
12911 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
12912 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
12913 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
12914 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
12915 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
12916 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
12917 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
12918 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
12919 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
12920 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
12921 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
12922 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
12923 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
12924 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
12925 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
12926 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
12927 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
12928 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
12929 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
12930 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
12931 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
12932 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
12933 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
12934 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
12935 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
12936 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
12937 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
12938 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
12939 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
12940 /* ??? XSCALE is really an architecture. */
12941 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
12942 /* ??? iwmmxt is not a processor. */
12943 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
12944 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
12946 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
12947 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
12950 struct arm_arch_option_table
12953 const arm_feature_set value
;
12954 const arm_feature_set default_fpu
;
12957 /* This list should, at a minimum, contain all the architecture names
12958 recognized by GCC. */
12959 static const struct arm_arch_option_table arm_archs
[] =
12961 {"all", ARM_ANY
, FPU_ARCH_FPA
},
12962 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
12963 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
12964 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
12965 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
12966 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
12967 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
12968 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
12969 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
12970 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
12971 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
12972 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
12973 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
12974 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
12975 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
12976 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
12977 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
12978 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
12979 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
12980 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
12981 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
12982 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
12983 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
12984 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
12985 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
12986 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
12987 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
12988 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
12989 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
12992 /* ISA extensions in the co-processor space. */
12993 struct arm_option_cpu_value_table
12996 const arm_feature_set value
;
12999 static const struct arm_option_cpu_value_table arm_extensions
[] =
13001 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
13002 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
13003 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
13004 {NULL
, ARM_ARCH_NONE
}
13007 /* This list should, at a minimum, contain all the fpu names
13008 recognized by GCC. */
13009 static const struct arm_option_cpu_value_table arm_fpus
[] =
13011 {"softfpa", FPU_NONE
},
13012 {"fpe", FPU_ARCH_FPE
},
13013 {"fpe2", FPU_ARCH_FPE
},
13014 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
13015 {"fpa", FPU_ARCH_FPA
},
13016 {"fpa10", FPU_ARCH_FPA
},
13017 {"fpa11", FPU_ARCH_FPA
},
13018 {"arm7500fe", FPU_ARCH_FPA
},
13019 {"softvfp", FPU_ARCH_VFP
},
13020 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
13021 {"vfp", FPU_ARCH_VFP_V2
},
13022 {"vfp9", FPU_ARCH_VFP_V2
},
13023 {"vfp10", FPU_ARCH_VFP_V2
},
13024 {"vfp10-r0", FPU_ARCH_VFP_V1
},
13025 {"vfpxd", FPU_ARCH_VFP_V1xD
},
13026 {"arm1020t", FPU_ARCH_VFP_V1
},
13027 {"arm1020e", FPU_ARCH_VFP_V2
},
13028 {"arm1136jfs", FPU_ARCH_VFP_V2
},
13029 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
13030 {"maverick", FPU_ARCH_MAVERICK
},
13031 {NULL
, ARM_ARCH_NONE
}
13034 struct arm_option_value_table
13040 static const struct arm_option_value_table arm_float_abis
[] =
13042 {"hard", ARM_FLOAT_ABI_HARD
},
13043 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
13044 {"soft", ARM_FLOAT_ABI_SOFT
},
13049 /* We only know how to output GNU and ver 4 (AAELF) formats. */
13050 static const struct arm_option_value_table arm_eabis
[] =
13052 {"gnu", EF_ARM_EABI_UNKNOWN
},
13053 {"4", EF_ARM_EABI_VER4
},
13058 struct arm_long_option_table
13060 char * option
; /* Substring to match. */
13061 char * help
; /* Help information. */
13062 int (* func
) (char * subopt
); /* Function to decode sub-option. */
13063 char * deprecated
; /* If non-null, print this message. */
13067 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
13069 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
13071 /* Copy the feature set, so that we can modify it. */
13072 *ext_set
= **opt_p
;
13075 while (str
!= NULL
&& *str
!= 0)
13077 const struct arm_option_cpu_value_table
* opt
;
13083 as_bad (_("invalid architectural extension"));
13088 ext
= strchr (str
, '+');
13091 optlen
= ext
- str
;
13093 optlen
= strlen (str
);
13097 as_bad (_("missing architectural extension"));
13101 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
13102 if (strncmp (opt
->name
, str
, optlen
) == 0)
13104 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
13108 if (opt
->name
== NULL
)
13110 as_bad (_("unknown architectural extnsion `%s'"), str
);
13121 arm_parse_cpu (char * str
)
13123 const struct arm_cpu_option_table
* opt
;
13124 char * ext
= strchr (str
, '+');
13128 optlen
= ext
- str
;
13130 optlen
= strlen (str
);
13134 as_bad (_("missing cpu name `%s'"), str
);
13138 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
13139 if (strncmp (opt
->name
, str
, optlen
) == 0)
13141 mcpu_cpu_opt
= &opt
->value
;
13142 mcpu_fpu_opt
= &opt
->default_fpu
;
13143 if (opt
->canonical_name
)
13144 strcpy(selected_cpu_name
, opt
->canonical_name
);
13148 for (i
= 0; i
< optlen
; i
++)
13149 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
13150 selected_cpu_name
[i
] = 0;
13154 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
13159 as_bad (_("unknown cpu `%s'"), str
);
13164 arm_parse_arch (char * str
)
13166 const struct arm_arch_option_table
*opt
;
13167 char *ext
= strchr (str
, '+');
13171 optlen
= ext
- str
;
13173 optlen
= strlen (str
);
13177 as_bad (_("missing architecture name `%s'"), str
);
13181 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
13182 if (streq (opt
->name
, str
))
13184 march_cpu_opt
= &opt
->value
;
13185 march_fpu_opt
= &opt
->default_fpu
;
13186 strcpy(selected_cpu_name
, opt
->name
);
13189 return arm_parse_extension (ext
, &march_cpu_opt
);
13194 as_bad (_("unknown architecture `%s'\n"), str
);
13199 arm_parse_fpu (char * str
)
13201 const struct arm_option_cpu_value_table
* opt
;
13203 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
13204 if (streq (opt
->name
, str
))
13206 mfpu_opt
= &opt
->value
;
13210 as_bad (_("unknown floating point format `%s'\n"), str
);
13215 arm_parse_float_abi (char * str
)
13217 const struct arm_option_value_table
* opt
;
13219 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
13220 if (streq (opt
->name
, str
))
13222 mfloat_abi_opt
= opt
->value
;
13226 as_bad (_("unknown floating point abi `%s'\n"), str
);
13232 arm_parse_eabi (char * str
)
13234 const struct arm_option_value_table
*opt
;
13236 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
13237 if (streq (opt
->name
, str
))
13239 meabi_flags
= opt
->value
;
13242 as_bad (_("unknown EABI `%s'\n"), str
);
13247 struct arm_long_option_table arm_long_opts
[] =
13249 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
13250 arm_parse_cpu
, NULL
},
13251 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
13252 arm_parse_arch
, NULL
},
13253 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
13254 arm_parse_fpu
, NULL
},
13255 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
13256 arm_parse_float_abi
, NULL
},
13258 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
13259 arm_parse_eabi
, NULL
},
13261 {NULL
, NULL
, 0, NULL
}
13265 md_parse_option (int c
, char * arg
)
13267 struct arm_option_table
*opt
;
13268 const struct arm_legacy_option_table
*fopt
;
13269 struct arm_long_option_table
*lopt
;
13275 target_big_endian
= 1;
13281 target_big_endian
= 0;
13286 /* Listing option. Just ignore these, we don't support additional
13291 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
13293 if (c
== opt
->option
[0]
13294 && ((arg
== NULL
&& opt
->option
[1] == 0)
13295 || streq (arg
, opt
->option
+ 1)))
13297 #if WARN_DEPRECATED
13298 /* If the option is deprecated, tell the user. */
13299 if (opt
->deprecated
!= NULL
)
13300 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
13301 arg
? arg
: "", _(opt
->deprecated
));
13304 if (opt
->var
!= NULL
)
13305 *opt
->var
= opt
->value
;
13311 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
13313 if (c
== fopt
->option
[0]
13314 && ((arg
== NULL
&& fopt
->option
[1] == 0)
13315 || streq (arg
, fopt
->option
+ 1)))
13317 #if WARN_DEPRECATED
13318 /* If the option is deprecated, tell the user. */
13319 if (fopt
->deprecated
!= NULL
)
13320 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
13321 arg
? arg
: "", _(fopt
->deprecated
));
13324 if (fopt
->var
!= NULL
)
13325 *fopt
->var
= &fopt
->value
;
13331 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
13333 /* These options are expected to have an argument. */
13334 if (c
== lopt
->option
[0]
13336 && strncmp (arg
, lopt
->option
+ 1,
13337 strlen (lopt
->option
+ 1)) == 0)
13339 #if WARN_DEPRECATED
13340 /* If the option is deprecated, tell the user. */
13341 if (lopt
->deprecated
!= NULL
)
13342 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
13343 _(lopt
->deprecated
));
13346 /* Call the sup-option parser. */
13347 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
13358 md_show_usage (FILE * fp
)
13360 struct arm_option_table
*opt
;
13361 struct arm_long_option_table
*lopt
;
13363 fprintf (fp
, _(" ARM-specific assembler options:\n"));
13365 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
13366 if (opt
->help
!= NULL
)
13367 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
13369 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
13370 if (lopt
->help
!= NULL
)
13371 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
13375 -EB assemble code for a big-endian cpu\n"));
13380 -EL assemble code for a little-endian cpu\n"));
13386 /* Set the public EABI object attributes. */
13388 aeabi_set_public_attributes (void)
13391 arm_feature_set flags
;
13393 /* Choose the architecture based on the capabilities of the requested cpu
13394 (if any) and/or the instructions actually used. */
13395 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
13396 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
13397 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
13398 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6t2
))
13400 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6z
))
13402 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6k
))
13404 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6
))
13406 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v5e
))
13408 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v5
)
13409 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v5t
))
13411 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
))
13413 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4
))
13418 /* Tag_CPU_name. */
13419 if (selected_cpu_name
[0])
13423 p
= selected_cpu_name
;
13424 if (strncmp(p
, "armv", 4) == 0)
13429 for (i
= 0; p
[i
]; i
++)
13430 p
[i
] = TOUPPER (p
[i
]);
13432 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
13434 /* Tag_CPU_arch. */
13435 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
13436 /* Tag_ARM_ISA_use. */
13437 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
13438 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
13439 /* Tag_THUMB_ISA_use. */
13440 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
13441 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
13442 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
13443 /* Tag_VFP_arch. */
13444 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_arch_vfp_v2
)
13445 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_arch_vfp_v2
))
13446 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
13447 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_arch_vfp_v1
)
13448 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_arch_vfp_v1
))
13449 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
13450 /* Tag_WMMX_arch. */
13451 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
13452 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
13453 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
13456 /* Add the .ARM.attributes section. */
13465 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
13468 aeabi_set_public_attributes ();
13469 size
= elf32_arm_eabi_attr_size (stdoutput
);
13470 s
= subseg_new (".ARM.attributes", 0);
13471 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
13472 addr
= frag_now_fix ();
13473 p
= frag_more (size
);
13474 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
13478 /* Parse a .cpu directive. */
13481 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
13483 const struct arm_cpu_option_table
*opt
;
13487 name
= input_line_pointer
;
13488 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
13489 input_line_pointer
++;
13490 saved_char
= *input_line_pointer
;
13491 *input_line_pointer
= 0;
13493 /* Skip the first "all" entry. */
13494 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
13495 if (streq (opt
->name
, name
))
13497 mcpu_cpu_opt
= &opt
->value
;
13498 selected_cpu
= opt
->value
;
13499 if (opt
->canonical_name
)
13500 strcpy(selected_cpu_name
, opt
->canonical_name
);
13504 for (i
= 0; opt
->name
[i
]; i
++)
13505 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
13506 selected_cpu_name
[i
] = 0;
13508 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
13509 *input_line_pointer
= saved_char
;
13510 demand_empty_rest_of_line ();
13513 as_bad (_("unknown cpu `%s'"), name
);
13514 *input_line_pointer
= saved_char
;
13515 ignore_rest_of_line ();
13519 /* Parse a .arch directive. */
13522 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
13524 const struct arm_arch_option_table
*opt
;
13528 name
= input_line_pointer
;
13529 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
13530 input_line_pointer
++;
13531 saved_char
= *input_line_pointer
;
13532 *input_line_pointer
= 0;
13534 /* Skip the first "all" entry. */
13535 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
13536 if (streq (opt
->name
, name
))
13538 mcpu_cpu_opt
= &opt
->value
;
13539 selected_cpu
= opt
->value
;
13540 strcpy(selected_cpu_name
, opt
->name
);
13541 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
13542 *input_line_pointer
= saved_char
;
13543 demand_empty_rest_of_line ();
13547 as_bad (_("unknown architecture `%s'\n"), name
);
13548 *input_line_pointer
= saved_char
;
13549 ignore_rest_of_line ();
13553 /* Parse a .fpu directive. */
13556 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
13558 const struct arm_option_cpu_value_table
*opt
;
13562 name
= input_line_pointer
;
13563 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
13564 input_line_pointer
++;
13565 saved_char
= *input_line_pointer
;
13566 *input_line_pointer
= 0;
13568 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
13569 if (streq (opt
->name
, name
))
13571 mfpu_opt
= &opt
->value
;
13572 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
13573 *input_line_pointer
= saved_char
;
13574 demand_empty_rest_of_line ();
13578 as_bad (_("unknown floating point format `%s'\n"), name
);
13579 *input_line_pointer
= saved_char
;
13580 ignore_rest_of_line ();
13582 #endif /* OBJ_ELF */