1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
188 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
221 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
222 static const arm_feature_set fpu_vfp_ext_d32
=
223 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
224 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
225 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
226 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
227 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
228 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
229 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
231 static int mfloat_abi_opt
= -1;
232 /* Record user cpu selection for object attributes. */
233 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
234 /* Must be long enough to hold any of the names in arm_cpus. */
235 static char selected_cpu_name
[16];
238 static int meabi_flags
= EABI_DEFAULT
;
240 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
243 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
248 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
253 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
254 symbolS
* GOT_symbol
;
257 /* 0: assemble for ARM,
258 1: assemble for Thumb,
259 2: assemble for Thumb even though target CPU does not support thumb
261 static int thumb_mode
= 0;
262 /* A value distinct from the possible values for thumb_mode that we
263 can use to record whether thumb_mode has been copied into the
264 tc_frag_data field of a frag. */
265 #define MODE_RECORDED (1 << 4)
267 /* Specifies the intrinsic IT insn behavior mode. */
268 enum implicit_it_mode
270 IMPLICIT_IT_MODE_NEVER
= 0x00,
271 IMPLICIT_IT_MODE_ARM
= 0x01,
272 IMPLICIT_IT_MODE_THUMB
= 0x02,
273 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
275 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
277 /* If unified_syntax is true, we are processing the new unified
278 ARM/Thumb syntax. Important differences from the old ARM mode:
280 - Immediate operands do not require a # prefix.
281 - Conditional affixes always appear at the end of the
282 instruction. (For backward compatibility, those instructions
283 that formerly had them in the middle, continue to accept them
285 - The IT instruction may appear, and if it does is validated
286 against subsequent conditional affixes. It does not generate
289 Important differences from the old Thumb mode:
291 - Immediate operands do not require a # prefix.
292 - Most of the V6T2 instructions are only available in unified mode.
293 - The .N and .W suffixes are recognized and honored (it is an error
294 if they cannot be honored).
295 - All instructions set the flags if and only if they have an 's' affix.
296 - Conditional affixes may be used. They are validated against
297 preceding IT instructions. Unlike ARM mode, you cannot use a
298 conditional affix except in the scope of an IT instruction. */
300 static bfd_boolean unified_syntax
= FALSE
;
315 enum neon_el_type type
;
319 #define NEON_MAX_TYPE_ELS 4
323 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
327 enum it_instruction_type
332 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
333 if inside, should be the last one. */
334 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
335 i.e. BKPT and NOP. */
336 IT_INSN
/* The IT insn has been parsed. */
342 unsigned long instruction
;
346 /* "uncond_value" is set to the value in place of the conditional field in
347 unconditional versions of the instruction, or -1 if nothing is
350 struct neon_type vectype
;
351 /* This does not indicate an actual NEON instruction, only that
352 the mnemonic accepts neon-style type suffixes. */
354 /* Set to the opcode if the instruction needs relaxation.
355 Zero if the instruction is not relaxed. */
359 bfd_reloc_code_real_type type
;
364 enum it_instruction_type it_insn_type
;
370 struct neon_type_el vectype
;
371 unsigned present
: 1; /* Operand present. */
372 unsigned isreg
: 1; /* Operand was a register. */
373 unsigned immisreg
: 1; /* .imm field is a second register. */
374 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
375 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
376 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
377 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
378 instructions. This allows us to disambiguate ARM <-> vector insns. */
379 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
380 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
381 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
382 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
383 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
384 unsigned writeback
: 1; /* Operand has trailing ! */
385 unsigned preind
: 1; /* Preindexed address. */
386 unsigned postind
: 1; /* Postindexed address. */
387 unsigned negative
: 1; /* Index register was negated. */
388 unsigned shifted
: 1; /* Shift applied to operation. */
389 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
393 static struct arm_it inst
;
395 #define NUM_FLOAT_VALS 8
397 const char * fp_const
[] =
399 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
402 /* Number of littlenums required to hold an extended precision number. */
403 #define MAX_LITTLENUMS 6
405 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
415 #define CP_T_X 0x00008000
416 #define CP_T_Y 0x00400000
418 #define CONDS_BIT 0x00100000
419 #define LOAD_BIT 0x00100000
421 #define DOUBLE_LOAD_FLAG 0x00000001
425 const char * template_name
;
429 #define COND_ALWAYS 0xE
433 const char * template_name
;
437 struct asm_barrier_opt
439 const char * template_name
;
443 /* The bit that distinguishes CPSR and SPSR. */
444 #define SPSR_BIT (1 << 22)
446 /* The individual PSR flag bits. */
447 #define PSR_c (1 << 16)
448 #define PSR_x (1 << 17)
449 #define PSR_s (1 << 18)
450 #define PSR_f (1 << 19)
455 bfd_reloc_code_real_type reloc
;
460 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
461 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
466 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
469 /* Bits for DEFINED field in neon_typed_alias. */
470 #define NTA_HASTYPE 1
471 #define NTA_HASINDEX 2
473 struct neon_typed_alias
475 unsigned char defined
;
477 struct neon_type_el eltype
;
480 /* ARM register categories. This includes coprocessor numbers and various
481 architecture extensions' registers. */
507 /* Structure for a hash table entry for a register.
508 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
509 information which states whether a vector type or index is specified (for a
510 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
514 unsigned char number
;
516 unsigned char builtin
;
517 struct neon_typed_alias
* neon
;
520 /* Diagnostics used when we don't get a register of the expected type. */
521 const char * const reg_expected_msgs
[] =
523 N_("ARM register expected"),
524 N_("bad or missing co-processor number"),
525 N_("co-processor register expected"),
526 N_("FPA register expected"),
527 N_("VFP single precision register expected"),
528 N_("VFP/Neon double precision register expected"),
529 N_("Neon quad precision register expected"),
530 N_("VFP single or double precision register expected"),
531 N_("Neon double or quad precision register expected"),
532 N_("VFP single, double or Neon quad precision register expected"),
533 N_("VFP system register expected"),
534 N_("Maverick MVF register expected"),
535 N_("Maverick MVD register expected"),
536 N_("Maverick MVFX register expected"),
537 N_("Maverick MVDX register expected"),
538 N_("Maverick MVAX register expected"),
539 N_("Maverick DSPSC register expected"),
540 N_("iWMMXt data register expected"),
541 N_("iWMMXt control register expected"),
542 N_("iWMMXt scalar register expected"),
543 N_("XScale accumulator register expected"),
546 /* Some well known registers that we refer to directly elsewhere. */
551 /* ARM instructions take 4bytes in the object file, Thumb instructions
557 /* Basic string to match. */
558 const char * template_name
;
560 /* Parameters to instruction. */
561 unsigned int operands
[8];
563 /* Conditional tag - see opcode_lookup. */
564 unsigned int tag
: 4;
566 /* Basic instruction code. */
567 unsigned int avalue
: 28;
569 /* Thumb-format instruction code. */
572 /* Which architecture variant provides this instruction. */
573 const arm_feature_set
* avariant
;
574 const arm_feature_set
* tvariant
;
576 /* Function to call to encode instruction in ARM format. */
577 void (* aencode
) (void);
579 /* Function to call to encode instruction in Thumb format. */
580 void (* tencode
) (void);
583 /* Defines for various bits that we will want to toggle. */
584 #define INST_IMMEDIATE 0x02000000
585 #define OFFSET_REG 0x02000000
586 #define HWOFFSET_IMM 0x00400000
587 #define SHIFT_BY_REG 0x00000010
588 #define PRE_INDEX 0x01000000
589 #define INDEX_UP 0x00800000
590 #define WRITE_BACK 0x00200000
591 #define LDM_TYPE_2_OR_3 0x00400000
592 #define CPSI_MMOD 0x00020000
594 #define LITERAL_MASK 0xf000f000
595 #define OPCODE_MASK 0xfe1fffff
596 #define V4_STR_BIT 0x00000020
598 #define T2_SUBS_PC_LR 0xf3de8f00
600 #define DATA_OP_SHIFT 21
602 #define T2_OPCODE_MASK 0xfe1fffff
603 #define T2_DATA_OP_SHIFT 21
605 /* Codes to distinguish the arithmetic instructions. */
616 #define OPCODE_CMP 10
617 #define OPCODE_CMN 11
618 #define OPCODE_ORR 12
619 #define OPCODE_MOV 13
620 #define OPCODE_BIC 14
621 #define OPCODE_MVN 15
623 #define T2_OPCODE_AND 0
624 #define T2_OPCODE_BIC 1
625 #define T2_OPCODE_ORR 2
626 #define T2_OPCODE_ORN 3
627 #define T2_OPCODE_EOR 4
628 #define T2_OPCODE_ADD 8
629 #define T2_OPCODE_ADC 10
630 #define T2_OPCODE_SBC 11
631 #define T2_OPCODE_SUB 13
632 #define T2_OPCODE_RSB 14
634 #define T_OPCODE_MUL 0x4340
635 #define T_OPCODE_TST 0x4200
636 #define T_OPCODE_CMN 0x42c0
637 #define T_OPCODE_NEG 0x4240
638 #define T_OPCODE_MVN 0x43c0
640 #define T_OPCODE_ADD_R3 0x1800
641 #define T_OPCODE_SUB_R3 0x1a00
642 #define T_OPCODE_ADD_HI 0x4400
643 #define T_OPCODE_ADD_ST 0xb000
644 #define T_OPCODE_SUB_ST 0xb080
645 #define T_OPCODE_ADD_SP 0xa800
646 #define T_OPCODE_ADD_PC 0xa000
647 #define T_OPCODE_ADD_I8 0x3000
648 #define T_OPCODE_SUB_I8 0x3800
649 #define T_OPCODE_ADD_I3 0x1c00
650 #define T_OPCODE_SUB_I3 0x1e00
652 #define T_OPCODE_ASR_R 0x4100
653 #define T_OPCODE_LSL_R 0x4080
654 #define T_OPCODE_LSR_R 0x40c0
655 #define T_OPCODE_ROR_R 0x41c0
656 #define T_OPCODE_ASR_I 0x1000
657 #define T_OPCODE_LSL_I 0x0000
658 #define T_OPCODE_LSR_I 0x0800
660 #define T_OPCODE_MOV_I8 0x2000
661 #define T_OPCODE_CMP_I8 0x2800
662 #define T_OPCODE_CMP_LR 0x4280
663 #define T_OPCODE_MOV_HR 0x4600
664 #define T_OPCODE_CMP_HR 0x4500
666 #define T_OPCODE_LDR_PC 0x4800
667 #define T_OPCODE_LDR_SP 0x9800
668 #define T_OPCODE_STR_SP 0x9000
669 #define T_OPCODE_LDR_IW 0x6800
670 #define T_OPCODE_STR_IW 0x6000
671 #define T_OPCODE_LDR_IH 0x8800
672 #define T_OPCODE_STR_IH 0x8000
673 #define T_OPCODE_LDR_IB 0x7800
674 #define T_OPCODE_STR_IB 0x7000
675 #define T_OPCODE_LDR_RW 0x5800
676 #define T_OPCODE_STR_RW 0x5000
677 #define T_OPCODE_LDR_RH 0x5a00
678 #define T_OPCODE_STR_RH 0x5200
679 #define T_OPCODE_LDR_RB 0x5c00
680 #define T_OPCODE_STR_RB 0x5400
682 #define T_OPCODE_PUSH 0xb400
683 #define T_OPCODE_POP 0xbc00
685 #define T_OPCODE_BRANCH 0xe000
687 #define THUMB_SIZE 2 /* Size of thumb instruction. */
688 #define THUMB_PP_PC_LR 0x0100
689 #define THUMB_LOAD_BIT 0x0800
690 #define THUMB2_LOAD_BIT 0x00100000
692 #define BAD_ARGS _("bad arguments to instruction")
693 #define BAD_SP _("r13 not allowed here")
694 #define BAD_PC _("r15 not allowed here")
695 #define BAD_COND _("instruction cannot be conditional")
696 #define BAD_OVERLAP _("registers may not be the same")
697 #define BAD_HIREG _("lo register required")
698 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
699 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
700 #define BAD_BRANCH _("branch must be last instruction in IT block")
701 #define BAD_NOT_IT _("instruction not allowed in IT block")
702 #define BAD_FPU _("selected FPU does not support instruction")
703 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
704 #define BAD_IT_COND _("incorrect condition in IT block")
705 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
706 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
707 #define BAD_PC_ADDRESSING \
708 _("cannot use register index with PC-relative addressing")
709 #define BAD_PC_WRITEBACK \
710 _("cannot use writeback with PC-relative addressing")
712 static struct hash_control
* arm_ops_hsh
;
713 static struct hash_control
* arm_cond_hsh
;
714 static struct hash_control
* arm_shift_hsh
;
715 static struct hash_control
* arm_psr_hsh
;
716 static struct hash_control
* arm_v7m_psr_hsh
;
717 static struct hash_control
* arm_reg_hsh
;
718 static struct hash_control
* arm_reloc_hsh
;
719 static struct hash_control
* arm_barrier_opt_hsh
;
721 /* Stuff needed to resolve the label ambiguity
730 symbolS
* last_label_seen
;
731 static int label_is_thumb_function_name
= FALSE
;
733 /* Literal pool structure. Held on a per-section
734 and per-sub-section basis. */
736 #define MAX_LITERAL_POOL_SIZE 1024
737 typedef struct literal_pool
739 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
740 unsigned int next_free_entry
;
745 struct literal_pool
* next
;
748 /* Pointer to a linked list of literal pools. */
749 literal_pool
* list_of_pools
= NULL
;
752 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
754 static struct current_it now_it
;
758 now_it_compatible (int cond
)
760 return (cond
& ~1) == (now_it
.cc
& ~1);
764 conditional_insn (void)
766 return inst
.cond
!= COND_ALWAYS
;
769 static int in_it_block (void);
771 static int handle_it_state (void);
773 static void force_automatic_it_block_close (void);
775 static void it_fsm_post_encode (void);
777 #define set_it_insn_type(type) \
780 inst.it_insn_type = type; \
781 if (handle_it_state () == FAIL) \
786 #define set_it_insn_type_nonvoid(type, failret) \
789 inst.it_insn_type = type; \
790 if (handle_it_state () == FAIL) \
795 #define set_it_insn_type_last() \
798 if (inst.cond == COND_ALWAYS) \
799 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
801 set_it_insn_type (INSIDE_IT_LAST_INSN); \
807 /* This array holds the chars that always start a comment. If the
808 pre-processor is disabled, these aren't very useful. */
809 const char comment_chars
[] = "@";
811 /* This array holds the chars that only start a comment at the beginning of
812 a line. If the line seems to have the form '# 123 filename'
813 .line and .file directives will appear in the pre-processed output. */
814 /* Note that input_file.c hand checks for '#' at the beginning of the
815 first line of the input file. This is because the compiler outputs
816 #NO_APP at the beginning of its output. */
817 /* Also note that comments like this one will always work. */
818 const char line_comment_chars
[] = "#";
820 const char line_separator_chars
[] = ";";
822 /* Chars that can be used to separate mant
823 from exp in floating point numbers. */
824 const char EXP_CHARS
[] = "eE";
826 /* Chars that mean this number is a floating point constant. */
830 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
832 /* Prefix characters that indicate the start of an immediate
834 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
836 /* Separator character handling. */
838 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
841 skip_past_char (char ** str
, char c
)
852 #define skip_past_comma(str) skip_past_char (str, ',')
854 /* Arithmetic expressions (possibly involving symbols). */
856 /* Return TRUE if anything in the expression is a bignum. */
859 walk_no_bignums (symbolS
* sp
)
861 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
864 if (symbol_get_value_expression (sp
)->X_add_symbol
)
866 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
867 || (symbol_get_value_expression (sp
)->X_op_symbol
868 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
874 static int in_my_get_expression
= 0;
876 /* Third argument to my_get_expression. */
877 #define GE_NO_PREFIX 0
878 #define GE_IMM_PREFIX 1
879 #define GE_OPT_PREFIX 2
880 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
881 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
882 #define GE_OPT_PREFIX_BIG 3
885 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
890 /* In unified syntax, all prefixes are optional. */
892 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
897 case GE_NO_PREFIX
: break;
899 if (!is_immediate_prefix (**str
))
901 inst
.error
= _("immediate expression requires a # prefix");
907 case GE_OPT_PREFIX_BIG
:
908 if (is_immediate_prefix (**str
))
914 memset (ep
, 0, sizeof (expressionS
));
916 save_in
= input_line_pointer
;
917 input_line_pointer
= *str
;
918 in_my_get_expression
= 1;
919 seg
= expression (ep
);
920 in_my_get_expression
= 0;
922 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
924 /* We found a bad or missing expression in md_operand(). */
925 *str
= input_line_pointer
;
926 input_line_pointer
= save_in
;
927 if (inst
.error
== NULL
)
928 inst
.error
= (ep
->X_op
== O_absent
929 ? _("missing expression") :_("bad expression"));
934 if (seg
!= absolute_section
935 && seg
!= text_section
936 && seg
!= data_section
937 && seg
!= bss_section
938 && seg
!= undefined_section
)
940 inst
.error
= _("bad segment");
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
947 /* Get rid of any bignums now, so that we don't generate an error for which
948 we can't establish a line number later on. Big numbers are never valid
949 in instructions, which is where this routine is always called. */
950 if (prefix_mode
!= GE_OPT_PREFIX_BIG
951 && (ep
->X_op
== O_big
953 && (walk_no_bignums (ep
->X_add_symbol
)
955 && walk_no_bignums (ep
->X_op_symbol
))))))
957 inst
.error
= _("invalid constant");
958 *str
= input_line_pointer
;
959 input_line_pointer
= save_in
;
963 *str
= input_line_pointer
;
964 input_line_pointer
= save_in
;
968 /* Turn a string in input_line_pointer into a floating point constant
969 of type TYPE, and store the appropriate bytes in *LITP. The number
970 of LITTLENUMS emitted is stored in *SIZEP. An error message is
971 returned, or NULL on OK.
973 Note that fp constants aren't represent in the normal way on the ARM.
974 In big endian mode, things are as expected. However, in little endian
975 mode fp constants are big-endian word-wise, and little-endian byte-wise
976 within the words. For example, (double) 1.1 in big endian mode is
977 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
978 the byte sequence 99 99 f1 3f 9a 99 99 99.
980 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
983 md_atof (int type
, char * litP
, int * sizeP
)
986 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1018 return _("Unrecognized or unsupported floating point constant");
1021 t
= atof_ieee (input_line_pointer
, type
, words
);
1023 input_line_pointer
= t
;
1024 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1026 if (target_big_endian
)
1028 for (i
= 0; i
< prec
; i
++)
1030 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1031 litP
+= sizeof (LITTLENUM_TYPE
);
1036 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1037 for (i
= prec
- 1; i
>= 0; i
--)
1039 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1040 litP
+= sizeof (LITTLENUM_TYPE
);
1043 /* For a 4 byte float the order of elements in `words' is 1 0.
1044 For an 8 byte float the order is 1 0 3 2. */
1045 for (i
= 0; i
< prec
; i
+= 2)
1047 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1048 sizeof (LITTLENUM_TYPE
));
1049 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1050 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1051 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1058 /* We handle all bad expressions here, so that we can report the faulty
1059 instruction in the error message. */
1061 md_operand (expressionS
* exp
)
1063 if (in_my_get_expression
)
1064 exp
->X_op
= O_illegal
;
1067 /* Immediate values. */
1069 /* Generic immediate-value read function for use in directives.
1070 Accepts anything that 'expression' can fold to a constant.
1071 *val receives the number. */
1074 immediate_for_directive (int *val
)
1077 exp
.X_op
= O_illegal
;
1079 if (is_immediate_prefix (*input_line_pointer
))
1081 input_line_pointer
++;
1085 if (exp
.X_op
!= O_constant
)
1087 as_bad (_("expected #constant"));
1088 ignore_rest_of_line ();
1091 *val
= exp
.X_add_number
;
1096 /* Register parsing. */
1098 /* Generic register parser. CCP points to what should be the
1099 beginning of a register name. If it is indeed a valid register
1100 name, advance CCP over it and return the reg_entry structure;
1101 otherwise return NULL. Does not issue diagnostics. */
1103 static struct reg_entry
*
1104 arm_reg_parse_multi (char **ccp
)
1108 struct reg_entry
*reg
;
1110 #ifdef REGISTER_PREFIX
1111 if (*start
!= REGISTER_PREFIX
)
1115 #ifdef OPTIONAL_REGISTER_PREFIX
1116 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1121 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1126 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1128 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1138 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1139 enum arm_reg_type type
)
1141 /* Alternative syntaxes are accepted for a few register classes. */
1148 /* Generic coprocessor register names are allowed for these. */
1149 if (reg
&& reg
->type
== REG_TYPE_CN
)
1154 /* For backward compatibility, a bare number is valid here. */
1156 unsigned long processor
= strtoul (start
, ccp
, 10);
1157 if (*ccp
!= start
&& processor
<= 15)
1161 case REG_TYPE_MMXWC
:
1162 /* WC includes WCG. ??? I'm not sure this is true for all
1163 instructions that take WC registers. */
1164 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1175 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1176 return value is the register number or FAIL. */
1179 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1182 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1185 /* Do not allow a scalar (reg+index) to parse as a register. */
1186 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1189 if (reg
&& reg
->type
== type
)
1192 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1199 /* Parse a Neon type specifier. *STR should point at the leading '.'
1200 character. Does no verification at this stage that the type fits the opcode
1207 Can all be legally parsed by this function.
1209 Fills in neon_type struct pointer with parsed information, and updates STR
1210 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1211 type, FAIL if not. */
1214 parse_neon_type (struct neon_type
*type
, char **str
)
1221 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1223 enum neon_el_type thistype
= NT_untyped
;
1224 unsigned thissize
= -1u;
1231 /* Just a size without an explicit type. */
1235 switch (TOLOWER (*ptr
))
1237 case 'i': thistype
= NT_integer
; break;
1238 case 'f': thistype
= NT_float
; break;
1239 case 'p': thistype
= NT_poly
; break;
1240 case 's': thistype
= NT_signed
; break;
1241 case 'u': thistype
= NT_unsigned
; break;
1243 thistype
= NT_float
;
1248 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1254 /* .f is an abbreviation for .f32. */
1255 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1260 thissize
= strtoul (ptr
, &ptr
, 10);
1262 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1265 as_bad (_("bad size %d in type specifier"), thissize
);
1273 type
->el
[type
->elems
].type
= thistype
;
1274 type
->el
[type
->elems
].size
= thissize
;
1279 /* Empty/missing type is not a successful parse. */
1280 if (type
->elems
== 0)
1288 /* Errors may be set multiple times during parsing or bit encoding
1289 (particularly in the Neon bits), but usually the earliest error which is set
1290 will be the most meaningful. Avoid overwriting it with later (cascading)
1291 errors by calling this function. */
1294 first_error (const char *err
)
1300 /* Parse a single type, e.g. ".s32", leading period included. */
1302 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1305 struct neon_type optype
;
1309 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1311 if (optype
.elems
== 1)
1312 *vectype
= optype
.el
[0];
1315 first_error (_("only one type should be specified for operand"));
1321 first_error (_("vector type expected"));
1333 /* Special meanings for indices (which have a range of 0-7), which will fit into
1336 #define NEON_ALL_LANES 15
1337 #define NEON_INTERLEAVE_LANES 14
1339 /* Parse either a register or a scalar, with an optional type. Return the
1340 register number, and optionally fill in the actual type of the register
1341 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1342 type/index information in *TYPEINFO. */
1345 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1346 enum arm_reg_type
*rtype
,
1347 struct neon_typed_alias
*typeinfo
)
1350 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1351 struct neon_typed_alias atype
;
1352 struct neon_type_el parsetype
;
1356 atype
.eltype
.type
= NT_invtype
;
1357 atype
.eltype
.size
= -1;
1359 /* Try alternate syntax for some types of register. Note these are mutually
1360 exclusive with the Neon syntax extensions. */
1363 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1371 /* Undo polymorphism when a set of register types may be accepted. */
1372 if ((type
== REG_TYPE_NDQ
1373 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1374 || (type
== REG_TYPE_VFSD
1375 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1376 || (type
== REG_TYPE_NSDQ
1377 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1378 || reg
->type
== REG_TYPE_NQ
))
1379 || (type
== REG_TYPE_MMXWC
1380 && (reg
->type
== REG_TYPE_MMXWCG
)))
1381 type
= (enum arm_reg_type
) reg
->type
;
1383 if (type
!= reg
->type
)
1389 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1391 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1393 first_error (_("can't redefine type for operand"));
1396 atype
.defined
|= NTA_HASTYPE
;
1397 atype
.eltype
= parsetype
;
1400 if (skip_past_char (&str
, '[') == SUCCESS
)
1402 if (type
!= REG_TYPE_VFD
)
1404 first_error (_("only D registers may be indexed"));
1408 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1410 first_error (_("can't change index for operand"));
1414 atype
.defined
|= NTA_HASINDEX
;
1416 if (skip_past_char (&str
, ']') == SUCCESS
)
1417 atype
.index
= NEON_ALL_LANES
;
1422 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1424 if (exp
.X_op
!= O_constant
)
1426 first_error (_("constant expression required"));
1430 if (skip_past_char (&str
, ']') == FAIL
)
1433 atype
.index
= exp
.X_add_number
;
1448 /* Like arm_reg_parse, but allow allow the following extra features:
1449 - If RTYPE is non-zero, return the (possibly restricted) type of the
1450 register (e.g. Neon double or quad reg when either has been requested).
1451 - If this is a Neon vector type with additional type information, fill
1452 in the struct pointed to by VECTYPE (if non-NULL).
1453 This function will fault on encountering a scalar. */
1456 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1457 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1459 struct neon_typed_alias atype
;
1461 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1466 /* Do not allow a scalar (reg+index) to parse as a register. */
1467 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1469 first_error (_("register operand expected, but got scalar"));
1474 *vectype
= atype
.eltype
;
1481 #define NEON_SCALAR_REG(X) ((X) >> 4)
1482 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1484 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1485 have enough information to be able to do a good job bounds-checking. So, we
1486 just do easy checks here, and do further checks later. */
1489 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1493 struct neon_typed_alias atype
;
1495 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1497 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1500 if (atype
.index
== NEON_ALL_LANES
)
1502 first_error (_("scalar must have an index"));
1505 else if (atype
.index
>= 64 / elsize
)
1507 first_error (_("scalar index out of range"));
1512 *type
= atype
.eltype
;
1516 return reg
* 16 + atype
.index
;
1519 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1522 parse_reg_list (char ** strp
)
1524 char * str
= * strp
;
1528 /* We come back here if we get ranges concatenated by '+' or '|'. */
1543 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1545 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1555 first_error (_("bad range in register list"));
1559 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1561 if (range
& (1 << i
))
1563 (_("Warning: duplicated register (r%d) in register list"),
1571 if (range
& (1 << reg
))
1572 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1574 else if (reg
<= cur_reg
)
1575 as_tsktsk (_("Warning: register range not in ascending order"));
1580 while (skip_past_comma (&str
) != FAIL
1581 || (in_range
= 1, *str
++ == '-'));
1586 first_error (_("missing `}'"));
1594 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1597 if (exp
.X_op
== O_constant
)
1599 if (exp
.X_add_number
1600 != (exp
.X_add_number
& 0x0000ffff))
1602 inst
.error
= _("invalid register mask");
1606 if ((range
& exp
.X_add_number
) != 0)
1608 int regno
= range
& exp
.X_add_number
;
1611 regno
= (1 << regno
) - 1;
1613 (_("Warning: duplicated register (r%d) in register list"),
1617 range
|= exp
.X_add_number
;
1621 if (inst
.reloc
.type
!= 0)
1623 inst
.error
= _("expression too complex");
1627 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1628 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1629 inst
.reloc
.pc_rel
= 0;
1633 if (*str
== '|' || *str
== '+')
1639 while (another_range
);
1645 /* Types of registers in a list. */
1654 /* Parse a VFP register list. If the string is invalid return FAIL.
1655 Otherwise return the number of registers, and set PBASE to the first
1656 register. Parses registers of type ETYPE.
1657 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1658 - Q registers can be used to specify pairs of D registers
1659 - { } can be omitted from around a singleton register list
1660 FIXME: This is not implemented, as it would require backtracking in
1663 This could be done (the meaning isn't really ambiguous), but doesn't
1664 fit in well with the current parsing framework.
1665 - 32 D registers may be used (also true for VFPv3).
1666 FIXME: Types are ignored in these register lists, which is probably a
1670 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1675 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1679 unsigned long mask
= 0;
1684 inst
.error
= _("expecting {");
1693 regtype
= REG_TYPE_VFS
;
1698 regtype
= REG_TYPE_VFD
;
1701 case REGLIST_NEON_D
:
1702 regtype
= REG_TYPE_NDQ
;
1706 if (etype
!= REGLIST_VFP_S
)
1708 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1709 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1713 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1716 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1723 base_reg
= max_regs
;
1727 int setmask
= 1, addregs
= 1;
1729 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1731 if (new_base
== FAIL
)
1733 first_error (_(reg_expected_msgs
[regtype
]));
1737 if (new_base
>= max_regs
)
1739 first_error (_("register out of range in list"));
1743 /* Note: a value of 2 * n is returned for the register Q<n>. */
1744 if (regtype
== REG_TYPE_NQ
)
1750 if (new_base
< base_reg
)
1751 base_reg
= new_base
;
1753 if (mask
& (setmask
<< new_base
))
1755 first_error (_("invalid register list"));
1759 if ((mask
>> new_base
) != 0 && ! warned
)
1761 as_tsktsk (_("register list not in ascending order"));
1765 mask
|= setmask
<< new_base
;
1768 if (*str
== '-') /* We have the start of a range expression */
1774 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1777 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1781 if (high_range
>= max_regs
)
1783 first_error (_("register out of range in list"));
1787 if (regtype
== REG_TYPE_NQ
)
1788 high_range
= high_range
+ 1;
1790 if (high_range
<= new_base
)
1792 inst
.error
= _("register range not in ascending order");
1796 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1798 if (mask
& (setmask
<< new_base
))
1800 inst
.error
= _("invalid register list");
1804 mask
|= setmask
<< new_base
;
1809 while (skip_past_comma (&str
) != FAIL
);
1813 /* Sanity check -- should have raised a parse error above. */
1814 if (count
== 0 || count
> max_regs
)
1819 /* Final test -- the registers must be consecutive. */
1821 for (i
= 0; i
< count
; i
++)
1823 if ((mask
& (1u << i
)) == 0)
1825 inst
.error
= _("non-contiguous register range");
1835 /* True if two alias types are the same. */
1838 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1846 if (a
->defined
!= b
->defined
)
1849 if ((a
->defined
& NTA_HASTYPE
) != 0
1850 && (a
->eltype
.type
!= b
->eltype
.type
1851 || a
->eltype
.size
!= b
->eltype
.size
))
1854 if ((a
->defined
& NTA_HASINDEX
) != 0
1855 && (a
->index
!= b
->index
))
1861 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1862 The base register is put in *PBASE.
1863 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1865 The register stride (minus one) is put in bit 4 of the return value.
1866 Bits [6:5] encode the list length (minus one).
1867 The type of the list elements is put in *ELTYPE, if non-NULL. */
1869 #define NEON_LANE(X) ((X) & 0xf)
1870 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1871 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1874 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1875 struct neon_type_el
*eltype
)
1882 int leading_brace
= 0;
1883 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1885 const char *const incr_error
= _("register stride must be 1 or 2");
1886 const char *const type_error
= _("mismatched element/structure types in list");
1887 struct neon_typed_alias firsttype
;
1889 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1894 struct neon_typed_alias atype
;
1895 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1899 first_error (_(reg_expected_msgs
[rtype
]));
1906 if (rtype
== REG_TYPE_NQ
)
1913 else if (reg_incr
== -1)
1915 reg_incr
= getreg
- base_reg
;
1916 if (reg_incr
< 1 || reg_incr
> 2)
1918 first_error (_(incr_error
));
1922 else if (getreg
!= base_reg
+ reg_incr
* count
)
1924 first_error (_(incr_error
));
1928 if (! neon_alias_types_same (&atype
, &firsttype
))
1930 first_error (_(type_error
));
1934 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1938 struct neon_typed_alias htype
;
1939 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1941 lane
= NEON_INTERLEAVE_LANES
;
1942 else if (lane
!= NEON_INTERLEAVE_LANES
)
1944 first_error (_(type_error
));
1949 else if (reg_incr
!= 1)
1951 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1955 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1958 first_error (_(reg_expected_msgs
[rtype
]));
1961 if (! neon_alias_types_same (&htype
, &firsttype
))
1963 first_error (_(type_error
));
1966 count
+= hireg
+ dregs
- getreg
;
1970 /* If we're using Q registers, we can't use [] or [n] syntax. */
1971 if (rtype
== REG_TYPE_NQ
)
1977 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1981 else if (lane
!= atype
.index
)
1983 first_error (_(type_error
));
1987 else if (lane
== -1)
1988 lane
= NEON_INTERLEAVE_LANES
;
1989 else if (lane
!= NEON_INTERLEAVE_LANES
)
1991 first_error (_(type_error
));
1996 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1998 /* No lane set by [x]. We must be interleaving structures. */
2000 lane
= NEON_INTERLEAVE_LANES
;
2003 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2004 || (count
> 1 && reg_incr
== -1))
2006 first_error (_("error parsing element/structure list"));
2010 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2012 first_error (_("expected }"));
2020 *eltype
= firsttype
.eltype
;
2025 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2028 /* Parse an explicit relocation suffix on an expression. This is
2029 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2030 arm_reloc_hsh contains no entries, so this function can only
2031 succeed if there is no () after the word. Returns -1 on error,
2032 BFD_RELOC_UNUSED if there wasn't any suffix. */
2034 parse_reloc (char **str
)
2036 struct reloc_entry
*r
;
2040 return BFD_RELOC_UNUSED
;
2045 while (*q
&& *q
!= ')' && *q
!= ',')
2050 if ((r
= (struct reloc_entry
*)
2051 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2058 /* Directives: register aliases. */
2060 static struct reg_entry
*
2061 insert_reg_alias (char *str
, int number
, int type
)
2063 struct reg_entry
*new_reg
;
2066 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2068 if (new_reg
->builtin
)
2069 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2071 /* Only warn about a redefinition if it's not defined as the
2073 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2074 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2079 name
= xstrdup (str
);
2080 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2082 new_reg
->name
= name
;
2083 new_reg
->number
= number
;
2084 new_reg
->type
= type
;
2085 new_reg
->builtin
= FALSE
;
2086 new_reg
->neon
= NULL
;
2088 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2095 insert_neon_reg_alias (char *str
, int number
, int type
,
2096 struct neon_typed_alias
*atype
)
2098 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2102 first_error (_("attempt to redefine typed alias"));
2108 reg
->neon
= (struct neon_typed_alias
*)
2109 xmalloc (sizeof (struct neon_typed_alias
));
2110 *reg
->neon
= *atype
;
2114 /* Look for the .req directive. This is of the form:
2116 new_register_name .req existing_register_name
2118 If we find one, or if it looks sufficiently like one that we want to
2119 handle any error here, return TRUE. Otherwise return FALSE. */
2122 create_register_alias (char * newname
, char *p
)
2124 struct reg_entry
*old
;
2125 char *oldname
, *nbuf
;
2128 /* The input scrubber ensures that whitespace after the mnemonic is
2129 collapsed to single spaces. */
2131 if (strncmp (oldname
, " .req ", 6) != 0)
2135 if (*oldname
== '\0')
2138 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2141 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2145 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2146 the desired alias name, and p points to its end. If not, then
2147 the desired alias name is in the global original_case_string. */
2148 #ifdef TC_CASE_SENSITIVE
2151 newname
= original_case_string
;
2152 nlen
= strlen (newname
);
2155 nbuf
= (char *) alloca (nlen
+ 1);
2156 memcpy (nbuf
, newname
, nlen
);
2159 /* Create aliases under the new name as stated; an all-lowercase
2160 version of the new name; and an all-uppercase version of the new
2162 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2164 for (p
= nbuf
; *p
; p
++)
2167 if (strncmp (nbuf
, newname
, nlen
))
2169 /* If this attempt to create an additional alias fails, do not bother
2170 trying to create the all-lower case alias. We will fail and issue
2171 a second, duplicate error message. This situation arises when the
2172 programmer does something like:
2175 The second .req creates the "Foo" alias but then fails to create
2176 the artificial FOO alias because it has already been created by the
2178 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2182 for (p
= nbuf
; *p
; p
++)
2185 if (strncmp (nbuf
, newname
, nlen
))
2186 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2192 /* Create a Neon typed/indexed register alias using directives, e.g.:
2197 These typed registers can be used instead of the types specified after the
2198 Neon mnemonic, so long as all operands given have types. Types can also be
2199 specified directly, e.g.:
2200 vadd d0.s32, d1.s32, d2.s32 */
2203 create_neon_reg_alias (char *newname
, char *p
)
2205 enum arm_reg_type basetype
;
2206 struct reg_entry
*basereg
;
2207 struct reg_entry mybasereg
;
2208 struct neon_type ntype
;
2209 struct neon_typed_alias typeinfo
;
2210 char *namebuf
, *nameend
;
2213 typeinfo
.defined
= 0;
2214 typeinfo
.eltype
.type
= NT_invtype
;
2215 typeinfo
.eltype
.size
= -1;
2216 typeinfo
.index
= -1;
2220 if (strncmp (p
, " .dn ", 5) == 0)
2221 basetype
= REG_TYPE_VFD
;
2222 else if (strncmp (p
, " .qn ", 5) == 0)
2223 basetype
= REG_TYPE_NQ
;
2232 basereg
= arm_reg_parse_multi (&p
);
2234 if (basereg
&& basereg
->type
!= basetype
)
2236 as_bad (_("bad type for register"));
2240 if (basereg
== NULL
)
2243 /* Try parsing as an integer. */
2244 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2245 if (exp
.X_op
!= O_constant
)
2247 as_bad (_("expression must be constant"));
2250 basereg
= &mybasereg
;
2251 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2257 typeinfo
= *basereg
->neon
;
2259 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2261 /* We got a type. */
2262 if (typeinfo
.defined
& NTA_HASTYPE
)
2264 as_bad (_("can't redefine the type of a register alias"));
2268 typeinfo
.defined
|= NTA_HASTYPE
;
2269 if (ntype
.elems
!= 1)
2271 as_bad (_("you must specify a single type only"));
2274 typeinfo
.eltype
= ntype
.el
[0];
2277 if (skip_past_char (&p
, '[') == SUCCESS
)
2280 /* We got a scalar index. */
2282 if (typeinfo
.defined
& NTA_HASINDEX
)
2284 as_bad (_("can't redefine the index of a scalar alias"));
2288 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2290 if (exp
.X_op
!= O_constant
)
2292 as_bad (_("scalar index must be constant"));
2296 typeinfo
.defined
|= NTA_HASINDEX
;
2297 typeinfo
.index
= exp
.X_add_number
;
2299 if (skip_past_char (&p
, ']') == FAIL
)
2301 as_bad (_("expecting ]"));
2306 namelen
= nameend
- newname
;
2307 namebuf
= (char *) alloca (namelen
+ 1);
2308 strncpy (namebuf
, newname
, namelen
);
2309 namebuf
[namelen
] = '\0';
2311 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2312 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2314 /* Insert name in all uppercase. */
2315 for (p
= namebuf
; *p
; p
++)
2318 if (strncmp (namebuf
, newname
, namelen
))
2319 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2320 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2322 /* Insert name in all lowercase. */
2323 for (p
= namebuf
; *p
; p
++)
2326 if (strncmp (namebuf
, newname
, namelen
))
2327 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2328 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2333 /* Should never be called, as .req goes between the alias and the
2334 register name, not at the beginning of the line. */
2337 s_req (int a ATTRIBUTE_UNUSED
)
2339 as_bad (_("invalid syntax for .req directive"));
2343 s_dn (int a ATTRIBUTE_UNUSED
)
2345 as_bad (_("invalid syntax for .dn directive"));
2349 s_qn (int a ATTRIBUTE_UNUSED
)
2351 as_bad (_("invalid syntax for .qn directive"));
2354 /* The .unreq directive deletes an alias which was previously defined
2355 by .req. For example:
2361 s_unreq (int a ATTRIBUTE_UNUSED
)
2366 name
= input_line_pointer
;
2368 while (*input_line_pointer
!= 0
2369 && *input_line_pointer
!= ' '
2370 && *input_line_pointer
!= '\n')
2371 ++input_line_pointer
;
2373 saved_char
= *input_line_pointer
;
2374 *input_line_pointer
= 0;
2377 as_bad (_("invalid syntax for .unreq directive"));
2380 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2384 as_bad (_("unknown register alias '%s'"), name
);
2385 else if (reg
->builtin
)
2386 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2393 hash_delete (arm_reg_hsh
, name
, FALSE
);
2394 free ((char *) reg
->name
);
2399 /* Also locate the all upper case and all lower case versions.
2400 Do not complain if we cannot find one or the other as it
2401 was probably deleted above. */
2403 nbuf
= strdup (name
);
2404 for (p
= nbuf
; *p
; p
++)
2406 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2409 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2410 free ((char *) reg
->name
);
2416 for (p
= nbuf
; *p
; p
++)
2418 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2421 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2422 free ((char *) reg
->name
);
2432 *input_line_pointer
= saved_char
;
2433 demand_empty_rest_of_line ();
2436 /* Directives: Instruction set selection. */
2439 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2440 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2441 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2442 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2444 /* Create a new mapping symbol for the transition to STATE. */
2447 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2450 const char * symname
;
2457 type
= BSF_NO_FLAGS
;
2461 type
= BSF_NO_FLAGS
;
2465 type
= BSF_NO_FLAGS
;
2471 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2472 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2477 THUMB_SET_FUNC (symbolP
, 0);
2478 ARM_SET_THUMB (symbolP
, 0);
2479 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2483 THUMB_SET_FUNC (symbolP
, 1);
2484 ARM_SET_THUMB (symbolP
, 1);
2485 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2493 /* Save the mapping symbols for future reference. Also check that
2494 we do not place two mapping symbols at the same offset within a
2495 frag. We'll handle overlap between frags in
2496 check_mapping_symbols. */
2499 know (frag
->tc_frag_data
.first_map
== NULL
);
2500 frag
->tc_frag_data
.first_map
= symbolP
;
2502 if (frag
->tc_frag_data
.last_map
!= NULL
)
2503 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) < S_GET_VALUE (symbolP
));
2504 frag
->tc_frag_data
.last_map
= symbolP
;
2507 /* We must sometimes convert a region marked as code to data during
2508 code alignment, if an odd number of bytes have to be padded. The
2509 code mapping symbol is pushed to an aligned address. */
2512 insert_data_mapping_symbol (enum mstate state
,
2513 valueT value
, fragS
*frag
, offsetT bytes
)
2515 /* If there was already a mapping symbol, remove it. */
2516 if (frag
->tc_frag_data
.last_map
!= NULL
2517 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2519 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2523 know (frag
->tc_frag_data
.first_map
== symp
);
2524 frag
->tc_frag_data
.first_map
= NULL
;
2526 frag
->tc_frag_data
.last_map
= NULL
;
2527 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2530 make_mapping_symbol (MAP_DATA
, value
, frag
);
2531 make_mapping_symbol (state
, value
+ bytes
, frag
);
2534 static void mapping_state_2 (enum mstate state
, int max_chars
);
2536 /* Set the mapping state to STATE. Only call this when about to
2537 emit some STATE bytes to the file. */
2540 mapping_state (enum mstate state
)
2542 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2544 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2546 if (mapstate
== state
)
2547 /* The mapping symbol has already been emitted.
2548 There is nothing else to do. */
2550 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2551 /* This case will be evaluated later in the next else. */
2553 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2554 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2556 /* Only add the symbol if the offset is > 0:
2557 if we're at the first frag, check it's size > 0;
2558 if we're not at the first frag, then for sure
2559 the offset is > 0. */
2560 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2561 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2564 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2567 mapping_state_2 (state
, 0);
2571 /* Same as mapping_state, but MAX_CHARS bytes have already been
2572 allocated. Put the mapping symbol that far back. */
2575 mapping_state_2 (enum mstate state
, int max_chars
)
2577 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2579 if (!SEG_NORMAL (now_seg
))
2582 if (mapstate
== state
)
2583 /* The mapping symbol has already been emitted.
2584 There is nothing else to do. */
2587 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2588 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2591 #define mapping_state(x) ((void)0)
2592 #define mapping_state_2(x, y) ((void)0)
2595 /* Find the real, Thumb encoded start of a Thumb function. */
2599 find_real_start (symbolS
* symbolP
)
2602 const char * name
= S_GET_NAME (symbolP
);
2603 symbolS
* new_target
;
2605 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2606 #define STUB_NAME ".real_start_of"
2611 /* The compiler may generate BL instructions to local labels because
2612 it needs to perform a branch to a far away location. These labels
2613 do not have a corresponding ".real_start_of" label. We check
2614 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2615 the ".real_start_of" convention for nonlocal branches. */
2616 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2619 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2620 new_target
= symbol_find (real_start
);
2622 if (new_target
== NULL
)
2624 as_warn (_("Failed to find real start of function: %s\n"), name
);
2625 new_target
= symbolP
;
2633 opcode_select (int width
)
2640 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2641 as_bad (_("selected processor does not support THUMB opcodes"));
2644 /* No need to force the alignment, since we will have been
2645 coming from ARM mode, which is word-aligned. */
2646 record_alignment (now_seg
, 1);
2653 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2654 as_bad (_("selected processor does not support ARM opcodes"));
2659 frag_align (2, 0, 0);
2661 record_alignment (now_seg
, 1);
2666 as_bad (_("invalid instruction size selected (%d)"), width
);
2671 s_arm (int ignore ATTRIBUTE_UNUSED
)
2674 demand_empty_rest_of_line ();
2678 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2681 demand_empty_rest_of_line ();
2685 s_code (int unused ATTRIBUTE_UNUSED
)
2689 temp
= get_absolute_expression ();
2694 opcode_select (temp
);
2698 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2703 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2705 /* If we are not already in thumb mode go into it, EVEN if
2706 the target processor does not support thumb instructions.
2707 This is used by gcc/config/arm/lib1funcs.asm for example
2708 to compile interworking support functions even if the
2709 target processor should not support interworking. */
2713 record_alignment (now_seg
, 1);
2716 demand_empty_rest_of_line ();
2720 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2724 /* The following label is the name/address of the start of a Thumb function.
2725 We need to know this for the interworking support. */
2726 label_is_thumb_function_name
= TRUE
;
2729 /* Perform a .set directive, but also mark the alias as
2730 being a thumb function. */
2733 s_thumb_set (int equiv
)
2735 /* XXX the following is a duplicate of the code for s_set() in read.c
2736 We cannot just call that code as we need to get at the symbol that
2743 /* Especial apologies for the random logic:
2744 This just grew, and could be parsed much more simply!
2746 name
= input_line_pointer
;
2747 delim
= get_symbol_end ();
2748 end_name
= input_line_pointer
;
2751 if (*input_line_pointer
!= ',')
2754 as_bad (_("expected comma after name \"%s\""), name
);
2756 ignore_rest_of_line ();
2760 input_line_pointer
++;
2763 if (name
[0] == '.' && name
[1] == '\0')
2765 /* XXX - this should not happen to .thumb_set. */
2769 if ((symbolP
= symbol_find (name
)) == NULL
2770 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2773 /* When doing symbol listings, play games with dummy fragments living
2774 outside the normal fragment chain to record the file and line info
2776 if (listing
& LISTING_SYMBOLS
)
2778 extern struct list_info_struct
* listing_tail
;
2779 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2781 memset (dummy_frag
, 0, sizeof (fragS
));
2782 dummy_frag
->fr_type
= rs_fill
;
2783 dummy_frag
->line
= listing_tail
;
2784 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2785 dummy_frag
->fr_symbol
= symbolP
;
2789 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2792 /* "set" symbols are local unless otherwise specified. */
2793 SF_SET_LOCAL (symbolP
);
2794 #endif /* OBJ_COFF */
2795 } /* Make a new symbol. */
2797 symbol_table_insert (symbolP
);
2802 && S_IS_DEFINED (symbolP
)
2803 && S_GET_SEGMENT (symbolP
) != reg_section
)
2804 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2806 pseudo_set (symbolP
);
2808 demand_empty_rest_of_line ();
2810 /* XXX Now we come to the Thumb specific bit of code. */
2812 THUMB_SET_FUNC (symbolP
, 1);
2813 ARM_SET_THUMB (symbolP
, 1);
2814 #if defined OBJ_ELF || defined OBJ_COFF
2815 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2819 /* Directives: Mode selection. */
2821 /* .syntax [unified|divided] - choose the new unified syntax
2822 (same for Arm and Thumb encoding, modulo slight differences in what
2823 can be represented) or the old divergent syntax for each mode. */
2825 s_syntax (int unused ATTRIBUTE_UNUSED
)
2829 name
= input_line_pointer
;
2830 delim
= get_symbol_end ();
2832 if (!strcasecmp (name
, "unified"))
2833 unified_syntax
= TRUE
;
2834 else if (!strcasecmp (name
, "divided"))
2835 unified_syntax
= FALSE
;
2838 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2841 *input_line_pointer
= delim
;
2842 demand_empty_rest_of_line ();
2845 /* Directives: sectioning and alignment. */
2847 /* Same as s_align_ptwo but align 0 => align 2. */
2850 s_align (int unused ATTRIBUTE_UNUSED
)
2855 long max_alignment
= 15;
2857 temp
= get_absolute_expression ();
2858 if (temp
> max_alignment
)
2859 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2862 as_bad (_("alignment negative. 0 assumed."));
2866 if (*input_line_pointer
== ',')
2868 input_line_pointer
++;
2869 temp_fill
= get_absolute_expression ();
2881 /* Only make a frag if we HAVE to. */
2882 if (temp
&& !need_pass_2
)
2884 if (!fill_p
&& subseg_text_p (now_seg
))
2885 frag_align_code (temp
, 0);
2887 frag_align (temp
, (int) temp_fill
, 0);
2889 demand_empty_rest_of_line ();
2891 record_alignment (now_seg
, temp
);
2895 s_bss (int ignore ATTRIBUTE_UNUSED
)
2897 /* We don't support putting frags in the BSS segment, we fake it by
2898 marking in_bss, then looking at s_skip for clues. */
2899 subseg_set (bss_section
, 0);
2900 demand_empty_rest_of_line ();
2902 #ifdef md_elf_section_change_hook
2903 md_elf_section_change_hook ();
2908 s_even (int ignore ATTRIBUTE_UNUSED
)
2910 /* Never make frag if expect extra pass. */
2912 frag_align (1, 0, 0);
2914 record_alignment (now_seg
, 1);
2916 demand_empty_rest_of_line ();
2919 /* Directives: Literal pools. */
2921 static literal_pool
*
2922 find_literal_pool (void)
2924 literal_pool
* pool
;
2926 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2928 if (pool
->section
== now_seg
2929 && pool
->sub_section
== now_subseg
)
2936 static literal_pool
*
2937 find_or_make_literal_pool (void)
2939 /* Next literal pool ID number. */
2940 static unsigned int latest_pool_num
= 1;
2941 literal_pool
* pool
;
2943 pool
= find_literal_pool ();
2947 /* Create a new pool. */
2948 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2952 pool
->next_free_entry
= 0;
2953 pool
->section
= now_seg
;
2954 pool
->sub_section
= now_subseg
;
2955 pool
->next
= list_of_pools
;
2956 pool
->symbol
= NULL
;
2958 /* Add it to the list. */
2959 list_of_pools
= pool
;
2962 /* New pools, and emptied pools, will have a NULL symbol. */
2963 if (pool
->symbol
== NULL
)
2965 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2966 (valueT
) 0, &zero_address_frag
);
2967 pool
->id
= latest_pool_num
++;
2974 /* Add the literal in the global 'inst'
2975 structure to the relevant literal pool. */
2978 add_to_lit_pool (void)
2980 literal_pool
* pool
;
2983 pool
= find_or_make_literal_pool ();
2985 /* Check if this literal value is already in the pool. */
2986 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2988 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2989 && (inst
.reloc
.exp
.X_op
== O_constant
)
2990 && (pool
->literals
[entry
].X_add_number
2991 == inst
.reloc
.exp
.X_add_number
)
2992 && (pool
->literals
[entry
].X_unsigned
2993 == inst
.reloc
.exp
.X_unsigned
))
2996 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2997 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2998 && (pool
->literals
[entry
].X_add_number
2999 == inst
.reloc
.exp
.X_add_number
)
3000 && (pool
->literals
[entry
].X_add_symbol
3001 == inst
.reloc
.exp
.X_add_symbol
)
3002 && (pool
->literals
[entry
].X_op_symbol
3003 == inst
.reloc
.exp
.X_op_symbol
))
3007 /* Do we need to create a new entry? */
3008 if (entry
== pool
->next_free_entry
)
3010 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3012 inst
.error
= _("literal pool overflow");
3016 pool
->literals
[entry
] = inst
.reloc
.exp
;
3017 pool
->next_free_entry
+= 1;
3020 inst
.reloc
.exp
.X_op
= O_symbol
;
3021 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3022 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3027 /* Can't use symbol_new here, so have to create a symbol and then at
3028 a later date assign it a value. Thats what these functions do. */
3031 symbol_locate (symbolS
* symbolP
,
3032 const char * name
, /* It is copied, the caller can modify. */
3033 segT segment
, /* Segment identifier (SEG_<something>). */
3034 valueT valu
, /* Symbol value. */
3035 fragS
* frag
) /* Associated fragment. */
3037 unsigned int name_length
;
3038 char * preserved_copy_of_name
;
3040 name_length
= strlen (name
) + 1; /* +1 for \0. */
3041 obstack_grow (¬es
, name
, name_length
);
3042 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3044 #ifdef tc_canonicalize_symbol_name
3045 preserved_copy_of_name
=
3046 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3049 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3051 S_SET_SEGMENT (symbolP
, segment
);
3052 S_SET_VALUE (symbolP
, valu
);
3053 symbol_clear_list_pointers (symbolP
);
3055 symbol_set_frag (symbolP
, frag
);
3057 /* Link to end of symbol chain. */
3059 extern int symbol_table_frozen
;
3061 if (symbol_table_frozen
)
3065 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3067 obj_symbol_new_hook (symbolP
);
3069 #ifdef tc_symbol_new_hook
3070 tc_symbol_new_hook (symbolP
);
3074 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3075 #endif /* DEBUG_SYMS */
3080 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3083 literal_pool
* pool
;
3086 pool
= find_literal_pool ();
3088 || pool
->symbol
== NULL
3089 || pool
->next_free_entry
== 0)
3092 mapping_state (MAP_DATA
);
3094 /* Align pool as you have word accesses.
3095 Only make a frag if we have to. */
3097 frag_align (2, 0, 0);
3099 record_alignment (now_seg
, 2);
3101 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3103 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3104 (valueT
) frag_now_fix (), frag_now
);
3105 symbol_table_insert (pool
->symbol
);
3107 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3109 #if defined OBJ_COFF || defined OBJ_ELF
3110 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3113 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3114 /* First output the expression in the instruction to the pool. */
3115 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3117 /* Mark the pool as empty. */
3118 pool
->next_free_entry
= 0;
3119 pool
->symbol
= NULL
;
3123 /* Forward declarations for functions below, in the MD interface
3125 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3126 static valueT
create_unwind_entry (int);
3127 static void start_unwind_section (const segT
, int);
3128 static void add_unwind_opcode (valueT
, int);
3129 static void flush_pending_unwind (void);
3131 /* Directives: Data. */
3134 s_arm_elf_cons (int nbytes
)
3138 #ifdef md_flush_pending_output
3139 md_flush_pending_output ();
3142 if (is_it_end_of_statement ())
3144 demand_empty_rest_of_line ();
3148 #ifdef md_cons_align
3149 md_cons_align (nbytes
);
3152 mapping_state (MAP_DATA
);
3156 char *base
= input_line_pointer
;
3160 if (exp
.X_op
!= O_symbol
)
3161 emit_expr (&exp
, (unsigned int) nbytes
);
3164 char *before_reloc
= input_line_pointer
;
3165 reloc
= parse_reloc (&input_line_pointer
);
3168 as_bad (_("unrecognized relocation suffix"));
3169 ignore_rest_of_line ();
3172 else if (reloc
== BFD_RELOC_UNUSED
)
3173 emit_expr (&exp
, (unsigned int) nbytes
);
3176 reloc_howto_type
*howto
= (reloc_howto_type
*)
3177 bfd_reloc_type_lookup (stdoutput
,
3178 (bfd_reloc_code_real_type
) reloc
);
3179 int size
= bfd_get_reloc_size (howto
);
3181 if (reloc
== BFD_RELOC_ARM_PLT32
)
3183 as_bad (_("(plt) is only valid on branch targets"));
3184 reloc
= BFD_RELOC_UNUSED
;
3189 as_bad (_("%s relocations do not fit in %d bytes"),
3190 howto
->name
, nbytes
);
3193 /* We've parsed an expression stopping at O_symbol.
3194 But there may be more expression left now that we
3195 have parsed the relocation marker. Parse it again.
3196 XXX Surely there is a cleaner way to do this. */
3197 char *p
= input_line_pointer
;
3199 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3200 memcpy (save_buf
, base
, input_line_pointer
- base
);
3201 memmove (base
+ (input_line_pointer
- before_reloc
),
3202 base
, before_reloc
- base
);
3204 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3206 memcpy (base
, save_buf
, p
- base
);
3208 offset
= nbytes
- size
;
3209 p
= frag_more ((int) nbytes
);
3210 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3211 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3216 while (*input_line_pointer
++ == ',');
3218 /* Put terminator back into stream. */
3219 input_line_pointer
--;
3220 demand_empty_rest_of_line ();
3223 /* Emit an expression containing a 32-bit thumb instruction.
3224 Implementation based on put_thumb32_insn. */
3227 emit_thumb32_expr (expressionS
* exp
)
3229 expressionS exp_high
= *exp
;
3231 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3232 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3233 exp
->X_add_number
&= 0xffff;
3234 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3237 /* Guess the instruction size based on the opcode. */
3240 thumb_insn_size (int opcode
)
3242 if ((unsigned int) opcode
< 0xe800u
)
3244 else if ((unsigned int) opcode
>= 0xe8000000u
)
3251 emit_insn (expressionS
*exp
, int nbytes
)
3255 if (exp
->X_op
== O_constant
)
3260 size
= thumb_insn_size (exp
->X_add_number
);
3264 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3266 as_bad (_(".inst.n operand too big. "\
3267 "Use .inst.w instead"));
3272 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3273 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3275 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3277 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3278 emit_thumb32_expr (exp
);
3280 emit_expr (exp
, (unsigned int) size
);
3282 it_fsm_post_encode ();
3286 as_bad (_("cannot determine Thumb instruction size. " \
3287 "Use .inst.n/.inst.w instead"));
3290 as_bad (_("constant expression required"));
3295 /* Like s_arm_elf_cons but do not use md_cons_align and
3296 set the mapping state to MAP_ARM/MAP_THUMB. */
3299 s_arm_elf_inst (int nbytes
)
3301 if (is_it_end_of_statement ())
3303 demand_empty_rest_of_line ();
3307 /* Calling mapping_state () here will not change ARM/THUMB,
3308 but will ensure not to be in DATA state. */
3311 mapping_state (MAP_THUMB
);
3316 as_bad (_("width suffixes are invalid in ARM mode"));
3317 ignore_rest_of_line ();
3323 mapping_state (MAP_ARM
);
3332 if (! emit_insn (& exp
, nbytes
))
3334 ignore_rest_of_line ();
3338 while (*input_line_pointer
++ == ',');
3340 /* Put terminator back into stream. */
3341 input_line_pointer
--;
3342 demand_empty_rest_of_line ();
3345 /* Parse a .rel31 directive. */
3348 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3355 if (*input_line_pointer
== '1')
3356 highbit
= 0x80000000;
3357 else if (*input_line_pointer
!= '0')
3358 as_bad (_("expected 0 or 1"));
3360 input_line_pointer
++;
3361 if (*input_line_pointer
!= ',')
3362 as_bad (_("missing comma"));
3363 input_line_pointer
++;
3365 #ifdef md_flush_pending_output
3366 md_flush_pending_output ();
3369 #ifdef md_cons_align
3373 mapping_state (MAP_DATA
);
3378 md_number_to_chars (p
, highbit
, 4);
3379 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3380 BFD_RELOC_ARM_PREL31
);
3382 demand_empty_rest_of_line ();
3385 /* Directives: AEABI stack-unwind tables. */
3387 /* Parse an unwind_fnstart directive. Simply records the current location. */
3390 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3392 demand_empty_rest_of_line ();
3393 if (unwind
.proc_start
)
3395 as_bad (_("duplicate .fnstart directive"));
3399 /* Mark the start of the function. */
3400 unwind
.proc_start
= expr_build_dot ();
3402 /* Reset the rest of the unwind info. */
3403 unwind
.opcode_count
= 0;
3404 unwind
.table_entry
= NULL
;
3405 unwind
.personality_routine
= NULL
;
3406 unwind
.personality_index
= -1;
3407 unwind
.frame_size
= 0;
3408 unwind
.fp_offset
= 0;
3409 unwind
.fp_reg
= REG_SP
;
3411 unwind
.sp_restored
= 0;
3415 /* Parse a handlerdata directive. Creates the exception handling table entry
3416 for the function. */
3419 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3421 demand_empty_rest_of_line ();
3422 if (!unwind
.proc_start
)
3423 as_bad (MISSING_FNSTART
);
3425 if (unwind
.table_entry
)
3426 as_bad (_("duplicate .handlerdata directive"));
3428 create_unwind_entry (1);
3431 /* Parse an unwind_fnend directive. Generates the index table entry. */
3434 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3439 unsigned int marked_pr_dependency
;
3441 demand_empty_rest_of_line ();
3443 if (!unwind
.proc_start
)
3445 as_bad (_(".fnend directive without .fnstart"));
3449 /* Add eh table entry. */
3450 if (unwind
.table_entry
== NULL
)
3451 val
= create_unwind_entry (0);
3455 /* Add index table entry. This is two words. */
3456 start_unwind_section (unwind
.saved_seg
, 1);
3457 frag_align (2, 0, 0);
3458 record_alignment (now_seg
, 2);
3460 ptr
= frag_more (8);
3461 where
= frag_now_fix () - 8;
3463 /* Self relative offset of the function start. */
3464 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3465 BFD_RELOC_ARM_PREL31
);
3467 /* Indicate dependency on EHABI-defined personality routines to the
3468 linker, if it hasn't been done already. */
3469 marked_pr_dependency
3470 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3471 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3472 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3474 static const char *const name
[] =
3476 "__aeabi_unwind_cpp_pr0",
3477 "__aeabi_unwind_cpp_pr1",
3478 "__aeabi_unwind_cpp_pr2"
3480 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3481 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3482 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3483 |= 1 << unwind
.personality_index
;
3487 /* Inline exception table entry. */
3488 md_number_to_chars (ptr
+ 4, val
, 4);
3490 /* Self relative offset of the table entry. */
3491 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3492 BFD_RELOC_ARM_PREL31
);
3494 /* Restore the original section. */
3495 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3497 unwind
.proc_start
= NULL
;
3501 /* Parse an unwind_cantunwind directive. */
3504 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3506 demand_empty_rest_of_line ();
3507 if (!unwind
.proc_start
)
3508 as_bad (MISSING_FNSTART
);
3510 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3511 as_bad (_("personality routine specified for cantunwind frame"));
3513 unwind
.personality_index
= -2;
3517 /* Parse a personalityindex directive. */
3520 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3524 if (!unwind
.proc_start
)
3525 as_bad (MISSING_FNSTART
);
3527 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3528 as_bad (_("duplicate .personalityindex directive"));
3532 if (exp
.X_op
!= O_constant
3533 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3535 as_bad (_("bad personality routine number"));
3536 ignore_rest_of_line ();
3540 unwind
.personality_index
= exp
.X_add_number
;
3542 demand_empty_rest_of_line ();
3546 /* Parse a personality directive. */
3549 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3553 if (!unwind
.proc_start
)
3554 as_bad (MISSING_FNSTART
);
3556 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3557 as_bad (_("duplicate .personality directive"));
3559 name
= input_line_pointer
;
3560 c
= get_symbol_end ();
3561 p
= input_line_pointer
;
3562 unwind
.personality_routine
= symbol_find_or_make (name
);
3564 demand_empty_rest_of_line ();
3568 /* Parse a directive saving core registers. */
3571 s_arm_unwind_save_core (void)
3577 range
= parse_reg_list (&input_line_pointer
);
3580 as_bad (_("expected register list"));
3581 ignore_rest_of_line ();
3585 demand_empty_rest_of_line ();
3587 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3588 into .unwind_save {..., sp...}. We aren't bothered about the value of
3589 ip because it is clobbered by calls. */
3590 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3591 && (range
& 0x3000) == 0x1000)
3593 unwind
.opcode_count
--;
3594 unwind
.sp_restored
= 0;
3595 range
= (range
| 0x2000) & ~0x1000;
3596 unwind
.pending_offset
= 0;
3602 /* See if we can use the short opcodes. These pop a block of up to 8
3603 registers starting with r4, plus maybe r14. */
3604 for (n
= 0; n
< 8; n
++)
3606 /* Break at the first non-saved register. */
3607 if ((range
& (1 << (n
+ 4))) == 0)
3610 /* See if there are any other bits set. */
3611 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3613 /* Use the long form. */
3614 op
= 0x8000 | ((range
>> 4) & 0xfff);
3615 add_unwind_opcode (op
, 2);
3619 /* Use the short form. */
3621 op
= 0xa8; /* Pop r14. */
3623 op
= 0xa0; /* Do not pop r14. */
3625 add_unwind_opcode (op
, 1);
3632 op
= 0xb100 | (range
& 0xf);
3633 add_unwind_opcode (op
, 2);
3636 /* Record the number of bytes pushed. */
3637 for (n
= 0; n
< 16; n
++)
3639 if (range
& (1 << n
))
3640 unwind
.frame_size
+= 4;
3645 /* Parse a directive saving FPA registers. */
3648 s_arm_unwind_save_fpa (int reg
)
3654 /* Get Number of registers to transfer. */
3655 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3658 exp
.X_op
= O_illegal
;
3660 if (exp
.X_op
!= O_constant
)
3662 as_bad (_("expected , <constant>"));
3663 ignore_rest_of_line ();
3667 num_regs
= exp
.X_add_number
;
3669 if (num_regs
< 1 || num_regs
> 4)
3671 as_bad (_("number of registers must be in the range [1:4]"));
3672 ignore_rest_of_line ();
3676 demand_empty_rest_of_line ();
3681 op
= 0xb4 | (num_regs
- 1);
3682 add_unwind_opcode (op
, 1);
3687 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3688 add_unwind_opcode (op
, 2);
3690 unwind
.frame_size
+= num_regs
* 12;
3694 /* Parse a directive saving VFP registers for ARMv6 and above. */
3697 s_arm_unwind_save_vfp_armv6 (void)
3702 int num_vfpv3_regs
= 0;
3703 int num_regs_below_16
;
3705 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3708 as_bad (_("expected register list"));
3709 ignore_rest_of_line ();
3713 demand_empty_rest_of_line ();
3715 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3716 than FSTMX/FLDMX-style ones). */
3718 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3720 num_vfpv3_regs
= count
;
3721 else if (start
+ count
> 16)
3722 num_vfpv3_regs
= start
+ count
- 16;
3724 if (num_vfpv3_regs
> 0)
3726 int start_offset
= start
> 16 ? start
- 16 : 0;
3727 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3728 add_unwind_opcode (op
, 2);
3731 /* Generate opcode for registers numbered in the range 0 .. 15. */
3732 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3733 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3734 if (num_regs_below_16
> 0)
3736 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3737 add_unwind_opcode (op
, 2);
3740 unwind
.frame_size
+= count
* 8;
3744 /* Parse a directive saving VFP registers for pre-ARMv6. */
3747 s_arm_unwind_save_vfp (void)
3753 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3756 as_bad (_("expected register list"));
3757 ignore_rest_of_line ();
3761 demand_empty_rest_of_line ();
3766 op
= 0xb8 | (count
- 1);
3767 add_unwind_opcode (op
, 1);
3772 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3773 add_unwind_opcode (op
, 2);
3775 unwind
.frame_size
+= count
* 8 + 4;
3779 /* Parse a directive saving iWMMXt data registers. */
3782 s_arm_unwind_save_mmxwr (void)
3790 if (*input_line_pointer
== '{')
3791 input_line_pointer
++;
3795 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3799 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3804 as_tsktsk (_("register list not in ascending order"));
3807 if (*input_line_pointer
== '-')
3809 input_line_pointer
++;
3810 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3813 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3816 else if (reg
>= hi_reg
)
3818 as_bad (_("bad register range"));
3821 for (; reg
< hi_reg
; reg
++)
3825 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3827 if (*input_line_pointer
== '}')
3828 input_line_pointer
++;
3830 demand_empty_rest_of_line ();
3832 /* Generate any deferred opcodes because we're going to be looking at
3834 flush_pending_unwind ();
3836 for (i
= 0; i
< 16; i
++)
3838 if (mask
& (1 << i
))
3839 unwind
.frame_size
+= 8;
3842 /* Attempt to combine with a previous opcode. We do this because gcc
3843 likes to output separate unwind directives for a single block of
3845 if (unwind
.opcode_count
> 0)
3847 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3848 if ((i
& 0xf8) == 0xc0)
3851 /* Only merge if the blocks are contiguous. */
3854 if ((mask
& 0xfe00) == (1 << 9))
3856 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3857 unwind
.opcode_count
--;
3860 else if (i
== 6 && unwind
.opcode_count
>= 2)
3862 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3866 op
= 0xffff << (reg
- 1);
3868 && ((mask
& op
) == (1u << (reg
- 1))))
3870 op
= (1 << (reg
+ i
+ 1)) - 1;
3871 op
&= ~((1 << reg
) - 1);
3873 unwind
.opcode_count
-= 2;
3880 /* We want to generate opcodes in the order the registers have been
3881 saved, ie. descending order. */
3882 for (reg
= 15; reg
>= -1; reg
--)
3884 /* Save registers in blocks. */
3886 || !(mask
& (1 << reg
)))
3888 /* We found an unsaved reg. Generate opcodes to save the
3895 op
= 0xc0 | (hi_reg
- 10);
3896 add_unwind_opcode (op
, 1);
3901 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3902 add_unwind_opcode (op
, 2);
3911 ignore_rest_of_line ();
3915 s_arm_unwind_save_mmxwcg (void)
3922 if (*input_line_pointer
== '{')
3923 input_line_pointer
++;
3927 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3931 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3937 as_tsktsk (_("register list not in ascending order"));
3940 if (*input_line_pointer
== '-')
3942 input_line_pointer
++;
3943 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3946 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3949 else if (reg
>= hi_reg
)
3951 as_bad (_("bad register range"));
3954 for (; reg
< hi_reg
; reg
++)
3958 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3960 if (*input_line_pointer
== '}')
3961 input_line_pointer
++;
3963 demand_empty_rest_of_line ();
3965 /* Generate any deferred opcodes because we're going to be looking at
3967 flush_pending_unwind ();
3969 for (reg
= 0; reg
< 16; reg
++)
3971 if (mask
& (1 << reg
))
3972 unwind
.frame_size
+= 4;
3975 add_unwind_opcode (op
, 2);
3978 ignore_rest_of_line ();
3982 /* Parse an unwind_save directive.
3983 If the argument is non-zero, this is a .vsave directive. */
3986 s_arm_unwind_save (int arch_v6
)
3989 struct reg_entry
*reg
;
3990 bfd_boolean had_brace
= FALSE
;
3992 if (!unwind
.proc_start
)
3993 as_bad (MISSING_FNSTART
);
3995 /* Figure out what sort of save we have. */
3996 peek
= input_line_pointer
;
4004 reg
= arm_reg_parse_multi (&peek
);
4008 as_bad (_("register expected"));
4009 ignore_rest_of_line ();
4018 as_bad (_("FPA .unwind_save does not take a register list"));
4019 ignore_rest_of_line ();
4022 input_line_pointer
= peek
;
4023 s_arm_unwind_save_fpa (reg
->number
);
4026 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4029 s_arm_unwind_save_vfp_armv6 ();
4031 s_arm_unwind_save_vfp ();
4033 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4034 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4037 as_bad (_(".unwind_save does not support this kind of register"));
4038 ignore_rest_of_line ();
4043 /* Parse an unwind_movsp directive. */
4046 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4052 if (!unwind
.proc_start
)
4053 as_bad (MISSING_FNSTART
);
4055 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4058 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4059 ignore_rest_of_line ();
4063 /* Optional constant. */
4064 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4066 if (immediate_for_directive (&offset
) == FAIL
)
4072 demand_empty_rest_of_line ();
4074 if (reg
== REG_SP
|| reg
== REG_PC
)
4076 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4080 if (unwind
.fp_reg
!= REG_SP
)
4081 as_bad (_("unexpected .unwind_movsp directive"));
4083 /* Generate opcode to restore the value. */
4085 add_unwind_opcode (op
, 1);
4087 /* Record the information for later. */
4088 unwind
.fp_reg
= reg
;
4089 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4090 unwind
.sp_restored
= 1;
4093 /* Parse an unwind_pad directive. */
4096 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4100 if (!unwind
.proc_start
)
4101 as_bad (MISSING_FNSTART
);
4103 if (immediate_for_directive (&offset
) == FAIL
)
4108 as_bad (_("stack increment must be multiple of 4"));
4109 ignore_rest_of_line ();
4113 /* Don't generate any opcodes, just record the details for later. */
4114 unwind
.frame_size
+= offset
;
4115 unwind
.pending_offset
+= offset
;
4117 demand_empty_rest_of_line ();
4120 /* Parse an unwind_setfp directive. */
4123 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4129 if (!unwind
.proc_start
)
4130 as_bad (MISSING_FNSTART
);
4132 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4133 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4136 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4138 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4140 as_bad (_("expected <reg>, <reg>"));
4141 ignore_rest_of_line ();
4145 /* Optional constant. */
4146 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4148 if (immediate_for_directive (&offset
) == FAIL
)
4154 demand_empty_rest_of_line ();
4156 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4158 as_bad (_("register must be either sp or set by a previous"
4159 "unwind_movsp directive"));
4163 /* Don't generate any opcodes, just record the information for later. */
4164 unwind
.fp_reg
= fp_reg
;
4166 if (sp_reg
== REG_SP
)
4167 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4169 unwind
.fp_offset
-= offset
;
4172 /* Parse an unwind_raw directive. */
4175 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4178 /* This is an arbitrary limit. */
4179 unsigned char op
[16];
4182 if (!unwind
.proc_start
)
4183 as_bad (MISSING_FNSTART
);
4186 if (exp
.X_op
== O_constant
4187 && skip_past_comma (&input_line_pointer
) != FAIL
)
4189 unwind
.frame_size
+= exp
.X_add_number
;
4193 exp
.X_op
= O_illegal
;
4195 if (exp
.X_op
!= O_constant
)
4197 as_bad (_("expected <offset>, <opcode>"));
4198 ignore_rest_of_line ();
4204 /* Parse the opcode. */
4209 as_bad (_("unwind opcode too long"));
4210 ignore_rest_of_line ();
4212 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4214 as_bad (_("invalid unwind opcode"));
4215 ignore_rest_of_line ();
4218 op
[count
++] = exp
.X_add_number
;
4220 /* Parse the next byte. */
4221 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4227 /* Add the opcode bytes in reverse order. */
4229 add_unwind_opcode (op
[count
], 1);
4231 demand_empty_rest_of_line ();
4235 /* Parse a .eabi_attribute directive. */
4238 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4240 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4242 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4243 attributes_set_explicitly
[tag
] = 1;
4245 #endif /* OBJ_ELF */
4247 static void s_arm_arch (int);
4248 static void s_arm_object_arch (int);
4249 static void s_arm_cpu (int);
4250 static void s_arm_fpu (int);
4255 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4262 if (exp
.X_op
== O_symbol
)
4263 exp
.X_op
= O_secrel
;
4265 emit_expr (&exp
, 4);
4267 while (*input_line_pointer
++ == ',');
4269 input_line_pointer
--;
4270 demand_empty_rest_of_line ();
4274 /* This table describes all the machine specific pseudo-ops the assembler
4275 has to support. The fields are:
4276 pseudo-op name without dot
4277 function to call to execute this pseudo-op
4278 Integer arg to pass to the function. */
4280 const pseudo_typeS md_pseudo_table
[] =
4282 /* Never called because '.req' does not start a line. */
4283 { "req", s_req
, 0 },
4284 /* Following two are likewise never called. */
4287 { "unreq", s_unreq
, 0 },
4288 { "bss", s_bss
, 0 },
4289 { "align", s_align
, 0 },
4290 { "arm", s_arm
, 0 },
4291 { "thumb", s_thumb
, 0 },
4292 { "code", s_code
, 0 },
4293 { "force_thumb", s_force_thumb
, 0 },
4294 { "thumb_func", s_thumb_func
, 0 },
4295 { "thumb_set", s_thumb_set
, 0 },
4296 { "even", s_even
, 0 },
4297 { "ltorg", s_ltorg
, 0 },
4298 { "pool", s_ltorg
, 0 },
4299 { "syntax", s_syntax
, 0 },
4300 { "cpu", s_arm_cpu
, 0 },
4301 { "arch", s_arm_arch
, 0 },
4302 { "object_arch", s_arm_object_arch
, 0 },
4303 { "fpu", s_arm_fpu
, 0 },
4305 { "word", s_arm_elf_cons
, 4 },
4306 { "long", s_arm_elf_cons
, 4 },
4307 { "inst.n", s_arm_elf_inst
, 2 },
4308 { "inst.w", s_arm_elf_inst
, 4 },
4309 { "inst", s_arm_elf_inst
, 0 },
4310 { "rel31", s_arm_rel31
, 0 },
4311 { "fnstart", s_arm_unwind_fnstart
, 0 },
4312 { "fnend", s_arm_unwind_fnend
, 0 },
4313 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4314 { "personality", s_arm_unwind_personality
, 0 },
4315 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4316 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4317 { "save", s_arm_unwind_save
, 0 },
4318 { "vsave", s_arm_unwind_save
, 1 },
4319 { "movsp", s_arm_unwind_movsp
, 0 },
4320 { "pad", s_arm_unwind_pad
, 0 },
4321 { "setfp", s_arm_unwind_setfp
, 0 },
4322 { "unwind_raw", s_arm_unwind_raw
, 0 },
4323 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4327 /* These are used for dwarf. */
4331 /* These are used for dwarf2. */
4332 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4333 { "loc", dwarf2_directive_loc
, 0 },
4334 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4336 { "extend", float_cons
, 'x' },
4337 { "ldouble", float_cons
, 'x' },
4338 { "packed", float_cons
, 'p' },
4340 {"secrel32", pe_directive_secrel
, 0},
4345 /* Parser functions used exclusively in instruction operands. */
4347 /* Generic immediate-value read function for use in insn parsing.
4348 STR points to the beginning of the immediate (the leading #);
4349 VAL receives the value; if the value is outside [MIN, MAX]
4350 issue an error. PREFIX_OPT is true if the immediate prefix is
4354 parse_immediate (char **str
, int *val
, int min
, int max
,
4355 bfd_boolean prefix_opt
)
4358 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4359 if (exp
.X_op
!= O_constant
)
4361 inst
.error
= _("constant expression required");
4365 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4367 inst
.error
= _("immediate value out of range");
4371 *val
= exp
.X_add_number
;
4375 /* Less-generic immediate-value read function with the possibility of loading a
4376 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4377 instructions. Puts the result directly in inst.operands[i]. */
4380 parse_big_immediate (char **str
, int i
)
4385 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4387 if (exp
.X_op
== O_constant
)
4389 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4390 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4391 O_constant. We have to be careful not to break compilation for
4392 32-bit X_add_number, though. */
4393 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4395 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4396 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4397 inst
.operands
[i
].regisimm
= 1;
4400 else if (exp
.X_op
== O_big
4401 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4402 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4404 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4405 /* Bignums have their least significant bits in
4406 generic_bignum[0]. Make sure we put 32 bits in imm and
4407 32 bits in reg, in a (hopefully) portable way. */
4408 gas_assert (parts
!= 0);
4409 inst
.operands
[i
].imm
= 0;
4410 for (j
= 0; j
< parts
; j
++, idx
++)
4411 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4412 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4413 inst
.operands
[i
].reg
= 0;
4414 for (j
= 0; j
< parts
; j
++, idx
++)
4415 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4416 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4417 inst
.operands
[i
].regisimm
= 1;
4427 /* Returns the pseudo-register number of an FPA immediate constant,
4428 or FAIL if there isn't a valid constant here. */
4431 parse_fpa_immediate (char ** str
)
4433 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4439 /* First try and match exact strings, this is to guarantee
4440 that some formats will work even for cross assembly. */
4442 for (i
= 0; fp_const
[i
]; i
++)
4444 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4448 *str
+= strlen (fp_const
[i
]);
4449 if (is_end_of_line
[(unsigned char) **str
])
4455 /* Just because we didn't get a match doesn't mean that the constant
4456 isn't valid, just that it is in a format that we don't
4457 automatically recognize. Try parsing it with the standard
4458 expression routines. */
4460 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4462 /* Look for a raw floating point number. */
4463 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4464 && is_end_of_line
[(unsigned char) *save_in
])
4466 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4468 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4470 if (words
[j
] != fp_values
[i
][j
])
4474 if (j
== MAX_LITTLENUMS
)
4482 /* Try and parse a more complex expression, this will probably fail
4483 unless the code uses a floating point prefix (eg "0f"). */
4484 save_in
= input_line_pointer
;
4485 input_line_pointer
= *str
;
4486 if (expression (&exp
) == absolute_section
4487 && exp
.X_op
== O_big
4488 && exp
.X_add_number
< 0)
4490 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4492 if (gen_to_words (words
, 5, (long) 15) == 0)
4494 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4496 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4498 if (words
[j
] != fp_values
[i
][j
])
4502 if (j
== MAX_LITTLENUMS
)
4504 *str
= input_line_pointer
;
4505 input_line_pointer
= save_in
;
4512 *str
= input_line_pointer
;
4513 input_line_pointer
= save_in
;
4514 inst
.error
= _("invalid FPA immediate expression");
4518 /* Returns 1 if a number has "quarter-precision" float format
4519 0baBbbbbbc defgh000 00000000 00000000. */
4522 is_quarter_float (unsigned imm
)
4524 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4525 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4528 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4529 0baBbbbbbc defgh000 00000000 00000000.
4530 The zero and minus-zero cases need special handling, since they can't be
4531 encoded in the "quarter-precision" float format, but can nonetheless be
4532 loaded as integer constants. */
4535 parse_qfloat_immediate (char **ccp
, int *immed
)
4539 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4540 int found_fpchar
= 0;
4542 skip_past_char (&str
, '#');
4544 /* We must not accidentally parse an integer as a floating-point number. Make
4545 sure that the value we parse is not an integer by checking for special
4546 characters '.' or 'e'.
4547 FIXME: This is a horrible hack, but doing better is tricky because type
4548 information isn't in a very usable state at parse time. */
4550 skip_whitespace (fpnum
);
4552 if (strncmp (fpnum
, "0x", 2) == 0)
4556 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4557 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4567 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4569 unsigned fpword
= 0;
4572 /* Our FP word must be 32 bits (single-precision FP). */
4573 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4575 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4579 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4592 /* Shift operands. */
4595 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4598 struct asm_shift_name
4601 enum shift_kind kind
;
4604 /* Third argument to parse_shift. */
4605 enum parse_shift_mode
4607 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4608 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4609 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4610 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4611 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4614 /* Parse a <shift> specifier on an ARM data processing instruction.
4615 This has three forms:
4617 (LSL|LSR|ASL|ASR|ROR) Rs
4618 (LSL|LSR|ASL|ASR|ROR) #imm
4621 Note that ASL is assimilated to LSL in the instruction encoding, and
4622 RRX to ROR #0 (which cannot be written as such). */
4625 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4627 const struct asm_shift_name
*shift_name
;
4628 enum shift_kind shift
;
4633 for (p
= *str
; ISALPHA (*p
); p
++)
4638 inst
.error
= _("shift expression expected");
4642 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4645 if (shift_name
== NULL
)
4647 inst
.error
= _("shift expression expected");
4651 shift
= shift_name
->kind
;
4655 case NO_SHIFT_RESTRICT
:
4656 case SHIFT_IMMEDIATE
: break;
4658 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4659 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4661 inst
.error
= _("'LSL' or 'ASR' required");
4666 case SHIFT_LSL_IMMEDIATE
:
4667 if (shift
!= SHIFT_LSL
)
4669 inst
.error
= _("'LSL' required");
4674 case SHIFT_ASR_IMMEDIATE
:
4675 if (shift
!= SHIFT_ASR
)
4677 inst
.error
= _("'ASR' required");
4685 if (shift
!= SHIFT_RRX
)
4687 /* Whitespace can appear here if the next thing is a bare digit. */
4688 skip_whitespace (p
);
4690 if (mode
== NO_SHIFT_RESTRICT
4691 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4693 inst
.operands
[i
].imm
= reg
;
4694 inst
.operands
[i
].immisreg
= 1;
4696 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4699 inst
.operands
[i
].shift_kind
= shift
;
4700 inst
.operands
[i
].shifted
= 1;
4705 /* Parse a <shifter_operand> for an ARM data processing instruction:
4708 #<immediate>, <rotate>
4712 where <shift> is defined by parse_shift above, and <rotate> is a
4713 multiple of 2 between 0 and 30. Validation of immediate operands
4714 is deferred to md_apply_fix. */
4717 parse_shifter_operand (char **str
, int i
)
4722 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4724 inst
.operands
[i
].reg
= value
;
4725 inst
.operands
[i
].isreg
= 1;
4727 /* parse_shift will override this if appropriate */
4728 inst
.reloc
.exp
.X_op
= O_constant
;
4729 inst
.reloc
.exp
.X_add_number
= 0;
4731 if (skip_past_comma (str
) == FAIL
)
4734 /* Shift operation on register. */
4735 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4738 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4741 if (skip_past_comma (str
) == SUCCESS
)
4743 /* #x, y -- ie explicit rotation by Y. */
4744 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4747 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4749 inst
.error
= _("constant expression expected");
4753 value
= exp
.X_add_number
;
4754 if (value
< 0 || value
> 30 || value
% 2 != 0)
4756 inst
.error
= _("invalid rotation");
4759 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4761 inst
.error
= _("invalid constant");
4765 /* Convert to decoded value. md_apply_fix will put it back. */
4766 inst
.reloc
.exp
.X_add_number
4767 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4768 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4771 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4772 inst
.reloc
.pc_rel
= 0;
4776 /* Group relocation information. Each entry in the table contains the
4777 textual name of the relocation as may appear in assembler source
4778 and must end with a colon.
4779 Along with this textual name are the relocation codes to be used if
4780 the corresponding instruction is an ALU instruction (ADD or SUB only),
4781 an LDR, an LDRS, or an LDC. */
4783 struct group_reloc_table_entry
4794 /* Varieties of non-ALU group relocation. */
4801 static struct group_reloc_table_entry group_reloc_table
[] =
4802 { /* Program counter relative: */
4804 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4809 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4810 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4811 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4812 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4814 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4819 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4820 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4821 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4822 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4824 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4825 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4826 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4827 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4828 /* Section base relative */
4830 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4835 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4836 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4837 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4838 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4840 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4845 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4846 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4847 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4848 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4850 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4851 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4852 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4853 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4855 /* Given the address of a pointer pointing to the textual name of a group
4856 relocation as may appear in assembler source, attempt to find its details
4857 in group_reloc_table. The pointer will be updated to the character after
4858 the trailing colon. On failure, FAIL will be returned; SUCCESS
4859 otherwise. On success, *entry will be updated to point at the relevant
4860 group_reloc_table entry. */
4863 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4866 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4868 int length
= strlen (group_reloc_table
[i
].name
);
4870 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4871 && (*str
)[length
] == ':')
4873 *out
= &group_reloc_table
[i
];
4874 *str
+= (length
+ 1);
4882 /* Parse a <shifter_operand> for an ARM data processing instruction
4883 (as for parse_shifter_operand) where group relocations are allowed:
4886 #<immediate>, <rotate>
4887 #:<group_reloc>:<expression>
4891 where <group_reloc> is one of the strings defined in group_reloc_table.
4892 The hashes are optional.
4894 Everything else is as for parse_shifter_operand. */
4896 static parse_operand_result
4897 parse_shifter_operand_group_reloc (char **str
, int i
)
4899 /* Determine if we have the sequence of characters #: or just :
4900 coming next. If we do, then we check for a group relocation.
4901 If we don't, punt the whole lot to parse_shifter_operand. */
4903 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4904 || (*str
)[0] == ':')
4906 struct group_reloc_table_entry
*entry
;
4908 if ((*str
)[0] == '#')
4913 /* Try to parse a group relocation. Anything else is an error. */
4914 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4916 inst
.error
= _("unknown group relocation");
4917 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4920 /* We now have the group relocation table entry corresponding to
4921 the name in the assembler source. Next, we parse the expression. */
4922 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4923 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4925 /* Record the relocation type (always the ALU variant here). */
4926 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4927 gas_assert (inst
.reloc
.type
!= 0);
4929 return PARSE_OPERAND_SUCCESS
;
4932 return parse_shifter_operand (str
, i
) == SUCCESS
4933 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4935 /* Never reached. */
4938 /* Parse all forms of an ARM address expression. Information is written
4939 to inst.operands[i] and/or inst.reloc.
4941 Preindexed addressing (.preind=1):
4943 [Rn, #offset] .reg=Rn .reloc.exp=offset
4944 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4945 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4946 .shift_kind=shift .reloc.exp=shift_imm
4948 These three may have a trailing ! which causes .writeback to be set also.
4950 Postindexed addressing (.postind=1, .writeback=1):
4952 [Rn], #offset .reg=Rn .reloc.exp=offset
4953 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4954 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4955 .shift_kind=shift .reloc.exp=shift_imm
4957 Unindexed addressing (.preind=0, .postind=0):
4959 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4963 [Rn]{!} shorthand for [Rn,#0]{!}
4964 =immediate .isreg=0 .reloc.exp=immediate
4965 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4967 It is the caller's responsibility to check for addressing modes not
4968 supported by the instruction, and to set inst.reloc.type. */
4970 static parse_operand_result
4971 parse_address_main (char **str
, int i
, int group_relocations
,
4972 group_reloc_type group_type
)
4977 if (skip_past_char (&p
, '[') == FAIL
)
4979 if (skip_past_char (&p
, '=') == FAIL
)
4981 /* Bare address - translate to PC-relative offset. */
4982 inst
.reloc
.pc_rel
= 1;
4983 inst
.operands
[i
].reg
= REG_PC
;
4984 inst
.operands
[i
].isreg
= 1;
4985 inst
.operands
[i
].preind
= 1;
4987 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
4989 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4990 return PARSE_OPERAND_FAIL
;
4993 return PARSE_OPERAND_SUCCESS
;
4996 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4998 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4999 return PARSE_OPERAND_FAIL
;
5001 inst
.operands
[i
].reg
= reg
;
5002 inst
.operands
[i
].isreg
= 1;
5004 if (skip_past_comma (&p
) == SUCCESS
)
5006 inst
.operands
[i
].preind
= 1;
5009 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5011 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5013 inst
.operands
[i
].imm
= reg
;
5014 inst
.operands
[i
].immisreg
= 1;
5016 if (skip_past_comma (&p
) == SUCCESS
)
5017 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5018 return PARSE_OPERAND_FAIL
;
5020 else if (skip_past_char (&p
, ':') == SUCCESS
)
5022 /* FIXME: '@' should be used here, but it's filtered out by generic
5023 code before we get to see it here. This may be subject to
5026 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5027 if (exp
.X_op
!= O_constant
)
5029 inst
.error
= _("alignment must be constant");
5030 return PARSE_OPERAND_FAIL
;
5032 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5033 inst
.operands
[i
].immisalign
= 1;
5034 /* Alignments are not pre-indexes. */
5035 inst
.operands
[i
].preind
= 0;
5039 if (inst
.operands
[i
].negative
)
5041 inst
.operands
[i
].negative
= 0;
5045 if (group_relocations
5046 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5048 struct group_reloc_table_entry
*entry
;
5050 /* Skip over the #: or : sequence. */
5056 /* Try to parse a group relocation. Anything else is an
5058 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5060 inst
.error
= _("unknown group relocation");
5061 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5064 /* We now have the group relocation table entry corresponding to
5065 the name in the assembler source. Next, we parse the
5067 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5068 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5070 /* Record the relocation type. */
5074 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5078 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5082 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5089 if (inst
.reloc
.type
== 0)
5091 inst
.error
= _("this group relocation is not allowed on this instruction");
5092 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5096 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5097 return PARSE_OPERAND_FAIL
;
5101 if (skip_past_char (&p
, ']') == FAIL
)
5103 inst
.error
= _("']' expected");
5104 return PARSE_OPERAND_FAIL
;
5107 if (skip_past_char (&p
, '!') == SUCCESS
)
5108 inst
.operands
[i
].writeback
= 1;
5110 else if (skip_past_comma (&p
) == SUCCESS
)
5112 if (skip_past_char (&p
, '{') == SUCCESS
)
5114 /* [Rn], {expr} - unindexed, with option */
5115 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5116 0, 255, TRUE
) == FAIL
)
5117 return PARSE_OPERAND_FAIL
;
5119 if (skip_past_char (&p
, '}') == FAIL
)
5121 inst
.error
= _("'}' expected at end of 'option' field");
5122 return PARSE_OPERAND_FAIL
;
5124 if (inst
.operands
[i
].preind
)
5126 inst
.error
= _("cannot combine index with option");
5127 return PARSE_OPERAND_FAIL
;
5130 return PARSE_OPERAND_SUCCESS
;
5134 inst
.operands
[i
].postind
= 1;
5135 inst
.operands
[i
].writeback
= 1;
5137 if (inst
.operands
[i
].preind
)
5139 inst
.error
= _("cannot combine pre- and post-indexing");
5140 return PARSE_OPERAND_FAIL
;
5144 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5146 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5148 /* We might be using the immediate for alignment already. If we
5149 are, OR the register number into the low-order bits. */
5150 if (inst
.operands
[i
].immisalign
)
5151 inst
.operands
[i
].imm
|= reg
;
5153 inst
.operands
[i
].imm
= reg
;
5154 inst
.operands
[i
].immisreg
= 1;
5156 if (skip_past_comma (&p
) == SUCCESS
)
5157 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5158 return PARSE_OPERAND_FAIL
;
5162 if (inst
.operands
[i
].negative
)
5164 inst
.operands
[i
].negative
= 0;
5167 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5168 return PARSE_OPERAND_FAIL
;
5173 /* If at this point neither .preind nor .postind is set, we have a
5174 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5175 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5177 inst
.operands
[i
].preind
= 1;
5178 inst
.reloc
.exp
.X_op
= O_constant
;
5179 inst
.reloc
.exp
.X_add_number
= 0;
5182 return PARSE_OPERAND_SUCCESS
;
5186 parse_address (char **str
, int i
)
5188 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5192 static parse_operand_result
5193 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5195 return parse_address_main (str
, i
, 1, type
);
5198 /* Parse an operand for a MOVW or MOVT instruction. */
5200 parse_half (char **str
)
5205 skip_past_char (&p
, '#');
5206 if (strncasecmp (p
, ":lower16:", 9) == 0)
5207 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5208 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5209 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5211 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5214 skip_whitespace (p
);
5217 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5220 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5222 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5224 inst
.error
= _("constant expression expected");
5227 if (inst
.reloc
.exp
.X_add_number
< 0
5228 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5230 inst
.error
= _("immediate value out of range");
5238 /* Miscellaneous. */
5240 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5241 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5243 parse_psr (char **str
)
5246 unsigned long psr_field
;
5247 const struct asm_psr
*psr
;
5250 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5251 feature for ease of use and backwards compatibility. */
5253 if (strncasecmp (p
, "SPSR", 4) == 0)
5254 psr_field
= SPSR_BIT
;
5255 else if (strncasecmp (p
, "CPSR", 4) == 0)
5262 while (ISALNUM (*p
) || *p
== '_');
5264 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5276 /* A suffix follows. */
5282 while (ISALNUM (*p
) || *p
== '_');
5284 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5289 psr_field
|= psr
->field
;
5294 goto error
; /* Garbage after "[CS]PSR". */
5296 psr_field
|= (PSR_c
| PSR_f
);
5302 inst
.error
= _("flag for {c}psr instruction expected");
5306 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5307 value suitable for splatting into the AIF field of the instruction. */
5310 parse_cps_flags (char **str
)
5319 case '\0': case ',':
5322 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5323 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5324 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5327 inst
.error
= _("unrecognized CPS flag");
5332 if (saw_a_flag
== 0)
5334 inst
.error
= _("missing CPS flags");
5342 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5343 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5346 parse_endian_specifier (char **str
)
5351 if (strncasecmp (s
, "BE", 2))
5353 else if (strncasecmp (s
, "LE", 2))
5357 inst
.error
= _("valid endian specifiers are be or le");
5361 if (ISALNUM (s
[2]) || s
[2] == '_')
5363 inst
.error
= _("valid endian specifiers are be or le");
5368 return little_endian
;
5371 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5372 value suitable for poking into the rotate field of an sxt or sxta
5373 instruction, or FAIL on error. */
5376 parse_ror (char **str
)
5381 if (strncasecmp (s
, "ROR", 3) == 0)
5385 inst
.error
= _("missing rotation field after comma");
5389 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5394 case 0: *str
= s
; return 0x0;
5395 case 8: *str
= s
; return 0x1;
5396 case 16: *str
= s
; return 0x2;
5397 case 24: *str
= s
; return 0x3;
5400 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5405 /* Parse a conditional code (from conds[] below). The value returned is in the
5406 range 0 .. 14, or FAIL. */
5408 parse_cond (char **str
)
5411 const struct asm_cond
*c
;
5413 /* Condition codes are always 2 characters, so matching up to
5414 3 characters is sufficient. */
5419 while (ISALPHA (*q
) && n
< 3)
5421 cond
[n
] = TOLOWER (*q
);
5426 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5429 inst
.error
= _("condition required");
5437 /* Parse an option for a barrier instruction. Returns the encoding for the
5440 parse_barrier (char **str
)
5443 const struct asm_barrier_opt
*o
;
5446 while (ISALPHA (*q
))
5449 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5458 /* Parse the operands of a table branch instruction. Similar to a memory
5461 parse_tb (char **str
)
5466 if (skip_past_char (&p
, '[') == FAIL
)
5468 inst
.error
= _("'[' expected");
5472 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5474 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5477 inst
.operands
[0].reg
= reg
;
5479 if (skip_past_comma (&p
) == FAIL
)
5481 inst
.error
= _("',' expected");
5485 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5487 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5490 inst
.operands
[0].imm
= reg
;
5492 if (skip_past_comma (&p
) == SUCCESS
)
5494 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5496 if (inst
.reloc
.exp
.X_add_number
!= 1)
5498 inst
.error
= _("invalid shift");
5501 inst
.operands
[0].shifted
= 1;
5504 if (skip_past_char (&p
, ']') == FAIL
)
5506 inst
.error
= _("']' expected");
5513 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5514 information on the types the operands can take and how they are encoded.
5515 Up to four operands may be read; this function handles setting the
5516 ".present" field for each read operand itself.
5517 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5518 else returns FAIL. */
5521 parse_neon_mov (char **str
, int *which_operand
)
5523 int i
= *which_operand
, val
;
5524 enum arm_reg_type rtype
;
5526 struct neon_type_el optype
;
5528 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5530 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5531 inst
.operands
[i
].reg
= val
;
5532 inst
.operands
[i
].isscalar
= 1;
5533 inst
.operands
[i
].vectype
= optype
;
5534 inst
.operands
[i
++].present
= 1;
5536 if (skip_past_comma (&ptr
) == FAIL
)
5539 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5542 inst
.operands
[i
].reg
= val
;
5543 inst
.operands
[i
].isreg
= 1;
5544 inst
.operands
[i
].present
= 1;
5546 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5549 /* Cases 0, 1, 2, 3, 5 (D only). */
5550 if (skip_past_comma (&ptr
) == FAIL
)
5553 inst
.operands
[i
].reg
= val
;
5554 inst
.operands
[i
].isreg
= 1;
5555 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5556 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5557 inst
.operands
[i
].isvec
= 1;
5558 inst
.operands
[i
].vectype
= optype
;
5559 inst
.operands
[i
++].present
= 1;
5561 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5563 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5564 Case 13: VMOV <Sd>, <Rm> */
5565 inst
.operands
[i
].reg
= val
;
5566 inst
.operands
[i
].isreg
= 1;
5567 inst
.operands
[i
].present
= 1;
5569 if (rtype
== REG_TYPE_NQ
)
5571 first_error (_("can't use Neon quad register here"));
5574 else if (rtype
!= REG_TYPE_VFS
)
5577 if (skip_past_comma (&ptr
) == FAIL
)
5579 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5581 inst
.operands
[i
].reg
= val
;
5582 inst
.operands
[i
].isreg
= 1;
5583 inst
.operands
[i
].present
= 1;
5586 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5589 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5590 Case 1: VMOV<c><q> <Dd>, <Dm>
5591 Case 8: VMOV.F32 <Sd>, <Sm>
5592 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5594 inst
.operands
[i
].reg
= val
;
5595 inst
.operands
[i
].isreg
= 1;
5596 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5597 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5598 inst
.operands
[i
].isvec
= 1;
5599 inst
.operands
[i
].vectype
= optype
;
5600 inst
.operands
[i
].present
= 1;
5602 if (skip_past_comma (&ptr
) == SUCCESS
)
5607 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5610 inst
.operands
[i
].reg
= val
;
5611 inst
.operands
[i
].isreg
= 1;
5612 inst
.operands
[i
++].present
= 1;
5614 if (skip_past_comma (&ptr
) == FAIL
)
5617 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5620 inst
.operands
[i
].reg
= val
;
5621 inst
.operands
[i
].isreg
= 1;
5622 inst
.operands
[i
++].present
= 1;
5625 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5626 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5627 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5628 Case 10: VMOV.F32 <Sd>, #<imm>
5629 Case 11: VMOV.F64 <Dd>, #<imm> */
5630 inst
.operands
[i
].immisfloat
= 1;
5631 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5632 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5633 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5637 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5641 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5644 inst
.operands
[i
].reg
= val
;
5645 inst
.operands
[i
].isreg
= 1;
5646 inst
.operands
[i
++].present
= 1;
5648 if (skip_past_comma (&ptr
) == FAIL
)
5651 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5653 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5654 inst
.operands
[i
].reg
= val
;
5655 inst
.operands
[i
].isscalar
= 1;
5656 inst
.operands
[i
].present
= 1;
5657 inst
.operands
[i
].vectype
= optype
;
5659 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5661 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5662 inst
.operands
[i
].reg
= val
;
5663 inst
.operands
[i
].isreg
= 1;
5664 inst
.operands
[i
++].present
= 1;
5666 if (skip_past_comma (&ptr
) == FAIL
)
5669 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5672 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5676 inst
.operands
[i
].reg
= val
;
5677 inst
.operands
[i
].isreg
= 1;
5678 inst
.operands
[i
].isvec
= 1;
5679 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5680 inst
.operands
[i
].vectype
= optype
;
5681 inst
.operands
[i
].present
= 1;
5683 if (rtype
== REG_TYPE_VFS
)
5687 if (skip_past_comma (&ptr
) == FAIL
)
5689 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5692 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5695 inst
.operands
[i
].reg
= val
;
5696 inst
.operands
[i
].isreg
= 1;
5697 inst
.operands
[i
].isvec
= 1;
5698 inst
.operands
[i
].issingle
= 1;
5699 inst
.operands
[i
].vectype
= optype
;
5700 inst
.operands
[i
].present
= 1;
5703 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5707 inst
.operands
[i
].reg
= val
;
5708 inst
.operands
[i
].isreg
= 1;
5709 inst
.operands
[i
].isvec
= 1;
5710 inst
.operands
[i
].issingle
= 1;
5711 inst
.operands
[i
].vectype
= optype
;
5712 inst
.operands
[i
++].present
= 1;
5717 first_error (_("parse error"));
5721 /* Successfully parsed the operands. Update args. */
5727 first_error (_("expected comma"));
5731 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5735 /* Use this macro when the operand constraints are different
5736 for ARM and THUMB (e.g. ldrd). */
5737 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5738 ((arm_operand) | ((thumb_operand) << 16))
5740 /* Matcher codes for parse_operands. */
5741 enum operand_parse_code
5743 OP_stop
, /* end of line */
5745 OP_RR
, /* ARM register */
5746 OP_RRnpc
, /* ARM register, not r15 */
5747 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5748 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5749 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5750 OP_RCP
, /* Coprocessor number */
5751 OP_RCN
, /* Coprocessor register */
5752 OP_RF
, /* FPA register */
5753 OP_RVS
, /* VFP single precision register */
5754 OP_RVD
, /* VFP double precision register (0..15) */
5755 OP_RND
, /* Neon double precision register (0..31) */
5756 OP_RNQ
, /* Neon quad precision register */
5757 OP_RVSD
, /* VFP single or double precision register */
5758 OP_RNDQ
, /* Neon double or quad precision register */
5759 OP_RNSDQ
, /* Neon single, double or quad precision register */
5760 OP_RNSC
, /* Neon scalar D[X] */
5761 OP_RVC
, /* VFP control register */
5762 OP_RMF
, /* Maverick F register */
5763 OP_RMD
, /* Maverick D register */
5764 OP_RMFX
, /* Maverick FX register */
5765 OP_RMDX
, /* Maverick DX register */
5766 OP_RMAX
, /* Maverick AX register */
5767 OP_RMDS
, /* Maverick DSPSC register */
5768 OP_RIWR
, /* iWMMXt wR register */
5769 OP_RIWC
, /* iWMMXt wC register */
5770 OP_RIWG
, /* iWMMXt wCG register */
5771 OP_RXA
, /* XScale accumulator register */
5773 OP_REGLST
, /* ARM register list */
5774 OP_VRSLST
, /* VFP single-precision register list */
5775 OP_VRDLST
, /* VFP double-precision register list */
5776 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5777 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5778 OP_NSTRLST
, /* Neon element/structure list */
5780 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5781 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5782 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5783 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5784 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5785 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5786 OP_VMOV
, /* Neon VMOV operands. */
5787 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5788 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5789 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5791 OP_I0
, /* immediate zero */
5792 OP_I7
, /* immediate value 0 .. 7 */
5793 OP_I15
, /* 0 .. 15 */
5794 OP_I16
, /* 1 .. 16 */
5795 OP_I16z
, /* 0 .. 16 */
5796 OP_I31
, /* 0 .. 31 */
5797 OP_I31w
, /* 0 .. 31, optional trailing ! */
5798 OP_I32
, /* 1 .. 32 */
5799 OP_I32z
, /* 0 .. 32 */
5800 OP_I63
, /* 0 .. 63 */
5801 OP_I63s
, /* -64 .. 63 */
5802 OP_I64
, /* 1 .. 64 */
5803 OP_I64z
, /* 0 .. 64 */
5804 OP_I255
, /* 0 .. 255 */
5806 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5807 OP_I7b
, /* 0 .. 7 */
5808 OP_I15b
, /* 0 .. 15 */
5809 OP_I31b
, /* 0 .. 31 */
5811 OP_SH
, /* shifter operand */
5812 OP_SHG
, /* shifter operand with possible group relocation */
5813 OP_ADDR
, /* Memory address expression (any mode) */
5814 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5815 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5816 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5817 OP_EXP
, /* arbitrary expression */
5818 OP_EXPi
, /* same, with optional immediate prefix */
5819 OP_EXPr
, /* same, with optional relocation suffix */
5820 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5822 OP_CPSF
, /* CPS flags */
5823 OP_ENDI
, /* Endianness specifier */
5824 OP_PSR
, /* CPSR/SPSR mask for msr */
5825 OP_COND
, /* conditional code */
5826 OP_TB
, /* Table branch. */
5828 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5829 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5831 OP_RRnpc_I0
, /* ARM register or literal 0 */
5832 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5833 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5834 OP_RF_IF
, /* FPA register or immediate */
5835 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5836 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5838 /* Optional operands. */
5839 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5840 OP_oI31b
, /* 0 .. 31 */
5841 OP_oI32b
, /* 1 .. 32 */
5842 OP_oIffffb
, /* 0 .. 65535 */
5843 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5845 OP_oRR
, /* ARM register */
5846 OP_oRRnpc
, /* ARM register, not the PC */
5847 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5848 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5849 OP_oRND
, /* Optional Neon double precision register */
5850 OP_oRNQ
, /* Optional Neon quad precision register */
5851 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5852 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5853 OP_oSHll
, /* LSL immediate */
5854 OP_oSHar
, /* ASR immediate */
5855 OP_oSHllar
, /* LSL or ASR immediate */
5856 OP_oROR
, /* ROR 0/8/16/24 */
5857 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5859 /* Some pre-defined mixed (ARM/THUMB) operands. */
5860 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5861 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5862 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5864 OP_FIRST_OPTIONAL
= OP_oI7b
5867 /* Generic instruction operand parser. This does no encoding and no
5868 semantic validation; it merely squirrels values away in the inst
5869 structure. Returns SUCCESS or FAIL depending on whether the
5870 specified grammar matched. */
5872 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5874 unsigned const int *upat
= pattern
;
5875 char *backtrack_pos
= 0;
5876 const char *backtrack_error
= 0;
5877 int i
, val
, backtrack_index
= 0;
5878 enum arm_reg_type rtype
;
5879 parse_operand_result result
;
5880 unsigned int op_parse_code
;
5882 #define po_char_or_fail(chr) \
5885 if (skip_past_char (&str, chr) == FAIL) \
5890 #define po_reg_or_fail(regtype) \
5893 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5894 & inst.operands[i].vectype); \
5897 first_error (_(reg_expected_msgs[regtype])); \
5900 inst.operands[i].reg = val; \
5901 inst.operands[i].isreg = 1; \
5902 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5903 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5904 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5905 || rtype == REG_TYPE_VFD \
5906 || rtype == REG_TYPE_NQ); \
5910 #define po_reg_or_goto(regtype, label) \
5913 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5914 & inst.operands[i].vectype); \
5918 inst.operands[i].reg = val; \
5919 inst.operands[i].isreg = 1; \
5920 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5921 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5922 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5923 || rtype == REG_TYPE_VFD \
5924 || rtype == REG_TYPE_NQ); \
5928 #define po_imm_or_fail(min, max, popt) \
5931 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5933 inst.operands[i].imm = val; \
5937 #define po_scalar_or_goto(elsz, label) \
5940 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5943 inst.operands[i].reg = val; \
5944 inst.operands[i].isscalar = 1; \
5948 #define po_misc_or_fail(expr) \
5956 #define po_misc_or_fail_no_backtrack(expr) \
5960 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
5961 backtrack_pos = 0; \
5962 if (result != PARSE_OPERAND_SUCCESS) \
5967 skip_whitespace (str
);
5969 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5971 op_parse_code
= upat
[i
];
5972 if (op_parse_code
>= 1<<16)
5973 op_parse_code
= thumb
? (op_parse_code
>> 16)
5974 : (op_parse_code
& ((1<<16)-1));
5976 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
5978 /* Remember where we are in case we need to backtrack. */
5979 gas_assert (!backtrack_pos
);
5980 backtrack_pos
= str
;
5981 backtrack_error
= inst
.error
;
5982 backtrack_index
= i
;
5985 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5986 po_char_or_fail (',');
5988 switch (op_parse_code
)
5996 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5997 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5998 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5999 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6000 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6001 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6003 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6005 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6007 /* Also accept generic coprocessor regs for unknown registers. */
6009 po_reg_or_fail (REG_TYPE_CN
);
6011 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6012 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6013 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6014 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6015 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6016 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6017 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6018 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6019 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6020 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6022 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6024 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6025 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6027 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6029 /* Neon scalar. Using an element size of 8 means that some invalid
6030 scalars are accepted here, so deal with those in later code. */
6031 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6035 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6038 po_imm_or_fail (0, 0, TRUE
);
6043 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6048 po_scalar_or_goto (8, try_rr
);
6051 po_reg_or_fail (REG_TYPE_RN
);
6057 po_scalar_or_goto (8, try_nsdq
);
6060 po_reg_or_fail (REG_TYPE_NSDQ
);
6066 po_scalar_or_goto (8, try_ndq
);
6069 po_reg_or_fail (REG_TYPE_NDQ
);
6075 po_scalar_or_goto (8, try_vfd
);
6078 po_reg_or_fail (REG_TYPE_VFD
);
6083 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6084 not careful then bad things might happen. */
6085 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6090 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6093 /* There's a possibility of getting a 64-bit immediate here, so
6094 we need special handling. */
6095 if (parse_big_immediate (&str
, i
) == FAIL
)
6097 inst
.error
= _("immediate value is out of range");
6105 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6108 po_imm_or_fail (0, 63, TRUE
);
6113 po_char_or_fail ('[');
6114 po_reg_or_fail (REG_TYPE_RN
);
6115 po_char_or_fail (']');
6120 po_reg_or_fail (REG_TYPE_RN
);
6121 if (skip_past_char (&str
, '!') == SUCCESS
)
6122 inst
.operands
[i
].writeback
= 1;
6126 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6127 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6128 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6129 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6130 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6131 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6132 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6133 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6134 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6135 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6136 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6137 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6139 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6141 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6142 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6144 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6145 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6146 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6148 /* Immediate variants */
6150 po_char_or_fail ('{');
6151 po_imm_or_fail (0, 255, TRUE
);
6152 po_char_or_fail ('}');
6156 /* The expression parser chokes on a trailing !, so we have
6157 to find it first and zap it. */
6160 while (*s
&& *s
!= ',')
6165 inst
.operands
[i
].writeback
= 1;
6167 po_imm_or_fail (0, 31, TRUE
);
6175 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6180 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6185 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6187 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6189 val
= parse_reloc (&str
);
6192 inst
.error
= _("unrecognized relocation suffix");
6195 else if (val
!= BFD_RELOC_UNUSED
)
6197 inst
.operands
[i
].imm
= val
;
6198 inst
.operands
[i
].hasreloc
= 1;
6203 /* Operand for MOVW or MOVT. */
6205 po_misc_or_fail (parse_half (&str
));
6208 /* Register or expression. */
6209 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6210 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6212 /* Register or immediate. */
6213 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6214 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6216 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6218 if (!is_immediate_prefix (*str
))
6221 val
= parse_fpa_immediate (&str
);
6224 /* FPA immediates are encoded as registers 8-15.
6225 parse_fpa_immediate has already applied the offset. */
6226 inst
.operands
[i
].reg
= val
;
6227 inst
.operands
[i
].isreg
= 1;
6230 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6231 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6233 /* Two kinds of register. */
6236 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6238 || (rege
->type
!= REG_TYPE_MMXWR
6239 && rege
->type
!= REG_TYPE_MMXWC
6240 && rege
->type
!= REG_TYPE_MMXWCG
))
6242 inst
.error
= _("iWMMXt data or control register expected");
6245 inst
.operands
[i
].reg
= rege
->number
;
6246 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6252 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6254 || (rege
->type
!= REG_TYPE_MMXWC
6255 && rege
->type
!= REG_TYPE_MMXWCG
))
6257 inst
.error
= _("iWMMXt control register expected");
6260 inst
.operands
[i
].reg
= rege
->number
;
6261 inst
.operands
[i
].isreg
= 1;
6266 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6267 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6268 case OP_oROR
: val
= parse_ror (&str
); break;
6269 case OP_PSR
: val
= parse_psr (&str
); break;
6270 case OP_COND
: val
= parse_cond (&str
); break;
6271 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
6274 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6275 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6278 val
= parse_psr (&str
);
6282 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6285 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6287 if (strncasecmp (str
, "APSR_", 5) == 0)
6294 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6295 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6296 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6297 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6298 default: found
= 16;
6302 inst
.operands
[i
].isvec
= 1;
6303 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6304 inst
.operands
[i
].reg
= REG_PC
;
6311 po_misc_or_fail (parse_tb (&str
));
6314 /* Register lists. */
6316 val
= parse_reg_list (&str
);
6319 inst
.operands
[1].writeback
= 1;
6325 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6329 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6333 /* Allow Q registers too. */
6334 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6339 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6341 inst
.operands
[i
].issingle
= 1;
6346 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6351 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6352 &inst
.operands
[i
].vectype
);
6355 /* Addressing modes */
6357 po_misc_or_fail (parse_address (&str
, i
));
6361 po_misc_or_fail_no_backtrack (
6362 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6366 po_misc_or_fail_no_backtrack (
6367 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6371 po_misc_or_fail_no_backtrack (
6372 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6376 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6380 po_misc_or_fail_no_backtrack (
6381 parse_shifter_operand_group_reloc (&str
, i
));
6385 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6389 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6393 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6397 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6400 /* Various value-based sanity checks and shared operations. We
6401 do not signal immediate failures for the register constraints;
6402 this allows a syntax error to take precedence. */
6403 switch (op_parse_code
)
6411 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6412 inst
.error
= BAD_PC
;
6417 if (inst
.operands
[i
].isreg
)
6419 if (inst
.operands
[i
].reg
== REG_PC
)
6420 inst
.error
= BAD_PC
;
6421 else if (inst
.operands
[i
].reg
== REG_SP
)
6422 inst
.error
= BAD_SP
;
6441 inst
.operands
[i
].imm
= val
;
6448 /* If we get here, this operand was successfully parsed. */
6449 inst
.operands
[i
].present
= 1;
6453 inst
.error
= BAD_ARGS
;
6458 /* The parse routine should already have set inst.error, but set a
6459 default here just in case. */
6461 inst
.error
= _("syntax error");
6465 /* Do not backtrack over a trailing optional argument that
6466 absorbed some text. We will only fail again, with the
6467 'garbage following instruction' error message, which is
6468 probably less helpful than the current one. */
6469 if (backtrack_index
== i
&& backtrack_pos
!= str
6470 && upat
[i
+1] == OP_stop
)
6473 inst
.error
= _("syntax error");
6477 /* Try again, skipping the optional argument at backtrack_pos. */
6478 str
= backtrack_pos
;
6479 inst
.error
= backtrack_error
;
6480 inst
.operands
[backtrack_index
].present
= 0;
6481 i
= backtrack_index
;
6485 /* Check that we have parsed all the arguments. */
6486 if (*str
!= '\0' && !inst
.error
)
6487 inst
.error
= _("garbage following instruction");
6489 return inst
.error
? FAIL
: SUCCESS
;
6492 #undef po_char_or_fail
6493 #undef po_reg_or_fail
6494 #undef po_reg_or_goto
6495 #undef po_imm_or_fail
6496 #undef po_scalar_or_fail
6498 /* Shorthand macro for instruction encoding functions issuing errors. */
6499 #define constraint(expr, err) \
6510 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6511 instructions are unpredictable if these registers are used. This
6512 is the BadReg predicate in ARM's Thumb-2 documentation. */
6513 #define reject_bad_reg(reg) \
6515 if (reg == REG_SP || reg == REG_PC) \
6517 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6522 /* If REG is R13 (the stack pointer), warn that its use is
6524 #define warn_deprecated_sp(reg) \
6526 if (warn_on_deprecated && reg == REG_SP) \
6527 as_warn (_("use of r13 is deprecated")); \
6530 /* Functions for operand encoding. ARM, then Thumb. */
6532 #define rotate_left(v, n) (v << n | v >> (32 - n))
6534 /* If VAL can be encoded in the immediate field of an ARM instruction,
6535 return the encoded form. Otherwise, return FAIL. */
6538 encode_arm_immediate (unsigned int val
)
6542 for (i
= 0; i
< 32; i
+= 2)
6543 if ((a
= rotate_left (val
, i
)) <= 0xff)
6544 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6549 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6550 return the encoded form. Otherwise, return FAIL. */
6552 encode_thumb32_immediate (unsigned int val
)
6559 for (i
= 1; i
<= 24; i
++)
6562 if ((val
& ~(0xff << i
)) == 0)
6563 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6567 if (val
== ((a
<< 16) | a
))
6569 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6573 if (val
== ((a
<< 16) | a
))
6574 return 0x200 | (a
>> 8);
6578 /* Encode a VFP SP or DP register number into inst.instruction. */
6581 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6583 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6586 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6589 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6592 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6597 first_error (_("D register out of range for selected VFP version"));
6605 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6609 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6613 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6617 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6621 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6625 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6633 /* Encode a <shift> in an ARM-format instruction. The immediate,
6634 if any, is handled by md_apply_fix. */
6636 encode_arm_shift (int i
)
6638 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6639 inst
.instruction
|= SHIFT_ROR
<< 5;
6642 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6643 if (inst
.operands
[i
].immisreg
)
6645 inst
.instruction
|= SHIFT_BY_REG
;
6646 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6649 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6654 encode_arm_shifter_operand (int i
)
6656 if (inst
.operands
[i
].isreg
)
6658 inst
.instruction
|= inst
.operands
[i
].reg
;
6659 encode_arm_shift (i
);
6662 inst
.instruction
|= INST_IMMEDIATE
;
6665 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6667 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6669 gas_assert (inst
.operands
[i
].isreg
);
6670 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6672 if (inst
.operands
[i
].preind
)
6676 inst
.error
= _("instruction does not accept preindexed addressing");
6679 inst
.instruction
|= PRE_INDEX
;
6680 if (inst
.operands
[i
].writeback
)
6681 inst
.instruction
|= WRITE_BACK
;
6684 else if (inst
.operands
[i
].postind
)
6686 gas_assert (inst
.operands
[i
].writeback
);
6688 inst
.instruction
|= WRITE_BACK
;
6690 else /* unindexed - only for coprocessor */
6692 inst
.error
= _("instruction does not accept unindexed addressing");
6696 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6697 && (((inst
.instruction
& 0x000f0000) >> 16)
6698 == ((inst
.instruction
& 0x0000f000) >> 12)))
6699 as_warn ((inst
.instruction
& LOAD_BIT
)
6700 ? _("destination register same as write-back base")
6701 : _("source register same as write-back base"));
6704 /* inst.operands[i] was set up by parse_address. Encode it into an
6705 ARM-format mode 2 load or store instruction. If is_t is true,
6706 reject forms that cannot be used with a T instruction (i.e. not
6709 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6711 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6713 encode_arm_addr_mode_common (i
, is_t
);
6715 if (inst
.operands
[i
].immisreg
)
6717 constraint ((inst
.operands
[i
].imm
== REG_PC
6718 || (is_pc
&& inst
.operands
[i
].writeback
)),
6720 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6721 inst
.instruction
|= inst
.operands
[i
].imm
;
6722 if (!inst
.operands
[i
].negative
)
6723 inst
.instruction
|= INDEX_UP
;
6724 if (inst
.operands
[i
].shifted
)
6726 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6727 inst
.instruction
|= SHIFT_ROR
<< 5;
6730 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6731 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6735 else /* immediate offset in inst.reloc */
6737 if (is_pc
&& !inst
.reloc
.pc_rel
)
6739 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6740 /* BAD_PC_ADDRESSING Condition =
6742 which becomes !is_load || is_t. */
6743 constraint ((!is_load
|| is_t
),
6747 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6748 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6752 /* inst.operands[i] was set up by parse_address. Encode it into an
6753 ARM-format mode 3 load or store instruction. Reject forms that
6754 cannot be used with such instructions. If is_t is true, reject
6755 forms that cannot be used with a T instruction (i.e. not
6758 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6760 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6762 inst
.error
= _("instruction does not accept scaled register index");
6766 encode_arm_addr_mode_common (i
, is_t
);
6768 if (inst
.operands
[i
].immisreg
)
6770 constraint ((inst
.operands
[i
].imm
== REG_PC
6771 || inst
.operands
[i
].reg
== REG_PC
),
6773 inst
.instruction
|= inst
.operands
[i
].imm
;
6774 if (!inst
.operands
[i
].negative
)
6775 inst
.instruction
|= INDEX_UP
;
6777 else /* immediate offset in inst.reloc */
6779 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6780 && inst
.operands
[i
].writeback
),
6782 inst
.instruction
|= HWOFFSET_IMM
;
6783 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6784 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6788 /* inst.operands[i] was set up by parse_address. Encode it into an
6789 ARM-format instruction. Reject all forms which cannot be encoded
6790 into a coprocessor load/store instruction. If wb_ok is false,
6791 reject use of writeback; if unind_ok is false, reject use of
6792 unindexed addressing. If reloc_override is not 0, use it instead
6793 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6794 (in which case it is preserved). */
6797 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6799 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6801 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6803 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6805 gas_assert (!inst
.operands
[i
].writeback
);
6808 inst
.error
= _("instruction does not support unindexed addressing");
6811 inst
.instruction
|= inst
.operands
[i
].imm
;
6812 inst
.instruction
|= INDEX_UP
;
6816 if (inst
.operands
[i
].preind
)
6817 inst
.instruction
|= PRE_INDEX
;
6819 if (inst
.operands
[i
].writeback
)
6821 if (inst
.operands
[i
].reg
== REG_PC
)
6823 inst
.error
= _("pc may not be used with write-back");
6828 inst
.error
= _("instruction does not support writeback");
6831 inst
.instruction
|= WRITE_BACK
;
6835 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6836 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6837 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6838 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6841 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6843 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6849 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6850 Determine whether it can be performed with a move instruction; if
6851 it can, convert inst.instruction to that move instruction and
6852 return TRUE; if it can't, convert inst.instruction to a literal-pool
6853 load and return FALSE. If this is not a valid thing to do in the
6854 current context, set inst.error and return TRUE.
6856 inst.operands[i] describes the destination register. */
6859 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6864 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6868 if ((inst
.instruction
& tbit
) == 0)
6870 inst
.error
= _("invalid pseudo operation");
6873 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6875 inst
.error
= _("constant expression expected");
6878 if (inst
.reloc
.exp
.X_op
== O_constant
)
6882 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6884 /* This can be done with a mov(1) instruction. */
6885 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6886 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6892 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6895 /* This can be done with a mov instruction. */
6896 inst
.instruction
&= LITERAL_MASK
;
6897 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6898 inst
.instruction
|= value
& 0xfff;
6902 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6905 /* This can be done with a mvn instruction. */
6906 inst
.instruction
&= LITERAL_MASK
;
6907 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6908 inst
.instruction
|= value
& 0xfff;
6914 if (add_to_lit_pool () == FAIL
)
6916 inst
.error
= _("literal pool insertion failed");
6919 inst
.operands
[1].reg
= REG_PC
;
6920 inst
.operands
[1].isreg
= 1;
6921 inst
.operands
[1].preind
= 1;
6922 inst
.reloc
.pc_rel
= 1;
6923 inst
.reloc
.type
= (thumb_p
6924 ? BFD_RELOC_ARM_THUMB_OFFSET
6926 ? BFD_RELOC_ARM_HWLITERAL
6927 : BFD_RELOC_ARM_LITERAL
));
6931 /* Functions for instruction encoding, sorted by sub-architecture.
6932 First some generics; their names are taken from the conventional
6933 bit positions for register arguments in ARM format instructions. */
6943 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6950 inst
.instruction
|= inst
.operands
[1].reg
;
6956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6957 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6963 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6964 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6970 unsigned Rn
= inst
.operands
[2].reg
;
6971 /* Enforce restrictions on SWP instruction. */
6972 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6973 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6974 _("Rn must not overlap other operands"));
6975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6976 inst
.instruction
|= inst
.operands
[1].reg
;
6977 inst
.instruction
|= Rn
<< 16;
6983 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6984 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6985 inst
.instruction
|= inst
.operands
[2].reg
;
6991 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
6992 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
6993 && inst
.reloc
.exp
.X_op
!= O_illegal
)
6994 || inst
.reloc
.exp
.X_add_number
!= 0),
6996 inst
.instruction
|= inst
.operands
[0].reg
;
6997 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6998 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7004 inst
.instruction
|= inst
.operands
[0].imm
;
7010 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7011 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7014 /* ARM instructions, in alphabetical order by function name (except
7015 that wrapper functions appear immediately after the function they
7018 /* This is a pseudo-op of the form "adr rd, label" to be converted
7019 into a relative address of the form "add rd, pc, #label-.-8". */
7024 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7026 /* Frag hacking will turn this into a sub instruction if the offset turns
7027 out to be negative. */
7028 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7029 inst
.reloc
.pc_rel
= 1;
7030 inst
.reloc
.exp
.X_add_number
-= 8;
7033 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7034 into a relative address of the form:
7035 add rd, pc, #low(label-.-8)"
7036 add rd, rd, #high(label-.-8)" */
7041 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7043 /* Frag hacking will turn this into a sub instruction if the offset turns
7044 out to be negative. */
7045 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7046 inst
.reloc
.pc_rel
= 1;
7047 inst
.size
= INSN_SIZE
* 2;
7048 inst
.reloc
.exp
.X_add_number
-= 8;
7054 if (!inst
.operands
[1].present
)
7055 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7057 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7058 encode_arm_shifter_operand (2);
7064 if (inst
.operands
[0].present
)
7066 constraint ((inst
.instruction
& 0xf0) != 0x40
7067 && inst
.operands
[0].imm
!= 0xf,
7068 _("bad barrier type"));
7069 inst
.instruction
|= inst
.operands
[0].imm
;
7072 inst
.instruction
|= 0xf;
7078 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7079 constraint (msb
> 32, _("bit-field extends past end of register"));
7080 /* The instruction encoding stores the LSB and MSB,
7081 not the LSB and width. */
7082 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7083 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7084 inst
.instruction
|= (msb
- 1) << 16;
7092 /* #0 in second position is alternative syntax for bfc, which is
7093 the same instruction but with REG_PC in the Rm field. */
7094 if (!inst
.operands
[1].isreg
)
7095 inst
.operands
[1].reg
= REG_PC
;
7097 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7098 constraint (msb
> 32, _("bit-field extends past end of register"));
7099 /* The instruction encoding stores the LSB and MSB,
7100 not the LSB and width. */
7101 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7102 inst
.instruction
|= inst
.operands
[1].reg
;
7103 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7104 inst
.instruction
|= (msb
- 1) << 16;
7110 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7111 _("bit-field extends past end of register"));
7112 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7113 inst
.instruction
|= inst
.operands
[1].reg
;
7114 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7115 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7118 /* ARM V5 breakpoint instruction (argument parse)
7119 BKPT <16 bit unsigned immediate>
7120 Instruction is not conditional.
7121 The bit pattern given in insns[] has the COND_ALWAYS condition,
7122 and it is an error if the caller tried to override that. */
7127 /* Top 12 of 16 bits to bits 19:8. */
7128 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7130 /* Bottom 4 of 16 bits to bits 3:0. */
7131 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7135 encode_branch (int default_reloc
)
7137 if (inst
.operands
[0].hasreloc
)
7139 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7140 _("the only suffix valid here is '(plt)'"));
7141 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7145 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7147 inst
.reloc
.pc_rel
= 1;
7154 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7155 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7158 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7165 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7167 if (inst
.cond
== COND_ALWAYS
)
7168 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7170 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7174 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7177 /* ARM V5 branch-link-exchange instruction (argument parse)
7178 BLX <target_addr> ie BLX(1)
7179 BLX{<condition>} <Rm> ie BLX(2)
7180 Unfortunately, there are two different opcodes for this mnemonic.
7181 So, the insns[].value is not used, and the code here zaps values
7182 into inst.instruction.
7183 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7188 if (inst
.operands
[0].isreg
)
7190 /* Arg is a register; the opcode provided by insns[] is correct.
7191 It is not illegal to do "blx pc", just useless. */
7192 if (inst
.operands
[0].reg
== REG_PC
)
7193 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7195 inst
.instruction
|= inst
.operands
[0].reg
;
7199 /* Arg is an address; this instruction cannot be executed
7200 conditionally, and the opcode must be adjusted.
7201 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7202 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7203 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7204 inst
.instruction
= 0xfa000000;
7205 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7212 bfd_boolean want_reloc
;
7214 if (inst
.operands
[0].reg
== REG_PC
)
7215 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7217 inst
.instruction
|= inst
.operands
[0].reg
;
7218 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7219 it is for ARMv4t or earlier. */
7220 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7221 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7225 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7230 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7234 /* ARM v5TEJ. Jump to Jazelle code. */
7239 if (inst
.operands
[0].reg
== REG_PC
)
7240 as_tsktsk (_("use of r15 in bxj is not really useful"));
7242 inst
.instruction
|= inst
.operands
[0].reg
;
7245 /* Co-processor data operation:
7246 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7247 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7251 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7252 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7253 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7254 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7255 inst
.instruction
|= inst
.operands
[4].reg
;
7256 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7262 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7263 encode_arm_shifter_operand (1);
7266 /* Transfer between coprocessor and ARM registers.
7267 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7272 No special properties. */
7279 Rd
= inst
.operands
[2].reg
;
7282 if (inst
.instruction
== 0xee000010
7283 || inst
.instruction
== 0xfe000010)
7285 reject_bad_reg (Rd
);
7288 constraint (Rd
== REG_SP
, BAD_SP
);
7293 if (inst
.instruction
== 0xe000010)
7294 constraint (Rd
== REG_PC
, BAD_PC
);
7298 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7299 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7300 inst
.instruction
|= Rd
<< 12;
7301 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7302 inst
.instruction
|= inst
.operands
[4].reg
;
7303 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7306 /* Transfer between coprocessor register and pair of ARM registers.
7307 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7312 Two XScale instructions are special cases of these:
7314 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7315 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7317 Result unpredictable if Rd or Rn is R15. */
7324 Rd
= inst
.operands
[2].reg
;
7325 Rn
= inst
.operands
[3].reg
;
7329 reject_bad_reg (Rd
);
7330 reject_bad_reg (Rn
);
7334 constraint (Rd
== REG_PC
, BAD_PC
);
7335 constraint (Rn
== REG_PC
, BAD_PC
);
7338 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7339 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7340 inst
.instruction
|= Rd
<< 12;
7341 inst
.instruction
|= Rn
<< 16;
7342 inst
.instruction
|= inst
.operands
[4].reg
;
7348 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7349 if (inst
.operands
[1].present
)
7351 inst
.instruction
|= CPSI_MMOD
;
7352 inst
.instruction
|= inst
.operands
[1].imm
;
7359 inst
.instruction
|= inst
.operands
[0].imm
;
7365 /* There is no IT instruction in ARM mode. We
7366 process it to do the validation as if in
7367 thumb mode, just in case the code gets
7368 assembled for thumb using the unified syntax. */
7373 set_it_insn_type (IT_INSN
);
7374 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7375 now_it
.cc
= inst
.operands
[0].imm
;
7382 int base_reg
= inst
.operands
[0].reg
;
7383 int range
= inst
.operands
[1].imm
;
7385 inst
.instruction
|= base_reg
<< 16;
7386 inst
.instruction
|= range
;
7388 if (inst
.operands
[1].writeback
)
7389 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7391 if (inst
.operands
[0].writeback
)
7393 inst
.instruction
|= WRITE_BACK
;
7394 /* Check for unpredictable uses of writeback. */
7395 if (inst
.instruction
& LOAD_BIT
)
7397 /* Not allowed in LDM type 2. */
7398 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7399 && ((range
& (1 << REG_PC
)) == 0))
7400 as_warn (_("writeback of base register is UNPREDICTABLE"));
7401 /* Only allowed if base reg not in list for other types. */
7402 else if (range
& (1 << base_reg
))
7403 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7407 /* Not allowed for type 2. */
7408 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7409 as_warn (_("writeback of base register is UNPREDICTABLE"));
7410 /* Only allowed if base reg not in list, or first in list. */
7411 else if ((range
& (1 << base_reg
))
7412 && (range
& ((1 << base_reg
) - 1)))
7413 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7418 /* ARMv5TE load-consecutive (argument parse)
7427 constraint (inst
.operands
[0].reg
% 2 != 0,
7428 _("first destination register must be even"));
7429 constraint (inst
.operands
[1].present
7430 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7431 _("can only load two consecutive registers"));
7432 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7433 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7435 if (!inst
.operands
[1].present
)
7436 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7438 if (inst
.instruction
& LOAD_BIT
)
7440 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7441 register and the first register written; we have to diagnose
7442 overlap between the base and the second register written here. */
7444 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7445 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7446 as_warn (_("base register written back, and overlaps "
7447 "second destination register"));
7449 /* For an index-register load, the index register must not overlap the
7450 destination (even if not write-back). */
7451 else if (inst
.operands
[2].immisreg
7452 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7453 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7454 as_warn (_("index register overlaps destination register"));
7457 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7458 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7464 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7465 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7466 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7467 || inst
.operands
[1].negative
7468 /* This can arise if the programmer has written
7470 or if they have mistakenly used a register name as the last
7473 It is very difficult to distinguish between these two cases
7474 because "rX" might actually be a label. ie the register
7475 name has been occluded by a symbol of the same name. So we
7476 just generate a general 'bad addressing mode' type error
7477 message and leave it up to the programmer to discover the
7478 true cause and fix their mistake. */
7479 || (inst
.operands
[1].reg
== REG_PC
),
7482 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7483 || inst
.reloc
.exp
.X_add_number
!= 0,
7484 _("offset must be zero in ARM encoding"));
7486 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7488 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7489 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7490 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7496 constraint (inst
.operands
[0].reg
% 2 != 0,
7497 _("even register required"));
7498 constraint (inst
.operands
[1].present
7499 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7500 _("can only load two consecutive registers"));
7501 /* If op 1 were present and equal to PC, this function wouldn't
7502 have been called in the first place. */
7503 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7505 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7506 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7512 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7513 if (!inst
.operands
[1].isreg
)
7514 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7516 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7522 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7524 if (inst
.operands
[1].preind
)
7526 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7527 || inst
.reloc
.exp
.X_add_number
!= 0,
7528 _("this instruction requires a post-indexed address"));
7530 inst
.operands
[1].preind
= 0;
7531 inst
.operands
[1].postind
= 1;
7532 inst
.operands
[1].writeback
= 1;
7534 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7535 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7538 /* Halfword and signed-byte load/store operations. */
7543 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7544 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7545 if (!inst
.operands
[1].isreg
)
7546 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7548 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7554 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7556 if (inst
.operands
[1].preind
)
7558 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7559 || inst
.reloc
.exp
.X_add_number
!= 0,
7560 _("this instruction requires a post-indexed address"));
7562 inst
.operands
[1].preind
= 0;
7563 inst
.operands
[1].postind
= 1;
7564 inst
.operands
[1].writeback
= 1;
7566 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7567 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7570 /* Co-processor register load/store.
7571 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7575 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7576 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7577 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7583 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7584 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7585 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7586 && !(inst
.instruction
& 0x00400000))
7587 as_tsktsk (_("Rd and Rm should be different in mla"));
7589 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7590 inst
.instruction
|= inst
.operands
[1].reg
;
7591 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7592 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7598 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7599 encode_arm_shifter_operand (1);
7602 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7609 top
= (inst
.instruction
& 0x00400000) != 0;
7610 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7611 _(":lower16: not allowed this instruction"));
7612 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7613 _(":upper16: not allowed instruction"));
7614 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7615 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7617 imm
= inst
.reloc
.exp
.X_add_number
;
7618 /* The value is in two pieces: 0:11, 16:19. */
7619 inst
.instruction
|= (imm
& 0x00000fff);
7620 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7624 static void do_vfp_nsyn_opcode (const char *);
7627 do_vfp_nsyn_mrs (void)
7629 if (inst
.operands
[0].isvec
)
7631 if (inst
.operands
[1].reg
!= 1)
7632 first_error (_("operand 1 must be FPSCR"));
7633 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7634 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7635 do_vfp_nsyn_opcode ("fmstat");
7637 else if (inst
.operands
[1].isvec
)
7638 do_vfp_nsyn_opcode ("fmrx");
7646 do_vfp_nsyn_msr (void)
7648 if (inst
.operands
[0].isvec
)
7649 do_vfp_nsyn_opcode ("fmxr");
7659 unsigned Rt
= inst
.operands
[0].reg
;
7661 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7663 inst
.error
= BAD_SP
;
7667 /* APSR_ sets isvec. All other refs to PC are illegal. */
7668 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7670 inst
.error
= BAD_PC
;
7674 if (inst
.operands
[1].reg
!= 1)
7675 first_error (_("operand 1 must be FPSCR"));
7677 inst
.instruction
|= (Rt
<< 12);
7683 unsigned Rt
= inst
.operands
[1].reg
;
7686 reject_bad_reg (Rt
);
7687 else if (Rt
== REG_PC
)
7689 inst
.error
= BAD_PC
;
7693 if (inst
.operands
[0].reg
!= 1)
7694 first_error (_("operand 0 must be FPSCR"));
7696 inst
.instruction
|= (Rt
<< 12);
7702 if (do_vfp_nsyn_mrs () == SUCCESS
)
7705 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7706 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7708 _("'CPSR' or 'SPSR' expected"));
7709 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7710 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7711 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7714 /* Two possible forms:
7715 "{C|S}PSR_<field>, Rm",
7716 "{C|S}PSR_f, #expression". */
7721 if (do_vfp_nsyn_msr () == SUCCESS
)
7724 inst
.instruction
|= inst
.operands
[0].imm
;
7725 if (inst
.operands
[1].isreg
)
7726 inst
.instruction
|= inst
.operands
[1].reg
;
7729 inst
.instruction
|= INST_IMMEDIATE
;
7730 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7731 inst
.reloc
.pc_rel
= 0;
7738 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7740 if (!inst
.operands
[2].present
)
7741 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7742 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7743 inst
.instruction
|= inst
.operands
[1].reg
;
7744 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7746 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7747 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7748 as_tsktsk (_("Rd and Rm should be different in mul"));
7751 /* Long Multiply Parser
7752 UMULL RdLo, RdHi, Rm, Rs
7753 SMULL RdLo, RdHi, Rm, Rs
7754 UMLAL RdLo, RdHi, Rm, Rs
7755 SMLAL RdLo, RdHi, Rm, Rs. */
7760 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7761 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7762 inst
.instruction
|= inst
.operands
[2].reg
;
7763 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7765 /* rdhi and rdlo must be different. */
7766 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7767 as_tsktsk (_("rdhi and rdlo must be different"));
7769 /* rdhi, rdlo and rm must all be different before armv6. */
7770 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7771 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7772 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7773 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7779 if (inst
.operands
[0].present
7780 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7782 /* Architectural NOP hints are CPSR sets with no bits selected. */
7783 inst
.instruction
&= 0xf0000000;
7784 inst
.instruction
|= 0x0320f000;
7785 if (inst
.operands
[0].present
)
7786 inst
.instruction
|= inst
.operands
[0].imm
;
7790 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7791 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7792 Condition defaults to COND_ALWAYS.
7793 Error if Rd, Rn or Rm are R15. */
7798 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7799 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7800 inst
.instruction
|= inst
.operands
[2].reg
;
7801 if (inst
.operands
[3].present
)
7802 encode_arm_shift (3);
7805 /* ARM V6 PKHTB (Argument Parse). */
7810 if (!inst
.operands
[3].present
)
7812 /* If the shift specifier is omitted, turn the instruction
7813 into pkhbt rd, rm, rn. */
7814 inst
.instruction
&= 0xfff00010;
7815 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7816 inst
.instruction
|= inst
.operands
[1].reg
;
7817 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7821 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7822 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7823 inst
.instruction
|= inst
.operands
[2].reg
;
7824 encode_arm_shift (3);
7828 /* ARMv5TE: Preload-Cache
7832 Syntactically, like LDR with B=1, W=0, L=1. */
7837 constraint (!inst
.operands
[0].isreg
,
7838 _("'[' expected after PLD mnemonic"));
7839 constraint (inst
.operands
[0].postind
,
7840 _("post-indexed expression used in preload instruction"));
7841 constraint (inst
.operands
[0].writeback
,
7842 _("writeback used in preload instruction"));
7843 constraint (!inst
.operands
[0].preind
,
7844 _("unindexed addressing used in preload instruction"));
7845 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7848 /* ARMv7: PLI <addr_mode> */
7852 constraint (!inst
.operands
[0].isreg
,
7853 _("'[' expected after PLI mnemonic"));
7854 constraint (inst
.operands
[0].postind
,
7855 _("post-indexed expression used in preload instruction"));
7856 constraint (inst
.operands
[0].writeback
,
7857 _("writeback used in preload instruction"));
7858 constraint (!inst
.operands
[0].preind
,
7859 _("unindexed addressing used in preload instruction"));
7860 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7861 inst
.instruction
&= ~PRE_INDEX
;
7867 inst
.operands
[1] = inst
.operands
[0];
7868 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7869 inst
.operands
[0].isreg
= 1;
7870 inst
.operands
[0].writeback
= 1;
7871 inst
.operands
[0].reg
= REG_SP
;
7875 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7876 word at the specified address and the following word
7878 Unconditionally executed.
7879 Error if Rn is R15. */
7884 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7885 if (inst
.operands
[0].writeback
)
7886 inst
.instruction
|= WRITE_BACK
;
7889 /* ARM V6 ssat (argument parse). */
7894 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7895 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7896 inst
.instruction
|= inst
.operands
[2].reg
;
7898 if (inst
.operands
[3].present
)
7899 encode_arm_shift (3);
7902 /* ARM V6 usat (argument parse). */
7907 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7908 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7909 inst
.instruction
|= inst
.operands
[2].reg
;
7911 if (inst
.operands
[3].present
)
7912 encode_arm_shift (3);
7915 /* ARM V6 ssat16 (argument parse). */
7920 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7921 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7922 inst
.instruction
|= inst
.operands
[2].reg
;
7928 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7929 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7930 inst
.instruction
|= inst
.operands
[2].reg
;
7933 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7934 preserving the other bits.
7936 setend <endian_specifier>, where <endian_specifier> is either
7942 if (inst
.operands
[0].imm
)
7943 inst
.instruction
|= 0x200;
7949 unsigned int Rm
= (inst
.operands
[1].present
7950 ? inst
.operands
[1].reg
7951 : inst
.operands
[0].reg
);
7953 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7954 inst
.instruction
|= Rm
;
7955 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7957 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7958 inst
.instruction
|= SHIFT_BY_REG
;
7961 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7967 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7968 inst
.reloc
.pc_rel
= 0;
7974 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7975 inst
.reloc
.pc_rel
= 0;
7978 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7979 SMLAxy{cond} Rd,Rm,Rs,Rn
7980 SMLAWy{cond} Rd,Rm,Rs,Rn
7981 Error if any register is R15. */
7986 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7987 inst
.instruction
|= inst
.operands
[1].reg
;
7988 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7989 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7992 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7993 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7994 Error if any register is R15.
7995 Warning if Rdlo == Rdhi. */
8000 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8001 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8002 inst
.instruction
|= inst
.operands
[2].reg
;
8003 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8005 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8006 as_tsktsk (_("rdhi and rdlo must be different"));
8009 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8010 SMULxy{cond} Rd,Rm,Rs
8011 Error if any register is R15. */
8016 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8017 inst
.instruction
|= inst
.operands
[1].reg
;
8018 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8021 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8022 the same for both ARM and Thumb-2. */
8029 if (inst
.operands
[0].present
)
8031 reg
= inst
.operands
[0].reg
;
8032 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8037 inst
.instruction
|= reg
<< 16;
8038 inst
.instruction
|= inst
.operands
[1].imm
;
8039 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8040 inst
.instruction
|= WRITE_BACK
;
8043 /* ARM V6 strex (argument parse). */
8048 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8049 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8050 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8051 || inst
.operands
[2].negative
8052 /* See comment in do_ldrex(). */
8053 || (inst
.operands
[2].reg
== REG_PC
),
8056 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8057 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8059 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8060 || inst
.reloc
.exp
.X_add_number
!= 0,
8061 _("offset must be zero in ARM encoding"));
8063 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8064 inst
.instruction
|= inst
.operands
[1].reg
;
8065 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8066 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8072 constraint (inst
.operands
[1].reg
% 2 != 0,
8073 _("even register required"));
8074 constraint (inst
.operands
[2].present
8075 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8076 _("can only store two consecutive registers"));
8077 /* If op 2 were present and equal to PC, this function wouldn't
8078 have been called in the first place. */
8079 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8081 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8082 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8083 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8086 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8087 inst
.instruction
|= inst
.operands
[1].reg
;
8088 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8091 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8092 extends it to 32-bits, and adds the result to a value in another
8093 register. You can specify a rotation by 0, 8, 16, or 24 bits
8094 before extracting the 16-bit value.
8095 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8096 Condition defaults to COND_ALWAYS.
8097 Error if any register uses R15. */
8102 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8103 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8104 inst
.instruction
|= inst
.operands
[2].reg
;
8105 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8110 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8111 Condition defaults to COND_ALWAYS.
8112 Error if any register uses R15. */
8117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8118 inst
.instruction
|= inst
.operands
[1].reg
;
8119 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8122 /* VFP instructions. In a logical order: SP variant first, monad
8123 before dyad, arithmetic then move then load/store. */
8126 do_vfp_sp_monadic (void)
8128 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8129 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8133 do_vfp_sp_dyadic (void)
8135 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8136 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8137 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8141 do_vfp_sp_compare_z (void)
8143 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8147 do_vfp_dp_sp_cvt (void)
8149 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8150 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8154 do_vfp_sp_dp_cvt (void)
8156 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8157 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8161 do_vfp_reg_from_sp (void)
8163 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8164 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8168 do_vfp_reg2_from_sp2 (void)
8170 constraint (inst
.operands
[2].imm
!= 2,
8171 _("only two consecutive VFP SP registers allowed here"));
8172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8173 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8174 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8178 do_vfp_sp_from_reg (void)
8180 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8181 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8185 do_vfp_sp2_from_reg2 (void)
8187 constraint (inst
.operands
[0].imm
!= 2,
8188 _("only two consecutive VFP SP registers allowed here"));
8189 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8190 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8191 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8195 do_vfp_sp_ldst (void)
8197 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8198 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8202 do_vfp_dp_ldst (void)
8204 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8205 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8210 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8212 if (inst
.operands
[0].writeback
)
8213 inst
.instruction
|= WRITE_BACK
;
8215 constraint (ldstm_type
!= VFP_LDSTMIA
,
8216 _("this addressing mode requires base-register writeback"));
8217 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8218 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8219 inst
.instruction
|= inst
.operands
[1].imm
;
8223 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8227 if (inst
.operands
[0].writeback
)
8228 inst
.instruction
|= WRITE_BACK
;
8230 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8231 _("this addressing mode requires base-register writeback"));
8233 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8234 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8236 count
= inst
.operands
[1].imm
<< 1;
8237 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8240 inst
.instruction
|= count
;
8244 do_vfp_sp_ldstmia (void)
8246 vfp_sp_ldstm (VFP_LDSTMIA
);
8250 do_vfp_sp_ldstmdb (void)
8252 vfp_sp_ldstm (VFP_LDSTMDB
);
8256 do_vfp_dp_ldstmia (void)
8258 vfp_dp_ldstm (VFP_LDSTMIA
);
8262 do_vfp_dp_ldstmdb (void)
8264 vfp_dp_ldstm (VFP_LDSTMDB
);
8268 do_vfp_xp_ldstmia (void)
8270 vfp_dp_ldstm (VFP_LDSTMIAX
);
8274 do_vfp_xp_ldstmdb (void)
8276 vfp_dp_ldstm (VFP_LDSTMDBX
);
8280 do_vfp_dp_rd_rm (void)
8282 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8283 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8287 do_vfp_dp_rn_rd (void)
8289 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8290 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8294 do_vfp_dp_rd_rn (void)
8296 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8297 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8301 do_vfp_dp_rd_rn_rm (void)
8303 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8304 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8305 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8311 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8315 do_vfp_dp_rm_rd_rn (void)
8317 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8318 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8319 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8322 /* VFPv3 instructions. */
8324 do_vfp_sp_const (void)
8326 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8327 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8328 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8332 do_vfp_dp_const (void)
8334 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8335 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8336 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8340 vfp_conv (int srcsize
)
8342 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8343 inst
.instruction
|= (immbits
& 1) << 5;
8344 inst
.instruction
|= (immbits
>> 1);
8348 do_vfp_sp_conv_16 (void)
8350 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8355 do_vfp_dp_conv_16 (void)
8357 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8362 do_vfp_sp_conv_32 (void)
8364 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8369 do_vfp_dp_conv_32 (void)
8371 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8375 /* FPA instructions. Also in a logical order. */
8380 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8381 inst
.instruction
|= inst
.operands
[1].reg
;
8385 do_fpa_ldmstm (void)
8387 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8388 switch (inst
.operands
[1].imm
)
8390 case 1: inst
.instruction
|= CP_T_X
; break;
8391 case 2: inst
.instruction
|= CP_T_Y
; break;
8392 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8397 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8399 /* The instruction specified "ea" or "fd", so we can only accept
8400 [Rn]{!}. The instruction does not really support stacking or
8401 unstacking, so we have to emulate these by setting appropriate
8402 bits and offsets. */
8403 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8404 || inst
.reloc
.exp
.X_add_number
!= 0,
8405 _("this instruction does not support indexing"));
8407 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8408 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8410 if (!(inst
.instruction
& INDEX_UP
))
8411 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8413 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8415 inst
.operands
[2].preind
= 0;
8416 inst
.operands
[2].postind
= 1;
8420 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8423 /* iWMMXt instructions: strictly in alphabetical order. */
8426 do_iwmmxt_tandorc (void)
8428 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8432 do_iwmmxt_textrc (void)
8434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8435 inst
.instruction
|= inst
.operands
[1].imm
;
8439 do_iwmmxt_textrm (void)
8441 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8442 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8443 inst
.instruction
|= inst
.operands
[2].imm
;
8447 do_iwmmxt_tinsr (void)
8449 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8450 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8451 inst
.instruction
|= inst
.operands
[2].imm
;
8455 do_iwmmxt_tmia (void)
8457 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8458 inst
.instruction
|= inst
.operands
[1].reg
;
8459 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8463 do_iwmmxt_waligni (void)
8465 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8466 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8467 inst
.instruction
|= inst
.operands
[2].reg
;
8468 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8472 do_iwmmxt_wmerge (void)
8474 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8475 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8476 inst
.instruction
|= inst
.operands
[2].reg
;
8477 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8481 do_iwmmxt_wmov (void)
8483 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8484 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8485 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8486 inst
.instruction
|= inst
.operands
[1].reg
;
8490 do_iwmmxt_wldstbh (void)
8493 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8495 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8497 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8498 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8502 do_iwmmxt_wldstw (void)
8504 /* RIWR_RIWC clears .isreg for a control register. */
8505 if (!inst
.operands
[0].isreg
)
8507 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8508 inst
.instruction
|= 0xf0000000;
8511 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8512 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8516 do_iwmmxt_wldstd (void)
8518 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8519 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8520 && inst
.operands
[1].immisreg
)
8522 inst
.instruction
&= ~0x1a000ff;
8523 inst
.instruction
|= (0xf << 28);
8524 if (inst
.operands
[1].preind
)
8525 inst
.instruction
|= PRE_INDEX
;
8526 if (!inst
.operands
[1].negative
)
8527 inst
.instruction
|= INDEX_UP
;
8528 if (inst
.operands
[1].writeback
)
8529 inst
.instruction
|= WRITE_BACK
;
8530 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8531 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8532 inst
.instruction
|= inst
.operands
[1].imm
;
8535 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8539 do_iwmmxt_wshufh (void)
8541 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8542 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8543 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8544 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8548 do_iwmmxt_wzero (void)
8550 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8551 inst
.instruction
|= inst
.operands
[0].reg
;
8552 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8553 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8557 do_iwmmxt_wrwrwr_or_imm5 (void)
8559 if (inst
.operands
[2].isreg
)
8562 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8563 _("immediate operand requires iWMMXt2"));
8565 if (inst
.operands
[2].imm
== 0)
8567 switch ((inst
.instruction
>> 20) & 0xf)
8573 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8574 inst
.operands
[2].imm
= 16;
8575 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8581 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8582 inst
.operands
[2].imm
= 32;
8583 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8590 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8592 wrn
= (inst
.instruction
>> 16) & 0xf;
8593 inst
.instruction
&= 0xff0fff0f;
8594 inst
.instruction
|= wrn
;
8595 /* Bail out here; the instruction is now assembled. */
8600 /* Map 32 -> 0, etc. */
8601 inst
.operands
[2].imm
&= 0x1f;
8602 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8606 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8607 operations first, then control, shift, and load/store. */
8609 /* Insns like "foo X,Y,Z". */
8612 do_mav_triple (void)
8614 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8615 inst
.instruction
|= inst
.operands
[1].reg
;
8616 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8619 /* Insns like "foo W,X,Y,Z".
8620 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8625 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8626 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8627 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8628 inst
.instruction
|= inst
.operands
[3].reg
;
8631 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8635 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8638 /* Maverick shift immediate instructions.
8639 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8640 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8645 int imm
= inst
.operands
[2].imm
;
8647 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8648 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8650 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8651 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8652 Bit 4 should be 0. */
8653 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8655 inst
.instruction
|= imm
;
8658 /* XScale instructions. Also sorted arithmetic before move. */
8660 /* Xscale multiply-accumulate (argument parse)
8663 MIAxycc acc0,Rm,Rs. */
8668 inst
.instruction
|= inst
.operands
[1].reg
;
8669 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8672 /* Xscale move-accumulator-register (argument parse)
8674 MARcc acc0,RdLo,RdHi. */
8679 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8680 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8683 /* Xscale move-register-accumulator (argument parse)
8685 MRAcc RdLo,RdHi,acc0. */
8690 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8691 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8692 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8695 /* Encoding functions relevant only to Thumb. */
8697 /* inst.operands[i] is a shifted-register operand; encode
8698 it into inst.instruction in the format used by Thumb32. */
8701 encode_thumb32_shifted_operand (int i
)
8703 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8704 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8706 constraint (inst
.operands
[i
].immisreg
,
8707 _("shift by register not allowed in thumb mode"));
8708 inst
.instruction
|= inst
.operands
[i
].reg
;
8709 if (shift
== SHIFT_RRX
)
8710 inst
.instruction
|= SHIFT_ROR
<< 4;
8713 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8714 _("expression too complex"));
8716 constraint (value
> 32
8717 || (value
== 32 && (shift
== SHIFT_LSL
8718 || shift
== SHIFT_ROR
)),
8719 _("shift expression is too large"));
8723 else if (value
== 32)
8726 inst
.instruction
|= shift
<< 4;
8727 inst
.instruction
|= (value
& 0x1c) << 10;
8728 inst
.instruction
|= (value
& 0x03) << 6;
8733 /* inst.operands[i] was set up by parse_address. Encode it into a
8734 Thumb32 format load or store instruction. Reject forms that cannot
8735 be used with such instructions. If is_t is true, reject forms that
8736 cannot be used with a T instruction; if is_d is true, reject forms
8737 that cannot be used with a D instruction. If it is a store insn,
8741 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8743 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8745 constraint (!inst
.operands
[i
].isreg
,
8746 _("Instruction does not support =N addresses"));
8748 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8749 if (inst
.operands
[i
].immisreg
)
8751 constraint (is_pc
, BAD_PC_ADDRESSING
);
8752 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8753 constraint (inst
.operands
[i
].negative
,
8754 _("Thumb does not support negative register indexing"));
8755 constraint (inst
.operands
[i
].postind
,
8756 _("Thumb does not support register post-indexing"));
8757 constraint (inst
.operands
[i
].writeback
,
8758 _("Thumb does not support register indexing with writeback"));
8759 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8760 _("Thumb supports only LSL in shifted register indexing"));
8762 inst
.instruction
|= inst
.operands
[i
].imm
;
8763 if (inst
.operands
[i
].shifted
)
8765 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8766 _("expression too complex"));
8767 constraint (inst
.reloc
.exp
.X_add_number
< 0
8768 || inst
.reloc
.exp
.X_add_number
> 3,
8769 _("shift out of range"));
8770 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8772 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8774 else if (inst
.operands
[i
].preind
)
8776 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8777 constraint (is_t
&& inst
.operands
[i
].writeback
,
8778 _("cannot use writeback with this instruction"));
8779 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8780 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8784 inst
.instruction
|= 0x01000000;
8785 if (inst
.operands
[i
].writeback
)
8786 inst
.instruction
|= 0x00200000;
8790 inst
.instruction
|= 0x00000c00;
8791 if (inst
.operands
[i
].writeback
)
8792 inst
.instruction
|= 0x00000100;
8794 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8796 else if (inst
.operands
[i
].postind
)
8798 gas_assert (inst
.operands
[i
].writeback
);
8799 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8800 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8803 inst
.instruction
|= 0x00200000;
8805 inst
.instruction
|= 0x00000900;
8806 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8808 else /* unindexed - only for coprocessor */
8809 inst
.error
= _("instruction does not accept unindexed addressing");
8812 /* Table of Thumb instructions which exist in both 16- and 32-bit
8813 encodings (the latter only in post-V6T2 cores). The index is the
8814 value used in the insns table below. When there is more than one
8815 possible 16-bit encoding for the instruction, this table always
8817 Also contains several pseudo-instructions used during relaxation. */
8818 #define T16_32_TAB \
8819 X(_adc, 4140, eb400000), \
8820 X(_adcs, 4140, eb500000), \
8821 X(_add, 1c00, eb000000), \
8822 X(_adds, 1c00, eb100000), \
8823 X(_addi, 0000, f1000000), \
8824 X(_addis, 0000, f1100000), \
8825 X(_add_pc,000f, f20f0000), \
8826 X(_add_sp,000d, f10d0000), \
8827 X(_adr, 000f, f20f0000), \
8828 X(_and, 4000, ea000000), \
8829 X(_ands, 4000, ea100000), \
8830 X(_asr, 1000, fa40f000), \
8831 X(_asrs, 1000, fa50f000), \
8832 X(_b, e000, f000b000), \
8833 X(_bcond, d000, f0008000), \
8834 X(_bic, 4380, ea200000), \
8835 X(_bics, 4380, ea300000), \
8836 X(_cmn, 42c0, eb100f00), \
8837 X(_cmp, 2800, ebb00f00), \
8838 X(_cpsie, b660, f3af8400), \
8839 X(_cpsid, b670, f3af8600), \
8840 X(_cpy, 4600, ea4f0000), \
8841 X(_dec_sp,80dd, f1ad0d00), \
8842 X(_eor, 4040, ea800000), \
8843 X(_eors, 4040, ea900000), \
8844 X(_inc_sp,00dd, f10d0d00), \
8845 X(_ldmia, c800, e8900000), \
8846 X(_ldr, 6800, f8500000), \
8847 X(_ldrb, 7800, f8100000), \
8848 X(_ldrh, 8800, f8300000), \
8849 X(_ldrsb, 5600, f9100000), \
8850 X(_ldrsh, 5e00, f9300000), \
8851 X(_ldr_pc,4800, f85f0000), \
8852 X(_ldr_pc2,4800, f85f0000), \
8853 X(_ldr_sp,9800, f85d0000), \
8854 X(_lsl, 0000, fa00f000), \
8855 X(_lsls, 0000, fa10f000), \
8856 X(_lsr, 0800, fa20f000), \
8857 X(_lsrs, 0800, fa30f000), \
8858 X(_mov, 2000, ea4f0000), \
8859 X(_movs, 2000, ea5f0000), \
8860 X(_mul, 4340, fb00f000), \
8861 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8862 X(_mvn, 43c0, ea6f0000), \
8863 X(_mvns, 43c0, ea7f0000), \
8864 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8865 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8866 X(_orr, 4300, ea400000), \
8867 X(_orrs, 4300, ea500000), \
8868 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8869 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8870 X(_rev, ba00, fa90f080), \
8871 X(_rev16, ba40, fa90f090), \
8872 X(_revsh, bac0, fa90f0b0), \
8873 X(_ror, 41c0, fa60f000), \
8874 X(_rors, 41c0, fa70f000), \
8875 X(_sbc, 4180, eb600000), \
8876 X(_sbcs, 4180, eb700000), \
8877 X(_stmia, c000, e8800000), \
8878 X(_str, 6000, f8400000), \
8879 X(_strb, 7000, f8000000), \
8880 X(_strh, 8000, f8200000), \
8881 X(_str_sp,9000, f84d0000), \
8882 X(_sub, 1e00, eba00000), \
8883 X(_subs, 1e00, ebb00000), \
8884 X(_subi, 8000, f1a00000), \
8885 X(_subis, 8000, f1b00000), \
8886 X(_sxtb, b240, fa4ff080), \
8887 X(_sxth, b200, fa0ff080), \
8888 X(_tst, 4200, ea100f00), \
8889 X(_uxtb, b2c0, fa5ff080), \
8890 X(_uxth, b280, fa1ff080), \
8891 X(_nop, bf00, f3af8000), \
8892 X(_yield, bf10, f3af8001), \
8893 X(_wfe, bf20, f3af8002), \
8894 X(_wfi, bf30, f3af8003), \
8895 X(_sev, bf40, f3af8004),
8897 /* To catch errors in encoding functions, the codes are all offset by
8898 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8899 as 16-bit instructions. */
8900 #define X(a,b,c) T_MNEM##a
8901 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8904 #define X(a,b,c) 0x##b
8905 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8906 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8909 #define X(a,b,c) 0x##c
8910 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8911 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8912 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8916 /* Thumb instruction encoders, in alphabetical order. */
8921 do_t_add_sub_w (void)
8925 Rd
= inst
.operands
[0].reg
;
8926 Rn
= inst
.operands
[1].reg
;
8928 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
8929 is the SP-{plus,minus}-immediate form of the instruction. */
8931 constraint (Rd
== REG_PC
, BAD_PC
);
8933 reject_bad_reg (Rd
);
8935 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8936 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8939 /* Parse an add or subtract instruction. We get here with inst.instruction
8940 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8947 Rd
= inst
.operands
[0].reg
;
8948 Rs
= (inst
.operands
[1].present
8949 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8950 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8953 set_it_insn_type_last ();
8961 flags
= (inst
.instruction
== T_MNEM_adds
8962 || inst
.instruction
== T_MNEM_subs
);
8964 narrow
= !in_it_block ();
8966 narrow
= in_it_block ();
8967 if (!inst
.operands
[2].isreg
)
8971 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8973 add
= (inst
.instruction
== T_MNEM_add
8974 || inst
.instruction
== T_MNEM_adds
);
8976 if (inst
.size_req
!= 4)
8978 /* Attempt to use a narrow opcode, with relaxation if
8980 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8981 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8982 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8983 opcode
= T_MNEM_add_sp
;
8984 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8985 opcode
= T_MNEM_add_pc
;
8986 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8989 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8991 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8995 inst
.instruction
= THUMB_OP16(opcode
);
8996 inst
.instruction
|= (Rd
<< 4) | Rs
;
8997 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8998 if (inst
.size_req
!= 2)
8999 inst
.relax
= opcode
;
9002 constraint (inst
.size_req
== 2, BAD_HIREG
);
9004 if (inst
.size_req
== 4
9005 || (inst
.size_req
!= 2 && !opcode
))
9009 constraint (add
, BAD_PC
);
9010 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9011 _("only SUBS PC, LR, #const allowed"));
9012 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9013 _("expression too complex"));
9014 constraint (inst
.reloc
.exp
.X_add_number
< 0
9015 || inst
.reloc
.exp
.X_add_number
> 0xff,
9016 _("immediate value out of range"));
9017 inst
.instruction
= T2_SUBS_PC_LR
9018 | inst
.reloc
.exp
.X_add_number
;
9019 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9022 else if (Rs
== REG_PC
)
9024 /* Always use addw/subw. */
9025 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9026 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9030 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9031 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9034 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9036 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9038 inst
.instruction
|= Rd
<< 8;
9039 inst
.instruction
|= Rs
<< 16;
9044 Rn
= inst
.operands
[2].reg
;
9045 /* See if we can do this with a 16-bit instruction. */
9046 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9048 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9053 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9054 || inst
.instruction
== T_MNEM_add
)
9057 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9061 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9063 /* Thumb-1 cores (except v6-M) require at least one high
9064 register in a narrow non flag setting add. */
9065 if (Rd
> 7 || Rn
> 7
9066 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9067 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9074 inst
.instruction
= T_OPCODE_ADD_HI
;
9075 inst
.instruction
|= (Rd
& 8) << 4;
9076 inst
.instruction
|= (Rd
& 7);
9077 inst
.instruction
|= Rn
<< 3;
9083 constraint (Rd
== REG_PC
, BAD_PC
);
9084 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9085 constraint (Rs
== REG_PC
, BAD_PC
);
9086 reject_bad_reg (Rn
);
9088 /* If we get here, it can't be done in 16 bits. */
9089 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9090 _("shift must be constant"));
9091 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9092 inst
.instruction
|= Rd
<< 8;
9093 inst
.instruction
|= Rs
<< 16;
9094 encode_thumb32_shifted_operand (2);
9099 constraint (inst
.instruction
== T_MNEM_adds
9100 || inst
.instruction
== T_MNEM_subs
,
9103 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9105 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9106 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9109 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9111 inst
.instruction
|= (Rd
<< 4) | Rs
;
9112 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9116 Rn
= inst
.operands
[2].reg
;
9117 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9119 /* We now have Rd, Rs, and Rn set to registers. */
9120 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9122 /* Can't do this for SUB. */
9123 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9124 inst
.instruction
= T_OPCODE_ADD_HI
;
9125 inst
.instruction
|= (Rd
& 8) << 4;
9126 inst
.instruction
|= (Rd
& 7);
9128 inst
.instruction
|= Rn
<< 3;
9130 inst
.instruction
|= Rs
<< 3;
9132 constraint (1, _("dest must overlap one source register"));
9136 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9137 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9138 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9148 Rd
= inst
.operands
[0].reg
;
9149 reject_bad_reg (Rd
);
9151 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9153 /* Defer to section relaxation. */
9154 inst
.relax
= inst
.instruction
;
9155 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9156 inst
.instruction
|= Rd
<< 4;
9158 else if (unified_syntax
&& inst
.size_req
!= 2)
9160 /* Generate a 32-bit opcode. */
9161 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9162 inst
.instruction
|= Rd
<< 8;
9163 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9164 inst
.reloc
.pc_rel
= 1;
9168 /* Generate a 16-bit opcode. */
9169 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9170 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9171 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9172 inst
.reloc
.pc_rel
= 1;
9174 inst
.instruction
|= Rd
<< 4;
9178 /* Arithmetic instructions for which there is just one 16-bit
9179 instruction encoding, and it allows only two low registers.
9180 For maximal compatibility with ARM syntax, we allow three register
9181 operands even when Thumb-32 instructions are not available, as long
9182 as the first two are identical. For instance, both "sbc r0,r1" and
9183 "sbc r0,r0,r1" are allowed. */
9189 Rd
= inst
.operands
[0].reg
;
9190 Rs
= (inst
.operands
[1].present
9191 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9192 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9193 Rn
= inst
.operands
[2].reg
;
9195 reject_bad_reg (Rd
);
9196 reject_bad_reg (Rs
);
9197 if (inst
.operands
[2].isreg
)
9198 reject_bad_reg (Rn
);
9202 if (!inst
.operands
[2].isreg
)
9204 /* For an immediate, we always generate a 32-bit opcode;
9205 section relaxation will shrink it later if possible. */
9206 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9207 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9208 inst
.instruction
|= Rd
<< 8;
9209 inst
.instruction
|= Rs
<< 16;
9210 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9216 /* See if we can do this with a 16-bit instruction. */
9217 if (THUMB_SETS_FLAGS (inst
.instruction
))
9218 narrow
= !in_it_block ();
9220 narrow
= in_it_block ();
9222 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9224 if (inst
.operands
[2].shifted
)
9226 if (inst
.size_req
== 4)
9232 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9233 inst
.instruction
|= Rd
;
9234 inst
.instruction
|= Rn
<< 3;
9238 /* If we get here, it can't be done in 16 bits. */
9239 constraint (inst
.operands
[2].shifted
9240 && inst
.operands
[2].immisreg
,
9241 _("shift must be constant"));
9242 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9243 inst
.instruction
|= Rd
<< 8;
9244 inst
.instruction
|= Rs
<< 16;
9245 encode_thumb32_shifted_operand (2);
9250 /* On its face this is a lie - the instruction does set the
9251 flags. However, the only supported mnemonic in this mode
9253 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9255 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9256 _("unshifted register required"));
9257 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9258 constraint (Rd
!= Rs
,
9259 _("dest and source1 must be the same register"));
9261 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9262 inst
.instruction
|= Rd
;
9263 inst
.instruction
|= Rn
<< 3;
9267 /* Similarly, but for instructions where the arithmetic operation is
9268 commutative, so we can allow either of them to be different from
9269 the destination operand in a 16-bit instruction. For instance, all
9270 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9277 Rd
= inst
.operands
[0].reg
;
9278 Rs
= (inst
.operands
[1].present
9279 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9280 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9281 Rn
= inst
.operands
[2].reg
;
9283 reject_bad_reg (Rd
);
9284 reject_bad_reg (Rs
);
9285 if (inst
.operands
[2].isreg
)
9286 reject_bad_reg (Rn
);
9290 if (!inst
.operands
[2].isreg
)
9292 /* For an immediate, we always generate a 32-bit opcode;
9293 section relaxation will shrink it later if possible. */
9294 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9295 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9296 inst
.instruction
|= Rd
<< 8;
9297 inst
.instruction
|= Rs
<< 16;
9298 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9304 /* See if we can do this with a 16-bit instruction. */
9305 if (THUMB_SETS_FLAGS (inst
.instruction
))
9306 narrow
= !in_it_block ();
9308 narrow
= in_it_block ();
9310 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9312 if (inst
.operands
[2].shifted
)
9314 if (inst
.size_req
== 4)
9321 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9322 inst
.instruction
|= Rd
;
9323 inst
.instruction
|= Rn
<< 3;
9328 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9329 inst
.instruction
|= Rd
;
9330 inst
.instruction
|= Rs
<< 3;
9335 /* If we get here, it can't be done in 16 bits. */
9336 constraint (inst
.operands
[2].shifted
9337 && inst
.operands
[2].immisreg
,
9338 _("shift must be constant"));
9339 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9340 inst
.instruction
|= Rd
<< 8;
9341 inst
.instruction
|= Rs
<< 16;
9342 encode_thumb32_shifted_operand (2);
9347 /* On its face this is a lie - the instruction does set the
9348 flags. However, the only supported mnemonic in this mode
9350 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9352 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9353 _("unshifted register required"));
9354 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9356 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9357 inst
.instruction
|= Rd
;
9360 inst
.instruction
|= Rn
<< 3;
9362 inst
.instruction
|= Rs
<< 3;
9364 constraint (1, _("dest must overlap one source register"));
9371 if (inst
.operands
[0].present
)
9373 constraint ((inst
.instruction
& 0xf0) != 0x40
9374 && inst
.operands
[0].imm
!= 0xf,
9375 _("bad barrier type"));
9376 inst
.instruction
|= inst
.operands
[0].imm
;
9379 inst
.instruction
|= 0xf;
9386 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9387 constraint (msb
> 32, _("bit-field extends past end of register"));
9388 /* The instruction encoding stores the LSB and MSB,
9389 not the LSB and width. */
9390 Rd
= inst
.operands
[0].reg
;
9391 reject_bad_reg (Rd
);
9392 inst
.instruction
|= Rd
<< 8;
9393 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9394 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9395 inst
.instruction
|= msb
- 1;
9404 Rd
= inst
.operands
[0].reg
;
9405 reject_bad_reg (Rd
);
9407 /* #0 in second position is alternative syntax for bfc, which is
9408 the same instruction but with REG_PC in the Rm field. */
9409 if (!inst
.operands
[1].isreg
)
9413 Rn
= inst
.operands
[1].reg
;
9414 reject_bad_reg (Rn
);
9417 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9418 constraint (msb
> 32, _("bit-field extends past end of register"));
9419 /* The instruction encoding stores the LSB and MSB,
9420 not the LSB and width. */
9421 inst
.instruction
|= Rd
<< 8;
9422 inst
.instruction
|= Rn
<< 16;
9423 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9424 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9425 inst
.instruction
|= msb
- 1;
9433 Rd
= inst
.operands
[0].reg
;
9434 Rn
= inst
.operands
[1].reg
;
9436 reject_bad_reg (Rd
);
9437 reject_bad_reg (Rn
);
9439 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9440 _("bit-field extends past end of register"));
9441 inst
.instruction
|= Rd
<< 8;
9442 inst
.instruction
|= Rn
<< 16;
9443 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9444 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9445 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9448 /* ARM V5 Thumb BLX (argument parse)
9449 BLX <target_addr> which is BLX(1)
9450 BLX <Rm> which is BLX(2)
9451 Unfortunately, there are two different opcodes for this mnemonic.
9452 So, the insns[].value is not used, and the code here zaps values
9453 into inst.instruction.
9455 ??? How to take advantage of the additional two bits of displacement
9456 available in Thumb32 mode? Need new relocation? */
9461 set_it_insn_type_last ();
9463 if (inst
.operands
[0].isreg
)
9465 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9466 /* We have a register, so this is BLX(2). */
9467 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9471 /* No register. This must be BLX(1). */
9472 inst
.instruction
= 0xf000e800;
9473 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9474 inst
.reloc
.pc_rel
= 1;
9485 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9489 /* Conditional branches inside IT blocks are encoded as unconditional
9496 if (cond
!= COND_ALWAYS
)
9497 opcode
= T_MNEM_bcond
;
9499 opcode
= inst
.instruction
;
9501 if (unified_syntax
&& inst
.size_req
== 4)
9503 inst
.instruction
= THUMB_OP32(opcode
);
9504 if (cond
== COND_ALWAYS
)
9505 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9508 gas_assert (cond
!= 0xF);
9509 inst
.instruction
|= cond
<< 22;
9510 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9515 inst
.instruction
= THUMB_OP16(opcode
);
9516 if (cond
== COND_ALWAYS
)
9517 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9520 inst
.instruction
|= cond
<< 8;
9521 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9523 /* Allow section relaxation. */
9524 if (unified_syntax
&& inst
.size_req
!= 2)
9525 inst
.relax
= opcode
;
9528 inst
.reloc
.pc_rel
= 1;
9534 constraint (inst
.cond
!= COND_ALWAYS
,
9535 _("instruction is always unconditional"));
9536 if (inst
.operands
[0].present
)
9538 constraint (inst
.operands
[0].imm
> 255,
9539 _("immediate value out of range"));
9540 inst
.instruction
|= inst
.operands
[0].imm
;
9541 set_it_insn_type (NEUTRAL_IT_INSN
);
9546 do_t_branch23 (void)
9548 set_it_insn_type_last ();
9549 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9550 inst
.reloc
.pc_rel
= 1;
9552 #if defined(OBJ_COFF)
9553 /* If the destination of the branch is a defined symbol which does not have
9554 the THUMB_FUNC attribute, then we must be calling a function which has
9555 the (interfacearm) attribute. We look for the Thumb entry point to that
9556 function and change the branch to refer to that function instead. */
9557 if ( inst
.reloc
.exp
.X_op
== O_symbol
9558 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9559 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9560 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9561 inst
.reloc
.exp
.X_add_symbol
=
9562 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9569 set_it_insn_type_last ();
9570 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9571 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9572 should cause the alignment to be checked once it is known. This is
9573 because BX PC only works if the instruction is word aligned. */
9581 set_it_insn_type_last ();
9582 Rm
= inst
.operands
[0].reg
;
9583 reject_bad_reg (Rm
);
9584 inst
.instruction
|= Rm
<< 16;
9593 Rd
= inst
.operands
[0].reg
;
9594 Rm
= inst
.operands
[1].reg
;
9596 reject_bad_reg (Rd
);
9597 reject_bad_reg (Rm
);
9599 inst
.instruction
|= Rd
<< 8;
9600 inst
.instruction
|= Rm
<< 16;
9601 inst
.instruction
|= Rm
;
9607 set_it_insn_type (OUTSIDE_IT_INSN
);
9608 inst
.instruction
|= inst
.operands
[0].imm
;
9614 set_it_insn_type (OUTSIDE_IT_INSN
);
9616 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9617 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9619 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9620 inst
.instruction
= 0xf3af8000;
9621 inst
.instruction
|= imod
<< 9;
9622 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9623 if (inst
.operands
[1].present
)
9624 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9628 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9629 && (inst
.operands
[0].imm
& 4),
9630 _("selected processor does not support 'A' form "
9631 "of this instruction"));
9632 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9633 _("Thumb does not support the 2-argument "
9634 "form of this instruction"));
9635 inst
.instruction
|= inst
.operands
[0].imm
;
9639 /* THUMB CPY instruction (argument parse). */
9644 if (inst
.size_req
== 4)
9646 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9647 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9648 inst
.instruction
|= inst
.operands
[1].reg
;
9652 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9653 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9654 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9661 set_it_insn_type (OUTSIDE_IT_INSN
);
9662 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9663 inst
.instruction
|= inst
.operands
[0].reg
;
9664 inst
.reloc
.pc_rel
= 1;
9665 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9671 inst
.instruction
|= inst
.operands
[0].imm
;
9677 unsigned Rd
, Rn
, Rm
;
9679 Rd
= inst
.operands
[0].reg
;
9680 Rn
= (inst
.operands
[1].present
9681 ? inst
.operands
[1].reg
: Rd
);
9682 Rm
= inst
.operands
[2].reg
;
9684 reject_bad_reg (Rd
);
9685 reject_bad_reg (Rn
);
9686 reject_bad_reg (Rm
);
9688 inst
.instruction
|= Rd
<< 8;
9689 inst
.instruction
|= Rn
<< 16;
9690 inst
.instruction
|= Rm
;
9696 if (unified_syntax
&& inst
.size_req
== 4)
9697 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9699 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9705 unsigned int cond
= inst
.operands
[0].imm
;
9707 set_it_insn_type (IT_INSN
);
9708 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9711 /* If the condition is a negative condition, invert the mask. */
9712 if ((cond
& 0x1) == 0x0)
9714 unsigned int mask
= inst
.instruction
& 0x000f;
9716 if ((mask
& 0x7) == 0)
9717 /* no conversion needed */;
9718 else if ((mask
& 0x3) == 0)
9720 else if ((mask
& 0x1) == 0)
9725 inst
.instruction
&= 0xfff0;
9726 inst
.instruction
|= mask
;
9729 inst
.instruction
|= cond
<< 4;
9732 /* Helper function used for both push/pop and ldm/stm. */
9734 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9738 load
= (inst
.instruction
& (1 << 20)) != 0;
9740 if (mask
& (1 << 13))
9741 inst
.error
= _("SP not allowed in register list");
9744 if (mask
& (1 << 15))
9746 if (mask
& (1 << 14))
9747 inst
.error
= _("LR and PC should not both be in register list");
9749 set_it_insn_type_last ();
9752 if ((mask
& (1 << base
)) != 0
9754 as_warn (_("base register should not be in register list "
9755 "when written back"));
9759 if (mask
& (1 << 15))
9760 inst
.error
= _("PC not allowed in register list");
9762 if (mask
& (1 << base
))
9763 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9766 if ((mask
& (mask
- 1)) == 0)
9768 /* Single register transfers implemented as str/ldr. */
9771 if (inst
.instruction
& (1 << 23))
9772 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9774 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9778 if (inst
.instruction
& (1 << 23))
9779 inst
.instruction
= 0x00800000; /* ia -> [base] */
9781 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9784 inst
.instruction
|= 0xf8400000;
9786 inst
.instruction
|= 0x00100000;
9788 mask
= ffs (mask
) - 1;
9792 inst
.instruction
|= WRITE_BACK
;
9794 inst
.instruction
|= mask
;
9795 inst
.instruction
|= base
<< 16;
9801 /* This really doesn't seem worth it. */
9802 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9803 _("expression too complex"));
9804 constraint (inst
.operands
[1].writeback
,
9805 _("Thumb load/store multiple does not support {reglist}^"));
9813 /* See if we can use a 16-bit instruction. */
9814 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9815 && inst
.size_req
!= 4
9816 && !(inst
.operands
[1].imm
& ~0xff))
9818 mask
= 1 << inst
.operands
[0].reg
;
9820 if (inst
.operands
[0].reg
<= 7
9821 && (inst
.instruction
== T_MNEM_stmia
9822 ? inst
.operands
[0].writeback
9823 : (inst
.operands
[0].writeback
9824 == !(inst
.operands
[1].imm
& mask
))))
9826 if (inst
.instruction
== T_MNEM_stmia
9827 && (inst
.operands
[1].imm
& mask
)
9828 && (inst
.operands
[1].imm
& (mask
- 1)))
9829 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9830 inst
.operands
[0].reg
);
9832 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9833 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9834 inst
.instruction
|= inst
.operands
[1].imm
;
9837 else if (inst
.operands
[0] .reg
== REG_SP
9838 && inst
.operands
[0].writeback
)
9840 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9841 ? T_MNEM_push
: T_MNEM_pop
);
9842 inst
.instruction
|= inst
.operands
[1].imm
;
9849 if (inst
.instruction
< 0xffff)
9850 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9852 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9853 inst
.operands
[0].writeback
);
9858 constraint (inst
.operands
[0].reg
> 7
9859 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9860 constraint (inst
.instruction
!= T_MNEM_ldmia
9861 && inst
.instruction
!= T_MNEM_stmia
,
9862 _("Thumb-2 instruction only valid in unified syntax"));
9863 if (inst
.instruction
== T_MNEM_stmia
)
9865 if (!inst
.operands
[0].writeback
)
9866 as_warn (_("this instruction will write back the base register"));
9867 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9868 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9869 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9870 inst
.operands
[0].reg
);
9874 if (!inst
.operands
[0].writeback
9875 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9876 as_warn (_("this instruction will write back the base register"));
9877 else if (inst
.operands
[0].writeback
9878 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9879 as_warn (_("this instruction will not write back the base register"));
9882 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9883 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9884 inst
.instruction
|= inst
.operands
[1].imm
;
9891 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9892 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9893 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9894 || inst
.operands
[1].negative
,
9897 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9899 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9900 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9901 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9907 if (!inst
.operands
[1].present
)
9909 constraint (inst
.operands
[0].reg
== REG_LR
,
9910 _("r14 not allowed as first register "
9911 "when second register is omitted"));
9912 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9914 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9917 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9918 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9919 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9925 unsigned long opcode
;
9928 if (inst
.operands
[0].isreg
9929 && !inst
.operands
[0].preind
9930 && inst
.operands
[0].reg
== REG_PC
)
9931 set_it_insn_type_last ();
9933 opcode
= inst
.instruction
;
9936 if (!inst
.operands
[1].isreg
)
9938 if (opcode
<= 0xffff)
9939 inst
.instruction
= THUMB_OP32 (opcode
);
9940 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9943 if (inst
.operands
[1].isreg
9944 && !inst
.operands
[1].writeback
9945 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9946 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9948 && inst
.size_req
!= 4)
9950 /* Insn may have a 16-bit form. */
9951 Rn
= inst
.operands
[1].reg
;
9952 if (inst
.operands
[1].immisreg
)
9954 inst
.instruction
= THUMB_OP16 (opcode
);
9956 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9958 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
9959 reject_bad_reg (inst
.operands
[1].imm
);
9961 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9962 && opcode
!= T_MNEM_ldrsb
)
9963 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9964 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9971 if (inst
.reloc
.pc_rel
)
9972 opcode
= T_MNEM_ldr_pc2
;
9974 opcode
= T_MNEM_ldr_pc
;
9978 if (opcode
== T_MNEM_ldr
)
9979 opcode
= T_MNEM_ldr_sp
;
9981 opcode
= T_MNEM_str_sp
;
9983 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9987 inst
.instruction
= inst
.operands
[0].reg
;
9988 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9990 inst
.instruction
|= THUMB_OP16 (opcode
);
9991 if (inst
.size_req
== 2)
9992 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9994 inst
.relax
= opcode
;
9998 /* Definitely a 32-bit variant. */
10000 /* Do some validations regarding addressing modes. */
10001 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10002 && opcode
!= T_MNEM_str
)
10003 reject_bad_reg (inst
.operands
[1].imm
);
10005 inst
.instruction
= THUMB_OP32 (opcode
);
10006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10007 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10011 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10013 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10015 /* Only [Rn,Rm] is acceptable. */
10016 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10017 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10018 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10019 || inst
.operands
[1].negative
,
10020 _("Thumb does not support this addressing mode"));
10021 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10025 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10026 if (!inst
.operands
[1].isreg
)
10027 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10030 constraint (!inst
.operands
[1].preind
10031 || inst
.operands
[1].shifted
10032 || inst
.operands
[1].writeback
,
10033 _("Thumb does not support this addressing mode"));
10034 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10036 constraint (inst
.instruction
& 0x0600,
10037 _("byte or halfword not valid for base register"));
10038 constraint (inst
.operands
[1].reg
== REG_PC
10039 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10040 _("r15 based store not allowed"));
10041 constraint (inst
.operands
[1].immisreg
,
10042 _("invalid base register for register offset"));
10044 if (inst
.operands
[1].reg
== REG_PC
)
10045 inst
.instruction
= T_OPCODE_LDR_PC
;
10046 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10047 inst
.instruction
= T_OPCODE_LDR_SP
;
10049 inst
.instruction
= T_OPCODE_STR_SP
;
10051 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10052 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10056 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10057 if (!inst
.operands
[1].immisreg
)
10059 /* Immediate offset. */
10060 inst
.instruction
|= inst
.operands
[0].reg
;
10061 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10062 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10066 /* Register offset. */
10067 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10068 constraint (inst
.operands
[1].negative
,
10069 _("Thumb does not support this addressing mode"));
10072 switch (inst
.instruction
)
10074 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10075 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10076 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10077 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10078 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10079 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10080 case 0x5600 /* ldrsb */:
10081 case 0x5e00 /* ldrsh */: break;
10085 inst
.instruction
|= inst
.operands
[0].reg
;
10086 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10087 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10093 if (!inst
.operands
[1].present
)
10095 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10096 constraint (inst
.operands
[0].reg
== REG_LR
,
10097 _("r14 not allowed here"));
10099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10100 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10101 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10107 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10108 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10114 unsigned Rd
, Rn
, Rm
, Ra
;
10116 Rd
= inst
.operands
[0].reg
;
10117 Rn
= inst
.operands
[1].reg
;
10118 Rm
= inst
.operands
[2].reg
;
10119 Ra
= inst
.operands
[3].reg
;
10121 reject_bad_reg (Rd
);
10122 reject_bad_reg (Rn
);
10123 reject_bad_reg (Rm
);
10124 reject_bad_reg (Ra
);
10126 inst
.instruction
|= Rd
<< 8;
10127 inst
.instruction
|= Rn
<< 16;
10128 inst
.instruction
|= Rm
;
10129 inst
.instruction
|= Ra
<< 12;
10135 unsigned RdLo
, RdHi
, Rn
, Rm
;
10137 RdLo
= inst
.operands
[0].reg
;
10138 RdHi
= inst
.operands
[1].reg
;
10139 Rn
= inst
.operands
[2].reg
;
10140 Rm
= inst
.operands
[3].reg
;
10142 reject_bad_reg (RdLo
);
10143 reject_bad_reg (RdHi
);
10144 reject_bad_reg (Rn
);
10145 reject_bad_reg (Rm
);
10147 inst
.instruction
|= RdLo
<< 12;
10148 inst
.instruction
|= RdHi
<< 8;
10149 inst
.instruction
|= Rn
<< 16;
10150 inst
.instruction
|= Rm
;
10154 do_t_mov_cmp (void)
10158 Rn
= inst
.operands
[0].reg
;
10159 Rm
= inst
.operands
[1].reg
;
10162 set_it_insn_type_last ();
10164 if (unified_syntax
)
10166 int r0off
= (inst
.instruction
== T_MNEM_mov
10167 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10168 unsigned long opcode
;
10169 bfd_boolean narrow
;
10170 bfd_boolean low_regs
;
10172 low_regs
= (Rn
<= 7 && Rm
<= 7);
10173 opcode
= inst
.instruction
;
10174 if (in_it_block ())
10175 narrow
= opcode
!= T_MNEM_movs
;
10177 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10178 if (inst
.size_req
== 4
10179 || inst
.operands
[1].shifted
)
10182 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10183 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10184 && !inst
.operands
[1].shifted
10188 inst
.instruction
= T2_SUBS_PC_LR
;
10192 if (opcode
== T_MNEM_cmp
)
10194 constraint (Rn
== REG_PC
, BAD_PC
);
10197 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10199 warn_deprecated_sp (Rm
);
10200 /* R15 was documented as a valid choice for Rm in ARMv6,
10201 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10202 tools reject R15, so we do too. */
10203 constraint (Rm
== REG_PC
, BAD_PC
);
10206 reject_bad_reg (Rm
);
10208 else if (opcode
== T_MNEM_mov
10209 || opcode
== T_MNEM_movs
)
10211 if (inst
.operands
[1].isreg
)
10213 if (opcode
== T_MNEM_movs
)
10215 reject_bad_reg (Rn
);
10216 reject_bad_reg (Rm
);
10218 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10219 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10220 reject_bad_reg (Rm
);
10223 reject_bad_reg (Rn
);
10226 if (!inst
.operands
[1].isreg
)
10228 /* Immediate operand. */
10229 if (!in_it_block () && opcode
== T_MNEM_mov
)
10231 if (low_regs
&& narrow
)
10233 inst
.instruction
= THUMB_OP16 (opcode
);
10234 inst
.instruction
|= Rn
<< 8;
10235 if (inst
.size_req
== 2)
10236 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10238 inst
.relax
= opcode
;
10242 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10243 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10244 inst
.instruction
|= Rn
<< r0off
;
10245 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10248 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10249 && (inst
.instruction
== T_MNEM_mov
10250 || inst
.instruction
== T_MNEM_movs
))
10252 /* Register shifts are encoded as separate shift instructions. */
10253 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10255 if (in_it_block ())
10260 if (inst
.size_req
== 4)
10263 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10269 switch (inst
.operands
[1].shift_kind
)
10272 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10275 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10278 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10281 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10287 inst
.instruction
= opcode
;
10290 inst
.instruction
|= Rn
;
10291 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10296 inst
.instruction
|= CONDS_BIT
;
10298 inst
.instruction
|= Rn
<< 8;
10299 inst
.instruction
|= Rm
<< 16;
10300 inst
.instruction
|= inst
.operands
[1].imm
;
10305 /* Some mov with immediate shift have narrow variants.
10306 Register shifts are handled above. */
10307 if (low_regs
&& inst
.operands
[1].shifted
10308 && (inst
.instruction
== T_MNEM_mov
10309 || inst
.instruction
== T_MNEM_movs
))
10311 if (in_it_block ())
10312 narrow
= (inst
.instruction
== T_MNEM_mov
);
10314 narrow
= (inst
.instruction
== T_MNEM_movs
);
10319 switch (inst
.operands
[1].shift_kind
)
10321 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10322 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10323 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10324 default: narrow
= FALSE
; break;
10330 inst
.instruction
|= Rn
;
10331 inst
.instruction
|= Rm
<< 3;
10332 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10336 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10337 inst
.instruction
|= Rn
<< r0off
;
10338 encode_thumb32_shifted_operand (1);
10342 switch (inst
.instruction
)
10345 inst
.instruction
= T_OPCODE_MOV_HR
;
10346 inst
.instruction
|= (Rn
& 0x8) << 4;
10347 inst
.instruction
|= (Rn
& 0x7);
10348 inst
.instruction
|= Rm
<< 3;
10352 /* We know we have low registers at this point.
10353 Generate ADD Rd, Rs, #0. */
10354 inst
.instruction
= T_OPCODE_ADD_I3
;
10355 inst
.instruction
|= Rn
;
10356 inst
.instruction
|= Rm
<< 3;
10362 inst
.instruction
= T_OPCODE_CMP_LR
;
10363 inst
.instruction
|= Rn
;
10364 inst
.instruction
|= Rm
<< 3;
10368 inst
.instruction
= T_OPCODE_CMP_HR
;
10369 inst
.instruction
|= (Rn
& 0x8) << 4;
10370 inst
.instruction
|= (Rn
& 0x7);
10371 inst
.instruction
|= Rm
<< 3;
10378 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10380 /* PR 10443: Do not silently ignore shifted operands. */
10381 constraint (inst
.operands
[1].shifted
,
10382 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10384 if (inst
.operands
[1].isreg
)
10386 if (Rn
< 8 && Rm
< 8)
10388 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10389 since a MOV instruction produces unpredictable results. */
10390 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10391 inst
.instruction
= T_OPCODE_ADD_I3
;
10393 inst
.instruction
= T_OPCODE_CMP_LR
;
10395 inst
.instruction
|= Rn
;
10396 inst
.instruction
|= Rm
<< 3;
10400 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10401 inst
.instruction
= T_OPCODE_MOV_HR
;
10403 inst
.instruction
= T_OPCODE_CMP_HR
;
10409 constraint (Rn
> 7,
10410 _("only lo regs allowed with immediate"));
10411 inst
.instruction
|= Rn
<< 8;
10412 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10423 top
= (inst
.instruction
& 0x00800000) != 0;
10424 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10426 constraint (top
, _(":lower16: not allowed this instruction"));
10427 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10429 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10431 constraint (!top
, _(":upper16: not allowed this instruction"));
10432 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10435 Rd
= inst
.operands
[0].reg
;
10436 reject_bad_reg (Rd
);
10438 inst
.instruction
|= Rd
<< 8;
10439 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10441 imm
= inst
.reloc
.exp
.X_add_number
;
10442 inst
.instruction
|= (imm
& 0xf000) << 4;
10443 inst
.instruction
|= (imm
& 0x0800) << 15;
10444 inst
.instruction
|= (imm
& 0x0700) << 4;
10445 inst
.instruction
|= (imm
& 0x00ff);
10450 do_t_mvn_tst (void)
10454 Rn
= inst
.operands
[0].reg
;
10455 Rm
= inst
.operands
[1].reg
;
10457 if (inst
.instruction
== T_MNEM_cmp
10458 || inst
.instruction
== T_MNEM_cmn
)
10459 constraint (Rn
== REG_PC
, BAD_PC
);
10461 reject_bad_reg (Rn
);
10462 reject_bad_reg (Rm
);
10464 if (unified_syntax
)
10466 int r0off
= (inst
.instruction
== T_MNEM_mvn
10467 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10468 bfd_boolean narrow
;
10470 if (inst
.size_req
== 4
10471 || inst
.instruction
> 0xffff
10472 || inst
.operands
[1].shifted
10473 || Rn
> 7 || Rm
> 7)
10475 else if (inst
.instruction
== T_MNEM_cmn
)
10477 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10478 narrow
= !in_it_block ();
10480 narrow
= in_it_block ();
10482 if (!inst
.operands
[1].isreg
)
10484 /* For an immediate, we always generate a 32-bit opcode;
10485 section relaxation will shrink it later if possible. */
10486 if (inst
.instruction
< 0xffff)
10487 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10488 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10489 inst
.instruction
|= Rn
<< r0off
;
10490 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10494 /* See if we can do this with a 16-bit instruction. */
10497 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10498 inst
.instruction
|= Rn
;
10499 inst
.instruction
|= Rm
<< 3;
10503 constraint (inst
.operands
[1].shifted
10504 && inst
.operands
[1].immisreg
,
10505 _("shift must be constant"));
10506 if (inst
.instruction
< 0xffff)
10507 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10508 inst
.instruction
|= Rn
<< r0off
;
10509 encode_thumb32_shifted_operand (1);
10515 constraint (inst
.instruction
> 0xffff
10516 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10517 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10518 _("unshifted register required"));
10519 constraint (Rn
> 7 || Rm
> 7,
10522 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10523 inst
.instruction
|= Rn
;
10524 inst
.instruction
|= Rm
<< 3;
10534 if (do_vfp_nsyn_mrs () == SUCCESS
)
10537 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10540 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10541 _("selected processor does not support "
10542 "requested special purpose register"));
10546 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10547 _("selected processor does not support "
10548 "requested special purpose register"));
10549 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10550 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10551 _("'CPSR' or 'SPSR' expected"));
10554 Rd
= inst
.operands
[0].reg
;
10555 reject_bad_reg (Rd
);
10557 inst
.instruction
|= Rd
<< 8;
10558 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10559 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10568 if (do_vfp_nsyn_msr () == SUCCESS
)
10571 constraint (!inst
.operands
[1].isreg
,
10572 _("Thumb encoding does not support an immediate here"));
10573 flags
= inst
.operands
[0].imm
;
10576 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10577 _("selected processor does not support "
10578 "requested special purpose register"));
10582 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10583 _("selected processor does not support "
10584 "requested special purpose register"));
10588 Rn
= inst
.operands
[1].reg
;
10589 reject_bad_reg (Rn
);
10591 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10592 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10593 inst
.instruction
|= (flags
& 0xff);
10594 inst
.instruction
|= Rn
<< 16;
10600 bfd_boolean narrow
;
10601 unsigned Rd
, Rn
, Rm
;
10603 if (!inst
.operands
[2].present
)
10604 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10606 Rd
= inst
.operands
[0].reg
;
10607 Rn
= inst
.operands
[1].reg
;
10608 Rm
= inst
.operands
[2].reg
;
10610 if (unified_syntax
)
10612 if (inst
.size_req
== 4
10618 else if (inst
.instruction
== T_MNEM_muls
)
10619 narrow
= !in_it_block ();
10621 narrow
= in_it_block ();
10625 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10626 constraint (Rn
> 7 || Rm
> 7,
10633 /* 16-bit MULS/Conditional MUL. */
10634 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10635 inst
.instruction
|= Rd
;
10638 inst
.instruction
|= Rm
<< 3;
10640 inst
.instruction
|= Rn
<< 3;
10642 constraint (1, _("dest must overlap one source register"));
10646 constraint (inst
.instruction
!= T_MNEM_mul
,
10647 _("Thumb-2 MUL must not set flags"));
10649 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10650 inst
.instruction
|= Rd
<< 8;
10651 inst
.instruction
|= Rn
<< 16;
10652 inst
.instruction
|= Rm
<< 0;
10654 reject_bad_reg (Rd
);
10655 reject_bad_reg (Rn
);
10656 reject_bad_reg (Rm
);
10663 unsigned RdLo
, RdHi
, Rn
, Rm
;
10665 RdLo
= inst
.operands
[0].reg
;
10666 RdHi
= inst
.operands
[1].reg
;
10667 Rn
= inst
.operands
[2].reg
;
10668 Rm
= inst
.operands
[3].reg
;
10670 reject_bad_reg (RdLo
);
10671 reject_bad_reg (RdHi
);
10672 reject_bad_reg (Rn
);
10673 reject_bad_reg (Rm
);
10675 inst
.instruction
|= RdLo
<< 12;
10676 inst
.instruction
|= RdHi
<< 8;
10677 inst
.instruction
|= Rn
<< 16;
10678 inst
.instruction
|= Rm
;
10681 as_tsktsk (_("rdhi and rdlo must be different"));
10687 set_it_insn_type (NEUTRAL_IT_INSN
);
10689 if (unified_syntax
)
10691 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10693 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10694 inst
.instruction
|= inst
.operands
[0].imm
;
10698 /* PR9722: Check for Thumb2 availability before
10699 generating a thumb2 nop instruction. */
10700 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10702 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10703 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10706 inst
.instruction
= 0x46c0;
10711 constraint (inst
.operands
[0].present
,
10712 _("Thumb does not support NOP with hints"));
10713 inst
.instruction
= 0x46c0;
10720 if (unified_syntax
)
10722 bfd_boolean narrow
;
10724 if (THUMB_SETS_FLAGS (inst
.instruction
))
10725 narrow
= !in_it_block ();
10727 narrow
= in_it_block ();
10728 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10730 if (inst
.size_req
== 4)
10735 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10736 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10737 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10741 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10742 inst
.instruction
|= inst
.operands
[0].reg
;
10743 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10748 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10750 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10752 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10753 inst
.instruction
|= inst
.operands
[0].reg
;
10754 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10763 Rd
= inst
.operands
[0].reg
;
10764 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10766 reject_bad_reg (Rd
);
10767 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10768 reject_bad_reg (Rn
);
10770 inst
.instruction
|= Rd
<< 8;
10771 inst
.instruction
|= Rn
<< 16;
10773 if (!inst
.operands
[2].isreg
)
10775 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10776 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10782 Rm
= inst
.operands
[2].reg
;
10783 reject_bad_reg (Rm
);
10785 constraint (inst
.operands
[2].shifted
10786 && inst
.operands
[2].immisreg
,
10787 _("shift must be constant"));
10788 encode_thumb32_shifted_operand (2);
10795 unsigned Rd
, Rn
, Rm
;
10797 Rd
= inst
.operands
[0].reg
;
10798 Rn
= inst
.operands
[1].reg
;
10799 Rm
= inst
.operands
[2].reg
;
10801 reject_bad_reg (Rd
);
10802 reject_bad_reg (Rn
);
10803 reject_bad_reg (Rm
);
10805 inst
.instruction
|= Rd
<< 8;
10806 inst
.instruction
|= Rn
<< 16;
10807 inst
.instruction
|= Rm
;
10808 if (inst
.operands
[3].present
)
10810 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10811 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10812 _("expression too complex"));
10813 inst
.instruction
|= (val
& 0x1c) << 10;
10814 inst
.instruction
|= (val
& 0x03) << 6;
10821 if (!inst
.operands
[3].present
)
10825 inst
.instruction
&= ~0x00000020;
10827 /* PR 10168. Swap the Rm and Rn registers. */
10828 Rtmp
= inst
.operands
[1].reg
;
10829 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10830 inst
.operands
[2].reg
= Rtmp
;
10838 if (inst
.operands
[0].immisreg
)
10839 reject_bad_reg (inst
.operands
[0].imm
);
10841 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10845 do_t_push_pop (void)
10849 constraint (inst
.operands
[0].writeback
,
10850 _("push/pop do not support {reglist}^"));
10851 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10852 _("expression too complex"));
10854 mask
= inst
.operands
[0].imm
;
10855 if ((mask
& ~0xff) == 0)
10856 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10857 else if ((inst
.instruction
== T_MNEM_push
10858 && (mask
& ~0xff) == 1 << REG_LR
)
10859 || (inst
.instruction
== T_MNEM_pop
10860 && (mask
& ~0xff) == 1 << REG_PC
))
10862 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10863 inst
.instruction
|= THUMB_PP_PC_LR
;
10864 inst
.instruction
|= mask
& 0xff;
10866 else if (unified_syntax
)
10868 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10869 encode_thumb2_ldmstm (13, mask
, TRUE
);
10873 inst
.error
= _("invalid register list to push/pop instruction");
10883 Rd
= inst
.operands
[0].reg
;
10884 Rm
= inst
.operands
[1].reg
;
10886 reject_bad_reg (Rd
);
10887 reject_bad_reg (Rm
);
10889 inst
.instruction
|= Rd
<< 8;
10890 inst
.instruction
|= Rm
<< 16;
10891 inst
.instruction
|= Rm
;
10899 Rd
= inst
.operands
[0].reg
;
10900 Rm
= inst
.operands
[1].reg
;
10902 reject_bad_reg (Rd
);
10903 reject_bad_reg (Rm
);
10905 if (Rd
<= 7 && Rm
<= 7
10906 && inst
.size_req
!= 4)
10908 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10909 inst
.instruction
|= Rd
;
10910 inst
.instruction
|= Rm
<< 3;
10912 else if (unified_syntax
)
10914 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10915 inst
.instruction
|= Rd
<< 8;
10916 inst
.instruction
|= Rm
<< 16;
10917 inst
.instruction
|= Rm
;
10920 inst
.error
= BAD_HIREG
;
10928 Rd
= inst
.operands
[0].reg
;
10929 Rm
= inst
.operands
[1].reg
;
10931 reject_bad_reg (Rd
);
10932 reject_bad_reg (Rm
);
10934 inst
.instruction
|= Rd
<< 8;
10935 inst
.instruction
|= Rm
;
10943 Rd
= inst
.operands
[0].reg
;
10944 Rs
= (inst
.operands
[1].present
10945 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10946 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10948 reject_bad_reg (Rd
);
10949 reject_bad_reg (Rs
);
10950 if (inst
.operands
[2].isreg
)
10951 reject_bad_reg (inst
.operands
[2].reg
);
10953 inst
.instruction
|= Rd
<< 8;
10954 inst
.instruction
|= Rs
<< 16;
10955 if (!inst
.operands
[2].isreg
)
10957 bfd_boolean narrow
;
10959 if ((inst
.instruction
& 0x00100000) != 0)
10960 narrow
= !in_it_block ();
10962 narrow
= in_it_block ();
10964 if (Rd
> 7 || Rs
> 7)
10967 if (inst
.size_req
== 4 || !unified_syntax
)
10970 if (inst
.reloc
.exp
.X_op
!= O_constant
10971 || inst
.reloc
.exp
.X_add_number
!= 0)
10974 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10975 relaxation, but it doesn't seem worth the hassle. */
10978 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10979 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10980 inst
.instruction
|= Rs
<< 3;
10981 inst
.instruction
|= Rd
;
10985 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10986 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10990 encode_thumb32_shifted_operand (2);
10996 set_it_insn_type (OUTSIDE_IT_INSN
);
10997 if (inst
.operands
[0].imm
)
10998 inst
.instruction
|= 0x8;
11004 if (!inst
.operands
[1].present
)
11005 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11007 if (unified_syntax
)
11009 bfd_boolean narrow
;
11012 switch (inst
.instruction
)
11015 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11017 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11019 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11021 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11025 if (THUMB_SETS_FLAGS (inst
.instruction
))
11026 narrow
= !in_it_block ();
11028 narrow
= in_it_block ();
11029 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11031 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11033 if (inst
.operands
[2].isreg
11034 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11035 || inst
.operands
[2].reg
> 7))
11037 if (inst
.size_req
== 4)
11040 reject_bad_reg (inst
.operands
[0].reg
);
11041 reject_bad_reg (inst
.operands
[1].reg
);
11045 if (inst
.operands
[2].isreg
)
11047 reject_bad_reg (inst
.operands
[2].reg
);
11048 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11049 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11050 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11051 inst
.instruction
|= inst
.operands
[2].reg
;
11055 inst
.operands
[1].shifted
= 1;
11056 inst
.operands
[1].shift_kind
= shift_kind
;
11057 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11058 ? T_MNEM_movs
: T_MNEM_mov
);
11059 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11060 encode_thumb32_shifted_operand (1);
11061 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11062 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11067 if (inst
.operands
[2].isreg
)
11069 switch (shift_kind
)
11071 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11072 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11073 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11074 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11078 inst
.instruction
|= inst
.operands
[0].reg
;
11079 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11083 switch (shift_kind
)
11085 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11086 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11087 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11090 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11091 inst
.instruction
|= inst
.operands
[0].reg
;
11092 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11098 constraint (inst
.operands
[0].reg
> 7
11099 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11100 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11102 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11104 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11105 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11106 _("source1 and dest must be same register"));
11108 switch (inst
.instruction
)
11110 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11111 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11112 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11113 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11117 inst
.instruction
|= inst
.operands
[0].reg
;
11118 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11122 switch (inst
.instruction
)
11124 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11125 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11126 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11127 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11130 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11131 inst
.instruction
|= inst
.operands
[0].reg
;
11132 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11140 unsigned Rd
, Rn
, Rm
;
11142 Rd
= inst
.operands
[0].reg
;
11143 Rn
= inst
.operands
[1].reg
;
11144 Rm
= inst
.operands
[2].reg
;
11146 reject_bad_reg (Rd
);
11147 reject_bad_reg (Rn
);
11148 reject_bad_reg (Rm
);
11150 inst
.instruction
|= Rd
<< 8;
11151 inst
.instruction
|= Rn
<< 16;
11152 inst
.instruction
|= Rm
;
11158 unsigned Rd
, Rn
, Rm
;
11160 Rd
= inst
.operands
[0].reg
;
11161 Rm
= inst
.operands
[1].reg
;
11162 Rn
= inst
.operands
[2].reg
;
11164 reject_bad_reg (Rd
);
11165 reject_bad_reg (Rn
);
11166 reject_bad_reg (Rm
);
11168 inst
.instruction
|= Rd
<< 8;
11169 inst
.instruction
|= Rn
<< 16;
11170 inst
.instruction
|= Rm
;
11176 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11177 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11178 _("expression too complex"));
11179 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11180 inst
.instruction
|= (value
& 0xf000) >> 12;
11181 inst
.instruction
|= (value
& 0x0ff0);
11182 inst
.instruction
|= (value
& 0x000f) << 16;
11186 do_t_ssat_usat (int bias
)
11190 Rd
= inst
.operands
[0].reg
;
11191 Rn
= inst
.operands
[2].reg
;
11193 reject_bad_reg (Rd
);
11194 reject_bad_reg (Rn
);
11196 inst
.instruction
|= Rd
<< 8;
11197 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11198 inst
.instruction
|= Rn
<< 16;
11200 if (inst
.operands
[3].present
)
11202 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11204 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11206 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11207 _("expression too complex"));
11209 if (shift_amount
!= 0)
11211 constraint (shift_amount
> 31,
11212 _("shift expression is too large"));
11214 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11215 inst
.instruction
|= 0x00200000; /* sh bit. */
11217 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11218 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11226 do_t_ssat_usat (1);
11234 Rd
= inst
.operands
[0].reg
;
11235 Rn
= inst
.operands
[2].reg
;
11237 reject_bad_reg (Rd
);
11238 reject_bad_reg (Rn
);
11240 inst
.instruction
|= Rd
<< 8;
11241 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11242 inst
.instruction
|= Rn
<< 16;
11248 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11249 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11250 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11251 || inst
.operands
[2].negative
,
11254 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11256 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11257 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11258 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11259 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11265 if (!inst
.operands
[2].present
)
11266 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11268 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11269 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11270 || inst
.operands
[0].reg
== inst
.operands
[3].reg
11271 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
11274 inst
.instruction
|= inst
.operands
[0].reg
;
11275 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11276 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11277 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11283 unsigned Rd
, Rn
, Rm
;
11285 Rd
= inst
.operands
[0].reg
;
11286 Rn
= inst
.operands
[1].reg
;
11287 Rm
= inst
.operands
[2].reg
;
11289 reject_bad_reg (Rd
);
11290 reject_bad_reg (Rn
);
11291 reject_bad_reg (Rm
);
11293 inst
.instruction
|= Rd
<< 8;
11294 inst
.instruction
|= Rn
<< 16;
11295 inst
.instruction
|= Rm
;
11296 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11304 Rd
= inst
.operands
[0].reg
;
11305 Rm
= inst
.operands
[1].reg
;
11307 reject_bad_reg (Rd
);
11308 reject_bad_reg (Rm
);
11310 if (inst
.instruction
<= 0xffff
11311 && inst
.size_req
!= 4
11312 && Rd
<= 7 && Rm
<= 7
11313 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11315 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11316 inst
.instruction
|= Rd
;
11317 inst
.instruction
|= Rm
<< 3;
11319 else if (unified_syntax
)
11321 if (inst
.instruction
<= 0xffff)
11322 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11323 inst
.instruction
|= Rd
<< 8;
11324 inst
.instruction
|= Rm
;
11325 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11329 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11330 _("Thumb encoding does not support rotation"));
11331 constraint (1, BAD_HIREG
);
11338 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11347 half
= (inst
.instruction
& 0x10) != 0;
11348 set_it_insn_type_last ();
11349 constraint (inst
.operands
[0].immisreg
,
11350 _("instruction requires register index"));
11352 Rn
= inst
.operands
[0].reg
;
11353 Rm
= inst
.operands
[0].imm
;
11355 constraint (Rn
== REG_SP
, BAD_SP
);
11356 reject_bad_reg (Rm
);
11358 constraint (!half
&& inst
.operands
[0].shifted
,
11359 _("instruction does not allow shifted index"));
11360 inst
.instruction
|= (Rn
<< 16) | Rm
;
11366 do_t_ssat_usat (0);
11374 Rd
= inst
.operands
[0].reg
;
11375 Rn
= inst
.operands
[2].reg
;
11377 reject_bad_reg (Rd
);
11378 reject_bad_reg (Rn
);
11380 inst
.instruction
|= Rd
<< 8;
11381 inst
.instruction
|= inst
.operands
[1].imm
;
11382 inst
.instruction
|= Rn
<< 16;
11385 /* Neon instruction encoder helpers. */
11387 /* Encodings for the different types for various Neon opcodes. */
11389 /* An "invalid" code for the following tables. */
11392 struct neon_tab_entry
11395 unsigned float_or_poly
;
11396 unsigned scalar_or_imm
;
11399 /* Map overloaded Neon opcodes to their respective encodings. */
11400 #define NEON_ENC_TAB \
11401 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11402 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11403 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11404 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11405 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11406 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11407 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11408 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11409 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11410 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11411 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11412 /* Register variants of the following two instructions are encoded as
11413 vcge / vcgt with the operands reversed. */ \
11414 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11415 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11416 X(vfma, N_INV, 0x0000c10, N_INV), \
11417 X(vfms, N_INV, 0x0200c10, N_INV), \
11418 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11419 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11420 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11421 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11422 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11423 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11424 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11425 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11426 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11427 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11428 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11429 X(vshl, 0x0000400, N_INV, 0x0800510), \
11430 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11431 X(vand, 0x0000110, N_INV, 0x0800030), \
11432 X(vbic, 0x0100110, N_INV, 0x0800030), \
11433 X(veor, 0x1000110, N_INV, N_INV), \
11434 X(vorn, 0x0300110, N_INV, 0x0800010), \
11435 X(vorr, 0x0200110, N_INV, 0x0800010), \
11436 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11437 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11438 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11439 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11440 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11441 X(vst1, 0x0000000, 0x0800000, N_INV), \
11442 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11443 X(vst2, 0x0000100, 0x0800100, N_INV), \
11444 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11445 X(vst3, 0x0000200, 0x0800200, N_INV), \
11446 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11447 X(vst4, 0x0000300, 0x0800300, N_INV), \
11448 X(vmovn, 0x1b20200, N_INV, N_INV), \
11449 X(vtrn, 0x1b20080, N_INV, N_INV), \
11450 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11451 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11452 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11453 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11454 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11455 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11456 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11457 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11458 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11459 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11460 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11464 #define X(OPC,I,F,S) N_MNEM_##OPC
11469 static const struct neon_tab_entry neon_enc_tab
[] =
11471 #define X(OPC,I,F,S) { (I), (F), (S) }
11476 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11477 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11478 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11479 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11480 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11481 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11482 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11483 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11484 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11485 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11486 #define NEON_ENC_SINGLE_(X) \
11487 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11488 #define NEON_ENC_DOUBLE_(X) \
11489 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11491 #define NEON_ENCODE(type, inst) \
11494 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11495 inst.is_neon = 1; \
11499 #define check_neon_suffixes \
11502 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11504 as_bad (_("invalid neon suffix for non neon instruction")); \
11510 /* Define shapes for instruction operands. The following mnemonic characters
11511 are used in this table:
11513 F - VFP S<n> register
11514 D - Neon D<n> register
11515 Q - Neon Q<n> register
11519 L - D<n> register list
11521 This table is used to generate various data:
11522 - enumerations of the form NS_DDR to be used as arguments to
11524 - a table classifying shapes into single, double, quad, mixed.
11525 - a table used to drive neon_select_shape. */
11527 #define NEON_SHAPE_DEF \
11528 X(3, (D, D, D), DOUBLE), \
11529 X(3, (Q, Q, Q), QUAD), \
11530 X(3, (D, D, I), DOUBLE), \
11531 X(3, (Q, Q, I), QUAD), \
11532 X(3, (D, D, S), DOUBLE), \
11533 X(3, (Q, Q, S), QUAD), \
11534 X(2, (D, D), DOUBLE), \
11535 X(2, (Q, Q), QUAD), \
11536 X(2, (D, S), DOUBLE), \
11537 X(2, (Q, S), QUAD), \
11538 X(2, (D, R), DOUBLE), \
11539 X(2, (Q, R), QUAD), \
11540 X(2, (D, I), DOUBLE), \
11541 X(2, (Q, I), QUAD), \
11542 X(3, (D, L, D), DOUBLE), \
11543 X(2, (D, Q), MIXED), \
11544 X(2, (Q, D), MIXED), \
11545 X(3, (D, Q, I), MIXED), \
11546 X(3, (Q, D, I), MIXED), \
11547 X(3, (Q, D, D), MIXED), \
11548 X(3, (D, Q, Q), MIXED), \
11549 X(3, (Q, Q, D), MIXED), \
11550 X(3, (Q, D, S), MIXED), \
11551 X(3, (D, Q, S), MIXED), \
11552 X(4, (D, D, D, I), DOUBLE), \
11553 X(4, (Q, Q, Q, I), QUAD), \
11554 X(2, (F, F), SINGLE), \
11555 X(3, (F, F, F), SINGLE), \
11556 X(2, (F, I), SINGLE), \
11557 X(2, (F, D), MIXED), \
11558 X(2, (D, F), MIXED), \
11559 X(3, (F, F, I), MIXED), \
11560 X(4, (R, R, F, F), SINGLE), \
11561 X(4, (F, F, R, R), SINGLE), \
11562 X(3, (D, R, R), DOUBLE), \
11563 X(3, (R, R, D), DOUBLE), \
11564 X(2, (S, R), SINGLE), \
11565 X(2, (R, S), SINGLE), \
11566 X(2, (F, R), SINGLE), \
11567 X(2, (R, F), SINGLE)
11569 #define S2(A,B) NS_##A##B
11570 #define S3(A,B,C) NS_##A##B##C
11571 #define S4(A,B,C,D) NS_##A##B##C##D
11573 #define X(N, L, C) S##N L
11586 enum neon_shape_class
11594 #define X(N, L, C) SC_##C
11596 static enum neon_shape_class neon_shape_class
[] =
11614 /* Register widths of above. */
11615 static unsigned neon_shape_el_size
[] =
11626 struct neon_shape_info
11629 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11632 #define S2(A,B) { SE_##A, SE_##B }
11633 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11634 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11636 #define X(N, L, C) { N, S##N L }
11638 static struct neon_shape_info neon_shape_tab
[] =
11648 /* Bit masks used in type checking given instructions.
11649 'N_EQK' means the type must be the same as (or based on in some way) the key
11650 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11651 set, various other bits can be set as well in order to modify the meaning of
11652 the type constraint. */
11654 enum neon_type_mask
11677 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11678 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11679 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11680 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11681 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11682 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11683 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11684 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11685 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11686 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11688 N_MAX_NONSPECIAL
= N_F64
11691 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11693 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11694 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11695 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11696 #define N_SUF_32 (N_SU_32 | N_F32)
11697 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11698 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11700 /* Pass this as the first type argument to neon_check_type to ignore types
11702 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11704 /* Select a "shape" for the current instruction (describing register types or
11705 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11706 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11707 function of operand parsing, so this function doesn't need to be called.
11708 Shapes should be listed in order of decreasing length. */
11710 static enum neon_shape
11711 neon_select_shape (enum neon_shape shape
, ...)
11714 enum neon_shape first_shape
= shape
;
11716 /* Fix missing optional operands. FIXME: we don't know at this point how
11717 many arguments we should have, so this makes the assumption that we have
11718 > 1. This is true of all current Neon opcodes, I think, but may not be
11719 true in the future. */
11720 if (!inst
.operands
[1].present
)
11721 inst
.operands
[1] = inst
.operands
[0];
11723 va_start (ap
, shape
);
11725 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11730 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11732 if (!inst
.operands
[j
].present
)
11738 switch (neon_shape_tab
[shape
].el
[j
])
11741 if (!(inst
.operands
[j
].isreg
11742 && inst
.operands
[j
].isvec
11743 && inst
.operands
[j
].issingle
11744 && !inst
.operands
[j
].isquad
))
11749 if (!(inst
.operands
[j
].isreg
11750 && inst
.operands
[j
].isvec
11751 && !inst
.operands
[j
].isquad
11752 && !inst
.operands
[j
].issingle
))
11757 if (!(inst
.operands
[j
].isreg
11758 && !inst
.operands
[j
].isvec
))
11763 if (!(inst
.operands
[j
].isreg
11764 && inst
.operands
[j
].isvec
11765 && inst
.operands
[j
].isquad
11766 && !inst
.operands
[j
].issingle
))
11771 if (!(!inst
.operands
[j
].isreg
11772 && !inst
.operands
[j
].isscalar
))
11777 if (!(!inst
.operands
[j
].isreg
11778 && inst
.operands
[j
].isscalar
))
11792 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11793 first_error (_("invalid instruction shape"));
11798 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11799 means the Q bit should be set). */
11802 neon_quad (enum neon_shape shape
)
11804 return neon_shape_class
[shape
] == SC_QUAD
;
11808 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11811 /* Allow modification to be made to types which are constrained to be
11812 based on the key element, based on bits set alongside N_EQK. */
11813 if ((typebits
& N_EQK
) != 0)
11815 if ((typebits
& N_HLF
) != 0)
11817 else if ((typebits
& N_DBL
) != 0)
11819 if ((typebits
& N_SGN
) != 0)
11820 *g_type
= NT_signed
;
11821 else if ((typebits
& N_UNS
) != 0)
11822 *g_type
= NT_unsigned
;
11823 else if ((typebits
& N_INT
) != 0)
11824 *g_type
= NT_integer
;
11825 else if ((typebits
& N_FLT
) != 0)
11826 *g_type
= NT_float
;
11827 else if ((typebits
& N_SIZ
) != 0)
11828 *g_type
= NT_untyped
;
11832 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11833 operand type, i.e. the single type specified in a Neon instruction when it
11834 is the only one given. */
11836 static struct neon_type_el
11837 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11839 struct neon_type_el dest
= *key
;
11841 gas_assert ((thisarg
& N_EQK
) != 0);
11843 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11848 /* Convert Neon type and size into compact bitmask representation. */
11850 static enum neon_type_mask
11851 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11858 case 8: return N_8
;
11859 case 16: return N_16
;
11860 case 32: return N_32
;
11861 case 64: return N_64
;
11869 case 8: return N_I8
;
11870 case 16: return N_I16
;
11871 case 32: return N_I32
;
11872 case 64: return N_I64
;
11880 case 16: return N_F16
;
11881 case 32: return N_F32
;
11882 case 64: return N_F64
;
11890 case 8: return N_P8
;
11891 case 16: return N_P16
;
11899 case 8: return N_S8
;
11900 case 16: return N_S16
;
11901 case 32: return N_S32
;
11902 case 64: return N_S64
;
11910 case 8: return N_U8
;
11911 case 16: return N_U16
;
11912 case 32: return N_U32
;
11913 case 64: return N_U64
;
11924 /* Convert compact Neon bitmask type representation to a type and size. Only
11925 handles the case where a single bit is set in the mask. */
11928 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11929 enum neon_type_mask mask
)
11931 if ((mask
& N_EQK
) != 0)
11934 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11936 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11938 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11940 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11945 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11947 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11948 *type
= NT_unsigned
;
11949 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11950 *type
= NT_integer
;
11951 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11952 *type
= NT_untyped
;
11953 else if ((mask
& (N_P8
| N_P16
)) != 0)
11955 else if ((mask
& (N_F32
| N_F64
)) != 0)
11963 /* Modify a bitmask of allowed types. This is only needed for type
11967 modify_types_allowed (unsigned allowed
, unsigned mods
)
11970 enum neon_el_type type
;
11976 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11978 if (el_type_of_type_chk (&type
, &size
,
11979 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
11981 neon_modify_type_size (mods
, &type
, &size
);
11982 destmask
|= type_chk_of_el_type (type
, size
);
11989 /* Check type and return type classification.
11990 The manual states (paraphrase): If one datatype is given, it indicates the
11992 - the second operand, if there is one
11993 - the operand, if there is no second operand
11994 - the result, if there are no operands.
11995 This isn't quite good enough though, so we use a concept of a "key" datatype
11996 which is set on a per-instruction basis, which is the one which matters when
11997 only one data type is written.
11998 Note: this function has side-effects (e.g. filling in missing operands). All
11999 Neon instructions should call it before performing bit encoding. */
12001 static struct neon_type_el
12002 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12005 unsigned i
, pass
, key_el
= 0;
12006 unsigned types
[NEON_MAX_TYPE_ELS
];
12007 enum neon_el_type k_type
= NT_invtype
;
12008 unsigned k_size
= -1u;
12009 struct neon_type_el badtype
= {NT_invtype
, -1};
12010 unsigned key_allowed
= 0;
12012 /* Optional registers in Neon instructions are always (not) in operand 1.
12013 Fill in the missing operand here, if it was omitted. */
12014 if (els
> 1 && !inst
.operands
[1].present
)
12015 inst
.operands
[1] = inst
.operands
[0];
12017 /* Suck up all the varargs. */
12019 for (i
= 0; i
< els
; i
++)
12021 unsigned thisarg
= va_arg (ap
, unsigned);
12022 if (thisarg
== N_IGNORE_TYPE
)
12027 types
[i
] = thisarg
;
12028 if ((thisarg
& N_KEY
) != 0)
12033 if (inst
.vectype
.elems
> 0)
12034 for (i
= 0; i
< els
; i
++)
12035 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12037 first_error (_("types specified in both the mnemonic and operands"));
12041 /* Duplicate inst.vectype elements here as necessary.
12042 FIXME: No idea if this is exactly the same as the ARM assembler,
12043 particularly when an insn takes one register and one non-register
12045 if (inst
.vectype
.elems
== 1 && els
> 1)
12048 inst
.vectype
.elems
= els
;
12049 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12050 for (j
= 0; j
< els
; j
++)
12052 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12055 else if (inst
.vectype
.elems
== 0 && els
> 0)
12058 /* No types were given after the mnemonic, so look for types specified
12059 after each operand. We allow some flexibility here; as long as the
12060 "key" operand has a type, we can infer the others. */
12061 for (j
= 0; j
< els
; j
++)
12062 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12063 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12065 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12067 for (j
= 0; j
< els
; j
++)
12068 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12069 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12074 first_error (_("operand types can't be inferred"));
12078 else if (inst
.vectype
.elems
!= els
)
12080 first_error (_("type specifier has the wrong number of parts"));
12084 for (pass
= 0; pass
< 2; pass
++)
12086 for (i
= 0; i
< els
; i
++)
12088 unsigned thisarg
= types
[i
];
12089 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12090 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12091 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12092 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12094 /* Decay more-specific signed & unsigned types to sign-insensitive
12095 integer types if sign-specific variants are unavailable. */
12096 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12097 && (types_allowed
& N_SU_ALL
) == 0)
12098 g_type
= NT_integer
;
12100 /* If only untyped args are allowed, decay any more specific types to
12101 them. Some instructions only care about signs for some element
12102 sizes, so handle that properly. */
12103 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12104 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12105 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12106 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12107 g_type
= NT_untyped
;
12111 if ((thisarg
& N_KEY
) != 0)
12115 key_allowed
= thisarg
& ~N_KEY
;
12120 if ((thisarg
& N_VFP
) != 0)
12122 enum neon_shape_el regshape
;
12123 unsigned regwidth
, match
;
12125 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12128 first_error (_("invalid instruction shape"));
12131 regshape
= neon_shape_tab
[ns
].el
[i
];
12132 regwidth
= neon_shape_el_size
[regshape
];
12134 /* In VFP mode, operands must match register widths. If we
12135 have a key operand, use its width, else use the width of
12136 the current operand. */
12142 if (regwidth
!= match
)
12144 first_error (_("operand size must match register width"));
12149 if ((thisarg
& N_EQK
) == 0)
12151 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12153 if ((given_type
& types_allowed
) == 0)
12155 first_error (_("bad type in Neon instruction"));
12161 enum neon_el_type mod_k_type
= k_type
;
12162 unsigned mod_k_size
= k_size
;
12163 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12164 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12166 first_error (_("inconsistent types in Neon instruction"));
12174 return inst
.vectype
.el
[key_el
];
12177 /* Neon-style VFP instruction forwarding. */
12179 /* Thumb VFP instructions have 0xE in the condition field. */
12182 do_vfp_cond_or_thumb (void)
12187 inst
.instruction
|= 0xe0000000;
12189 inst
.instruction
|= inst
.cond
<< 28;
12192 /* Look up and encode a simple mnemonic, for use as a helper function for the
12193 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12194 etc. It is assumed that operand parsing has already been done, and that the
12195 operands are in the form expected by the given opcode (this isn't necessarily
12196 the same as the form in which they were parsed, hence some massaging must
12197 take place before this function is called).
12198 Checks current arch version against that in the looked-up opcode. */
12201 do_vfp_nsyn_opcode (const char *opname
)
12203 const struct asm_opcode
*opcode
;
12205 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12210 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12211 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12218 inst
.instruction
= opcode
->tvalue
;
12219 opcode
->tencode ();
12223 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12224 opcode
->aencode ();
12229 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12231 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12236 do_vfp_nsyn_opcode ("fadds");
12238 do_vfp_nsyn_opcode ("fsubs");
12243 do_vfp_nsyn_opcode ("faddd");
12245 do_vfp_nsyn_opcode ("fsubd");
12249 /* Check operand types to see if this is a VFP instruction, and if so call
12253 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12255 enum neon_shape rs
;
12256 struct neon_type_el et
;
12261 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12262 et
= neon_check_type (2, rs
,
12263 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12267 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12268 et
= neon_check_type (3, rs
,
12269 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12276 if (et
.type
!= NT_invtype
)
12287 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12289 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12294 do_vfp_nsyn_opcode ("fmacs");
12296 do_vfp_nsyn_opcode ("fnmacs");
12301 do_vfp_nsyn_opcode ("fmacd");
12303 do_vfp_nsyn_opcode ("fnmacd");
12308 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12310 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12315 do_vfp_nsyn_opcode ("ffmas");
12317 do_vfp_nsyn_opcode ("ffnmas");
12322 do_vfp_nsyn_opcode ("ffmad");
12324 do_vfp_nsyn_opcode ("ffnmad");
12329 do_vfp_nsyn_mul (enum neon_shape rs
)
12332 do_vfp_nsyn_opcode ("fmuls");
12334 do_vfp_nsyn_opcode ("fmuld");
12338 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12340 int is_neg
= (inst
.instruction
& 0x80) != 0;
12341 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12346 do_vfp_nsyn_opcode ("fnegs");
12348 do_vfp_nsyn_opcode ("fabss");
12353 do_vfp_nsyn_opcode ("fnegd");
12355 do_vfp_nsyn_opcode ("fabsd");
12359 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12360 insns belong to Neon, and are handled elsewhere. */
12363 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12365 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12369 do_vfp_nsyn_opcode ("fldmdbs");
12371 do_vfp_nsyn_opcode ("fldmias");
12376 do_vfp_nsyn_opcode ("fstmdbs");
12378 do_vfp_nsyn_opcode ("fstmias");
12383 do_vfp_nsyn_sqrt (void)
12385 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12386 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12389 do_vfp_nsyn_opcode ("fsqrts");
12391 do_vfp_nsyn_opcode ("fsqrtd");
12395 do_vfp_nsyn_div (void)
12397 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12398 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12399 N_F32
| N_F64
| N_KEY
| N_VFP
);
12402 do_vfp_nsyn_opcode ("fdivs");
12404 do_vfp_nsyn_opcode ("fdivd");
12408 do_vfp_nsyn_nmul (void)
12410 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12411 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12412 N_F32
| N_F64
| N_KEY
| N_VFP
);
12416 NEON_ENCODE (SINGLE
, inst
);
12417 do_vfp_sp_dyadic ();
12421 NEON_ENCODE (DOUBLE
, inst
);
12422 do_vfp_dp_rd_rn_rm ();
12424 do_vfp_cond_or_thumb ();
12428 do_vfp_nsyn_cmp (void)
12430 if (inst
.operands
[1].isreg
)
12432 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12433 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12437 NEON_ENCODE (SINGLE
, inst
);
12438 do_vfp_sp_monadic ();
12442 NEON_ENCODE (DOUBLE
, inst
);
12443 do_vfp_dp_rd_rm ();
12448 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12449 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12451 switch (inst
.instruction
& 0x0fffffff)
12454 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12457 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12465 NEON_ENCODE (SINGLE
, inst
);
12466 do_vfp_sp_compare_z ();
12470 NEON_ENCODE (DOUBLE
, inst
);
12474 do_vfp_cond_or_thumb ();
12478 nsyn_insert_sp (void)
12480 inst
.operands
[1] = inst
.operands
[0];
12481 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12482 inst
.operands
[0].reg
= REG_SP
;
12483 inst
.operands
[0].isreg
= 1;
12484 inst
.operands
[0].writeback
= 1;
12485 inst
.operands
[0].present
= 1;
12489 do_vfp_nsyn_push (void)
12492 if (inst
.operands
[1].issingle
)
12493 do_vfp_nsyn_opcode ("fstmdbs");
12495 do_vfp_nsyn_opcode ("fstmdbd");
12499 do_vfp_nsyn_pop (void)
12502 if (inst
.operands
[1].issingle
)
12503 do_vfp_nsyn_opcode ("fldmias");
12505 do_vfp_nsyn_opcode ("fldmiad");
12508 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12509 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12512 neon_dp_fixup (struct arm_it
* insn
)
12514 unsigned int i
= insn
->instruction
;
12519 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12530 insn
->instruction
= i
;
12533 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12537 neon_logbits (unsigned x
)
12539 return ffs (x
) - 4;
12542 #define LOW4(R) ((R) & 0xf)
12543 #define HI1(R) (((R) >> 4) & 1)
12545 /* Encode insns with bit pattern:
12547 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12548 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12550 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12551 different meaning for some instruction. */
12554 neon_three_same (int isquad
, int ubit
, int size
)
12556 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12557 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12558 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12559 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12560 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12561 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12562 inst
.instruction
|= (isquad
!= 0) << 6;
12563 inst
.instruction
|= (ubit
!= 0) << 24;
12565 inst
.instruction
|= neon_logbits (size
) << 20;
12567 neon_dp_fixup (&inst
);
12570 /* Encode instructions of the form:
12572 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12573 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12575 Don't write size if SIZE == -1. */
12578 neon_two_same (int qbit
, int ubit
, int size
)
12580 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12581 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12582 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12583 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12584 inst
.instruction
|= (qbit
!= 0) << 6;
12585 inst
.instruction
|= (ubit
!= 0) << 24;
12588 inst
.instruction
|= neon_logbits (size
) << 18;
12590 neon_dp_fixup (&inst
);
12593 /* Neon instruction encoders, in approximate order of appearance. */
12596 do_neon_dyadic_i_su (void)
12598 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12599 struct neon_type_el et
= neon_check_type (3, rs
,
12600 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12601 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12605 do_neon_dyadic_i64_su (void)
12607 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12608 struct neon_type_el et
= neon_check_type (3, rs
,
12609 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12610 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12614 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12617 unsigned size
= et
.size
>> 3;
12618 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12619 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12620 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12621 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12622 inst
.instruction
|= (isquad
!= 0) << 6;
12623 inst
.instruction
|= immbits
<< 16;
12624 inst
.instruction
|= (size
>> 3) << 7;
12625 inst
.instruction
|= (size
& 0x7) << 19;
12627 inst
.instruction
|= (uval
!= 0) << 24;
12629 neon_dp_fixup (&inst
);
12633 do_neon_shl_imm (void)
12635 if (!inst
.operands
[2].isreg
)
12637 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12638 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12639 NEON_ENCODE (IMMED
, inst
);
12640 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12644 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12645 struct neon_type_el et
= neon_check_type (3, rs
,
12646 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12649 /* VSHL/VQSHL 3-register variants have syntax such as:
12651 whereas other 3-register operations encoded by neon_three_same have
12654 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12656 tmp
= inst
.operands
[2].reg
;
12657 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12658 inst
.operands
[1].reg
= tmp
;
12659 NEON_ENCODE (INTEGER
, inst
);
12660 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12665 do_neon_qshl_imm (void)
12667 if (!inst
.operands
[2].isreg
)
12669 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12670 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12672 NEON_ENCODE (IMMED
, inst
);
12673 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12674 inst
.operands
[2].imm
);
12678 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12679 struct neon_type_el et
= neon_check_type (3, rs
,
12680 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12683 /* See note in do_neon_shl_imm. */
12684 tmp
= inst
.operands
[2].reg
;
12685 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12686 inst
.operands
[1].reg
= tmp
;
12687 NEON_ENCODE (INTEGER
, inst
);
12688 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12693 do_neon_rshl (void)
12695 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12696 struct neon_type_el et
= neon_check_type (3, rs
,
12697 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12700 tmp
= inst
.operands
[2].reg
;
12701 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12702 inst
.operands
[1].reg
= tmp
;
12703 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12707 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12709 /* Handle .I8 pseudo-instructions. */
12712 /* Unfortunately, this will make everything apart from zero out-of-range.
12713 FIXME is this the intended semantics? There doesn't seem much point in
12714 accepting .I8 if so. */
12715 immediate
|= immediate
<< 8;
12721 if (immediate
== (immediate
& 0x000000ff))
12723 *immbits
= immediate
;
12726 else if (immediate
== (immediate
& 0x0000ff00))
12728 *immbits
= immediate
>> 8;
12731 else if (immediate
== (immediate
& 0x00ff0000))
12733 *immbits
= immediate
>> 16;
12736 else if (immediate
== (immediate
& 0xff000000))
12738 *immbits
= immediate
>> 24;
12741 if ((immediate
& 0xffff) != (immediate
>> 16))
12742 goto bad_immediate
;
12743 immediate
&= 0xffff;
12746 if (immediate
== (immediate
& 0x000000ff))
12748 *immbits
= immediate
;
12751 else if (immediate
== (immediate
& 0x0000ff00))
12753 *immbits
= immediate
>> 8;
12758 first_error (_("immediate value out of range"));
12762 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12766 neon_bits_same_in_bytes (unsigned imm
)
12768 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12769 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12770 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12771 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12774 /* For immediate of above form, return 0bABCD. */
12777 neon_squash_bits (unsigned imm
)
12779 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12780 | ((imm
& 0x01000000) >> 21);
12783 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12786 neon_qfloat_bits (unsigned imm
)
12788 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12791 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12792 the instruction. *OP is passed as the initial value of the op field, and
12793 may be set to a different value depending on the constant (i.e.
12794 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12795 MVN). If the immediate looks like a repeated pattern then also
12796 try smaller element sizes. */
12799 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12800 unsigned *immbits
, int *op
, int size
,
12801 enum neon_el_type type
)
12803 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12805 if (type
== NT_float
&& !float_p
)
12808 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12810 if (size
!= 32 || *op
== 1)
12812 *immbits
= neon_qfloat_bits (immlo
);
12818 if (neon_bits_same_in_bytes (immhi
)
12819 && neon_bits_same_in_bytes (immlo
))
12823 *immbits
= (neon_squash_bits (immhi
) << 4)
12824 | neon_squash_bits (immlo
);
12829 if (immhi
!= immlo
)
12835 if (immlo
== (immlo
& 0x000000ff))
12840 else if (immlo
== (immlo
& 0x0000ff00))
12842 *immbits
= immlo
>> 8;
12845 else if (immlo
== (immlo
& 0x00ff0000))
12847 *immbits
= immlo
>> 16;
12850 else if (immlo
== (immlo
& 0xff000000))
12852 *immbits
= immlo
>> 24;
12855 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12857 *immbits
= (immlo
>> 8) & 0xff;
12860 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12862 *immbits
= (immlo
>> 16) & 0xff;
12866 if ((immlo
& 0xffff) != (immlo
>> 16))
12873 if (immlo
== (immlo
& 0x000000ff))
12878 else if (immlo
== (immlo
& 0x0000ff00))
12880 *immbits
= immlo
>> 8;
12884 if ((immlo
& 0xff) != (immlo
>> 8))
12889 if (immlo
== (immlo
& 0x000000ff))
12891 /* Don't allow MVN with 8-bit immediate. */
12901 /* Write immediate bits [7:0] to the following locations:
12903 |28/24|23 19|18 16|15 4|3 0|
12904 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12906 This function is used by VMOV/VMVN/VORR/VBIC. */
12909 neon_write_immbits (unsigned immbits
)
12911 inst
.instruction
|= immbits
& 0xf;
12912 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12913 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12916 /* Invert low-order SIZE bits of XHI:XLO. */
12919 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12921 unsigned immlo
= xlo
? *xlo
: 0;
12922 unsigned immhi
= xhi
? *xhi
: 0;
12927 immlo
= (~immlo
) & 0xff;
12931 immlo
= (~immlo
) & 0xffff;
12935 immhi
= (~immhi
) & 0xffffffff;
12936 /* fall through. */
12939 immlo
= (~immlo
) & 0xffffffff;
12954 do_neon_logic (void)
12956 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12958 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12959 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12960 /* U bit and size field were set as part of the bitmask. */
12961 NEON_ENCODE (INTEGER
, inst
);
12962 neon_three_same (neon_quad (rs
), 0, -1);
12966 const int three_ops_form
= (inst
.operands
[2].present
12967 && !inst
.operands
[2].isreg
);
12968 const int immoperand
= (three_ops_form
? 2 : 1);
12969 enum neon_shape rs
= (three_ops_form
12970 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
12971 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
12972 struct neon_type_el et
= neon_check_type (2, rs
,
12973 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12974 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
12978 if (et
.type
== NT_invtype
)
12981 if (three_ops_form
)
12982 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12983 _("first and second operands shall be the same register"));
12985 NEON_ENCODE (IMMED
, inst
);
12987 immbits
= inst
.operands
[immoperand
].imm
;
12990 /* .i64 is a pseudo-op, so the immediate must be a repeating
12992 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
12993 inst
.operands
[immoperand
].reg
: 0))
12995 /* Set immbits to an invalid constant. */
12996 immbits
= 0xdeadbeef;
13003 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13007 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13011 /* Pseudo-instruction for VBIC. */
13012 neon_invert_size (&immbits
, 0, et
.size
);
13013 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13017 /* Pseudo-instruction for VORR. */
13018 neon_invert_size (&immbits
, 0, et
.size
);
13019 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13029 inst
.instruction
|= neon_quad (rs
) << 6;
13030 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13031 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13032 inst
.instruction
|= cmode
<< 8;
13033 neon_write_immbits (immbits
);
13035 neon_dp_fixup (&inst
);
13040 do_neon_bitfield (void)
13042 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13043 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13044 neon_three_same (neon_quad (rs
), 0, -1);
13048 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13051 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13052 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13054 if (et
.type
== NT_float
)
13056 NEON_ENCODE (FLOAT
, inst
);
13057 neon_three_same (neon_quad (rs
), 0, -1);
13061 NEON_ENCODE (INTEGER
, inst
);
13062 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13067 do_neon_dyadic_if_su (void)
13069 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13073 do_neon_dyadic_if_su_d (void)
13075 /* This version only allow D registers, but that constraint is enforced during
13076 operand parsing so we don't need to do anything extra here. */
13077 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13081 do_neon_dyadic_if_i_d (void)
13083 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13084 affected if we specify unsigned args. */
13085 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13088 enum vfp_or_neon_is_neon_bits
13091 NEON_CHECK_ARCH
= 2
13094 /* Call this function if an instruction which may have belonged to the VFP or
13095 Neon instruction sets, but turned out to be a Neon instruction (due to the
13096 operand types involved, etc.). We have to check and/or fix-up a couple of
13099 - Make sure the user hasn't attempted to make a Neon instruction
13101 - Alter the value in the condition code field if necessary.
13102 - Make sure that the arch supports Neon instructions.
13104 Which of these operations take place depends on bits from enum
13105 vfp_or_neon_is_neon_bits.
13107 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13108 current instruction's condition is COND_ALWAYS, the condition field is
13109 changed to inst.uncond_value. This is necessary because instructions shared
13110 between VFP and Neon may be conditional for the VFP variants only, and the
13111 unconditional Neon version must have, e.g., 0xF in the condition field. */
13114 vfp_or_neon_is_neon (unsigned check
)
13116 /* Conditions are always legal in Thumb mode (IT blocks). */
13117 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13119 if (inst
.cond
!= COND_ALWAYS
)
13121 first_error (_(BAD_COND
));
13124 if (inst
.uncond_value
!= -1)
13125 inst
.instruction
|= inst
.uncond_value
<< 28;
13128 if ((check
& NEON_CHECK_ARCH
)
13129 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13131 first_error (_(BAD_FPU
));
13139 do_neon_addsub_if_i (void)
13141 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13144 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13147 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13148 affected if we specify unsigned args. */
13149 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13152 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13154 V<op> A,B (A is operand 0, B is operand 2)
13159 so handle that case specially. */
13162 neon_exchange_operands (void)
13164 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13165 if (inst
.operands
[1].present
)
13167 /* Swap operands[1] and operands[2]. */
13168 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13169 inst
.operands
[1] = inst
.operands
[2];
13170 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13174 inst
.operands
[1] = inst
.operands
[2];
13175 inst
.operands
[2] = inst
.operands
[0];
13180 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13182 if (inst
.operands
[2].isreg
)
13185 neon_exchange_operands ();
13186 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13190 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13191 struct neon_type_el et
= neon_check_type (2, rs
,
13192 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13194 NEON_ENCODE (IMMED
, inst
);
13195 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13196 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13197 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13198 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13199 inst
.instruction
|= neon_quad (rs
) << 6;
13200 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13201 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13203 neon_dp_fixup (&inst
);
13210 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13214 do_neon_cmp_inv (void)
13216 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13222 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13225 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13226 scalars, which are encoded in 5 bits, M : Rm.
13227 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13228 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13232 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13234 unsigned regno
= NEON_SCALAR_REG (scalar
);
13235 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13240 if (regno
> 7 || elno
> 3)
13242 return regno
| (elno
<< 3);
13245 if (regno
> 15 || elno
> 1)
13247 return regno
| (elno
<< 4);
13251 first_error (_("scalar out of range for multiply instruction"));
13257 /* Encode multiply / multiply-accumulate scalar instructions. */
13260 neon_mul_mac (struct neon_type_el et
, int ubit
)
13264 /* Give a more helpful error message if we have an invalid type. */
13265 if (et
.type
== NT_invtype
)
13268 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13269 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13270 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13271 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13272 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13273 inst
.instruction
|= LOW4 (scalar
);
13274 inst
.instruction
|= HI1 (scalar
) << 5;
13275 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13276 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13277 inst
.instruction
|= (ubit
!= 0) << 24;
13279 neon_dp_fixup (&inst
);
13283 do_neon_mac_maybe_scalar (void)
13285 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13288 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13291 if (inst
.operands
[2].isscalar
)
13293 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13294 struct neon_type_el et
= neon_check_type (3, rs
,
13295 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13296 NEON_ENCODE (SCALAR
, inst
);
13297 neon_mul_mac (et
, neon_quad (rs
));
13301 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13302 affected if we specify unsigned args. */
13303 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13308 do_neon_fmac (void)
13310 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13313 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13316 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13322 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13323 struct neon_type_el et
= neon_check_type (3, rs
,
13324 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13325 neon_three_same (neon_quad (rs
), 0, et
.size
);
13328 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13329 same types as the MAC equivalents. The polynomial type for this instruction
13330 is encoded the same as the integer type. */
13335 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13338 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13341 if (inst
.operands
[2].isscalar
)
13342 do_neon_mac_maybe_scalar ();
13344 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13348 do_neon_qdmulh (void)
13350 if (inst
.operands
[2].isscalar
)
13352 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13353 struct neon_type_el et
= neon_check_type (3, rs
,
13354 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13355 NEON_ENCODE (SCALAR
, inst
);
13356 neon_mul_mac (et
, neon_quad (rs
));
13360 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13361 struct neon_type_el et
= neon_check_type (3, rs
,
13362 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13363 NEON_ENCODE (INTEGER
, inst
);
13364 /* The U bit (rounding) comes from bit mask. */
13365 neon_three_same (neon_quad (rs
), 0, et
.size
);
13370 do_neon_fcmp_absolute (void)
13372 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13373 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13374 /* Size field comes from bit mask. */
13375 neon_three_same (neon_quad (rs
), 1, -1);
13379 do_neon_fcmp_absolute_inv (void)
13381 neon_exchange_operands ();
13382 do_neon_fcmp_absolute ();
13386 do_neon_step (void)
13388 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13389 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13390 neon_three_same (neon_quad (rs
), 0, -1);
13394 do_neon_abs_neg (void)
13396 enum neon_shape rs
;
13397 struct neon_type_el et
;
13399 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13402 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13405 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13406 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13408 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13409 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13410 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13411 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13412 inst
.instruction
|= neon_quad (rs
) << 6;
13413 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13414 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13416 neon_dp_fixup (&inst
);
13422 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13423 struct neon_type_el et
= neon_check_type (2, rs
,
13424 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13425 int imm
= inst
.operands
[2].imm
;
13426 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13427 _("immediate out of range for insert"));
13428 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13434 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13435 struct neon_type_el et
= neon_check_type (2, rs
,
13436 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13437 int imm
= inst
.operands
[2].imm
;
13438 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13439 _("immediate out of range for insert"));
13440 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13444 do_neon_qshlu_imm (void)
13446 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13447 struct neon_type_el et
= neon_check_type (2, rs
,
13448 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13449 int imm
= inst
.operands
[2].imm
;
13450 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13451 _("immediate out of range for shift"));
13452 /* Only encodes the 'U present' variant of the instruction.
13453 In this case, signed types have OP (bit 8) set to 0.
13454 Unsigned types have OP set to 1. */
13455 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13456 /* The rest of the bits are the same as other immediate shifts. */
13457 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13461 do_neon_qmovn (void)
13463 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13464 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13465 /* Saturating move where operands can be signed or unsigned, and the
13466 destination has the same signedness. */
13467 NEON_ENCODE (INTEGER
, inst
);
13468 if (et
.type
== NT_unsigned
)
13469 inst
.instruction
|= 0xc0;
13471 inst
.instruction
|= 0x80;
13472 neon_two_same (0, 1, et
.size
/ 2);
13476 do_neon_qmovun (void)
13478 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13479 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13480 /* Saturating move with unsigned results. Operands must be signed. */
13481 NEON_ENCODE (INTEGER
, inst
);
13482 neon_two_same (0, 1, et
.size
/ 2);
13486 do_neon_rshift_sat_narrow (void)
13488 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13489 or unsigned. If operands are unsigned, results must also be unsigned. */
13490 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13491 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13492 int imm
= inst
.operands
[2].imm
;
13493 /* This gets the bounds check, size encoding and immediate bits calculation
13497 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13498 VQMOVN.I<size> <Dd>, <Qm>. */
13501 inst
.operands
[2].present
= 0;
13502 inst
.instruction
= N_MNEM_vqmovn
;
13507 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13508 _("immediate out of range"));
13509 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13513 do_neon_rshift_sat_narrow_u (void)
13515 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13516 or unsigned. If operands are unsigned, results must also be unsigned. */
13517 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13518 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13519 int imm
= inst
.operands
[2].imm
;
13520 /* This gets the bounds check, size encoding and immediate bits calculation
13524 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13525 VQMOVUN.I<size> <Dd>, <Qm>. */
13528 inst
.operands
[2].present
= 0;
13529 inst
.instruction
= N_MNEM_vqmovun
;
13534 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13535 _("immediate out of range"));
13536 /* FIXME: The manual is kind of unclear about what value U should have in
13537 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13539 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13543 do_neon_movn (void)
13545 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13546 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13547 NEON_ENCODE (INTEGER
, inst
);
13548 neon_two_same (0, 1, et
.size
/ 2);
13552 do_neon_rshift_narrow (void)
13554 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13555 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13556 int imm
= inst
.operands
[2].imm
;
13557 /* This gets the bounds check, size encoding and immediate bits calculation
13561 /* If immediate is zero then we are a pseudo-instruction for
13562 VMOVN.I<size> <Dd>, <Qm> */
13565 inst
.operands
[2].present
= 0;
13566 inst
.instruction
= N_MNEM_vmovn
;
13571 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13572 _("immediate out of range for narrowing operation"));
13573 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13577 do_neon_shll (void)
13579 /* FIXME: Type checking when lengthening. */
13580 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13581 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13582 unsigned imm
= inst
.operands
[2].imm
;
13584 if (imm
== et
.size
)
13586 /* Maximum shift variant. */
13587 NEON_ENCODE (INTEGER
, inst
);
13588 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13589 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13590 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13591 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13592 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13594 neon_dp_fixup (&inst
);
13598 /* A more-specific type check for non-max versions. */
13599 et
= neon_check_type (2, NS_QDI
,
13600 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13601 NEON_ENCODE (IMMED
, inst
);
13602 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13606 /* Check the various types for the VCVT instruction, and return which version
13607 the current instruction is. */
13610 neon_cvt_flavour (enum neon_shape rs
)
13612 #define CVT_VAR(C,X,Y) \
13613 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13614 if (et.type != NT_invtype) \
13616 inst.error = NULL; \
13619 struct neon_type_el et
;
13620 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13621 || rs
== NS_FF
) ? N_VFP
: 0;
13622 /* The instruction versions which take an immediate take one register
13623 argument, which is extended to the width of the full register. Thus the
13624 "source" and "destination" registers must have the same width. Hack that
13625 here by making the size equal to the key (wider, in this case) operand. */
13626 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13628 CVT_VAR (0, N_S32
, N_F32
);
13629 CVT_VAR (1, N_U32
, N_F32
);
13630 CVT_VAR (2, N_F32
, N_S32
);
13631 CVT_VAR (3, N_F32
, N_U32
);
13632 /* Half-precision conversions. */
13633 CVT_VAR (4, N_F32
, N_F16
);
13634 CVT_VAR (5, N_F16
, N_F32
);
13638 /* VFP instructions. */
13639 CVT_VAR (6, N_F32
, N_F64
);
13640 CVT_VAR (7, N_F64
, N_F32
);
13641 CVT_VAR (8, N_S32
, N_F64
| key
);
13642 CVT_VAR (9, N_U32
, N_F64
| key
);
13643 CVT_VAR (10, N_F64
| key
, N_S32
);
13644 CVT_VAR (11, N_F64
| key
, N_U32
);
13645 /* VFP instructions with bitshift. */
13646 CVT_VAR (12, N_F32
| key
, N_S16
);
13647 CVT_VAR (13, N_F32
| key
, N_U16
);
13648 CVT_VAR (14, N_F64
| key
, N_S16
);
13649 CVT_VAR (15, N_F64
| key
, N_U16
);
13650 CVT_VAR (16, N_S16
, N_F32
| key
);
13651 CVT_VAR (17, N_U16
, N_F32
| key
);
13652 CVT_VAR (18, N_S16
, N_F64
| key
);
13653 CVT_VAR (19, N_U16
, N_F64
| key
);
13659 /* Neon-syntax VFP conversions. */
13662 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13664 const char *opname
= 0;
13666 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13668 /* Conversions with immediate bitshift. */
13669 const char *enc
[] =
13693 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13695 opname
= enc
[flavour
];
13696 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13697 _("operands 0 and 1 must be the same register"));
13698 inst
.operands
[1] = inst
.operands
[2];
13699 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13704 /* Conversions without bitshift. */
13705 const char *enc
[] =
13721 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13722 opname
= enc
[flavour
];
13726 do_vfp_nsyn_opcode (opname
);
13730 do_vfp_nsyn_cvtz (void)
13732 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13733 int flavour
= neon_cvt_flavour (rs
);
13734 const char *enc
[] =
13748 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13749 do_vfp_nsyn_opcode (enc
[flavour
]);
13753 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13755 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13756 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13757 int flavour
= neon_cvt_flavour (rs
);
13759 /* PR11109: Handle round-to-zero for VCVT conversions. */
13761 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13762 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13763 && (rs
== NS_FD
|| rs
== NS_FF
))
13765 do_vfp_nsyn_cvtz ();
13769 /* VFP rather than Neon conversions. */
13772 do_vfp_nsyn_cvt (rs
, flavour
);
13782 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13784 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13787 /* Fixed-point conversion with #0 immediate is encoded as an
13788 integer conversion. */
13789 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13791 immbits
= 32 - inst
.operands
[2].imm
;
13792 NEON_ENCODE (IMMED
, inst
);
13794 inst
.instruction
|= enctab
[flavour
];
13795 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13796 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13797 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13798 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13799 inst
.instruction
|= neon_quad (rs
) << 6;
13800 inst
.instruction
|= 1 << 21;
13801 inst
.instruction
|= immbits
<< 16;
13803 neon_dp_fixup (&inst
);
13811 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13813 NEON_ENCODE (INTEGER
, inst
);
13815 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13819 inst
.instruction
|= enctab
[flavour
];
13821 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13822 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13823 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13824 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13825 inst
.instruction
|= neon_quad (rs
) << 6;
13826 inst
.instruction
|= 2 << 18;
13828 neon_dp_fixup (&inst
);
13832 /* Half-precision conversions for Advanced SIMD -- neon. */
13837 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13839 as_bad (_("operand size must match register width"));
13844 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13846 as_bad (_("operand size must match register width"));
13851 inst
.instruction
= 0x3b60600;
13853 inst
.instruction
= 0x3b60700;
13855 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13856 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13857 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13858 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13859 neon_dp_fixup (&inst
);
13863 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13864 do_vfp_nsyn_cvt (rs
, flavour
);
13869 do_neon_cvtr (void)
13871 do_neon_cvt_1 (FALSE
);
13877 do_neon_cvt_1 (TRUE
);
13881 do_neon_cvtb (void)
13883 inst
.instruction
= 0xeb20a40;
13885 /* The sizes are attached to the mnemonic. */
13886 if (inst
.vectype
.el
[0].type
!= NT_invtype
13887 && inst
.vectype
.el
[0].size
== 16)
13888 inst
.instruction
|= 0x00010000;
13890 /* Programmer's syntax: the sizes are attached to the operands. */
13891 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13892 && inst
.operands
[0].vectype
.size
== 16)
13893 inst
.instruction
|= 0x00010000;
13895 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13896 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13897 do_vfp_cond_or_thumb ();
13902 do_neon_cvtt (void)
13905 inst
.instruction
|= 0x80;
13909 neon_move_immediate (void)
13911 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13912 struct neon_type_el et
= neon_check_type (2, rs
,
13913 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13914 unsigned immlo
, immhi
= 0, immbits
;
13915 int op
, cmode
, float_p
;
13917 constraint (et
.type
== NT_invtype
,
13918 _("operand size must be specified for immediate VMOV"));
13920 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13921 op
= (inst
.instruction
& (1 << 5)) != 0;
13923 immlo
= inst
.operands
[1].imm
;
13924 if (inst
.operands
[1].regisimm
)
13925 immhi
= inst
.operands
[1].reg
;
13927 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13928 _("immediate has bits set outside the operand size"));
13930 float_p
= inst
.operands
[1].immisfloat
;
13932 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13933 et
.size
, et
.type
)) == FAIL
)
13935 /* Invert relevant bits only. */
13936 neon_invert_size (&immlo
, &immhi
, et
.size
);
13937 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13938 with one or the other; those cases are caught by
13939 neon_cmode_for_move_imm. */
13941 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13942 &op
, et
.size
, et
.type
)) == FAIL
)
13944 first_error (_("immediate out of range"));
13949 inst
.instruction
&= ~(1 << 5);
13950 inst
.instruction
|= op
<< 5;
13952 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13953 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13954 inst
.instruction
|= neon_quad (rs
) << 6;
13955 inst
.instruction
|= cmode
<< 8;
13957 neon_write_immbits (immbits
);
13963 if (inst
.operands
[1].isreg
)
13965 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13967 NEON_ENCODE (INTEGER
, inst
);
13968 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13969 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13970 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13971 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13972 inst
.instruction
|= neon_quad (rs
) << 6;
13976 NEON_ENCODE (IMMED
, inst
);
13977 neon_move_immediate ();
13980 neon_dp_fixup (&inst
);
13983 /* Encode instructions of form:
13985 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13986 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13989 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13991 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13992 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13993 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13994 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13995 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13996 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13997 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13998 inst
.instruction
|= neon_logbits (size
) << 20;
14000 neon_dp_fixup (&inst
);
14004 do_neon_dyadic_long (void)
14006 /* FIXME: Type checking for lengthening op. */
14007 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14008 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14009 neon_mixed_length (et
, et
.size
);
14013 do_neon_abal (void)
14015 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14016 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14017 neon_mixed_length (et
, et
.size
);
14021 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14023 if (inst
.operands
[2].isscalar
)
14025 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14026 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14027 NEON_ENCODE (SCALAR
, inst
);
14028 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14032 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14033 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14034 NEON_ENCODE (INTEGER
, inst
);
14035 neon_mixed_length (et
, et
.size
);
14040 do_neon_mac_maybe_scalar_long (void)
14042 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14046 do_neon_dyadic_wide (void)
14048 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14049 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14050 neon_mixed_length (et
, et
.size
);
14054 do_neon_dyadic_narrow (void)
14056 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14057 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14058 /* Operand sign is unimportant, and the U bit is part of the opcode,
14059 so force the operand type to integer. */
14060 et
.type
= NT_integer
;
14061 neon_mixed_length (et
, et
.size
/ 2);
14065 do_neon_mul_sat_scalar_long (void)
14067 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14071 do_neon_vmull (void)
14073 if (inst
.operands
[2].isscalar
)
14074 do_neon_mac_maybe_scalar_long ();
14077 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14078 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14079 if (et
.type
== NT_poly
)
14080 NEON_ENCODE (POLY
, inst
);
14082 NEON_ENCODE (INTEGER
, inst
);
14083 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14084 zero. Should be OK as-is. */
14085 neon_mixed_length (et
, et
.size
);
14092 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14093 struct neon_type_el et
= neon_check_type (3, rs
,
14094 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14095 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14097 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14098 _("shift out of range"));
14099 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14100 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14101 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14102 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14103 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14104 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14105 inst
.instruction
|= neon_quad (rs
) << 6;
14106 inst
.instruction
|= imm
<< 8;
14108 neon_dp_fixup (&inst
);
14114 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14115 struct neon_type_el et
= neon_check_type (2, rs
,
14116 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14117 unsigned op
= (inst
.instruction
>> 7) & 3;
14118 /* N (width of reversed regions) is encoded as part of the bitmask. We
14119 extract it here to check the elements to be reversed are smaller.
14120 Otherwise we'd get a reserved instruction. */
14121 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14122 gas_assert (elsize
!= 0);
14123 constraint (et
.size
>= elsize
,
14124 _("elements must be smaller than reversal region"));
14125 neon_two_same (neon_quad (rs
), 1, et
.size
);
14131 if (inst
.operands
[1].isscalar
)
14133 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14134 struct neon_type_el et
= neon_check_type (2, rs
,
14135 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14136 unsigned sizebits
= et
.size
>> 3;
14137 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14138 int logsize
= neon_logbits (et
.size
);
14139 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14141 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14144 NEON_ENCODE (SCALAR
, inst
);
14145 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14146 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14147 inst
.instruction
|= LOW4 (dm
);
14148 inst
.instruction
|= HI1 (dm
) << 5;
14149 inst
.instruction
|= neon_quad (rs
) << 6;
14150 inst
.instruction
|= x
<< 17;
14151 inst
.instruction
|= sizebits
<< 16;
14153 neon_dp_fixup (&inst
);
14157 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14158 struct neon_type_el et
= neon_check_type (2, rs
,
14159 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14160 /* Duplicate ARM register to lanes of vector. */
14161 NEON_ENCODE (ARMREG
, inst
);
14164 case 8: inst
.instruction
|= 0x400000; break;
14165 case 16: inst
.instruction
|= 0x000020; break;
14166 case 32: inst
.instruction
|= 0x000000; break;
14169 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14170 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14171 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14172 inst
.instruction
|= neon_quad (rs
) << 21;
14173 /* The encoding for this instruction is identical for the ARM and Thumb
14174 variants, except for the condition field. */
14175 do_vfp_cond_or_thumb ();
14179 /* VMOV has particularly many variations. It can be one of:
14180 0. VMOV<c><q> <Qd>, <Qm>
14181 1. VMOV<c><q> <Dd>, <Dm>
14182 (Register operations, which are VORR with Rm = Rn.)
14183 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14184 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14186 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14187 (ARM register to scalar.)
14188 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14189 (Two ARM registers to vector.)
14190 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14191 (Scalar to ARM register.)
14192 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14193 (Vector to two ARM registers.)
14194 8. VMOV.F32 <Sd>, <Sm>
14195 9. VMOV.F64 <Dd>, <Dm>
14196 (VFP register moves.)
14197 10. VMOV.F32 <Sd>, #imm
14198 11. VMOV.F64 <Dd>, #imm
14199 (VFP float immediate load.)
14200 12. VMOV <Rd>, <Sm>
14201 (VFP single to ARM reg.)
14202 13. VMOV <Sd>, <Rm>
14203 (ARM reg to VFP single.)
14204 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14205 (Two ARM regs to two VFP singles.)
14206 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14207 (Two VFP singles to two ARM regs.)
14209 These cases can be disambiguated using neon_select_shape, except cases 1/9
14210 and 3/11 which depend on the operand type too.
14212 All the encoded bits are hardcoded by this function.
14214 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14215 Cases 5, 7 may be used with VFPv2 and above.
14217 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14218 can specify a type where it doesn't make sense to, and is ignored). */
14223 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14224 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14226 struct neon_type_el et
;
14227 const char *ldconst
= 0;
14231 case NS_DD
: /* case 1/9. */
14232 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14233 /* It is not an error here if no type is given. */
14235 if (et
.type
== NT_float
&& et
.size
== 64)
14237 do_vfp_nsyn_opcode ("fcpyd");
14240 /* fall through. */
14242 case NS_QQ
: /* case 0/1. */
14244 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14246 /* The architecture manual I have doesn't explicitly state which
14247 value the U bit should have for register->register moves, but
14248 the equivalent VORR instruction has U = 0, so do that. */
14249 inst
.instruction
= 0x0200110;
14250 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14251 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14252 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14253 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14254 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14255 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14256 inst
.instruction
|= neon_quad (rs
) << 6;
14258 neon_dp_fixup (&inst
);
14262 case NS_DI
: /* case 3/11. */
14263 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14265 if (et
.type
== NT_float
&& et
.size
== 64)
14267 /* case 11 (fconstd). */
14268 ldconst
= "fconstd";
14269 goto encode_fconstd
;
14271 /* fall through. */
14273 case NS_QI
: /* case 2/3. */
14274 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14276 inst
.instruction
= 0x0800010;
14277 neon_move_immediate ();
14278 neon_dp_fixup (&inst
);
14281 case NS_SR
: /* case 4. */
14283 unsigned bcdebits
= 0;
14285 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14286 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14288 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14289 logsize
= neon_logbits (et
.size
);
14291 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14293 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14294 && et
.size
!= 32, _(BAD_FPU
));
14295 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14296 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14300 case 8: bcdebits
= 0x8; break;
14301 case 16: bcdebits
= 0x1; break;
14302 case 32: bcdebits
= 0x0; break;
14306 bcdebits
|= x
<< logsize
;
14308 inst
.instruction
= 0xe000b10;
14309 do_vfp_cond_or_thumb ();
14310 inst
.instruction
|= LOW4 (dn
) << 16;
14311 inst
.instruction
|= HI1 (dn
) << 7;
14312 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14313 inst
.instruction
|= (bcdebits
& 3) << 5;
14314 inst
.instruction
|= (bcdebits
>> 2) << 21;
14318 case NS_DRR
: /* case 5 (fmdrr). */
14319 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14322 inst
.instruction
= 0xc400b10;
14323 do_vfp_cond_or_thumb ();
14324 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14325 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14326 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14327 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14330 case NS_RS
: /* case 6. */
14333 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14334 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14335 unsigned abcdebits
= 0;
14337 et
= neon_check_type (2, NS_NULL
,
14338 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14339 logsize
= neon_logbits (et
.size
);
14341 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14343 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14344 && et
.size
!= 32, _(BAD_FPU
));
14345 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14346 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14350 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14351 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14352 case 32: abcdebits
= 0x00; break;
14356 abcdebits
|= x
<< logsize
;
14357 inst
.instruction
= 0xe100b10;
14358 do_vfp_cond_or_thumb ();
14359 inst
.instruction
|= LOW4 (dn
) << 16;
14360 inst
.instruction
|= HI1 (dn
) << 7;
14361 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14362 inst
.instruction
|= (abcdebits
& 3) << 5;
14363 inst
.instruction
|= (abcdebits
>> 2) << 21;
14367 case NS_RRD
: /* case 7 (fmrrd). */
14368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14371 inst
.instruction
= 0xc500b10;
14372 do_vfp_cond_or_thumb ();
14373 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14374 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14375 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14376 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14379 case NS_FF
: /* case 8 (fcpys). */
14380 do_vfp_nsyn_opcode ("fcpys");
14383 case NS_FI
: /* case 10 (fconsts). */
14384 ldconst
= "fconsts";
14386 if (is_quarter_float (inst
.operands
[1].imm
))
14388 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14389 do_vfp_nsyn_opcode (ldconst
);
14392 first_error (_("immediate out of range"));
14395 case NS_RF
: /* case 12 (fmrs). */
14396 do_vfp_nsyn_opcode ("fmrs");
14399 case NS_FR
: /* case 13 (fmsr). */
14400 do_vfp_nsyn_opcode ("fmsr");
14403 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14404 (one of which is a list), but we have parsed four. Do some fiddling to
14405 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14407 case NS_RRFF
: /* case 14 (fmrrs). */
14408 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14409 _("VFP registers must be adjacent"));
14410 inst
.operands
[2].imm
= 2;
14411 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14412 do_vfp_nsyn_opcode ("fmrrs");
14415 case NS_FFRR
: /* case 15 (fmsrr). */
14416 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14417 _("VFP registers must be adjacent"));
14418 inst
.operands
[1] = inst
.operands
[2];
14419 inst
.operands
[2] = inst
.operands
[3];
14420 inst
.operands
[0].imm
= 2;
14421 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14422 do_vfp_nsyn_opcode ("fmsrr");
14431 do_neon_rshift_round_imm (void)
14433 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14434 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14435 int imm
= inst
.operands
[2].imm
;
14437 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14440 inst
.operands
[2].present
= 0;
14445 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14446 _("immediate out of range for shift"));
14447 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14452 do_neon_movl (void)
14454 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14455 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14456 unsigned sizebits
= et
.size
>> 3;
14457 inst
.instruction
|= sizebits
<< 19;
14458 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14464 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14465 struct neon_type_el et
= neon_check_type (2, rs
,
14466 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14467 NEON_ENCODE (INTEGER
, inst
);
14468 neon_two_same (neon_quad (rs
), 1, et
.size
);
14472 do_neon_zip_uzp (void)
14474 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14475 struct neon_type_el et
= neon_check_type (2, rs
,
14476 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14477 if (rs
== NS_DD
&& et
.size
== 32)
14479 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14480 inst
.instruction
= N_MNEM_vtrn
;
14484 neon_two_same (neon_quad (rs
), 1, et
.size
);
14488 do_neon_sat_abs_neg (void)
14490 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14491 struct neon_type_el et
= neon_check_type (2, rs
,
14492 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14493 neon_two_same (neon_quad (rs
), 1, et
.size
);
14497 do_neon_pair_long (void)
14499 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14500 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14501 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14502 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14503 neon_two_same (neon_quad (rs
), 1, et
.size
);
14507 do_neon_recip_est (void)
14509 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14510 struct neon_type_el et
= neon_check_type (2, rs
,
14511 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14512 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14513 neon_two_same (neon_quad (rs
), 1, et
.size
);
14519 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14520 struct neon_type_el et
= neon_check_type (2, rs
,
14521 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14522 neon_two_same (neon_quad (rs
), 1, et
.size
);
14528 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14529 struct neon_type_el et
= neon_check_type (2, rs
,
14530 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14531 neon_two_same (neon_quad (rs
), 1, et
.size
);
14537 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14538 struct neon_type_el et
= neon_check_type (2, rs
,
14539 N_EQK
| N_INT
, N_8
| N_KEY
);
14540 neon_two_same (neon_quad (rs
), 1, et
.size
);
14546 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14547 neon_two_same (neon_quad (rs
), 1, -1);
14551 do_neon_tbl_tbx (void)
14553 unsigned listlenbits
;
14554 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14556 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14558 first_error (_("bad list length for table lookup"));
14562 listlenbits
= inst
.operands
[1].imm
- 1;
14563 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14564 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14565 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14566 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14567 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14568 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14569 inst
.instruction
|= listlenbits
<< 8;
14571 neon_dp_fixup (&inst
);
14575 do_neon_ldm_stm (void)
14577 /* P, U and L bits are part of bitmask. */
14578 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14579 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14581 if (inst
.operands
[1].issingle
)
14583 do_vfp_nsyn_ldm_stm (is_dbmode
);
14587 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14588 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14590 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14591 _("register list must contain at least 1 and at most 16 "
14594 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14595 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14596 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14597 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14599 inst
.instruction
|= offsetbits
;
14601 do_vfp_cond_or_thumb ();
14605 do_neon_ldr_str (void)
14607 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14609 if (inst
.operands
[0].issingle
)
14612 do_vfp_nsyn_opcode ("flds");
14614 do_vfp_nsyn_opcode ("fsts");
14619 do_vfp_nsyn_opcode ("fldd");
14621 do_vfp_nsyn_opcode ("fstd");
14625 /* "interleave" version also handles non-interleaving register VLD1/VST1
14629 do_neon_ld_st_interleave (void)
14631 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14632 N_8
| N_16
| N_32
| N_64
);
14633 unsigned alignbits
= 0;
14635 /* The bits in this table go:
14636 0: register stride of one (0) or two (1)
14637 1,2: register list length, minus one (1, 2, 3, 4).
14638 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14639 We use -1 for invalid entries. */
14640 const int typetable
[] =
14642 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14643 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14644 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14645 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14649 if (et
.type
== NT_invtype
)
14652 if (inst
.operands
[1].immisalign
)
14653 switch (inst
.operands
[1].imm
>> 8)
14655 case 64: alignbits
= 1; break;
14657 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14658 goto bad_alignment
;
14662 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14663 goto bad_alignment
;
14668 first_error (_("bad alignment"));
14672 inst
.instruction
|= alignbits
<< 4;
14673 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14675 /* Bits [4:6] of the immediate in a list specifier encode register stride
14676 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14677 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14678 up the right value for "type" in a table based on this value and the given
14679 list style, then stick it back. */
14680 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14681 | (((inst
.instruction
>> 8) & 3) << 3);
14683 typebits
= typetable
[idx
];
14685 constraint (typebits
== -1, _("bad list type for instruction"));
14687 inst
.instruction
&= ~0xf00;
14688 inst
.instruction
|= typebits
<< 8;
14691 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14692 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14693 otherwise. The variable arguments are a list of pairs of legal (size, align)
14694 values, terminated with -1. */
14697 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14700 int result
= FAIL
, thissize
, thisalign
;
14702 if (!inst
.operands
[1].immisalign
)
14708 va_start (ap
, do_align
);
14712 thissize
= va_arg (ap
, int);
14713 if (thissize
== -1)
14715 thisalign
= va_arg (ap
, int);
14717 if (size
== thissize
&& align
== thisalign
)
14720 while (result
!= SUCCESS
);
14724 if (result
== SUCCESS
)
14727 first_error (_("unsupported alignment for instruction"));
14733 do_neon_ld_st_lane (void)
14735 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14736 int align_good
, do_align
= 0;
14737 int logsize
= neon_logbits (et
.size
);
14738 int align
= inst
.operands
[1].imm
>> 8;
14739 int n
= (inst
.instruction
>> 8) & 3;
14740 int max_el
= 64 / et
.size
;
14742 if (et
.type
== NT_invtype
)
14745 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14746 _("bad list length"));
14747 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14748 _("scalar index out of range"));
14749 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14751 _("stride of 2 unavailable when element size is 8"));
14755 case 0: /* VLD1 / VST1. */
14756 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14758 if (align_good
== FAIL
)
14762 unsigned alignbits
= 0;
14765 case 16: alignbits
= 0x1; break;
14766 case 32: alignbits
= 0x3; break;
14769 inst
.instruction
|= alignbits
<< 4;
14773 case 1: /* VLD2 / VST2. */
14774 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14776 if (align_good
== FAIL
)
14779 inst
.instruction
|= 1 << 4;
14782 case 2: /* VLD3 / VST3. */
14783 constraint (inst
.operands
[1].immisalign
,
14784 _("can't use alignment with this instruction"));
14787 case 3: /* VLD4 / VST4. */
14788 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14789 16, 64, 32, 64, 32, 128, -1);
14790 if (align_good
== FAIL
)
14794 unsigned alignbits
= 0;
14797 case 8: alignbits
= 0x1; break;
14798 case 16: alignbits
= 0x1; break;
14799 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14802 inst
.instruction
|= alignbits
<< 4;
14809 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14810 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14811 inst
.instruction
|= 1 << (4 + logsize
);
14813 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14814 inst
.instruction
|= logsize
<< 10;
14817 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14820 do_neon_ld_dup (void)
14822 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14823 int align_good
, do_align
= 0;
14825 if (et
.type
== NT_invtype
)
14828 switch ((inst
.instruction
>> 8) & 3)
14830 case 0: /* VLD1. */
14831 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14832 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14833 &do_align
, 16, 16, 32, 32, -1);
14834 if (align_good
== FAIL
)
14836 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14839 case 2: inst
.instruction
|= 1 << 5; break;
14840 default: first_error (_("bad list length")); return;
14842 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14845 case 1: /* VLD2. */
14846 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14847 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14848 if (align_good
== FAIL
)
14850 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14851 _("bad list length"));
14852 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14853 inst
.instruction
|= 1 << 5;
14854 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14857 case 2: /* VLD3. */
14858 constraint (inst
.operands
[1].immisalign
,
14859 _("can't use alignment with this instruction"));
14860 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14861 _("bad list length"));
14862 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14863 inst
.instruction
|= 1 << 5;
14864 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14867 case 3: /* VLD4. */
14869 int align
= inst
.operands
[1].imm
>> 8;
14870 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14871 16, 64, 32, 64, 32, 128, -1);
14872 if (align_good
== FAIL
)
14874 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14875 _("bad list length"));
14876 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14877 inst
.instruction
|= 1 << 5;
14878 if (et
.size
== 32 && align
== 128)
14879 inst
.instruction
|= 0x3 << 6;
14881 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14888 inst
.instruction
|= do_align
<< 4;
14891 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14892 apart from bits [11:4]. */
14895 do_neon_ldx_stx (void)
14897 if (inst
.operands
[1].isreg
)
14898 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
14900 switch (NEON_LANE (inst
.operands
[0].imm
))
14902 case NEON_INTERLEAVE_LANES
:
14903 NEON_ENCODE (INTERLV
, inst
);
14904 do_neon_ld_st_interleave ();
14907 case NEON_ALL_LANES
:
14908 NEON_ENCODE (DUP
, inst
);
14913 NEON_ENCODE (LANE
, inst
);
14914 do_neon_ld_st_lane ();
14917 /* L bit comes from bit mask. */
14918 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14919 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14920 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14922 if (inst
.operands
[1].postind
)
14924 int postreg
= inst
.operands
[1].imm
& 0xf;
14925 constraint (!inst
.operands
[1].immisreg
,
14926 _("post-index must be a register"));
14927 constraint (postreg
== 0xd || postreg
== 0xf,
14928 _("bad register for post-index"));
14929 inst
.instruction
|= postreg
;
14931 else if (inst
.operands
[1].writeback
)
14933 inst
.instruction
|= 0xd;
14936 inst
.instruction
|= 0xf;
14939 inst
.instruction
|= 0xf9000000;
14941 inst
.instruction
|= 0xf4000000;
14944 /* Overall per-instruction processing. */
14946 /* We need to be able to fix up arbitrary expressions in some statements.
14947 This is so that we can handle symbols that are an arbitrary distance from
14948 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14949 which returns part of an address in a form which will be valid for
14950 a data instruction. We do this by pushing the expression into a symbol
14951 in the expr_section, and creating a fix for that. */
14954 fix_new_arm (fragS
* frag
,
14969 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
14970 (enum bfd_reloc_code_real
) reloc
);
14974 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14975 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
14979 /* Mark whether the fix is to a THUMB instruction, or an ARM
14981 new_fix
->tc_fix_data
= thumb_mode
;
14984 /* Create a frg for an instruction requiring relaxation. */
14986 output_relax_insn (void)
14992 /* The size of the instruction is unknown, so tie the debug info to the
14993 start of the instruction. */
14994 dwarf2_emit_insn (0);
14996 switch (inst
.reloc
.exp
.X_op
)
14999 sym
= inst
.reloc
.exp
.X_add_symbol
;
15000 offset
= inst
.reloc
.exp
.X_add_number
;
15004 offset
= inst
.reloc
.exp
.X_add_number
;
15007 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15011 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15012 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15013 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15016 /* Write a 32-bit thumb instruction to buf. */
15018 put_thumb32_insn (char * buf
, unsigned long insn
)
15020 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15021 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15025 output_inst (const char * str
)
15031 as_bad ("%s -- `%s'", inst
.error
, str
);
15036 output_relax_insn ();
15039 if (inst
.size
== 0)
15042 to
= frag_more (inst
.size
);
15043 /* PR 9814: Record the thumb mode into the current frag so that we know
15044 what type of NOP padding to use, if necessary. We override any previous
15045 setting so that if the mode has changed then the NOPS that we use will
15046 match the encoding of the last instruction in the frag. */
15047 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15049 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15051 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15052 put_thumb32_insn (to
, inst
.instruction
);
15054 else if (inst
.size
> INSN_SIZE
)
15056 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15057 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15058 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15061 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15063 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15064 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15065 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15068 dwarf2_emit_insn (inst
.size
);
15072 output_it_inst (int cond
, int mask
, char * to
)
15074 unsigned long instruction
= 0xbf00;
15077 instruction
|= mask
;
15078 instruction
|= cond
<< 4;
15082 to
= frag_more (2);
15084 dwarf2_emit_insn (2);
15088 md_number_to_chars (to
, instruction
, 2);
15093 /* Tag values used in struct asm_opcode's tag field. */
15096 OT_unconditional
, /* Instruction cannot be conditionalized.
15097 The ARM condition field is still 0xE. */
15098 OT_unconditionalF
, /* Instruction cannot be conditionalized
15099 and carries 0xF in its ARM condition field. */
15100 OT_csuffix
, /* Instruction takes a conditional suffix. */
15101 OT_csuffixF
, /* Some forms of the instruction take a conditional
15102 suffix, others place 0xF where the condition field
15104 OT_cinfix3
, /* Instruction takes a conditional infix,
15105 beginning at character index 3. (In
15106 unified mode, it becomes a suffix.) */
15107 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15108 tsts, cmps, cmns, and teqs. */
15109 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15110 character index 3, even in unified mode. Used for
15111 legacy instructions where suffix and infix forms
15112 may be ambiguous. */
15113 OT_csuf_or_in3
, /* Instruction takes either a conditional
15114 suffix or an infix at character index 3. */
15115 OT_odd_infix_unc
, /* This is the unconditional variant of an
15116 instruction that takes a conditional infix
15117 at an unusual position. In unified mode,
15118 this variant will accept a suffix. */
15119 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15120 are the conditional variants of instructions that
15121 take conditional infixes in unusual positions.
15122 The infix appears at character index
15123 (tag - OT_odd_infix_0). These are not accepted
15124 in unified mode. */
15127 /* Subroutine of md_assemble, responsible for looking up the primary
15128 opcode from the mnemonic the user wrote. STR points to the
15129 beginning of the mnemonic.
15131 This is not simply a hash table lookup, because of conditional
15132 variants. Most instructions have conditional variants, which are
15133 expressed with a _conditional affix_ to the mnemonic. If we were
15134 to encode each conditional variant as a literal string in the opcode
15135 table, it would have approximately 20,000 entries.
15137 Most mnemonics take this affix as a suffix, and in unified syntax,
15138 'most' is upgraded to 'all'. However, in the divided syntax, some
15139 instructions take the affix as an infix, notably the s-variants of
15140 the arithmetic instructions. Of those instructions, all but six
15141 have the infix appear after the third character of the mnemonic.
15143 Accordingly, the algorithm for looking up primary opcodes given
15146 1. Look up the identifier in the opcode table.
15147 If we find a match, go to step U.
15149 2. Look up the last two characters of the identifier in the
15150 conditions table. If we find a match, look up the first N-2
15151 characters of the identifier in the opcode table. If we
15152 find a match, go to step CE.
15154 3. Look up the fourth and fifth characters of the identifier in
15155 the conditions table. If we find a match, extract those
15156 characters from the identifier, and look up the remaining
15157 characters in the opcode table. If we find a match, go
15162 U. Examine the tag field of the opcode structure, in case this is
15163 one of the six instructions with its conditional infix in an
15164 unusual place. If it is, the tag tells us where to find the
15165 infix; look it up in the conditions table and set inst.cond
15166 accordingly. Otherwise, this is an unconditional instruction.
15167 Again set inst.cond accordingly. Return the opcode structure.
15169 CE. Examine the tag field to make sure this is an instruction that
15170 should receive a conditional suffix. If it is not, fail.
15171 Otherwise, set inst.cond from the suffix we already looked up,
15172 and return the opcode structure.
15174 CM. Examine the tag field to make sure this is an instruction that
15175 should receive a conditional infix after the third character.
15176 If it is not, fail. Otherwise, undo the edits to the current
15177 line of input and proceed as for case CE. */
15179 static const struct asm_opcode
*
15180 opcode_lookup (char **str
)
15184 const struct asm_opcode
*opcode
;
15185 const struct asm_cond
*cond
;
15188 /* Scan up to the end of the mnemonic, which must end in white space,
15189 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15190 for (base
= end
= *str
; *end
!= '\0'; end
++)
15191 if (*end
== ' ' || *end
== '.')
15197 /* Handle a possible width suffix and/or Neon type suffix. */
15202 /* The .w and .n suffixes are only valid if the unified syntax is in
15204 if (unified_syntax
&& end
[1] == 'w')
15206 else if (unified_syntax
&& end
[1] == 'n')
15211 inst
.vectype
.elems
= 0;
15213 *str
= end
+ offset
;
15215 if (end
[offset
] == '.')
15217 /* See if we have a Neon type suffix (possible in either unified or
15218 non-unified ARM syntax mode). */
15219 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15222 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15228 /* Look for unaffixed or special-case affixed mnemonic. */
15229 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15234 if (opcode
->tag
< OT_odd_infix_0
)
15236 inst
.cond
= COND_ALWAYS
;
15240 if (warn_on_deprecated
&& unified_syntax
)
15241 as_warn (_("conditional infixes are deprecated in unified syntax"));
15242 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15243 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15246 inst
.cond
= cond
->value
;
15250 /* Cannot have a conditional suffix on a mnemonic of less than two
15252 if (end
- base
< 3)
15255 /* Look for suffixed mnemonic. */
15257 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15258 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15260 if (opcode
&& cond
)
15263 switch (opcode
->tag
)
15265 case OT_cinfix3_legacy
:
15266 /* Ignore conditional suffixes matched on infix only mnemonics. */
15270 case OT_cinfix3_deprecated
:
15271 case OT_odd_infix_unc
:
15272 if (!unified_syntax
)
15274 /* else fall through */
15278 case OT_csuf_or_in3
:
15279 inst
.cond
= cond
->value
;
15282 case OT_unconditional
:
15283 case OT_unconditionalF
:
15285 inst
.cond
= cond
->value
;
15288 /* Delayed diagnostic. */
15289 inst
.error
= BAD_COND
;
15290 inst
.cond
= COND_ALWAYS
;
15299 /* Cannot have a usual-position infix on a mnemonic of less than
15300 six characters (five would be a suffix). */
15301 if (end
- base
< 6)
15304 /* Look for infixed mnemonic in the usual position. */
15306 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15310 memcpy (save
, affix
, 2);
15311 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15312 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15314 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15315 memcpy (affix
, save
, 2);
15318 && (opcode
->tag
== OT_cinfix3
15319 || opcode
->tag
== OT_cinfix3_deprecated
15320 || opcode
->tag
== OT_csuf_or_in3
15321 || opcode
->tag
== OT_cinfix3_legacy
))
15324 if (warn_on_deprecated
&& unified_syntax
15325 && (opcode
->tag
== OT_cinfix3
15326 || opcode
->tag
== OT_cinfix3_deprecated
))
15327 as_warn (_("conditional infixes are deprecated in unified syntax"));
15329 inst
.cond
= cond
->value
;
15336 /* This function generates an initial IT instruction, leaving its block
15337 virtually open for the new instructions. Eventually,
15338 the mask will be updated by now_it_add_mask () each time
15339 a new instruction needs to be included in the IT block.
15340 Finally, the block is closed with close_automatic_it_block ().
15341 The block closure can be requested either from md_assemble (),
15342 a tencode (), or due to a label hook. */
15345 new_automatic_it_block (int cond
)
15347 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15348 now_it
.mask
= 0x18;
15350 now_it
.block_length
= 1;
15351 mapping_state (MAP_THUMB
);
15352 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15355 /* Close an automatic IT block.
15356 See comments in new_automatic_it_block (). */
15359 close_automatic_it_block (void)
15361 now_it
.mask
= 0x10;
15362 now_it
.block_length
= 0;
15365 /* Update the mask of the current automatically-generated IT
15366 instruction. See comments in new_automatic_it_block (). */
15369 now_it_add_mask (int cond
)
15371 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15372 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15373 | ((bitvalue) << (nbit)))
15374 const int resulting_bit
= (cond
& 1);
15376 now_it
.mask
&= 0xf;
15377 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15379 (5 - now_it
.block_length
));
15380 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15382 ((5 - now_it
.block_length
) - 1) );
15383 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15386 #undef SET_BIT_VALUE
15389 /* The IT blocks handling machinery is accessed through the these functions:
15390 it_fsm_pre_encode () from md_assemble ()
15391 set_it_insn_type () optional, from the tencode functions
15392 set_it_insn_type_last () ditto
15393 in_it_block () ditto
15394 it_fsm_post_encode () from md_assemble ()
15395 force_automatic_it_block_close () from label habdling functions
15398 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15399 initializing the IT insn type with a generic initial value depending
15400 on the inst.condition.
15401 2) During the tencode function, two things may happen:
15402 a) The tencode function overrides the IT insn type by
15403 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15404 b) The tencode function queries the IT block state by
15405 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15407 Both set_it_insn_type and in_it_block run the internal FSM state
15408 handling function (handle_it_state), because: a) setting the IT insn
15409 type may incur in an invalid state (exiting the function),
15410 and b) querying the state requires the FSM to be updated.
15411 Specifically we want to avoid creating an IT block for conditional
15412 branches, so it_fsm_pre_encode is actually a guess and we can't
15413 determine whether an IT block is required until the tencode () routine
15414 has decided what type of instruction this actually it.
15415 Because of this, if set_it_insn_type and in_it_block have to be used,
15416 set_it_insn_type has to be called first.
15418 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15419 determines the insn IT type depending on the inst.cond code.
15420 When a tencode () routine encodes an instruction that can be
15421 either outside an IT block, or, in the case of being inside, has to be
15422 the last one, set_it_insn_type_last () will determine the proper
15423 IT instruction type based on the inst.cond code. Otherwise,
15424 set_it_insn_type can be called for overriding that logic or
15425 for covering other cases.
15427 Calling handle_it_state () may not transition the IT block state to
15428 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15429 still queried. Instead, if the FSM determines that the state should
15430 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15431 after the tencode () function: that's what it_fsm_post_encode () does.
15433 Since in_it_block () calls the state handling function to get an
15434 updated state, an error may occur (due to invalid insns combination).
15435 In that case, inst.error is set.
15436 Therefore, inst.error has to be checked after the execution of
15437 the tencode () routine.
15439 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15440 any pending state change (if any) that didn't take place in
15441 handle_it_state () as explained above. */
15444 it_fsm_pre_encode (void)
15446 if (inst
.cond
!= COND_ALWAYS
)
15447 inst
.it_insn_type
= INSIDE_IT_INSN
;
15449 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15451 now_it
.state_handled
= 0;
15454 /* IT state FSM handling function. */
15457 handle_it_state (void)
15459 now_it
.state_handled
= 1;
15461 switch (now_it
.state
)
15463 case OUTSIDE_IT_BLOCK
:
15464 switch (inst
.it_insn_type
)
15466 case OUTSIDE_IT_INSN
:
15469 case INSIDE_IT_INSN
:
15470 case INSIDE_IT_LAST_INSN
:
15471 if (thumb_mode
== 0)
15474 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15475 as_tsktsk (_("Warning: conditional outside an IT block"\
15480 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15481 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15483 /* Automatically generate the IT instruction. */
15484 new_automatic_it_block (inst
.cond
);
15485 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15486 close_automatic_it_block ();
15490 inst
.error
= BAD_OUT_IT
;
15496 case IF_INSIDE_IT_LAST_INSN
:
15497 case NEUTRAL_IT_INSN
:
15501 now_it
.state
= MANUAL_IT_BLOCK
;
15502 now_it
.block_length
= 0;
15507 case AUTOMATIC_IT_BLOCK
:
15508 /* Three things may happen now:
15509 a) We should increment current it block size;
15510 b) We should close current it block (closing insn or 4 insns);
15511 c) We should close current it block and start a new one (due
15512 to incompatible conditions or
15513 4 insns-length block reached). */
15515 switch (inst
.it_insn_type
)
15517 case OUTSIDE_IT_INSN
:
15518 /* The closure of the block shall happen immediatelly,
15519 so any in_it_block () call reports the block as closed. */
15520 force_automatic_it_block_close ();
15523 case INSIDE_IT_INSN
:
15524 case INSIDE_IT_LAST_INSN
:
15525 case IF_INSIDE_IT_LAST_INSN
:
15526 now_it
.block_length
++;
15528 if (now_it
.block_length
> 4
15529 || !now_it_compatible (inst
.cond
))
15531 force_automatic_it_block_close ();
15532 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15533 new_automatic_it_block (inst
.cond
);
15537 now_it_add_mask (inst
.cond
);
15540 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15541 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15542 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15543 close_automatic_it_block ();
15546 case NEUTRAL_IT_INSN
:
15547 now_it
.block_length
++;
15549 if (now_it
.block_length
> 4)
15550 force_automatic_it_block_close ();
15552 now_it_add_mask (now_it
.cc
& 1);
15556 close_automatic_it_block ();
15557 now_it
.state
= MANUAL_IT_BLOCK
;
15562 case MANUAL_IT_BLOCK
:
15564 /* Check conditional suffixes. */
15565 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15568 now_it
.mask
&= 0x1f;
15569 is_last
= (now_it
.mask
== 0x10);
15571 switch (inst
.it_insn_type
)
15573 case OUTSIDE_IT_INSN
:
15574 inst
.error
= BAD_NOT_IT
;
15577 case INSIDE_IT_INSN
:
15578 if (cond
!= inst
.cond
)
15580 inst
.error
= BAD_IT_COND
;
15585 case INSIDE_IT_LAST_INSN
:
15586 case IF_INSIDE_IT_LAST_INSN
:
15587 if (cond
!= inst
.cond
)
15589 inst
.error
= BAD_IT_COND
;
15594 inst
.error
= BAD_BRANCH
;
15599 case NEUTRAL_IT_INSN
:
15600 /* The BKPT instruction is unconditional even in an IT block. */
15604 inst
.error
= BAD_IT_IT
;
15615 it_fsm_post_encode (void)
15619 if (!now_it
.state_handled
)
15620 handle_it_state ();
15622 is_last
= (now_it
.mask
== 0x10);
15625 now_it
.state
= OUTSIDE_IT_BLOCK
;
15631 force_automatic_it_block_close (void)
15633 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15635 close_automatic_it_block ();
15636 now_it
.state
= OUTSIDE_IT_BLOCK
;
15644 if (!now_it
.state_handled
)
15645 handle_it_state ();
15647 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15651 md_assemble (char *str
)
15654 const struct asm_opcode
* opcode
;
15656 /* Align the previous label if needed. */
15657 if (last_label_seen
!= NULL
)
15659 symbol_set_frag (last_label_seen
, frag_now
);
15660 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15661 S_SET_SEGMENT (last_label_seen
, now_seg
);
15664 memset (&inst
, '\0', sizeof (inst
));
15665 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15667 opcode
= opcode_lookup (&p
);
15670 /* It wasn't an instruction, but it might be a register alias of
15671 the form alias .req reg, or a Neon .dn/.qn directive. */
15672 if (! create_register_alias (str
, p
)
15673 && ! create_neon_reg_alias (str
, p
))
15674 as_bad (_("bad instruction `%s'"), str
);
15679 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15680 as_warn (_("s suffix on comparison instruction is deprecated"));
15682 /* The value which unconditional instructions should have in place of the
15683 condition field. */
15684 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15688 arm_feature_set variant
;
15690 variant
= cpu_variant
;
15691 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15692 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15693 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15694 /* Check that this instruction is supported for this CPU. */
15695 if (!opcode
->tvariant
15696 || (thumb_mode
== 1
15697 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15699 as_bad (_("selected processor does not support `%s'"), str
);
15702 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15703 && opcode
->tencode
!= do_t_branch
)
15705 as_bad (_("Thumb does not support conditional execution"));
15709 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15711 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15712 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15713 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15715 /* Two things are addressed here.
15716 1) Implicit require narrow instructions on Thumb-1.
15717 This avoids relaxation accidentally introducing Thumb-2
15719 2) Reject wide instructions in non Thumb-2 cores. */
15720 if (inst
.size_req
== 0)
15722 else if (inst
.size_req
== 4)
15724 as_bad (_("selected processor does not support `%s'"), str
);
15730 inst
.instruction
= opcode
->tvalue
;
15732 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15734 /* Prepare the it_insn_type for those encodings that don't set
15736 it_fsm_pre_encode ();
15738 opcode
->tencode ();
15740 it_fsm_post_encode ();
15743 if (!(inst
.error
|| inst
.relax
))
15745 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15746 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15747 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15749 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15754 /* Something has gone badly wrong if we try to relax a fixed size
15756 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15758 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15759 *opcode
->tvariant
);
15760 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15761 set those bits when Thumb-2 32-bit instructions are seen. ie.
15762 anything other than bl/blx and v6-M instructions.
15763 This is overly pessimistic for relaxable instructions. */
15764 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15766 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15767 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15768 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15771 check_neon_suffixes
;
15775 mapping_state (MAP_THUMB
);
15778 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15782 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15783 is_bx
= (opcode
->aencode
== do_bx
);
15785 /* Check that this instruction is supported for this CPU. */
15786 if (!(is_bx
&& fix_v4bx
)
15787 && !(opcode
->avariant
&&
15788 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15790 as_bad (_("selected processor does not support `%s'"), str
);
15795 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15799 inst
.instruction
= opcode
->avalue
;
15800 if (opcode
->tag
== OT_unconditionalF
)
15801 inst
.instruction
|= 0xF << 28;
15803 inst
.instruction
|= inst
.cond
<< 28;
15804 inst
.size
= INSN_SIZE
;
15805 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
15807 it_fsm_pre_encode ();
15808 opcode
->aencode ();
15809 it_fsm_post_encode ();
15811 /* Arm mode bx is marked as both v4T and v5 because it's still required
15812 on a hypothetical non-thumb v5 core. */
15814 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15816 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15817 *opcode
->avariant
);
15819 check_neon_suffixes
;
15823 mapping_state (MAP_ARM
);
15828 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15836 check_it_blocks_finished (void)
15841 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15842 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15843 == MANUAL_IT_BLOCK
)
15845 as_warn (_("section '%s' finished with an open IT block."),
15849 if (now_it
.state
== MANUAL_IT_BLOCK
)
15850 as_warn (_("file finished with an open IT block."));
15854 /* Various frobbings of labels and their addresses. */
15857 arm_start_line_hook (void)
15859 last_label_seen
= NULL
;
15863 arm_frob_label (symbolS
* sym
)
15865 last_label_seen
= sym
;
15867 ARM_SET_THUMB (sym
, thumb_mode
);
15869 #if defined OBJ_COFF || defined OBJ_ELF
15870 ARM_SET_INTERWORK (sym
, support_interwork
);
15873 force_automatic_it_block_close ();
15875 /* Note - do not allow local symbols (.Lxxx) to be labelled
15876 as Thumb functions. This is because these labels, whilst
15877 they exist inside Thumb code, are not the entry points for
15878 possible ARM->Thumb calls. Also, these labels can be used
15879 as part of a computed goto or switch statement. eg gcc
15880 can generate code that looks like this:
15882 ldr r2, [pc, .Laaa]
15892 The first instruction loads the address of the jump table.
15893 The second instruction converts a table index into a byte offset.
15894 The third instruction gets the jump address out of the table.
15895 The fourth instruction performs the jump.
15897 If the address stored at .Laaa is that of a symbol which has the
15898 Thumb_Func bit set, then the linker will arrange for this address
15899 to have the bottom bit set, which in turn would mean that the
15900 address computation performed by the third instruction would end
15901 up with the bottom bit set. Since the ARM is capable of unaligned
15902 word loads, the instruction would then load the incorrect address
15903 out of the jump table, and chaos would ensue. */
15904 if (label_is_thumb_function_name
15905 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
15906 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
15908 /* When the address of a Thumb function is taken the bottom
15909 bit of that address should be set. This will allow
15910 interworking between Arm and Thumb functions to work
15913 THUMB_SET_FUNC (sym
, 1);
15915 label_is_thumb_function_name
= FALSE
;
15918 dwarf2_emit_label (sym
);
15922 arm_data_in_code (void)
15924 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
15926 *input_line_pointer
= '/';
15927 input_line_pointer
+= 5;
15928 *input_line_pointer
= 0;
15936 arm_canonicalize_symbol_name (char * name
)
15940 if (thumb_mode
&& (len
= strlen (name
)) > 5
15941 && streq (name
+ len
- 5, "/data"))
15942 *(name
+ len
- 5) = 0;
15947 /* Table of all register names defined by default. The user can
15948 define additional names with .req. Note that all register names
15949 should appear in both upper and lowercase variants. Some registers
15950 also have mixed-case names. */
15952 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
15953 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
15954 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
15955 #define REGSET(p,t) \
15956 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
15957 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
15958 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
15959 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
15960 #define REGSETH(p,t) \
15961 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
15962 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
15963 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
15964 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
15965 #define REGSET2(p,t) \
15966 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
15967 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
15968 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
15969 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
15971 static const struct reg_entry reg_names
[] =
15973 /* ARM integer registers. */
15974 REGSET(r
, RN
), REGSET(R
, RN
),
15976 /* ATPCS synonyms. */
15977 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
15978 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
15979 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
15981 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
15982 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
15983 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
15985 /* Well-known aliases. */
15986 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
15987 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
15989 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
15990 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
15992 /* Coprocessor numbers. */
15993 REGSET(p
, CP
), REGSET(P
, CP
),
15995 /* Coprocessor register numbers. The "cr" variants are for backward
15997 REGSET(c
, CN
), REGSET(C
, CN
),
15998 REGSET(cr
, CN
), REGSET(CR
, CN
),
16000 /* FPA registers. */
16001 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16002 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16004 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16005 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16007 /* VFP SP registers. */
16008 REGSET(s
,VFS
), REGSET(S
,VFS
),
16009 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16011 /* VFP DP Registers. */
16012 REGSET(d
,VFD
), REGSET(D
,VFD
),
16013 /* Extra Neon DP registers. */
16014 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16016 /* Neon QP registers. */
16017 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16019 /* VFP control registers. */
16020 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16021 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16022 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16023 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16024 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16025 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16027 /* Maverick DSP coprocessor registers. */
16028 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16029 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16031 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16032 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16033 REGDEF(dspsc
,0,DSPSC
),
16035 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16036 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16037 REGDEF(DSPSC
,0,DSPSC
),
16039 /* iWMMXt data registers - p0, c0-15. */
16040 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16042 /* iWMMXt control registers - p1, c0-3. */
16043 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16044 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16045 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16046 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16048 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16049 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16050 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16051 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16052 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16054 /* XScale accumulator registers. */
16055 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16061 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16062 within psr_required_here. */
16063 static const struct asm_psr psrs
[] =
16065 /* Backward compatibility notation. Note that "all" is no longer
16066 truly all possible PSR bits. */
16067 {"all", PSR_c
| PSR_f
},
16071 /* Individual flags. */
16076 /* Combinations of flags. */
16077 {"fs", PSR_f
| PSR_s
},
16078 {"fx", PSR_f
| PSR_x
},
16079 {"fc", PSR_f
| PSR_c
},
16080 {"sf", PSR_s
| PSR_f
},
16081 {"sx", PSR_s
| PSR_x
},
16082 {"sc", PSR_s
| PSR_c
},
16083 {"xf", PSR_x
| PSR_f
},
16084 {"xs", PSR_x
| PSR_s
},
16085 {"xc", PSR_x
| PSR_c
},
16086 {"cf", PSR_c
| PSR_f
},
16087 {"cs", PSR_c
| PSR_s
},
16088 {"cx", PSR_c
| PSR_x
},
16089 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16090 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16091 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16092 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16093 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16094 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16095 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16096 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16097 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16098 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16099 {"scf", PSR_s
| PSR_c
| PSR_f
},
16100 {"scx", PSR_s
| PSR_c
| PSR_x
},
16101 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16102 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16103 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16104 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16105 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16106 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16107 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16108 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16109 {"csf", PSR_c
| PSR_s
| PSR_f
},
16110 {"csx", PSR_c
| PSR_s
| PSR_x
},
16111 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16112 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16113 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16114 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16115 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16116 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16117 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16118 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16119 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16120 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16121 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16122 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16123 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16124 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16125 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16126 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16127 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16128 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16129 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16130 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16131 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16132 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16133 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16134 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16135 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16136 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16139 /* Table of V7M psr names. */
16140 static const struct asm_psr v7m_psrs
[] =
16142 {"apsr", 0 }, {"APSR", 0 },
16143 {"iapsr", 1 }, {"IAPSR", 1 },
16144 {"eapsr", 2 }, {"EAPSR", 2 },
16145 {"psr", 3 }, {"PSR", 3 },
16146 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16147 {"ipsr", 5 }, {"IPSR", 5 },
16148 {"epsr", 6 }, {"EPSR", 6 },
16149 {"iepsr", 7 }, {"IEPSR", 7 },
16150 {"msp", 8 }, {"MSP", 8 },
16151 {"psp", 9 }, {"PSP", 9 },
16152 {"primask", 16}, {"PRIMASK", 16},
16153 {"basepri", 17}, {"BASEPRI", 17},
16154 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16155 {"faultmask", 19}, {"FAULTMASK", 19},
16156 {"control", 20}, {"CONTROL", 20}
16159 /* Table of all shift-in-operand names. */
16160 static const struct asm_shift_name shift_names
[] =
16162 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16163 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16164 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16165 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16166 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16167 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16170 /* Table of all explicit relocation names. */
16172 static struct reloc_entry reloc_names
[] =
16174 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16175 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16176 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16177 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16178 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16179 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16180 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16181 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16182 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16183 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16184 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
16188 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16189 static const struct asm_cond conds
[] =
16193 {"cs", 0x2}, {"hs", 0x2},
16194 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16208 static struct asm_barrier_opt barrier_opt_names
[] =
16216 /* Table of ARM-format instructions. */
16218 /* Macros for gluing together operand strings. N.B. In all cases
16219 other than OPS0, the trailing OP_stop comes from default
16220 zero-initialization of the unspecified elements of the array. */
16221 #define OPS0() { OP_stop, }
16222 #define OPS1(a) { OP_##a, }
16223 #define OPS2(a,b) { OP_##a,OP_##b, }
16224 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16225 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16226 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16227 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16229 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16230 This is useful when mixing operands for ARM and THUMB, i.e. using the
16231 MIX_ARM_THUMB_OPERANDS macro.
16232 In order to use these macros, prefix the number of operands with _
16234 #define OPS_1(a) { a, }
16235 #define OPS_2(a,b) { a,b, }
16236 #define OPS_3(a,b,c) { a,b,c, }
16237 #define OPS_4(a,b,c,d) { a,b,c,d, }
16238 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16239 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16241 /* These macros abstract out the exact format of the mnemonic table and
16242 save some repeated characters. */
16244 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16245 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16246 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16247 THUMB_VARIANT, do_##ae, do_##te }
16249 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16250 a T_MNEM_xyz enumerator. */
16251 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16252 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16253 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16254 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16256 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16257 infix after the third character. */
16258 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16259 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16260 THUMB_VARIANT, do_##ae, do_##te }
16261 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16262 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16263 THUMB_VARIANT, do_##ae, do_##te }
16264 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16265 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16266 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16267 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16268 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16269 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16270 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16271 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16273 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16274 appear in the condition table. */
16275 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16276 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16277 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16279 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16280 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16281 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16282 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16283 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16284 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16285 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16286 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16287 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16288 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16289 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16290 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16291 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16292 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16293 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16294 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16295 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16296 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16297 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16298 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16300 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16301 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16302 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16303 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16305 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16306 field is still 0xE. Many of the Thumb variants can be executed
16307 conditionally, so this is checked separately. */
16308 #define TUE(mnem, op, top, nops, ops, ae, te) \
16309 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16310 THUMB_VARIANT, do_##ae, do_##te }
16312 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16313 condition code field. */
16314 #define TUF(mnem, op, top, nops, ops, ae, te) \
16315 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16316 THUMB_VARIANT, do_##ae, do_##te }
16318 /* ARM-only variants of all the above. */
16319 #define CE(mnem, op, nops, ops, ae) \
16320 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16322 #define C3(mnem, op, nops, ops, ae) \
16323 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16325 /* Legacy mnemonics that always have conditional infix after the third
16327 #define CL(mnem, op, nops, ops, ae) \
16328 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16329 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16331 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16332 #define cCE(mnem, op, nops, ops, ae) \
16333 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16335 /* Legacy coprocessor instructions where conditional infix and conditional
16336 suffix are ambiguous. For consistency this includes all FPA instructions,
16337 not just the potentially ambiguous ones. */
16338 #define cCL(mnem, op, nops, ops, ae) \
16339 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16340 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16342 /* Coprocessor, takes either a suffix or a position-3 infix
16343 (for an FPA corner case). */
16344 #define C3E(mnem, op, nops, ops, ae) \
16345 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16346 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16348 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16349 { m1 #m2 m3, OPS##nops ops, \
16350 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16351 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16353 #define CM(m1, m2, op, nops, ops, ae) \
16354 xCM_ (m1, , m2, op, nops, ops, ae), \
16355 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16356 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16357 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16358 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16359 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16360 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16361 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16362 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16363 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16364 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16365 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16366 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16367 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16368 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16369 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16370 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16371 xCM_ (m1, le, m2, op, nops, ops, ae), \
16372 xCM_ (m1, al, m2, op, nops, ops, ae)
16374 #define UE(mnem, op, nops, ops, ae) \
16375 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16377 #define UF(mnem, op, nops, ops, ae) \
16378 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16380 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16381 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16382 use the same encoding function for each. */
16383 #define NUF(mnem, op, nops, ops, enc) \
16384 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16385 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16387 /* Neon data processing, version which indirects through neon_enc_tab for
16388 the various overloaded versions of opcodes. */
16389 #define nUF(mnem, op, nops, ops, enc) \
16390 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16391 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16393 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16395 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16396 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16397 THUMB_VARIANT, do_##enc, do_##enc }
16399 #define NCE(mnem, op, nops, ops, enc) \
16400 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16402 #define NCEF(mnem, op, nops, ops, enc) \
16403 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16405 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16406 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16407 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16408 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16410 #define nCE(mnem, op, nops, ops, enc) \
16411 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16413 #define nCEF(mnem, op, nops, ops, enc) \
16414 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16418 /* Thumb-only, unconditional. */
16419 #define UT(mnem, op, nops, ops, te) TUE (mnem, 0, op, nops, ops, 0, te)
16421 static const struct asm_opcode insns
[] =
16423 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16424 #define THUMB_VARIANT &arm_ext_v4t
16425 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16426 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16427 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16428 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16429 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16430 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16431 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16432 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16433 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16434 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16435 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16436 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16437 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16438 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16439 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16440 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16442 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16443 for setting PSR flag bits. They are obsolete in V6 and do not
16444 have Thumb equivalents. */
16445 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16446 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16447 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16448 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16449 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16450 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16451 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16452 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16453 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16455 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16456 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16457 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16458 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16460 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16461 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16462 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16464 OP_ADDRGLDR
),ldst
, t_ldst
),
16465 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16467 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16468 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16469 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16470 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16471 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16472 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16474 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16475 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16476 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16477 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16480 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16481 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16482 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16484 /* Thumb-compatibility pseudo ops. */
16485 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16486 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16487 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16488 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16489 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16490 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16491 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16492 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16493 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16494 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16495 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16496 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16498 /* These may simplify to neg. */
16499 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16500 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16502 #undef THUMB_VARIANT
16503 #define THUMB_VARIANT & arm_ext_v6
16505 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16507 /* V1 instructions with no Thumb analogue prior to V6T2. */
16508 #undef THUMB_VARIANT
16509 #define THUMB_VARIANT & arm_ext_v6t2
16511 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16512 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16513 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16515 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16516 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16517 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16518 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16520 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16521 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16523 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16524 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16526 /* V1 instructions with no Thumb analogue at all. */
16527 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16528 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16530 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16531 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16532 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16533 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16534 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16535 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16536 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16537 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16540 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16541 #undef THUMB_VARIANT
16542 #define THUMB_VARIANT & arm_ext_v4t
16544 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16545 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16547 #undef THUMB_VARIANT
16548 #define THUMB_VARIANT & arm_ext_v6t2
16550 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16551 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16553 /* Generic coprocessor instructions. */
16554 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16555 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16556 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16557 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16558 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16559 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16560 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16563 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16565 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16566 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16569 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16570 #undef THUMB_VARIANT
16571 #define THUMB_VARIANT & arm_ext_msr
16573 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16574 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16577 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16578 #undef THUMB_VARIANT
16579 #define THUMB_VARIANT & arm_ext_v6t2
16581 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16582 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16583 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16584 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16585 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16586 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16587 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16588 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16591 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16592 #undef THUMB_VARIANT
16593 #define THUMB_VARIANT & arm_ext_v4t
16595 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16596 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16597 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16598 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16599 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16600 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16603 #define ARM_VARIANT & arm_ext_v4t_5
16605 /* ARM Architecture 4T. */
16606 /* Note: bx (and blx) are required on V5, even if the processor does
16607 not support Thumb. */
16608 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16611 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16612 #undef THUMB_VARIANT
16613 #define THUMB_VARIANT & arm_ext_v5t
16615 /* Note: blx has 2 variants; the .value coded here is for
16616 BLX(2). Only this variant has conditional execution. */
16617 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16618 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16620 #undef THUMB_VARIANT
16621 #define THUMB_VARIANT & arm_ext_v6t2
16623 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16624 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16625 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16626 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16627 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16628 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16629 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16630 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16633 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16634 #undef THUMB_VARIANT
16635 #define THUMB_VARIANT &arm_ext_v5exp
16637 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16638 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16639 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16640 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16642 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16643 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16645 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16646 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16647 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16648 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16650 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16651 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16652 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16653 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16655 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16656 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16658 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16659 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16660 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16661 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16664 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16665 #undef THUMB_VARIANT
16666 #define THUMB_VARIANT &arm_ext_v6t2
16668 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16669 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16671 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16672 ADDRGLDRS
), ldrd
, t_ldstd
),
16674 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16675 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16678 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16680 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16683 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16684 #undef THUMB_VARIANT
16685 #define THUMB_VARIANT & arm_ext_v6
16687 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16688 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16689 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16690 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16691 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16692 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16693 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16694 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16695 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16696 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16698 #undef THUMB_VARIANT
16699 #define THUMB_VARIANT & arm_ext_v6t2
16701 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16702 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16704 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16705 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16707 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16708 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16710 /* ARM V6 not included in V7M. */
16711 #undef THUMB_VARIANT
16712 #define THUMB_VARIANT & arm_ext_v6_notm
16713 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16714 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16715 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16716 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16717 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16718 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16719 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16720 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16721 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16722 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16723 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16724 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16726 /* ARM V6 not included in V7M (eg. integer SIMD). */
16727 #undef THUMB_VARIANT
16728 #define THUMB_VARIANT & arm_ext_v6_dsp
16729 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16730 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16731 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16732 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16733 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16734 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16735 /* Old name for QASX. */
16736 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16737 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16738 /* Old name for QSAX. */
16739 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16740 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16741 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16742 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16743 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16744 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16745 /* Old name for SASX. */
16746 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16747 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16748 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16749 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16750 /* Old name for SHASX. */
16751 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16752 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16753 /* Old name for SHSAX. */
16754 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16755 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16756 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16757 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16758 /* Old name for SSAX. */
16759 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16760 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16761 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16762 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16763 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16764 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16765 /* Old name for UASX. */
16766 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16767 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16768 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16769 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16770 /* Old name for UHASX. */
16771 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16772 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16773 /* Old name for UHSAX. */
16774 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16775 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16776 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16777 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16778 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16779 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16780 /* Old name for UQASX. */
16781 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16782 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16783 /* Old name for UQSAX. */
16784 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16785 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16786 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16787 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16788 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16789 /* Old name for USAX. */
16790 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16791 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16792 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16793 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16794 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16795 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16796 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16797 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16798 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16799 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16800 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16801 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16802 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16803 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16804 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16805 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16806 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16807 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16808 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16809 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16810 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16811 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16812 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16813 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16814 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16815 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16816 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16817 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16818 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16819 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16820 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16821 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16822 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16823 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16826 #define ARM_VARIANT & arm_ext_v6k
16827 #undef THUMB_VARIANT
16828 #define THUMB_VARIANT & arm_ext_v6k
16830 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16831 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16832 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16833 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16835 #undef THUMB_VARIANT
16836 #define THUMB_VARIANT & arm_ext_v6_notm
16837 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
16839 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
16840 RRnpcb
), strexd
, t_strexd
),
16842 #undef THUMB_VARIANT
16843 #define THUMB_VARIANT & arm_ext_v6t2
16844 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
16846 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
16848 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16850 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16852 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16855 #define ARM_VARIANT & arm_ext_v6z
16857 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16860 #define ARM_VARIANT & arm_ext_v6t2
16862 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16863 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16864 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16865 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16867 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16868 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16869 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16870 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16872 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16873 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16874 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16875 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16877 UT("cbnz", b900
, 2, (RR
, EXP
), t_cbz
),
16878 UT("cbz", b100
, 2, (RR
, EXP
), t_cbz
),
16880 /* ARM does not really have an IT instruction, so always allow it.
16881 The opcode is copied from Thumb in order to allow warnings in
16882 -mimplicit-it=[never | arm] modes. */
16884 #define ARM_VARIANT & arm_ext_v1
16886 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
16887 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
16888 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
16889 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
16890 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
16891 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
16892 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
16893 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
16894 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
16895 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
16896 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
16897 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
16898 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
16899 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
16900 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
16901 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
16902 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16903 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
16905 /* Thumb2 only instructions. */
16907 #define ARM_VARIANT NULL
16909 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16910 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
16911 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16912 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
16913 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
16914 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
16916 /* Thumb-2 hardware division instructions (R and M profiles only). */
16917 #undef THUMB_VARIANT
16918 #define THUMB_VARIANT & arm_ext_div
16920 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16921 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
16923 /* ARM V6M/V7 instructions. */
16925 #define ARM_VARIANT & arm_ext_barrier
16926 #undef THUMB_VARIANT
16927 #define THUMB_VARIANT & arm_ext_barrier
16929 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
16930 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
16931 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
16933 /* ARM V7 instructions. */
16935 #define ARM_VARIANT & arm_ext_v7
16936 #undef THUMB_VARIANT
16937 #define THUMB_VARIANT & arm_ext_v7
16939 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
16940 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
16943 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
16945 cCE("wfs", e200110
, 1, (RR
), rd
),
16946 cCE("rfs", e300110
, 1, (RR
), rd
),
16947 cCE("wfc", e400110
, 1, (RR
), rd
),
16948 cCE("rfc", e500110
, 1, (RR
), rd
),
16950 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16951 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16952 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16953 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16955 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16956 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16957 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16958 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
16960 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
16961 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
16962 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
16963 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
16964 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
16965 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
16966 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
16967 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
16968 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
16969 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
16970 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
16971 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
16973 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
16974 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
16975 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
16976 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
16977 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
16978 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
16979 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
16980 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
16981 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
16982 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
16983 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
16984 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
16986 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
16987 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
16988 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
16989 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
16990 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
16991 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
16992 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
16993 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
16994 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
16995 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
16996 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
16997 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
16999 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17000 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17001 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17002 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17003 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17004 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17005 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17006 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17007 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17008 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17009 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17010 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17012 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17013 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17014 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17015 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17016 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17017 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17018 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17019 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17020 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17021 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17022 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17023 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17025 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17026 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17027 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17028 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17029 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17030 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17031 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17032 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17033 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17034 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17035 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17036 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17038 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17039 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17040 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17041 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17042 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17043 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17044 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17045 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17046 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17047 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17048 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17049 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17051 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17052 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17053 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17054 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17055 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17056 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17057 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17058 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17059 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17060 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17061 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17062 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17064 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17065 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17066 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17067 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17068 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17069 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17070 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17071 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17072 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17073 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17074 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17075 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17077 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17078 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17079 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17080 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17081 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17082 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17083 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17084 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17085 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17086 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17087 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17088 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17090 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17091 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17092 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17093 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17094 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17095 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17096 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17097 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17098 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17099 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17100 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17101 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17103 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17104 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17105 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17106 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17107 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17108 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17109 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17110 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17111 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17112 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17113 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17114 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17116 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17117 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17118 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17119 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17120 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17121 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17122 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17123 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17124 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17125 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17126 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17127 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17129 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17130 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17131 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17132 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17133 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17134 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17135 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17136 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17137 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17138 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17139 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17140 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17142 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17143 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17144 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17145 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17146 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17147 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17148 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17149 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17150 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17151 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17152 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17153 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17155 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17156 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17157 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17158 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17159 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17160 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17161 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17162 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17163 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17164 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17165 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17166 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17168 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17169 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17170 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17171 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17172 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17173 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17174 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17175 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17176 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17177 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17178 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17179 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17181 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17182 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17183 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17184 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17185 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17186 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17187 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17188 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17189 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17190 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17191 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17192 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17194 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17195 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17196 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17197 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17198 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17199 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17200 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17201 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17202 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17203 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17204 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17205 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17207 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17208 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17209 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17210 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17211 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17212 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17213 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17214 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17215 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17216 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17217 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17218 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17220 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17221 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17222 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17223 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17224 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17225 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17226 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17227 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17228 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17229 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17230 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17231 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17233 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17234 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17235 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17236 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17237 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17238 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17239 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17240 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17241 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17242 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17243 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17244 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17246 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17247 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17248 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17249 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17250 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17251 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17252 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17253 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17254 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17255 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17256 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17257 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17259 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17260 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17261 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17262 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17263 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17264 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17265 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17266 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17267 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17268 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17269 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17270 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17272 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17273 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17274 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17275 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17276 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17277 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17278 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17279 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17280 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17281 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17282 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17283 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17285 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17286 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17287 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17288 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17289 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17290 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17291 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17292 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17293 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17294 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17295 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17296 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17298 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17299 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17300 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17301 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17302 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17303 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17304 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17305 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17306 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17307 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17308 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17309 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17311 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17312 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17313 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17314 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17315 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17316 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17317 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17318 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17319 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17320 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17321 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17322 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17324 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17325 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17326 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17327 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17328 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17329 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17330 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17331 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17332 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17333 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17334 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17335 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17337 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17338 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17339 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17340 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17342 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17343 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17344 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17345 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17346 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17347 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17348 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17349 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17350 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17351 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17352 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17353 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17355 /* The implementation of the FIX instruction is broken on some
17356 assemblers, in that it accepts a precision specifier as well as a
17357 rounding specifier, despite the fact that this is meaningless.
17358 To be more compatible, we accept it as well, though of course it
17359 does not set any bits. */
17360 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17361 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17362 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17363 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17364 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17365 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17366 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17367 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17368 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17369 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17370 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17371 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17372 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17374 /* Instructions that were new with the real FPA, call them V2. */
17376 #define ARM_VARIANT & fpu_fpa_ext_v2
17378 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17379 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17380 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17381 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17382 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17383 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17386 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17388 /* Moves and type conversions. */
17389 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17390 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17391 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17392 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17393 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17394 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17395 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17396 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17397 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17398 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17399 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17400 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17401 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17402 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17404 /* Memory operations. */
17405 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17406 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17407 cCE("fldmias", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17408 cCE("fldmfds", c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17409 cCE("fldmdbs", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17410 cCE("fldmeas", d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17411 cCE("fldmiax", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17412 cCE("fldmfdx", c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17413 cCE("fldmdbx", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17414 cCE("fldmeax", d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17415 cCE("fstmias", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17416 cCE("fstmeas", c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
17417 cCE("fstmdbs", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17418 cCE("fstmfds", d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
17419 cCE("fstmiax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17420 cCE("fstmeax", c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
17421 cCE("fstmdbx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17422 cCE("fstmfdx", d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
17424 /* Monadic operations. */
17425 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17426 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17427 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17429 /* Dyadic operations. */
17430 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17431 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17432 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17433 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17434 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17435 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17436 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17437 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17438 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17441 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17442 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17443 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17444 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17446 /* Double precision load/store are still present on single precision
17447 implementations. */
17448 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17449 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17450 cCE("fldmiad", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17451 cCE("fldmfdd", c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17452 cCE("fldmdbd", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17453 cCE("fldmead", d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17454 cCE("fstmiad", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17455 cCE("fstmead", c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
17456 cCE("fstmdbd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17457 cCE("fstmfdd", d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
17460 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17462 /* Moves and type conversions. */
17463 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17464 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17465 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17466 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17467 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17468 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17469 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17470 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17471 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17472 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17473 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17474 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17475 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17477 /* Monadic operations. */
17478 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17479 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17480 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17482 /* Dyadic operations. */
17483 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17484 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17485 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17486 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17487 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17488 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17489 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17490 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17491 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17494 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17495 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17496 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17497 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17500 #define ARM_VARIANT & fpu_vfp_ext_v2
17502 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17503 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17504 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17505 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17507 /* Instructions which may belong to either the Neon or VFP instruction sets.
17508 Individual encoder functions perform additional architecture checks. */
17510 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17511 #undef THUMB_VARIANT
17512 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17514 /* These mnemonics are unique to VFP. */
17515 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17516 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17517 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17518 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17519 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17520 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17521 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17522 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17523 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17524 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17526 /* Mnemonics shared by Neon and VFP. */
17527 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17528 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17529 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17531 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17532 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17534 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17535 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17537 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17538 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17539 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17540 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17541 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17542 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
17543 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17544 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17546 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17547 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17548 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17549 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17552 /* NOTE: All VMOV encoding is special-cased! */
17553 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17554 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17556 #undef THUMB_VARIANT
17557 #define THUMB_VARIANT & fpu_neon_ext_v1
17559 #define ARM_VARIANT & fpu_neon_ext_v1
17561 /* Data processing with three registers of the same length. */
17562 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17563 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17564 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17565 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17566 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17567 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17568 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17569 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17570 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17571 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17572 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17573 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17574 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17575 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17576 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17577 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17578 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17579 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17580 /* If not immediate, fall back to neon_dyadic_i64_su.
17581 shl_imm should accept I8 I16 I32 I64,
17582 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17583 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17584 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17585 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17586 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17587 /* Logic ops, types optional & ignored. */
17588 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17589 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17590 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17591 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17592 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17593 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17594 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17595 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17596 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17597 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17598 /* Bitfield ops, untyped. */
17599 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17600 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17601 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17602 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17603 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17604 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17605 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17606 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17607 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17608 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17609 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17610 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17611 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17612 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17613 back to neon_dyadic_if_su. */
17614 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17615 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17616 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17617 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17618 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17619 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17620 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17621 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17622 /* Comparison. Type I8 I16 I32 F32. */
17623 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17624 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17625 /* As above, D registers only. */
17626 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17627 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17628 /* Int and float variants, signedness unimportant. */
17629 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17630 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17631 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17632 /* Add/sub take types I8 I16 I32 I64 F32. */
17633 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17634 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17635 /* vtst takes sizes 8, 16, 32. */
17636 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17637 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17638 /* VMUL takes I8 I16 I32 F32 P8. */
17639 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17640 /* VQD{R}MULH takes S16 S32. */
17641 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17642 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17643 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17644 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17645 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17646 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17647 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17648 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17649 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17650 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17651 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17652 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17653 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17654 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17655 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17656 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17658 /* Two address, int/float. Types S8 S16 S32 F32. */
17659 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17660 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17662 /* Data processing with two registers and a shift amount. */
17663 /* Right shifts, and variants with rounding.
17664 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17665 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17666 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17667 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17668 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17669 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17670 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17671 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17672 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17673 /* Shift and insert. Sizes accepted 8 16 32 64. */
17674 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17675 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17676 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17677 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17678 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17679 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17680 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17681 /* Right shift immediate, saturating & narrowing, with rounding variants.
17682 Types accepted S16 S32 S64 U16 U32 U64. */
17683 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17684 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17685 /* As above, unsigned. Types accepted S16 S32 S64. */
17686 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17687 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17688 /* Right shift narrowing. Types accepted I16 I32 I64. */
17689 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17690 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17691 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17692 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17693 /* CVT with optional immediate for fixed-point variant. */
17694 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17696 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17697 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17699 /* Data processing, three registers of different lengths. */
17700 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17701 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17702 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17703 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17704 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17705 /* If not scalar, fall back to neon_dyadic_long.
17706 Vector types as above, scalar types S16 S32 U16 U32. */
17707 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17708 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17709 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17710 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17711 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17712 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17713 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17714 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17715 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17716 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17717 /* Saturating doubling multiplies. Types S16 S32. */
17718 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17719 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17720 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17721 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17722 S16 S32 U16 U32. */
17723 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17725 /* Extract. Size 8. */
17726 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17727 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17729 /* Two registers, miscellaneous. */
17730 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17731 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17732 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17733 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17734 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17735 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17736 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17737 /* Vector replicate. Sizes 8 16 32. */
17738 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17739 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17740 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17741 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17742 /* VMOVN. Types I16 I32 I64. */
17743 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17744 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17745 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17746 /* VQMOVUN. Types S16 S32 S64. */
17747 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17748 /* VZIP / VUZP. Sizes 8 16 32. */
17749 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17750 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17751 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17752 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17753 /* VQABS / VQNEG. Types S8 S16 S32. */
17754 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17755 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17756 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17757 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17758 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17759 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17760 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17761 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17762 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17763 /* Reciprocal estimates. Types U32 F32. */
17764 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17765 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17766 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17767 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17768 /* VCLS. Types S8 S16 S32. */
17769 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17770 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17771 /* VCLZ. Types I8 I16 I32. */
17772 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17773 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17774 /* VCNT. Size 8. */
17775 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17776 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17777 /* Two address, untyped. */
17778 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17779 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17780 /* VTRN. Sizes 8 16 32. */
17781 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17782 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17784 /* Table lookup. Size 8. */
17785 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17786 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17788 #undef THUMB_VARIANT
17789 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17791 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17793 /* Neon element/structure load/store. */
17794 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17795 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17796 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17797 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17798 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17799 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17800 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17801 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17803 #undef THUMB_VARIANT
17804 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17806 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17807 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17808 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17809 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17810 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17811 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17812 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17813 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17814 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17815 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17817 #undef THUMB_VARIANT
17818 #define THUMB_VARIANT & fpu_vfp_ext_v3
17820 #define ARM_VARIANT & fpu_vfp_ext_v3
17822 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17823 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17824 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17825 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17826 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17827 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17828 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17829 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17830 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17833 #define ARM_VARIANT &fpu_vfp_ext_fma
17834 #undef THUMB_VARIANT
17835 #define THUMB_VARIANT &fpu_vfp_ext_fma
17836 /* Mnemonics shared by Neon and VFP. These are included in the
17837 VFP FMA variant; NEON and VFP FMA always includes the NEON
17838 FMA instructions. */
17839 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17840 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17841 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17842 the v form should always be used. */
17843 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17844 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17845 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17846 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17847 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17848 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17850 #undef THUMB_VARIANT
17852 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17854 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17855 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17856 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17857 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17858 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17859 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17860 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17861 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17864 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17866 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17867 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17868 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17869 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17870 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17871 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17872 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17873 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17874 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17875 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17876 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17877 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17878 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17879 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17880 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17881 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17882 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17883 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
17884 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
17885 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
17886 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17887 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17888 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17889 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17890 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17891 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
17892 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
17893 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
17894 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
17895 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
17896 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
17897 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
17898 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
17899 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
17900 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17901 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17902 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
17903 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17904 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17905 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17906 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17907 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17908 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17909 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17910 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17911 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17912 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
17913 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17914 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17915 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17916 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17917 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17918 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17919 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17920 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17921 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17922 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17923 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17924 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17925 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17926 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17927 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17928 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17929 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17930 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17931 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17932 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17933 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17934 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17935 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17936 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17937 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17938 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17939 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17940 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17941 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17942 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17943 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17944 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17945 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17946 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17947 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17948 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17949 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17950 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17951 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17952 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17953 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17954 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
17955 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17956 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17957 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17958 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17959 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17960 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17961 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17962 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17963 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17964 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17965 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17966 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17967 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17968 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17969 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17970 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17971 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17972 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17973 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17974 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17975 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17976 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
17977 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17978 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17979 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17980 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17981 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17982 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17983 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17984 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17985 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17986 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17987 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17988 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17989 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17990 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17991 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17992 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17993 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
17994 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
17995 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17996 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
17997 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
17998 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
17999 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18000 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18001 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18002 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18003 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18004 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18005 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18006 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18007 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18008 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18009 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18010 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18011 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18012 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18013 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18014 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18015 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18016 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18017 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18018 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18019 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18020 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18021 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18022 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18023 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18024 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18025 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18026 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18027 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18030 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18032 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18033 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18034 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18035 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18036 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18037 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18038 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18039 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18040 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18041 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18042 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18043 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18044 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18045 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18046 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18047 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18048 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18049 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18050 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18051 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18052 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18053 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18054 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18055 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18056 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18057 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18058 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18059 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18060 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18061 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18062 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18063 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18064 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18065 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18066 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18067 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18068 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18069 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18070 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18071 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18072 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18073 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18074 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18075 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18076 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18077 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18078 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18079 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18080 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18081 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18082 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18083 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18084 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18085 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18086 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18087 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18088 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18091 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18093 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18094 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18095 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18096 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18097 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18098 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18099 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18100 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18101 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18102 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18103 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18104 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18105 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18106 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18107 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18108 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18109 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18110 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18111 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18112 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18113 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18114 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18115 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18116 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18117 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18118 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18119 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18120 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18121 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18122 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18123 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18124 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18125 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18126 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18127 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18128 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18129 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18130 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18131 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18132 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18133 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18134 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18135 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18136 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18137 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18138 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18139 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18140 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18141 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18142 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18143 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18144 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18145 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18146 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18147 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18148 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18149 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18150 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18151 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18152 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18153 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18154 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18155 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18156 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18157 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18158 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18159 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18160 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18161 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18162 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18163 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18164 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18165 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18166 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18167 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18168 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18171 #undef THUMB_VARIANT
18198 /* MD interface: bits in the object file. */
18200 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18201 for use in the a.out file, and stores them in the array pointed to by buf.
18202 This knows about the endian-ness of the target machine and does
18203 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18204 2 (short) and 4 (long) Floating numbers are put out as a series of
18205 LITTLENUMS (shorts, here at least). */
18208 md_number_to_chars (char * buf
, valueT val
, int n
)
18210 if (target_big_endian
)
18211 number_to_chars_bigendian (buf
, val
, n
);
18213 number_to_chars_littleendian (buf
, val
, n
);
18217 md_chars_to_number (char * buf
, int n
)
18220 unsigned char * where
= (unsigned char *) buf
;
18222 if (target_big_endian
)
18227 result
|= (*where
++ & 255);
18235 result
|= (where
[n
] & 255);
18242 /* MD interface: Sections. */
18244 /* Estimate the size of a frag before relaxing. Assume everything fits in
18248 md_estimate_size_before_relax (fragS
* fragp
,
18249 segT segtype ATTRIBUTE_UNUSED
)
18255 /* Convert a machine dependent frag. */
18258 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18260 unsigned long insn
;
18261 unsigned long old_op
;
18269 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18271 old_op
= bfd_get_16(abfd
, buf
);
18272 if (fragp
->fr_symbol
)
18274 exp
.X_op
= O_symbol
;
18275 exp
.X_add_symbol
= fragp
->fr_symbol
;
18279 exp
.X_op
= O_constant
;
18281 exp
.X_add_number
= fragp
->fr_offset
;
18282 opcode
= fragp
->fr_subtype
;
18285 case T_MNEM_ldr_pc
:
18286 case T_MNEM_ldr_pc2
:
18287 case T_MNEM_ldr_sp
:
18288 case T_MNEM_str_sp
:
18295 if (fragp
->fr_var
== 4)
18297 insn
= THUMB_OP32 (opcode
);
18298 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18300 insn
|= (old_op
& 0x700) << 4;
18304 insn
|= (old_op
& 7) << 12;
18305 insn
|= (old_op
& 0x38) << 13;
18307 insn
|= 0x00000c00;
18308 put_thumb32_insn (buf
, insn
);
18309 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18313 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18315 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18318 if (fragp
->fr_var
== 4)
18320 insn
= THUMB_OP32 (opcode
);
18321 insn
|= (old_op
& 0xf0) << 4;
18322 put_thumb32_insn (buf
, insn
);
18323 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18327 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18328 exp
.X_add_number
-= 4;
18336 if (fragp
->fr_var
== 4)
18338 int r0off
= (opcode
== T_MNEM_mov
18339 || opcode
== T_MNEM_movs
) ? 0 : 8;
18340 insn
= THUMB_OP32 (opcode
);
18341 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18342 insn
|= (old_op
& 0x700) << r0off
;
18343 put_thumb32_insn (buf
, insn
);
18344 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18348 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18353 if (fragp
->fr_var
== 4)
18355 insn
= THUMB_OP32(opcode
);
18356 put_thumb32_insn (buf
, insn
);
18357 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18360 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18364 if (fragp
->fr_var
== 4)
18366 insn
= THUMB_OP32(opcode
);
18367 insn
|= (old_op
& 0xf00) << 14;
18368 put_thumb32_insn (buf
, insn
);
18369 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18372 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18375 case T_MNEM_add_sp
:
18376 case T_MNEM_add_pc
:
18377 case T_MNEM_inc_sp
:
18378 case T_MNEM_dec_sp
:
18379 if (fragp
->fr_var
== 4)
18381 /* ??? Choose between add and addw. */
18382 insn
= THUMB_OP32 (opcode
);
18383 insn
|= (old_op
& 0xf0) << 4;
18384 put_thumb32_insn (buf
, insn
);
18385 if (opcode
== T_MNEM_add_pc
)
18386 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18388 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18391 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18399 if (fragp
->fr_var
== 4)
18401 insn
= THUMB_OP32 (opcode
);
18402 insn
|= (old_op
& 0xf0) << 4;
18403 insn
|= (old_op
& 0xf) << 16;
18404 put_thumb32_insn (buf
, insn
);
18405 if (insn
& (1 << 20))
18406 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18408 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18411 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18417 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18418 (enum bfd_reloc_code_real
) reloc_type
);
18419 fixp
->fx_file
= fragp
->fr_file
;
18420 fixp
->fx_line
= fragp
->fr_line
;
18421 fragp
->fr_fix
+= fragp
->fr_var
;
18424 /* Return the size of a relaxable immediate operand instruction.
18425 SHIFT and SIZE specify the form of the allowable immediate. */
18427 relax_immediate (fragS
*fragp
, int size
, int shift
)
18433 /* ??? Should be able to do better than this. */
18434 if (fragp
->fr_symbol
)
18437 low
= (1 << shift
) - 1;
18438 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18439 offset
= fragp
->fr_offset
;
18440 /* Force misaligned offsets to 32-bit variant. */
18443 if (offset
& ~mask
)
18448 /* Get the address of a symbol during relaxation. */
18450 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18456 sym
= fragp
->fr_symbol
;
18457 sym_frag
= symbol_get_frag (sym
);
18458 know (S_GET_SEGMENT (sym
) != absolute_section
18459 || sym_frag
== &zero_address_frag
);
18460 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18462 /* If frag has yet to be reached on this pass, assume it will
18463 move by STRETCH just as we did. If this is not so, it will
18464 be because some frag between grows, and that will force
18468 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18472 /* Adjust stretch for any alignment frag. Note that if have
18473 been expanding the earlier code, the symbol may be
18474 defined in what appears to be an earlier frag. FIXME:
18475 This doesn't handle the fr_subtype field, which specifies
18476 a maximum number of bytes to skip when doing an
18478 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18480 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18483 stretch
= - ((- stretch
)
18484 & ~ ((1 << (int) f
->fr_offset
) - 1));
18486 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18498 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18501 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18506 /* Assume worst case for symbols not known to be in the same section. */
18507 if (fragp
->fr_symbol
== NULL
18508 || !S_IS_DEFINED (fragp
->fr_symbol
)
18509 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18512 val
= relaxed_symbol_addr (fragp
, stretch
);
18513 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18514 addr
= (addr
+ 4) & ~3;
18515 /* Force misaligned targets to 32-bit variant. */
18519 if (val
< 0 || val
> 1020)
18524 /* Return the size of a relaxable add/sub immediate instruction. */
18526 relax_addsub (fragS
*fragp
, asection
*sec
)
18531 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18532 op
= bfd_get_16(sec
->owner
, buf
);
18533 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18534 return relax_immediate (fragp
, 8, 0);
18536 return relax_immediate (fragp
, 3, 0);
18540 /* Return the size of a relaxable branch instruction. BITS is the
18541 size of the offset field in the narrow instruction. */
18544 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18550 /* Assume worst case for symbols not known to be in the same section. */
18551 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18552 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
18556 if (S_IS_DEFINED (fragp
->fr_symbol
)
18557 && ARM_IS_FUNC (fragp
->fr_symbol
))
18561 val
= relaxed_symbol_addr (fragp
, stretch
);
18562 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18565 /* Offset is a signed value *2 */
18567 if (val
>= limit
|| val
< -limit
)
18573 /* Relax a machine dependent frag. This returns the amount by which
18574 the current size of the frag should change. */
18577 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18582 oldsize
= fragp
->fr_var
;
18583 switch (fragp
->fr_subtype
)
18585 case T_MNEM_ldr_pc2
:
18586 newsize
= relax_adr (fragp
, sec
, stretch
);
18588 case T_MNEM_ldr_pc
:
18589 case T_MNEM_ldr_sp
:
18590 case T_MNEM_str_sp
:
18591 newsize
= relax_immediate (fragp
, 8, 2);
18595 newsize
= relax_immediate (fragp
, 5, 2);
18599 newsize
= relax_immediate (fragp
, 5, 1);
18603 newsize
= relax_immediate (fragp
, 5, 0);
18606 newsize
= relax_adr (fragp
, sec
, stretch
);
18612 newsize
= relax_immediate (fragp
, 8, 0);
18615 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18618 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18620 case T_MNEM_add_sp
:
18621 case T_MNEM_add_pc
:
18622 newsize
= relax_immediate (fragp
, 8, 2);
18624 case T_MNEM_inc_sp
:
18625 case T_MNEM_dec_sp
:
18626 newsize
= relax_immediate (fragp
, 7, 2);
18632 newsize
= relax_addsub (fragp
, sec
);
18638 fragp
->fr_var
= newsize
;
18639 /* Freeze wide instructions that are at or before the same location as
18640 in the previous pass. This avoids infinite loops.
18641 Don't freeze them unconditionally because targets may be artificially
18642 misaligned by the expansion of preceding frags. */
18643 if (stretch
<= 0 && newsize
> 2)
18645 md_convert_frag (sec
->owner
, sec
, fragp
);
18649 return newsize
- oldsize
;
18652 /* Round up a section size to the appropriate boundary. */
18655 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18658 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18659 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18661 /* For a.out, force the section size to be aligned. If we don't do
18662 this, BFD will align it for us, but it will not write out the
18663 final bytes of the section. This may be a bug in BFD, but it is
18664 easier to fix it here since that is how the other a.out targets
18668 align
= bfd_get_section_alignment (stdoutput
, segment
);
18669 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18676 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18677 of an rs_align_code fragment. */
18680 arm_handle_align (fragS
* fragP
)
18682 static char const arm_noop
[2][2][4] =
18685 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18686 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18689 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18690 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18693 static char const thumb_noop
[2][2][2] =
18696 {0xc0, 0x46}, /* LE */
18697 {0x46, 0xc0}, /* BE */
18700 {0x00, 0xbf}, /* LE */
18701 {0xbf, 0x00} /* BE */
18704 static char const wide_thumb_noop
[2][4] =
18705 { /* Wide Thumb-2 */
18706 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18707 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18710 unsigned bytes
, fix
, noop_size
;
18713 const char *narrow_noop
= NULL
;
18718 if (fragP
->fr_type
!= rs_align_code
)
18721 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18722 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18725 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18726 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18728 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18730 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18732 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18734 narrow_noop
= thumb_noop
[1][target_big_endian
];
18735 noop
= wide_thumb_noop
[target_big_endian
];
18738 noop
= thumb_noop
[0][target_big_endian
];
18746 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18747 [target_big_endian
];
18754 fragP
->fr_var
= noop_size
;
18756 if (bytes
& (noop_size
- 1))
18758 fix
= bytes
& (noop_size
- 1);
18760 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18762 memset (p
, 0, fix
);
18769 if (bytes
& noop_size
)
18771 /* Insert a narrow noop. */
18772 memcpy (p
, narrow_noop
, noop_size
);
18774 bytes
-= noop_size
;
18778 /* Use wide noops for the remainder */
18782 while (bytes
>= noop_size
)
18784 memcpy (p
, noop
, noop_size
);
18786 bytes
-= noop_size
;
18790 fragP
->fr_fix
+= fix
;
18793 /* Called from md_do_align. Used to create an alignment
18794 frag in a code section. */
18797 arm_frag_align_code (int n
, int max
)
18801 /* We assume that there will never be a requirement
18802 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18803 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18808 _("alignments greater than %d bytes not supported in .text sections."),
18809 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18810 as_fatal ("%s", err_msg
);
18813 p
= frag_var (rs_align_code
,
18814 MAX_MEM_FOR_RS_ALIGN_CODE
,
18816 (relax_substateT
) max
,
18823 /* Perform target specific initialisation of a frag.
18824 Note - despite the name this initialisation is not done when the frag
18825 is created, but only when its type is assigned. A frag can be created
18826 and used a long time before its type is set, so beware of assuming that
18827 this initialisationis performed first. */
18831 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18833 /* Record whether this frag is in an ARM or a THUMB area. */
18834 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18837 #else /* OBJ_ELF is defined. */
18839 arm_init_frag (fragS
* fragP
, int max_chars
)
18841 /* If the current ARM vs THUMB mode has not already
18842 been recorded into this frag then do so now. */
18843 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18845 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18847 /* Record a mapping symbol for alignment frags. We will delete this
18848 later if the alignment ends up empty. */
18849 switch (fragP
->fr_type
)
18852 case rs_align_test
:
18854 mapping_state_2 (MAP_DATA
, max_chars
);
18856 case rs_align_code
:
18857 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18865 /* When we change sections we need to issue a new mapping symbol. */
18868 arm_elf_change_section (void)
18870 /* Link an unlinked unwind index table section to the .text section. */
18871 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18872 && elf_linked_to_section (now_seg
) == NULL
)
18873 elf_linked_to_section (now_seg
) = text_section
;
18877 arm_elf_section_type (const char * str
, size_t len
)
18879 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
18880 return SHT_ARM_EXIDX
;
18885 /* Code to deal with unwinding tables. */
18887 static void add_unwind_adjustsp (offsetT
);
18889 /* Generate any deferred unwind frame offset. */
18892 flush_pending_unwind (void)
18896 offset
= unwind
.pending_offset
;
18897 unwind
.pending_offset
= 0;
18899 add_unwind_adjustsp (offset
);
18902 /* Add an opcode to this list for this function. Two-byte opcodes should
18903 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
18907 add_unwind_opcode (valueT op
, int length
)
18909 /* Add any deferred stack adjustment. */
18910 if (unwind
.pending_offset
)
18911 flush_pending_unwind ();
18913 unwind
.sp_restored
= 0;
18915 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
18917 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
18918 if (unwind
.opcodes
)
18919 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
18920 unwind
.opcode_alloc
);
18922 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
18927 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
18929 unwind
.opcode_count
++;
18933 /* Add unwind opcodes to adjust the stack pointer. */
18936 add_unwind_adjustsp (offsetT offset
)
18940 if (offset
> 0x200)
18942 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
18947 /* Long form: 0xb2, uleb128. */
18948 /* This might not fit in a word so add the individual bytes,
18949 remembering the list is built in reverse order. */
18950 o
= (valueT
) ((offset
- 0x204) >> 2);
18952 add_unwind_opcode (0, 1);
18954 /* Calculate the uleb128 encoding of the offset. */
18958 bytes
[n
] = o
& 0x7f;
18964 /* Add the insn. */
18966 add_unwind_opcode (bytes
[n
- 1], 1);
18967 add_unwind_opcode (0xb2, 1);
18969 else if (offset
> 0x100)
18971 /* Two short opcodes. */
18972 add_unwind_opcode (0x3f, 1);
18973 op
= (offset
- 0x104) >> 2;
18974 add_unwind_opcode (op
, 1);
18976 else if (offset
> 0)
18978 /* Short opcode. */
18979 op
= (offset
- 4) >> 2;
18980 add_unwind_opcode (op
, 1);
18982 else if (offset
< 0)
18985 while (offset
> 0x100)
18987 add_unwind_opcode (0x7f, 1);
18990 op
= ((offset
- 4) >> 2) | 0x40;
18991 add_unwind_opcode (op
, 1);
18995 /* Finish the list of unwind opcodes for this function. */
18997 finish_unwind_opcodes (void)
19001 if (unwind
.fp_used
)
19003 /* Adjust sp as necessary. */
19004 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19005 flush_pending_unwind ();
19007 /* After restoring sp from the frame pointer. */
19008 op
= 0x90 | unwind
.fp_reg
;
19009 add_unwind_opcode (op
, 1);
19012 flush_pending_unwind ();
19016 /* Start an exception table entry. If idx is nonzero this is an index table
19020 start_unwind_section (const segT text_seg
, int idx
)
19022 const char * text_name
;
19023 const char * prefix
;
19024 const char * prefix_once
;
19025 const char * group_name
;
19029 size_t sec_name_len
;
19036 prefix
= ELF_STRING_ARM_unwind
;
19037 prefix_once
= ELF_STRING_ARM_unwind_once
;
19038 type
= SHT_ARM_EXIDX
;
19042 prefix
= ELF_STRING_ARM_unwind_info
;
19043 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19044 type
= SHT_PROGBITS
;
19047 text_name
= segment_name (text_seg
);
19048 if (streq (text_name
, ".text"))
19051 if (strncmp (text_name
, ".gnu.linkonce.t.",
19052 strlen (".gnu.linkonce.t.")) == 0)
19054 prefix
= prefix_once
;
19055 text_name
+= strlen (".gnu.linkonce.t.");
19058 prefix_len
= strlen (prefix
);
19059 text_len
= strlen (text_name
);
19060 sec_name_len
= prefix_len
+ text_len
;
19061 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19062 memcpy (sec_name
, prefix
, prefix_len
);
19063 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19064 sec_name
[prefix_len
+ text_len
] = '\0';
19070 /* Handle COMDAT group. */
19071 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19073 group_name
= elf_group_name (text_seg
);
19074 if (group_name
== NULL
)
19076 as_bad (_("Group section `%s' has no group signature"),
19077 segment_name (text_seg
));
19078 ignore_rest_of_line ();
19081 flags
|= SHF_GROUP
;
19085 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19087 /* Set the section link for index tables. */
19089 elf_linked_to_section (now_seg
) = text_seg
;
19093 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19094 personality routine data. Returns zero, or the index table value for
19095 and inline entry. */
19098 create_unwind_entry (int have_data
)
19103 /* The current word of data. */
19105 /* The number of bytes left in this word. */
19108 finish_unwind_opcodes ();
19110 /* Remember the current text section. */
19111 unwind
.saved_seg
= now_seg
;
19112 unwind
.saved_subseg
= now_subseg
;
19114 start_unwind_section (now_seg
, 0);
19116 if (unwind
.personality_routine
== NULL
)
19118 if (unwind
.personality_index
== -2)
19121 as_bad (_("handlerdata in cantunwind frame"));
19122 return 1; /* EXIDX_CANTUNWIND. */
19125 /* Use a default personality routine if none is specified. */
19126 if (unwind
.personality_index
== -1)
19128 if (unwind
.opcode_count
> 3)
19129 unwind
.personality_index
= 1;
19131 unwind
.personality_index
= 0;
19134 /* Space for the personality routine entry. */
19135 if (unwind
.personality_index
== 0)
19137 if (unwind
.opcode_count
> 3)
19138 as_bad (_("too many unwind opcodes for personality routine 0"));
19142 /* All the data is inline in the index table. */
19145 while (unwind
.opcode_count
> 0)
19147 unwind
.opcode_count
--;
19148 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19152 /* Pad with "finish" opcodes. */
19154 data
= (data
<< 8) | 0xb0;
19161 /* We get two opcodes "free" in the first word. */
19162 size
= unwind
.opcode_count
- 2;
19165 /* An extra byte is required for the opcode count. */
19166 size
= unwind
.opcode_count
+ 1;
19168 size
= (size
+ 3) >> 2;
19170 as_bad (_("too many unwind opcodes"));
19172 frag_align (2, 0, 0);
19173 record_alignment (now_seg
, 2);
19174 unwind
.table_entry
= expr_build_dot ();
19176 /* Allocate the table entry. */
19177 ptr
= frag_more ((size
<< 2) + 4);
19178 where
= frag_now_fix () - ((size
<< 2) + 4);
19180 switch (unwind
.personality_index
)
19183 /* ??? Should this be a PLT generating relocation? */
19184 /* Custom personality routine. */
19185 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19186 BFD_RELOC_ARM_PREL31
);
19191 /* Set the first byte to the number of additional words. */
19196 /* ABI defined personality routines. */
19198 /* Three opcodes bytes are packed into the first word. */
19205 /* The size and first two opcode bytes go in the first word. */
19206 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19211 /* Should never happen. */
19215 /* Pack the opcodes into words (MSB first), reversing the list at the same
19217 while (unwind
.opcode_count
> 0)
19221 md_number_to_chars (ptr
, data
, 4);
19226 unwind
.opcode_count
--;
19228 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19231 /* Finish off the last word. */
19234 /* Pad with "finish" opcodes. */
19236 data
= (data
<< 8) | 0xb0;
19238 md_number_to_chars (ptr
, data
, 4);
19243 /* Add an empty descriptor if there is no user-specified data. */
19244 ptr
= frag_more (4);
19245 md_number_to_chars (ptr
, 0, 4);
19252 /* Initialize the DWARF-2 unwind information for this procedure. */
19255 tc_arm_frame_initial_instructions (void)
19257 cfi_add_CFA_def_cfa (REG_SP
, 0);
19259 #endif /* OBJ_ELF */
19261 /* Convert REGNAME to a DWARF-2 register number. */
19264 tc_arm_regname_to_dw2regnum (char *regname
)
19266 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19276 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19280 exp
.X_op
= O_secrel
;
19281 exp
.X_add_symbol
= symbol
;
19282 exp
.X_add_number
= 0;
19283 emit_expr (&exp
, size
);
19287 /* MD interface: Symbol and relocation handling. */
19289 /* Return the address within the segment that a PC-relative fixup is
19290 relative to. For ARM, PC-relative fixups applied to instructions
19291 are generally relative to the location of the fixup plus 8 bytes.
19292 Thumb branches are offset by 4, and Thumb loads relative to PC
19293 require special handling. */
19296 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19298 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19300 /* If this is pc-relative and we are going to emit a relocation
19301 then we just want to put out any pipeline compensation that the linker
19302 will need. Otherwise we want to use the calculated base.
19303 For WinCE we skip the bias for externals as well, since this
19304 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19306 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19307 || (arm_force_relocation (fixP
)
19309 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19315 switch (fixP
->fx_r_type
)
19317 /* PC relative addressing on the Thumb is slightly odd as the
19318 bottom two bits of the PC are forced to zero for the
19319 calculation. This happens *after* application of the
19320 pipeline offset. However, Thumb adrl already adjusts for
19321 this, so we need not do it again. */
19322 case BFD_RELOC_ARM_THUMB_ADD
:
19325 case BFD_RELOC_ARM_THUMB_OFFSET
:
19326 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19327 case BFD_RELOC_ARM_T32_ADD_PC12
:
19328 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19329 return (base
+ 4) & ~3;
19331 /* Thumb branches are simply offset by +4. */
19332 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19333 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19334 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19335 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19336 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19339 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19341 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19342 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19343 && ARM_IS_FUNC (fixP
->fx_addsy
)
19344 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19345 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19348 /* BLX is like branches above, but forces the low two bits of PC to
19350 case BFD_RELOC_THUMB_PCREL_BLX
:
19352 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19353 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19354 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19355 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19356 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19357 return (base
+ 4) & ~3;
19359 /* ARM mode branches are offset by +8. However, the Windows CE
19360 loader expects the relocation not to take this into account. */
19361 case BFD_RELOC_ARM_PCREL_BLX
:
19363 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19364 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19365 && ARM_IS_FUNC (fixP
->fx_addsy
)
19366 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19367 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19370 case BFD_RELOC_ARM_PCREL_CALL
:
19372 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19373 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19374 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19375 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19376 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19379 case BFD_RELOC_ARM_PCREL_BRANCH
:
19380 case BFD_RELOC_ARM_PCREL_JUMP
:
19381 case BFD_RELOC_ARM_PLT32
:
19383 /* When handling fixups immediately, because we have already
19384 discovered the value of a symbol, or the address of the frag involved
19385 we must account for the offset by +8, as the OS loader will never see the reloc.
19386 see fixup_segment() in write.c
19387 The S_IS_EXTERNAL test handles the case of global symbols.
19388 Those need the calculated base, not just the pipe compensation the linker will need. */
19390 && fixP
->fx_addsy
!= NULL
19391 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19392 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19400 /* ARM mode loads relative to PC are also offset by +8. Unlike
19401 branches, the Windows CE loader *does* expect the relocation
19402 to take this into account. */
19403 case BFD_RELOC_ARM_OFFSET_IMM
:
19404 case BFD_RELOC_ARM_OFFSET_IMM8
:
19405 case BFD_RELOC_ARM_HWLITERAL
:
19406 case BFD_RELOC_ARM_LITERAL
:
19407 case BFD_RELOC_ARM_CP_OFF_IMM
:
19411 /* Other PC-relative relocations are un-offset. */
19417 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19418 Otherwise we have no need to default values of symbols. */
19421 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19424 if (name
[0] == '_' && name
[1] == 'G'
19425 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19429 if (symbol_find (name
))
19430 as_bad (_("GOT already in the symbol table"));
19432 GOT_symbol
= symbol_new (name
, undefined_section
,
19433 (valueT
) 0, & zero_address_frag
);
19443 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19444 computed as two separate immediate values, added together. We
19445 already know that this value cannot be computed by just one ARM
19448 static unsigned int
19449 validate_immediate_twopart (unsigned int val
,
19450 unsigned int * highpart
)
19455 for (i
= 0; i
< 32; i
+= 2)
19456 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19462 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19464 else if (a
& 0xff0000)
19466 if (a
& 0xff000000)
19468 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19472 gas_assert (a
& 0xff000000);
19473 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19476 return (a
& 0xff) | (i
<< 7);
19483 validate_offset_imm (unsigned int val
, int hwse
)
19485 if ((hwse
&& val
> 255) || val
> 4095)
19490 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19491 negative immediate constant by altering the instruction. A bit of
19496 by inverting the second operand, and
19499 by negating the second operand. */
19502 negate_data_op (unsigned long * instruction
,
19503 unsigned long value
)
19506 unsigned long negated
, inverted
;
19508 negated
= encode_arm_immediate (-value
);
19509 inverted
= encode_arm_immediate (~value
);
19511 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19514 /* First negates. */
19515 case OPCODE_SUB
: /* ADD <-> SUB */
19516 new_inst
= OPCODE_ADD
;
19521 new_inst
= OPCODE_SUB
;
19525 case OPCODE_CMP
: /* CMP <-> CMN */
19526 new_inst
= OPCODE_CMN
;
19531 new_inst
= OPCODE_CMP
;
19535 /* Now Inverted ops. */
19536 case OPCODE_MOV
: /* MOV <-> MVN */
19537 new_inst
= OPCODE_MVN
;
19542 new_inst
= OPCODE_MOV
;
19546 case OPCODE_AND
: /* AND <-> BIC */
19547 new_inst
= OPCODE_BIC
;
19552 new_inst
= OPCODE_AND
;
19556 case OPCODE_ADC
: /* ADC <-> SBC */
19557 new_inst
= OPCODE_SBC
;
19562 new_inst
= OPCODE_ADC
;
19566 /* We cannot do anything. */
19571 if (value
== (unsigned) FAIL
)
19574 *instruction
&= OPCODE_MASK
;
19575 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19579 /* Like negate_data_op, but for Thumb-2. */
19581 static unsigned int
19582 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19586 unsigned int negated
, inverted
;
19588 negated
= encode_thumb32_immediate (-value
);
19589 inverted
= encode_thumb32_immediate (~value
);
19591 rd
= (*instruction
>> 8) & 0xf;
19592 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19595 /* ADD <-> SUB. Includes CMP <-> CMN. */
19596 case T2_OPCODE_SUB
:
19597 new_inst
= T2_OPCODE_ADD
;
19601 case T2_OPCODE_ADD
:
19602 new_inst
= T2_OPCODE_SUB
;
19606 /* ORR <-> ORN. Includes MOV <-> MVN. */
19607 case T2_OPCODE_ORR
:
19608 new_inst
= T2_OPCODE_ORN
;
19612 case T2_OPCODE_ORN
:
19613 new_inst
= T2_OPCODE_ORR
;
19617 /* AND <-> BIC. TST has no inverted equivalent. */
19618 case T2_OPCODE_AND
:
19619 new_inst
= T2_OPCODE_BIC
;
19626 case T2_OPCODE_BIC
:
19627 new_inst
= T2_OPCODE_AND
;
19632 case T2_OPCODE_ADC
:
19633 new_inst
= T2_OPCODE_SBC
;
19637 case T2_OPCODE_SBC
:
19638 new_inst
= T2_OPCODE_ADC
;
19642 /* We cannot do anything. */
19647 if (value
== (unsigned int)FAIL
)
19650 *instruction
&= T2_OPCODE_MASK
;
19651 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19655 /* Read a 32-bit thumb instruction from buf. */
19656 static unsigned long
19657 get_thumb32_insn (char * buf
)
19659 unsigned long insn
;
19660 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19661 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19667 /* We usually want to set the low bit on the address of thumb function
19668 symbols. In particular .word foo - . should have the low bit set.
19669 Generic code tries to fold the difference of two symbols to
19670 a constant. Prevent this and force a relocation when the first symbols
19671 is a thumb function. */
19674 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19676 if (op
== O_subtract
19677 && l
->X_op
== O_symbol
19678 && r
->X_op
== O_symbol
19679 && THUMB_IS_FUNC (l
->X_add_symbol
))
19681 l
->X_op
= O_subtract
;
19682 l
->X_op_symbol
= r
->X_add_symbol
;
19683 l
->X_add_number
-= r
->X_add_number
;
19687 /* Process as normal. */
19691 /* Encode Thumb2 unconditional branches and calls. The encoding
19692 for the 2 are identical for the immediate values. */
19695 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19697 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19700 addressT S
, I1
, I2
, lo
, hi
;
19702 S
= (value
>> 24) & 0x01;
19703 I1
= (value
>> 23) & 0x01;
19704 I2
= (value
>> 22) & 0x01;
19705 hi
= (value
>> 12) & 0x3ff;
19706 lo
= (value
>> 1) & 0x7ff;
19707 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19708 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19709 newval
|= (S
<< 10) | hi
;
19710 newval2
&= ~T2I1I2MASK
;
19711 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19712 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19713 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19717 md_apply_fix (fixS
* fixP
,
19721 offsetT value
= * valP
;
19723 unsigned int newimm
;
19724 unsigned long temp
;
19726 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19728 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19730 /* Note whether this will delete the relocation. */
19732 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19735 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19736 consistency with the behaviour on 32-bit hosts. Remember value
19738 value
&= 0xffffffff;
19739 value
^= 0x80000000;
19740 value
-= 0x80000000;
19743 fixP
->fx_addnumber
= value
;
19745 /* Same treatment for fixP->fx_offset. */
19746 fixP
->fx_offset
&= 0xffffffff;
19747 fixP
->fx_offset
^= 0x80000000;
19748 fixP
->fx_offset
-= 0x80000000;
19750 switch (fixP
->fx_r_type
)
19752 case BFD_RELOC_NONE
:
19753 /* This will need to go in the object file. */
19757 case BFD_RELOC_ARM_IMMEDIATE
:
19758 /* We claim that this fixup has been processed here,
19759 even if in fact we generate an error because we do
19760 not have a reloc for it, so tc_gen_reloc will reject it. */
19764 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19767 _("undefined symbol %s used as an immediate value"),
19768 S_GET_NAME (fixP
->fx_addsy
));
19773 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19776 _("symbol %s is in a different section"),
19777 S_GET_NAME (fixP
->fx_addsy
));
19781 newimm
= encode_arm_immediate (value
);
19782 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19784 /* If the instruction will fail, see if we can fix things up by
19785 changing the opcode. */
19786 if (newimm
== (unsigned int) FAIL
19787 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19790 _("invalid constant (%lx) after fixup"),
19791 (unsigned long) value
);
19795 newimm
|= (temp
& 0xfffff000);
19796 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19799 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19801 unsigned int highpart
= 0;
19802 unsigned int newinsn
= 0xe1a00000; /* nop. */
19805 && ! S_IS_DEFINED (fixP
->fx_addsy
))
19807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19808 _("undefined symbol %s used as an immediate value"),
19809 S_GET_NAME (fixP
->fx_addsy
));
19814 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19817 _("symbol %s is in a different section"),
19818 S_GET_NAME (fixP
->fx_addsy
));
19822 newimm
= encode_arm_immediate (value
);
19823 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19825 /* If the instruction will fail, see if we can fix things up by
19826 changing the opcode. */
19827 if (newimm
== (unsigned int) FAIL
19828 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19830 /* No ? OK - try using two ADD instructions to generate
19832 newimm
= validate_immediate_twopart (value
, & highpart
);
19834 /* Yes - then make sure that the second instruction is
19836 if (newimm
!= (unsigned int) FAIL
)
19838 /* Still No ? Try using a negated value. */
19839 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19840 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19841 /* Otherwise - give up. */
19844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19845 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19850 /* Replace the first operand in the 2nd instruction (which
19851 is the PC) with the destination register. We have
19852 already added in the PC in the first instruction and we
19853 do not want to do it again. */
19854 newinsn
&= ~ 0xf0000;
19855 newinsn
|= ((newinsn
& 0x0f000) << 4);
19858 newimm
|= (temp
& 0xfffff000);
19859 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19861 highpart
|= (newinsn
& 0xfffff000);
19862 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19866 case BFD_RELOC_ARM_OFFSET_IMM
:
19867 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19870 case BFD_RELOC_ARM_LITERAL
:
19876 if (validate_offset_imm (value
, 0) == FAIL
)
19878 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
19879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19880 _("invalid literal constant: pool needs to be closer"));
19882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19883 _("bad immediate value for offset (%ld)"),
19888 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19889 newval
&= 0xff7ff000;
19890 newval
|= value
| (sign
? INDEX_UP
: 0);
19891 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19894 case BFD_RELOC_ARM_OFFSET_IMM8
:
19895 case BFD_RELOC_ARM_HWLITERAL
:
19901 if (validate_offset_imm (value
, 1) == FAIL
)
19903 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
19904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19905 _("invalid literal constant: pool needs to be closer"));
19907 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
19912 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19913 newval
&= 0xff7ff0f0;
19914 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
19915 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19918 case BFD_RELOC_ARM_T32_OFFSET_U8
:
19919 if (value
< 0 || value
> 1020 || value
% 4 != 0)
19920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19921 _("bad immediate value for offset (%ld)"), (long) value
);
19924 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
19926 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
19929 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19930 /* This is a complicated relocation used for all varieties of Thumb32
19931 load/store instruction with immediate offset:
19933 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
19934 *4, optional writeback(W)
19935 (doubleword load/store)
19937 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
19938 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
19939 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
19940 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
19941 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
19943 Uppercase letters indicate bits that are already encoded at
19944 this point. Lowercase letters are our problem. For the
19945 second block of instructions, the secondary opcode nybble
19946 (bits 8..11) is present, and bit 23 is zero, even if this is
19947 a PC-relative operation. */
19948 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19950 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
19952 if ((newval
& 0xf0000000) == 0xe0000000)
19954 /* Doubleword load/store: 8-bit offset, scaled by 4. */
19956 newval
|= (1 << 23);
19959 if (value
% 4 != 0)
19961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19962 _("offset not a multiple of 4"));
19968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19969 _("offset out of range"));
19974 else if ((newval
& 0x000f0000) == 0x000f0000)
19976 /* PC-relative, 12-bit offset. */
19978 newval
|= (1 << 23);
19983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19984 _("offset out of range"));
19989 else if ((newval
& 0x00000100) == 0x00000100)
19991 /* Writeback: 8-bit, +/- offset. */
19993 newval
|= (1 << 9);
19998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19999 _("offset out of range"));
20004 else if ((newval
& 0x00000f00) == 0x00000e00)
20006 /* T-instruction: positive 8-bit offset. */
20007 if (value
< 0 || value
> 0xff)
20009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20010 _("offset out of range"));
20018 /* Positive 12-bit or negative 8-bit offset. */
20022 newval
|= (1 << 23);
20032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20033 _("offset out of range"));
20040 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20041 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20044 case BFD_RELOC_ARM_SHIFT_IMM
:
20045 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20046 if (((unsigned long) value
) > 32
20048 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20050 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20051 _("shift expression is too large"));
20056 /* Shifts of zero must be done as lsl. */
20058 else if (value
== 32)
20060 newval
&= 0xfffff07f;
20061 newval
|= (value
& 0x1f) << 7;
20062 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20065 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20066 case BFD_RELOC_ARM_T32_ADD_IMM
:
20067 case BFD_RELOC_ARM_T32_IMM12
:
20068 case BFD_RELOC_ARM_T32_ADD_PC12
:
20069 /* We claim that this fixup has been processed here,
20070 even if in fact we generate an error because we do
20071 not have a reloc for it, so tc_gen_reloc will reject it. */
20075 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20077 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20078 _("undefined symbol %s used as an immediate value"),
20079 S_GET_NAME (fixP
->fx_addsy
));
20083 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20085 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20088 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20089 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20091 newimm
= encode_thumb32_immediate (value
);
20092 if (newimm
== (unsigned int) FAIL
)
20093 newimm
= thumb32_negate_data_op (&newval
, value
);
20095 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20096 && newimm
== (unsigned int) FAIL
)
20098 /* Turn add/sum into addw/subw. */
20099 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20100 newval
= (newval
& 0xfeffffff) | 0x02000000;
20102 /* 12 bit immediate for addw/subw. */
20106 newval
^= 0x00a00000;
20109 newimm
= (unsigned int) FAIL
;
20114 if (newimm
== (unsigned int)FAIL
)
20116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20117 _("invalid constant (%lx) after fixup"),
20118 (unsigned long) value
);
20122 newval
|= (newimm
& 0x800) << 15;
20123 newval
|= (newimm
& 0x700) << 4;
20124 newval
|= (newimm
& 0x0ff);
20126 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20127 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20130 case BFD_RELOC_ARM_SMC
:
20131 if (((unsigned long) value
) > 0xffff)
20132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20133 _("invalid smc expression"));
20134 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20135 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20136 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20139 case BFD_RELOC_ARM_SWI
:
20140 if (fixP
->tc_fix_data
!= 0)
20142 if (((unsigned long) value
) > 0xff)
20143 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20144 _("invalid swi expression"));
20145 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20147 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20151 if (((unsigned long) value
) > 0x00ffffff)
20152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20153 _("invalid swi expression"));
20154 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20156 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20160 case BFD_RELOC_ARM_MULTI
:
20161 if (((unsigned long) value
) > 0xffff)
20162 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20163 _("invalid expression in load/store multiple"));
20164 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20165 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20169 case BFD_RELOC_ARM_PCREL_CALL
:
20171 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20173 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20174 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20175 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20176 /* Flip the bl to blx. This is a simple flip
20177 bit here because we generate PCREL_CALL for
20178 unconditional bls. */
20180 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20181 newval
= newval
| 0x10000000;
20182 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20188 goto arm_branch_common
;
20190 case BFD_RELOC_ARM_PCREL_JUMP
:
20191 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20193 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20194 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20195 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20197 /* This would map to a bl<cond>, b<cond>,
20198 b<always> to a Thumb function. We
20199 need to force a relocation for this particular
20201 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20205 case BFD_RELOC_ARM_PLT32
:
20207 case BFD_RELOC_ARM_PCREL_BRANCH
:
20209 goto arm_branch_common
;
20211 case BFD_RELOC_ARM_PCREL_BLX
:
20214 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20216 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20217 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20218 && ARM_IS_FUNC (fixP
->fx_addsy
))
20220 /* Flip the blx to a bl and warn. */
20221 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20222 newval
= 0xeb000000;
20223 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20224 _("blx to '%s' an ARM ISA state function changed to bl"),
20226 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20232 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20233 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20237 /* We are going to store value (shifted right by two) in the
20238 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20239 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20240 also be be clear. */
20242 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20243 _("misaligned branch destination"));
20244 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20245 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20247 _("branch out of range"));
20249 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20251 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20252 newval
|= (value
>> 2) & 0x00ffffff;
20253 /* Set the H bit on BLX instructions. */
20257 newval
|= 0x01000000;
20259 newval
&= ~0x01000000;
20261 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20265 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20266 /* CBZ can only branch forward. */
20268 /* Attempts to use CBZ to branch to the next instruction
20269 (which, strictly speaking, are prohibited) will be turned into
20272 FIXME: It may be better to remove the instruction completely and
20273 perform relaxation. */
20276 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20277 newval
= 0xbf00; /* NOP encoding T1 */
20278 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20284 _("branch out of range"));
20286 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20288 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20289 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20290 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20295 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20296 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20298 _("branch out of range"));
20300 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20302 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20303 newval
|= (value
& 0x1ff) >> 1;
20304 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20308 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20309 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20310 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20311 _("branch out of range"));
20313 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20315 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20316 newval
|= (value
& 0xfff) >> 1;
20317 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20321 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20323 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20324 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20325 && S_IS_DEFINED (fixP
->fx_addsy
)
20326 && ARM_IS_FUNC (fixP
->fx_addsy
)
20327 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20329 /* Force a relocation for a branch 20 bits wide. */
20332 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20333 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20334 _("conditional branch out of range"));
20336 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20339 addressT S
, J1
, J2
, lo
, hi
;
20341 S
= (value
& 0x00100000) >> 20;
20342 J2
= (value
& 0x00080000) >> 19;
20343 J1
= (value
& 0x00040000) >> 18;
20344 hi
= (value
& 0x0003f000) >> 12;
20345 lo
= (value
& 0x00000ffe) >> 1;
20347 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20348 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20349 newval
|= (S
<< 10) | hi
;
20350 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20351 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20352 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20356 case BFD_RELOC_THUMB_PCREL_BLX
:
20358 /* If there is a blx from a thumb state function to
20359 another thumb function flip this to a bl and warn
20363 && S_IS_DEFINED (fixP
->fx_addsy
)
20364 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20365 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20366 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20368 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20369 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20370 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20372 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20373 newval
= newval
| 0x1000;
20374 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20375 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20380 goto thumb_bl_common
;
20382 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20384 /* A bl from Thumb state ISA to an internal ARM state function
20385 is converted to a blx. */
20387 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20388 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20389 && S_IS_DEFINED (fixP
->fx_addsy
)
20390 && ARM_IS_FUNC (fixP
->fx_addsy
)
20391 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20393 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20394 newval
= newval
& ~0x1000;
20395 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20396 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20403 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20404 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20405 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20408 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20409 /* For a BLX instruction, make sure that the relocation is rounded up
20410 to a word boundary. This follows the semantics of the instruction
20411 which specifies that bit 1 of the target address will come from bit
20412 1 of the base address. */
20413 value
= (value
+ 1) & ~ 1;
20416 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20418 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20421 _("branch out of range"));
20423 else if ((value
& ~0x1ffffff)
20424 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20426 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20427 _("Thumb2 branch out of range"));
20431 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20432 encode_thumb2_b_bl_offset (buf
, value
);
20436 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20437 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20438 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20439 _("branch out of range"));
20441 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20442 encode_thumb2_b_bl_offset (buf
, value
);
20447 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20448 md_number_to_chars (buf
, value
, 1);
20452 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20453 md_number_to_chars (buf
, value
, 2);
20457 case BFD_RELOC_ARM_TLS_GD32
:
20458 case BFD_RELOC_ARM_TLS_LE32
:
20459 case BFD_RELOC_ARM_TLS_IE32
:
20460 case BFD_RELOC_ARM_TLS_LDM32
:
20461 case BFD_RELOC_ARM_TLS_LDO32
:
20462 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20465 case BFD_RELOC_ARM_GOT32
:
20466 case BFD_RELOC_ARM_GOTOFF
:
20467 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20468 md_number_to_chars (buf
, 0, 4);
20471 case BFD_RELOC_ARM_TARGET2
:
20472 /* TARGET2 is not partial-inplace, so we need to write the
20473 addend here for REL targets, because it won't be written out
20474 during reloc processing later. */
20475 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20476 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20480 case BFD_RELOC_RVA
:
20482 case BFD_RELOC_ARM_TARGET1
:
20483 case BFD_RELOC_ARM_ROSEGREL32
:
20484 case BFD_RELOC_ARM_SBREL32
:
20485 case BFD_RELOC_32_PCREL
:
20487 case BFD_RELOC_32_SECREL
:
20489 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20491 /* For WinCE we only do this for pcrel fixups. */
20492 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20494 md_number_to_chars (buf
, value
, 4);
20498 case BFD_RELOC_ARM_PREL31
:
20499 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20501 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20502 if ((value
^ (value
>> 1)) & 0x40000000)
20504 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20505 _("rel31 relocation overflow"));
20507 newval
|= value
& 0x7fffffff;
20508 md_number_to_chars (buf
, newval
, 4);
20513 case BFD_RELOC_ARM_CP_OFF_IMM
:
20514 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20515 if (value
< -1023 || value
> 1023 || (value
& 3))
20516 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20517 _("co-processor offset out of range"));
20522 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20523 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20524 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20526 newval
= get_thumb32_insn (buf
);
20527 newval
&= 0xff7fff00;
20528 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20529 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20530 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20531 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20533 put_thumb32_insn (buf
, newval
);
20536 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20537 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20538 if (value
< -255 || value
> 255)
20539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20540 _("co-processor offset out of range"));
20542 goto cp_off_common
;
20544 case BFD_RELOC_ARM_THUMB_OFFSET
:
20545 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20546 /* Exactly what ranges, and where the offset is inserted depends
20547 on the type of instruction, we can establish this from the
20549 switch (newval
>> 12)
20551 case 4: /* PC load. */
20552 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20553 forced to zero for these loads; md_pcrel_from has already
20554 compensated for this. */
20556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20557 _("invalid offset, target not word aligned (0x%08lX)"),
20558 (((unsigned long) fixP
->fx_frag
->fr_address
20559 + (unsigned long) fixP
->fx_where
) & ~3)
20560 + (unsigned long) value
);
20562 if (value
& ~0x3fc)
20563 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20564 _("invalid offset, value too big (0x%08lX)"),
20567 newval
|= value
>> 2;
20570 case 9: /* SP load/store. */
20571 if (value
& ~0x3fc)
20572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20573 _("invalid offset, value too big (0x%08lX)"),
20575 newval
|= value
>> 2;
20578 case 6: /* Word load/store. */
20580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20581 _("invalid offset, value too big (0x%08lX)"),
20583 newval
|= value
<< 4; /* 6 - 2. */
20586 case 7: /* Byte load/store. */
20588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20589 _("invalid offset, value too big (0x%08lX)"),
20591 newval
|= value
<< 6;
20594 case 8: /* Halfword load/store. */
20596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20597 _("invalid offset, value too big (0x%08lX)"),
20599 newval
|= value
<< 5; /* 6 - 1. */
20603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20604 "Unable to process relocation for thumb opcode: %lx",
20605 (unsigned long) newval
);
20608 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20611 case BFD_RELOC_ARM_THUMB_ADD
:
20612 /* This is a complicated relocation, since we use it for all of
20613 the following immediate relocations:
20617 9bit ADD/SUB SP word-aligned
20618 10bit ADD PC/SP word-aligned
20620 The type of instruction being processed is encoded in the
20627 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20629 int rd
= (newval
>> 4) & 0xf;
20630 int rs
= newval
& 0xf;
20631 int subtract
= !!(newval
& 0x8000);
20633 /* Check for HI regs, only very restricted cases allowed:
20634 Adjusting SP, and using PC or SP to get an address. */
20635 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20636 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20638 _("invalid Hi register with immediate"));
20640 /* If value is negative, choose the opposite instruction. */
20644 subtract
= !subtract
;
20646 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20647 _("immediate value out of range"));
20652 if (value
& ~0x1fc)
20653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20654 _("invalid immediate for stack address calculation"));
20655 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20656 newval
|= value
>> 2;
20658 else if (rs
== REG_PC
|| rs
== REG_SP
)
20660 if (subtract
|| value
& ~0x3fc)
20661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20662 _("invalid immediate for address calculation (value = 0x%08lX)"),
20663 (unsigned long) value
);
20664 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20666 newval
|= value
>> 2;
20671 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20672 _("immediate value out of range"));
20673 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20674 newval
|= (rd
<< 8) | value
;
20679 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20680 _("immediate value out of range"));
20681 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20682 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20685 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20688 case BFD_RELOC_ARM_THUMB_IMM
:
20689 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20690 if (value
< 0 || value
> 255)
20691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20692 _("invalid immediate: %ld is out of range"),
20695 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20698 case BFD_RELOC_ARM_THUMB_SHIFT
:
20699 /* 5bit shift value (0..32). LSL cannot take 32. */
20700 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20701 temp
= newval
& 0xf800;
20702 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20704 _("invalid shift value: %ld"), (long) value
);
20705 /* Shifts of zero must be encoded as LSL. */
20707 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20708 /* Shifts of 32 are encoded as zero. */
20709 else if (value
== 32)
20711 newval
|= value
<< 6;
20712 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20715 case BFD_RELOC_VTABLE_INHERIT
:
20716 case BFD_RELOC_VTABLE_ENTRY
:
20720 case BFD_RELOC_ARM_MOVW
:
20721 case BFD_RELOC_ARM_MOVT
:
20722 case BFD_RELOC_ARM_THUMB_MOVW
:
20723 case BFD_RELOC_ARM_THUMB_MOVT
:
20724 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20726 /* REL format relocations are limited to a 16-bit addend. */
20727 if (!fixP
->fx_done
)
20729 if (value
< -0x8000 || value
> 0x7fff)
20730 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20731 _("offset out of range"));
20733 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20734 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20739 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20740 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20742 newval
= get_thumb32_insn (buf
);
20743 newval
&= 0xfbf08f00;
20744 newval
|= (value
& 0xf000) << 4;
20745 newval
|= (value
& 0x0800) << 15;
20746 newval
|= (value
& 0x0700) << 4;
20747 newval
|= (value
& 0x00ff);
20748 put_thumb32_insn (buf
, newval
);
20752 newval
= md_chars_to_number (buf
, 4);
20753 newval
&= 0xfff0f000;
20754 newval
|= value
& 0x0fff;
20755 newval
|= (value
& 0xf000) << 4;
20756 md_number_to_chars (buf
, newval
, 4);
20761 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20762 case BFD_RELOC_ARM_ALU_PC_G0
:
20763 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20764 case BFD_RELOC_ARM_ALU_PC_G1
:
20765 case BFD_RELOC_ARM_ALU_PC_G2
:
20766 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20767 case BFD_RELOC_ARM_ALU_SB_G0
:
20768 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20769 case BFD_RELOC_ARM_ALU_SB_G1
:
20770 case BFD_RELOC_ARM_ALU_SB_G2
:
20771 gas_assert (!fixP
->fx_done
);
20772 if (!seg
->use_rela_p
)
20775 bfd_vma encoded_addend
;
20776 bfd_vma addend_abs
= abs (value
);
20778 /* Check that the absolute value of the addend can be
20779 expressed as an 8-bit constant plus a rotation. */
20780 encoded_addend
= encode_arm_immediate (addend_abs
);
20781 if (encoded_addend
== (unsigned int) FAIL
)
20782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20783 _("the offset 0x%08lX is not representable"),
20784 (unsigned long) addend_abs
);
20786 /* Extract the instruction. */
20787 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20789 /* If the addend is positive, use an ADD instruction.
20790 Otherwise use a SUB. Take care not to destroy the S bit. */
20791 insn
&= 0xff1fffff;
20797 /* Place the encoded addend into the first 12 bits of the
20799 insn
&= 0xfffff000;
20800 insn
|= encoded_addend
;
20802 /* Update the instruction. */
20803 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20807 case BFD_RELOC_ARM_LDR_PC_G0
:
20808 case BFD_RELOC_ARM_LDR_PC_G1
:
20809 case BFD_RELOC_ARM_LDR_PC_G2
:
20810 case BFD_RELOC_ARM_LDR_SB_G0
:
20811 case BFD_RELOC_ARM_LDR_SB_G1
:
20812 case BFD_RELOC_ARM_LDR_SB_G2
:
20813 gas_assert (!fixP
->fx_done
);
20814 if (!seg
->use_rela_p
)
20817 bfd_vma addend_abs
= abs (value
);
20819 /* Check that the absolute value of the addend can be
20820 encoded in 12 bits. */
20821 if (addend_abs
>= 0x1000)
20822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20823 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20824 (unsigned long) addend_abs
);
20826 /* Extract the instruction. */
20827 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20829 /* If the addend is negative, clear bit 23 of the instruction.
20830 Otherwise set it. */
20832 insn
&= ~(1 << 23);
20836 /* Place the absolute value of the addend into the first 12 bits
20837 of the instruction. */
20838 insn
&= 0xfffff000;
20839 insn
|= addend_abs
;
20841 /* Update the instruction. */
20842 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20846 case BFD_RELOC_ARM_LDRS_PC_G0
:
20847 case BFD_RELOC_ARM_LDRS_PC_G1
:
20848 case BFD_RELOC_ARM_LDRS_PC_G2
:
20849 case BFD_RELOC_ARM_LDRS_SB_G0
:
20850 case BFD_RELOC_ARM_LDRS_SB_G1
:
20851 case BFD_RELOC_ARM_LDRS_SB_G2
:
20852 gas_assert (!fixP
->fx_done
);
20853 if (!seg
->use_rela_p
)
20856 bfd_vma addend_abs
= abs (value
);
20858 /* Check that the absolute value of the addend can be
20859 encoded in 8 bits. */
20860 if (addend_abs
>= 0x100)
20861 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20862 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20863 (unsigned long) addend_abs
);
20865 /* Extract the instruction. */
20866 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20868 /* If the addend is negative, clear bit 23 of the instruction.
20869 Otherwise set it. */
20871 insn
&= ~(1 << 23);
20875 /* Place the first four bits of the absolute value of the addend
20876 into the first 4 bits of the instruction, and the remaining
20877 four into bits 8 .. 11. */
20878 insn
&= 0xfffff0f0;
20879 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
20881 /* Update the instruction. */
20882 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20886 case BFD_RELOC_ARM_LDC_PC_G0
:
20887 case BFD_RELOC_ARM_LDC_PC_G1
:
20888 case BFD_RELOC_ARM_LDC_PC_G2
:
20889 case BFD_RELOC_ARM_LDC_SB_G0
:
20890 case BFD_RELOC_ARM_LDC_SB_G1
:
20891 case BFD_RELOC_ARM_LDC_SB_G2
:
20892 gas_assert (!fixP
->fx_done
);
20893 if (!seg
->use_rela_p
)
20896 bfd_vma addend_abs
= abs (value
);
20898 /* Check that the absolute value of the addend is a multiple of
20899 four and, when divided by four, fits in 8 bits. */
20900 if (addend_abs
& 0x3)
20901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20902 _("bad offset 0x%08lX (must be word-aligned)"),
20903 (unsigned long) addend_abs
);
20905 if ((addend_abs
>> 2) > 0xff)
20906 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20907 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
20908 (unsigned long) addend_abs
);
20910 /* Extract the instruction. */
20911 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20913 /* If the addend is negative, clear bit 23 of the instruction.
20914 Otherwise set it. */
20916 insn
&= ~(1 << 23);
20920 /* Place the addend (divided by four) into the first eight
20921 bits of the instruction. */
20922 insn
&= 0xfffffff0;
20923 insn
|= addend_abs
>> 2;
20925 /* Update the instruction. */
20926 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20930 case BFD_RELOC_ARM_V4BX
:
20931 /* This will need to go in the object file. */
20935 case BFD_RELOC_UNUSED
:
20937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20938 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
20942 /* Translate internal representation of relocation info to BFD target
20946 tc_gen_reloc (asection
*section
, fixS
*fixp
)
20949 bfd_reloc_code_real_type code
;
20951 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
20953 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
20954 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
20955 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
20957 if (fixp
->fx_pcrel
)
20959 if (section
->use_rela_p
)
20960 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
20962 fixp
->fx_offset
= reloc
->address
;
20964 reloc
->addend
= fixp
->fx_offset
;
20966 switch (fixp
->fx_r_type
)
20969 if (fixp
->fx_pcrel
)
20971 code
= BFD_RELOC_8_PCREL
;
20976 if (fixp
->fx_pcrel
)
20978 code
= BFD_RELOC_16_PCREL
;
20983 if (fixp
->fx_pcrel
)
20985 code
= BFD_RELOC_32_PCREL
;
20989 case BFD_RELOC_ARM_MOVW
:
20990 if (fixp
->fx_pcrel
)
20992 code
= BFD_RELOC_ARM_MOVW_PCREL
;
20996 case BFD_RELOC_ARM_MOVT
:
20997 if (fixp
->fx_pcrel
)
20999 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21003 case BFD_RELOC_ARM_THUMB_MOVW
:
21004 if (fixp
->fx_pcrel
)
21006 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21010 case BFD_RELOC_ARM_THUMB_MOVT
:
21011 if (fixp
->fx_pcrel
)
21013 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21017 case BFD_RELOC_NONE
:
21018 case BFD_RELOC_ARM_PCREL_BRANCH
:
21019 case BFD_RELOC_ARM_PCREL_BLX
:
21020 case BFD_RELOC_RVA
:
21021 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21022 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21023 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21024 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21025 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21026 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21027 case BFD_RELOC_VTABLE_ENTRY
:
21028 case BFD_RELOC_VTABLE_INHERIT
:
21030 case BFD_RELOC_32_SECREL
:
21032 code
= fixp
->fx_r_type
;
21035 case BFD_RELOC_THUMB_PCREL_BLX
:
21037 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21038 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21041 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21044 case BFD_RELOC_ARM_LITERAL
:
21045 case BFD_RELOC_ARM_HWLITERAL
:
21046 /* If this is called then the a literal has
21047 been referenced across a section boundary. */
21048 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21049 _("literal referenced across section boundary"));
21053 case BFD_RELOC_ARM_GOT32
:
21054 case BFD_RELOC_ARM_GOTOFF
:
21055 case BFD_RELOC_ARM_PLT32
:
21056 case BFD_RELOC_ARM_TARGET1
:
21057 case BFD_RELOC_ARM_ROSEGREL32
:
21058 case BFD_RELOC_ARM_SBREL32
:
21059 case BFD_RELOC_ARM_PREL31
:
21060 case BFD_RELOC_ARM_TARGET2
:
21061 case BFD_RELOC_ARM_TLS_LE32
:
21062 case BFD_RELOC_ARM_TLS_LDO32
:
21063 case BFD_RELOC_ARM_PCREL_CALL
:
21064 case BFD_RELOC_ARM_PCREL_JUMP
:
21065 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21066 case BFD_RELOC_ARM_ALU_PC_G0
:
21067 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21068 case BFD_RELOC_ARM_ALU_PC_G1
:
21069 case BFD_RELOC_ARM_ALU_PC_G2
:
21070 case BFD_RELOC_ARM_LDR_PC_G0
:
21071 case BFD_RELOC_ARM_LDR_PC_G1
:
21072 case BFD_RELOC_ARM_LDR_PC_G2
:
21073 case BFD_RELOC_ARM_LDRS_PC_G0
:
21074 case BFD_RELOC_ARM_LDRS_PC_G1
:
21075 case BFD_RELOC_ARM_LDRS_PC_G2
:
21076 case BFD_RELOC_ARM_LDC_PC_G0
:
21077 case BFD_RELOC_ARM_LDC_PC_G1
:
21078 case BFD_RELOC_ARM_LDC_PC_G2
:
21079 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21080 case BFD_RELOC_ARM_ALU_SB_G0
:
21081 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21082 case BFD_RELOC_ARM_ALU_SB_G1
:
21083 case BFD_RELOC_ARM_ALU_SB_G2
:
21084 case BFD_RELOC_ARM_LDR_SB_G0
:
21085 case BFD_RELOC_ARM_LDR_SB_G1
:
21086 case BFD_RELOC_ARM_LDR_SB_G2
:
21087 case BFD_RELOC_ARM_LDRS_SB_G0
:
21088 case BFD_RELOC_ARM_LDRS_SB_G1
:
21089 case BFD_RELOC_ARM_LDRS_SB_G2
:
21090 case BFD_RELOC_ARM_LDC_SB_G0
:
21091 case BFD_RELOC_ARM_LDC_SB_G1
:
21092 case BFD_RELOC_ARM_LDC_SB_G2
:
21093 case BFD_RELOC_ARM_V4BX
:
21094 code
= fixp
->fx_r_type
;
21097 case BFD_RELOC_ARM_TLS_GD32
:
21098 case BFD_RELOC_ARM_TLS_IE32
:
21099 case BFD_RELOC_ARM_TLS_LDM32
:
21100 /* BFD will include the symbol's address in the addend.
21101 But we don't want that, so subtract it out again here. */
21102 if (!S_IS_COMMON (fixp
->fx_addsy
))
21103 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21104 code
= fixp
->fx_r_type
;
21108 case BFD_RELOC_ARM_IMMEDIATE
:
21109 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21110 _("internal relocation (type: IMMEDIATE) not fixed up"));
21113 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21114 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21115 _("ADRL used for a symbol not defined in the same file"));
21118 case BFD_RELOC_ARM_OFFSET_IMM
:
21119 if (section
->use_rela_p
)
21121 code
= fixp
->fx_r_type
;
21125 if (fixp
->fx_addsy
!= NULL
21126 && !S_IS_DEFINED (fixp
->fx_addsy
)
21127 && S_IS_LOCAL (fixp
->fx_addsy
))
21129 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21130 _("undefined local label `%s'"),
21131 S_GET_NAME (fixp
->fx_addsy
));
21135 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21136 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21143 switch (fixp
->fx_r_type
)
21145 case BFD_RELOC_NONE
: type
= "NONE"; break;
21146 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21147 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21148 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21149 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21150 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21151 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21152 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21153 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21154 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21155 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21156 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21157 default: type
= _("<unknown>"); break;
21159 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21160 _("cannot represent %s relocation in this object file format"),
21167 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21169 && fixp
->fx_addsy
== GOT_symbol
)
21171 code
= BFD_RELOC_ARM_GOTPC
;
21172 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21176 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21178 if (reloc
->howto
== NULL
)
21180 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21181 _("cannot represent %s relocation in this object file format"),
21182 bfd_get_reloc_code_name (code
));
21186 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21187 vtable entry to be used in the relocation's section offset. */
21188 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21189 reloc
->address
= fixp
->fx_offset
;
21194 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21197 cons_fix_new_arm (fragS
* frag
,
21202 bfd_reloc_code_real_type type
;
21206 FIXME: @@ Should look at CPU word size. */
21210 type
= BFD_RELOC_8
;
21213 type
= BFD_RELOC_16
;
21217 type
= BFD_RELOC_32
;
21220 type
= BFD_RELOC_64
;
21225 if (exp
->X_op
== O_secrel
)
21227 exp
->X_op
= O_symbol
;
21228 type
= BFD_RELOC_32_SECREL
;
21232 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21235 #if defined (OBJ_COFF)
21237 arm_validate_fix (fixS
* fixP
)
21239 /* If the destination of the branch is a defined symbol which does not have
21240 the THUMB_FUNC attribute, then we must be calling a function which has
21241 the (interfacearm) attribute. We look for the Thumb entry point to that
21242 function and change the branch to refer to that function instead. */
21243 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21244 && fixP
->fx_addsy
!= NULL
21245 && S_IS_DEFINED (fixP
->fx_addsy
)
21246 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21248 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21255 arm_force_relocation (struct fix
* fixp
)
21257 #if defined (OBJ_COFF) && defined (TE_PE)
21258 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21262 /* In case we have a call or a branch to a function in ARM ISA mode from
21263 a thumb function or vice-versa force the relocation. These relocations
21264 are cleared off for some cores that might have blx and simple transformations
21268 switch (fixp
->fx_r_type
)
21270 case BFD_RELOC_ARM_PCREL_JUMP
:
21271 case BFD_RELOC_ARM_PCREL_CALL
:
21272 case BFD_RELOC_THUMB_PCREL_BLX
:
21273 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21277 case BFD_RELOC_ARM_PCREL_BLX
:
21278 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21279 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21280 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21281 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21290 /* Resolve these relocations even if the symbol is extern or weak. */
21291 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21292 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21293 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21294 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21295 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21296 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21297 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21300 /* Always leave these relocations for the linker. */
21301 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21302 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21303 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21306 /* Always generate relocations against function symbols. */
21307 if (fixp
->fx_r_type
== BFD_RELOC_32
21309 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21312 return generic_force_reloc (fixp
);
21315 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21316 /* Relocations against function names must be left unadjusted,
21317 so that the linker can use this information to generate interworking
21318 stubs. The MIPS version of this function
21319 also prevents relocations that are mips-16 specific, but I do not
21320 know why it does this.
21323 There is one other problem that ought to be addressed here, but
21324 which currently is not: Taking the address of a label (rather
21325 than a function) and then later jumping to that address. Such
21326 addresses also ought to have their bottom bit set (assuming that
21327 they reside in Thumb code), but at the moment they will not. */
21330 arm_fix_adjustable (fixS
* fixP
)
21332 if (fixP
->fx_addsy
== NULL
)
21335 /* Preserve relocations against symbols with function type. */
21336 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21339 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21340 && fixP
->fx_subsy
== NULL
)
21343 /* We need the symbol name for the VTABLE entries. */
21344 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21345 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21348 /* Don't allow symbols to be discarded on GOT related relocs. */
21349 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21350 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21351 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21352 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21353 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21354 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21355 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21356 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21357 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21360 /* Similarly for group relocations. */
21361 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21362 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21363 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21366 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21367 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21368 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21369 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21370 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21371 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21372 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21373 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21374 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21379 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21384 elf32_arm_target_format (void)
21387 return (target_big_endian
21388 ? "elf32-bigarm-symbian"
21389 : "elf32-littlearm-symbian");
21390 #elif defined (TE_VXWORKS)
21391 return (target_big_endian
21392 ? "elf32-bigarm-vxworks"
21393 : "elf32-littlearm-vxworks");
21395 if (target_big_endian
)
21396 return "elf32-bigarm";
21398 return "elf32-littlearm";
21403 armelf_frob_symbol (symbolS
* symp
,
21406 elf_frob_symbol (symp
, puntp
);
21410 /* MD interface: Finalization. */
21415 literal_pool
* pool
;
21417 /* Ensure that all the IT blocks are properly closed. */
21418 check_it_blocks_finished ();
21420 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21422 /* Put it at the end of the relevant section. */
21423 subseg_set (pool
->section
, pool
->sub_section
);
21425 arm_elf_change_section ();
21432 /* Remove any excess mapping symbols generated for alignment frags in
21433 SEC. We may have created a mapping symbol before a zero byte
21434 alignment; remove it if there's a mapping symbol after the
21437 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21438 void *dummy ATTRIBUTE_UNUSED
)
21440 segment_info_type
*seginfo
= seg_info (sec
);
21443 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21446 for (fragp
= seginfo
->frchainP
->frch_root
;
21448 fragp
= fragp
->fr_next
)
21450 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21451 fragS
*next
= fragp
->fr_next
;
21453 /* Variable-sized frags have been converted to fixed size by
21454 this point. But if this was variable-sized to start with,
21455 there will be a fixed-size frag after it. So don't handle
21457 if (sym
== NULL
|| next
== NULL
)
21460 if (S_GET_VALUE (sym
) < next
->fr_address
)
21461 /* Not at the end of this frag. */
21463 know (S_GET_VALUE (sym
) == next
->fr_address
);
21467 if (next
->tc_frag_data
.first_map
!= NULL
)
21469 /* Next frag starts with a mapping symbol. Discard this
21471 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21475 if (next
->fr_next
== NULL
)
21477 /* This mapping symbol is at the end of the section. Discard
21479 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21480 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21484 /* As long as we have empty frags without any mapping symbols,
21486 /* If the next frag is non-empty and does not start with a
21487 mapping symbol, then this mapping symbol is required. */
21488 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21491 next
= next
->fr_next
;
21493 while (next
!= NULL
);
21498 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21502 arm_adjust_symtab (void)
21507 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21509 if (ARM_IS_THUMB (sym
))
21511 if (THUMB_IS_FUNC (sym
))
21513 /* Mark the symbol as a Thumb function. */
21514 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21515 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21516 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21518 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21519 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21521 as_bad (_("%s: unexpected function type: %d"),
21522 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21524 else switch (S_GET_STORAGE_CLASS (sym
))
21527 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21530 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21533 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21541 if (ARM_IS_INTERWORK (sym
))
21542 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21549 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21551 if (ARM_IS_THUMB (sym
))
21553 elf_symbol_type
* elf_sym
;
21555 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21556 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21558 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21559 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21561 /* If it's a .thumb_func, declare it as so,
21562 otherwise tag label as .code 16. */
21563 if (THUMB_IS_FUNC (sym
))
21564 elf_sym
->internal_elf_sym
.st_info
=
21565 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21566 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21567 elf_sym
->internal_elf_sym
.st_info
=
21568 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21573 /* Remove any overlapping mapping symbols generated by alignment frags. */
21574 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21578 /* MD interface: Initialization. */
21581 set_constant_flonums (void)
21585 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21586 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21590 /* Auto-select Thumb mode if it's the only available instruction set for the
21591 given architecture. */
21594 autoselect_thumb_from_cpu_variant (void)
21596 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21597 opcode_select (16);
21606 if ( (arm_ops_hsh
= hash_new ()) == NULL
21607 || (arm_cond_hsh
= hash_new ()) == NULL
21608 || (arm_shift_hsh
= hash_new ()) == NULL
21609 || (arm_psr_hsh
= hash_new ()) == NULL
21610 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21611 || (arm_reg_hsh
= hash_new ()) == NULL
21612 || (arm_reloc_hsh
= hash_new ()) == NULL
21613 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21614 as_fatal (_("virtual memory exhausted"));
21616 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21617 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21618 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21619 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21620 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21621 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21622 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21623 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21624 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21625 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21626 (void *) (v7m_psrs
+ i
));
21627 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21628 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21630 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21632 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21633 (void *) (barrier_opt_names
+ i
));
21635 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21636 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21639 set_constant_flonums ();
21641 /* Set the cpu variant based on the command-line options. We prefer
21642 -mcpu= over -march= if both are set (as for GCC); and we prefer
21643 -mfpu= over any other way of setting the floating point unit.
21644 Use of legacy options with new options are faulted. */
21647 if (mcpu_cpu_opt
|| march_cpu_opt
)
21648 as_bad (_("use of old and new-style options to set CPU type"));
21650 mcpu_cpu_opt
= legacy_cpu
;
21652 else if (!mcpu_cpu_opt
)
21653 mcpu_cpu_opt
= march_cpu_opt
;
21658 as_bad (_("use of old and new-style options to set FPU type"));
21660 mfpu_opt
= legacy_fpu
;
21662 else if (!mfpu_opt
)
21664 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21665 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21666 /* Some environments specify a default FPU. If they don't, infer it
21667 from the processor. */
21669 mfpu_opt
= mcpu_fpu_opt
;
21671 mfpu_opt
= march_fpu_opt
;
21673 mfpu_opt
= &fpu_default
;
21679 if (mcpu_cpu_opt
!= NULL
)
21680 mfpu_opt
= &fpu_default
;
21681 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21682 mfpu_opt
= &fpu_arch_vfp_v2
;
21684 mfpu_opt
= &fpu_arch_fpa
;
21690 mcpu_cpu_opt
= &cpu_default
;
21691 selected_cpu
= cpu_default
;
21695 selected_cpu
= *mcpu_cpu_opt
;
21697 mcpu_cpu_opt
= &arm_arch_any
;
21700 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21702 autoselect_thumb_from_cpu_variant ();
21704 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21706 #if defined OBJ_COFF || defined OBJ_ELF
21708 unsigned int flags
= 0;
21710 #if defined OBJ_ELF
21711 flags
= meabi_flags
;
21713 switch (meabi_flags
)
21715 case EF_ARM_EABI_UNKNOWN
:
21717 /* Set the flags in the private structure. */
21718 if (uses_apcs_26
) flags
|= F_APCS26
;
21719 if (support_interwork
) flags
|= F_INTERWORK
;
21720 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21721 if (pic_code
) flags
|= F_PIC
;
21722 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21723 flags
|= F_SOFT_FLOAT
;
21725 switch (mfloat_abi_opt
)
21727 case ARM_FLOAT_ABI_SOFT
:
21728 case ARM_FLOAT_ABI_SOFTFP
:
21729 flags
|= F_SOFT_FLOAT
;
21732 case ARM_FLOAT_ABI_HARD
:
21733 if (flags
& F_SOFT_FLOAT
)
21734 as_bad (_("hard-float conflicts with specified fpu"));
21738 /* Using pure-endian doubles (even if soft-float). */
21739 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21740 flags
|= F_VFP_FLOAT
;
21742 #if defined OBJ_ELF
21743 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21744 flags
|= EF_ARM_MAVERICK_FLOAT
;
21747 case EF_ARM_EABI_VER4
:
21748 case EF_ARM_EABI_VER5
:
21749 /* No additional flags to set. */
21756 bfd_set_private_flags (stdoutput
, flags
);
21758 /* We have run out flags in the COFF header to encode the
21759 status of ATPCS support, so instead we create a dummy,
21760 empty, debug section called .arm.atpcs. */
21765 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21769 bfd_set_section_flags
21770 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21771 bfd_set_section_size (stdoutput
, sec
, 0);
21772 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21778 /* Record the CPU type as well. */
21779 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21780 mach
= bfd_mach_arm_iWMMXt2
;
21781 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21782 mach
= bfd_mach_arm_iWMMXt
;
21783 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21784 mach
= bfd_mach_arm_XScale
;
21785 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21786 mach
= bfd_mach_arm_ep9312
;
21787 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21788 mach
= bfd_mach_arm_5TE
;
21789 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21791 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21792 mach
= bfd_mach_arm_5T
;
21794 mach
= bfd_mach_arm_5
;
21796 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21798 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21799 mach
= bfd_mach_arm_4T
;
21801 mach
= bfd_mach_arm_4
;
21803 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21804 mach
= bfd_mach_arm_3M
;
21805 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21806 mach
= bfd_mach_arm_3
;
21807 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21808 mach
= bfd_mach_arm_2a
;
21809 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21810 mach
= bfd_mach_arm_2
;
21812 mach
= bfd_mach_arm_unknown
;
21814 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21817 /* Command line processing. */
21820 Invocation line includes a switch not recognized by the base assembler.
21821 See if it's a processor-specific option.
21823 This routine is somewhat complicated by the need for backwards
21824 compatibility (since older releases of gcc can't be changed).
21825 The new options try to make the interface as compatible as
21828 New options (supported) are:
21830 -mcpu=<cpu name> Assemble for selected processor
21831 -march=<architecture name> Assemble for selected architecture
21832 -mfpu=<fpu architecture> Assemble for selected FPU.
21833 -EB/-mbig-endian Big-endian
21834 -EL/-mlittle-endian Little-endian
21835 -k Generate PIC code
21836 -mthumb Start in Thumb mode
21837 -mthumb-interwork Code supports ARM/Thumb interworking
21839 -m[no-]warn-deprecated Warn about deprecated features
21841 For now we will also provide support for:
21843 -mapcs-32 32-bit Program counter
21844 -mapcs-26 26-bit Program counter
21845 -macps-float Floats passed in FP registers
21846 -mapcs-reentrant Reentrant code
21848 (sometime these will probably be replaced with -mapcs=<list of options>
21849 and -matpcs=<list of options>)
21851 The remaining options are only supported for back-wards compatibility.
21852 Cpu variants, the arm part is optional:
21853 -m[arm]1 Currently not supported.
21854 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21855 -m[arm]3 Arm 3 processor
21856 -m[arm]6[xx], Arm 6 processors
21857 -m[arm]7[xx][t][[d]m] Arm 7 processors
21858 -m[arm]8[10] Arm 8 processors
21859 -m[arm]9[20][tdmi] Arm 9 processors
21860 -mstrongarm[110[0]] StrongARM processors
21861 -mxscale XScale processors
21862 -m[arm]v[2345[t[e]]] Arm architectures
21863 -mall All (except the ARM1)
21865 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
21866 -mfpe-old (No float load/store multiples)
21867 -mvfpxd VFP Single precision
21869 -mno-fpu Disable all floating point instructions
21871 The following CPU names are recognized:
21872 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
21873 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
21874 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
21875 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
21876 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
21877 arm10t arm10e, arm1020t, arm1020e, arm10200e,
21878 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
21882 const char * md_shortopts
= "m:k";
21884 #ifdef ARM_BI_ENDIAN
21885 #define OPTION_EB (OPTION_MD_BASE + 0)
21886 #define OPTION_EL (OPTION_MD_BASE + 1)
21888 #if TARGET_BYTES_BIG_ENDIAN
21889 #define OPTION_EB (OPTION_MD_BASE + 0)
21891 #define OPTION_EL (OPTION_MD_BASE + 1)
21894 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
21896 struct option md_longopts
[] =
21899 {"EB", no_argument
, NULL
, OPTION_EB
},
21902 {"EL", no_argument
, NULL
, OPTION_EL
},
21904 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
21905 {NULL
, no_argument
, NULL
, 0}
21908 size_t md_longopts_size
= sizeof (md_longopts
);
21910 struct arm_option_table
21912 char *option
; /* Option name to match. */
21913 char *help
; /* Help information. */
21914 int *var
; /* Variable to change. */
21915 int value
; /* What to change it to. */
21916 char *deprecated
; /* If non-null, print this message. */
21919 struct arm_option_table arm_opts
[] =
21921 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
21922 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
21923 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
21924 &support_interwork
, 1, NULL
},
21925 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
21926 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
21927 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
21929 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
21930 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
21931 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
21932 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
21935 /* These are recognized by the assembler, but have no affect on code. */
21936 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
21937 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
21939 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
21940 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
21941 &warn_on_deprecated
, 0, NULL
},
21942 {NULL
, NULL
, NULL
, 0, NULL
}
21945 struct arm_legacy_option_table
21947 char *option
; /* Option name to match. */
21948 const arm_feature_set
**var
; /* Variable to change. */
21949 const arm_feature_set value
; /* What to change it to. */
21950 char *deprecated
; /* If non-null, print this message. */
21953 const struct arm_legacy_option_table arm_legacy_opts
[] =
21955 /* DON'T add any new processors to this list -- we want the whole list
21956 to go away... Add them to the processors table instead. */
21957 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21958 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
21959 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21960 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
21961 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21962 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
21963 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21964 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
21965 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21966 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
21967 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21968 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
21969 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21970 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
21971 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21972 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
21973 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21974 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
21975 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21976 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
21977 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21978 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
21979 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21980 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
21981 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21982 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
21983 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21984 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
21985 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21986 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
21987 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21988 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
21989 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21990 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
21991 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21992 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
21993 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21994 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
21995 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21996 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
21997 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21998 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
21999 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22000 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22001 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22002 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22003 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22004 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22005 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22006 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22007 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22008 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22009 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22010 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22011 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22012 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22013 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22014 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22015 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22016 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22017 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22018 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22019 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22020 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22021 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22022 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22023 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22024 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22025 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22026 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22027 N_("use -mcpu=strongarm110")},
22028 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22029 N_("use -mcpu=strongarm1100")},
22030 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22031 N_("use -mcpu=strongarm1110")},
22032 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22033 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22034 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22036 /* Architecture variants -- don't add any more to this list either. */
22037 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22038 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22039 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22040 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22041 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22042 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22043 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22044 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22045 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22046 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22047 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22048 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22049 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22050 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22051 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22052 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22053 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22054 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22056 /* Floating point variants -- don't add any more to this list either. */
22057 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22058 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22059 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22060 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22061 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22063 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22066 struct arm_cpu_option_table
22069 const arm_feature_set value
;
22070 /* For some CPUs we assume an FPU unless the user explicitly sets
22072 const arm_feature_set default_fpu
;
22073 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22075 const char *canonical_name
;
22078 /* This list should, at a minimum, contain all the cpu names
22079 recognized by GCC. */
22080 static const struct arm_cpu_option_table arm_cpus
[] =
22082 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22083 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22084 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22085 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22086 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22087 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22088 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22089 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22090 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22091 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22092 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22093 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22094 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22095 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22096 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22097 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22098 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22099 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22100 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22101 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22102 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22103 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22104 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22105 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22106 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22107 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22108 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22109 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22110 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22111 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22112 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22113 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22114 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22115 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22116 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22117 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22118 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22119 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22120 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22121 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22122 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22123 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22124 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22125 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22126 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22127 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22128 /* For V5 or later processors we default to using VFP; but the user
22129 should really set the FPU type explicitly. */
22130 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22131 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22132 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22133 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22134 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22135 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22136 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22137 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22138 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22139 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22140 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22141 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22142 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22143 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22144 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22145 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22146 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22147 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22148 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22149 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22150 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22151 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22152 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22153 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22154 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22155 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22156 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22157 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
22158 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
22159 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22160 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22161 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22162 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22163 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
22164 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22165 | FPU_NEON_EXT_V1
),
22167 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22168 | FPU_NEON_EXT_V1
),
22170 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
22171 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
22172 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
22173 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22174 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22175 /* ??? XSCALE is really an architecture. */
22176 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22177 /* ??? iwmmxt is not a processor. */
22178 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22179 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22180 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22182 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22183 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22186 struct arm_arch_option_table
22189 const arm_feature_set value
;
22190 const arm_feature_set default_fpu
;
22193 /* This list should, at a minimum, contain all the architecture names
22194 recognized by GCC. */
22195 static const struct arm_arch_option_table arm_archs
[] =
22197 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22198 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22199 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22200 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22201 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22202 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22203 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22204 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22205 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22206 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22207 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22208 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22209 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22210 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22211 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22212 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22213 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22214 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22215 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22216 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22217 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22218 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22219 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22220 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22221 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22222 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22223 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22224 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22225 /* The official spelling of the ARMv7 profile variants is the dashed form.
22226 Accept the non-dashed form for compatibility with old toolchains. */
22227 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22228 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22229 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22230 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22231 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22232 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22233 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22234 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22235 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22236 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22237 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22240 /* ISA extensions in the co-processor space. */
22241 struct arm_option_cpu_value_table
22244 const arm_feature_set value
;
22247 static const struct arm_option_cpu_value_table arm_extensions
[] =
22249 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22250 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22251 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22252 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22253 {NULL
, ARM_ARCH_NONE
}
22256 /* This list should, at a minimum, contain all the fpu names
22257 recognized by GCC. */
22258 static const struct arm_option_cpu_value_table arm_fpus
[] =
22260 {"softfpa", FPU_NONE
},
22261 {"fpe", FPU_ARCH_FPE
},
22262 {"fpe2", FPU_ARCH_FPE
},
22263 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22264 {"fpa", FPU_ARCH_FPA
},
22265 {"fpa10", FPU_ARCH_FPA
},
22266 {"fpa11", FPU_ARCH_FPA
},
22267 {"arm7500fe", FPU_ARCH_FPA
},
22268 {"softvfp", FPU_ARCH_VFP
},
22269 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22270 {"vfp", FPU_ARCH_VFP_V2
},
22271 {"vfp9", FPU_ARCH_VFP_V2
},
22272 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22273 {"vfp10", FPU_ARCH_VFP_V2
},
22274 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22275 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22276 {"vfpv2", FPU_ARCH_VFP_V2
},
22277 {"vfpv3", FPU_ARCH_VFP_V3
},
22278 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22279 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22280 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22281 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22282 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22283 {"arm1020t", FPU_ARCH_VFP_V1
},
22284 {"arm1020e", FPU_ARCH_VFP_V2
},
22285 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22286 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22287 {"maverick", FPU_ARCH_MAVERICK
},
22288 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22289 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22290 {"vfpv4", FPU_ARCH_VFP_V4
},
22291 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22292 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22293 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22294 {NULL
, ARM_ARCH_NONE
}
22297 struct arm_option_value_table
22303 static const struct arm_option_value_table arm_float_abis
[] =
22305 {"hard", ARM_FLOAT_ABI_HARD
},
22306 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22307 {"soft", ARM_FLOAT_ABI_SOFT
},
22312 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22313 static const struct arm_option_value_table arm_eabis
[] =
22315 {"gnu", EF_ARM_EABI_UNKNOWN
},
22316 {"4", EF_ARM_EABI_VER4
},
22317 {"5", EF_ARM_EABI_VER5
},
22322 struct arm_long_option_table
22324 char * option
; /* Substring to match. */
22325 char * help
; /* Help information. */
22326 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22327 char * deprecated
; /* If non-null, print this message. */
22331 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22333 arm_feature_set
*ext_set
= (arm_feature_set
*)
22334 xmalloc (sizeof (arm_feature_set
));
22336 /* Copy the feature set, so that we can modify it. */
22337 *ext_set
= **opt_p
;
22340 while (str
!= NULL
&& *str
!= 0)
22342 const struct arm_option_cpu_value_table
* opt
;
22348 as_bad (_("invalid architectural extension"));
22353 ext
= strchr (str
, '+');
22356 optlen
= ext
- str
;
22358 optlen
= strlen (str
);
22362 as_bad (_("missing architectural extension"));
22366 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22367 if (strncmp (opt
->name
, str
, optlen
) == 0)
22369 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22373 if (opt
->name
== NULL
)
22375 as_bad (_("unknown architectural extension `%s'"), str
);
22386 arm_parse_cpu (char * str
)
22388 const struct arm_cpu_option_table
* opt
;
22389 char * ext
= strchr (str
, '+');
22393 optlen
= ext
- str
;
22395 optlen
= strlen (str
);
22399 as_bad (_("missing cpu name `%s'"), str
);
22403 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22404 if (strncmp (opt
->name
, str
, optlen
) == 0)
22406 mcpu_cpu_opt
= &opt
->value
;
22407 mcpu_fpu_opt
= &opt
->default_fpu
;
22408 if (opt
->canonical_name
)
22409 strcpy (selected_cpu_name
, opt
->canonical_name
);
22414 for (i
= 0; i
< optlen
; i
++)
22415 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22416 selected_cpu_name
[i
] = 0;
22420 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22425 as_bad (_("unknown cpu `%s'"), str
);
22430 arm_parse_arch (char * str
)
22432 const struct arm_arch_option_table
*opt
;
22433 char *ext
= strchr (str
, '+');
22437 optlen
= ext
- str
;
22439 optlen
= strlen (str
);
22443 as_bad (_("missing architecture name `%s'"), str
);
22447 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22448 if (streq (opt
->name
, str
))
22450 march_cpu_opt
= &opt
->value
;
22451 march_fpu_opt
= &opt
->default_fpu
;
22452 strcpy (selected_cpu_name
, opt
->name
);
22455 return arm_parse_extension (ext
, &march_cpu_opt
);
22460 as_bad (_("unknown architecture `%s'\n"), str
);
22465 arm_parse_fpu (char * str
)
22467 const struct arm_option_cpu_value_table
* opt
;
22469 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22470 if (streq (opt
->name
, str
))
22472 mfpu_opt
= &opt
->value
;
22476 as_bad (_("unknown floating point format `%s'\n"), str
);
22481 arm_parse_float_abi (char * str
)
22483 const struct arm_option_value_table
* opt
;
22485 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22486 if (streq (opt
->name
, str
))
22488 mfloat_abi_opt
= opt
->value
;
22492 as_bad (_("unknown floating point abi `%s'\n"), str
);
22498 arm_parse_eabi (char * str
)
22500 const struct arm_option_value_table
*opt
;
22502 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22503 if (streq (opt
->name
, str
))
22505 meabi_flags
= opt
->value
;
22508 as_bad (_("unknown EABI `%s'\n"), str
);
22514 arm_parse_it_mode (char * str
)
22516 bfd_boolean ret
= TRUE
;
22518 if (streq ("arm", str
))
22519 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22520 else if (streq ("thumb", str
))
22521 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22522 else if (streq ("always", str
))
22523 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22524 else if (streq ("never", str
))
22525 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22528 as_bad (_("unknown implicit IT mode `%s', should be "\
22529 "arm, thumb, always, or never."), str
);
22536 struct arm_long_option_table arm_long_opts
[] =
22538 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22539 arm_parse_cpu
, NULL
},
22540 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22541 arm_parse_arch
, NULL
},
22542 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22543 arm_parse_fpu
, NULL
},
22544 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22545 arm_parse_float_abi
, NULL
},
22547 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22548 arm_parse_eabi
, NULL
},
22550 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22551 arm_parse_it_mode
, NULL
},
22552 {NULL
, NULL
, 0, NULL
}
22556 md_parse_option (int c
, char * arg
)
22558 struct arm_option_table
*opt
;
22559 const struct arm_legacy_option_table
*fopt
;
22560 struct arm_long_option_table
*lopt
;
22566 target_big_endian
= 1;
22572 target_big_endian
= 0;
22576 case OPTION_FIX_V4BX
:
22581 /* Listing option. Just ignore these, we don't support additional
22586 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22588 if (c
== opt
->option
[0]
22589 && ((arg
== NULL
&& opt
->option
[1] == 0)
22590 || streq (arg
, opt
->option
+ 1)))
22592 /* If the option is deprecated, tell the user. */
22593 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22594 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22595 arg
? arg
: "", _(opt
->deprecated
));
22597 if (opt
->var
!= NULL
)
22598 *opt
->var
= opt
->value
;
22604 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22606 if (c
== fopt
->option
[0]
22607 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22608 || streq (arg
, fopt
->option
+ 1)))
22610 /* If the option is deprecated, tell the user. */
22611 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22612 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22613 arg
? arg
: "", _(fopt
->deprecated
));
22615 if (fopt
->var
!= NULL
)
22616 *fopt
->var
= &fopt
->value
;
22622 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22624 /* These options are expected to have an argument. */
22625 if (c
== lopt
->option
[0]
22627 && strncmp (arg
, lopt
->option
+ 1,
22628 strlen (lopt
->option
+ 1)) == 0)
22630 /* If the option is deprecated, tell the user. */
22631 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22632 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22633 _(lopt
->deprecated
));
22635 /* Call the sup-option parser. */
22636 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22647 md_show_usage (FILE * fp
)
22649 struct arm_option_table
*opt
;
22650 struct arm_long_option_table
*lopt
;
22652 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22654 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22655 if (opt
->help
!= NULL
)
22656 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22658 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22659 if (lopt
->help
!= NULL
)
22660 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22664 -EB assemble code for a big-endian cpu\n"));
22669 -EL assemble code for a little-endian cpu\n"));
22673 --fix-v4bx Allow BX in ARMv4 code\n"));
22681 arm_feature_set flags
;
22682 } cpu_arch_ver_table
;
22684 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22685 least features first. */
22686 static const cpu_arch_ver_table cpu_arch_ver
[] =
22692 {4, ARM_ARCH_V5TE
},
22693 {5, ARM_ARCH_V5TEJ
},
22697 {11, ARM_ARCH_V6M
},
22698 {8, ARM_ARCH_V6T2
},
22699 {10, ARM_ARCH_V7A
},
22700 {10, ARM_ARCH_V7R
},
22701 {10, ARM_ARCH_V7M
},
22705 /* Set an attribute if it has not already been set by the user. */
22707 aeabi_set_attribute_int (int tag
, int value
)
22710 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22711 || !attributes_set_explicitly
[tag
])
22712 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22716 aeabi_set_attribute_string (int tag
, const char *value
)
22719 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22720 || !attributes_set_explicitly
[tag
])
22721 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22724 /* Set the public EABI object attributes. */
22726 aeabi_set_public_attributes (void)
22729 arm_feature_set flags
;
22730 arm_feature_set tmp
;
22731 const cpu_arch_ver_table
*p
;
22733 /* Choose the architecture based on the capabilities of the requested cpu
22734 (if any) and/or the instructions actually used. */
22735 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22736 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22737 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22738 /*Allow the user to override the reported architecture. */
22741 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22742 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22747 for (p
= cpu_arch_ver
; p
->val
; p
++)
22749 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22752 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22756 /* The table lookup above finds the last architecture to contribute
22757 a new feature. Unfortunately, Tag13 is a subset of the union of
22758 v6T2 and v7-M, so it is never seen as contributing a new feature.
22759 We can not search for the last entry which is entirely used,
22760 because if no CPU is specified we build up only those flags
22761 actually used. Perhaps we should separate out the specified
22762 and implicit cases. Avoid taking this path for -march=all by
22763 checking for contradictory v7-A / v7-M features. */
22765 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22766 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22767 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22770 /* Tag_CPU_name. */
22771 if (selected_cpu_name
[0])
22775 q
= selected_cpu_name
;
22776 if (strncmp (q
, "armv", 4) == 0)
22781 for (i
= 0; q
[i
]; i
++)
22782 q
[i
] = TOUPPER (q
[i
]);
22784 aeabi_set_attribute_string (Tag_CPU_name
, q
);
22787 /* Tag_CPU_arch. */
22788 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22790 /* Tag_CPU_arch_profile. */
22791 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22792 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22793 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22794 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22795 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22796 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22798 /* Tag_ARM_ISA_use. */
22799 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22801 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22803 /* Tag_THUMB_ISA_use. */
22804 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22806 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22807 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22809 /* Tag_VFP_arch. */
22810 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22811 aeabi_set_attribute_int (Tag_VFP_arch
,
22812 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22814 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22815 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22816 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
22817 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22818 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22819 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22820 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22821 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22822 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22824 /* Tag_WMMX_arch. */
22825 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22826 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22827 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22828 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22830 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22831 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22832 aeabi_set_attribute_int
22833 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22836 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22837 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22838 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22841 /* Add the default contents for the .ARM.attributes section. */
22845 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22848 aeabi_set_public_attributes ();
22850 #endif /* OBJ_ELF */
22853 /* Parse a .cpu directive. */
22856 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
22858 const struct arm_cpu_option_table
*opt
;
22862 name
= input_line_pointer
;
22863 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22864 input_line_pointer
++;
22865 saved_char
= *input_line_pointer
;
22866 *input_line_pointer
= 0;
22868 /* Skip the first "all" entry. */
22869 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
22870 if (streq (opt
->name
, name
))
22872 mcpu_cpu_opt
= &opt
->value
;
22873 selected_cpu
= opt
->value
;
22874 if (opt
->canonical_name
)
22875 strcpy (selected_cpu_name
, opt
->canonical_name
);
22879 for (i
= 0; opt
->name
[i
]; i
++)
22880 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22881 selected_cpu_name
[i
] = 0;
22883 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22884 *input_line_pointer
= saved_char
;
22885 demand_empty_rest_of_line ();
22888 as_bad (_("unknown cpu `%s'"), name
);
22889 *input_line_pointer
= saved_char
;
22890 ignore_rest_of_line ();
22894 /* Parse a .arch directive. */
22897 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
22899 const struct arm_arch_option_table
*opt
;
22903 name
= input_line_pointer
;
22904 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22905 input_line_pointer
++;
22906 saved_char
= *input_line_pointer
;
22907 *input_line_pointer
= 0;
22909 /* Skip the first "all" entry. */
22910 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22911 if (streq (opt
->name
, name
))
22913 mcpu_cpu_opt
= &opt
->value
;
22914 selected_cpu
= opt
->value
;
22915 strcpy (selected_cpu_name
, opt
->name
);
22916 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22917 *input_line_pointer
= saved_char
;
22918 demand_empty_rest_of_line ();
22922 as_bad (_("unknown architecture `%s'\n"), name
);
22923 *input_line_pointer
= saved_char
;
22924 ignore_rest_of_line ();
22928 /* Parse a .object_arch directive. */
22931 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
22933 const struct arm_arch_option_table
*opt
;
22937 name
= input_line_pointer
;
22938 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22939 input_line_pointer
++;
22940 saved_char
= *input_line_pointer
;
22941 *input_line_pointer
= 0;
22943 /* Skip the first "all" entry. */
22944 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
22945 if (streq (opt
->name
, name
))
22947 object_arch
= &opt
->value
;
22948 *input_line_pointer
= saved_char
;
22949 demand_empty_rest_of_line ();
22953 as_bad (_("unknown architecture `%s'\n"), name
);
22954 *input_line_pointer
= saved_char
;
22955 ignore_rest_of_line ();
22958 /* Parse a .fpu directive. */
22961 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
22963 const struct arm_option_cpu_value_table
*opt
;
22967 name
= input_line_pointer
;
22968 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
22969 input_line_pointer
++;
22970 saved_char
= *input_line_pointer
;
22971 *input_line_pointer
= 0;
22973 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22974 if (streq (opt
->name
, name
))
22976 mfpu_opt
= &opt
->value
;
22977 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22978 *input_line_pointer
= saved_char
;
22979 demand_empty_rest_of_line ();
22983 as_bad (_("unknown floating point format `%s'\n"), name
);
22984 *input_line_pointer
= saved_char
;
22985 ignore_rest_of_line ();
22988 /* Copy symbol information. */
22991 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
22993 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
22997 /* Given a symbolic attribute NAME, return the proper integer value.
22998 Returns -1 if the attribute is not known. */
23001 arm_convert_symbolic_attribute (const char *name
)
23003 static const struct
23008 attribute_table
[] =
23010 /* When you modify this table you should
23011 also modify the list in doc/c-arm.texi. */
23012 #define T(tag) {#tag, tag}
23013 T (Tag_CPU_raw_name
),
23016 T (Tag_CPU_arch_profile
),
23017 T (Tag_ARM_ISA_use
),
23018 T (Tag_THUMB_ISA_use
),
23021 T (Tag_Advanced_SIMD_arch
),
23022 T (Tag_PCS_config
),
23023 T (Tag_ABI_PCS_R9_use
),
23024 T (Tag_ABI_PCS_RW_data
),
23025 T (Tag_ABI_PCS_RO_data
),
23026 T (Tag_ABI_PCS_GOT_use
),
23027 T (Tag_ABI_PCS_wchar_t
),
23028 T (Tag_ABI_FP_rounding
),
23029 T (Tag_ABI_FP_denormal
),
23030 T (Tag_ABI_FP_exceptions
),
23031 T (Tag_ABI_FP_user_exceptions
),
23032 T (Tag_ABI_FP_number_model
),
23033 T (Tag_ABI_align8_needed
),
23034 T (Tag_ABI_align8_preserved
),
23035 T (Tag_ABI_enum_size
),
23036 T (Tag_ABI_HardFP_use
),
23037 T (Tag_ABI_VFP_args
),
23038 T (Tag_ABI_WMMX_args
),
23039 T (Tag_ABI_optimization_goals
),
23040 T (Tag_ABI_FP_optimization_goals
),
23041 T (Tag_compatibility
),
23042 T (Tag_CPU_unaligned_access
),
23043 T (Tag_VFP_HP_extension
),
23044 T (Tag_ABI_FP_16bit_format
),
23045 T (Tag_MPextension_use
),
23047 T (Tag_nodefaults
),
23048 T (Tag_also_compatible_with
),
23049 T (Tag_conformance
),
23051 T (Tag_Virtualization_use
),
23052 /* We deliberately do not include Tag_MPextension_use_legacy. */
23060 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23061 if (streq (name
, attribute_table
[i
].name
))
23062 return attribute_table
[i
].tag
;
23068 /* Apply sym value for relocations only in the case that
23069 they are for local symbols and you have the respective
23070 architectural feature for blx and simple switches. */
23072 arm_apply_sym_value (struct fix
* fixP
)
23075 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23076 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23078 switch (fixP
->fx_r_type
)
23080 case BFD_RELOC_ARM_PCREL_BLX
:
23081 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23082 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23086 case BFD_RELOC_ARM_PCREL_CALL
:
23087 case BFD_RELOC_THUMB_PCREL_BLX
:
23088 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23099 #endif /* OBJ_ELF */