1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
188 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
221 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
222 static const arm_feature_set fpu_vfp_ext_d32
=
223 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
224 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
225 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
226 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
227 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
228 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
229 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
231 static int mfloat_abi_opt
= -1;
232 /* Record user cpu selection for object attributes. */
233 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
234 /* Must be long enough to hold any of the names in arm_cpus. */
235 static char selected_cpu_name
[16];
238 static int meabi_flags
= EABI_DEFAULT
;
240 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
243 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
248 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
253 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
254 symbolS
* GOT_symbol
;
257 /* 0: assemble for ARM,
258 1: assemble for Thumb,
259 2: assemble for Thumb even though target CPU does not support thumb
261 static int thumb_mode
= 0;
262 /* A value distinct from the possible values for thumb_mode that we
263 can use to record whether thumb_mode has been copied into the
264 tc_frag_data field of a frag. */
265 #define MODE_RECORDED (1 << 4)
267 /* Specifies the intrinsic IT insn behavior mode. */
268 enum implicit_it_mode
270 IMPLICIT_IT_MODE_NEVER
= 0x00,
271 IMPLICIT_IT_MODE_ARM
= 0x01,
272 IMPLICIT_IT_MODE_THUMB
= 0x02,
273 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
275 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
277 /* If unified_syntax is true, we are processing the new unified
278 ARM/Thumb syntax. Important differences from the old ARM mode:
280 - Immediate operands do not require a # prefix.
281 - Conditional affixes always appear at the end of the
282 instruction. (For backward compatibility, those instructions
283 that formerly had them in the middle, continue to accept them
285 - The IT instruction may appear, and if it does is validated
286 against subsequent conditional affixes. It does not generate
289 Important differences from the old Thumb mode:
291 - Immediate operands do not require a # prefix.
292 - Most of the V6T2 instructions are only available in unified mode.
293 - The .N and .W suffixes are recognized and honored (it is an error
294 if they cannot be honored).
295 - All instructions set the flags if and only if they have an 's' affix.
296 - Conditional affixes may be used. They are validated against
297 preceding IT instructions. Unlike ARM mode, you cannot use a
298 conditional affix except in the scope of an IT instruction. */
300 static bfd_boolean unified_syntax
= FALSE
;
315 enum neon_el_type type
;
319 #define NEON_MAX_TYPE_ELS 4
323 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
327 enum it_instruction_type
332 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
333 if inside, should be the last one. */
334 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
335 i.e. BKPT and NOP. */
336 IT_INSN
/* The IT insn has been parsed. */
342 unsigned long instruction
;
346 /* "uncond_value" is set to the value in place of the conditional field in
347 unconditional versions of the instruction, or -1 if nothing is
350 struct neon_type vectype
;
351 /* This does not indicate an actual NEON instruction, only that
352 the mnemonic accepts neon-style type suffixes. */
354 /* Set to the opcode if the instruction needs relaxation.
355 Zero if the instruction is not relaxed. */
359 bfd_reloc_code_real_type type
;
364 enum it_instruction_type it_insn_type
;
370 struct neon_type_el vectype
;
371 unsigned present
: 1; /* Operand present. */
372 unsigned isreg
: 1; /* Operand was a register. */
373 unsigned immisreg
: 1; /* .imm field is a second register. */
374 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
375 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
376 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
377 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
378 instructions. This allows us to disambiguate ARM <-> vector insns. */
379 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
380 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
381 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
382 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
383 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
384 unsigned writeback
: 1; /* Operand has trailing ! */
385 unsigned preind
: 1; /* Preindexed address. */
386 unsigned postind
: 1; /* Postindexed address. */
387 unsigned negative
: 1; /* Index register was negated. */
388 unsigned shifted
: 1; /* Shift applied to operation. */
389 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
393 static struct arm_it inst
;
395 #define NUM_FLOAT_VALS 8
397 const char * fp_const
[] =
399 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
402 /* Number of littlenums required to hold an extended precision number. */
403 #define MAX_LITTLENUMS 6
405 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
415 #define CP_T_X 0x00008000
416 #define CP_T_Y 0x00400000
418 #define CONDS_BIT 0x00100000
419 #define LOAD_BIT 0x00100000
421 #define DOUBLE_LOAD_FLAG 0x00000001
425 const char * template_name
;
429 #define COND_ALWAYS 0xE
433 const char * template_name
;
437 struct asm_barrier_opt
439 const char * template_name
;
443 /* The bit that distinguishes CPSR and SPSR. */
444 #define SPSR_BIT (1 << 22)
446 /* The individual PSR flag bits. */
447 #define PSR_c (1 << 16)
448 #define PSR_x (1 << 17)
449 #define PSR_s (1 << 18)
450 #define PSR_f (1 << 19)
455 bfd_reloc_code_real_type reloc
;
460 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
461 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
466 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
469 /* Bits for DEFINED field in neon_typed_alias. */
470 #define NTA_HASTYPE 1
471 #define NTA_HASINDEX 2
473 struct neon_typed_alias
475 unsigned char defined
;
477 struct neon_type_el eltype
;
480 /* ARM register categories. This includes coprocessor numbers and various
481 architecture extensions' registers. */
507 /* Structure for a hash table entry for a register.
508 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
509 information which states whether a vector type or index is specified (for a
510 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
514 unsigned char number
;
516 unsigned char builtin
;
517 struct neon_typed_alias
* neon
;
520 /* Diagnostics used when we don't get a register of the expected type. */
521 const char * const reg_expected_msgs
[] =
523 N_("ARM register expected"),
524 N_("bad or missing co-processor number"),
525 N_("co-processor register expected"),
526 N_("FPA register expected"),
527 N_("VFP single precision register expected"),
528 N_("VFP/Neon double precision register expected"),
529 N_("Neon quad precision register expected"),
530 N_("VFP single or double precision register expected"),
531 N_("Neon double or quad precision register expected"),
532 N_("VFP single, double or Neon quad precision register expected"),
533 N_("VFP system register expected"),
534 N_("Maverick MVF register expected"),
535 N_("Maverick MVD register expected"),
536 N_("Maverick MVFX register expected"),
537 N_("Maverick MVDX register expected"),
538 N_("Maverick MVAX register expected"),
539 N_("Maverick DSPSC register expected"),
540 N_("iWMMXt data register expected"),
541 N_("iWMMXt control register expected"),
542 N_("iWMMXt scalar register expected"),
543 N_("XScale accumulator register expected"),
546 /* Some well known registers that we refer to directly elsewhere. */
551 /* ARM instructions take 4bytes in the object file, Thumb instructions
557 /* Basic string to match. */
558 const char * template_name
;
560 /* Parameters to instruction. */
561 unsigned int operands
[8];
563 /* Conditional tag - see opcode_lookup. */
564 unsigned int tag
: 4;
566 /* Basic instruction code. */
567 unsigned int avalue
: 28;
569 /* Thumb-format instruction code. */
572 /* Which architecture variant provides this instruction. */
573 const arm_feature_set
* avariant
;
574 const arm_feature_set
* tvariant
;
576 /* Function to call to encode instruction in ARM format. */
577 void (* aencode
) (void);
579 /* Function to call to encode instruction in Thumb format. */
580 void (* tencode
) (void);
583 /* Defines for various bits that we will want to toggle. */
584 #define INST_IMMEDIATE 0x02000000
585 #define OFFSET_REG 0x02000000
586 #define HWOFFSET_IMM 0x00400000
587 #define SHIFT_BY_REG 0x00000010
588 #define PRE_INDEX 0x01000000
589 #define INDEX_UP 0x00800000
590 #define WRITE_BACK 0x00200000
591 #define LDM_TYPE_2_OR_3 0x00400000
592 #define CPSI_MMOD 0x00020000
594 #define LITERAL_MASK 0xf000f000
595 #define OPCODE_MASK 0xfe1fffff
596 #define V4_STR_BIT 0x00000020
598 #define T2_SUBS_PC_LR 0xf3de8f00
600 #define DATA_OP_SHIFT 21
602 #define T2_OPCODE_MASK 0xfe1fffff
603 #define T2_DATA_OP_SHIFT 21
605 /* Codes to distinguish the arithmetic instructions. */
616 #define OPCODE_CMP 10
617 #define OPCODE_CMN 11
618 #define OPCODE_ORR 12
619 #define OPCODE_MOV 13
620 #define OPCODE_BIC 14
621 #define OPCODE_MVN 15
623 #define T2_OPCODE_AND 0
624 #define T2_OPCODE_BIC 1
625 #define T2_OPCODE_ORR 2
626 #define T2_OPCODE_ORN 3
627 #define T2_OPCODE_EOR 4
628 #define T2_OPCODE_ADD 8
629 #define T2_OPCODE_ADC 10
630 #define T2_OPCODE_SBC 11
631 #define T2_OPCODE_SUB 13
632 #define T2_OPCODE_RSB 14
634 #define T_OPCODE_MUL 0x4340
635 #define T_OPCODE_TST 0x4200
636 #define T_OPCODE_CMN 0x42c0
637 #define T_OPCODE_NEG 0x4240
638 #define T_OPCODE_MVN 0x43c0
640 #define T_OPCODE_ADD_R3 0x1800
641 #define T_OPCODE_SUB_R3 0x1a00
642 #define T_OPCODE_ADD_HI 0x4400
643 #define T_OPCODE_ADD_ST 0xb000
644 #define T_OPCODE_SUB_ST 0xb080
645 #define T_OPCODE_ADD_SP 0xa800
646 #define T_OPCODE_ADD_PC 0xa000
647 #define T_OPCODE_ADD_I8 0x3000
648 #define T_OPCODE_SUB_I8 0x3800
649 #define T_OPCODE_ADD_I3 0x1c00
650 #define T_OPCODE_SUB_I3 0x1e00
652 #define T_OPCODE_ASR_R 0x4100
653 #define T_OPCODE_LSL_R 0x4080
654 #define T_OPCODE_LSR_R 0x40c0
655 #define T_OPCODE_ROR_R 0x41c0
656 #define T_OPCODE_ASR_I 0x1000
657 #define T_OPCODE_LSL_I 0x0000
658 #define T_OPCODE_LSR_I 0x0800
660 #define T_OPCODE_MOV_I8 0x2000
661 #define T_OPCODE_CMP_I8 0x2800
662 #define T_OPCODE_CMP_LR 0x4280
663 #define T_OPCODE_MOV_HR 0x4600
664 #define T_OPCODE_CMP_HR 0x4500
666 #define T_OPCODE_LDR_PC 0x4800
667 #define T_OPCODE_LDR_SP 0x9800
668 #define T_OPCODE_STR_SP 0x9000
669 #define T_OPCODE_LDR_IW 0x6800
670 #define T_OPCODE_STR_IW 0x6000
671 #define T_OPCODE_LDR_IH 0x8800
672 #define T_OPCODE_STR_IH 0x8000
673 #define T_OPCODE_LDR_IB 0x7800
674 #define T_OPCODE_STR_IB 0x7000
675 #define T_OPCODE_LDR_RW 0x5800
676 #define T_OPCODE_STR_RW 0x5000
677 #define T_OPCODE_LDR_RH 0x5a00
678 #define T_OPCODE_STR_RH 0x5200
679 #define T_OPCODE_LDR_RB 0x5c00
680 #define T_OPCODE_STR_RB 0x5400
682 #define T_OPCODE_PUSH 0xb400
683 #define T_OPCODE_POP 0xbc00
685 #define T_OPCODE_BRANCH 0xe000
687 #define THUMB_SIZE 2 /* Size of thumb instruction. */
688 #define THUMB_PP_PC_LR 0x0100
689 #define THUMB_LOAD_BIT 0x0800
690 #define THUMB2_LOAD_BIT 0x00100000
692 #define BAD_ARGS _("bad arguments to instruction")
693 #define BAD_SP _("r13 not allowed here")
694 #define BAD_PC _("r15 not allowed here")
695 #define BAD_COND _("instruction cannot be conditional")
696 #define BAD_OVERLAP _("registers may not be the same")
697 #define BAD_HIREG _("lo register required")
698 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
699 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
700 #define BAD_BRANCH _("branch must be last instruction in IT block")
701 #define BAD_NOT_IT _("instruction not allowed in IT block")
702 #define BAD_FPU _("selected FPU does not support instruction")
703 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
704 #define BAD_IT_COND _("incorrect condition in IT block")
705 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
706 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
707 #define BAD_PC_ADDRESSING \
708 _("cannot use register index with PC-relative addressing")
709 #define BAD_PC_WRITEBACK \
710 _("cannot use writeback with PC-relative addressing")
712 static struct hash_control
* arm_ops_hsh
;
713 static struct hash_control
* arm_cond_hsh
;
714 static struct hash_control
* arm_shift_hsh
;
715 static struct hash_control
* arm_psr_hsh
;
716 static struct hash_control
* arm_v7m_psr_hsh
;
717 static struct hash_control
* arm_reg_hsh
;
718 static struct hash_control
* arm_reloc_hsh
;
719 static struct hash_control
* arm_barrier_opt_hsh
;
721 /* Stuff needed to resolve the label ambiguity
730 symbolS
* last_label_seen
;
731 static int label_is_thumb_function_name
= FALSE
;
733 /* Literal pool structure. Held on a per-section
734 and per-sub-section basis. */
736 #define MAX_LITERAL_POOL_SIZE 1024
737 typedef struct literal_pool
739 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
740 unsigned int next_free_entry
;
745 struct literal_pool
* next
;
748 /* Pointer to a linked list of literal pools. */
749 literal_pool
* list_of_pools
= NULL
;
752 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
754 static struct current_it now_it
;
758 now_it_compatible (int cond
)
760 return (cond
& ~1) == (now_it
.cc
& ~1);
764 conditional_insn (void)
766 return inst
.cond
!= COND_ALWAYS
;
769 static int in_it_block (void);
771 static int handle_it_state (void);
773 static void force_automatic_it_block_close (void);
775 static void it_fsm_post_encode (void);
777 #define set_it_insn_type(type) \
780 inst.it_insn_type = type; \
781 if (handle_it_state () == FAIL) \
786 #define set_it_insn_type_nonvoid(type, failret) \
789 inst.it_insn_type = type; \
790 if (handle_it_state () == FAIL) \
795 #define set_it_insn_type_last() \
798 if (inst.cond == COND_ALWAYS) \
799 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
801 set_it_insn_type (INSIDE_IT_LAST_INSN); \
807 /* This array holds the chars that always start a comment. If the
808 pre-processor is disabled, these aren't very useful. */
809 const char comment_chars
[] = "@";
811 /* This array holds the chars that only start a comment at the beginning of
812 a line. If the line seems to have the form '# 123 filename'
813 .line and .file directives will appear in the pre-processed output. */
814 /* Note that input_file.c hand checks for '#' at the beginning of the
815 first line of the input file. This is because the compiler outputs
816 #NO_APP at the beginning of its output. */
817 /* Also note that comments like this one will always work. */
818 const char line_comment_chars
[] = "#";
820 const char line_separator_chars
[] = ";";
822 /* Chars that can be used to separate mant
823 from exp in floating point numbers. */
824 const char EXP_CHARS
[] = "eE";
826 /* Chars that mean this number is a floating point constant. */
830 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
832 /* Prefix characters that indicate the start of an immediate
834 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
836 /* Separator character handling. */
838 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
841 skip_past_char (char ** str
, char c
)
852 #define skip_past_comma(str) skip_past_char (str, ',')
854 /* Arithmetic expressions (possibly involving symbols). */
856 /* Return TRUE if anything in the expression is a bignum. */
859 walk_no_bignums (symbolS
* sp
)
861 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
864 if (symbol_get_value_expression (sp
)->X_add_symbol
)
866 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
867 || (symbol_get_value_expression (sp
)->X_op_symbol
868 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
874 static int in_my_get_expression
= 0;
876 /* Third argument to my_get_expression. */
877 #define GE_NO_PREFIX 0
878 #define GE_IMM_PREFIX 1
879 #define GE_OPT_PREFIX 2
880 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
881 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
882 #define GE_OPT_PREFIX_BIG 3
885 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
890 /* In unified syntax, all prefixes are optional. */
892 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
897 case GE_NO_PREFIX
: break;
899 if (!is_immediate_prefix (**str
))
901 inst
.error
= _("immediate expression requires a # prefix");
907 case GE_OPT_PREFIX_BIG
:
908 if (is_immediate_prefix (**str
))
914 memset (ep
, 0, sizeof (expressionS
));
916 save_in
= input_line_pointer
;
917 input_line_pointer
= *str
;
918 in_my_get_expression
= 1;
919 seg
= expression (ep
);
920 in_my_get_expression
= 0;
922 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
924 /* We found a bad or missing expression in md_operand(). */
925 *str
= input_line_pointer
;
926 input_line_pointer
= save_in
;
927 if (inst
.error
== NULL
)
928 inst
.error
= (ep
->X_op
== O_absent
929 ? _("missing expression") :_("bad expression"));
934 if (seg
!= absolute_section
935 && seg
!= text_section
936 && seg
!= data_section
937 && seg
!= bss_section
938 && seg
!= undefined_section
)
940 inst
.error
= _("bad segment");
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
949 /* Get rid of any bignums now, so that we don't generate an error for which
950 we can't establish a line number later on. Big numbers are never valid
951 in instructions, which is where this routine is always called. */
952 if (prefix_mode
!= GE_OPT_PREFIX_BIG
953 && (ep
->X_op
== O_big
955 && (walk_no_bignums (ep
->X_add_symbol
)
957 && walk_no_bignums (ep
->X_op_symbol
))))))
959 inst
.error
= _("invalid constant");
960 *str
= input_line_pointer
;
961 input_line_pointer
= save_in
;
965 *str
= input_line_pointer
;
966 input_line_pointer
= save_in
;
970 /* Turn a string in input_line_pointer into a floating point constant
971 of type TYPE, and store the appropriate bytes in *LITP. The number
972 of LITTLENUMS emitted is stored in *SIZEP. An error message is
973 returned, or NULL on OK.
975 Note that fp constants aren't represent in the normal way on the ARM.
976 In big endian mode, things are as expected. However, in little endian
977 mode fp constants are big-endian word-wise, and little-endian byte-wise
978 within the words. For example, (double) 1.1 in big endian mode is
979 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
980 the byte sequence 99 99 f1 3f 9a 99 99 99.
982 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
985 md_atof (int type
, char * litP
, int * sizeP
)
988 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1020 return _("Unrecognized or unsupported floating point constant");
1023 t
= atof_ieee (input_line_pointer
, type
, words
);
1025 input_line_pointer
= t
;
1026 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1028 if (target_big_endian
)
1030 for (i
= 0; i
< prec
; i
++)
1032 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1033 litP
+= sizeof (LITTLENUM_TYPE
);
1038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1039 for (i
= prec
- 1; i
>= 0; i
--)
1041 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1042 litP
+= sizeof (LITTLENUM_TYPE
);
1045 /* For a 4 byte float the order of elements in `words' is 1 0.
1046 For an 8 byte float the order is 1 0 3 2. */
1047 for (i
= 0; i
< prec
; i
+= 2)
1049 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1050 sizeof (LITTLENUM_TYPE
));
1051 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1052 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1053 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1060 /* We handle all bad expressions here, so that we can report the faulty
1061 instruction in the error message. */
1063 md_operand (expressionS
* exp
)
1065 if (in_my_get_expression
)
1066 exp
->X_op
= O_illegal
;
1069 /* Immediate values. */
1071 /* Generic immediate-value read function for use in directives.
1072 Accepts anything that 'expression' can fold to a constant.
1073 *val receives the number. */
1076 immediate_for_directive (int *val
)
1079 exp
.X_op
= O_illegal
;
1081 if (is_immediate_prefix (*input_line_pointer
))
1083 input_line_pointer
++;
1087 if (exp
.X_op
!= O_constant
)
1089 as_bad (_("expected #constant"));
1090 ignore_rest_of_line ();
1093 *val
= exp
.X_add_number
;
1098 /* Register parsing. */
1100 /* Generic register parser. CCP points to what should be the
1101 beginning of a register name. If it is indeed a valid register
1102 name, advance CCP over it and return the reg_entry structure;
1103 otherwise return NULL. Does not issue diagnostics. */
1105 static struct reg_entry
*
1106 arm_reg_parse_multi (char **ccp
)
1110 struct reg_entry
*reg
;
1112 #ifdef REGISTER_PREFIX
1113 if (*start
!= REGISTER_PREFIX
)
1117 #ifdef OPTIONAL_REGISTER_PREFIX
1118 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1123 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1128 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1130 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1140 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1141 enum arm_reg_type type
)
1143 /* Alternative syntaxes are accepted for a few register classes. */
1150 /* Generic coprocessor register names are allowed for these. */
1151 if (reg
&& reg
->type
== REG_TYPE_CN
)
1156 /* For backward compatibility, a bare number is valid here. */
1158 unsigned long processor
= strtoul (start
, ccp
, 10);
1159 if (*ccp
!= start
&& processor
<= 15)
1163 case REG_TYPE_MMXWC
:
1164 /* WC includes WCG. ??? I'm not sure this is true for all
1165 instructions that take WC registers. */
1166 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1177 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1178 return value is the register number or FAIL. */
1181 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1184 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1187 /* Do not allow a scalar (reg+index) to parse as a register. */
1188 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1191 if (reg
&& reg
->type
== type
)
1194 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1201 /* Parse a Neon type specifier. *STR should point at the leading '.'
1202 character. Does no verification at this stage that the type fits the opcode
1209 Can all be legally parsed by this function.
1211 Fills in neon_type struct pointer with parsed information, and updates STR
1212 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1213 type, FAIL if not. */
1216 parse_neon_type (struct neon_type
*type
, char **str
)
1223 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1225 enum neon_el_type thistype
= NT_untyped
;
1226 unsigned thissize
= -1u;
1233 /* Just a size without an explicit type. */
1237 switch (TOLOWER (*ptr
))
1239 case 'i': thistype
= NT_integer
; break;
1240 case 'f': thistype
= NT_float
; break;
1241 case 'p': thistype
= NT_poly
; break;
1242 case 's': thistype
= NT_signed
; break;
1243 case 'u': thistype
= NT_unsigned
; break;
1245 thistype
= NT_float
;
1250 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1256 /* .f is an abbreviation for .f32. */
1257 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1262 thissize
= strtoul (ptr
, &ptr
, 10);
1264 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1267 as_bad (_("bad size %d in type specifier"), thissize
);
1275 type
->el
[type
->elems
].type
= thistype
;
1276 type
->el
[type
->elems
].size
= thissize
;
1281 /* Empty/missing type is not a successful parse. */
1282 if (type
->elems
== 0)
1290 /* Errors may be set multiple times during parsing or bit encoding
1291 (particularly in the Neon bits), but usually the earliest error which is set
1292 will be the most meaningful. Avoid overwriting it with later (cascading)
1293 errors by calling this function. */
1296 first_error (const char *err
)
1302 /* Parse a single type, e.g. ".s32", leading period included. */
1304 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1307 struct neon_type optype
;
1311 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1313 if (optype
.elems
== 1)
1314 *vectype
= optype
.el
[0];
1317 first_error (_("only one type should be specified for operand"));
1323 first_error (_("vector type expected"));
1335 /* Special meanings for indices (which have a range of 0-7), which will fit into
1338 #define NEON_ALL_LANES 15
1339 #define NEON_INTERLEAVE_LANES 14
1341 /* Parse either a register or a scalar, with an optional type. Return the
1342 register number, and optionally fill in the actual type of the register
1343 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1344 type/index information in *TYPEINFO. */
1347 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1348 enum arm_reg_type
*rtype
,
1349 struct neon_typed_alias
*typeinfo
)
1352 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1353 struct neon_typed_alias atype
;
1354 struct neon_type_el parsetype
;
1358 atype
.eltype
.type
= NT_invtype
;
1359 atype
.eltype
.size
= -1;
1361 /* Try alternate syntax for some types of register. Note these are mutually
1362 exclusive with the Neon syntax extensions. */
1365 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1373 /* Undo polymorphism when a set of register types may be accepted. */
1374 if ((type
== REG_TYPE_NDQ
1375 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1376 || (type
== REG_TYPE_VFSD
1377 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1378 || (type
== REG_TYPE_NSDQ
1379 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1380 || reg
->type
== REG_TYPE_NQ
))
1381 || (type
== REG_TYPE_MMXWC
1382 && (reg
->type
== REG_TYPE_MMXWCG
)))
1383 type
= (enum arm_reg_type
) reg
->type
;
1385 if (type
!= reg
->type
)
1391 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1393 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1395 first_error (_("can't redefine type for operand"));
1398 atype
.defined
|= NTA_HASTYPE
;
1399 atype
.eltype
= parsetype
;
1402 if (skip_past_char (&str
, '[') == SUCCESS
)
1404 if (type
!= REG_TYPE_VFD
)
1406 first_error (_("only D registers may be indexed"));
1410 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1412 first_error (_("can't change index for operand"));
1416 atype
.defined
|= NTA_HASINDEX
;
1418 if (skip_past_char (&str
, ']') == SUCCESS
)
1419 atype
.index
= NEON_ALL_LANES
;
1424 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1426 if (exp
.X_op
!= O_constant
)
1428 first_error (_("constant expression required"));
1432 if (skip_past_char (&str
, ']') == FAIL
)
1435 atype
.index
= exp
.X_add_number
;
1450 /* Like arm_reg_parse, but allow allow the following extra features:
1451 - If RTYPE is non-zero, return the (possibly restricted) type of the
1452 register (e.g. Neon double or quad reg when either has been requested).
1453 - If this is a Neon vector type with additional type information, fill
1454 in the struct pointed to by VECTYPE (if non-NULL).
1455 This function will fault on encountering a scalar. */
1458 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1459 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1461 struct neon_typed_alias atype
;
1463 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1468 /* Do not allow a scalar (reg+index) to parse as a register. */
1469 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1471 first_error (_("register operand expected, but got scalar"));
1476 *vectype
= atype
.eltype
;
1483 #define NEON_SCALAR_REG(X) ((X) >> 4)
1484 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1486 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1487 have enough information to be able to do a good job bounds-checking. So, we
1488 just do easy checks here, and do further checks later. */
1491 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1495 struct neon_typed_alias atype
;
1497 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1499 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1502 if (atype
.index
== NEON_ALL_LANES
)
1504 first_error (_("scalar must have an index"));
1507 else if (atype
.index
>= 64 / elsize
)
1509 first_error (_("scalar index out of range"));
1514 *type
= atype
.eltype
;
1518 return reg
* 16 + atype
.index
;
1521 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1524 parse_reg_list (char ** strp
)
1526 char * str
= * strp
;
1530 /* We come back here if we get ranges concatenated by '+' or '|'. */
1545 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1547 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1557 first_error (_("bad range in register list"));
1561 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1563 if (range
& (1 << i
))
1565 (_("Warning: duplicated register (r%d) in register list"),
1573 if (range
& (1 << reg
))
1574 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1576 else if (reg
<= cur_reg
)
1577 as_tsktsk (_("Warning: register range not in ascending order"));
1582 while (skip_past_comma (&str
) != FAIL
1583 || (in_range
= 1, *str
++ == '-'));
1588 first_error (_("missing `}'"));
1596 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1599 if (exp
.X_op
== O_constant
)
1601 if (exp
.X_add_number
1602 != (exp
.X_add_number
& 0x0000ffff))
1604 inst
.error
= _("invalid register mask");
1608 if ((range
& exp
.X_add_number
) != 0)
1610 int regno
= range
& exp
.X_add_number
;
1613 regno
= (1 << regno
) - 1;
1615 (_("Warning: duplicated register (r%d) in register list"),
1619 range
|= exp
.X_add_number
;
1623 if (inst
.reloc
.type
!= 0)
1625 inst
.error
= _("expression too complex");
1629 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1630 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1631 inst
.reloc
.pc_rel
= 0;
1635 if (*str
== '|' || *str
== '+')
1641 while (another_range
);
1647 /* Types of registers in a list. */
1656 /* Parse a VFP register list. If the string is invalid return FAIL.
1657 Otherwise return the number of registers, and set PBASE to the first
1658 register. Parses registers of type ETYPE.
1659 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1660 - Q registers can be used to specify pairs of D registers
1661 - { } can be omitted from around a singleton register list
1662 FIXME: This is not implemented, as it would require backtracking in
1665 This could be done (the meaning isn't really ambiguous), but doesn't
1666 fit in well with the current parsing framework.
1667 - 32 D registers may be used (also true for VFPv3).
1668 FIXME: Types are ignored in these register lists, which is probably a
1672 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1677 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1681 unsigned long mask
= 0;
1686 inst
.error
= _("expecting {");
1695 regtype
= REG_TYPE_VFS
;
1700 regtype
= REG_TYPE_VFD
;
1703 case REGLIST_NEON_D
:
1704 regtype
= REG_TYPE_NDQ
;
1708 if (etype
!= REGLIST_VFP_S
)
1710 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1711 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1715 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1718 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1725 base_reg
= max_regs
;
1729 int setmask
= 1, addregs
= 1;
1731 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1733 if (new_base
== FAIL
)
1735 first_error (_(reg_expected_msgs
[regtype
]));
1739 if (new_base
>= max_regs
)
1741 first_error (_("register out of range in list"));
1745 /* Note: a value of 2 * n is returned for the register Q<n>. */
1746 if (regtype
== REG_TYPE_NQ
)
1752 if (new_base
< base_reg
)
1753 base_reg
= new_base
;
1755 if (mask
& (setmask
<< new_base
))
1757 first_error (_("invalid register list"));
1761 if ((mask
>> new_base
) != 0 && ! warned
)
1763 as_tsktsk (_("register list not in ascending order"));
1767 mask
|= setmask
<< new_base
;
1770 if (*str
== '-') /* We have the start of a range expression */
1776 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1779 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1783 if (high_range
>= max_regs
)
1785 first_error (_("register out of range in list"));
1789 if (regtype
== REG_TYPE_NQ
)
1790 high_range
= high_range
+ 1;
1792 if (high_range
<= new_base
)
1794 inst
.error
= _("register range not in ascending order");
1798 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1800 if (mask
& (setmask
<< new_base
))
1802 inst
.error
= _("invalid register list");
1806 mask
|= setmask
<< new_base
;
1811 while (skip_past_comma (&str
) != FAIL
);
1815 /* Sanity check -- should have raised a parse error above. */
1816 if (count
== 0 || count
> max_regs
)
1821 /* Final test -- the registers must be consecutive. */
1823 for (i
= 0; i
< count
; i
++)
1825 if ((mask
& (1u << i
)) == 0)
1827 inst
.error
= _("non-contiguous register range");
1837 /* True if two alias types are the same. */
1840 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1848 if (a
->defined
!= b
->defined
)
1851 if ((a
->defined
& NTA_HASTYPE
) != 0
1852 && (a
->eltype
.type
!= b
->eltype
.type
1853 || a
->eltype
.size
!= b
->eltype
.size
))
1856 if ((a
->defined
& NTA_HASINDEX
) != 0
1857 && (a
->index
!= b
->index
))
1863 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1864 The base register is put in *PBASE.
1865 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1867 The register stride (minus one) is put in bit 4 of the return value.
1868 Bits [6:5] encode the list length (minus one).
1869 The type of the list elements is put in *ELTYPE, if non-NULL. */
1871 #define NEON_LANE(X) ((X) & 0xf)
1872 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1873 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1876 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1877 struct neon_type_el
*eltype
)
1884 int leading_brace
= 0;
1885 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1886 const char *const incr_error
= _("register stride must be 1 or 2");
1887 const char *const type_error
= _("mismatched element/structure types in list");
1888 struct neon_typed_alias firsttype
;
1890 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1895 struct neon_typed_alias atype
;
1896 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1900 first_error (_(reg_expected_msgs
[rtype
]));
1907 if (rtype
== REG_TYPE_NQ
)
1913 else if (reg_incr
== -1)
1915 reg_incr
= getreg
- base_reg
;
1916 if (reg_incr
< 1 || reg_incr
> 2)
1918 first_error (_(incr_error
));
1922 else if (getreg
!= base_reg
+ reg_incr
* count
)
1924 first_error (_(incr_error
));
1928 if (! neon_alias_types_same (&atype
, &firsttype
))
1930 first_error (_(type_error
));
1934 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1938 struct neon_typed_alias htype
;
1939 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1941 lane
= NEON_INTERLEAVE_LANES
;
1942 else if (lane
!= NEON_INTERLEAVE_LANES
)
1944 first_error (_(type_error
));
1949 else if (reg_incr
!= 1)
1951 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1955 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1958 first_error (_(reg_expected_msgs
[rtype
]));
1961 if (! neon_alias_types_same (&htype
, &firsttype
))
1963 first_error (_(type_error
));
1966 count
+= hireg
+ dregs
- getreg
;
1970 /* If we're using Q registers, we can't use [] or [n] syntax. */
1971 if (rtype
== REG_TYPE_NQ
)
1977 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1981 else if (lane
!= atype
.index
)
1983 first_error (_(type_error
));
1987 else if (lane
== -1)
1988 lane
= NEON_INTERLEAVE_LANES
;
1989 else if (lane
!= NEON_INTERLEAVE_LANES
)
1991 first_error (_(type_error
));
1996 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1998 /* No lane set by [x]. We must be interleaving structures. */
2000 lane
= NEON_INTERLEAVE_LANES
;
2003 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2004 || (count
> 1 && reg_incr
== -1))
2006 first_error (_("error parsing element/structure list"));
2010 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2012 first_error (_("expected }"));
2020 *eltype
= firsttype
.eltype
;
2025 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2028 /* Parse an explicit relocation suffix on an expression. This is
2029 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2030 arm_reloc_hsh contains no entries, so this function can only
2031 succeed if there is no () after the word. Returns -1 on error,
2032 BFD_RELOC_UNUSED if there wasn't any suffix. */
2034 parse_reloc (char **str
)
2036 struct reloc_entry
*r
;
2040 return BFD_RELOC_UNUSED
;
2045 while (*q
&& *q
!= ')' && *q
!= ',')
2050 if ((r
= (struct reloc_entry
*)
2051 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2058 /* Directives: register aliases. */
2060 static struct reg_entry
*
2061 insert_reg_alias (char *str
, int number
, int type
)
2063 struct reg_entry
*new_reg
;
2066 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2068 if (new_reg
->builtin
)
2069 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2071 /* Only warn about a redefinition if it's not defined as the
2073 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2074 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2079 name
= xstrdup (str
);
2080 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2082 new_reg
->name
= name
;
2083 new_reg
->number
= number
;
2084 new_reg
->type
= type
;
2085 new_reg
->builtin
= FALSE
;
2086 new_reg
->neon
= NULL
;
2088 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2095 insert_neon_reg_alias (char *str
, int number
, int type
,
2096 struct neon_typed_alias
*atype
)
2098 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2102 first_error (_("attempt to redefine typed alias"));
2108 reg
->neon
= (struct neon_typed_alias
*)
2109 xmalloc (sizeof (struct neon_typed_alias
));
2110 *reg
->neon
= *atype
;
2114 /* Look for the .req directive. This is of the form:
2116 new_register_name .req existing_register_name
2118 If we find one, or if it looks sufficiently like one that we want to
2119 handle any error here, return TRUE. Otherwise return FALSE. */
2122 create_register_alias (char * newname
, char *p
)
2124 struct reg_entry
*old
;
2125 char *oldname
, *nbuf
;
2128 /* The input scrubber ensures that whitespace after the mnemonic is
2129 collapsed to single spaces. */
2131 if (strncmp (oldname
, " .req ", 6) != 0)
2135 if (*oldname
== '\0')
2138 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2141 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2145 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2146 the desired alias name, and p points to its end. If not, then
2147 the desired alias name is in the global original_case_string. */
2148 #ifdef TC_CASE_SENSITIVE
2151 newname
= original_case_string
;
2152 nlen
= strlen (newname
);
2155 nbuf
= (char *) alloca (nlen
+ 1);
2156 memcpy (nbuf
, newname
, nlen
);
2159 /* Create aliases under the new name as stated; an all-lowercase
2160 version of the new name; and an all-uppercase version of the new
2162 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2164 for (p
= nbuf
; *p
; p
++)
2167 if (strncmp (nbuf
, newname
, nlen
))
2169 /* If this attempt to create an additional alias fails, do not bother
2170 trying to create the all-lower case alias. We will fail and issue
2171 a second, duplicate error message. This situation arises when the
2172 programmer does something like:
2175 The second .req creates the "Foo" alias but then fails to create
2176 the artificial FOO alias because it has already been created by the
2178 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2182 for (p
= nbuf
; *p
; p
++)
2185 if (strncmp (nbuf
, newname
, nlen
))
2186 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2192 /* Create a Neon typed/indexed register alias using directives, e.g.:
2197 These typed registers can be used instead of the types specified after the
2198 Neon mnemonic, so long as all operands given have types. Types can also be
2199 specified directly, e.g.:
2200 vadd d0.s32, d1.s32, d2.s32 */
2203 create_neon_reg_alias (char *newname
, char *p
)
2205 enum arm_reg_type basetype
;
2206 struct reg_entry
*basereg
;
2207 struct reg_entry mybasereg
;
2208 struct neon_type ntype
;
2209 struct neon_typed_alias typeinfo
;
2210 char *namebuf
, *nameend
;
2213 typeinfo
.defined
= 0;
2214 typeinfo
.eltype
.type
= NT_invtype
;
2215 typeinfo
.eltype
.size
= -1;
2216 typeinfo
.index
= -1;
2220 if (strncmp (p
, " .dn ", 5) == 0)
2221 basetype
= REG_TYPE_VFD
;
2222 else if (strncmp (p
, " .qn ", 5) == 0)
2223 basetype
= REG_TYPE_NQ
;
2232 basereg
= arm_reg_parse_multi (&p
);
2234 if (basereg
&& basereg
->type
!= basetype
)
2236 as_bad (_("bad type for register"));
2240 if (basereg
== NULL
)
2243 /* Try parsing as an integer. */
2244 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2245 if (exp
.X_op
!= O_constant
)
2247 as_bad (_("expression must be constant"));
2250 basereg
= &mybasereg
;
2251 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2257 typeinfo
= *basereg
->neon
;
2259 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2261 /* We got a type. */
2262 if (typeinfo
.defined
& NTA_HASTYPE
)
2264 as_bad (_("can't redefine the type of a register alias"));
2268 typeinfo
.defined
|= NTA_HASTYPE
;
2269 if (ntype
.elems
!= 1)
2271 as_bad (_("you must specify a single type only"));
2274 typeinfo
.eltype
= ntype
.el
[0];
2277 if (skip_past_char (&p
, '[') == SUCCESS
)
2280 /* We got a scalar index. */
2282 if (typeinfo
.defined
& NTA_HASINDEX
)
2284 as_bad (_("can't redefine the index of a scalar alias"));
2288 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2290 if (exp
.X_op
!= O_constant
)
2292 as_bad (_("scalar index must be constant"));
2296 typeinfo
.defined
|= NTA_HASINDEX
;
2297 typeinfo
.index
= exp
.X_add_number
;
2299 if (skip_past_char (&p
, ']') == FAIL
)
2301 as_bad (_("expecting ]"));
2306 namelen
= nameend
- newname
;
2307 namebuf
= (char *) alloca (namelen
+ 1);
2308 strncpy (namebuf
, newname
, namelen
);
2309 namebuf
[namelen
] = '\0';
2311 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2312 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2314 /* Insert name in all uppercase. */
2315 for (p
= namebuf
; *p
; p
++)
2318 if (strncmp (namebuf
, newname
, namelen
))
2319 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2320 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2322 /* Insert name in all lowercase. */
2323 for (p
= namebuf
; *p
; p
++)
2326 if (strncmp (namebuf
, newname
, namelen
))
2327 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2328 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2333 /* Should never be called, as .req goes between the alias and the
2334 register name, not at the beginning of the line. */
2337 s_req (int a ATTRIBUTE_UNUSED
)
2339 as_bad (_("invalid syntax for .req directive"));
2343 s_dn (int a ATTRIBUTE_UNUSED
)
2345 as_bad (_("invalid syntax for .dn directive"));
2349 s_qn (int a ATTRIBUTE_UNUSED
)
2351 as_bad (_("invalid syntax for .qn directive"));
2354 /* The .unreq directive deletes an alias which was previously defined
2355 by .req. For example:
2361 s_unreq (int a ATTRIBUTE_UNUSED
)
2366 name
= input_line_pointer
;
2368 while (*input_line_pointer
!= 0
2369 && *input_line_pointer
!= ' '
2370 && *input_line_pointer
!= '\n')
2371 ++input_line_pointer
;
2373 saved_char
= *input_line_pointer
;
2374 *input_line_pointer
= 0;
2377 as_bad (_("invalid syntax for .unreq directive"));
2380 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2384 as_bad (_("unknown register alias '%s'"), name
);
2385 else if (reg
->builtin
)
2386 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2393 hash_delete (arm_reg_hsh
, name
, FALSE
);
2394 free ((char *) reg
->name
);
2399 /* Also locate the all upper case and all lower case versions.
2400 Do not complain if we cannot find one or the other as it
2401 was probably deleted above. */
2403 nbuf
= strdup (name
);
2404 for (p
= nbuf
; *p
; p
++)
2406 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2409 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2410 free ((char *) reg
->name
);
2416 for (p
= nbuf
; *p
; p
++)
2418 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2421 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2422 free ((char *) reg
->name
);
2432 *input_line_pointer
= saved_char
;
2433 demand_empty_rest_of_line ();
2436 /* Directives: Instruction set selection. */
2439 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2440 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2441 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2442 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2444 /* Create a new mapping symbol for the transition to STATE. */
2447 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2450 const char * symname
;
2457 type
= BSF_NO_FLAGS
;
2461 type
= BSF_NO_FLAGS
;
2465 type
= BSF_NO_FLAGS
;
2471 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2472 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2477 THUMB_SET_FUNC (symbolP
, 0);
2478 ARM_SET_THUMB (symbolP
, 0);
2479 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2483 THUMB_SET_FUNC (symbolP
, 1);
2484 ARM_SET_THUMB (symbolP
, 1);
2485 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2493 /* Save the mapping symbols for future reference. Also check that
2494 we do not place two mapping symbols at the same offset within a
2495 frag. We'll handle overlap between frags in
2496 check_mapping_symbols.
2498 If .fill or other data filling directive generates zero sized data,
2499 the mapping symbol for the following code will have the same value
2500 as the one generated for the data filling directive. In this case,
2501 we replace the old symbol with the new one at the same address. */
2504 if (frag
->tc_frag_data
.first_map
!= NULL
)
2506 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2507 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2509 frag
->tc_frag_data
.first_map
= symbolP
;
2511 if (frag
->tc_frag_data
.last_map
!= NULL
)
2513 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2514 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2515 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2517 frag
->tc_frag_data
.last_map
= symbolP
;
2520 /* We must sometimes convert a region marked as code to data during
2521 code alignment, if an odd number of bytes have to be padded. The
2522 code mapping symbol is pushed to an aligned address. */
2525 insert_data_mapping_symbol (enum mstate state
,
2526 valueT value
, fragS
*frag
, offsetT bytes
)
2528 /* If there was already a mapping symbol, remove it. */
2529 if (frag
->tc_frag_data
.last_map
!= NULL
2530 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2532 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2536 know (frag
->tc_frag_data
.first_map
== symp
);
2537 frag
->tc_frag_data
.first_map
= NULL
;
2539 frag
->tc_frag_data
.last_map
= NULL
;
2540 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2543 make_mapping_symbol (MAP_DATA
, value
, frag
);
2544 make_mapping_symbol (state
, value
+ bytes
, frag
);
2547 static void mapping_state_2 (enum mstate state
, int max_chars
);
2549 /* Set the mapping state to STATE. Only call this when about to
2550 emit some STATE bytes to the file. */
2553 mapping_state (enum mstate state
)
2555 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2557 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2559 if (mapstate
== state
)
2560 /* The mapping symbol has already been emitted.
2561 There is nothing else to do. */
2563 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2564 /* This case will be evaluated later in the next else. */
2566 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2567 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2569 /* Only add the symbol if the offset is > 0:
2570 if we're at the first frag, check it's size > 0;
2571 if we're not at the first frag, then for sure
2572 the offset is > 0. */
2573 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2574 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2577 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2580 mapping_state_2 (state
, 0);
2584 /* Same as mapping_state, but MAX_CHARS bytes have already been
2585 allocated. Put the mapping symbol that far back. */
2588 mapping_state_2 (enum mstate state
, int max_chars
)
2590 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2592 if (!SEG_NORMAL (now_seg
))
2595 if (mapstate
== state
)
2596 /* The mapping symbol has already been emitted.
2597 There is nothing else to do. */
2600 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2601 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2604 #define mapping_state(x) ((void)0)
2605 #define mapping_state_2(x, y) ((void)0)
2608 /* Find the real, Thumb encoded start of a Thumb function. */
2612 find_real_start (symbolS
* symbolP
)
2615 const char * name
= S_GET_NAME (symbolP
);
2616 symbolS
* new_target
;
2618 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2619 #define STUB_NAME ".real_start_of"
2624 /* The compiler may generate BL instructions to local labels because
2625 it needs to perform a branch to a far away location. These labels
2626 do not have a corresponding ".real_start_of" label. We check
2627 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2628 the ".real_start_of" convention for nonlocal branches. */
2629 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2632 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2633 new_target
= symbol_find (real_start
);
2635 if (new_target
== NULL
)
2637 as_warn (_("Failed to find real start of function: %s\n"), name
);
2638 new_target
= symbolP
;
2646 opcode_select (int width
)
2653 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2654 as_bad (_("selected processor does not support THUMB opcodes"));
2657 /* No need to force the alignment, since we will have been
2658 coming from ARM mode, which is word-aligned. */
2659 record_alignment (now_seg
, 1);
2666 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2667 as_bad (_("selected processor does not support ARM opcodes"));
2672 frag_align (2, 0, 0);
2674 record_alignment (now_seg
, 1);
2679 as_bad (_("invalid instruction size selected (%d)"), width
);
2684 s_arm (int ignore ATTRIBUTE_UNUSED
)
2687 demand_empty_rest_of_line ();
2691 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2694 demand_empty_rest_of_line ();
2698 s_code (int unused ATTRIBUTE_UNUSED
)
2702 temp
= get_absolute_expression ();
2707 opcode_select (temp
);
2711 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2716 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2718 /* If we are not already in thumb mode go into it, EVEN if
2719 the target processor does not support thumb instructions.
2720 This is used by gcc/config/arm/lib1funcs.asm for example
2721 to compile interworking support functions even if the
2722 target processor should not support interworking. */
2726 record_alignment (now_seg
, 1);
2729 demand_empty_rest_of_line ();
2733 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2737 /* The following label is the name/address of the start of a Thumb function.
2738 We need to know this for the interworking support. */
2739 label_is_thumb_function_name
= TRUE
;
2742 /* Perform a .set directive, but also mark the alias as
2743 being a thumb function. */
2746 s_thumb_set (int equiv
)
2748 /* XXX the following is a duplicate of the code for s_set() in read.c
2749 We cannot just call that code as we need to get at the symbol that
2756 /* Especial apologies for the random logic:
2757 This just grew, and could be parsed much more simply!
2759 name
= input_line_pointer
;
2760 delim
= get_symbol_end ();
2761 end_name
= input_line_pointer
;
2764 if (*input_line_pointer
!= ',')
2767 as_bad (_("expected comma after name \"%s\""), name
);
2769 ignore_rest_of_line ();
2773 input_line_pointer
++;
2776 if (name
[0] == '.' && name
[1] == '\0')
2778 /* XXX - this should not happen to .thumb_set. */
2782 if ((symbolP
= symbol_find (name
)) == NULL
2783 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2786 /* When doing symbol listings, play games with dummy fragments living
2787 outside the normal fragment chain to record the file and line info
2789 if (listing
& LISTING_SYMBOLS
)
2791 extern struct list_info_struct
* listing_tail
;
2792 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2794 memset (dummy_frag
, 0, sizeof (fragS
));
2795 dummy_frag
->fr_type
= rs_fill
;
2796 dummy_frag
->line
= listing_tail
;
2797 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2798 dummy_frag
->fr_symbol
= symbolP
;
2802 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2805 /* "set" symbols are local unless otherwise specified. */
2806 SF_SET_LOCAL (symbolP
);
2807 #endif /* OBJ_COFF */
2808 } /* Make a new symbol. */
2810 symbol_table_insert (symbolP
);
2815 && S_IS_DEFINED (symbolP
)
2816 && S_GET_SEGMENT (symbolP
) != reg_section
)
2817 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2819 pseudo_set (symbolP
);
2821 demand_empty_rest_of_line ();
2823 /* XXX Now we come to the Thumb specific bit of code. */
2825 THUMB_SET_FUNC (symbolP
, 1);
2826 ARM_SET_THUMB (symbolP
, 1);
2827 #if defined OBJ_ELF || defined OBJ_COFF
2828 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2832 /* Directives: Mode selection. */
2834 /* .syntax [unified|divided] - choose the new unified syntax
2835 (same for Arm and Thumb encoding, modulo slight differences in what
2836 can be represented) or the old divergent syntax for each mode. */
2838 s_syntax (int unused ATTRIBUTE_UNUSED
)
2842 name
= input_line_pointer
;
2843 delim
= get_symbol_end ();
2845 if (!strcasecmp (name
, "unified"))
2846 unified_syntax
= TRUE
;
2847 else if (!strcasecmp (name
, "divided"))
2848 unified_syntax
= FALSE
;
2851 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2854 *input_line_pointer
= delim
;
2855 demand_empty_rest_of_line ();
2858 /* Directives: sectioning and alignment. */
2860 /* Same as s_align_ptwo but align 0 => align 2. */
2863 s_align (int unused ATTRIBUTE_UNUSED
)
2868 long max_alignment
= 15;
2870 temp
= get_absolute_expression ();
2871 if (temp
> max_alignment
)
2872 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2875 as_bad (_("alignment negative. 0 assumed."));
2879 if (*input_line_pointer
== ',')
2881 input_line_pointer
++;
2882 temp_fill
= get_absolute_expression ();
2894 /* Only make a frag if we HAVE to. */
2895 if (temp
&& !need_pass_2
)
2897 if (!fill_p
&& subseg_text_p (now_seg
))
2898 frag_align_code (temp
, 0);
2900 frag_align (temp
, (int) temp_fill
, 0);
2902 demand_empty_rest_of_line ();
2904 record_alignment (now_seg
, temp
);
2908 s_bss (int ignore ATTRIBUTE_UNUSED
)
2910 /* We don't support putting frags in the BSS segment, we fake it by
2911 marking in_bss, then looking at s_skip for clues. */
2912 subseg_set (bss_section
, 0);
2913 demand_empty_rest_of_line ();
2915 #ifdef md_elf_section_change_hook
2916 md_elf_section_change_hook ();
2921 s_even (int ignore ATTRIBUTE_UNUSED
)
2923 /* Never make frag if expect extra pass. */
2925 frag_align (1, 0, 0);
2927 record_alignment (now_seg
, 1);
2929 demand_empty_rest_of_line ();
2932 /* Directives: Literal pools. */
2934 static literal_pool
*
2935 find_literal_pool (void)
2937 literal_pool
* pool
;
2939 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2941 if (pool
->section
== now_seg
2942 && pool
->sub_section
== now_subseg
)
2949 static literal_pool
*
2950 find_or_make_literal_pool (void)
2952 /* Next literal pool ID number. */
2953 static unsigned int latest_pool_num
= 1;
2954 literal_pool
* pool
;
2956 pool
= find_literal_pool ();
2960 /* Create a new pool. */
2961 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2965 pool
->next_free_entry
= 0;
2966 pool
->section
= now_seg
;
2967 pool
->sub_section
= now_subseg
;
2968 pool
->next
= list_of_pools
;
2969 pool
->symbol
= NULL
;
2971 /* Add it to the list. */
2972 list_of_pools
= pool
;
2975 /* New pools, and emptied pools, will have a NULL symbol. */
2976 if (pool
->symbol
== NULL
)
2978 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2979 (valueT
) 0, &zero_address_frag
);
2980 pool
->id
= latest_pool_num
++;
2987 /* Add the literal in the global 'inst'
2988 structure to the relevant literal pool. */
2991 add_to_lit_pool (void)
2993 literal_pool
* pool
;
2996 pool
= find_or_make_literal_pool ();
2998 /* Check if this literal value is already in the pool. */
2999 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3001 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3002 && (inst
.reloc
.exp
.X_op
== O_constant
)
3003 && (pool
->literals
[entry
].X_add_number
3004 == inst
.reloc
.exp
.X_add_number
)
3005 && (pool
->literals
[entry
].X_unsigned
3006 == inst
.reloc
.exp
.X_unsigned
))
3009 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3010 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3011 && (pool
->literals
[entry
].X_add_number
3012 == inst
.reloc
.exp
.X_add_number
)
3013 && (pool
->literals
[entry
].X_add_symbol
3014 == inst
.reloc
.exp
.X_add_symbol
)
3015 && (pool
->literals
[entry
].X_op_symbol
3016 == inst
.reloc
.exp
.X_op_symbol
))
3020 /* Do we need to create a new entry? */
3021 if (entry
== pool
->next_free_entry
)
3023 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3025 inst
.error
= _("literal pool overflow");
3029 pool
->literals
[entry
] = inst
.reloc
.exp
;
3030 pool
->next_free_entry
+= 1;
3033 inst
.reloc
.exp
.X_op
= O_symbol
;
3034 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3035 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3040 /* Can't use symbol_new here, so have to create a symbol and then at
3041 a later date assign it a value. Thats what these functions do. */
3044 symbol_locate (symbolS
* symbolP
,
3045 const char * name
, /* It is copied, the caller can modify. */
3046 segT segment
, /* Segment identifier (SEG_<something>). */
3047 valueT valu
, /* Symbol value. */
3048 fragS
* frag
) /* Associated fragment. */
3050 unsigned int name_length
;
3051 char * preserved_copy_of_name
;
3053 name_length
= strlen (name
) + 1; /* +1 for \0. */
3054 obstack_grow (¬es
, name
, name_length
);
3055 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3057 #ifdef tc_canonicalize_symbol_name
3058 preserved_copy_of_name
=
3059 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3062 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3064 S_SET_SEGMENT (symbolP
, segment
);
3065 S_SET_VALUE (symbolP
, valu
);
3066 symbol_clear_list_pointers (symbolP
);
3068 symbol_set_frag (symbolP
, frag
);
3070 /* Link to end of symbol chain. */
3072 extern int symbol_table_frozen
;
3074 if (symbol_table_frozen
)
3078 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3080 obj_symbol_new_hook (symbolP
);
3082 #ifdef tc_symbol_new_hook
3083 tc_symbol_new_hook (symbolP
);
3087 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3088 #endif /* DEBUG_SYMS */
3093 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3096 literal_pool
* pool
;
3099 pool
= find_literal_pool ();
3101 || pool
->symbol
== NULL
3102 || pool
->next_free_entry
== 0)
3105 mapping_state (MAP_DATA
);
3107 /* Align pool as you have word accesses.
3108 Only make a frag if we have to. */
3110 frag_align (2, 0, 0);
3112 record_alignment (now_seg
, 2);
3114 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3116 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3117 (valueT
) frag_now_fix (), frag_now
);
3118 symbol_table_insert (pool
->symbol
);
3120 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3122 #if defined OBJ_COFF || defined OBJ_ELF
3123 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3126 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3127 /* First output the expression in the instruction to the pool. */
3128 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3130 /* Mark the pool as empty. */
3131 pool
->next_free_entry
= 0;
3132 pool
->symbol
= NULL
;
3136 /* Forward declarations for functions below, in the MD interface
3138 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3139 static valueT
create_unwind_entry (int);
3140 static void start_unwind_section (const segT
, int);
3141 static void add_unwind_opcode (valueT
, int);
3142 static void flush_pending_unwind (void);
3144 /* Directives: Data. */
3147 s_arm_elf_cons (int nbytes
)
3151 #ifdef md_flush_pending_output
3152 md_flush_pending_output ();
3155 if (is_it_end_of_statement ())
3157 demand_empty_rest_of_line ();
3161 #ifdef md_cons_align
3162 md_cons_align (nbytes
);
3165 mapping_state (MAP_DATA
);
3169 char *base
= input_line_pointer
;
3173 if (exp
.X_op
!= O_symbol
)
3174 emit_expr (&exp
, (unsigned int) nbytes
);
3177 char *before_reloc
= input_line_pointer
;
3178 reloc
= parse_reloc (&input_line_pointer
);
3181 as_bad (_("unrecognized relocation suffix"));
3182 ignore_rest_of_line ();
3185 else if (reloc
== BFD_RELOC_UNUSED
)
3186 emit_expr (&exp
, (unsigned int) nbytes
);
3189 reloc_howto_type
*howto
= (reloc_howto_type
*)
3190 bfd_reloc_type_lookup (stdoutput
,
3191 (bfd_reloc_code_real_type
) reloc
);
3192 int size
= bfd_get_reloc_size (howto
);
3194 if (reloc
== BFD_RELOC_ARM_PLT32
)
3196 as_bad (_("(plt) is only valid on branch targets"));
3197 reloc
= BFD_RELOC_UNUSED
;
3202 as_bad (_("%s relocations do not fit in %d bytes"),
3203 howto
->name
, nbytes
);
3206 /* We've parsed an expression stopping at O_symbol.
3207 But there may be more expression left now that we
3208 have parsed the relocation marker. Parse it again.
3209 XXX Surely there is a cleaner way to do this. */
3210 char *p
= input_line_pointer
;
3212 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3213 memcpy (save_buf
, base
, input_line_pointer
- base
);
3214 memmove (base
+ (input_line_pointer
- before_reloc
),
3215 base
, before_reloc
- base
);
3217 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3219 memcpy (base
, save_buf
, p
- base
);
3221 offset
= nbytes
- size
;
3222 p
= frag_more ((int) nbytes
);
3223 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3224 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3229 while (*input_line_pointer
++ == ',');
3231 /* Put terminator back into stream. */
3232 input_line_pointer
--;
3233 demand_empty_rest_of_line ();
3236 /* Emit an expression containing a 32-bit thumb instruction.
3237 Implementation based on put_thumb32_insn. */
3240 emit_thumb32_expr (expressionS
* exp
)
3242 expressionS exp_high
= *exp
;
3244 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3245 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3246 exp
->X_add_number
&= 0xffff;
3247 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3250 /* Guess the instruction size based on the opcode. */
3253 thumb_insn_size (int opcode
)
3255 if ((unsigned int) opcode
< 0xe800u
)
3257 else if ((unsigned int) opcode
>= 0xe8000000u
)
3264 emit_insn (expressionS
*exp
, int nbytes
)
3268 if (exp
->X_op
== O_constant
)
3273 size
= thumb_insn_size (exp
->X_add_number
);
3277 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3279 as_bad (_(".inst.n operand too big. "\
3280 "Use .inst.w instead"));
3285 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3286 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3288 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3290 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3291 emit_thumb32_expr (exp
);
3293 emit_expr (exp
, (unsigned int) size
);
3295 it_fsm_post_encode ();
3299 as_bad (_("cannot determine Thumb instruction size. " \
3300 "Use .inst.n/.inst.w instead"));
3303 as_bad (_("constant expression required"));
3308 /* Like s_arm_elf_cons but do not use md_cons_align and
3309 set the mapping state to MAP_ARM/MAP_THUMB. */
3312 s_arm_elf_inst (int nbytes
)
3314 if (is_it_end_of_statement ())
3316 demand_empty_rest_of_line ();
3320 /* Calling mapping_state () here will not change ARM/THUMB,
3321 but will ensure not to be in DATA state. */
3324 mapping_state (MAP_THUMB
);
3329 as_bad (_("width suffixes are invalid in ARM mode"));
3330 ignore_rest_of_line ();
3336 mapping_state (MAP_ARM
);
3345 if (! emit_insn (& exp
, nbytes
))
3347 ignore_rest_of_line ();
3351 while (*input_line_pointer
++ == ',');
3353 /* Put terminator back into stream. */
3354 input_line_pointer
--;
3355 demand_empty_rest_of_line ();
3358 /* Parse a .rel31 directive. */
3361 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3368 if (*input_line_pointer
== '1')
3369 highbit
= 0x80000000;
3370 else if (*input_line_pointer
!= '0')
3371 as_bad (_("expected 0 or 1"));
3373 input_line_pointer
++;
3374 if (*input_line_pointer
!= ',')
3375 as_bad (_("missing comma"));
3376 input_line_pointer
++;
3378 #ifdef md_flush_pending_output
3379 md_flush_pending_output ();
3382 #ifdef md_cons_align
3386 mapping_state (MAP_DATA
);
3391 md_number_to_chars (p
, highbit
, 4);
3392 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3393 BFD_RELOC_ARM_PREL31
);
3395 demand_empty_rest_of_line ();
3398 /* Directives: AEABI stack-unwind tables. */
3400 /* Parse an unwind_fnstart directive. Simply records the current location. */
3403 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3405 demand_empty_rest_of_line ();
3406 if (unwind
.proc_start
)
3408 as_bad (_("duplicate .fnstart directive"));
3412 /* Mark the start of the function. */
3413 unwind
.proc_start
= expr_build_dot ();
3415 /* Reset the rest of the unwind info. */
3416 unwind
.opcode_count
= 0;
3417 unwind
.table_entry
= NULL
;
3418 unwind
.personality_routine
= NULL
;
3419 unwind
.personality_index
= -1;
3420 unwind
.frame_size
= 0;
3421 unwind
.fp_offset
= 0;
3422 unwind
.fp_reg
= REG_SP
;
3424 unwind
.sp_restored
= 0;
3428 /* Parse a handlerdata directive. Creates the exception handling table entry
3429 for the function. */
3432 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3434 demand_empty_rest_of_line ();
3435 if (!unwind
.proc_start
)
3436 as_bad (MISSING_FNSTART
);
3438 if (unwind
.table_entry
)
3439 as_bad (_("duplicate .handlerdata directive"));
3441 create_unwind_entry (1);
3444 /* Parse an unwind_fnend directive. Generates the index table entry. */
3447 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3452 unsigned int marked_pr_dependency
;
3454 demand_empty_rest_of_line ();
3456 if (!unwind
.proc_start
)
3458 as_bad (_(".fnend directive without .fnstart"));
3462 /* Add eh table entry. */
3463 if (unwind
.table_entry
== NULL
)
3464 val
= create_unwind_entry (0);
3468 /* Add index table entry. This is two words. */
3469 start_unwind_section (unwind
.saved_seg
, 1);
3470 frag_align (2, 0, 0);
3471 record_alignment (now_seg
, 2);
3473 ptr
= frag_more (8);
3474 where
= frag_now_fix () - 8;
3476 /* Self relative offset of the function start. */
3477 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3478 BFD_RELOC_ARM_PREL31
);
3480 /* Indicate dependency on EHABI-defined personality routines to the
3481 linker, if it hasn't been done already. */
3482 marked_pr_dependency
3483 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3484 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3485 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3487 static const char *const name
[] =
3489 "__aeabi_unwind_cpp_pr0",
3490 "__aeabi_unwind_cpp_pr1",
3491 "__aeabi_unwind_cpp_pr2"
3493 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3494 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3495 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3496 |= 1 << unwind
.personality_index
;
3500 /* Inline exception table entry. */
3501 md_number_to_chars (ptr
+ 4, val
, 4);
3503 /* Self relative offset of the table entry. */
3504 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3505 BFD_RELOC_ARM_PREL31
);
3507 /* Restore the original section. */
3508 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3510 unwind
.proc_start
= NULL
;
3514 /* Parse an unwind_cantunwind directive. */
3517 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3519 demand_empty_rest_of_line ();
3520 if (!unwind
.proc_start
)
3521 as_bad (MISSING_FNSTART
);
3523 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3524 as_bad (_("personality routine specified for cantunwind frame"));
3526 unwind
.personality_index
= -2;
3530 /* Parse a personalityindex directive. */
3533 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3537 if (!unwind
.proc_start
)
3538 as_bad (MISSING_FNSTART
);
3540 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3541 as_bad (_("duplicate .personalityindex directive"));
3545 if (exp
.X_op
!= O_constant
3546 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3548 as_bad (_("bad personality routine number"));
3549 ignore_rest_of_line ();
3553 unwind
.personality_index
= exp
.X_add_number
;
3555 demand_empty_rest_of_line ();
3559 /* Parse a personality directive. */
3562 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3566 if (!unwind
.proc_start
)
3567 as_bad (MISSING_FNSTART
);
3569 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3570 as_bad (_("duplicate .personality directive"));
3572 name
= input_line_pointer
;
3573 c
= get_symbol_end ();
3574 p
= input_line_pointer
;
3575 unwind
.personality_routine
= symbol_find_or_make (name
);
3577 demand_empty_rest_of_line ();
3581 /* Parse a directive saving core registers. */
3584 s_arm_unwind_save_core (void)
3590 range
= parse_reg_list (&input_line_pointer
);
3593 as_bad (_("expected register list"));
3594 ignore_rest_of_line ();
3598 demand_empty_rest_of_line ();
3600 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3601 into .unwind_save {..., sp...}. We aren't bothered about the value of
3602 ip because it is clobbered by calls. */
3603 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3604 && (range
& 0x3000) == 0x1000)
3606 unwind
.opcode_count
--;
3607 unwind
.sp_restored
= 0;
3608 range
= (range
| 0x2000) & ~0x1000;
3609 unwind
.pending_offset
= 0;
3615 /* See if we can use the short opcodes. These pop a block of up to 8
3616 registers starting with r4, plus maybe r14. */
3617 for (n
= 0; n
< 8; n
++)
3619 /* Break at the first non-saved register. */
3620 if ((range
& (1 << (n
+ 4))) == 0)
3623 /* See if there are any other bits set. */
3624 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3626 /* Use the long form. */
3627 op
= 0x8000 | ((range
>> 4) & 0xfff);
3628 add_unwind_opcode (op
, 2);
3632 /* Use the short form. */
3634 op
= 0xa8; /* Pop r14. */
3636 op
= 0xa0; /* Do not pop r14. */
3638 add_unwind_opcode (op
, 1);
3645 op
= 0xb100 | (range
& 0xf);
3646 add_unwind_opcode (op
, 2);
3649 /* Record the number of bytes pushed. */
3650 for (n
= 0; n
< 16; n
++)
3652 if (range
& (1 << n
))
3653 unwind
.frame_size
+= 4;
3658 /* Parse a directive saving FPA registers. */
3661 s_arm_unwind_save_fpa (int reg
)
3667 /* Get Number of registers to transfer. */
3668 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3671 exp
.X_op
= O_illegal
;
3673 if (exp
.X_op
!= O_constant
)
3675 as_bad (_("expected , <constant>"));
3676 ignore_rest_of_line ();
3680 num_regs
= exp
.X_add_number
;
3682 if (num_regs
< 1 || num_regs
> 4)
3684 as_bad (_("number of registers must be in the range [1:4]"));
3685 ignore_rest_of_line ();
3689 demand_empty_rest_of_line ();
3694 op
= 0xb4 | (num_regs
- 1);
3695 add_unwind_opcode (op
, 1);
3700 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3701 add_unwind_opcode (op
, 2);
3703 unwind
.frame_size
+= num_regs
* 12;
3707 /* Parse a directive saving VFP registers for ARMv6 and above. */
3710 s_arm_unwind_save_vfp_armv6 (void)
3715 int num_vfpv3_regs
= 0;
3716 int num_regs_below_16
;
3718 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3721 as_bad (_("expected register list"));
3722 ignore_rest_of_line ();
3726 demand_empty_rest_of_line ();
3728 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3729 than FSTMX/FLDMX-style ones). */
3731 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3733 num_vfpv3_regs
= count
;
3734 else if (start
+ count
> 16)
3735 num_vfpv3_regs
= start
+ count
- 16;
3737 if (num_vfpv3_regs
> 0)
3739 int start_offset
= start
> 16 ? start
- 16 : 0;
3740 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3741 add_unwind_opcode (op
, 2);
3744 /* Generate opcode for registers numbered in the range 0 .. 15. */
3745 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3746 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3747 if (num_regs_below_16
> 0)
3749 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3750 add_unwind_opcode (op
, 2);
3753 unwind
.frame_size
+= count
* 8;
3757 /* Parse a directive saving VFP registers for pre-ARMv6. */
3760 s_arm_unwind_save_vfp (void)
3766 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3769 as_bad (_("expected register list"));
3770 ignore_rest_of_line ();
3774 demand_empty_rest_of_line ();
3779 op
= 0xb8 | (count
- 1);
3780 add_unwind_opcode (op
, 1);
3785 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3786 add_unwind_opcode (op
, 2);
3788 unwind
.frame_size
+= count
* 8 + 4;
3792 /* Parse a directive saving iWMMXt data registers. */
3795 s_arm_unwind_save_mmxwr (void)
3803 if (*input_line_pointer
== '{')
3804 input_line_pointer
++;
3808 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3812 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3817 as_tsktsk (_("register list not in ascending order"));
3820 if (*input_line_pointer
== '-')
3822 input_line_pointer
++;
3823 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3826 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3829 else if (reg
>= hi_reg
)
3831 as_bad (_("bad register range"));
3834 for (; reg
< hi_reg
; reg
++)
3838 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3840 if (*input_line_pointer
== '}')
3841 input_line_pointer
++;
3843 demand_empty_rest_of_line ();
3845 /* Generate any deferred opcodes because we're going to be looking at
3847 flush_pending_unwind ();
3849 for (i
= 0; i
< 16; i
++)
3851 if (mask
& (1 << i
))
3852 unwind
.frame_size
+= 8;
3855 /* Attempt to combine with a previous opcode. We do this because gcc
3856 likes to output separate unwind directives for a single block of
3858 if (unwind
.opcode_count
> 0)
3860 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3861 if ((i
& 0xf8) == 0xc0)
3864 /* Only merge if the blocks are contiguous. */
3867 if ((mask
& 0xfe00) == (1 << 9))
3869 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3870 unwind
.opcode_count
--;
3873 else if (i
== 6 && unwind
.opcode_count
>= 2)
3875 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3879 op
= 0xffff << (reg
- 1);
3881 && ((mask
& op
) == (1u << (reg
- 1))))
3883 op
= (1 << (reg
+ i
+ 1)) - 1;
3884 op
&= ~((1 << reg
) - 1);
3886 unwind
.opcode_count
-= 2;
3893 /* We want to generate opcodes in the order the registers have been
3894 saved, ie. descending order. */
3895 for (reg
= 15; reg
>= -1; reg
--)
3897 /* Save registers in blocks. */
3899 || !(mask
& (1 << reg
)))
3901 /* We found an unsaved reg. Generate opcodes to save the
3908 op
= 0xc0 | (hi_reg
- 10);
3909 add_unwind_opcode (op
, 1);
3914 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3915 add_unwind_opcode (op
, 2);
3924 ignore_rest_of_line ();
3928 s_arm_unwind_save_mmxwcg (void)
3935 if (*input_line_pointer
== '{')
3936 input_line_pointer
++;
3940 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3944 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3950 as_tsktsk (_("register list not in ascending order"));
3953 if (*input_line_pointer
== '-')
3955 input_line_pointer
++;
3956 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3959 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3962 else if (reg
>= hi_reg
)
3964 as_bad (_("bad register range"));
3967 for (; reg
< hi_reg
; reg
++)
3971 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3973 if (*input_line_pointer
== '}')
3974 input_line_pointer
++;
3976 demand_empty_rest_of_line ();
3978 /* Generate any deferred opcodes because we're going to be looking at
3980 flush_pending_unwind ();
3982 for (reg
= 0; reg
< 16; reg
++)
3984 if (mask
& (1 << reg
))
3985 unwind
.frame_size
+= 4;
3988 add_unwind_opcode (op
, 2);
3991 ignore_rest_of_line ();
3995 /* Parse an unwind_save directive.
3996 If the argument is non-zero, this is a .vsave directive. */
3999 s_arm_unwind_save (int arch_v6
)
4002 struct reg_entry
*reg
;
4003 bfd_boolean had_brace
= FALSE
;
4005 if (!unwind
.proc_start
)
4006 as_bad (MISSING_FNSTART
);
4008 /* Figure out what sort of save we have. */
4009 peek
= input_line_pointer
;
4017 reg
= arm_reg_parse_multi (&peek
);
4021 as_bad (_("register expected"));
4022 ignore_rest_of_line ();
4031 as_bad (_("FPA .unwind_save does not take a register list"));
4032 ignore_rest_of_line ();
4035 input_line_pointer
= peek
;
4036 s_arm_unwind_save_fpa (reg
->number
);
4039 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4042 s_arm_unwind_save_vfp_armv6 ();
4044 s_arm_unwind_save_vfp ();
4046 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4047 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4050 as_bad (_(".unwind_save does not support this kind of register"));
4051 ignore_rest_of_line ();
4056 /* Parse an unwind_movsp directive. */
4059 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4065 if (!unwind
.proc_start
)
4066 as_bad (MISSING_FNSTART
);
4068 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4071 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4072 ignore_rest_of_line ();
4076 /* Optional constant. */
4077 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4079 if (immediate_for_directive (&offset
) == FAIL
)
4085 demand_empty_rest_of_line ();
4087 if (reg
== REG_SP
|| reg
== REG_PC
)
4089 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4093 if (unwind
.fp_reg
!= REG_SP
)
4094 as_bad (_("unexpected .unwind_movsp directive"));
4096 /* Generate opcode to restore the value. */
4098 add_unwind_opcode (op
, 1);
4100 /* Record the information for later. */
4101 unwind
.fp_reg
= reg
;
4102 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4103 unwind
.sp_restored
= 1;
4106 /* Parse an unwind_pad directive. */
4109 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4113 if (!unwind
.proc_start
)
4114 as_bad (MISSING_FNSTART
);
4116 if (immediate_for_directive (&offset
) == FAIL
)
4121 as_bad (_("stack increment must be multiple of 4"));
4122 ignore_rest_of_line ();
4126 /* Don't generate any opcodes, just record the details for later. */
4127 unwind
.frame_size
+= offset
;
4128 unwind
.pending_offset
+= offset
;
4130 demand_empty_rest_of_line ();
4133 /* Parse an unwind_setfp directive. */
4136 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4142 if (!unwind
.proc_start
)
4143 as_bad (MISSING_FNSTART
);
4145 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4146 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4149 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4151 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4153 as_bad (_("expected <reg>, <reg>"));
4154 ignore_rest_of_line ();
4158 /* Optional constant. */
4159 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4161 if (immediate_for_directive (&offset
) == FAIL
)
4167 demand_empty_rest_of_line ();
4169 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4171 as_bad (_("register must be either sp or set by a previous"
4172 "unwind_movsp directive"));
4176 /* Don't generate any opcodes, just record the information for later. */
4177 unwind
.fp_reg
= fp_reg
;
4179 if (sp_reg
== REG_SP
)
4180 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4182 unwind
.fp_offset
-= offset
;
4185 /* Parse an unwind_raw directive. */
4188 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4191 /* This is an arbitrary limit. */
4192 unsigned char op
[16];
4195 if (!unwind
.proc_start
)
4196 as_bad (MISSING_FNSTART
);
4199 if (exp
.X_op
== O_constant
4200 && skip_past_comma (&input_line_pointer
) != FAIL
)
4202 unwind
.frame_size
+= exp
.X_add_number
;
4206 exp
.X_op
= O_illegal
;
4208 if (exp
.X_op
!= O_constant
)
4210 as_bad (_("expected <offset>, <opcode>"));
4211 ignore_rest_of_line ();
4217 /* Parse the opcode. */
4222 as_bad (_("unwind opcode too long"));
4223 ignore_rest_of_line ();
4225 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4227 as_bad (_("invalid unwind opcode"));
4228 ignore_rest_of_line ();
4231 op
[count
++] = exp
.X_add_number
;
4233 /* Parse the next byte. */
4234 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4240 /* Add the opcode bytes in reverse order. */
4242 add_unwind_opcode (op
[count
], 1);
4244 demand_empty_rest_of_line ();
4248 /* Parse a .eabi_attribute directive. */
4251 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4253 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4255 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4256 attributes_set_explicitly
[tag
] = 1;
4258 #endif /* OBJ_ELF */
4260 static void s_arm_arch (int);
4261 static void s_arm_object_arch (int);
4262 static void s_arm_cpu (int);
4263 static void s_arm_fpu (int);
4268 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4275 if (exp
.X_op
== O_symbol
)
4276 exp
.X_op
= O_secrel
;
4278 emit_expr (&exp
, 4);
4280 while (*input_line_pointer
++ == ',');
4282 input_line_pointer
--;
4283 demand_empty_rest_of_line ();
4287 /* This table describes all the machine specific pseudo-ops the assembler
4288 has to support. The fields are:
4289 pseudo-op name without dot
4290 function to call to execute this pseudo-op
4291 Integer arg to pass to the function. */
4293 const pseudo_typeS md_pseudo_table
[] =
4295 /* Never called because '.req' does not start a line. */
4296 { "req", s_req
, 0 },
4297 /* Following two are likewise never called. */
4300 { "unreq", s_unreq
, 0 },
4301 { "bss", s_bss
, 0 },
4302 { "align", s_align
, 0 },
4303 { "arm", s_arm
, 0 },
4304 { "thumb", s_thumb
, 0 },
4305 { "code", s_code
, 0 },
4306 { "force_thumb", s_force_thumb
, 0 },
4307 { "thumb_func", s_thumb_func
, 0 },
4308 { "thumb_set", s_thumb_set
, 0 },
4309 { "even", s_even
, 0 },
4310 { "ltorg", s_ltorg
, 0 },
4311 { "pool", s_ltorg
, 0 },
4312 { "syntax", s_syntax
, 0 },
4313 { "cpu", s_arm_cpu
, 0 },
4314 { "arch", s_arm_arch
, 0 },
4315 { "object_arch", s_arm_object_arch
, 0 },
4316 { "fpu", s_arm_fpu
, 0 },
4318 { "word", s_arm_elf_cons
, 4 },
4319 { "long", s_arm_elf_cons
, 4 },
4320 { "inst.n", s_arm_elf_inst
, 2 },
4321 { "inst.w", s_arm_elf_inst
, 4 },
4322 { "inst", s_arm_elf_inst
, 0 },
4323 { "rel31", s_arm_rel31
, 0 },
4324 { "fnstart", s_arm_unwind_fnstart
, 0 },
4325 { "fnend", s_arm_unwind_fnend
, 0 },
4326 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4327 { "personality", s_arm_unwind_personality
, 0 },
4328 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4329 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4330 { "save", s_arm_unwind_save
, 0 },
4331 { "vsave", s_arm_unwind_save
, 1 },
4332 { "movsp", s_arm_unwind_movsp
, 0 },
4333 { "pad", s_arm_unwind_pad
, 0 },
4334 { "setfp", s_arm_unwind_setfp
, 0 },
4335 { "unwind_raw", s_arm_unwind_raw
, 0 },
4336 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4340 /* These are used for dwarf. */
4344 /* These are used for dwarf2. */
4345 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4346 { "loc", dwarf2_directive_loc
, 0 },
4347 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4349 { "extend", float_cons
, 'x' },
4350 { "ldouble", float_cons
, 'x' },
4351 { "packed", float_cons
, 'p' },
4353 {"secrel32", pe_directive_secrel
, 0},
4358 /* Parser functions used exclusively in instruction operands. */
4360 /* Generic immediate-value read function for use in insn parsing.
4361 STR points to the beginning of the immediate (the leading #);
4362 VAL receives the value; if the value is outside [MIN, MAX]
4363 issue an error. PREFIX_OPT is true if the immediate prefix is
4367 parse_immediate (char **str
, int *val
, int min
, int max
,
4368 bfd_boolean prefix_opt
)
4371 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4372 if (exp
.X_op
!= O_constant
)
4374 inst
.error
= _("constant expression required");
4378 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4380 inst
.error
= _("immediate value out of range");
4384 *val
= exp
.X_add_number
;
4388 /* Less-generic immediate-value read function with the possibility of loading a
4389 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4390 instructions. Puts the result directly in inst.operands[i]. */
4393 parse_big_immediate (char **str
, int i
)
4398 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4400 if (exp
.X_op
== O_constant
)
4402 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4403 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4404 O_constant. We have to be careful not to break compilation for
4405 32-bit X_add_number, though. */
4406 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4408 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4409 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4410 inst
.operands
[i
].regisimm
= 1;
4413 else if (exp
.X_op
== O_big
4414 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4415 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4417 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4418 /* Bignums have their least significant bits in
4419 generic_bignum[0]. Make sure we put 32 bits in imm and
4420 32 bits in reg, in a (hopefully) portable way. */
4421 gas_assert (parts
!= 0);
4422 inst
.operands
[i
].imm
= 0;
4423 for (j
= 0; j
< parts
; j
++, idx
++)
4424 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4425 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4426 inst
.operands
[i
].reg
= 0;
4427 for (j
= 0; j
< parts
; j
++, idx
++)
4428 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4429 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4430 inst
.operands
[i
].regisimm
= 1;
4440 /* Returns the pseudo-register number of an FPA immediate constant,
4441 or FAIL if there isn't a valid constant here. */
4444 parse_fpa_immediate (char ** str
)
4446 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4452 /* First try and match exact strings, this is to guarantee
4453 that some formats will work even for cross assembly. */
4455 for (i
= 0; fp_const
[i
]; i
++)
4457 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4461 *str
+= strlen (fp_const
[i
]);
4462 if (is_end_of_line
[(unsigned char) **str
])
4468 /* Just because we didn't get a match doesn't mean that the constant
4469 isn't valid, just that it is in a format that we don't
4470 automatically recognize. Try parsing it with the standard
4471 expression routines. */
4473 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4475 /* Look for a raw floating point number. */
4476 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4477 && is_end_of_line
[(unsigned char) *save_in
])
4479 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4481 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4483 if (words
[j
] != fp_values
[i
][j
])
4487 if (j
== MAX_LITTLENUMS
)
4495 /* Try and parse a more complex expression, this will probably fail
4496 unless the code uses a floating point prefix (eg "0f"). */
4497 save_in
= input_line_pointer
;
4498 input_line_pointer
= *str
;
4499 if (expression (&exp
) == absolute_section
4500 && exp
.X_op
== O_big
4501 && exp
.X_add_number
< 0)
4503 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4505 if (gen_to_words (words
, 5, (long) 15) == 0)
4507 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4509 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4511 if (words
[j
] != fp_values
[i
][j
])
4515 if (j
== MAX_LITTLENUMS
)
4517 *str
= input_line_pointer
;
4518 input_line_pointer
= save_in
;
4525 *str
= input_line_pointer
;
4526 input_line_pointer
= save_in
;
4527 inst
.error
= _("invalid FPA immediate expression");
4531 /* Returns 1 if a number has "quarter-precision" float format
4532 0baBbbbbbc defgh000 00000000 00000000. */
4535 is_quarter_float (unsigned imm
)
4537 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4538 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4541 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4542 0baBbbbbbc defgh000 00000000 00000000.
4543 The zero and minus-zero cases need special handling, since they can't be
4544 encoded in the "quarter-precision" float format, but can nonetheless be
4545 loaded as integer constants. */
4548 parse_qfloat_immediate (char **ccp
, int *immed
)
4552 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4553 int found_fpchar
= 0;
4555 skip_past_char (&str
, '#');
4557 /* We must not accidentally parse an integer as a floating-point number. Make
4558 sure that the value we parse is not an integer by checking for special
4559 characters '.' or 'e'.
4560 FIXME: This is a horrible hack, but doing better is tricky because type
4561 information isn't in a very usable state at parse time. */
4563 skip_whitespace (fpnum
);
4565 if (strncmp (fpnum
, "0x", 2) == 0)
4569 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4570 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4580 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4582 unsigned fpword
= 0;
4585 /* Our FP word must be 32 bits (single-precision FP). */
4586 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4588 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4592 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4605 /* Shift operands. */
4608 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4611 struct asm_shift_name
4614 enum shift_kind kind
;
4617 /* Third argument to parse_shift. */
4618 enum parse_shift_mode
4620 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4621 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4622 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4623 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4624 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4627 /* Parse a <shift> specifier on an ARM data processing instruction.
4628 This has three forms:
4630 (LSL|LSR|ASL|ASR|ROR) Rs
4631 (LSL|LSR|ASL|ASR|ROR) #imm
4634 Note that ASL is assimilated to LSL in the instruction encoding, and
4635 RRX to ROR #0 (which cannot be written as such). */
4638 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4640 const struct asm_shift_name
*shift_name
;
4641 enum shift_kind shift
;
4646 for (p
= *str
; ISALPHA (*p
); p
++)
4651 inst
.error
= _("shift expression expected");
4655 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4658 if (shift_name
== NULL
)
4660 inst
.error
= _("shift expression expected");
4664 shift
= shift_name
->kind
;
4668 case NO_SHIFT_RESTRICT
:
4669 case SHIFT_IMMEDIATE
: break;
4671 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4672 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4674 inst
.error
= _("'LSL' or 'ASR' required");
4679 case SHIFT_LSL_IMMEDIATE
:
4680 if (shift
!= SHIFT_LSL
)
4682 inst
.error
= _("'LSL' required");
4687 case SHIFT_ASR_IMMEDIATE
:
4688 if (shift
!= SHIFT_ASR
)
4690 inst
.error
= _("'ASR' required");
4698 if (shift
!= SHIFT_RRX
)
4700 /* Whitespace can appear here if the next thing is a bare digit. */
4701 skip_whitespace (p
);
4703 if (mode
== NO_SHIFT_RESTRICT
4704 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4706 inst
.operands
[i
].imm
= reg
;
4707 inst
.operands
[i
].immisreg
= 1;
4709 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4712 inst
.operands
[i
].shift_kind
= shift
;
4713 inst
.operands
[i
].shifted
= 1;
4718 /* Parse a <shifter_operand> for an ARM data processing instruction:
4721 #<immediate>, <rotate>
4725 where <shift> is defined by parse_shift above, and <rotate> is a
4726 multiple of 2 between 0 and 30. Validation of immediate operands
4727 is deferred to md_apply_fix. */
4730 parse_shifter_operand (char **str
, int i
)
4735 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4737 inst
.operands
[i
].reg
= value
;
4738 inst
.operands
[i
].isreg
= 1;
4740 /* parse_shift will override this if appropriate */
4741 inst
.reloc
.exp
.X_op
= O_constant
;
4742 inst
.reloc
.exp
.X_add_number
= 0;
4744 if (skip_past_comma (str
) == FAIL
)
4747 /* Shift operation on register. */
4748 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4751 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4754 if (skip_past_comma (str
) == SUCCESS
)
4756 /* #x, y -- ie explicit rotation by Y. */
4757 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4760 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4762 inst
.error
= _("constant expression expected");
4766 value
= exp
.X_add_number
;
4767 if (value
< 0 || value
> 30 || value
% 2 != 0)
4769 inst
.error
= _("invalid rotation");
4772 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4774 inst
.error
= _("invalid constant");
4778 /* Convert to decoded value. md_apply_fix will put it back. */
4779 inst
.reloc
.exp
.X_add_number
4780 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4781 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4784 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4785 inst
.reloc
.pc_rel
= 0;
4789 /* Group relocation information. Each entry in the table contains the
4790 textual name of the relocation as may appear in assembler source
4791 and must end with a colon.
4792 Along with this textual name are the relocation codes to be used if
4793 the corresponding instruction is an ALU instruction (ADD or SUB only),
4794 an LDR, an LDRS, or an LDC. */
4796 struct group_reloc_table_entry
4807 /* Varieties of non-ALU group relocation. */
4814 static struct group_reloc_table_entry group_reloc_table
[] =
4815 { /* Program counter relative: */
4817 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4822 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4823 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4824 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4825 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4827 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4832 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4833 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4834 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4835 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4837 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4838 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4839 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4840 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4841 /* Section base relative */
4843 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4848 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4849 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4850 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4851 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4853 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4858 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4859 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4860 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4861 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4863 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4864 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4865 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4866 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4868 /* Given the address of a pointer pointing to the textual name of a group
4869 relocation as may appear in assembler source, attempt to find its details
4870 in group_reloc_table. The pointer will be updated to the character after
4871 the trailing colon. On failure, FAIL will be returned; SUCCESS
4872 otherwise. On success, *entry will be updated to point at the relevant
4873 group_reloc_table entry. */
4876 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4879 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4881 int length
= strlen (group_reloc_table
[i
].name
);
4883 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4884 && (*str
)[length
] == ':')
4886 *out
= &group_reloc_table
[i
];
4887 *str
+= (length
+ 1);
4895 /* Parse a <shifter_operand> for an ARM data processing instruction
4896 (as for parse_shifter_operand) where group relocations are allowed:
4899 #<immediate>, <rotate>
4900 #:<group_reloc>:<expression>
4904 where <group_reloc> is one of the strings defined in group_reloc_table.
4905 The hashes are optional.
4907 Everything else is as for parse_shifter_operand. */
4909 static parse_operand_result
4910 parse_shifter_operand_group_reloc (char **str
, int i
)
4912 /* Determine if we have the sequence of characters #: or just :
4913 coming next. If we do, then we check for a group relocation.
4914 If we don't, punt the whole lot to parse_shifter_operand. */
4916 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4917 || (*str
)[0] == ':')
4919 struct group_reloc_table_entry
*entry
;
4921 if ((*str
)[0] == '#')
4926 /* Try to parse a group relocation. Anything else is an error. */
4927 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4929 inst
.error
= _("unknown group relocation");
4930 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4933 /* We now have the group relocation table entry corresponding to
4934 the name in the assembler source. Next, we parse the expression. */
4935 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4936 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4938 /* Record the relocation type (always the ALU variant here). */
4939 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4940 gas_assert (inst
.reloc
.type
!= 0);
4942 return PARSE_OPERAND_SUCCESS
;
4945 return parse_shifter_operand (str
, i
) == SUCCESS
4946 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4948 /* Never reached. */
4951 /* Parse a Neon alignment expression. Information is written to
4952 inst.operands[i]. We assume the initial ':' has been skipped.
4954 align .imm = align << 8, .immisalign=1, .preind=0 */
4955 static parse_operand_result
4956 parse_neon_alignment (char **str
, int i
)
4961 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4963 if (exp
.X_op
!= O_constant
)
4965 inst
.error
= _("alignment must be constant");
4966 return PARSE_OPERAND_FAIL
;
4969 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4970 inst
.operands
[i
].immisalign
= 1;
4971 /* Alignments are not pre-indexes. */
4972 inst
.operands
[i
].preind
= 0;
4975 return PARSE_OPERAND_SUCCESS
;
4978 /* Parse all forms of an ARM address expression. Information is written
4979 to inst.operands[i] and/or inst.reloc.
4981 Preindexed addressing (.preind=1):
4983 [Rn, #offset] .reg=Rn .reloc.exp=offset
4984 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4985 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4986 .shift_kind=shift .reloc.exp=shift_imm
4988 These three may have a trailing ! which causes .writeback to be set also.
4990 Postindexed addressing (.postind=1, .writeback=1):
4992 [Rn], #offset .reg=Rn .reloc.exp=offset
4993 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4994 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4995 .shift_kind=shift .reloc.exp=shift_imm
4997 Unindexed addressing (.preind=0, .postind=0):
4999 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5003 [Rn]{!} shorthand for [Rn,#0]{!}
5004 =immediate .isreg=0 .reloc.exp=immediate
5005 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5007 It is the caller's responsibility to check for addressing modes not
5008 supported by the instruction, and to set inst.reloc.type. */
5010 static parse_operand_result
5011 parse_address_main (char **str
, int i
, int group_relocations
,
5012 group_reloc_type group_type
)
5017 if (skip_past_char (&p
, '[') == FAIL
)
5019 if (skip_past_char (&p
, '=') == FAIL
)
5021 /* Bare address - translate to PC-relative offset. */
5022 inst
.reloc
.pc_rel
= 1;
5023 inst
.operands
[i
].reg
= REG_PC
;
5024 inst
.operands
[i
].isreg
= 1;
5025 inst
.operands
[i
].preind
= 1;
5027 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5029 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5030 return PARSE_OPERAND_FAIL
;
5033 return PARSE_OPERAND_SUCCESS
;
5036 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5038 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5039 return PARSE_OPERAND_FAIL
;
5041 inst
.operands
[i
].reg
= reg
;
5042 inst
.operands
[i
].isreg
= 1;
5044 if (skip_past_comma (&p
) == SUCCESS
)
5046 inst
.operands
[i
].preind
= 1;
5049 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5051 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5053 inst
.operands
[i
].imm
= reg
;
5054 inst
.operands
[i
].immisreg
= 1;
5056 if (skip_past_comma (&p
) == SUCCESS
)
5057 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5058 return PARSE_OPERAND_FAIL
;
5060 else if (skip_past_char (&p
, ':') == SUCCESS
)
5062 /* FIXME: '@' should be used here, but it's filtered out by generic
5063 code before we get to see it here. This may be subject to
5065 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5067 if (result
!= PARSE_OPERAND_SUCCESS
)
5072 if (inst
.operands
[i
].negative
)
5074 inst
.operands
[i
].negative
= 0;
5078 if (group_relocations
5079 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5081 struct group_reloc_table_entry
*entry
;
5083 /* Skip over the #: or : sequence. */
5089 /* Try to parse a group relocation. Anything else is an
5091 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5093 inst
.error
= _("unknown group relocation");
5094 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5097 /* We now have the group relocation table entry corresponding to
5098 the name in the assembler source. Next, we parse the
5100 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5101 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5103 /* Record the relocation type. */
5107 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5111 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5115 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5122 if (inst
.reloc
.type
== 0)
5124 inst
.error
= _("this group relocation is not allowed on this instruction");
5125 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5129 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5130 return PARSE_OPERAND_FAIL
;
5133 else if (skip_past_char (&p
, ':') == SUCCESS
)
5135 /* FIXME: '@' should be used here, but it's filtered out by generic code
5136 before we get to see it here. This may be subject to change. */
5137 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5139 if (result
!= PARSE_OPERAND_SUCCESS
)
5143 if (skip_past_char (&p
, ']') == FAIL
)
5145 inst
.error
= _("']' expected");
5146 return PARSE_OPERAND_FAIL
;
5149 if (skip_past_char (&p
, '!') == SUCCESS
)
5150 inst
.operands
[i
].writeback
= 1;
5152 else if (skip_past_comma (&p
) == SUCCESS
)
5154 if (skip_past_char (&p
, '{') == SUCCESS
)
5156 /* [Rn], {expr} - unindexed, with option */
5157 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5158 0, 255, TRUE
) == FAIL
)
5159 return PARSE_OPERAND_FAIL
;
5161 if (skip_past_char (&p
, '}') == FAIL
)
5163 inst
.error
= _("'}' expected at end of 'option' field");
5164 return PARSE_OPERAND_FAIL
;
5166 if (inst
.operands
[i
].preind
)
5168 inst
.error
= _("cannot combine index with option");
5169 return PARSE_OPERAND_FAIL
;
5172 return PARSE_OPERAND_SUCCESS
;
5176 inst
.operands
[i
].postind
= 1;
5177 inst
.operands
[i
].writeback
= 1;
5179 if (inst
.operands
[i
].preind
)
5181 inst
.error
= _("cannot combine pre- and post-indexing");
5182 return PARSE_OPERAND_FAIL
;
5186 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5188 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5190 /* We might be using the immediate for alignment already. If we
5191 are, OR the register number into the low-order bits. */
5192 if (inst
.operands
[i
].immisalign
)
5193 inst
.operands
[i
].imm
|= reg
;
5195 inst
.operands
[i
].imm
= reg
;
5196 inst
.operands
[i
].immisreg
= 1;
5198 if (skip_past_comma (&p
) == SUCCESS
)
5199 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5200 return PARSE_OPERAND_FAIL
;
5204 if (inst
.operands
[i
].negative
)
5206 inst
.operands
[i
].negative
= 0;
5209 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5210 return PARSE_OPERAND_FAIL
;
5215 /* If at this point neither .preind nor .postind is set, we have a
5216 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5217 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5219 inst
.operands
[i
].preind
= 1;
5220 inst
.reloc
.exp
.X_op
= O_constant
;
5221 inst
.reloc
.exp
.X_add_number
= 0;
5224 return PARSE_OPERAND_SUCCESS
;
5228 parse_address (char **str
, int i
)
5230 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5234 static parse_operand_result
5235 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5237 return parse_address_main (str
, i
, 1, type
);
5240 /* Parse an operand for a MOVW or MOVT instruction. */
5242 parse_half (char **str
)
5247 skip_past_char (&p
, '#');
5248 if (strncasecmp (p
, ":lower16:", 9) == 0)
5249 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5250 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5251 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5253 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5256 skip_whitespace (p
);
5259 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5262 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5264 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5266 inst
.error
= _("constant expression expected");
5269 if (inst
.reloc
.exp
.X_add_number
< 0
5270 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5272 inst
.error
= _("immediate value out of range");
5280 /* Miscellaneous. */
5282 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5283 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5285 parse_psr (char **str
)
5288 unsigned long psr_field
;
5289 const struct asm_psr
*psr
;
5292 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5293 feature for ease of use and backwards compatibility. */
5295 if (strncasecmp (p
, "SPSR", 4) == 0)
5296 psr_field
= SPSR_BIT
;
5297 else if (strncasecmp (p
, "CPSR", 4) == 0)
5304 while (ISALNUM (*p
) || *p
== '_');
5306 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5318 /* A suffix follows. */
5324 while (ISALNUM (*p
) || *p
== '_');
5326 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5331 psr_field
|= psr
->field
;
5336 goto error
; /* Garbage after "[CS]PSR". */
5338 psr_field
|= (PSR_c
| PSR_f
);
5344 inst
.error
= _("flag for {c}psr instruction expected");
5348 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5349 value suitable for splatting into the AIF field of the instruction. */
5352 parse_cps_flags (char **str
)
5361 case '\0': case ',':
5364 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5365 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5366 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5369 inst
.error
= _("unrecognized CPS flag");
5374 if (saw_a_flag
== 0)
5376 inst
.error
= _("missing CPS flags");
5384 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5385 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5388 parse_endian_specifier (char **str
)
5393 if (strncasecmp (s
, "BE", 2))
5395 else if (strncasecmp (s
, "LE", 2))
5399 inst
.error
= _("valid endian specifiers are be or le");
5403 if (ISALNUM (s
[2]) || s
[2] == '_')
5405 inst
.error
= _("valid endian specifiers are be or le");
5410 return little_endian
;
5413 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5414 value suitable for poking into the rotate field of an sxt or sxta
5415 instruction, or FAIL on error. */
5418 parse_ror (char **str
)
5423 if (strncasecmp (s
, "ROR", 3) == 0)
5427 inst
.error
= _("missing rotation field after comma");
5431 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5436 case 0: *str
= s
; return 0x0;
5437 case 8: *str
= s
; return 0x1;
5438 case 16: *str
= s
; return 0x2;
5439 case 24: *str
= s
; return 0x3;
5442 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5447 /* Parse a conditional code (from conds[] below). The value returned is in the
5448 range 0 .. 14, or FAIL. */
5450 parse_cond (char **str
)
5453 const struct asm_cond
*c
;
5455 /* Condition codes are always 2 characters, so matching up to
5456 3 characters is sufficient. */
5461 while (ISALPHA (*q
) && n
< 3)
5463 cond
[n
] = TOLOWER (*q
);
5468 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5471 inst
.error
= _("condition required");
5479 /* Parse an option for a barrier instruction. Returns the encoding for the
5482 parse_barrier (char **str
)
5485 const struct asm_barrier_opt
*o
;
5488 while (ISALPHA (*q
))
5491 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5500 /* Parse the operands of a table branch instruction. Similar to a memory
5503 parse_tb (char **str
)
5508 if (skip_past_char (&p
, '[') == FAIL
)
5510 inst
.error
= _("'[' expected");
5514 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5516 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5519 inst
.operands
[0].reg
= reg
;
5521 if (skip_past_comma (&p
) == FAIL
)
5523 inst
.error
= _("',' expected");
5527 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5529 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5532 inst
.operands
[0].imm
= reg
;
5534 if (skip_past_comma (&p
) == SUCCESS
)
5536 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5538 if (inst
.reloc
.exp
.X_add_number
!= 1)
5540 inst
.error
= _("invalid shift");
5543 inst
.operands
[0].shifted
= 1;
5546 if (skip_past_char (&p
, ']') == FAIL
)
5548 inst
.error
= _("']' expected");
5555 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5556 information on the types the operands can take and how they are encoded.
5557 Up to four operands may be read; this function handles setting the
5558 ".present" field for each read operand itself.
5559 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5560 else returns FAIL. */
5563 parse_neon_mov (char **str
, int *which_operand
)
5565 int i
= *which_operand
, val
;
5566 enum arm_reg_type rtype
;
5568 struct neon_type_el optype
;
5570 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5572 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5573 inst
.operands
[i
].reg
= val
;
5574 inst
.operands
[i
].isscalar
= 1;
5575 inst
.operands
[i
].vectype
= optype
;
5576 inst
.operands
[i
++].present
= 1;
5578 if (skip_past_comma (&ptr
) == FAIL
)
5581 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5584 inst
.operands
[i
].reg
= val
;
5585 inst
.operands
[i
].isreg
= 1;
5586 inst
.operands
[i
].present
= 1;
5588 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5591 /* Cases 0, 1, 2, 3, 5 (D only). */
5592 if (skip_past_comma (&ptr
) == FAIL
)
5595 inst
.operands
[i
].reg
= val
;
5596 inst
.operands
[i
].isreg
= 1;
5597 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5598 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5599 inst
.operands
[i
].isvec
= 1;
5600 inst
.operands
[i
].vectype
= optype
;
5601 inst
.operands
[i
++].present
= 1;
5603 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5605 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5606 Case 13: VMOV <Sd>, <Rm> */
5607 inst
.operands
[i
].reg
= val
;
5608 inst
.operands
[i
].isreg
= 1;
5609 inst
.operands
[i
].present
= 1;
5611 if (rtype
== REG_TYPE_NQ
)
5613 first_error (_("can't use Neon quad register here"));
5616 else if (rtype
!= REG_TYPE_VFS
)
5619 if (skip_past_comma (&ptr
) == FAIL
)
5621 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5623 inst
.operands
[i
].reg
= val
;
5624 inst
.operands
[i
].isreg
= 1;
5625 inst
.operands
[i
].present
= 1;
5628 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5631 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5632 Case 1: VMOV<c><q> <Dd>, <Dm>
5633 Case 8: VMOV.F32 <Sd>, <Sm>
5634 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5636 inst
.operands
[i
].reg
= val
;
5637 inst
.operands
[i
].isreg
= 1;
5638 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5639 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5640 inst
.operands
[i
].isvec
= 1;
5641 inst
.operands
[i
].vectype
= optype
;
5642 inst
.operands
[i
].present
= 1;
5644 if (skip_past_comma (&ptr
) == SUCCESS
)
5649 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5652 inst
.operands
[i
].reg
= val
;
5653 inst
.operands
[i
].isreg
= 1;
5654 inst
.operands
[i
++].present
= 1;
5656 if (skip_past_comma (&ptr
) == FAIL
)
5659 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5662 inst
.operands
[i
].reg
= val
;
5663 inst
.operands
[i
].isreg
= 1;
5664 inst
.operands
[i
++].present
= 1;
5667 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5668 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5669 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5670 Case 10: VMOV.F32 <Sd>, #<imm>
5671 Case 11: VMOV.F64 <Dd>, #<imm> */
5672 inst
.operands
[i
].immisfloat
= 1;
5673 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5674 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5675 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5679 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5683 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5686 inst
.operands
[i
].reg
= val
;
5687 inst
.operands
[i
].isreg
= 1;
5688 inst
.operands
[i
++].present
= 1;
5690 if (skip_past_comma (&ptr
) == FAIL
)
5693 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5695 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5696 inst
.operands
[i
].reg
= val
;
5697 inst
.operands
[i
].isscalar
= 1;
5698 inst
.operands
[i
].present
= 1;
5699 inst
.operands
[i
].vectype
= optype
;
5701 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5703 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5704 inst
.operands
[i
].reg
= val
;
5705 inst
.operands
[i
].isreg
= 1;
5706 inst
.operands
[i
++].present
= 1;
5708 if (skip_past_comma (&ptr
) == FAIL
)
5711 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5714 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5718 inst
.operands
[i
].reg
= val
;
5719 inst
.operands
[i
].isreg
= 1;
5720 inst
.operands
[i
].isvec
= 1;
5721 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5722 inst
.operands
[i
].vectype
= optype
;
5723 inst
.operands
[i
].present
= 1;
5725 if (rtype
== REG_TYPE_VFS
)
5729 if (skip_past_comma (&ptr
) == FAIL
)
5731 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5734 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5737 inst
.operands
[i
].reg
= val
;
5738 inst
.operands
[i
].isreg
= 1;
5739 inst
.operands
[i
].isvec
= 1;
5740 inst
.operands
[i
].issingle
= 1;
5741 inst
.operands
[i
].vectype
= optype
;
5742 inst
.operands
[i
].present
= 1;
5745 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5749 inst
.operands
[i
].reg
= val
;
5750 inst
.operands
[i
].isreg
= 1;
5751 inst
.operands
[i
].isvec
= 1;
5752 inst
.operands
[i
].issingle
= 1;
5753 inst
.operands
[i
].vectype
= optype
;
5754 inst
.operands
[i
++].present
= 1;
5759 first_error (_("parse error"));
5763 /* Successfully parsed the operands. Update args. */
5769 first_error (_("expected comma"));
5773 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5777 /* Use this macro when the operand constraints are different
5778 for ARM and THUMB (e.g. ldrd). */
5779 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5780 ((arm_operand) | ((thumb_operand) << 16))
5782 /* Matcher codes for parse_operands. */
5783 enum operand_parse_code
5785 OP_stop
, /* end of line */
5787 OP_RR
, /* ARM register */
5788 OP_RRnpc
, /* ARM register, not r15 */
5789 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5790 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5791 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5792 optional trailing ! */
5793 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5794 OP_RCP
, /* Coprocessor number */
5795 OP_RCN
, /* Coprocessor register */
5796 OP_RF
, /* FPA register */
5797 OP_RVS
, /* VFP single precision register */
5798 OP_RVD
, /* VFP double precision register (0..15) */
5799 OP_RND
, /* Neon double precision register (0..31) */
5800 OP_RNQ
, /* Neon quad precision register */
5801 OP_RVSD
, /* VFP single or double precision register */
5802 OP_RNDQ
, /* Neon double or quad precision register */
5803 OP_RNSDQ
, /* Neon single, double or quad precision register */
5804 OP_RNSC
, /* Neon scalar D[X] */
5805 OP_RVC
, /* VFP control register */
5806 OP_RMF
, /* Maverick F register */
5807 OP_RMD
, /* Maverick D register */
5808 OP_RMFX
, /* Maverick FX register */
5809 OP_RMDX
, /* Maverick DX register */
5810 OP_RMAX
, /* Maverick AX register */
5811 OP_RMDS
, /* Maverick DSPSC register */
5812 OP_RIWR
, /* iWMMXt wR register */
5813 OP_RIWC
, /* iWMMXt wC register */
5814 OP_RIWG
, /* iWMMXt wCG register */
5815 OP_RXA
, /* XScale accumulator register */
5817 OP_REGLST
, /* ARM register list */
5818 OP_VRSLST
, /* VFP single-precision register list */
5819 OP_VRDLST
, /* VFP double-precision register list */
5820 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5821 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5822 OP_NSTRLST
, /* Neon element/structure list */
5824 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5825 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5826 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5827 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5828 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5829 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5830 OP_VMOV
, /* Neon VMOV operands. */
5831 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5832 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5833 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5835 OP_I0
, /* immediate zero */
5836 OP_I7
, /* immediate value 0 .. 7 */
5837 OP_I15
, /* 0 .. 15 */
5838 OP_I16
, /* 1 .. 16 */
5839 OP_I16z
, /* 0 .. 16 */
5840 OP_I31
, /* 0 .. 31 */
5841 OP_I31w
, /* 0 .. 31, optional trailing ! */
5842 OP_I32
, /* 1 .. 32 */
5843 OP_I32z
, /* 0 .. 32 */
5844 OP_I63
, /* 0 .. 63 */
5845 OP_I63s
, /* -64 .. 63 */
5846 OP_I64
, /* 1 .. 64 */
5847 OP_I64z
, /* 0 .. 64 */
5848 OP_I255
, /* 0 .. 255 */
5850 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5851 OP_I7b
, /* 0 .. 7 */
5852 OP_I15b
, /* 0 .. 15 */
5853 OP_I31b
, /* 0 .. 31 */
5855 OP_SH
, /* shifter operand */
5856 OP_SHG
, /* shifter operand with possible group relocation */
5857 OP_ADDR
, /* Memory address expression (any mode) */
5858 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5859 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5860 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5861 OP_EXP
, /* arbitrary expression */
5862 OP_EXPi
, /* same, with optional immediate prefix */
5863 OP_EXPr
, /* same, with optional relocation suffix */
5864 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5866 OP_CPSF
, /* CPS flags */
5867 OP_ENDI
, /* Endianness specifier */
5868 OP_PSR
, /* CPSR/SPSR mask for msr */
5869 OP_COND
, /* conditional code */
5870 OP_TB
, /* Table branch. */
5872 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5873 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5875 OP_RRnpc_I0
, /* ARM register or literal 0 */
5876 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5877 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5878 OP_RF_IF
, /* FPA register or immediate */
5879 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5880 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5882 /* Optional operands. */
5883 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5884 OP_oI31b
, /* 0 .. 31 */
5885 OP_oI32b
, /* 1 .. 32 */
5886 OP_oIffffb
, /* 0 .. 65535 */
5887 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5889 OP_oRR
, /* ARM register */
5890 OP_oRRnpc
, /* ARM register, not the PC */
5891 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5892 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5893 OP_oRND
, /* Optional Neon double precision register */
5894 OP_oRNQ
, /* Optional Neon quad precision register */
5895 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5896 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5897 OP_oSHll
, /* LSL immediate */
5898 OP_oSHar
, /* ASR immediate */
5899 OP_oSHllar
, /* LSL or ASR immediate */
5900 OP_oROR
, /* ROR 0/8/16/24 */
5901 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
5903 /* Some pre-defined mixed (ARM/THUMB) operands. */
5904 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5905 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5906 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5908 OP_FIRST_OPTIONAL
= OP_oI7b
5911 /* Generic instruction operand parser. This does no encoding and no
5912 semantic validation; it merely squirrels values away in the inst
5913 structure. Returns SUCCESS or FAIL depending on whether the
5914 specified grammar matched. */
5916 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5918 unsigned const int *upat
= pattern
;
5919 char *backtrack_pos
= 0;
5920 const char *backtrack_error
= 0;
5921 int i
, val
, backtrack_index
= 0;
5922 enum arm_reg_type rtype
;
5923 parse_operand_result result
;
5924 unsigned int op_parse_code
;
5926 #define po_char_or_fail(chr) \
5929 if (skip_past_char (&str, chr) == FAIL) \
5934 #define po_reg_or_fail(regtype) \
5937 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5938 & inst.operands[i].vectype); \
5941 first_error (_(reg_expected_msgs[regtype])); \
5944 inst.operands[i].reg = val; \
5945 inst.operands[i].isreg = 1; \
5946 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5947 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5948 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5949 || rtype == REG_TYPE_VFD \
5950 || rtype == REG_TYPE_NQ); \
5954 #define po_reg_or_goto(regtype, label) \
5957 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5958 & inst.operands[i].vectype); \
5962 inst.operands[i].reg = val; \
5963 inst.operands[i].isreg = 1; \
5964 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5965 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5966 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5967 || rtype == REG_TYPE_VFD \
5968 || rtype == REG_TYPE_NQ); \
5972 #define po_imm_or_fail(min, max, popt) \
5975 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5977 inst.operands[i].imm = val; \
5981 #define po_scalar_or_goto(elsz, label) \
5984 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5987 inst.operands[i].reg = val; \
5988 inst.operands[i].isscalar = 1; \
5992 #define po_misc_or_fail(expr) \
6000 #define po_misc_or_fail_no_backtrack(expr) \
6004 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6005 backtrack_pos = 0; \
6006 if (result != PARSE_OPERAND_SUCCESS) \
6011 #define po_barrier_or_imm(str) \
6014 val = parse_barrier (&str); \
6017 if (ISALPHA (*str)) \
6024 if ((inst.instruction & 0xf0) == 0x60 \
6027 /* ISB can only take SY as an option. */ \
6028 inst.error = _("invalid barrier type"); \
6035 skip_whitespace (str
);
6037 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6039 op_parse_code
= upat
[i
];
6040 if (op_parse_code
>= 1<<16)
6041 op_parse_code
= thumb
? (op_parse_code
>> 16)
6042 : (op_parse_code
& ((1<<16)-1));
6044 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6046 /* Remember where we are in case we need to backtrack. */
6047 gas_assert (!backtrack_pos
);
6048 backtrack_pos
= str
;
6049 backtrack_error
= inst
.error
;
6050 backtrack_index
= i
;
6053 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6054 po_char_or_fail (',');
6056 switch (op_parse_code
)
6064 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6065 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6066 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6067 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6068 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6069 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6071 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6073 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6075 /* Also accept generic coprocessor regs for unknown registers. */
6077 po_reg_or_fail (REG_TYPE_CN
);
6079 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6080 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6081 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6082 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6083 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6084 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6085 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6086 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6087 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6088 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6090 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6092 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6093 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6095 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6097 /* Neon scalar. Using an element size of 8 means that some invalid
6098 scalars are accepted here, so deal with those in later code. */
6099 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6103 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6106 po_imm_or_fail (0, 0, TRUE
);
6111 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6116 po_scalar_or_goto (8, try_rr
);
6119 po_reg_or_fail (REG_TYPE_RN
);
6125 po_scalar_or_goto (8, try_nsdq
);
6128 po_reg_or_fail (REG_TYPE_NSDQ
);
6134 po_scalar_or_goto (8, try_ndq
);
6137 po_reg_or_fail (REG_TYPE_NDQ
);
6143 po_scalar_or_goto (8, try_vfd
);
6146 po_reg_or_fail (REG_TYPE_VFD
);
6151 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6152 not careful then bad things might happen. */
6153 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6158 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6161 /* There's a possibility of getting a 64-bit immediate here, so
6162 we need special handling. */
6163 if (parse_big_immediate (&str
, i
) == FAIL
)
6165 inst
.error
= _("immediate value is out of range");
6173 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6176 po_imm_or_fail (0, 63, TRUE
);
6181 po_char_or_fail ('[');
6182 po_reg_or_fail (REG_TYPE_RN
);
6183 po_char_or_fail (']');
6189 po_reg_or_fail (REG_TYPE_RN
);
6190 if (skip_past_char (&str
, '!') == SUCCESS
)
6191 inst
.operands
[i
].writeback
= 1;
6195 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6196 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6197 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6198 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6199 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6200 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6201 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6202 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6203 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6204 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6205 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6206 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6208 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6210 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6211 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6213 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6214 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6215 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6217 /* Immediate variants */
6219 po_char_or_fail ('{');
6220 po_imm_or_fail (0, 255, TRUE
);
6221 po_char_or_fail ('}');
6225 /* The expression parser chokes on a trailing !, so we have
6226 to find it first and zap it. */
6229 while (*s
&& *s
!= ',')
6234 inst
.operands
[i
].writeback
= 1;
6236 po_imm_or_fail (0, 31, TRUE
);
6244 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6249 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6254 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6256 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6258 val
= parse_reloc (&str
);
6261 inst
.error
= _("unrecognized relocation suffix");
6264 else if (val
!= BFD_RELOC_UNUSED
)
6266 inst
.operands
[i
].imm
= val
;
6267 inst
.operands
[i
].hasreloc
= 1;
6272 /* Operand for MOVW or MOVT. */
6274 po_misc_or_fail (parse_half (&str
));
6277 /* Register or expression. */
6278 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6279 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6281 /* Register or immediate. */
6282 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6283 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6285 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6287 if (!is_immediate_prefix (*str
))
6290 val
= parse_fpa_immediate (&str
);
6293 /* FPA immediates are encoded as registers 8-15.
6294 parse_fpa_immediate has already applied the offset. */
6295 inst
.operands
[i
].reg
= val
;
6296 inst
.operands
[i
].isreg
= 1;
6299 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6300 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6302 /* Two kinds of register. */
6305 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6307 || (rege
->type
!= REG_TYPE_MMXWR
6308 && rege
->type
!= REG_TYPE_MMXWC
6309 && rege
->type
!= REG_TYPE_MMXWCG
))
6311 inst
.error
= _("iWMMXt data or control register expected");
6314 inst
.operands
[i
].reg
= rege
->number
;
6315 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6321 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6323 || (rege
->type
!= REG_TYPE_MMXWC
6324 && rege
->type
!= REG_TYPE_MMXWCG
))
6326 inst
.error
= _("iWMMXt control register expected");
6329 inst
.operands
[i
].reg
= rege
->number
;
6330 inst
.operands
[i
].isreg
= 1;
6335 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6336 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6337 case OP_oROR
: val
= parse_ror (&str
); break;
6338 case OP_PSR
: val
= parse_psr (&str
); break;
6339 case OP_COND
: val
= parse_cond (&str
); break;
6340 case OP_oBARRIER_I15
:
6341 po_barrier_or_imm (str
); break;
6343 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6348 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6349 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6352 val
= parse_psr (&str
);
6356 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6359 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6361 if (strncasecmp (str
, "APSR_", 5) == 0)
6368 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6369 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6370 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6371 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6372 default: found
= 16;
6376 inst
.operands
[i
].isvec
= 1;
6377 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6378 inst
.operands
[i
].reg
= REG_PC
;
6385 po_misc_or_fail (parse_tb (&str
));
6388 /* Register lists. */
6390 val
= parse_reg_list (&str
);
6393 inst
.operands
[1].writeback
= 1;
6399 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6403 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6407 /* Allow Q registers too. */
6408 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6413 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6415 inst
.operands
[i
].issingle
= 1;
6420 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6425 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6426 &inst
.operands
[i
].vectype
);
6429 /* Addressing modes */
6431 po_misc_or_fail (parse_address (&str
, i
));
6435 po_misc_or_fail_no_backtrack (
6436 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6440 po_misc_or_fail_no_backtrack (
6441 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6445 po_misc_or_fail_no_backtrack (
6446 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6450 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6454 po_misc_or_fail_no_backtrack (
6455 parse_shifter_operand_group_reloc (&str
, i
));
6459 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6463 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6467 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6471 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6474 /* Various value-based sanity checks and shared operations. We
6475 do not signal immediate failures for the register constraints;
6476 this allows a syntax error to take precedence. */
6477 switch (op_parse_code
)
6485 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6486 inst
.error
= BAD_PC
;
6491 if (inst
.operands
[i
].isreg
)
6493 if (inst
.operands
[i
].reg
== REG_PC
)
6494 inst
.error
= BAD_PC
;
6495 else if (inst
.operands
[i
].reg
== REG_SP
)
6496 inst
.error
= BAD_SP
;
6501 if (inst
.operands
[i
].isreg
6502 && inst
.operands
[i
].reg
== REG_PC
6503 && (inst
.operands
[i
].writeback
|| thumb
))
6504 inst
.error
= BAD_PC
;
6513 case OP_oBARRIER_I15
:
6522 inst
.operands
[i
].imm
= val
;
6529 /* If we get here, this operand was successfully parsed. */
6530 inst
.operands
[i
].present
= 1;
6534 inst
.error
= BAD_ARGS
;
6539 /* The parse routine should already have set inst.error, but set a
6540 default here just in case. */
6542 inst
.error
= _("syntax error");
6546 /* Do not backtrack over a trailing optional argument that
6547 absorbed some text. We will only fail again, with the
6548 'garbage following instruction' error message, which is
6549 probably less helpful than the current one. */
6550 if (backtrack_index
== i
&& backtrack_pos
!= str
6551 && upat
[i
+1] == OP_stop
)
6554 inst
.error
= _("syntax error");
6558 /* Try again, skipping the optional argument at backtrack_pos. */
6559 str
= backtrack_pos
;
6560 inst
.error
= backtrack_error
;
6561 inst
.operands
[backtrack_index
].present
= 0;
6562 i
= backtrack_index
;
6566 /* Check that we have parsed all the arguments. */
6567 if (*str
!= '\0' && !inst
.error
)
6568 inst
.error
= _("garbage following instruction");
6570 return inst
.error
? FAIL
: SUCCESS
;
6573 #undef po_char_or_fail
6574 #undef po_reg_or_fail
6575 #undef po_reg_or_goto
6576 #undef po_imm_or_fail
6577 #undef po_scalar_or_fail
6578 #undef po_barrier_or_imm
6580 /* Shorthand macro for instruction encoding functions issuing errors. */
6581 #define constraint(expr, err) \
6592 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6593 instructions are unpredictable if these registers are used. This
6594 is the BadReg predicate in ARM's Thumb-2 documentation. */
6595 #define reject_bad_reg(reg) \
6597 if (reg == REG_SP || reg == REG_PC) \
6599 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6604 /* If REG is R13 (the stack pointer), warn that its use is
6606 #define warn_deprecated_sp(reg) \
6608 if (warn_on_deprecated && reg == REG_SP) \
6609 as_warn (_("use of r13 is deprecated")); \
6612 /* Functions for operand encoding. ARM, then Thumb. */
6614 #define rotate_left(v, n) (v << n | v >> (32 - n))
6616 /* If VAL can be encoded in the immediate field of an ARM instruction,
6617 return the encoded form. Otherwise, return FAIL. */
6620 encode_arm_immediate (unsigned int val
)
6624 for (i
= 0; i
< 32; i
+= 2)
6625 if ((a
= rotate_left (val
, i
)) <= 0xff)
6626 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6631 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6632 return the encoded form. Otherwise, return FAIL. */
6634 encode_thumb32_immediate (unsigned int val
)
6641 for (i
= 1; i
<= 24; i
++)
6644 if ((val
& ~(0xff << i
)) == 0)
6645 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6649 if (val
== ((a
<< 16) | a
))
6651 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6655 if (val
== ((a
<< 16) | a
))
6656 return 0x200 | (a
>> 8);
6660 /* Encode a VFP SP or DP register number into inst.instruction. */
6663 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6665 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6668 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6671 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6674 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6679 first_error (_("D register out of range for selected VFP version"));
6687 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6691 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6695 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6699 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6703 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6707 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6715 /* Encode a <shift> in an ARM-format instruction. The immediate,
6716 if any, is handled by md_apply_fix. */
6718 encode_arm_shift (int i
)
6720 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6721 inst
.instruction
|= SHIFT_ROR
<< 5;
6724 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6725 if (inst
.operands
[i
].immisreg
)
6727 inst
.instruction
|= SHIFT_BY_REG
;
6728 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6731 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6736 encode_arm_shifter_operand (int i
)
6738 if (inst
.operands
[i
].isreg
)
6740 inst
.instruction
|= inst
.operands
[i
].reg
;
6741 encode_arm_shift (i
);
6744 inst
.instruction
|= INST_IMMEDIATE
;
6747 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6749 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6751 gas_assert (inst
.operands
[i
].isreg
);
6752 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6754 if (inst
.operands
[i
].preind
)
6758 inst
.error
= _("instruction does not accept preindexed addressing");
6761 inst
.instruction
|= PRE_INDEX
;
6762 if (inst
.operands
[i
].writeback
)
6763 inst
.instruction
|= WRITE_BACK
;
6766 else if (inst
.operands
[i
].postind
)
6768 gas_assert (inst
.operands
[i
].writeback
);
6770 inst
.instruction
|= WRITE_BACK
;
6772 else /* unindexed - only for coprocessor */
6774 inst
.error
= _("instruction does not accept unindexed addressing");
6778 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6779 && (((inst
.instruction
& 0x000f0000) >> 16)
6780 == ((inst
.instruction
& 0x0000f000) >> 12)))
6781 as_warn ((inst
.instruction
& LOAD_BIT
)
6782 ? _("destination register same as write-back base")
6783 : _("source register same as write-back base"));
6786 /* inst.operands[i] was set up by parse_address. Encode it into an
6787 ARM-format mode 2 load or store instruction. If is_t is true,
6788 reject forms that cannot be used with a T instruction (i.e. not
6791 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6793 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6795 encode_arm_addr_mode_common (i
, is_t
);
6797 if (inst
.operands
[i
].immisreg
)
6799 constraint ((inst
.operands
[i
].imm
== REG_PC
6800 || (is_pc
&& inst
.operands
[i
].writeback
)),
6802 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6803 inst
.instruction
|= inst
.operands
[i
].imm
;
6804 if (!inst
.operands
[i
].negative
)
6805 inst
.instruction
|= INDEX_UP
;
6806 if (inst
.operands
[i
].shifted
)
6808 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6809 inst
.instruction
|= SHIFT_ROR
<< 5;
6812 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6813 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6817 else /* immediate offset in inst.reloc */
6819 if (is_pc
&& !inst
.reloc
.pc_rel
)
6821 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6823 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
6824 cannot use PC in addressing.
6825 PC cannot be used in writeback addressing, either. */
6826 constraint ((is_t
|| inst
.operands
[i
].writeback
),
6829 /* Use of PC in str is deprecated for ARMv7. */
6830 if (warn_on_deprecated
6832 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
6833 as_warn (_("use of PC in this instruction is deprecated"));
6836 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6837 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6841 /* inst.operands[i] was set up by parse_address. Encode it into an
6842 ARM-format mode 3 load or store instruction. Reject forms that
6843 cannot be used with such instructions. If is_t is true, reject
6844 forms that cannot be used with a T instruction (i.e. not
6847 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6849 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6851 inst
.error
= _("instruction does not accept scaled register index");
6855 encode_arm_addr_mode_common (i
, is_t
);
6857 if (inst
.operands
[i
].immisreg
)
6859 constraint ((inst
.operands
[i
].imm
== REG_PC
6860 || inst
.operands
[i
].reg
== REG_PC
),
6862 inst
.instruction
|= inst
.operands
[i
].imm
;
6863 if (!inst
.operands
[i
].negative
)
6864 inst
.instruction
|= INDEX_UP
;
6866 else /* immediate offset in inst.reloc */
6868 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6869 && inst
.operands
[i
].writeback
),
6871 inst
.instruction
|= HWOFFSET_IMM
;
6872 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6873 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6877 /* inst.operands[i] was set up by parse_address. Encode it into an
6878 ARM-format instruction. Reject all forms which cannot be encoded
6879 into a coprocessor load/store instruction. If wb_ok is false,
6880 reject use of writeback; if unind_ok is false, reject use of
6881 unindexed addressing. If reloc_override is not 0, use it instead
6882 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6883 (in which case it is preserved). */
6886 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6888 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6890 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6892 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6894 gas_assert (!inst
.operands
[i
].writeback
);
6897 inst
.error
= _("instruction does not support unindexed addressing");
6900 inst
.instruction
|= inst
.operands
[i
].imm
;
6901 inst
.instruction
|= INDEX_UP
;
6905 if (inst
.operands
[i
].preind
)
6906 inst
.instruction
|= PRE_INDEX
;
6908 if (inst
.operands
[i
].writeback
)
6910 if (inst
.operands
[i
].reg
== REG_PC
)
6912 inst
.error
= _("pc may not be used with write-back");
6917 inst
.error
= _("instruction does not support writeback");
6920 inst
.instruction
|= WRITE_BACK
;
6924 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6925 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6926 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6927 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6930 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6932 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6938 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6939 Determine whether it can be performed with a move instruction; if
6940 it can, convert inst.instruction to that move instruction and
6941 return TRUE; if it can't, convert inst.instruction to a literal-pool
6942 load and return FALSE. If this is not a valid thing to do in the
6943 current context, set inst.error and return TRUE.
6945 inst.operands[i] describes the destination register. */
6948 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6953 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6957 if ((inst
.instruction
& tbit
) == 0)
6959 inst
.error
= _("invalid pseudo operation");
6962 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6964 inst
.error
= _("constant expression expected");
6967 if (inst
.reloc
.exp
.X_op
== O_constant
)
6971 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6973 /* This can be done with a mov(1) instruction. */
6974 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6975 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6981 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6984 /* This can be done with a mov instruction. */
6985 inst
.instruction
&= LITERAL_MASK
;
6986 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6987 inst
.instruction
|= value
& 0xfff;
6991 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6994 /* This can be done with a mvn instruction. */
6995 inst
.instruction
&= LITERAL_MASK
;
6996 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6997 inst
.instruction
|= value
& 0xfff;
7003 if (add_to_lit_pool () == FAIL
)
7005 inst
.error
= _("literal pool insertion failed");
7008 inst
.operands
[1].reg
= REG_PC
;
7009 inst
.operands
[1].isreg
= 1;
7010 inst
.operands
[1].preind
= 1;
7011 inst
.reloc
.pc_rel
= 1;
7012 inst
.reloc
.type
= (thumb_p
7013 ? BFD_RELOC_ARM_THUMB_OFFSET
7015 ? BFD_RELOC_ARM_HWLITERAL
7016 : BFD_RELOC_ARM_LITERAL
));
7020 /* Functions for instruction encoding, sorted by sub-architecture.
7021 First some generics; their names are taken from the conventional
7022 bit positions for register arguments in ARM format instructions. */
7032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7039 inst
.instruction
|= inst
.operands
[1].reg
;
7045 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7046 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7052 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7053 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7059 unsigned Rn
= inst
.operands
[2].reg
;
7060 /* Enforce restrictions on SWP instruction. */
7061 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7063 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7064 _("Rn must not overlap other operands"));
7066 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7067 if (warn_on_deprecated
7068 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7069 as_warn (_("swp{b} use is deprecated for this architecture"));
7072 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7073 inst
.instruction
|= inst
.operands
[1].reg
;
7074 inst
.instruction
|= Rn
<< 16;
7080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7082 inst
.instruction
|= inst
.operands
[2].reg
;
7088 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7089 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7090 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7091 || inst
.reloc
.exp
.X_add_number
!= 0),
7093 inst
.instruction
|= inst
.operands
[0].reg
;
7094 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7095 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7101 inst
.instruction
|= inst
.operands
[0].imm
;
7107 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7108 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7111 /* ARM instructions, in alphabetical order by function name (except
7112 that wrapper functions appear immediately after the function they
7115 /* This is a pseudo-op of the form "adr rd, label" to be converted
7116 into a relative address of the form "add rd, pc, #label-.-8". */
7121 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7123 /* Frag hacking will turn this into a sub instruction if the offset turns
7124 out to be negative. */
7125 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7126 inst
.reloc
.pc_rel
= 1;
7127 inst
.reloc
.exp
.X_add_number
-= 8;
7130 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7131 into a relative address of the form:
7132 add rd, pc, #low(label-.-8)"
7133 add rd, rd, #high(label-.-8)" */
7138 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7140 /* Frag hacking will turn this into a sub instruction if the offset turns
7141 out to be negative. */
7142 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7143 inst
.reloc
.pc_rel
= 1;
7144 inst
.size
= INSN_SIZE
* 2;
7145 inst
.reloc
.exp
.X_add_number
-= 8;
7151 if (!inst
.operands
[1].present
)
7152 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7153 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7154 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7155 encode_arm_shifter_operand (2);
7161 if (inst
.operands
[0].present
)
7163 constraint ((inst
.instruction
& 0xf0) != 0x40
7164 && inst
.operands
[0].imm
> 0xf
7165 && inst
.operands
[0].imm
< 0x0,
7166 _("bad barrier type"));
7167 inst
.instruction
|= inst
.operands
[0].imm
;
7170 inst
.instruction
|= 0xf;
7176 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7177 constraint (msb
> 32, _("bit-field extends past end of register"));
7178 /* The instruction encoding stores the LSB and MSB,
7179 not the LSB and width. */
7180 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7181 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7182 inst
.instruction
|= (msb
- 1) << 16;
7190 /* #0 in second position is alternative syntax for bfc, which is
7191 the same instruction but with REG_PC in the Rm field. */
7192 if (!inst
.operands
[1].isreg
)
7193 inst
.operands
[1].reg
= REG_PC
;
7195 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7196 constraint (msb
> 32, _("bit-field extends past end of register"));
7197 /* The instruction encoding stores the LSB and MSB,
7198 not the LSB and width. */
7199 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7200 inst
.instruction
|= inst
.operands
[1].reg
;
7201 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7202 inst
.instruction
|= (msb
- 1) << 16;
7208 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7209 _("bit-field extends past end of register"));
7210 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7211 inst
.instruction
|= inst
.operands
[1].reg
;
7212 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7213 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7216 /* ARM V5 breakpoint instruction (argument parse)
7217 BKPT <16 bit unsigned immediate>
7218 Instruction is not conditional.
7219 The bit pattern given in insns[] has the COND_ALWAYS condition,
7220 and it is an error if the caller tried to override that. */
7225 /* Top 12 of 16 bits to bits 19:8. */
7226 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7228 /* Bottom 4 of 16 bits to bits 3:0. */
7229 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7233 encode_branch (int default_reloc
)
7235 if (inst
.operands
[0].hasreloc
)
7237 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7238 _("the only suffix valid here is '(plt)'"));
7239 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7243 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7245 inst
.reloc
.pc_rel
= 1;
7252 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7253 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7256 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7263 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7265 if (inst
.cond
== COND_ALWAYS
)
7266 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7268 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7272 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7275 /* ARM V5 branch-link-exchange instruction (argument parse)
7276 BLX <target_addr> ie BLX(1)
7277 BLX{<condition>} <Rm> ie BLX(2)
7278 Unfortunately, there are two different opcodes for this mnemonic.
7279 So, the insns[].value is not used, and the code here zaps values
7280 into inst.instruction.
7281 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7286 if (inst
.operands
[0].isreg
)
7288 /* Arg is a register; the opcode provided by insns[] is correct.
7289 It is not illegal to do "blx pc", just useless. */
7290 if (inst
.operands
[0].reg
== REG_PC
)
7291 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7293 inst
.instruction
|= inst
.operands
[0].reg
;
7297 /* Arg is an address; this instruction cannot be executed
7298 conditionally, and the opcode must be adjusted.
7299 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7300 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7301 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7302 inst
.instruction
= 0xfa000000;
7303 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7310 bfd_boolean want_reloc
;
7312 if (inst
.operands
[0].reg
== REG_PC
)
7313 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7315 inst
.instruction
|= inst
.operands
[0].reg
;
7316 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7317 it is for ARMv4t or earlier. */
7318 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7319 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7323 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7328 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7332 /* ARM v5TEJ. Jump to Jazelle code. */
7337 if (inst
.operands
[0].reg
== REG_PC
)
7338 as_tsktsk (_("use of r15 in bxj is not really useful"));
7340 inst
.instruction
|= inst
.operands
[0].reg
;
7343 /* Co-processor data operation:
7344 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7345 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7349 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7350 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7351 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7352 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7353 inst
.instruction
|= inst
.operands
[4].reg
;
7354 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7360 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7361 encode_arm_shifter_operand (1);
7364 /* Transfer between coprocessor and ARM registers.
7365 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7370 No special properties. */
7377 Rd
= inst
.operands
[2].reg
;
7380 if (inst
.instruction
== 0xee000010
7381 || inst
.instruction
== 0xfe000010)
7383 reject_bad_reg (Rd
);
7386 constraint (Rd
== REG_SP
, BAD_SP
);
7391 if (inst
.instruction
== 0xe000010)
7392 constraint (Rd
== REG_PC
, BAD_PC
);
7396 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7397 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7398 inst
.instruction
|= Rd
<< 12;
7399 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7400 inst
.instruction
|= inst
.operands
[4].reg
;
7401 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7404 /* Transfer between coprocessor register and pair of ARM registers.
7405 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7410 Two XScale instructions are special cases of these:
7412 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7413 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7415 Result unpredictable if Rd or Rn is R15. */
7422 Rd
= inst
.operands
[2].reg
;
7423 Rn
= inst
.operands
[3].reg
;
7427 reject_bad_reg (Rd
);
7428 reject_bad_reg (Rn
);
7432 constraint (Rd
== REG_PC
, BAD_PC
);
7433 constraint (Rn
== REG_PC
, BAD_PC
);
7436 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7437 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7438 inst
.instruction
|= Rd
<< 12;
7439 inst
.instruction
|= Rn
<< 16;
7440 inst
.instruction
|= inst
.operands
[4].reg
;
7446 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7447 if (inst
.operands
[1].present
)
7449 inst
.instruction
|= CPSI_MMOD
;
7450 inst
.instruction
|= inst
.operands
[1].imm
;
7457 inst
.instruction
|= inst
.operands
[0].imm
;
7463 /* There is no IT instruction in ARM mode. We
7464 process it to do the validation as if in
7465 thumb mode, just in case the code gets
7466 assembled for thumb using the unified syntax. */
7471 set_it_insn_type (IT_INSN
);
7472 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7473 now_it
.cc
= inst
.operands
[0].imm
;
7480 int base_reg
= inst
.operands
[0].reg
;
7481 int range
= inst
.operands
[1].imm
;
7483 inst
.instruction
|= base_reg
<< 16;
7484 inst
.instruction
|= range
;
7486 if (inst
.operands
[1].writeback
)
7487 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7489 if (inst
.operands
[0].writeback
)
7491 inst
.instruction
|= WRITE_BACK
;
7492 /* Check for unpredictable uses of writeback. */
7493 if (inst
.instruction
& LOAD_BIT
)
7495 /* Not allowed in LDM type 2. */
7496 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7497 && ((range
& (1 << REG_PC
)) == 0))
7498 as_warn (_("writeback of base register is UNPREDICTABLE"));
7499 /* Only allowed if base reg not in list for other types. */
7500 else if (range
& (1 << base_reg
))
7501 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7505 /* Not allowed for type 2. */
7506 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7507 as_warn (_("writeback of base register is UNPREDICTABLE"));
7508 /* Only allowed if base reg not in list, or first in list. */
7509 else if ((range
& (1 << base_reg
))
7510 && (range
& ((1 << base_reg
) - 1)))
7511 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7516 /* ARMv5TE load-consecutive (argument parse)
7525 constraint (inst
.operands
[0].reg
% 2 != 0,
7526 _("first destination register must be even"));
7527 constraint (inst
.operands
[1].present
7528 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7529 _("can only load two consecutive registers"));
7530 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7531 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7533 if (!inst
.operands
[1].present
)
7534 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7536 if (inst
.instruction
& LOAD_BIT
)
7538 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7539 register and the first register written; we have to diagnose
7540 overlap between the base and the second register written here. */
7542 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7543 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7544 as_warn (_("base register written back, and overlaps "
7545 "second destination register"));
7547 /* For an index-register load, the index register must not overlap the
7548 destination (even if not write-back). */
7549 else if (inst
.operands
[2].immisreg
7550 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7551 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7552 as_warn (_("index register overlaps destination register"));
7555 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7556 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7562 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7563 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7564 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7565 || inst
.operands
[1].negative
7566 /* This can arise if the programmer has written
7568 or if they have mistakenly used a register name as the last
7571 It is very difficult to distinguish between these two cases
7572 because "rX" might actually be a label. ie the register
7573 name has been occluded by a symbol of the same name. So we
7574 just generate a general 'bad addressing mode' type error
7575 message and leave it up to the programmer to discover the
7576 true cause and fix their mistake. */
7577 || (inst
.operands
[1].reg
== REG_PC
),
7580 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7581 || inst
.reloc
.exp
.X_add_number
!= 0,
7582 _("offset must be zero in ARM encoding"));
7584 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7586 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7587 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7588 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7594 constraint (inst
.operands
[0].reg
% 2 != 0,
7595 _("even register required"));
7596 constraint (inst
.operands
[1].present
7597 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7598 _("can only load two consecutive registers"));
7599 /* If op 1 were present and equal to PC, this function wouldn't
7600 have been called in the first place. */
7601 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7603 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7604 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7610 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7611 if (!inst
.operands
[1].isreg
)
7612 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7614 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7620 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7622 if (inst
.operands
[1].preind
)
7624 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7625 || inst
.reloc
.exp
.X_add_number
!= 0,
7626 _("this instruction requires a post-indexed address"));
7628 inst
.operands
[1].preind
= 0;
7629 inst
.operands
[1].postind
= 1;
7630 inst
.operands
[1].writeback
= 1;
7632 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7633 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7636 /* Halfword and signed-byte load/store operations. */
7641 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7642 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7643 if (!inst
.operands
[1].isreg
)
7644 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7646 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7652 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7654 if (inst
.operands
[1].preind
)
7656 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7657 || inst
.reloc
.exp
.X_add_number
!= 0,
7658 _("this instruction requires a post-indexed address"));
7660 inst
.operands
[1].preind
= 0;
7661 inst
.operands
[1].postind
= 1;
7662 inst
.operands
[1].writeback
= 1;
7664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7665 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7668 /* Co-processor register load/store.
7669 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7673 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7674 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7675 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7681 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7682 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7683 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7684 && !(inst
.instruction
& 0x00400000))
7685 as_tsktsk (_("Rd and Rm should be different in mla"));
7687 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7688 inst
.instruction
|= inst
.operands
[1].reg
;
7689 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7690 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7696 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7697 encode_arm_shifter_operand (1);
7700 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7707 top
= (inst
.instruction
& 0x00400000) != 0;
7708 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7709 _(":lower16: not allowed this instruction"));
7710 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7711 _(":upper16: not allowed instruction"));
7712 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7713 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7715 imm
= inst
.reloc
.exp
.X_add_number
;
7716 /* The value is in two pieces: 0:11, 16:19. */
7717 inst
.instruction
|= (imm
& 0x00000fff);
7718 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7722 static void do_vfp_nsyn_opcode (const char *);
7725 do_vfp_nsyn_mrs (void)
7727 if (inst
.operands
[0].isvec
)
7729 if (inst
.operands
[1].reg
!= 1)
7730 first_error (_("operand 1 must be FPSCR"));
7731 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7732 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7733 do_vfp_nsyn_opcode ("fmstat");
7735 else if (inst
.operands
[1].isvec
)
7736 do_vfp_nsyn_opcode ("fmrx");
7744 do_vfp_nsyn_msr (void)
7746 if (inst
.operands
[0].isvec
)
7747 do_vfp_nsyn_opcode ("fmxr");
7757 unsigned Rt
= inst
.operands
[0].reg
;
7759 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7761 inst
.error
= BAD_SP
;
7765 /* APSR_ sets isvec. All other refs to PC are illegal. */
7766 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7768 inst
.error
= BAD_PC
;
7772 if (inst
.operands
[1].reg
!= 1)
7773 first_error (_("operand 1 must be FPSCR"));
7775 inst
.instruction
|= (Rt
<< 12);
7781 unsigned Rt
= inst
.operands
[1].reg
;
7784 reject_bad_reg (Rt
);
7785 else if (Rt
== REG_PC
)
7787 inst
.error
= BAD_PC
;
7791 if (inst
.operands
[0].reg
!= 1)
7792 first_error (_("operand 0 must be FPSCR"));
7794 inst
.instruction
|= (Rt
<< 12);
7800 if (do_vfp_nsyn_mrs () == SUCCESS
)
7803 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7804 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7806 _("'CPSR' or 'SPSR' expected"));
7807 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7808 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7809 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7812 /* Two possible forms:
7813 "{C|S}PSR_<field>, Rm",
7814 "{C|S}PSR_f, #expression". */
7819 if (do_vfp_nsyn_msr () == SUCCESS
)
7822 inst
.instruction
|= inst
.operands
[0].imm
;
7823 if (inst
.operands
[1].isreg
)
7824 inst
.instruction
|= inst
.operands
[1].reg
;
7827 inst
.instruction
|= INST_IMMEDIATE
;
7828 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7829 inst
.reloc
.pc_rel
= 0;
7836 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7838 if (!inst
.operands
[2].present
)
7839 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7840 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7841 inst
.instruction
|= inst
.operands
[1].reg
;
7842 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7844 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7845 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7846 as_tsktsk (_("Rd and Rm should be different in mul"));
7849 /* Long Multiply Parser
7850 UMULL RdLo, RdHi, Rm, Rs
7851 SMULL RdLo, RdHi, Rm, Rs
7852 UMLAL RdLo, RdHi, Rm, Rs
7853 SMLAL RdLo, RdHi, Rm, Rs. */
7858 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7859 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7860 inst
.instruction
|= inst
.operands
[2].reg
;
7861 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7863 /* rdhi and rdlo must be different. */
7864 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7865 as_tsktsk (_("rdhi and rdlo must be different"));
7867 /* rdhi, rdlo and rm must all be different before armv6. */
7868 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7869 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7870 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7871 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7877 if (inst
.operands
[0].present
7878 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7880 /* Architectural NOP hints are CPSR sets with no bits selected. */
7881 inst
.instruction
&= 0xf0000000;
7882 inst
.instruction
|= 0x0320f000;
7883 if (inst
.operands
[0].present
)
7884 inst
.instruction
|= inst
.operands
[0].imm
;
7888 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7889 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7890 Condition defaults to COND_ALWAYS.
7891 Error if Rd, Rn or Rm are R15. */
7896 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7897 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7898 inst
.instruction
|= inst
.operands
[2].reg
;
7899 if (inst
.operands
[3].present
)
7900 encode_arm_shift (3);
7903 /* ARM V6 PKHTB (Argument Parse). */
7908 if (!inst
.operands
[3].present
)
7910 /* If the shift specifier is omitted, turn the instruction
7911 into pkhbt rd, rm, rn. */
7912 inst
.instruction
&= 0xfff00010;
7913 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7914 inst
.instruction
|= inst
.operands
[1].reg
;
7915 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7919 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7920 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7921 inst
.instruction
|= inst
.operands
[2].reg
;
7922 encode_arm_shift (3);
7926 /* ARMv5TE: Preload-Cache
7930 Syntactically, like LDR with B=1, W=0, L=1. */
7935 constraint (!inst
.operands
[0].isreg
,
7936 _("'[' expected after PLD mnemonic"));
7937 constraint (inst
.operands
[0].postind
,
7938 _("post-indexed expression used in preload instruction"));
7939 constraint (inst
.operands
[0].writeback
,
7940 _("writeback used in preload instruction"));
7941 constraint (!inst
.operands
[0].preind
,
7942 _("unindexed addressing used in preload instruction"));
7943 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7946 /* ARMv7: PLI <addr_mode> */
7950 constraint (!inst
.operands
[0].isreg
,
7951 _("'[' expected after PLI mnemonic"));
7952 constraint (inst
.operands
[0].postind
,
7953 _("post-indexed expression used in preload instruction"));
7954 constraint (inst
.operands
[0].writeback
,
7955 _("writeback used in preload instruction"));
7956 constraint (!inst
.operands
[0].preind
,
7957 _("unindexed addressing used in preload instruction"));
7958 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7959 inst
.instruction
&= ~PRE_INDEX
;
7965 inst
.operands
[1] = inst
.operands
[0];
7966 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7967 inst
.operands
[0].isreg
= 1;
7968 inst
.operands
[0].writeback
= 1;
7969 inst
.operands
[0].reg
= REG_SP
;
7973 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7974 word at the specified address and the following word
7976 Unconditionally executed.
7977 Error if Rn is R15. */
7982 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7983 if (inst
.operands
[0].writeback
)
7984 inst
.instruction
|= WRITE_BACK
;
7987 /* ARM V6 ssat (argument parse). */
7992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7993 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7994 inst
.instruction
|= inst
.operands
[2].reg
;
7996 if (inst
.operands
[3].present
)
7997 encode_arm_shift (3);
8000 /* ARM V6 usat (argument parse). */
8005 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8006 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8007 inst
.instruction
|= inst
.operands
[2].reg
;
8009 if (inst
.operands
[3].present
)
8010 encode_arm_shift (3);
8013 /* ARM V6 ssat16 (argument parse). */
8018 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8019 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8020 inst
.instruction
|= inst
.operands
[2].reg
;
8026 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8027 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8028 inst
.instruction
|= inst
.operands
[2].reg
;
8031 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8032 preserving the other bits.
8034 setend <endian_specifier>, where <endian_specifier> is either
8040 if (inst
.operands
[0].imm
)
8041 inst
.instruction
|= 0x200;
8047 unsigned int Rm
= (inst
.operands
[1].present
8048 ? inst
.operands
[1].reg
8049 : inst
.operands
[0].reg
);
8051 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8052 inst
.instruction
|= Rm
;
8053 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8055 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8056 inst
.instruction
|= SHIFT_BY_REG
;
8059 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8065 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8066 inst
.reloc
.pc_rel
= 0;
8072 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8073 inst
.reloc
.pc_rel
= 0;
8076 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8077 SMLAxy{cond} Rd,Rm,Rs,Rn
8078 SMLAWy{cond} Rd,Rm,Rs,Rn
8079 Error if any register is R15. */
8084 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8085 inst
.instruction
|= inst
.operands
[1].reg
;
8086 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8087 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8090 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8091 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8092 Error if any register is R15.
8093 Warning if Rdlo == Rdhi. */
8098 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8099 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8100 inst
.instruction
|= inst
.operands
[2].reg
;
8101 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8103 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8104 as_tsktsk (_("rdhi and rdlo must be different"));
8107 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8108 SMULxy{cond} Rd,Rm,Rs
8109 Error if any register is R15. */
8114 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8115 inst
.instruction
|= inst
.operands
[1].reg
;
8116 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8119 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8120 the same for both ARM and Thumb-2. */
8127 if (inst
.operands
[0].present
)
8129 reg
= inst
.operands
[0].reg
;
8130 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8135 inst
.instruction
|= reg
<< 16;
8136 inst
.instruction
|= inst
.operands
[1].imm
;
8137 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8138 inst
.instruction
|= WRITE_BACK
;
8141 /* ARM V6 strex (argument parse). */
8146 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8147 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8148 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8149 || inst
.operands
[2].negative
8150 /* See comment in do_ldrex(). */
8151 || (inst
.operands
[2].reg
== REG_PC
),
8154 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8155 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8157 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8158 || inst
.reloc
.exp
.X_add_number
!= 0,
8159 _("offset must be zero in ARM encoding"));
8161 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8162 inst
.instruction
|= inst
.operands
[1].reg
;
8163 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8164 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8170 constraint (inst
.operands
[1].reg
% 2 != 0,
8171 _("even register required"));
8172 constraint (inst
.operands
[2].present
8173 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8174 _("can only store two consecutive registers"));
8175 /* If op 2 were present and equal to PC, this function wouldn't
8176 have been called in the first place. */
8177 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8179 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8180 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8181 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8185 inst
.instruction
|= inst
.operands
[1].reg
;
8186 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8189 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8190 extends it to 32-bits, and adds the result to a value in another
8191 register. You can specify a rotation by 0, 8, 16, or 24 bits
8192 before extracting the 16-bit value.
8193 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8194 Condition defaults to COND_ALWAYS.
8195 Error if any register uses R15. */
8200 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8201 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8202 inst
.instruction
|= inst
.operands
[2].reg
;
8203 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8208 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8209 Condition defaults to COND_ALWAYS.
8210 Error if any register uses R15. */
8215 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8216 inst
.instruction
|= inst
.operands
[1].reg
;
8217 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8220 /* VFP instructions. In a logical order: SP variant first, monad
8221 before dyad, arithmetic then move then load/store. */
8224 do_vfp_sp_monadic (void)
8226 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8227 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8231 do_vfp_sp_dyadic (void)
8233 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8234 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8235 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8239 do_vfp_sp_compare_z (void)
8241 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8245 do_vfp_dp_sp_cvt (void)
8247 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8248 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8252 do_vfp_sp_dp_cvt (void)
8254 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8255 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8259 do_vfp_reg_from_sp (void)
8261 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8262 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8266 do_vfp_reg2_from_sp2 (void)
8268 constraint (inst
.operands
[2].imm
!= 2,
8269 _("only two consecutive VFP SP registers allowed here"));
8270 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8271 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8272 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8276 do_vfp_sp_from_reg (void)
8278 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8279 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8283 do_vfp_sp2_from_reg2 (void)
8285 constraint (inst
.operands
[0].imm
!= 2,
8286 _("only two consecutive VFP SP registers allowed here"));
8287 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8288 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8289 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8293 do_vfp_sp_ldst (void)
8295 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8296 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8300 do_vfp_dp_ldst (void)
8302 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8303 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8308 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8310 if (inst
.operands
[0].writeback
)
8311 inst
.instruction
|= WRITE_BACK
;
8313 constraint (ldstm_type
!= VFP_LDSTMIA
,
8314 _("this addressing mode requires base-register writeback"));
8315 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8316 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8317 inst
.instruction
|= inst
.operands
[1].imm
;
8321 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8325 if (inst
.operands
[0].writeback
)
8326 inst
.instruction
|= WRITE_BACK
;
8328 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8329 _("this addressing mode requires base-register writeback"));
8331 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8332 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8334 count
= inst
.operands
[1].imm
<< 1;
8335 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8338 inst
.instruction
|= count
;
8342 do_vfp_sp_ldstmia (void)
8344 vfp_sp_ldstm (VFP_LDSTMIA
);
8348 do_vfp_sp_ldstmdb (void)
8350 vfp_sp_ldstm (VFP_LDSTMDB
);
8354 do_vfp_dp_ldstmia (void)
8356 vfp_dp_ldstm (VFP_LDSTMIA
);
8360 do_vfp_dp_ldstmdb (void)
8362 vfp_dp_ldstm (VFP_LDSTMDB
);
8366 do_vfp_xp_ldstmia (void)
8368 vfp_dp_ldstm (VFP_LDSTMIAX
);
8372 do_vfp_xp_ldstmdb (void)
8374 vfp_dp_ldstm (VFP_LDSTMDBX
);
8378 do_vfp_dp_rd_rm (void)
8380 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8381 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8385 do_vfp_dp_rn_rd (void)
8387 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8388 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8392 do_vfp_dp_rd_rn (void)
8394 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8395 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8399 do_vfp_dp_rd_rn_rm (void)
8401 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8402 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8403 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8409 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8413 do_vfp_dp_rm_rd_rn (void)
8415 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8416 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8417 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8420 /* VFPv3 instructions. */
8422 do_vfp_sp_const (void)
8424 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8425 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8426 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8430 do_vfp_dp_const (void)
8432 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8433 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8434 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8438 vfp_conv (int srcsize
)
8440 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8441 inst
.instruction
|= (immbits
& 1) << 5;
8442 inst
.instruction
|= (immbits
>> 1);
8446 do_vfp_sp_conv_16 (void)
8448 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8453 do_vfp_dp_conv_16 (void)
8455 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8460 do_vfp_sp_conv_32 (void)
8462 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8467 do_vfp_dp_conv_32 (void)
8469 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8473 /* FPA instructions. Also in a logical order. */
8478 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8479 inst
.instruction
|= inst
.operands
[1].reg
;
8483 do_fpa_ldmstm (void)
8485 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8486 switch (inst
.operands
[1].imm
)
8488 case 1: inst
.instruction
|= CP_T_X
; break;
8489 case 2: inst
.instruction
|= CP_T_Y
; break;
8490 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8495 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8497 /* The instruction specified "ea" or "fd", so we can only accept
8498 [Rn]{!}. The instruction does not really support stacking or
8499 unstacking, so we have to emulate these by setting appropriate
8500 bits and offsets. */
8501 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8502 || inst
.reloc
.exp
.X_add_number
!= 0,
8503 _("this instruction does not support indexing"));
8505 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8506 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8508 if (!(inst
.instruction
& INDEX_UP
))
8509 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8511 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8513 inst
.operands
[2].preind
= 0;
8514 inst
.operands
[2].postind
= 1;
8518 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8521 /* iWMMXt instructions: strictly in alphabetical order. */
8524 do_iwmmxt_tandorc (void)
8526 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8530 do_iwmmxt_textrc (void)
8532 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8533 inst
.instruction
|= inst
.operands
[1].imm
;
8537 do_iwmmxt_textrm (void)
8539 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8540 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8541 inst
.instruction
|= inst
.operands
[2].imm
;
8545 do_iwmmxt_tinsr (void)
8547 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8548 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8549 inst
.instruction
|= inst
.operands
[2].imm
;
8553 do_iwmmxt_tmia (void)
8555 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8556 inst
.instruction
|= inst
.operands
[1].reg
;
8557 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8561 do_iwmmxt_waligni (void)
8563 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8564 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8565 inst
.instruction
|= inst
.operands
[2].reg
;
8566 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8570 do_iwmmxt_wmerge (void)
8572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8573 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8574 inst
.instruction
|= inst
.operands
[2].reg
;
8575 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8579 do_iwmmxt_wmov (void)
8581 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8582 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8583 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8584 inst
.instruction
|= inst
.operands
[1].reg
;
8588 do_iwmmxt_wldstbh (void)
8591 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8593 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8595 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8596 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8600 do_iwmmxt_wldstw (void)
8602 /* RIWR_RIWC clears .isreg for a control register. */
8603 if (!inst
.operands
[0].isreg
)
8605 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8606 inst
.instruction
|= 0xf0000000;
8609 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8610 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8614 do_iwmmxt_wldstd (void)
8616 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8617 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8618 && inst
.operands
[1].immisreg
)
8620 inst
.instruction
&= ~0x1a000ff;
8621 inst
.instruction
|= (0xf << 28);
8622 if (inst
.operands
[1].preind
)
8623 inst
.instruction
|= PRE_INDEX
;
8624 if (!inst
.operands
[1].negative
)
8625 inst
.instruction
|= INDEX_UP
;
8626 if (inst
.operands
[1].writeback
)
8627 inst
.instruction
|= WRITE_BACK
;
8628 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8629 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8630 inst
.instruction
|= inst
.operands
[1].imm
;
8633 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8637 do_iwmmxt_wshufh (void)
8639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8640 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8641 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8642 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8646 do_iwmmxt_wzero (void)
8648 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8649 inst
.instruction
|= inst
.operands
[0].reg
;
8650 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8651 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8655 do_iwmmxt_wrwrwr_or_imm5 (void)
8657 if (inst
.operands
[2].isreg
)
8660 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8661 _("immediate operand requires iWMMXt2"));
8663 if (inst
.operands
[2].imm
== 0)
8665 switch ((inst
.instruction
>> 20) & 0xf)
8671 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8672 inst
.operands
[2].imm
= 16;
8673 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8679 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8680 inst
.operands
[2].imm
= 32;
8681 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8688 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8690 wrn
= (inst
.instruction
>> 16) & 0xf;
8691 inst
.instruction
&= 0xff0fff0f;
8692 inst
.instruction
|= wrn
;
8693 /* Bail out here; the instruction is now assembled. */
8698 /* Map 32 -> 0, etc. */
8699 inst
.operands
[2].imm
&= 0x1f;
8700 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8704 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8705 operations first, then control, shift, and load/store. */
8707 /* Insns like "foo X,Y,Z". */
8710 do_mav_triple (void)
8712 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8713 inst
.instruction
|= inst
.operands
[1].reg
;
8714 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8717 /* Insns like "foo W,X,Y,Z".
8718 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8723 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8724 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8725 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8726 inst
.instruction
|= inst
.operands
[3].reg
;
8729 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8733 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8736 /* Maverick shift immediate instructions.
8737 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8738 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8743 int imm
= inst
.operands
[2].imm
;
8745 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8746 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8748 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8749 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8750 Bit 4 should be 0. */
8751 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8753 inst
.instruction
|= imm
;
8756 /* XScale instructions. Also sorted arithmetic before move. */
8758 /* Xscale multiply-accumulate (argument parse)
8761 MIAxycc acc0,Rm,Rs. */
8766 inst
.instruction
|= inst
.operands
[1].reg
;
8767 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8770 /* Xscale move-accumulator-register (argument parse)
8772 MARcc acc0,RdLo,RdHi. */
8777 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8778 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8781 /* Xscale move-register-accumulator (argument parse)
8783 MRAcc RdLo,RdHi,acc0. */
8788 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8789 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8790 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8793 /* Encoding functions relevant only to Thumb. */
8795 /* inst.operands[i] is a shifted-register operand; encode
8796 it into inst.instruction in the format used by Thumb32. */
8799 encode_thumb32_shifted_operand (int i
)
8801 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8802 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8804 constraint (inst
.operands
[i
].immisreg
,
8805 _("shift by register not allowed in thumb mode"));
8806 inst
.instruction
|= inst
.operands
[i
].reg
;
8807 if (shift
== SHIFT_RRX
)
8808 inst
.instruction
|= SHIFT_ROR
<< 4;
8811 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8812 _("expression too complex"));
8814 constraint (value
> 32
8815 || (value
== 32 && (shift
== SHIFT_LSL
8816 || shift
== SHIFT_ROR
)),
8817 _("shift expression is too large"));
8821 else if (value
== 32)
8824 inst
.instruction
|= shift
<< 4;
8825 inst
.instruction
|= (value
& 0x1c) << 10;
8826 inst
.instruction
|= (value
& 0x03) << 6;
8831 /* inst.operands[i] was set up by parse_address. Encode it into a
8832 Thumb32 format load or store instruction. Reject forms that cannot
8833 be used with such instructions. If is_t is true, reject forms that
8834 cannot be used with a T instruction; if is_d is true, reject forms
8835 that cannot be used with a D instruction. If it is a store insn,
8839 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8841 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8843 constraint (!inst
.operands
[i
].isreg
,
8844 _("Instruction does not support =N addresses"));
8846 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8847 if (inst
.operands
[i
].immisreg
)
8849 constraint (is_pc
, BAD_PC_ADDRESSING
);
8850 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8851 constraint (inst
.operands
[i
].negative
,
8852 _("Thumb does not support negative register indexing"));
8853 constraint (inst
.operands
[i
].postind
,
8854 _("Thumb does not support register post-indexing"));
8855 constraint (inst
.operands
[i
].writeback
,
8856 _("Thumb does not support register indexing with writeback"));
8857 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8858 _("Thumb supports only LSL in shifted register indexing"));
8860 inst
.instruction
|= inst
.operands
[i
].imm
;
8861 if (inst
.operands
[i
].shifted
)
8863 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8864 _("expression too complex"));
8865 constraint (inst
.reloc
.exp
.X_add_number
< 0
8866 || inst
.reloc
.exp
.X_add_number
> 3,
8867 _("shift out of range"));
8868 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8870 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8872 else if (inst
.operands
[i
].preind
)
8874 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8875 constraint (is_t
&& inst
.operands
[i
].writeback
,
8876 _("cannot use writeback with this instruction"));
8877 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8878 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8882 inst
.instruction
|= 0x01000000;
8883 if (inst
.operands
[i
].writeback
)
8884 inst
.instruction
|= 0x00200000;
8888 inst
.instruction
|= 0x00000c00;
8889 if (inst
.operands
[i
].writeback
)
8890 inst
.instruction
|= 0x00000100;
8892 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8894 else if (inst
.operands
[i
].postind
)
8896 gas_assert (inst
.operands
[i
].writeback
);
8897 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8898 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8901 inst
.instruction
|= 0x00200000;
8903 inst
.instruction
|= 0x00000900;
8904 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8906 else /* unindexed - only for coprocessor */
8907 inst
.error
= _("instruction does not accept unindexed addressing");
8910 /* Table of Thumb instructions which exist in both 16- and 32-bit
8911 encodings (the latter only in post-V6T2 cores). The index is the
8912 value used in the insns table below. When there is more than one
8913 possible 16-bit encoding for the instruction, this table always
8915 Also contains several pseudo-instructions used during relaxation. */
8916 #define T16_32_TAB \
8917 X(_adc, 4140, eb400000), \
8918 X(_adcs, 4140, eb500000), \
8919 X(_add, 1c00, eb000000), \
8920 X(_adds, 1c00, eb100000), \
8921 X(_addi, 0000, f1000000), \
8922 X(_addis, 0000, f1100000), \
8923 X(_add_pc,000f, f20f0000), \
8924 X(_add_sp,000d, f10d0000), \
8925 X(_adr, 000f, f20f0000), \
8926 X(_and, 4000, ea000000), \
8927 X(_ands, 4000, ea100000), \
8928 X(_asr, 1000, fa40f000), \
8929 X(_asrs, 1000, fa50f000), \
8930 X(_b, e000, f000b000), \
8931 X(_bcond, d000, f0008000), \
8932 X(_bic, 4380, ea200000), \
8933 X(_bics, 4380, ea300000), \
8934 X(_cmn, 42c0, eb100f00), \
8935 X(_cmp, 2800, ebb00f00), \
8936 X(_cpsie, b660, f3af8400), \
8937 X(_cpsid, b670, f3af8600), \
8938 X(_cpy, 4600, ea4f0000), \
8939 X(_dec_sp,80dd, f1ad0d00), \
8940 X(_eor, 4040, ea800000), \
8941 X(_eors, 4040, ea900000), \
8942 X(_inc_sp,00dd, f10d0d00), \
8943 X(_ldmia, c800, e8900000), \
8944 X(_ldr, 6800, f8500000), \
8945 X(_ldrb, 7800, f8100000), \
8946 X(_ldrh, 8800, f8300000), \
8947 X(_ldrsb, 5600, f9100000), \
8948 X(_ldrsh, 5e00, f9300000), \
8949 X(_ldr_pc,4800, f85f0000), \
8950 X(_ldr_pc2,4800, f85f0000), \
8951 X(_ldr_sp,9800, f85d0000), \
8952 X(_lsl, 0000, fa00f000), \
8953 X(_lsls, 0000, fa10f000), \
8954 X(_lsr, 0800, fa20f000), \
8955 X(_lsrs, 0800, fa30f000), \
8956 X(_mov, 2000, ea4f0000), \
8957 X(_movs, 2000, ea5f0000), \
8958 X(_mul, 4340, fb00f000), \
8959 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8960 X(_mvn, 43c0, ea6f0000), \
8961 X(_mvns, 43c0, ea7f0000), \
8962 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8963 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8964 X(_orr, 4300, ea400000), \
8965 X(_orrs, 4300, ea500000), \
8966 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8967 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8968 X(_rev, ba00, fa90f080), \
8969 X(_rev16, ba40, fa90f090), \
8970 X(_revsh, bac0, fa90f0b0), \
8971 X(_ror, 41c0, fa60f000), \
8972 X(_rors, 41c0, fa70f000), \
8973 X(_sbc, 4180, eb600000), \
8974 X(_sbcs, 4180, eb700000), \
8975 X(_stmia, c000, e8800000), \
8976 X(_str, 6000, f8400000), \
8977 X(_strb, 7000, f8000000), \
8978 X(_strh, 8000, f8200000), \
8979 X(_str_sp,9000, f84d0000), \
8980 X(_sub, 1e00, eba00000), \
8981 X(_subs, 1e00, ebb00000), \
8982 X(_subi, 8000, f1a00000), \
8983 X(_subis, 8000, f1b00000), \
8984 X(_sxtb, b240, fa4ff080), \
8985 X(_sxth, b200, fa0ff080), \
8986 X(_tst, 4200, ea100f00), \
8987 X(_uxtb, b2c0, fa5ff080), \
8988 X(_uxth, b280, fa1ff080), \
8989 X(_nop, bf00, f3af8000), \
8990 X(_yield, bf10, f3af8001), \
8991 X(_wfe, bf20, f3af8002), \
8992 X(_wfi, bf30, f3af8003), \
8993 X(_sev, bf40, f3af8004),
8995 /* To catch errors in encoding functions, the codes are all offset by
8996 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8997 as 16-bit instructions. */
8998 #define X(a,b,c) T_MNEM##a
8999 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9002 #define X(a,b,c) 0x##b
9003 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9004 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9007 #define X(a,b,c) 0x##c
9008 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9009 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9010 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9014 /* Thumb instruction encoders, in alphabetical order. */
9019 do_t_add_sub_w (void)
9023 Rd
= inst
.operands
[0].reg
;
9024 Rn
= inst
.operands
[1].reg
;
9026 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9027 is the SP-{plus,minus}-immediate form of the instruction. */
9029 constraint (Rd
== REG_PC
, BAD_PC
);
9031 reject_bad_reg (Rd
);
9033 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9034 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9037 /* Parse an add or subtract instruction. We get here with inst.instruction
9038 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9045 Rd
= inst
.operands
[0].reg
;
9046 Rs
= (inst
.operands
[1].present
9047 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9048 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9051 set_it_insn_type_last ();
9059 flags
= (inst
.instruction
== T_MNEM_adds
9060 || inst
.instruction
== T_MNEM_subs
);
9062 narrow
= !in_it_block ();
9064 narrow
= in_it_block ();
9065 if (!inst
.operands
[2].isreg
)
9069 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9071 add
= (inst
.instruction
== T_MNEM_add
9072 || inst
.instruction
== T_MNEM_adds
);
9074 if (inst
.size_req
!= 4)
9076 /* Attempt to use a narrow opcode, with relaxation if
9078 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9079 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9080 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9081 opcode
= T_MNEM_add_sp
;
9082 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9083 opcode
= T_MNEM_add_pc
;
9084 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9087 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9089 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9093 inst
.instruction
= THUMB_OP16(opcode
);
9094 inst
.instruction
|= (Rd
<< 4) | Rs
;
9095 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9096 if (inst
.size_req
!= 2)
9097 inst
.relax
= opcode
;
9100 constraint (inst
.size_req
== 2, BAD_HIREG
);
9102 if (inst
.size_req
== 4
9103 || (inst
.size_req
!= 2 && !opcode
))
9107 constraint (add
, BAD_PC
);
9108 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9109 _("only SUBS PC, LR, #const allowed"));
9110 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9111 _("expression too complex"));
9112 constraint (inst
.reloc
.exp
.X_add_number
< 0
9113 || inst
.reloc
.exp
.X_add_number
> 0xff,
9114 _("immediate value out of range"));
9115 inst
.instruction
= T2_SUBS_PC_LR
9116 | inst
.reloc
.exp
.X_add_number
;
9117 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9120 else if (Rs
== REG_PC
)
9122 /* Always use addw/subw. */
9123 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9124 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9128 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9129 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9132 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9134 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9136 inst
.instruction
|= Rd
<< 8;
9137 inst
.instruction
|= Rs
<< 16;
9142 Rn
= inst
.operands
[2].reg
;
9143 /* See if we can do this with a 16-bit instruction. */
9144 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9146 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9151 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9152 || inst
.instruction
== T_MNEM_add
)
9155 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9159 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9161 /* Thumb-1 cores (except v6-M) require at least one high
9162 register in a narrow non flag setting add. */
9163 if (Rd
> 7 || Rn
> 7
9164 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9165 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9172 inst
.instruction
= T_OPCODE_ADD_HI
;
9173 inst
.instruction
|= (Rd
& 8) << 4;
9174 inst
.instruction
|= (Rd
& 7);
9175 inst
.instruction
|= Rn
<< 3;
9181 constraint (Rd
== REG_PC
, BAD_PC
);
9182 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9183 constraint (Rs
== REG_PC
, BAD_PC
);
9184 reject_bad_reg (Rn
);
9186 /* If we get here, it can't be done in 16 bits. */
9187 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9188 _("shift must be constant"));
9189 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9190 inst
.instruction
|= Rd
<< 8;
9191 inst
.instruction
|= Rs
<< 16;
9192 encode_thumb32_shifted_operand (2);
9197 constraint (inst
.instruction
== T_MNEM_adds
9198 || inst
.instruction
== T_MNEM_subs
,
9201 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9203 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9204 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9207 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9209 inst
.instruction
|= (Rd
<< 4) | Rs
;
9210 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9214 Rn
= inst
.operands
[2].reg
;
9215 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9217 /* We now have Rd, Rs, and Rn set to registers. */
9218 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9220 /* Can't do this for SUB. */
9221 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9222 inst
.instruction
= T_OPCODE_ADD_HI
;
9223 inst
.instruction
|= (Rd
& 8) << 4;
9224 inst
.instruction
|= (Rd
& 7);
9226 inst
.instruction
|= Rn
<< 3;
9228 inst
.instruction
|= Rs
<< 3;
9230 constraint (1, _("dest must overlap one source register"));
9234 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9235 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9236 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9246 Rd
= inst
.operands
[0].reg
;
9247 reject_bad_reg (Rd
);
9249 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9251 /* Defer to section relaxation. */
9252 inst
.relax
= inst
.instruction
;
9253 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9254 inst
.instruction
|= Rd
<< 4;
9256 else if (unified_syntax
&& inst
.size_req
!= 2)
9258 /* Generate a 32-bit opcode. */
9259 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9260 inst
.instruction
|= Rd
<< 8;
9261 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9262 inst
.reloc
.pc_rel
= 1;
9266 /* Generate a 16-bit opcode. */
9267 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9268 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9269 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9270 inst
.reloc
.pc_rel
= 1;
9272 inst
.instruction
|= Rd
<< 4;
9276 /* Arithmetic instructions for which there is just one 16-bit
9277 instruction encoding, and it allows only two low registers.
9278 For maximal compatibility with ARM syntax, we allow three register
9279 operands even when Thumb-32 instructions are not available, as long
9280 as the first two are identical. For instance, both "sbc r0,r1" and
9281 "sbc r0,r0,r1" are allowed. */
9287 Rd
= inst
.operands
[0].reg
;
9288 Rs
= (inst
.operands
[1].present
9289 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9290 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9291 Rn
= inst
.operands
[2].reg
;
9293 reject_bad_reg (Rd
);
9294 reject_bad_reg (Rs
);
9295 if (inst
.operands
[2].isreg
)
9296 reject_bad_reg (Rn
);
9300 if (!inst
.operands
[2].isreg
)
9302 /* For an immediate, we always generate a 32-bit opcode;
9303 section relaxation will shrink it later if possible. */
9304 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9305 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9306 inst
.instruction
|= Rd
<< 8;
9307 inst
.instruction
|= Rs
<< 16;
9308 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9314 /* See if we can do this with a 16-bit instruction. */
9315 if (THUMB_SETS_FLAGS (inst
.instruction
))
9316 narrow
= !in_it_block ();
9318 narrow
= in_it_block ();
9320 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9322 if (inst
.operands
[2].shifted
)
9324 if (inst
.size_req
== 4)
9330 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9331 inst
.instruction
|= Rd
;
9332 inst
.instruction
|= Rn
<< 3;
9336 /* If we get here, it can't be done in 16 bits. */
9337 constraint (inst
.operands
[2].shifted
9338 && inst
.operands
[2].immisreg
,
9339 _("shift must be constant"));
9340 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9341 inst
.instruction
|= Rd
<< 8;
9342 inst
.instruction
|= Rs
<< 16;
9343 encode_thumb32_shifted_operand (2);
9348 /* On its face this is a lie - the instruction does set the
9349 flags. However, the only supported mnemonic in this mode
9351 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9353 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9354 _("unshifted register required"));
9355 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9356 constraint (Rd
!= Rs
,
9357 _("dest and source1 must be the same register"));
9359 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9360 inst
.instruction
|= Rd
;
9361 inst
.instruction
|= Rn
<< 3;
9365 /* Similarly, but for instructions where the arithmetic operation is
9366 commutative, so we can allow either of them to be different from
9367 the destination operand in a 16-bit instruction. For instance, all
9368 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9375 Rd
= inst
.operands
[0].reg
;
9376 Rs
= (inst
.operands
[1].present
9377 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9378 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9379 Rn
= inst
.operands
[2].reg
;
9381 reject_bad_reg (Rd
);
9382 reject_bad_reg (Rs
);
9383 if (inst
.operands
[2].isreg
)
9384 reject_bad_reg (Rn
);
9388 if (!inst
.operands
[2].isreg
)
9390 /* For an immediate, we always generate a 32-bit opcode;
9391 section relaxation will shrink it later if possible. */
9392 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9393 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9394 inst
.instruction
|= Rd
<< 8;
9395 inst
.instruction
|= Rs
<< 16;
9396 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9402 /* See if we can do this with a 16-bit instruction. */
9403 if (THUMB_SETS_FLAGS (inst
.instruction
))
9404 narrow
= !in_it_block ();
9406 narrow
= in_it_block ();
9408 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9410 if (inst
.operands
[2].shifted
)
9412 if (inst
.size_req
== 4)
9419 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9420 inst
.instruction
|= Rd
;
9421 inst
.instruction
|= Rn
<< 3;
9426 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9427 inst
.instruction
|= Rd
;
9428 inst
.instruction
|= Rs
<< 3;
9433 /* If we get here, it can't be done in 16 bits. */
9434 constraint (inst
.operands
[2].shifted
9435 && inst
.operands
[2].immisreg
,
9436 _("shift must be constant"));
9437 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9438 inst
.instruction
|= Rd
<< 8;
9439 inst
.instruction
|= Rs
<< 16;
9440 encode_thumb32_shifted_operand (2);
9445 /* On its face this is a lie - the instruction does set the
9446 flags. However, the only supported mnemonic in this mode
9448 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9450 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9451 _("unshifted register required"));
9452 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9454 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9455 inst
.instruction
|= Rd
;
9458 inst
.instruction
|= Rn
<< 3;
9460 inst
.instruction
|= Rs
<< 3;
9462 constraint (1, _("dest must overlap one source register"));
9469 if (inst
.operands
[0].present
)
9471 constraint ((inst
.instruction
& 0xf0) != 0x40
9472 && inst
.operands
[0].imm
> 0xf
9473 && inst
.operands
[0].imm
< 0x0,
9474 _("bad barrier type"));
9475 inst
.instruction
|= inst
.operands
[0].imm
;
9478 inst
.instruction
|= 0xf;
9485 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9486 constraint (msb
> 32, _("bit-field extends past end of register"));
9487 /* The instruction encoding stores the LSB and MSB,
9488 not the LSB and width. */
9489 Rd
= inst
.operands
[0].reg
;
9490 reject_bad_reg (Rd
);
9491 inst
.instruction
|= Rd
<< 8;
9492 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9493 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9494 inst
.instruction
|= msb
- 1;
9503 Rd
= inst
.operands
[0].reg
;
9504 reject_bad_reg (Rd
);
9506 /* #0 in second position is alternative syntax for bfc, which is
9507 the same instruction but with REG_PC in the Rm field. */
9508 if (!inst
.operands
[1].isreg
)
9512 Rn
= inst
.operands
[1].reg
;
9513 reject_bad_reg (Rn
);
9516 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9517 constraint (msb
> 32, _("bit-field extends past end of register"));
9518 /* The instruction encoding stores the LSB and MSB,
9519 not the LSB and width. */
9520 inst
.instruction
|= Rd
<< 8;
9521 inst
.instruction
|= Rn
<< 16;
9522 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9523 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9524 inst
.instruction
|= msb
- 1;
9532 Rd
= inst
.operands
[0].reg
;
9533 Rn
= inst
.operands
[1].reg
;
9535 reject_bad_reg (Rd
);
9536 reject_bad_reg (Rn
);
9538 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9539 _("bit-field extends past end of register"));
9540 inst
.instruction
|= Rd
<< 8;
9541 inst
.instruction
|= Rn
<< 16;
9542 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9543 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9544 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9547 /* ARM V5 Thumb BLX (argument parse)
9548 BLX <target_addr> which is BLX(1)
9549 BLX <Rm> which is BLX(2)
9550 Unfortunately, there are two different opcodes for this mnemonic.
9551 So, the insns[].value is not used, and the code here zaps values
9552 into inst.instruction.
9554 ??? How to take advantage of the additional two bits of displacement
9555 available in Thumb32 mode? Need new relocation? */
9560 set_it_insn_type_last ();
9562 if (inst
.operands
[0].isreg
)
9564 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9565 /* We have a register, so this is BLX(2). */
9566 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9570 /* No register. This must be BLX(1). */
9571 inst
.instruction
= 0xf000e800;
9572 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9573 inst
.reloc
.pc_rel
= 1;
9584 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9588 /* Conditional branches inside IT blocks are encoded as unconditional
9595 if (cond
!= COND_ALWAYS
)
9596 opcode
= T_MNEM_bcond
;
9598 opcode
= inst
.instruction
;
9600 if (unified_syntax
&& inst
.size_req
== 4)
9602 inst
.instruction
= THUMB_OP32(opcode
);
9603 if (cond
== COND_ALWAYS
)
9604 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9607 gas_assert (cond
!= 0xF);
9608 inst
.instruction
|= cond
<< 22;
9609 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9614 inst
.instruction
= THUMB_OP16(opcode
);
9615 if (cond
== COND_ALWAYS
)
9616 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9619 inst
.instruction
|= cond
<< 8;
9620 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9622 /* Allow section relaxation. */
9623 if (unified_syntax
&& inst
.size_req
!= 2)
9624 inst
.relax
= opcode
;
9627 inst
.reloc
.pc_rel
= 1;
9633 constraint (inst
.cond
!= COND_ALWAYS
,
9634 _("instruction is always unconditional"));
9635 if (inst
.operands
[0].present
)
9637 constraint (inst
.operands
[0].imm
> 255,
9638 _("immediate value out of range"));
9639 inst
.instruction
|= inst
.operands
[0].imm
;
9640 set_it_insn_type (NEUTRAL_IT_INSN
);
9645 do_t_branch23 (void)
9647 set_it_insn_type_last ();
9648 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9649 inst
.reloc
.pc_rel
= 1;
9651 #if defined(OBJ_COFF)
9652 /* If the destination of the branch is a defined symbol which does not have
9653 the THUMB_FUNC attribute, then we must be calling a function which has
9654 the (interfacearm) attribute. We look for the Thumb entry point to that
9655 function and change the branch to refer to that function instead. */
9656 if ( inst
.reloc
.exp
.X_op
== O_symbol
9657 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9658 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9659 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9660 inst
.reloc
.exp
.X_add_symbol
=
9661 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9668 set_it_insn_type_last ();
9669 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9670 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9671 should cause the alignment to be checked once it is known. This is
9672 because BX PC only works if the instruction is word aligned. */
9680 set_it_insn_type_last ();
9681 Rm
= inst
.operands
[0].reg
;
9682 reject_bad_reg (Rm
);
9683 inst
.instruction
|= Rm
<< 16;
9692 Rd
= inst
.operands
[0].reg
;
9693 Rm
= inst
.operands
[1].reg
;
9695 reject_bad_reg (Rd
);
9696 reject_bad_reg (Rm
);
9698 inst
.instruction
|= Rd
<< 8;
9699 inst
.instruction
|= Rm
<< 16;
9700 inst
.instruction
|= Rm
;
9706 set_it_insn_type (OUTSIDE_IT_INSN
);
9707 inst
.instruction
|= inst
.operands
[0].imm
;
9713 set_it_insn_type (OUTSIDE_IT_INSN
);
9715 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9716 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9718 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9719 inst
.instruction
= 0xf3af8000;
9720 inst
.instruction
|= imod
<< 9;
9721 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9722 if (inst
.operands
[1].present
)
9723 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9727 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9728 && (inst
.operands
[0].imm
& 4),
9729 _("selected processor does not support 'A' form "
9730 "of this instruction"));
9731 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9732 _("Thumb does not support the 2-argument "
9733 "form of this instruction"));
9734 inst
.instruction
|= inst
.operands
[0].imm
;
9738 /* THUMB CPY instruction (argument parse). */
9743 if (inst
.size_req
== 4)
9745 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9746 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9747 inst
.instruction
|= inst
.operands
[1].reg
;
9751 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9752 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9753 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9760 set_it_insn_type (OUTSIDE_IT_INSN
);
9761 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9762 inst
.instruction
|= inst
.operands
[0].reg
;
9763 inst
.reloc
.pc_rel
= 1;
9764 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9770 inst
.instruction
|= inst
.operands
[0].imm
;
9776 unsigned Rd
, Rn
, Rm
;
9778 Rd
= inst
.operands
[0].reg
;
9779 Rn
= (inst
.operands
[1].present
9780 ? inst
.operands
[1].reg
: Rd
);
9781 Rm
= inst
.operands
[2].reg
;
9783 reject_bad_reg (Rd
);
9784 reject_bad_reg (Rn
);
9785 reject_bad_reg (Rm
);
9787 inst
.instruction
|= Rd
<< 8;
9788 inst
.instruction
|= Rn
<< 16;
9789 inst
.instruction
|= Rm
;
9795 if (unified_syntax
&& inst
.size_req
== 4)
9796 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9798 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9804 unsigned int cond
= inst
.operands
[0].imm
;
9806 set_it_insn_type (IT_INSN
);
9807 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9810 /* If the condition is a negative condition, invert the mask. */
9811 if ((cond
& 0x1) == 0x0)
9813 unsigned int mask
= inst
.instruction
& 0x000f;
9815 if ((mask
& 0x7) == 0)
9816 /* no conversion needed */;
9817 else if ((mask
& 0x3) == 0)
9819 else if ((mask
& 0x1) == 0)
9824 inst
.instruction
&= 0xfff0;
9825 inst
.instruction
|= mask
;
9828 inst
.instruction
|= cond
<< 4;
9831 /* Helper function used for both push/pop and ldm/stm. */
9833 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9837 load
= (inst
.instruction
& (1 << 20)) != 0;
9839 if (mask
& (1 << 13))
9840 inst
.error
= _("SP not allowed in register list");
9842 if ((mask
& (1 << base
)) != 0
9844 inst
.error
= _("having the base register in the register list when "
9845 "using write back is UNPREDICTABLE");
9849 if (mask
& (1 << 15))
9851 if (mask
& (1 << 14))
9852 inst
.error
= _("LR and PC should not both be in register list");
9854 set_it_insn_type_last ();
9859 if (mask
& (1 << 15))
9860 inst
.error
= _("PC not allowed in register list");
9863 if ((mask
& (mask
- 1)) == 0)
9865 /* Single register transfers implemented as str/ldr. */
9868 if (inst
.instruction
& (1 << 23))
9869 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9871 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9875 if (inst
.instruction
& (1 << 23))
9876 inst
.instruction
= 0x00800000; /* ia -> [base] */
9878 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9881 inst
.instruction
|= 0xf8400000;
9883 inst
.instruction
|= 0x00100000;
9885 mask
= ffs (mask
) - 1;
9889 inst
.instruction
|= WRITE_BACK
;
9891 inst
.instruction
|= mask
;
9892 inst
.instruction
|= base
<< 16;
9898 /* This really doesn't seem worth it. */
9899 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9900 _("expression too complex"));
9901 constraint (inst
.operands
[1].writeback
,
9902 _("Thumb load/store multiple does not support {reglist}^"));
9910 /* See if we can use a 16-bit instruction. */
9911 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9912 && inst
.size_req
!= 4
9913 && !(inst
.operands
[1].imm
& ~0xff))
9915 mask
= 1 << inst
.operands
[0].reg
;
9917 if (inst
.operands
[0].reg
<= 7
9918 && (inst
.instruction
== T_MNEM_stmia
9919 ? inst
.operands
[0].writeback
9920 : (inst
.operands
[0].writeback
9921 == !(inst
.operands
[1].imm
& mask
))))
9923 if (inst
.instruction
== T_MNEM_stmia
9924 && (inst
.operands
[1].imm
& mask
)
9925 && (inst
.operands
[1].imm
& (mask
- 1)))
9926 as_warn (_("value stored for r%d is UNKNOWN"),
9927 inst
.operands
[0].reg
);
9929 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9930 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9931 inst
.instruction
|= inst
.operands
[1].imm
;
9934 else if (inst
.operands
[0] .reg
== REG_SP
9935 && inst
.operands
[0].writeback
)
9937 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9938 ? T_MNEM_push
: T_MNEM_pop
);
9939 inst
.instruction
|= inst
.operands
[1].imm
;
9946 if (inst
.instruction
< 0xffff)
9947 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9949 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9950 inst
.operands
[0].writeback
);
9955 constraint (inst
.operands
[0].reg
> 7
9956 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9957 constraint (inst
.instruction
!= T_MNEM_ldmia
9958 && inst
.instruction
!= T_MNEM_stmia
,
9959 _("Thumb-2 instruction only valid in unified syntax"));
9960 if (inst
.instruction
== T_MNEM_stmia
)
9962 if (!inst
.operands
[0].writeback
)
9963 as_warn (_("this instruction will write back the base register"));
9964 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9965 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9966 as_warn (_("value stored for r%d is UNKNOWN"),
9967 inst
.operands
[0].reg
);
9971 if (!inst
.operands
[0].writeback
9972 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9973 as_warn (_("this instruction will write back the base register"));
9974 else if (inst
.operands
[0].writeback
9975 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9976 as_warn (_("this instruction will not write back the base register"));
9979 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9980 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9981 inst
.instruction
|= inst
.operands
[1].imm
;
9988 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9989 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9990 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9991 || inst
.operands
[1].negative
,
9994 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9996 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9997 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9998 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10004 if (!inst
.operands
[1].present
)
10006 constraint (inst
.operands
[0].reg
== REG_LR
,
10007 _("r14 not allowed as first register "
10008 "when second register is omitted"));
10009 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10011 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10015 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10016 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10022 unsigned long opcode
;
10025 if (inst
.operands
[0].isreg
10026 && !inst
.operands
[0].preind
10027 && inst
.operands
[0].reg
== REG_PC
)
10028 set_it_insn_type_last ();
10030 opcode
= inst
.instruction
;
10031 if (unified_syntax
)
10033 if (!inst
.operands
[1].isreg
)
10035 if (opcode
<= 0xffff)
10036 inst
.instruction
= THUMB_OP32 (opcode
);
10037 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10040 if (inst
.operands
[1].isreg
10041 && !inst
.operands
[1].writeback
10042 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10043 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10044 && opcode
<= 0xffff
10045 && inst
.size_req
!= 4)
10047 /* Insn may have a 16-bit form. */
10048 Rn
= inst
.operands
[1].reg
;
10049 if (inst
.operands
[1].immisreg
)
10051 inst
.instruction
= THUMB_OP16 (opcode
);
10053 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10055 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10056 reject_bad_reg (inst
.operands
[1].imm
);
10058 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10059 && opcode
!= T_MNEM_ldrsb
)
10060 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10061 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10068 if (inst
.reloc
.pc_rel
)
10069 opcode
= T_MNEM_ldr_pc2
;
10071 opcode
= T_MNEM_ldr_pc
;
10075 if (opcode
== T_MNEM_ldr
)
10076 opcode
= T_MNEM_ldr_sp
;
10078 opcode
= T_MNEM_str_sp
;
10080 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10084 inst
.instruction
= inst
.operands
[0].reg
;
10085 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10087 inst
.instruction
|= THUMB_OP16 (opcode
);
10088 if (inst
.size_req
== 2)
10089 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10091 inst
.relax
= opcode
;
10095 /* Definitely a 32-bit variant. */
10097 /* Do some validations regarding addressing modes. */
10098 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10099 && opcode
!= T_MNEM_str
)
10100 reject_bad_reg (inst
.operands
[1].imm
);
10102 inst
.instruction
= THUMB_OP32 (opcode
);
10103 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10104 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10108 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10110 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10112 /* Only [Rn,Rm] is acceptable. */
10113 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10114 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10115 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10116 || inst
.operands
[1].negative
,
10117 _("Thumb does not support this addressing mode"));
10118 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10122 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10123 if (!inst
.operands
[1].isreg
)
10124 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10127 constraint (!inst
.operands
[1].preind
10128 || inst
.operands
[1].shifted
10129 || inst
.operands
[1].writeback
,
10130 _("Thumb does not support this addressing mode"));
10131 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10133 constraint (inst
.instruction
& 0x0600,
10134 _("byte or halfword not valid for base register"));
10135 constraint (inst
.operands
[1].reg
== REG_PC
10136 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10137 _("r15 based store not allowed"));
10138 constraint (inst
.operands
[1].immisreg
,
10139 _("invalid base register for register offset"));
10141 if (inst
.operands
[1].reg
== REG_PC
)
10142 inst
.instruction
= T_OPCODE_LDR_PC
;
10143 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10144 inst
.instruction
= T_OPCODE_LDR_SP
;
10146 inst
.instruction
= T_OPCODE_STR_SP
;
10148 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10149 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10153 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10154 if (!inst
.operands
[1].immisreg
)
10156 /* Immediate offset. */
10157 inst
.instruction
|= inst
.operands
[0].reg
;
10158 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10159 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10163 /* Register offset. */
10164 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10165 constraint (inst
.operands
[1].negative
,
10166 _("Thumb does not support this addressing mode"));
10169 switch (inst
.instruction
)
10171 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10172 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10173 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10174 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10175 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10176 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10177 case 0x5600 /* ldrsb */:
10178 case 0x5e00 /* ldrsh */: break;
10182 inst
.instruction
|= inst
.operands
[0].reg
;
10183 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10184 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10190 if (!inst
.operands
[1].present
)
10192 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10193 constraint (inst
.operands
[0].reg
== REG_LR
,
10194 _("r14 not allowed here"));
10196 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10197 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10198 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10204 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10205 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10211 unsigned Rd
, Rn
, Rm
, Ra
;
10213 Rd
= inst
.operands
[0].reg
;
10214 Rn
= inst
.operands
[1].reg
;
10215 Rm
= inst
.operands
[2].reg
;
10216 Ra
= inst
.operands
[3].reg
;
10218 reject_bad_reg (Rd
);
10219 reject_bad_reg (Rn
);
10220 reject_bad_reg (Rm
);
10221 reject_bad_reg (Ra
);
10223 inst
.instruction
|= Rd
<< 8;
10224 inst
.instruction
|= Rn
<< 16;
10225 inst
.instruction
|= Rm
;
10226 inst
.instruction
|= Ra
<< 12;
10232 unsigned RdLo
, RdHi
, Rn
, Rm
;
10234 RdLo
= inst
.operands
[0].reg
;
10235 RdHi
= inst
.operands
[1].reg
;
10236 Rn
= inst
.operands
[2].reg
;
10237 Rm
= inst
.operands
[3].reg
;
10239 reject_bad_reg (RdLo
);
10240 reject_bad_reg (RdHi
);
10241 reject_bad_reg (Rn
);
10242 reject_bad_reg (Rm
);
10244 inst
.instruction
|= RdLo
<< 12;
10245 inst
.instruction
|= RdHi
<< 8;
10246 inst
.instruction
|= Rn
<< 16;
10247 inst
.instruction
|= Rm
;
10251 do_t_mov_cmp (void)
10255 Rn
= inst
.operands
[0].reg
;
10256 Rm
= inst
.operands
[1].reg
;
10259 set_it_insn_type_last ();
10261 if (unified_syntax
)
10263 int r0off
= (inst
.instruction
== T_MNEM_mov
10264 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10265 unsigned long opcode
;
10266 bfd_boolean narrow
;
10267 bfd_boolean low_regs
;
10269 low_regs
= (Rn
<= 7 && Rm
<= 7);
10270 opcode
= inst
.instruction
;
10271 if (in_it_block ())
10272 narrow
= opcode
!= T_MNEM_movs
;
10274 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10275 if (inst
.size_req
== 4
10276 || inst
.operands
[1].shifted
)
10279 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10280 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10281 && !inst
.operands
[1].shifted
10285 inst
.instruction
= T2_SUBS_PC_LR
;
10289 if (opcode
== T_MNEM_cmp
)
10291 constraint (Rn
== REG_PC
, BAD_PC
);
10294 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10296 warn_deprecated_sp (Rm
);
10297 /* R15 was documented as a valid choice for Rm in ARMv6,
10298 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10299 tools reject R15, so we do too. */
10300 constraint (Rm
== REG_PC
, BAD_PC
);
10303 reject_bad_reg (Rm
);
10305 else if (opcode
== T_MNEM_mov
10306 || opcode
== T_MNEM_movs
)
10308 if (inst
.operands
[1].isreg
)
10310 if (opcode
== T_MNEM_movs
)
10312 reject_bad_reg (Rn
);
10313 reject_bad_reg (Rm
);
10317 /* This is mov.n. */
10318 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10319 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10321 as_warn (_("Use of r%u as a source register is "
10322 "deprecated when r%u is the destination "
10323 "register."), Rm
, Rn
);
10328 /* This is mov.w. */
10329 constraint (Rn
== REG_PC
, BAD_PC
);
10330 constraint (Rm
== REG_PC
, BAD_PC
);
10331 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10335 reject_bad_reg (Rn
);
10338 if (!inst
.operands
[1].isreg
)
10340 /* Immediate operand. */
10341 if (!in_it_block () && opcode
== T_MNEM_mov
)
10343 if (low_regs
&& narrow
)
10345 inst
.instruction
= THUMB_OP16 (opcode
);
10346 inst
.instruction
|= Rn
<< 8;
10347 if (inst
.size_req
== 2)
10348 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10350 inst
.relax
= opcode
;
10354 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10355 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10356 inst
.instruction
|= Rn
<< r0off
;
10357 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10360 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10361 && (inst
.instruction
== T_MNEM_mov
10362 || inst
.instruction
== T_MNEM_movs
))
10364 /* Register shifts are encoded as separate shift instructions. */
10365 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10367 if (in_it_block ())
10372 if (inst
.size_req
== 4)
10375 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10381 switch (inst
.operands
[1].shift_kind
)
10384 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10387 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10390 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10393 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10399 inst
.instruction
= opcode
;
10402 inst
.instruction
|= Rn
;
10403 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10408 inst
.instruction
|= CONDS_BIT
;
10410 inst
.instruction
|= Rn
<< 8;
10411 inst
.instruction
|= Rm
<< 16;
10412 inst
.instruction
|= inst
.operands
[1].imm
;
10417 /* Some mov with immediate shift have narrow variants.
10418 Register shifts are handled above. */
10419 if (low_regs
&& inst
.operands
[1].shifted
10420 && (inst
.instruction
== T_MNEM_mov
10421 || inst
.instruction
== T_MNEM_movs
))
10423 if (in_it_block ())
10424 narrow
= (inst
.instruction
== T_MNEM_mov
);
10426 narrow
= (inst
.instruction
== T_MNEM_movs
);
10431 switch (inst
.operands
[1].shift_kind
)
10433 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10434 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10435 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10436 default: narrow
= FALSE
; break;
10442 inst
.instruction
|= Rn
;
10443 inst
.instruction
|= Rm
<< 3;
10444 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10448 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10449 inst
.instruction
|= Rn
<< r0off
;
10450 encode_thumb32_shifted_operand (1);
10454 switch (inst
.instruction
)
10457 inst
.instruction
= T_OPCODE_MOV_HR
;
10458 inst
.instruction
|= (Rn
& 0x8) << 4;
10459 inst
.instruction
|= (Rn
& 0x7);
10460 inst
.instruction
|= Rm
<< 3;
10464 /* We know we have low registers at this point.
10465 Generate LSLS Rd, Rs, #0. */
10466 inst
.instruction
= T_OPCODE_LSL_I
;
10467 inst
.instruction
|= Rn
;
10468 inst
.instruction
|= Rm
<< 3;
10474 inst
.instruction
= T_OPCODE_CMP_LR
;
10475 inst
.instruction
|= Rn
;
10476 inst
.instruction
|= Rm
<< 3;
10480 inst
.instruction
= T_OPCODE_CMP_HR
;
10481 inst
.instruction
|= (Rn
& 0x8) << 4;
10482 inst
.instruction
|= (Rn
& 0x7);
10483 inst
.instruction
|= Rm
<< 3;
10490 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10492 /* PR 10443: Do not silently ignore shifted operands. */
10493 constraint (inst
.operands
[1].shifted
,
10494 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10496 if (inst
.operands
[1].isreg
)
10498 if (Rn
< 8 && Rm
< 8)
10500 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10501 since a MOV instruction produces unpredictable results. */
10502 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10503 inst
.instruction
= T_OPCODE_ADD_I3
;
10505 inst
.instruction
= T_OPCODE_CMP_LR
;
10507 inst
.instruction
|= Rn
;
10508 inst
.instruction
|= Rm
<< 3;
10512 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10513 inst
.instruction
= T_OPCODE_MOV_HR
;
10515 inst
.instruction
= T_OPCODE_CMP_HR
;
10521 constraint (Rn
> 7,
10522 _("only lo regs allowed with immediate"));
10523 inst
.instruction
|= Rn
<< 8;
10524 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10535 top
= (inst
.instruction
& 0x00800000) != 0;
10536 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10538 constraint (top
, _(":lower16: not allowed this instruction"));
10539 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10541 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10543 constraint (!top
, _(":upper16: not allowed this instruction"));
10544 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10547 Rd
= inst
.operands
[0].reg
;
10548 reject_bad_reg (Rd
);
10550 inst
.instruction
|= Rd
<< 8;
10551 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10553 imm
= inst
.reloc
.exp
.X_add_number
;
10554 inst
.instruction
|= (imm
& 0xf000) << 4;
10555 inst
.instruction
|= (imm
& 0x0800) << 15;
10556 inst
.instruction
|= (imm
& 0x0700) << 4;
10557 inst
.instruction
|= (imm
& 0x00ff);
10562 do_t_mvn_tst (void)
10566 Rn
= inst
.operands
[0].reg
;
10567 Rm
= inst
.operands
[1].reg
;
10569 if (inst
.instruction
== T_MNEM_cmp
10570 || inst
.instruction
== T_MNEM_cmn
)
10571 constraint (Rn
== REG_PC
, BAD_PC
);
10573 reject_bad_reg (Rn
);
10574 reject_bad_reg (Rm
);
10576 if (unified_syntax
)
10578 int r0off
= (inst
.instruction
== T_MNEM_mvn
10579 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10580 bfd_boolean narrow
;
10582 if (inst
.size_req
== 4
10583 || inst
.instruction
> 0xffff
10584 || inst
.operands
[1].shifted
10585 || Rn
> 7 || Rm
> 7)
10587 else if (inst
.instruction
== T_MNEM_cmn
)
10589 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10590 narrow
= !in_it_block ();
10592 narrow
= in_it_block ();
10594 if (!inst
.operands
[1].isreg
)
10596 /* For an immediate, we always generate a 32-bit opcode;
10597 section relaxation will shrink it later if possible. */
10598 if (inst
.instruction
< 0xffff)
10599 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10600 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10601 inst
.instruction
|= Rn
<< r0off
;
10602 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10606 /* See if we can do this with a 16-bit instruction. */
10609 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10610 inst
.instruction
|= Rn
;
10611 inst
.instruction
|= Rm
<< 3;
10615 constraint (inst
.operands
[1].shifted
10616 && inst
.operands
[1].immisreg
,
10617 _("shift must be constant"));
10618 if (inst
.instruction
< 0xffff)
10619 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10620 inst
.instruction
|= Rn
<< r0off
;
10621 encode_thumb32_shifted_operand (1);
10627 constraint (inst
.instruction
> 0xffff
10628 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10629 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10630 _("unshifted register required"));
10631 constraint (Rn
> 7 || Rm
> 7,
10634 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10635 inst
.instruction
|= Rn
;
10636 inst
.instruction
|= Rm
<< 3;
10646 if (do_vfp_nsyn_mrs () == SUCCESS
)
10649 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10652 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10653 _("selected processor does not support "
10654 "requested special purpose register"));
10658 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10659 _("selected processor does not support "
10660 "requested special purpose register"));
10661 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10662 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10663 _("'CPSR' or 'SPSR' expected"));
10666 Rd
= inst
.operands
[0].reg
;
10667 reject_bad_reg (Rd
);
10669 inst
.instruction
|= Rd
<< 8;
10670 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10671 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10680 if (do_vfp_nsyn_msr () == SUCCESS
)
10683 constraint (!inst
.operands
[1].isreg
,
10684 _("Thumb encoding does not support an immediate here"));
10685 flags
= inst
.operands
[0].imm
;
10688 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10689 _("selected processor does not support "
10690 "requested special purpose register"));
10694 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10695 _("selected processor does not support "
10696 "requested special purpose register"));
10700 Rn
= inst
.operands
[1].reg
;
10701 reject_bad_reg (Rn
);
10703 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10704 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10705 inst
.instruction
|= (flags
& 0xff);
10706 inst
.instruction
|= Rn
<< 16;
10712 bfd_boolean narrow
;
10713 unsigned Rd
, Rn
, Rm
;
10715 if (!inst
.operands
[2].present
)
10716 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10718 Rd
= inst
.operands
[0].reg
;
10719 Rn
= inst
.operands
[1].reg
;
10720 Rm
= inst
.operands
[2].reg
;
10722 if (unified_syntax
)
10724 if (inst
.size_req
== 4
10730 else if (inst
.instruction
== T_MNEM_muls
)
10731 narrow
= !in_it_block ();
10733 narrow
= in_it_block ();
10737 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10738 constraint (Rn
> 7 || Rm
> 7,
10745 /* 16-bit MULS/Conditional MUL. */
10746 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10747 inst
.instruction
|= Rd
;
10750 inst
.instruction
|= Rm
<< 3;
10752 inst
.instruction
|= Rn
<< 3;
10754 constraint (1, _("dest must overlap one source register"));
10758 constraint (inst
.instruction
!= T_MNEM_mul
,
10759 _("Thumb-2 MUL must not set flags"));
10761 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10762 inst
.instruction
|= Rd
<< 8;
10763 inst
.instruction
|= Rn
<< 16;
10764 inst
.instruction
|= Rm
<< 0;
10766 reject_bad_reg (Rd
);
10767 reject_bad_reg (Rn
);
10768 reject_bad_reg (Rm
);
10775 unsigned RdLo
, RdHi
, Rn
, Rm
;
10777 RdLo
= inst
.operands
[0].reg
;
10778 RdHi
= inst
.operands
[1].reg
;
10779 Rn
= inst
.operands
[2].reg
;
10780 Rm
= inst
.operands
[3].reg
;
10782 reject_bad_reg (RdLo
);
10783 reject_bad_reg (RdHi
);
10784 reject_bad_reg (Rn
);
10785 reject_bad_reg (Rm
);
10787 inst
.instruction
|= RdLo
<< 12;
10788 inst
.instruction
|= RdHi
<< 8;
10789 inst
.instruction
|= Rn
<< 16;
10790 inst
.instruction
|= Rm
;
10793 as_tsktsk (_("rdhi and rdlo must be different"));
10799 set_it_insn_type (NEUTRAL_IT_INSN
);
10801 if (unified_syntax
)
10803 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10805 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10806 inst
.instruction
|= inst
.operands
[0].imm
;
10810 /* PR9722: Check for Thumb2 availability before
10811 generating a thumb2 nop instruction. */
10812 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10814 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10815 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10818 inst
.instruction
= 0x46c0;
10823 constraint (inst
.operands
[0].present
,
10824 _("Thumb does not support NOP with hints"));
10825 inst
.instruction
= 0x46c0;
10832 if (unified_syntax
)
10834 bfd_boolean narrow
;
10836 if (THUMB_SETS_FLAGS (inst
.instruction
))
10837 narrow
= !in_it_block ();
10839 narrow
= in_it_block ();
10840 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10842 if (inst
.size_req
== 4)
10847 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10848 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10849 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10853 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10854 inst
.instruction
|= inst
.operands
[0].reg
;
10855 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10860 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10862 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10864 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10865 inst
.instruction
|= inst
.operands
[0].reg
;
10866 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10875 Rd
= inst
.operands
[0].reg
;
10876 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10878 reject_bad_reg (Rd
);
10879 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10880 reject_bad_reg (Rn
);
10882 inst
.instruction
|= Rd
<< 8;
10883 inst
.instruction
|= Rn
<< 16;
10885 if (!inst
.operands
[2].isreg
)
10887 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10888 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10894 Rm
= inst
.operands
[2].reg
;
10895 reject_bad_reg (Rm
);
10897 constraint (inst
.operands
[2].shifted
10898 && inst
.operands
[2].immisreg
,
10899 _("shift must be constant"));
10900 encode_thumb32_shifted_operand (2);
10907 unsigned Rd
, Rn
, Rm
;
10909 Rd
= inst
.operands
[0].reg
;
10910 Rn
= inst
.operands
[1].reg
;
10911 Rm
= inst
.operands
[2].reg
;
10913 reject_bad_reg (Rd
);
10914 reject_bad_reg (Rn
);
10915 reject_bad_reg (Rm
);
10917 inst
.instruction
|= Rd
<< 8;
10918 inst
.instruction
|= Rn
<< 16;
10919 inst
.instruction
|= Rm
;
10920 if (inst
.operands
[3].present
)
10922 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10923 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10924 _("expression too complex"));
10925 inst
.instruction
|= (val
& 0x1c) << 10;
10926 inst
.instruction
|= (val
& 0x03) << 6;
10933 if (!inst
.operands
[3].present
)
10937 inst
.instruction
&= ~0x00000020;
10939 /* PR 10168. Swap the Rm and Rn registers. */
10940 Rtmp
= inst
.operands
[1].reg
;
10941 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10942 inst
.operands
[2].reg
= Rtmp
;
10950 if (inst
.operands
[0].immisreg
)
10951 reject_bad_reg (inst
.operands
[0].imm
);
10953 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10957 do_t_push_pop (void)
10961 constraint (inst
.operands
[0].writeback
,
10962 _("push/pop do not support {reglist}^"));
10963 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10964 _("expression too complex"));
10966 mask
= inst
.operands
[0].imm
;
10967 if ((mask
& ~0xff) == 0)
10968 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10969 else if ((inst
.instruction
== T_MNEM_push
10970 && (mask
& ~0xff) == 1 << REG_LR
)
10971 || (inst
.instruction
== T_MNEM_pop
10972 && (mask
& ~0xff) == 1 << REG_PC
))
10974 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10975 inst
.instruction
|= THUMB_PP_PC_LR
;
10976 inst
.instruction
|= mask
& 0xff;
10978 else if (unified_syntax
)
10980 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10981 encode_thumb2_ldmstm (13, mask
, TRUE
);
10985 inst
.error
= _("invalid register list to push/pop instruction");
10995 Rd
= inst
.operands
[0].reg
;
10996 Rm
= inst
.operands
[1].reg
;
10998 reject_bad_reg (Rd
);
10999 reject_bad_reg (Rm
);
11001 inst
.instruction
|= Rd
<< 8;
11002 inst
.instruction
|= Rm
<< 16;
11003 inst
.instruction
|= Rm
;
11011 Rd
= inst
.operands
[0].reg
;
11012 Rm
= inst
.operands
[1].reg
;
11014 reject_bad_reg (Rd
);
11015 reject_bad_reg (Rm
);
11017 if (Rd
<= 7 && Rm
<= 7
11018 && inst
.size_req
!= 4)
11020 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11021 inst
.instruction
|= Rd
;
11022 inst
.instruction
|= Rm
<< 3;
11024 else if (unified_syntax
)
11026 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11027 inst
.instruction
|= Rd
<< 8;
11028 inst
.instruction
|= Rm
<< 16;
11029 inst
.instruction
|= Rm
;
11032 inst
.error
= BAD_HIREG
;
11040 Rd
= inst
.operands
[0].reg
;
11041 Rm
= inst
.operands
[1].reg
;
11043 reject_bad_reg (Rd
);
11044 reject_bad_reg (Rm
);
11046 inst
.instruction
|= Rd
<< 8;
11047 inst
.instruction
|= Rm
;
11055 Rd
= inst
.operands
[0].reg
;
11056 Rs
= (inst
.operands
[1].present
11057 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11058 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11060 reject_bad_reg (Rd
);
11061 reject_bad_reg (Rs
);
11062 if (inst
.operands
[2].isreg
)
11063 reject_bad_reg (inst
.operands
[2].reg
);
11065 inst
.instruction
|= Rd
<< 8;
11066 inst
.instruction
|= Rs
<< 16;
11067 if (!inst
.operands
[2].isreg
)
11069 bfd_boolean narrow
;
11071 if ((inst
.instruction
& 0x00100000) != 0)
11072 narrow
= !in_it_block ();
11074 narrow
= in_it_block ();
11076 if (Rd
> 7 || Rs
> 7)
11079 if (inst
.size_req
== 4 || !unified_syntax
)
11082 if (inst
.reloc
.exp
.X_op
!= O_constant
11083 || inst
.reloc
.exp
.X_add_number
!= 0)
11086 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11087 relaxation, but it doesn't seem worth the hassle. */
11090 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11091 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11092 inst
.instruction
|= Rs
<< 3;
11093 inst
.instruction
|= Rd
;
11097 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11098 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11102 encode_thumb32_shifted_operand (2);
11108 set_it_insn_type (OUTSIDE_IT_INSN
);
11109 if (inst
.operands
[0].imm
)
11110 inst
.instruction
|= 0x8;
11116 if (!inst
.operands
[1].present
)
11117 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11119 if (unified_syntax
)
11121 bfd_boolean narrow
;
11124 switch (inst
.instruction
)
11127 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11129 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11131 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11133 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11137 if (THUMB_SETS_FLAGS (inst
.instruction
))
11138 narrow
= !in_it_block ();
11140 narrow
= in_it_block ();
11141 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11143 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11145 if (inst
.operands
[2].isreg
11146 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11147 || inst
.operands
[2].reg
> 7))
11149 if (inst
.size_req
== 4)
11152 reject_bad_reg (inst
.operands
[0].reg
);
11153 reject_bad_reg (inst
.operands
[1].reg
);
11157 if (inst
.operands
[2].isreg
)
11159 reject_bad_reg (inst
.operands
[2].reg
);
11160 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11161 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11162 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11163 inst
.instruction
|= inst
.operands
[2].reg
;
11167 inst
.operands
[1].shifted
= 1;
11168 inst
.operands
[1].shift_kind
= shift_kind
;
11169 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11170 ? T_MNEM_movs
: T_MNEM_mov
);
11171 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11172 encode_thumb32_shifted_operand (1);
11173 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11174 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11179 if (inst
.operands
[2].isreg
)
11181 switch (shift_kind
)
11183 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11184 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11185 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11186 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11190 inst
.instruction
|= inst
.operands
[0].reg
;
11191 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11195 switch (shift_kind
)
11197 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11198 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11199 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11202 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11203 inst
.instruction
|= inst
.operands
[0].reg
;
11204 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11210 constraint (inst
.operands
[0].reg
> 7
11211 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11212 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11214 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11216 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11217 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11218 _("source1 and dest must be same register"));
11220 switch (inst
.instruction
)
11222 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11223 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11224 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11225 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11229 inst
.instruction
|= inst
.operands
[0].reg
;
11230 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11234 switch (inst
.instruction
)
11236 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11237 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11238 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11239 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11242 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11243 inst
.instruction
|= inst
.operands
[0].reg
;
11244 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11252 unsigned Rd
, Rn
, Rm
;
11254 Rd
= inst
.operands
[0].reg
;
11255 Rn
= inst
.operands
[1].reg
;
11256 Rm
= inst
.operands
[2].reg
;
11258 reject_bad_reg (Rd
);
11259 reject_bad_reg (Rn
);
11260 reject_bad_reg (Rm
);
11262 inst
.instruction
|= Rd
<< 8;
11263 inst
.instruction
|= Rn
<< 16;
11264 inst
.instruction
|= Rm
;
11270 unsigned Rd
, Rn
, Rm
;
11272 Rd
= inst
.operands
[0].reg
;
11273 Rm
= inst
.operands
[1].reg
;
11274 Rn
= inst
.operands
[2].reg
;
11276 reject_bad_reg (Rd
);
11277 reject_bad_reg (Rn
);
11278 reject_bad_reg (Rm
);
11280 inst
.instruction
|= Rd
<< 8;
11281 inst
.instruction
|= Rn
<< 16;
11282 inst
.instruction
|= Rm
;
11288 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11289 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11290 _("expression too complex"));
11291 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11292 inst
.instruction
|= (value
& 0xf000) >> 12;
11293 inst
.instruction
|= (value
& 0x0ff0);
11294 inst
.instruction
|= (value
& 0x000f) << 16;
11298 do_t_ssat_usat (int bias
)
11302 Rd
= inst
.operands
[0].reg
;
11303 Rn
= inst
.operands
[2].reg
;
11305 reject_bad_reg (Rd
);
11306 reject_bad_reg (Rn
);
11308 inst
.instruction
|= Rd
<< 8;
11309 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11310 inst
.instruction
|= Rn
<< 16;
11312 if (inst
.operands
[3].present
)
11314 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11316 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11318 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11319 _("expression too complex"));
11321 if (shift_amount
!= 0)
11323 constraint (shift_amount
> 31,
11324 _("shift expression is too large"));
11326 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11327 inst
.instruction
|= 0x00200000; /* sh bit. */
11329 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11330 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11338 do_t_ssat_usat (1);
11346 Rd
= inst
.operands
[0].reg
;
11347 Rn
= inst
.operands
[2].reg
;
11349 reject_bad_reg (Rd
);
11350 reject_bad_reg (Rn
);
11352 inst
.instruction
|= Rd
<< 8;
11353 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11354 inst
.instruction
|= Rn
<< 16;
11360 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11361 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11362 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11363 || inst
.operands
[2].negative
,
11366 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11368 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11369 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11370 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11371 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11377 if (!inst
.operands
[2].present
)
11378 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11380 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11381 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11382 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11385 inst
.instruction
|= inst
.operands
[0].reg
;
11386 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11387 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11388 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11394 unsigned Rd
, Rn
, Rm
;
11396 Rd
= inst
.operands
[0].reg
;
11397 Rn
= inst
.operands
[1].reg
;
11398 Rm
= inst
.operands
[2].reg
;
11400 reject_bad_reg (Rd
);
11401 reject_bad_reg (Rn
);
11402 reject_bad_reg (Rm
);
11404 inst
.instruction
|= Rd
<< 8;
11405 inst
.instruction
|= Rn
<< 16;
11406 inst
.instruction
|= Rm
;
11407 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11415 Rd
= inst
.operands
[0].reg
;
11416 Rm
= inst
.operands
[1].reg
;
11418 reject_bad_reg (Rd
);
11419 reject_bad_reg (Rm
);
11421 if (inst
.instruction
<= 0xffff
11422 && inst
.size_req
!= 4
11423 && Rd
<= 7 && Rm
<= 7
11424 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11426 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11427 inst
.instruction
|= Rd
;
11428 inst
.instruction
|= Rm
<< 3;
11430 else if (unified_syntax
)
11432 if (inst
.instruction
<= 0xffff)
11433 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11434 inst
.instruction
|= Rd
<< 8;
11435 inst
.instruction
|= Rm
;
11436 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11440 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11441 _("Thumb encoding does not support rotation"));
11442 constraint (1, BAD_HIREG
);
11449 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11458 half
= (inst
.instruction
& 0x10) != 0;
11459 set_it_insn_type_last ();
11460 constraint (inst
.operands
[0].immisreg
,
11461 _("instruction requires register index"));
11463 Rn
= inst
.operands
[0].reg
;
11464 Rm
= inst
.operands
[0].imm
;
11466 constraint (Rn
== REG_SP
, BAD_SP
);
11467 reject_bad_reg (Rm
);
11469 constraint (!half
&& inst
.operands
[0].shifted
,
11470 _("instruction does not allow shifted index"));
11471 inst
.instruction
|= (Rn
<< 16) | Rm
;
11477 do_t_ssat_usat (0);
11485 Rd
= inst
.operands
[0].reg
;
11486 Rn
= inst
.operands
[2].reg
;
11488 reject_bad_reg (Rd
);
11489 reject_bad_reg (Rn
);
11491 inst
.instruction
|= Rd
<< 8;
11492 inst
.instruction
|= inst
.operands
[1].imm
;
11493 inst
.instruction
|= Rn
<< 16;
11496 /* Neon instruction encoder helpers. */
11498 /* Encodings for the different types for various Neon opcodes. */
11500 /* An "invalid" code for the following tables. */
11503 struct neon_tab_entry
11506 unsigned float_or_poly
;
11507 unsigned scalar_or_imm
;
11510 /* Map overloaded Neon opcodes to their respective encodings. */
11511 #define NEON_ENC_TAB \
11512 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11513 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11514 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11515 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11516 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11517 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11518 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11519 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11520 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11521 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11522 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11523 /* Register variants of the following two instructions are encoded as
11524 vcge / vcgt with the operands reversed. */ \
11525 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11526 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11527 X(vfma, N_INV, 0x0000c10, N_INV), \
11528 X(vfms, N_INV, 0x0200c10, N_INV), \
11529 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11530 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11531 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11532 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11533 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11534 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11535 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11536 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11537 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11538 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11539 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11540 X(vshl, 0x0000400, N_INV, 0x0800510), \
11541 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11542 X(vand, 0x0000110, N_INV, 0x0800030), \
11543 X(vbic, 0x0100110, N_INV, 0x0800030), \
11544 X(veor, 0x1000110, N_INV, N_INV), \
11545 X(vorn, 0x0300110, N_INV, 0x0800010), \
11546 X(vorr, 0x0200110, N_INV, 0x0800010), \
11547 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11548 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11549 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11550 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11551 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11552 X(vst1, 0x0000000, 0x0800000, N_INV), \
11553 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11554 X(vst2, 0x0000100, 0x0800100, N_INV), \
11555 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11556 X(vst3, 0x0000200, 0x0800200, N_INV), \
11557 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11558 X(vst4, 0x0000300, 0x0800300, N_INV), \
11559 X(vmovn, 0x1b20200, N_INV, N_INV), \
11560 X(vtrn, 0x1b20080, N_INV, N_INV), \
11561 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11562 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11563 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11564 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11565 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11566 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11567 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11568 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11569 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11570 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11571 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11575 #define X(OPC,I,F,S) N_MNEM_##OPC
11580 static const struct neon_tab_entry neon_enc_tab
[] =
11582 #define X(OPC,I,F,S) { (I), (F), (S) }
11587 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11588 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11589 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11590 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11591 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11592 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11593 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11594 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11595 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11596 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11597 #define NEON_ENC_SINGLE_(X) \
11598 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11599 #define NEON_ENC_DOUBLE_(X) \
11600 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11602 #define NEON_ENCODE(type, inst) \
11605 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11606 inst.is_neon = 1; \
11610 #define check_neon_suffixes \
11613 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11615 as_bad (_("invalid neon suffix for non neon instruction")); \
11621 /* Define shapes for instruction operands. The following mnemonic characters
11622 are used in this table:
11624 F - VFP S<n> register
11625 D - Neon D<n> register
11626 Q - Neon Q<n> register
11630 L - D<n> register list
11632 This table is used to generate various data:
11633 - enumerations of the form NS_DDR to be used as arguments to
11635 - a table classifying shapes into single, double, quad, mixed.
11636 - a table used to drive neon_select_shape. */
11638 #define NEON_SHAPE_DEF \
11639 X(3, (D, D, D), DOUBLE), \
11640 X(3, (Q, Q, Q), QUAD), \
11641 X(3, (D, D, I), DOUBLE), \
11642 X(3, (Q, Q, I), QUAD), \
11643 X(3, (D, D, S), DOUBLE), \
11644 X(3, (Q, Q, S), QUAD), \
11645 X(2, (D, D), DOUBLE), \
11646 X(2, (Q, Q), QUAD), \
11647 X(2, (D, S), DOUBLE), \
11648 X(2, (Q, S), QUAD), \
11649 X(2, (D, R), DOUBLE), \
11650 X(2, (Q, R), QUAD), \
11651 X(2, (D, I), DOUBLE), \
11652 X(2, (Q, I), QUAD), \
11653 X(3, (D, L, D), DOUBLE), \
11654 X(2, (D, Q), MIXED), \
11655 X(2, (Q, D), MIXED), \
11656 X(3, (D, Q, I), MIXED), \
11657 X(3, (Q, D, I), MIXED), \
11658 X(3, (Q, D, D), MIXED), \
11659 X(3, (D, Q, Q), MIXED), \
11660 X(3, (Q, Q, D), MIXED), \
11661 X(3, (Q, D, S), MIXED), \
11662 X(3, (D, Q, S), MIXED), \
11663 X(4, (D, D, D, I), DOUBLE), \
11664 X(4, (Q, Q, Q, I), QUAD), \
11665 X(2, (F, F), SINGLE), \
11666 X(3, (F, F, F), SINGLE), \
11667 X(2, (F, I), SINGLE), \
11668 X(2, (F, D), MIXED), \
11669 X(2, (D, F), MIXED), \
11670 X(3, (F, F, I), MIXED), \
11671 X(4, (R, R, F, F), SINGLE), \
11672 X(4, (F, F, R, R), SINGLE), \
11673 X(3, (D, R, R), DOUBLE), \
11674 X(3, (R, R, D), DOUBLE), \
11675 X(2, (S, R), SINGLE), \
11676 X(2, (R, S), SINGLE), \
11677 X(2, (F, R), SINGLE), \
11678 X(2, (R, F), SINGLE)
11680 #define S2(A,B) NS_##A##B
11681 #define S3(A,B,C) NS_##A##B##C
11682 #define S4(A,B,C,D) NS_##A##B##C##D
11684 #define X(N, L, C) S##N L
11697 enum neon_shape_class
11705 #define X(N, L, C) SC_##C
11707 static enum neon_shape_class neon_shape_class
[] =
11725 /* Register widths of above. */
11726 static unsigned neon_shape_el_size
[] =
11737 struct neon_shape_info
11740 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11743 #define S2(A,B) { SE_##A, SE_##B }
11744 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11745 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11747 #define X(N, L, C) { N, S##N L }
11749 static struct neon_shape_info neon_shape_tab
[] =
11759 /* Bit masks used in type checking given instructions.
11760 'N_EQK' means the type must be the same as (or based on in some way) the key
11761 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11762 set, various other bits can be set as well in order to modify the meaning of
11763 the type constraint. */
11765 enum neon_type_mask
11788 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11789 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11790 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11791 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11792 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11793 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11794 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11795 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11796 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11797 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11799 N_MAX_NONSPECIAL
= N_F64
11802 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11804 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11805 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11806 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11807 #define N_SUF_32 (N_SU_32 | N_F32)
11808 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11809 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11811 /* Pass this as the first type argument to neon_check_type to ignore types
11813 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11815 /* Select a "shape" for the current instruction (describing register types or
11816 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11817 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11818 function of operand parsing, so this function doesn't need to be called.
11819 Shapes should be listed in order of decreasing length. */
11821 static enum neon_shape
11822 neon_select_shape (enum neon_shape shape
, ...)
11825 enum neon_shape first_shape
= shape
;
11827 /* Fix missing optional operands. FIXME: we don't know at this point how
11828 many arguments we should have, so this makes the assumption that we have
11829 > 1. This is true of all current Neon opcodes, I think, but may not be
11830 true in the future. */
11831 if (!inst
.operands
[1].present
)
11832 inst
.operands
[1] = inst
.operands
[0];
11834 va_start (ap
, shape
);
11836 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11841 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11843 if (!inst
.operands
[j
].present
)
11849 switch (neon_shape_tab
[shape
].el
[j
])
11852 if (!(inst
.operands
[j
].isreg
11853 && inst
.operands
[j
].isvec
11854 && inst
.operands
[j
].issingle
11855 && !inst
.operands
[j
].isquad
))
11860 if (!(inst
.operands
[j
].isreg
11861 && inst
.operands
[j
].isvec
11862 && !inst
.operands
[j
].isquad
11863 && !inst
.operands
[j
].issingle
))
11868 if (!(inst
.operands
[j
].isreg
11869 && !inst
.operands
[j
].isvec
))
11874 if (!(inst
.operands
[j
].isreg
11875 && inst
.operands
[j
].isvec
11876 && inst
.operands
[j
].isquad
11877 && !inst
.operands
[j
].issingle
))
11882 if (!(!inst
.operands
[j
].isreg
11883 && !inst
.operands
[j
].isscalar
))
11888 if (!(!inst
.operands
[j
].isreg
11889 && inst
.operands
[j
].isscalar
))
11905 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11906 first_error (_("invalid instruction shape"));
11911 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11912 means the Q bit should be set). */
11915 neon_quad (enum neon_shape shape
)
11917 return neon_shape_class
[shape
] == SC_QUAD
;
11921 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11924 /* Allow modification to be made to types which are constrained to be
11925 based on the key element, based on bits set alongside N_EQK. */
11926 if ((typebits
& N_EQK
) != 0)
11928 if ((typebits
& N_HLF
) != 0)
11930 else if ((typebits
& N_DBL
) != 0)
11932 if ((typebits
& N_SGN
) != 0)
11933 *g_type
= NT_signed
;
11934 else if ((typebits
& N_UNS
) != 0)
11935 *g_type
= NT_unsigned
;
11936 else if ((typebits
& N_INT
) != 0)
11937 *g_type
= NT_integer
;
11938 else if ((typebits
& N_FLT
) != 0)
11939 *g_type
= NT_float
;
11940 else if ((typebits
& N_SIZ
) != 0)
11941 *g_type
= NT_untyped
;
11945 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11946 operand type, i.e. the single type specified in a Neon instruction when it
11947 is the only one given. */
11949 static struct neon_type_el
11950 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11952 struct neon_type_el dest
= *key
;
11954 gas_assert ((thisarg
& N_EQK
) != 0);
11956 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11961 /* Convert Neon type and size into compact bitmask representation. */
11963 static enum neon_type_mask
11964 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11971 case 8: return N_8
;
11972 case 16: return N_16
;
11973 case 32: return N_32
;
11974 case 64: return N_64
;
11982 case 8: return N_I8
;
11983 case 16: return N_I16
;
11984 case 32: return N_I32
;
11985 case 64: return N_I64
;
11993 case 16: return N_F16
;
11994 case 32: return N_F32
;
11995 case 64: return N_F64
;
12003 case 8: return N_P8
;
12004 case 16: return N_P16
;
12012 case 8: return N_S8
;
12013 case 16: return N_S16
;
12014 case 32: return N_S32
;
12015 case 64: return N_S64
;
12023 case 8: return N_U8
;
12024 case 16: return N_U16
;
12025 case 32: return N_U32
;
12026 case 64: return N_U64
;
12037 /* Convert compact Neon bitmask type representation to a type and size. Only
12038 handles the case where a single bit is set in the mask. */
12041 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12042 enum neon_type_mask mask
)
12044 if ((mask
& N_EQK
) != 0)
12047 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12049 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12051 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12053 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12058 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12060 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12061 *type
= NT_unsigned
;
12062 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12063 *type
= NT_integer
;
12064 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12065 *type
= NT_untyped
;
12066 else if ((mask
& (N_P8
| N_P16
)) != 0)
12068 else if ((mask
& (N_F32
| N_F64
)) != 0)
12076 /* Modify a bitmask of allowed types. This is only needed for type
12080 modify_types_allowed (unsigned allowed
, unsigned mods
)
12083 enum neon_el_type type
;
12089 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12091 if (el_type_of_type_chk (&type
, &size
,
12092 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12094 neon_modify_type_size (mods
, &type
, &size
);
12095 destmask
|= type_chk_of_el_type (type
, size
);
12102 /* Check type and return type classification.
12103 The manual states (paraphrase): If one datatype is given, it indicates the
12105 - the second operand, if there is one
12106 - the operand, if there is no second operand
12107 - the result, if there are no operands.
12108 This isn't quite good enough though, so we use a concept of a "key" datatype
12109 which is set on a per-instruction basis, which is the one which matters when
12110 only one data type is written.
12111 Note: this function has side-effects (e.g. filling in missing operands). All
12112 Neon instructions should call it before performing bit encoding. */
12114 static struct neon_type_el
12115 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12118 unsigned i
, pass
, key_el
= 0;
12119 unsigned types
[NEON_MAX_TYPE_ELS
];
12120 enum neon_el_type k_type
= NT_invtype
;
12121 unsigned k_size
= -1u;
12122 struct neon_type_el badtype
= {NT_invtype
, -1};
12123 unsigned key_allowed
= 0;
12125 /* Optional registers in Neon instructions are always (not) in operand 1.
12126 Fill in the missing operand here, if it was omitted. */
12127 if (els
> 1 && !inst
.operands
[1].present
)
12128 inst
.operands
[1] = inst
.operands
[0];
12130 /* Suck up all the varargs. */
12132 for (i
= 0; i
< els
; i
++)
12134 unsigned thisarg
= va_arg (ap
, unsigned);
12135 if (thisarg
== N_IGNORE_TYPE
)
12140 types
[i
] = thisarg
;
12141 if ((thisarg
& N_KEY
) != 0)
12146 if (inst
.vectype
.elems
> 0)
12147 for (i
= 0; i
< els
; i
++)
12148 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12150 first_error (_("types specified in both the mnemonic and operands"));
12154 /* Duplicate inst.vectype elements here as necessary.
12155 FIXME: No idea if this is exactly the same as the ARM assembler,
12156 particularly when an insn takes one register and one non-register
12158 if (inst
.vectype
.elems
== 1 && els
> 1)
12161 inst
.vectype
.elems
= els
;
12162 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12163 for (j
= 0; j
< els
; j
++)
12165 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12168 else if (inst
.vectype
.elems
== 0 && els
> 0)
12171 /* No types were given after the mnemonic, so look for types specified
12172 after each operand. We allow some flexibility here; as long as the
12173 "key" operand has a type, we can infer the others. */
12174 for (j
= 0; j
< els
; j
++)
12175 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12176 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12178 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12180 for (j
= 0; j
< els
; j
++)
12181 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12182 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12187 first_error (_("operand types can't be inferred"));
12191 else if (inst
.vectype
.elems
!= els
)
12193 first_error (_("type specifier has the wrong number of parts"));
12197 for (pass
= 0; pass
< 2; pass
++)
12199 for (i
= 0; i
< els
; i
++)
12201 unsigned thisarg
= types
[i
];
12202 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12203 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12204 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12205 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12207 /* Decay more-specific signed & unsigned types to sign-insensitive
12208 integer types if sign-specific variants are unavailable. */
12209 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12210 && (types_allowed
& N_SU_ALL
) == 0)
12211 g_type
= NT_integer
;
12213 /* If only untyped args are allowed, decay any more specific types to
12214 them. Some instructions only care about signs for some element
12215 sizes, so handle that properly. */
12216 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12217 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12218 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12219 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12220 g_type
= NT_untyped
;
12224 if ((thisarg
& N_KEY
) != 0)
12228 key_allowed
= thisarg
& ~N_KEY
;
12233 if ((thisarg
& N_VFP
) != 0)
12235 enum neon_shape_el regshape
;
12236 unsigned regwidth
, match
;
12238 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12241 first_error (_("invalid instruction shape"));
12244 regshape
= neon_shape_tab
[ns
].el
[i
];
12245 regwidth
= neon_shape_el_size
[regshape
];
12247 /* In VFP mode, operands must match register widths. If we
12248 have a key operand, use its width, else use the width of
12249 the current operand. */
12255 if (regwidth
!= match
)
12257 first_error (_("operand size must match register width"));
12262 if ((thisarg
& N_EQK
) == 0)
12264 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12266 if ((given_type
& types_allowed
) == 0)
12268 first_error (_("bad type in Neon instruction"));
12274 enum neon_el_type mod_k_type
= k_type
;
12275 unsigned mod_k_size
= k_size
;
12276 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12277 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12279 first_error (_("inconsistent types in Neon instruction"));
12287 return inst
.vectype
.el
[key_el
];
12290 /* Neon-style VFP instruction forwarding. */
12292 /* Thumb VFP instructions have 0xE in the condition field. */
12295 do_vfp_cond_or_thumb (void)
12300 inst
.instruction
|= 0xe0000000;
12302 inst
.instruction
|= inst
.cond
<< 28;
12305 /* Look up and encode a simple mnemonic, for use as a helper function for the
12306 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12307 etc. It is assumed that operand parsing has already been done, and that the
12308 operands are in the form expected by the given opcode (this isn't necessarily
12309 the same as the form in which they were parsed, hence some massaging must
12310 take place before this function is called).
12311 Checks current arch version against that in the looked-up opcode. */
12314 do_vfp_nsyn_opcode (const char *opname
)
12316 const struct asm_opcode
*opcode
;
12318 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12323 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12324 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12331 inst
.instruction
= opcode
->tvalue
;
12332 opcode
->tencode ();
12336 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12337 opcode
->aencode ();
12342 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12344 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12349 do_vfp_nsyn_opcode ("fadds");
12351 do_vfp_nsyn_opcode ("fsubs");
12356 do_vfp_nsyn_opcode ("faddd");
12358 do_vfp_nsyn_opcode ("fsubd");
12362 /* Check operand types to see if this is a VFP instruction, and if so call
12366 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12368 enum neon_shape rs
;
12369 struct neon_type_el et
;
12374 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12375 et
= neon_check_type (2, rs
,
12376 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12380 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12381 et
= neon_check_type (3, rs
,
12382 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12389 if (et
.type
!= NT_invtype
)
12400 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12402 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12407 do_vfp_nsyn_opcode ("fmacs");
12409 do_vfp_nsyn_opcode ("fnmacs");
12414 do_vfp_nsyn_opcode ("fmacd");
12416 do_vfp_nsyn_opcode ("fnmacd");
12421 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12423 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12428 do_vfp_nsyn_opcode ("ffmas");
12430 do_vfp_nsyn_opcode ("ffnmas");
12435 do_vfp_nsyn_opcode ("ffmad");
12437 do_vfp_nsyn_opcode ("ffnmad");
12442 do_vfp_nsyn_mul (enum neon_shape rs
)
12445 do_vfp_nsyn_opcode ("fmuls");
12447 do_vfp_nsyn_opcode ("fmuld");
12451 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12453 int is_neg
= (inst
.instruction
& 0x80) != 0;
12454 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12459 do_vfp_nsyn_opcode ("fnegs");
12461 do_vfp_nsyn_opcode ("fabss");
12466 do_vfp_nsyn_opcode ("fnegd");
12468 do_vfp_nsyn_opcode ("fabsd");
12472 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12473 insns belong to Neon, and are handled elsewhere. */
12476 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12478 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12482 do_vfp_nsyn_opcode ("fldmdbs");
12484 do_vfp_nsyn_opcode ("fldmias");
12489 do_vfp_nsyn_opcode ("fstmdbs");
12491 do_vfp_nsyn_opcode ("fstmias");
12496 do_vfp_nsyn_sqrt (void)
12498 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12499 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12502 do_vfp_nsyn_opcode ("fsqrts");
12504 do_vfp_nsyn_opcode ("fsqrtd");
12508 do_vfp_nsyn_div (void)
12510 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12511 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12512 N_F32
| N_F64
| N_KEY
| N_VFP
);
12515 do_vfp_nsyn_opcode ("fdivs");
12517 do_vfp_nsyn_opcode ("fdivd");
12521 do_vfp_nsyn_nmul (void)
12523 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12524 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12525 N_F32
| N_F64
| N_KEY
| N_VFP
);
12529 NEON_ENCODE (SINGLE
, inst
);
12530 do_vfp_sp_dyadic ();
12534 NEON_ENCODE (DOUBLE
, inst
);
12535 do_vfp_dp_rd_rn_rm ();
12537 do_vfp_cond_or_thumb ();
12541 do_vfp_nsyn_cmp (void)
12543 if (inst
.operands
[1].isreg
)
12545 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12546 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12550 NEON_ENCODE (SINGLE
, inst
);
12551 do_vfp_sp_monadic ();
12555 NEON_ENCODE (DOUBLE
, inst
);
12556 do_vfp_dp_rd_rm ();
12561 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12562 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12564 switch (inst
.instruction
& 0x0fffffff)
12567 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12570 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12578 NEON_ENCODE (SINGLE
, inst
);
12579 do_vfp_sp_compare_z ();
12583 NEON_ENCODE (DOUBLE
, inst
);
12587 do_vfp_cond_or_thumb ();
12591 nsyn_insert_sp (void)
12593 inst
.operands
[1] = inst
.operands
[0];
12594 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12595 inst
.operands
[0].reg
= REG_SP
;
12596 inst
.operands
[0].isreg
= 1;
12597 inst
.operands
[0].writeback
= 1;
12598 inst
.operands
[0].present
= 1;
12602 do_vfp_nsyn_push (void)
12605 if (inst
.operands
[1].issingle
)
12606 do_vfp_nsyn_opcode ("fstmdbs");
12608 do_vfp_nsyn_opcode ("fstmdbd");
12612 do_vfp_nsyn_pop (void)
12615 if (inst
.operands
[1].issingle
)
12616 do_vfp_nsyn_opcode ("fldmias");
12618 do_vfp_nsyn_opcode ("fldmiad");
12621 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12622 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12625 neon_dp_fixup (struct arm_it
* insn
)
12627 unsigned int i
= insn
->instruction
;
12632 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12643 insn
->instruction
= i
;
12646 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12650 neon_logbits (unsigned x
)
12652 return ffs (x
) - 4;
12655 #define LOW4(R) ((R) & 0xf)
12656 #define HI1(R) (((R) >> 4) & 1)
12658 /* Encode insns with bit pattern:
12660 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12661 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12663 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12664 different meaning for some instruction. */
12667 neon_three_same (int isquad
, int ubit
, int size
)
12669 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12670 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12671 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12672 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12673 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12674 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12675 inst
.instruction
|= (isquad
!= 0) << 6;
12676 inst
.instruction
|= (ubit
!= 0) << 24;
12678 inst
.instruction
|= neon_logbits (size
) << 20;
12680 neon_dp_fixup (&inst
);
12683 /* Encode instructions of the form:
12685 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12686 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12688 Don't write size if SIZE == -1. */
12691 neon_two_same (int qbit
, int ubit
, int size
)
12693 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12694 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12695 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12696 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12697 inst
.instruction
|= (qbit
!= 0) << 6;
12698 inst
.instruction
|= (ubit
!= 0) << 24;
12701 inst
.instruction
|= neon_logbits (size
) << 18;
12703 neon_dp_fixup (&inst
);
12706 /* Neon instruction encoders, in approximate order of appearance. */
12709 do_neon_dyadic_i_su (void)
12711 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12712 struct neon_type_el et
= neon_check_type (3, rs
,
12713 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12714 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12718 do_neon_dyadic_i64_su (void)
12720 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12721 struct neon_type_el et
= neon_check_type (3, rs
,
12722 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12723 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12727 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12730 unsigned size
= et
.size
>> 3;
12731 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12732 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12733 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12734 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12735 inst
.instruction
|= (isquad
!= 0) << 6;
12736 inst
.instruction
|= immbits
<< 16;
12737 inst
.instruction
|= (size
>> 3) << 7;
12738 inst
.instruction
|= (size
& 0x7) << 19;
12740 inst
.instruction
|= (uval
!= 0) << 24;
12742 neon_dp_fixup (&inst
);
12746 do_neon_shl_imm (void)
12748 if (!inst
.operands
[2].isreg
)
12750 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12751 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12752 NEON_ENCODE (IMMED
, inst
);
12753 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12757 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12758 struct neon_type_el et
= neon_check_type (3, rs
,
12759 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12762 /* VSHL/VQSHL 3-register variants have syntax such as:
12764 whereas other 3-register operations encoded by neon_three_same have
12767 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12769 tmp
= inst
.operands
[2].reg
;
12770 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12771 inst
.operands
[1].reg
= tmp
;
12772 NEON_ENCODE (INTEGER
, inst
);
12773 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12778 do_neon_qshl_imm (void)
12780 if (!inst
.operands
[2].isreg
)
12782 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12783 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12785 NEON_ENCODE (IMMED
, inst
);
12786 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12787 inst
.operands
[2].imm
);
12791 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12792 struct neon_type_el et
= neon_check_type (3, rs
,
12793 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12796 /* See note in do_neon_shl_imm. */
12797 tmp
= inst
.operands
[2].reg
;
12798 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12799 inst
.operands
[1].reg
= tmp
;
12800 NEON_ENCODE (INTEGER
, inst
);
12801 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12806 do_neon_rshl (void)
12808 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12809 struct neon_type_el et
= neon_check_type (3, rs
,
12810 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12813 tmp
= inst
.operands
[2].reg
;
12814 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12815 inst
.operands
[1].reg
= tmp
;
12816 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12820 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12822 /* Handle .I8 pseudo-instructions. */
12825 /* Unfortunately, this will make everything apart from zero out-of-range.
12826 FIXME is this the intended semantics? There doesn't seem much point in
12827 accepting .I8 if so. */
12828 immediate
|= immediate
<< 8;
12834 if (immediate
== (immediate
& 0x000000ff))
12836 *immbits
= immediate
;
12839 else if (immediate
== (immediate
& 0x0000ff00))
12841 *immbits
= immediate
>> 8;
12844 else if (immediate
== (immediate
& 0x00ff0000))
12846 *immbits
= immediate
>> 16;
12849 else if (immediate
== (immediate
& 0xff000000))
12851 *immbits
= immediate
>> 24;
12854 if ((immediate
& 0xffff) != (immediate
>> 16))
12855 goto bad_immediate
;
12856 immediate
&= 0xffff;
12859 if (immediate
== (immediate
& 0x000000ff))
12861 *immbits
= immediate
;
12864 else if (immediate
== (immediate
& 0x0000ff00))
12866 *immbits
= immediate
>> 8;
12871 first_error (_("immediate value out of range"));
12875 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12879 neon_bits_same_in_bytes (unsigned imm
)
12881 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12882 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12883 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12884 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12887 /* For immediate of above form, return 0bABCD. */
12890 neon_squash_bits (unsigned imm
)
12892 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12893 | ((imm
& 0x01000000) >> 21);
12896 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12899 neon_qfloat_bits (unsigned imm
)
12901 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12904 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12905 the instruction. *OP is passed as the initial value of the op field, and
12906 may be set to a different value depending on the constant (i.e.
12907 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12908 MVN). If the immediate looks like a repeated pattern then also
12909 try smaller element sizes. */
12912 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12913 unsigned *immbits
, int *op
, int size
,
12914 enum neon_el_type type
)
12916 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12918 if (type
== NT_float
&& !float_p
)
12921 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12923 if (size
!= 32 || *op
== 1)
12925 *immbits
= neon_qfloat_bits (immlo
);
12931 if (neon_bits_same_in_bytes (immhi
)
12932 && neon_bits_same_in_bytes (immlo
))
12936 *immbits
= (neon_squash_bits (immhi
) << 4)
12937 | neon_squash_bits (immlo
);
12942 if (immhi
!= immlo
)
12948 if (immlo
== (immlo
& 0x000000ff))
12953 else if (immlo
== (immlo
& 0x0000ff00))
12955 *immbits
= immlo
>> 8;
12958 else if (immlo
== (immlo
& 0x00ff0000))
12960 *immbits
= immlo
>> 16;
12963 else if (immlo
== (immlo
& 0xff000000))
12965 *immbits
= immlo
>> 24;
12968 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12970 *immbits
= (immlo
>> 8) & 0xff;
12973 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12975 *immbits
= (immlo
>> 16) & 0xff;
12979 if ((immlo
& 0xffff) != (immlo
>> 16))
12986 if (immlo
== (immlo
& 0x000000ff))
12991 else if (immlo
== (immlo
& 0x0000ff00))
12993 *immbits
= immlo
>> 8;
12997 if ((immlo
& 0xff) != (immlo
>> 8))
13002 if (immlo
== (immlo
& 0x000000ff))
13004 /* Don't allow MVN with 8-bit immediate. */
13014 /* Write immediate bits [7:0] to the following locations:
13016 |28/24|23 19|18 16|15 4|3 0|
13017 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13019 This function is used by VMOV/VMVN/VORR/VBIC. */
13022 neon_write_immbits (unsigned immbits
)
13024 inst
.instruction
|= immbits
& 0xf;
13025 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13026 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13029 /* Invert low-order SIZE bits of XHI:XLO. */
13032 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13034 unsigned immlo
= xlo
? *xlo
: 0;
13035 unsigned immhi
= xhi
? *xhi
: 0;
13040 immlo
= (~immlo
) & 0xff;
13044 immlo
= (~immlo
) & 0xffff;
13048 immhi
= (~immhi
) & 0xffffffff;
13049 /* fall through. */
13052 immlo
= (~immlo
) & 0xffffffff;
13067 do_neon_logic (void)
13069 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13071 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13072 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13073 /* U bit and size field were set as part of the bitmask. */
13074 NEON_ENCODE (INTEGER
, inst
);
13075 neon_three_same (neon_quad (rs
), 0, -1);
13079 const int three_ops_form
= (inst
.operands
[2].present
13080 && !inst
.operands
[2].isreg
);
13081 const int immoperand
= (three_ops_form
? 2 : 1);
13082 enum neon_shape rs
= (three_ops_form
13083 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13084 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13085 struct neon_type_el et
= neon_check_type (2, rs
,
13086 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13087 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13091 if (et
.type
== NT_invtype
)
13094 if (three_ops_form
)
13095 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13096 _("first and second operands shall be the same register"));
13098 NEON_ENCODE (IMMED
, inst
);
13100 immbits
= inst
.operands
[immoperand
].imm
;
13103 /* .i64 is a pseudo-op, so the immediate must be a repeating
13105 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13106 inst
.operands
[immoperand
].reg
: 0))
13108 /* Set immbits to an invalid constant. */
13109 immbits
= 0xdeadbeef;
13116 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13120 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13124 /* Pseudo-instruction for VBIC. */
13125 neon_invert_size (&immbits
, 0, et
.size
);
13126 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13130 /* Pseudo-instruction for VORR. */
13131 neon_invert_size (&immbits
, 0, et
.size
);
13132 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13142 inst
.instruction
|= neon_quad (rs
) << 6;
13143 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13144 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13145 inst
.instruction
|= cmode
<< 8;
13146 neon_write_immbits (immbits
);
13148 neon_dp_fixup (&inst
);
13153 do_neon_bitfield (void)
13155 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13156 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13157 neon_three_same (neon_quad (rs
), 0, -1);
13161 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13164 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13165 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13167 if (et
.type
== NT_float
)
13169 NEON_ENCODE (FLOAT
, inst
);
13170 neon_three_same (neon_quad (rs
), 0, -1);
13174 NEON_ENCODE (INTEGER
, inst
);
13175 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13180 do_neon_dyadic_if_su (void)
13182 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13186 do_neon_dyadic_if_su_d (void)
13188 /* This version only allow D registers, but that constraint is enforced during
13189 operand parsing so we don't need to do anything extra here. */
13190 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13194 do_neon_dyadic_if_i_d (void)
13196 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13197 affected if we specify unsigned args. */
13198 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13201 enum vfp_or_neon_is_neon_bits
13204 NEON_CHECK_ARCH
= 2
13207 /* Call this function if an instruction which may have belonged to the VFP or
13208 Neon instruction sets, but turned out to be a Neon instruction (due to the
13209 operand types involved, etc.). We have to check and/or fix-up a couple of
13212 - Make sure the user hasn't attempted to make a Neon instruction
13214 - Alter the value in the condition code field if necessary.
13215 - Make sure that the arch supports Neon instructions.
13217 Which of these operations take place depends on bits from enum
13218 vfp_or_neon_is_neon_bits.
13220 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13221 current instruction's condition is COND_ALWAYS, the condition field is
13222 changed to inst.uncond_value. This is necessary because instructions shared
13223 between VFP and Neon may be conditional for the VFP variants only, and the
13224 unconditional Neon version must have, e.g., 0xF in the condition field. */
13227 vfp_or_neon_is_neon (unsigned check
)
13229 /* Conditions are always legal in Thumb mode (IT blocks). */
13230 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13232 if (inst
.cond
!= COND_ALWAYS
)
13234 first_error (_(BAD_COND
));
13237 if (inst
.uncond_value
!= -1)
13238 inst
.instruction
|= inst
.uncond_value
<< 28;
13241 if ((check
& NEON_CHECK_ARCH
)
13242 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13244 first_error (_(BAD_FPU
));
13252 do_neon_addsub_if_i (void)
13254 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13257 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13260 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13261 affected if we specify unsigned args. */
13262 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13265 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13267 V<op> A,B (A is operand 0, B is operand 2)
13272 so handle that case specially. */
13275 neon_exchange_operands (void)
13277 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13278 if (inst
.operands
[1].present
)
13280 /* Swap operands[1] and operands[2]. */
13281 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13282 inst
.operands
[1] = inst
.operands
[2];
13283 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13287 inst
.operands
[1] = inst
.operands
[2];
13288 inst
.operands
[2] = inst
.operands
[0];
13293 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13295 if (inst
.operands
[2].isreg
)
13298 neon_exchange_operands ();
13299 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13303 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13304 struct neon_type_el et
= neon_check_type (2, rs
,
13305 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13307 NEON_ENCODE (IMMED
, inst
);
13308 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13309 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13310 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13311 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13312 inst
.instruction
|= neon_quad (rs
) << 6;
13313 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13314 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13316 neon_dp_fixup (&inst
);
13323 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13327 do_neon_cmp_inv (void)
13329 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13335 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13338 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13339 scalars, which are encoded in 5 bits, M : Rm.
13340 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13341 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13345 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13347 unsigned regno
= NEON_SCALAR_REG (scalar
);
13348 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13353 if (regno
> 7 || elno
> 3)
13355 return regno
| (elno
<< 3);
13358 if (regno
> 15 || elno
> 1)
13360 return regno
| (elno
<< 4);
13364 first_error (_("scalar out of range for multiply instruction"));
13370 /* Encode multiply / multiply-accumulate scalar instructions. */
13373 neon_mul_mac (struct neon_type_el et
, int ubit
)
13377 /* Give a more helpful error message if we have an invalid type. */
13378 if (et
.type
== NT_invtype
)
13381 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13382 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13383 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13384 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13385 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13386 inst
.instruction
|= LOW4 (scalar
);
13387 inst
.instruction
|= HI1 (scalar
) << 5;
13388 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13389 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13390 inst
.instruction
|= (ubit
!= 0) << 24;
13392 neon_dp_fixup (&inst
);
13396 do_neon_mac_maybe_scalar (void)
13398 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13401 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13404 if (inst
.operands
[2].isscalar
)
13406 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13407 struct neon_type_el et
= neon_check_type (3, rs
,
13408 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13409 NEON_ENCODE (SCALAR
, inst
);
13410 neon_mul_mac (et
, neon_quad (rs
));
13414 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13415 affected if we specify unsigned args. */
13416 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13421 do_neon_fmac (void)
13423 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13426 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13429 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13435 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13436 struct neon_type_el et
= neon_check_type (3, rs
,
13437 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13438 neon_three_same (neon_quad (rs
), 0, et
.size
);
13441 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13442 same types as the MAC equivalents. The polynomial type for this instruction
13443 is encoded the same as the integer type. */
13448 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13451 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13454 if (inst
.operands
[2].isscalar
)
13455 do_neon_mac_maybe_scalar ();
13457 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13461 do_neon_qdmulh (void)
13463 if (inst
.operands
[2].isscalar
)
13465 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13466 struct neon_type_el et
= neon_check_type (3, rs
,
13467 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13468 NEON_ENCODE (SCALAR
, inst
);
13469 neon_mul_mac (et
, neon_quad (rs
));
13473 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13474 struct neon_type_el et
= neon_check_type (3, rs
,
13475 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13476 NEON_ENCODE (INTEGER
, inst
);
13477 /* The U bit (rounding) comes from bit mask. */
13478 neon_three_same (neon_quad (rs
), 0, et
.size
);
13483 do_neon_fcmp_absolute (void)
13485 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13486 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13487 /* Size field comes from bit mask. */
13488 neon_three_same (neon_quad (rs
), 1, -1);
13492 do_neon_fcmp_absolute_inv (void)
13494 neon_exchange_operands ();
13495 do_neon_fcmp_absolute ();
13499 do_neon_step (void)
13501 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13502 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13503 neon_three_same (neon_quad (rs
), 0, -1);
13507 do_neon_abs_neg (void)
13509 enum neon_shape rs
;
13510 struct neon_type_el et
;
13512 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13515 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13518 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13519 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13521 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13522 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13523 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13524 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13525 inst
.instruction
|= neon_quad (rs
) << 6;
13526 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13527 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13529 neon_dp_fixup (&inst
);
13535 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13536 struct neon_type_el et
= neon_check_type (2, rs
,
13537 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13538 int imm
= inst
.operands
[2].imm
;
13539 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13540 _("immediate out of range for insert"));
13541 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13547 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13548 struct neon_type_el et
= neon_check_type (2, rs
,
13549 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13550 int imm
= inst
.operands
[2].imm
;
13551 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13552 _("immediate out of range for insert"));
13553 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13557 do_neon_qshlu_imm (void)
13559 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13560 struct neon_type_el et
= neon_check_type (2, rs
,
13561 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13562 int imm
= inst
.operands
[2].imm
;
13563 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13564 _("immediate out of range for shift"));
13565 /* Only encodes the 'U present' variant of the instruction.
13566 In this case, signed types have OP (bit 8) set to 0.
13567 Unsigned types have OP set to 1. */
13568 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13569 /* The rest of the bits are the same as other immediate shifts. */
13570 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13574 do_neon_qmovn (void)
13576 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13577 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13578 /* Saturating move where operands can be signed or unsigned, and the
13579 destination has the same signedness. */
13580 NEON_ENCODE (INTEGER
, inst
);
13581 if (et
.type
== NT_unsigned
)
13582 inst
.instruction
|= 0xc0;
13584 inst
.instruction
|= 0x80;
13585 neon_two_same (0, 1, et
.size
/ 2);
13589 do_neon_qmovun (void)
13591 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13592 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13593 /* Saturating move with unsigned results. Operands must be signed. */
13594 NEON_ENCODE (INTEGER
, inst
);
13595 neon_two_same (0, 1, et
.size
/ 2);
13599 do_neon_rshift_sat_narrow (void)
13601 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13602 or unsigned. If operands are unsigned, results must also be unsigned. */
13603 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13604 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13605 int imm
= inst
.operands
[2].imm
;
13606 /* This gets the bounds check, size encoding and immediate bits calculation
13610 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13611 VQMOVN.I<size> <Dd>, <Qm>. */
13614 inst
.operands
[2].present
= 0;
13615 inst
.instruction
= N_MNEM_vqmovn
;
13620 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13621 _("immediate out of range"));
13622 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13626 do_neon_rshift_sat_narrow_u (void)
13628 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13629 or unsigned. If operands are unsigned, results must also be unsigned. */
13630 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13631 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13632 int imm
= inst
.operands
[2].imm
;
13633 /* This gets the bounds check, size encoding and immediate bits calculation
13637 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13638 VQMOVUN.I<size> <Dd>, <Qm>. */
13641 inst
.operands
[2].present
= 0;
13642 inst
.instruction
= N_MNEM_vqmovun
;
13647 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13648 _("immediate out of range"));
13649 /* FIXME: The manual is kind of unclear about what value U should have in
13650 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13652 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13656 do_neon_movn (void)
13658 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13659 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13660 NEON_ENCODE (INTEGER
, inst
);
13661 neon_two_same (0, 1, et
.size
/ 2);
13665 do_neon_rshift_narrow (void)
13667 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13668 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13669 int imm
= inst
.operands
[2].imm
;
13670 /* This gets the bounds check, size encoding and immediate bits calculation
13674 /* If immediate is zero then we are a pseudo-instruction for
13675 VMOVN.I<size> <Dd>, <Qm> */
13678 inst
.operands
[2].present
= 0;
13679 inst
.instruction
= N_MNEM_vmovn
;
13684 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13685 _("immediate out of range for narrowing operation"));
13686 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13690 do_neon_shll (void)
13692 /* FIXME: Type checking when lengthening. */
13693 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13694 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13695 unsigned imm
= inst
.operands
[2].imm
;
13697 if (imm
== et
.size
)
13699 /* Maximum shift variant. */
13700 NEON_ENCODE (INTEGER
, inst
);
13701 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13702 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13703 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13704 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13705 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13707 neon_dp_fixup (&inst
);
13711 /* A more-specific type check for non-max versions. */
13712 et
= neon_check_type (2, NS_QDI
,
13713 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13714 NEON_ENCODE (IMMED
, inst
);
13715 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13719 /* Check the various types for the VCVT instruction, and return which version
13720 the current instruction is. */
13723 neon_cvt_flavour (enum neon_shape rs
)
13725 #define CVT_VAR(C,X,Y) \
13726 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13727 if (et.type != NT_invtype) \
13729 inst.error = NULL; \
13732 struct neon_type_el et
;
13733 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13734 || rs
== NS_FF
) ? N_VFP
: 0;
13735 /* The instruction versions which take an immediate take one register
13736 argument, which is extended to the width of the full register. Thus the
13737 "source" and "destination" registers must have the same width. Hack that
13738 here by making the size equal to the key (wider, in this case) operand. */
13739 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13741 CVT_VAR (0, N_S32
, N_F32
);
13742 CVT_VAR (1, N_U32
, N_F32
);
13743 CVT_VAR (2, N_F32
, N_S32
);
13744 CVT_VAR (3, N_F32
, N_U32
);
13745 /* Half-precision conversions. */
13746 CVT_VAR (4, N_F32
, N_F16
);
13747 CVT_VAR (5, N_F16
, N_F32
);
13751 /* VFP instructions. */
13752 CVT_VAR (6, N_F32
, N_F64
);
13753 CVT_VAR (7, N_F64
, N_F32
);
13754 CVT_VAR (8, N_S32
, N_F64
| key
);
13755 CVT_VAR (9, N_U32
, N_F64
| key
);
13756 CVT_VAR (10, N_F64
| key
, N_S32
);
13757 CVT_VAR (11, N_F64
| key
, N_U32
);
13758 /* VFP instructions with bitshift. */
13759 CVT_VAR (12, N_F32
| key
, N_S16
);
13760 CVT_VAR (13, N_F32
| key
, N_U16
);
13761 CVT_VAR (14, N_F64
| key
, N_S16
);
13762 CVT_VAR (15, N_F64
| key
, N_U16
);
13763 CVT_VAR (16, N_S16
, N_F32
| key
);
13764 CVT_VAR (17, N_U16
, N_F32
| key
);
13765 CVT_VAR (18, N_S16
, N_F64
| key
);
13766 CVT_VAR (19, N_U16
, N_F64
| key
);
13772 /* Neon-syntax VFP conversions. */
13775 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13777 const char *opname
= 0;
13779 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13781 /* Conversions with immediate bitshift. */
13782 const char *enc
[] =
13806 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13808 opname
= enc
[flavour
];
13809 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13810 _("operands 0 and 1 must be the same register"));
13811 inst
.operands
[1] = inst
.operands
[2];
13812 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13817 /* Conversions without bitshift. */
13818 const char *enc
[] =
13834 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13835 opname
= enc
[flavour
];
13839 do_vfp_nsyn_opcode (opname
);
13843 do_vfp_nsyn_cvtz (void)
13845 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13846 int flavour
= neon_cvt_flavour (rs
);
13847 const char *enc
[] =
13861 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13862 do_vfp_nsyn_opcode (enc
[flavour
]);
13866 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13868 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13869 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13870 int flavour
= neon_cvt_flavour (rs
);
13872 /* PR11109: Handle round-to-zero for VCVT conversions. */
13874 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13875 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13876 && (rs
== NS_FD
|| rs
== NS_FF
))
13878 do_vfp_nsyn_cvtz ();
13882 /* VFP rather than Neon conversions. */
13885 do_vfp_nsyn_cvt (rs
, flavour
);
13895 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13897 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13900 /* Fixed-point conversion with #0 immediate is encoded as an
13901 integer conversion. */
13902 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13904 immbits
= 32 - inst
.operands
[2].imm
;
13905 NEON_ENCODE (IMMED
, inst
);
13907 inst
.instruction
|= enctab
[flavour
];
13908 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13909 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13910 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13911 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13912 inst
.instruction
|= neon_quad (rs
) << 6;
13913 inst
.instruction
|= 1 << 21;
13914 inst
.instruction
|= immbits
<< 16;
13916 neon_dp_fixup (&inst
);
13924 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13926 NEON_ENCODE (INTEGER
, inst
);
13928 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13932 inst
.instruction
|= enctab
[flavour
];
13934 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13935 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13936 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13937 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13938 inst
.instruction
|= neon_quad (rs
) << 6;
13939 inst
.instruction
|= 2 << 18;
13941 neon_dp_fixup (&inst
);
13945 /* Half-precision conversions for Advanced SIMD -- neon. */
13950 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13952 as_bad (_("operand size must match register width"));
13957 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13959 as_bad (_("operand size must match register width"));
13964 inst
.instruction
= 0x3b60600;
13966 inst
.instruction
= 0x3b60700;
13968 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13969 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13970 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13971 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13972 neon_dp_fixup (&inst
);
13976 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13977 do_vfp_nsyn_cvt (rs
, flavour
);
13982 do_neon_cvtr (void)
13984 do_neon_cvt_1 (FALSE
);
13990 do_neon_cvt_1 (TRUE
);
13994 do_neon_cvtb (void)
13996 inst
.instruction
= 0xeb20a40;
13998 /* The sizes are attached to the mnemonic. */
13999 if (inst
.vectype
.el
[0].type
!= NT_invtype
14000 && inst
.vectype
.el
[0].size
== 16)
14001 inst
.instruction
|= 0x00010000;
14003 /* Programmer's syntax: the sizes are attached to the operands. */
14004 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14005 && inst
.operands
[0].vectype
.size
== 16)
14006 inst
.instruction
|= 0x00010000;
14008 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14009 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14010 do_vfp_cond_or_thumb ();
14015 do_neon_cvtt (void)
14018 inst
.instruction
|= 0x80;
14022 neon_move_immediate (void)
14024 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14025 struct neon_type_el et
= neon_check_type (2, rs
,
14026 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14027 unsigned immlo
, immhi
= 0, immbits
;
14028 int op
, cmode
, float_p
;
14030 constraint (et
.type
== NT_invtype
,
14031 _("operand size must be specified for immediate VMOV"));
14033 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14034 op
= (inst
.instruction
& (1 << 5)) != 0;
14036 immlo
= inst
.operands
[1].imm
;
14037 if (inst
.operands
[1].regisimm
)
14038 immhi
= inst
.operands
[1].reg
;
14040 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14041 _("immediate has bits set outside the operand size"));
14043 float_p
= inst
.operands
[1].immisfloat
;
14045 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14046 et
.size
, et
.type
)) == FAIL
)
14048 /* Invert relevant bits only. */
14049 neon_invert_size (&immlo
, &immhi
, et
.size
);
14050 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14051 with one or the other; those cases are caught by
14052 neon_cmode_for_move_imm. */
14054 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14055 &op
, et
.size
, et
.type
)) == FAIL
)
14057 first_error (_("immediate out of range"));
14062 inst
.instruction
&= ~(1 << 5);
14063 inst
.instruction
|= op
<< 5;
14065 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14066 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14067 inst
.instruction
|= neon_quad (rs
) << 6;
14068 inst
.instruction
|= cmode
<< 8;
14070 neon_write_immbits (immbits
);
14076 if (inst
.operands
[1].isreg
)
14078 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14080 NEON_ENCODE (INTEGER
, inst
);
14081 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14082 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14083 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14084 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14085 inst
.instruction
|= neon_quad (rs
) << 6;
14089 NEON_ENCODE (IMMED
, inst
);
14090 neon_move_immediate ();
14093 neon_dp_fixup (&inst
);
14096 /* Encode instructions of form:
14098 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14099 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14102 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14104 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14105 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14106 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14107 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14108 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14109 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14110 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14111 inst
.instruction
|= neon_logbits (size
) << 20;
14113 neon_dp_fixup (&inst
);
14117 do_neon_dyadic_long (void)
14119 /* FIXME: Type checking for lengthening op. */
14120 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14121 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14122 neon_mixed_length (et
, et
.size
);
14126 do_neon_abal (void)
14128 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14129 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14130 neon_mixed_length (et
, et
.size
);
14134 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14136 if (inst
.operands
[2].isscalar
)
14138 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14139 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14140 NEON_ENCODE (SCALAR
, inst
);
14141 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14145 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14146 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14147 NEON_ENCODE (INTEGER
, inst
);
14148 neon_mixed_length (et
, et
.size
);
14153 do_neon_mac_maybe_scalar_long (void)
14155 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14159 do_neon_dyadic_wide (void)
14161 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14162 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14163 neon_mixed_length (et
, et
.size
);
14167 do_neon_dyadic_narrow (void)
14169 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14170 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14171 /* Operand sign is unimportant, and the U bit is part of the opcode,
14172 so force the operand type to integer. */
14173 et
.type
= NT_integer
;
14174 neon_mixed_length (et
, et
.size
/ 2);
14178 do_neon_mul_sat_scalar_long (void)
14180 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14184 do_neon_vmull (void)
14186 if (inst
.operands
[2].isscalar
)
14187 do_neon_mac_maybe_scalar_long ();
14190 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14191 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14192 if (et
.type
== NT_poly
)
14193 NEON_ENCODE (POLY
, inst
);
14195 NEON_ENCODE (INTEGER
, inst
);
14196 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14197 zero. Should be OK as-is. */
14198 neon_mixed_length (et
, et
.size
);
14205 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14206 struct neon_type_el et
= neon_check_type (3, rs
,
14207 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14208 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14210 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14211 _("shift out of range"));
14212 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14213 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14214 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14215 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14216 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14217 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14218 inst
.instruction
|= neon_quad (rs
) << 6;
14219 inst
.instruction
|= imm
<< 8;
14221 neon_dp_fixup (&inst
);
14227 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14228 struct neon_type_el et
= neon_check_type (2, rs
,
14229 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14230 unsigned op
= (inst
.instruction
>> 7) & 3;
14231 /* N (width of reversed regions) is encoded as part of the bitmask. We
14232 extract it here to check the elements to be reversed are smaller.
14233 Otherwise we'd get a reserved instruction. */
14234 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14235 gas_assert (elsize
!= 0);
14236 constraint (et
.size
>= elsize
,
14237 _("elements must be smaller than reversal region"));
14238 neon_two_same (neon_quad (rs
), 1, et
.size
);
14244 if (inst
.operands
[1].isscalar
)
14246 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14247 struct neon_type_el et
= neon_check_type (2, rs
,
14248 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14249 unsigned sizebits
= et
.size
>> 3;
14250 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14251 int logsize
= neon_logbits (et
.size
);
14252 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14254 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14257 NEON_ENCODE (SCALAR
, inst
);
14258 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14259 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14260 inst
.instruction
|= LOW4 (dm
);
14261 inst
.instruction
|= HI1 (dm
) << 5;
14262 inst
.instruction
|= neon_quad (rs
) << 6;
14263 inst
.instruction
|= x
<< 17;
14264 inst
.instruction
|= sizebits
<< 16;
14266 neon_dp_fixup (&inst
);
14270 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14271 struct neon_type_el et
= neon_check_type (2, rs
,
14272 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14273 /* Duplicate ARM register to lanes of vector. */
14274 NEON_ENCODE (ARMREG
, inst
);
14277 case 8: inst
.instruction
|= 0x400000; break;
14278 case 16: inst
.instruction
|= 0x000020; break;
14279 case 32: inst
.instruction
|= 0x000000; break;
14282 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14283 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14284 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14285 inst
.instruction
|= neon_quad (rs
) << 21;
14286 /* The encoding for this instruction is identical for the ARM and Thumb
14287 variants, except for the condition field. */
14288 do_vfp_cond_or_thumb ();
14292 /* VMOV has particularly many variations. It can be one of:
14293 0. VMOV<c><q> <Qd>, <Qm>
14294 1. VMOV<c><q> <Dd>, <Dm>
14295 (Register operations, which are VORR with Rm = Rn.)
14296 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14297 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14299 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14300 (ARM register to scalar.)
14301 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14302 (Two ARM registers to vector.)
14303 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14304 (Scalar to ARM register.)
14305 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14306 (Vector to two ARM registers.)
14307 8. VMOV.F32 <Sd>, <Sm>
14308 9. VMOV.F64 <Dd>, <Dm>
14309 (VFP register moves.)
14310 10. VMOV.F32 <Sd>, #imm
14311 11. VMOV.F64 <Dd>, #imm
14312 (VFP float immediate load.)
14313 12. VMOV <Rd>, <Sm>
14314 (VFP single to ARM reg.)
14315 13. VMOV <Sd>, <Rm>
14316 (ARM reg to VFP single.)
14317 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14318 (Two ARM regs to two VFP singles.)
14319 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14320 (Two VFP singles to two ARM regs.)
14322 These cases can be disambiguated using neon_select_shape, except cases 1/9
14323 and 3/11 which depend on the operand type too.
14325 All the encoded bits are hardcoded by this function.
14327 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14328 Cases 5, 7 may be used with VFPv2 and above.
14330 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14331 can specify a type where it doesn't make sense to, and is ignored). */
14336 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14337 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14339 struct neon_type_el et
;
14340 const char *ldconst
= 0;
14344 case NS_DD
: /* case 1/9. */
14345 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14346 /* It is not an error here if no type is given. */
14348 if (et
.type
== NT_float
&& et
.size
== 64)
14350 do_vfp_nsyn_opcode ("fcpyd");
14353 /* fall through. */
14355 case NS_QQ
: /* case 0/1. */
14357 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14359 /* The architecture manual I have doesn't explicitly state which
14360 value the U bit should have for register->register moves, but
14361 the equivalent VORR instruction has U = 0, so do that. */
14362 inst
.instruction
= 0x0200110;
14363 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14364 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14365 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14366 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14367 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14368 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14369 inst
.instruction
|= neon_quad (rs
) << 6;
14371 neon_dp_fixup (&inst
);
14375 case NS_DI
: /* case 3/11. */
14376 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14378 if (et
.type
== NT_float
&& et
.size
== 64)
14380 /* case 11 (fconstd). */
14381 ldconst
= "fconstd";
14382 goto encode_fconstd
;
14384 /* fall through. */
14386 case NS_QI
: /* case 2/3. */
14387 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14389 inst
.instruction
= 0x0800010;
14390 neon_move_immediate ();
14391 neon_dp_fixup (&inst
);
14394 case NS_SR
: /* case 4. */
14396 unsigned bcdebits
= 0;
14398 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14399 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14401 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14402 logsize
= neon_logbits (et
.size
);
14404 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14406 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14407 && et
.size
!= 32, _(BAD_FPU
));
14408 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14409 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14413 case 8: bcdebits
= 0x8; break;
14414 case 16: bcdebits
= 0x1; break;
14415 case 32: bcdebits
= 0x0; break;
14419 bcdebits
|= x
<< logsize
;
14421 inst
.instruction
= 0xe000b10;
14422 do_vfp_cond_or_thumb ();
14423 inst
.instruction
|= LOW4 (dn
) << 16;
14424 inst
.instruction
|= HI1 (dn
) << 7;
14425 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14426 inst
.instruction
|= (bcdebits
& 3) << 5;
14427 inst
.instruction
|= (bcdebits
>> 2) << 21;
14431 case NS_DRR
: /* case 5 (fmdrr). */
14432 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14435 inst
.instruction
= 0xc400b10;
14436 do_vfp_cond_or_thumb ();
14437 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14438 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14439 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14440 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14443 case NS_RS
: /* case 6. */
14446 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14447 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14448 unsigned abcdebits
= 0;
14450 et
= neon_check_type (2, NS_NULL
,
14451 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14452 logsize
= neon_logbits (et
.size
);
14454 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14456 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14457 && et
.size
!= 32, _(BAD_FPU
));
14458 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14459 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14463 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14464 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14465 case 32: abcdebits
= 0x00; break;
14469 abcdebits
|= x
<< logsize
;
14470 inst
.instruction
= 0xe100b10;
14471 do_vfp_cond_or_thumb ();
14472 inst
.instruction
|= LOW4 (dn
) << 16;
14473 inst
.instruction
|= HI1 (dn
) << 7;
14474 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14475 inst
.instruction
|= (abcdebits
& 3) << 5;
14476 inst
.instruction
|= (abcdebits
>> 2) << 21;
14480 case NS_RRD
: /* case 7 (fmrrd). */
14481 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14484 inst
.instruction
= 0xc500b10;
14485 do_vfp_cond_or_thumb ();
14486 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14487 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14488 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14489 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14492 case NS_FF
: /* case 8 (fcpys). */
14493 do_vfp_nsyn_opcode ("fcpys");
14496 case NS_FI
: /* case 10 (fconsts). */
14497 ldconst
= "fconsts";
14499 if (is_quarter_float (inst
.operands
[1].imm
))
14501 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14502 do_vfp_nsyn_opcode (ldconst
);
14505 first_error (_("immediate out of range"));
14508 case NS_RF
: /* case 12 (fmrs). */
14509 do_vfp_nsyn_opcode ("fmrs");
14512 case NS_FR
: /* case 13 (fmsr). */
14513 do_vfp_nsyn_opcode ("fmsr");
14516 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14517 (one of which is a list), but we have parsed four. Do some fiddling to
14518 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14520 case NS_RRFF
: /* case 14 (fmrrs). */
14521 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14522 _("VFP registers must be adjacent"));
14523 inst
.operands
[2].imm
= 2;
14524 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14525 do_vfp_nsyn_opcode ("fmrrs");
14528 case NS_FFRR
: /* case 15 (fmsrr). */
14529 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14530 _("VFP registers must be adjacent"));
14531 inst
.operands
[1] = inst
.operands
[2];
14532 inst
.operands
[2] = inst
.operands
[3];
14533 inst
.operands
[0].imm
= 2;
14534 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14535 do_vfp_nsyn_opcode ("fmsrr");
14544 do_neon_rshift_round_imm (void)
14546 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14547 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14548 int imm
= inst
.operands
[2].imm
;
14550 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14553 inst
.operands
[2].present
= 0;
14558 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14559 _("immediate out of range for shift"));
14560 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14565 do_neon_movl (void)
14567 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14568 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14569 unsigned sizebits
= et
.size
>> 3;
14570 inst
.instruction
|= sizebits
<< 19;
14571 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14577 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14578 struct neon_type_el et
= neon_check_type (2, rs
,
14579 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14580 NEON_ENCODE (INTEGER
, inst
);
14581 neon_two_same (neon_quad (rs
), 1, et
.size
);
14585 do_neon_zip_uzp (void)
14587 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14588 struct neon_type_el et
= neon_check_type (2, rs
,
14589 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14590 if (rs
== NS_DD
&& et
.size
== 32)
14592 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14593 inst
.instruction
= N_MNEM_vtrn
;
14597 neon_two_same (neon_quad (rs
), 1, et
.size
);
14601 do_neon_sat_abs_neg (void)
14603 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14604 struct neon_type_el et
= neon_check_type (2, rs
,
14605 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14606 neon_two_same (neon_quad (rs
), 1, et
.size
);
14610 do_neon_pair_long (void)
14612 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14613 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14614 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14615 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14616 neon_two_same (neon_quad (rs
), 1, et
.size
);
14620 do_neon_recip_est (void)
14622 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14623 struct neon_type_el et
= neon_check_type (2, rs
,
14624 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14625 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14626 neon_two_same (neon_quad (rs
), 1, et
.size
);
14632 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14633 struct neon_type_el et
= neon_check_type (2, rs
,
14634 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14635 neon_two_same (neon_quad (rs
), 1, et
.size
);
14641 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14642 struct neon_type_el et
= neon_check_type (2, rs
,
14643 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14644 neon_two_same (neon_quad (rs
), 1, et
.size
);
14650 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14651 struct neon_type_el et
= neon_check_type (2, rs
,
14652 N_EQK
| N_INT
, N_8
| N_KEY
);
14653 neon_two_same (neon_quad (rs
), 1, et
.size
);
14659 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14660 neon_two_same (neon_quad (rs
), 1, -1);
14664 do_neon_tbl_tbx (void)
14666 unsigned listlenbits
;
14667 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14669 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14671 first_error (_("bad list length for table lookup"));
14675 listlenbits
= inst
.operands
[1].imm
- 1;
14676 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14677 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14678 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14679 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14680 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14681 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14682 inst
.instruction
|= listlenbits
<< 8;
14684 neon_dp_fixup (&inst
);
14688 do_neon_ldm_stm (void)
14690 /* P, U and L bits are part of bitmask. */
14691 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14692 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14694 if (inst
.operands
[1].issingle
)
14696 do_vfp_nsyn_ldm_stm (is_dbmode
);
14700 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14701 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14703 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14704 _("register list must contain at least 1 and at most 16 "
14707 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14708 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14709 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14710 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14712 inst
.instruction
|= offsetbits
;
14714 do_vfp_cond_or_thumb ();
14718 do_neon_ldr_str (void)
14720 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14722 if (inst
.operands
[0].issingle
)
14725 do_vfp_nsyn_opcode ("flds");
14727 do_vfp_nsyn_opcode ("fsts");
14732 do_vfp_nsyn_opcode ("fldd");
14734 do_vfp_nsyn_opcode ("fstd");
14738 /* "interleave" version also handles non-interleaving register VLD1/VST1
14742 do_neon_ld_st_interleave (void)
14744 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14745 N_8
| N_16
| N_32
| N_64
);
14746 unsigned alignbits
= 0;
14748 /* The bits in this table go:
14749 0: register stride of one (0) or two (1)
14750 1,2: register list length, minus one (1, 2, 3, 4).
14751 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14752 We use -1 for invalid entries. */
14753 const int typetable
[] =
14755 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14756 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14757 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14758 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14762 if (et
.type
== NT_invtype
)
14765 if (inst
.operands
[1].immisalign
)
14766 switch (inst
.operands
[1].imm
>> 8)
14768 case 64: alignbits
= 1; break;
14770 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14771 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14772 goto bad_alignment
;
14776 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14777 goto bad_alignment
;
14782 first_error (_("bad alignment"));
14786 inst
.instruction
|= alignbits
<< 4;
14787 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14789 /* Bits [4:6] of the immediate in a list specifier encode register stride
14790 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14791 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14792 up the right value for "type" in a table based on this value and the given
14793 list style, then stick it back. */
14794 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14795 | (((inst
.instruction
>> 8) & 3) << 3);
14797 typebits
= typetable
[idx
];
14799 constraint (typebits
== -1, _("bad list type for instruction"));
14801 inst
.instruction
&= ~0xf00;
14802 inst
.instruction
|= typebits
<< 8;
14805 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14806 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14807 otherwise. The variable arguments are a list of pairs of legal (size, align)
14808 values, terminated with -1. */
14811 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14814 int result
= FAIL
, thissize
, thisalign
;
14816 if (!inst
.operands
[1].immisalign
)
14822 va_start (ap
, do_align
);
14826 thissize
= va_arg (ap
, int);
14827 if (thissize
== -1)
14829 thisalign
= va_arg (ap
, int);
14831 if (size
== thissize
&& align
== thisalign
)
14834 while (result
!= SUCCESS
);
14838 if (result
== SUCCESS
)
14841 first_error (_("unsupported alignment for instruction"));
14847 do_neon_ld_st_lane (void)
14849 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14850 int align_good
, do_align
= 0;
14851 int logsize
= neon_logbits (et
.size
);
14852 int align
= inst
.operands
[1].imm
>> 8;
14853 int n
= (inst
.instruction
>> 8) & 3;
14854 int max_el
= 64 / et
.size
;
14856 if (et
.type
== NT_invtype
)
14859 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14860 _("bad list length"));
14861 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14862 _("scalar index out of range"));
14863 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14865 _("stride of 2 unavailable when element size is 8"));
14869 case 0: /* VLD1 / VST1. */
14870 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14872 if (align_good
== FAIL
)
14876 unsigned alignbits
= 0;
14879 case 16: alignbits
= 0x1; break;
14880 case 32: alignbits
= 0x3; break;
14883 inst
.instruction
|= alignbits
<< 4;
14887 case 1: /* VLD2 / VST2. */
14888 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14890 if (align_good
== FAIL
)
14893 inst
.instruction
|= 1 << 4;
14896 case 2: /* VLD3 / VST3. */
14897 constraint (inst
.operands
[1].immisalign
,
14898 _("can't use alignment with this instruction"));
14901 case 3: /* VLD4 / VST4. */
14902 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14903 16, 64, 32, 64, 32, 128, -1);
14904 if (align_good
== FAIL
)
14908 unsigned alignbits
= 0;
14911 case 8: alignbits
= 0x1; break;
14912 case 16: alignbits
= 0x1; break;
14913 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14916 inst
.instruction
|= alignbits
<< 4;
14923 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14924 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14925 inst
.instruction
|= 1 << (4 + logsize
);
14927 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14928 inst
.instruction
|= logsize
<< 10;
14931 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14934 do_neon_ld_dup (void)
14936 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14937 int align_good
, do_align
= 0;
14939 if (et
.type
== NT_invtype
)
14942 switch ((inst
.instruction
>> 8) & 3)
14944 case 0: /* VLD1. */
14945 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14946 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14947 &do_align
, 16, 16, 32, 32, -1);
14948 if (align_good
== FAIL
)
14950 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14953 case 2: inst
.instruction
|= 1 << 5; break;
14954 default: first_error (_("bad list length")); return;
14956 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14959 case 1: /* VLD2. */
14960 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14961 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14962 if (align_good
== FAIL
)
14964 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14965 _("bad list length"));
14966 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14967 inst
.instruction
|= 1 << 5;
14968 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14971 case 2: /* VLD3. */
14972 constraint (inst
.operands
[1].immisalign
,
14973 _("can't use alignment with this instruction"));
14974 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14975 _("bad list length"));
14976 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14977 inst
.instruction
|= 1 << 5;
14978 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14981 case 3: /* VLD4. */
14983 int align
= inst
.operands
[1].imm
>> 8;
14984 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14985 16, 64, 32, 64, 32, 128, -1);
14986 if (align_good
== FAIL
)
14988 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14989 _("bad list length"));
14990 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14991 inst
.instruction
|= 1 << 5;
14992 if (et
.size
== 32 && align
== 128)
14993 inst
.instruction
|= 0x3 << 6;
14995 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15002 inst
.instruction
|= do_align
<< 4;
15005 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15006 apart from bits [11:4]. */
15009 do_neon_ldx_stx (void)
15011 if (inst
.operands
[1].isreg
)
15012 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15014 switch (NEON_LANE (inst
.operands
[0].imm
))
15016 case NEON_INTERLEAVE_LANES
:
15017 NEON_ENCODE (INTERLV
, inst
);
15018 do_neon_ld_st_interleave ();
15021 case NEON_ALL_LANES
:
15022 NEON_ENCODE (DUP
, inst
);
15027 NEON_ENCODE (LANE
, inst
);
15028 do_neon_ld_st_lane ();
15031 /* L bit comes from bit mask. */
15032 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15033 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15034 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15036 if (inst
.operands
[1].postind
)
15038 int postreg
= inst
.operands
[1].imm
& 0xf;
15039 constraint (!inst
.operands
[1].immisreg
,
15040 _("post-index must be a register"));
15041 constraint (postreg
== 0xd || postreg
== 0xf,
15042 _("bad register for post-index"));
15043 inst
.instruction
|= postreg
;
15045 else if (inst
.operands
[1].writeback
)
15047 inst
.instruction
|= 0xd;
15050 inst
.instruction
|= 0xf;
15053 inst
.instruction
|= 0xf9000000;
15055 inst
.instruction
|= 0xf4000000;
15058 /* Overall per-instruction processing. */
15060 /* We need to be able to fix up arbitrary expressions in some statements.
15061 This is so that we can handle symbols that are an arbitrary distance from
15062 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15063 which returns part of an address in a form which will be valid for
15064 a data instruction. We do this by pushing the expression into a symbol
15065 in the expr_section, and creating a fix for that. */
15068 fix_new_arm (fragS
* frag
,
15083 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15084 (enum bfd_reloc_code_real
) reloc
);
15088 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15089 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15093 /* Mark whether the fix is to a THUMB instruction, or an ARM
15095 new_fix
->tc_fix_data
= thumb_mode
;
15098 /* Create a frg for an instruction requiring relaxation. */
15100 output_relax_insn (void)
15106 /* The size of the instruction is unknown, so tie the debug info to the
15107 start of the instruction. */
15108 dwarf2_emit_insn (0);
15110 switch (inst
.reloc
.exp
.X_op
)
15113 sym
= inst
.reloc
.exp
.X_add_symbol
;
15114 offset
= inst
.reloc
.exp
.X_add_number
;
15118 offset
= inst
.reloc
.exp
.X_add_number
;
15121 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15125 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15126 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15127 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15130 /* Write a 32-bit thumb instruction to buf. */
15132 put_thumb32_insn (char * buf
, unsigned long insn
)
15134 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15135 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15139 output_inst (const char * str
)
15145 as_bad ("%s -- `%s'", inst
.error
, str
);
15150 output_relax_insn ();
15153 if (inst
.size
== 0)
15156 to
= frag_more (inst
.size
);
15157 /* PR 9814: Record the thumb mode into the current frag so that we know
15158 what type of NOP padding to use, if necessary. We override any previous
15159 setting so that if the mode has changed then the NOPS that we use will
15160 match the encoding of the last instruction in the frag. */
15161 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15163 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15165 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15166 put_thumb32_insn (to
, inst
.instruction
);
15168 else if (inst
.size
> INSN_SIZE
)
15170 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15171 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15172 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15175 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15177 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15178 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15179 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15182 dwarf2_emit_insn (inst
.size
);
15186 output_it_inst (int cond
, int mask
, char * to
)
15188 unsigned long instruction
= 0xbf00;
15191 instruction
|= mask
;
15192 instruction
|= cond
<< 4;
15196 to
= frag_more (2);
15198 dwarf2_emit_insn (2);
15202 md_number_to_chars (to
, instruction
, 2);
15207 /* Tag values used in struct asm_opcode's tag field. */
15210 OT_unconditional
, /* Instruction cannot be conditionalized.
15211 The ARM condition field is still 0xE. */
15212 OT_unconditionalF
, /* Instruction cannot be conditionalized
15213 and carries 0xF in its ARM condition field. */
15214 OT_csuffix
, /* Instruction takes a conditional suffix. */
15215 OT_csuffixF
, /* Some forms of the instruction take a conditional
15216 suffix, others place 0xF where the condition field
15218 OT_cinfix3
, /* Instruction takes a conditional infix,
15219 beginning at character index 3. (In
15220 unified mode, it becomes a suffix.) */
15221 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15222 tsts, cmps, cmns, and teqs. */
15223 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15224 character index 3, even in unified mode. Used for
15225 legacy instructions where suffix and infix forms
15226 may be ambiguous. */
15227 OT_csuf_or_in3
, /* Instruction takes either a conditional
15228 suffix or an infix at character index 3. */
15229 OT_odd_infix_unc
, /* This is the unconditional variant of an
15230 instruction that takes a conditional infix
15231 at an unusual position. In unified mode,
15232 this variant will accept a suffix. */
15233 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15234 are the conditional variants of instructions that
15235 take conditional infixes in unusual positions.
15236 The infix appears at character index
15237 (tag - OT_odd_infix_0). These are not accepted
15238 in unified mode. */
15241 /* Subroutine of md_assemble, responsible for looking up the primary
15242 opcode from the mnemonic the user wrote. STR points to the
15243 beginning of the mnemonic.
15245 This is not simply a hash table lookup, because of conditional
15246 variants. Most instructions have conditional variants, which are
15247 expressed with a _conditional affix_ to the mnemonic. If we were
15248 to encode each conditional variant as a literal string in the opcode
15249 table, it would have approximately 20,000 entries.
15251 Most mnemonics take this affix as a suffix, and in unified syntax,
15252 'most' is upgraded to 'all'. However, in the divided syntax, some
15253 instructions take the affix as an infix, notably the s-variants of
15254 the arithmetic instructions. Of those instructions, all but six
15255 have the infix appear after the third character of the mnemonic.
15257 Accordingly, the algorithm for looking up primary opcodes given
15260 1. Look up the identifier in the opcode table.
15261 If we find a match, go to step U.
15263 2. Look up the last two characters of the identifier in the
15264 conditions table. If we find a match, look up the first N-2
15265 characters of the identifier in the opcode table. If we
15266 find a match, go to step CE.
15268 3. Look up the fourth and fifth characters of the identifier in
15269 the conditions table. If we find a match, extract those
15270 characters from the identifier, and look up the remaining
15271 characters in the opcode table. If we find a match, go
15276 U. Examine the tag field of the opcode structure, in case this is
15277 one of the six instructions with its conditional infix in an
15278 unusual place. If it is, the tag tells us where to find the
15279 infix; look it up in the conditions table and set inst.cond
15280 accordingly. Otherwise, this is an unconditional instruction.
15281 Again set inst.cond accordingly. Return the opcode structure.
15283 CE. Examine the tag field to make sure this is an instruction that
15284 should receive a conditional suffix. If it is not, fail.
15285 Otherwise, set inst.cond from the suffix we already looked up,
15286 and return the opcode structure.
15288 CM. Examine the tag field to make sure this is an instruction that
15289 should receive a conditional infix after the third character.
15290 If it is not, fail. Otherwise, undo the edits to the current
15291 line of input and proceed as for case CE. */
15293 static const struct asm_opcode
*
15294 opcode_lookup (char **str
)
15298 const struct asm_opcode
*opcode
;
15299 const struct asm_cond
*cond
;
15302 /* Scan up to the end of the mnemonic, which must end in white space,
15303 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15304 for (base
= end
= *str
; *end
!= '\0'; end
++)
15305 if (*end
== ' ' || *end
== '.')
15311 /* Handle a possible width suffix and/or Neon type suffix. */
15316 /* The .w and .n suffixes are only valid if the unified syntax is in
15318 if (unified_syntax
&& end
[1] == 'w')
15320 else if (unified_syntax
&& end
[1] == 'n')
15325 inst
.vectype
.elems
= 0;
15327 *str
= end
+ offset
;
15329 if (end
[offset
] == '.')
15331 /* See if we have a Neon type suffix (possible in either unified or
15332 non-unified ARM syntax mode). */
15333 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15336 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15342 /* Look for unaffixed or special-case affixed mnemonic. */
15343 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15348 if (opcode
->tag
< OT_odd_infix_0
)
15350 inst
.cond
= COND_ALWAYS
;
15354 if (warn_on_deprecated
&& unified_syntax
)
15355 as_warn (_("conditional infixes are deprecated in unified syntax"));
15356 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15357 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15360 inst
.cond
= cond
->value
;
15364 /* Cannot have a conditional suffix on a mnemonic of less than two
15366 if (end
- base
< 3)
15369 /* Look for suffixed mnemonic. */
15371 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15372 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15374 if (opcode
&& cond
)
15377 switch (opcode
->tag
)
15379 case OT_cinfix3_legacy
:
15380 /* Ignore conditional suffixes matched on infix only mnemonics. */
15384 case OT_cinfix3_deprecated
:
15385 case OT_odd_infix_unc
:
15386 if (!unified_syntax
)
15388 /* else fall through */
15392 case OT_csuf_or_in3
:
15393 inst
.cond
= cond
->value
;
15396 case OT_unconditional
:
15397 case OT_unconditionalF
:
15399 inst
.cond
= cond
->value
;
15402 /* Delayed diagnostic. */
15403 inst
.error
= BAD_COND
;
15404 inst
.cond
= COND_ALWAYS
;
15413 /* Cannot have a usual-position infix on a mnemonic of less than
15414 six characters (five would be a suffix). */
15415 if (end
- base
< 6)
15418 /* Look for infixed mnemonic in the usual position. */
15420 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15424 memcpy (save
, affix
, 2);
15425 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15426 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15428 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15429 memcpy (affix
, save
, 2);
15432 && (opcode
->tag
== OT_cinfix3
15433 || opcode
->tag
== OT_cinfix3_deprecated
15434 || opcode
->tag
== OT_csuf_or_in3
15435 || opcode
->tag
== OT_cinfix3_legacy
))
15438 if (warn_on_deprecated
&& unified_syntax
15439 && (opcode
->tag
== OT_cinfix3
15440 || opcode
->tag
== OT_cinfix3_deprecated
))
15441 as_warn (_("conditional infixes are deprecated in unified syntax"));
15443 inst
.cond
= cond
->value
;
15450 /* This function generates an initial IT instruction, leaving its block
15451 virtually open for the new instructions. Eventually,
15452 the mask will be updated by now_it_add_mask () each time
15453 a new instruction needs to be included in the IT block.
15454 Finally, the block is closed with close_automatic_it_block ().
15455 The block closure can be requested either from md_assemble (),
15456 a tencode (), or due to a label hook. */
15459 new_automatic_it_block (int cond
)
15461 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15462 now_it
.mask
= 0x18;
15464 now_it
.block_length
= 1;
15465 mapping_state (MAP_THUMB
);
15466 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15469 /* Close an automatic IT block.
15470 See comments in new_automatic_it_block (). */
15473 close_automatic_it_block (void)
15475 now_it
.mask
= 0x10;
15476 now_it
.block_length
= 0;
15479 /* Update the mask of the current automatically-generated IT
15480 instruction. See comments in new_automatic_it_block (). */
15483 now_it_add_mask (int cond
)
15485 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15486 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15487 | ((bitvalue) << (nbit)))
15488 const int resulting_bit
= (cond
& 1);
15490 now_it
.mask
&= 0xf;
15491 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15493 (5 - now_it
.block_length
));
15494 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15496 ((5 - now_it
.block_length
) - 1) );
15497 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15500 #undef SET_BIT_VALUE
15503 /* The IT blocks handling machinery is accessed through the these functions:
15504 it_fsm_pre_encode () from md_assemble ()
15505 set_it_insn_type () optional, from the tencode functions
15506 set_it_insn_type_last () ditto
15507 in_it_block () ditto
15508 it_fsm_post_encode () from md_assemble ()
15509 force_automatic_it_block_close () from label habdling functions
15512 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15513 initializing the IT insn type with a generic initial value depending
15514 on the inst.condition.
15515 2) During the tencode function, two things may happen:
15516 a) The tencode function overrides the IT insn type by
15517 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15518 b) The tencode function queries the IT block state by
15519 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15521 Both set_it_insn_type and in_it_block run the internal FSM state
15522 handling function (handle_it_state), because: a) setting the IT insn
15523 type may incur in an invalid state (exiting the function),
15524 and b) querying the state requires the FSM to be updated.
15525 Specifically we want to avoid creating an IT block for conditional
15526 branches, so it_fsm_pre_encode is actually a guess and we can't
15527 determine whether an IT block is required until the tencode () routine
15528 has decided what type of instruction this actually it.
15529 Because of this, if set_it_insn_type and in_it_block have to be used,
15530 set_it_insn_type has to be called first.
15532 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15533 determines the insn IT type depending on the inst.cond code.
15534 When a tencode () routine encodes an instruction that can be
15535 either outside an IT block, or, in the case of being inside, has to be
15536 the last one, set_it_insn_type_last () will determine the proper
15537 IT instruction type based on the inst.cond code. Otherwise,
15538 set_it_insn_type can be called for overriding that logic or
15539 for covering other cases.
15541 Calling handle_it_state () may not transition the IT block state to
15542 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15543 still queried. Instead, if the FSM determines that the state should
15544 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15545 after the tencode () function: that's what it_fsm_post_encode () does.
15547 Since in_it_block () calls the state handling function to get an
15548 updated state, an error may occur (due to invalid insns combination).
15549 In that case, inst.error is set.
15550 Therefore, inst.error has to be checked after the execution of
15551 the tencode () routine.
15553 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15554 any pending state change (if any) that didn't take place in
15555 handle_it_state () as explained above. */
15558 it_fsm_pre_encode (void)
15560 if (inst
.cond
!= COND_ALWAYS
)
15561 inst
.it_insn_type
= INSIDE_IT_INSN
;
15563 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15565 now_it
.state_handled
= 0;
15568 /* IT state FSM handling function. */
15571 handle_it_state (void)
15573 now_it
.state_handled
= 1;
15575 switch (now_it
.state
)
15577 case OUTSIDE_IT_BLOCK
:
15578 switch (inst
.it_insn_type
)
15580 case OUTSIDE_IT_INSN
:
15583 case INSIDE_IT_INSN
:
15584 case INSIDE_IT_LAST_INSN
:
15585 if (thumb_mode
== 0)
15588 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15589 as_tsktsk (_("Warning: conditional outside an IT block"\
15594 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15595 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15597 /* Automatically generate the IT instruction. */
15598 new_automatic_it_block (inst
.cond
);
15599 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15600 close_automatic_it_block ();
15604 inst
.error
= BAD_OUT_IT
;
15610 case IF_INSIDE_IT_LAST_INSN
:
15611 case NEUTRAL_IT_INSN
:
15615 now_it
.state
= MANUAL_IT_BLOCK
;
15616 now_it
.block_length
= 0;
15621 case AUTOMATIC_IT_BLOCK
:
15622 /* Three things may happen now:
15623 a) We should increment current it block size;
15624 b) We should close current it block (closing insn or 4 insns);
15625 c) We should close current it block and start a new one (due
15626 to incompatible conditions or
15627 4 insns-length block reached). */
15629 switch (inst
.it_insn_type
)
15631 case OUTSIDE_IT_INSN
:
15632 /* The closure of the block shall happen immediatelly,
15633 so any in_it_block () call reports the block as closed. */
15634 force_automatic_it_block_close ();
15637 case INSIDE_IT_INSN
:
15638 case INSIDE_IT_LAST_INSN
:
15639 case IF_INSIDE_IT_LAST_INSN
:
15640 now_it
.block_length
++;
15642 if (now_it
.block_length
> 4
15643 || !now_it_compatible (inst
.cond
))
15645 force_automatic_it_block_close ();
15646 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15647 new_automatic_it_block (inst
.cond
);
15651 now_it_add_mask (inst
.cond
);
15654 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15655 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15656 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15657 close_automatic_it_block ();
15660 case NEUTRAL_IT_INSN
:
15661 now_it
.block_length
++;
15663 if (now_it
.block_length
> 4)
15664 force_automatic_it_block_close ();
15666 now_it_add_mask (now_it
.cc
& 1);
15670 close_automatic_it_block ();
15671 now_it
.state
= MANUAL_IT_BLOCK
;
15676 case MANUAL_IT_BLOCK
:
15678 /* Check conditional suffixes. */
15679 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15682 now_it
.mask
&= 0x1f;
15683 is_last
= (now_it
.mask
== 0x10);
15685 switch (inst
.it_insn_type
)
15687 case OUTSIDE_IT_INSN
:
15688 inst
.error
= BAD_NOT_IT
;
15691 case INSIDE_IT_INSN
:
15692 if (cond
!= inst
.cond
)
15694 inst
.error
= BAD_IT_COND
;
15699 case INSIDE_IT_LAST_INSN
:
15700 case IF_INSIDE_IT_LAST_INSN
:
15701 if (cond
!= inst
.cond
)
15703 inst
.error
= BAD_IT_COND
;
15708 inst
.error
= BAD_BRANCH
;
15713 case NEUTRAL_IT_INSN
:
15714 /* The BKPT instruction is unconditional even in an IT block. */
15718 inst
.error
= BAD_IT_IT
;
15729 it_fsm_post_encode (void)
15733 if (!now_it
.state_handled
)
15734 handle_it_state ();
15736 is_last
= (now_it
.mask
== 0x10);
15739 now_it
.state
= OUTSIDE_IT_BLOCK
;
15745 force_automatic_it_block_close (void)
15747 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15749 close_automatic_it_block ();
15750 now_it
.state
= OUTSIDE_IT_BLOCK
;
15758 if (!now_it
.state_handled
)
15759 handle_it_state ();
15761 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15765 md_assemble (char *str
)
15768 const struct asm_opcode
* opcode
;
15770 /* Align the previous label if needed. */
15771 if (last_label_seen
!= NULL
)
15773 symbol_set_frag (last_label_seen
, frag_now
);
15774 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15775 S_SET_SEGMENT (last_label_seen
, now_seg
);
15778 memset (&inst
, '\0', sizeof (inst
));
15779 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15781 opcode
= opcode_lookup (&p
);
15784 /* It wasn't an instruction, but it might be a register alias of
15785 the form alias .req reg, or a Neon .dn/.qn directive. */
15786 if (! create_register_alias (str
, p
)
15787 && ! create_neon_reg_alias (str
, p
))
15788 as_bad (_("bad instruction `%s'"), str
);
15793 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15794 as_warn (_("s suffix on comparison instruction is deprecated"));
15796 /* The value which unconditional instructions should have in place of the
15797 condition field. */
15798 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15802 arm_feature_set variant
;
15804 variant
= cpu_variant
;
15805 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15806 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15807 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15808 /* Check that this instruction is supported for this CPU. */
15809 if (!opcode
->tvariant
15810 || (thumb_mode
== 1
15811 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15813 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15816 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15817 && opcode
->tencode
!= do_t_branch
)
15819 as_bad (_("Thumb does not support conditional execution"));
15823 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15825 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15826 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15827 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15829 /* Two things are addressed here.
15830 1) Implicit require narrow instructions on Thumb-1.
15831 This avoids relaxation accidentally introducing Thumb-2
15833 2) Reject wide instructions in non Thumb-2 cores. */
15834 if (inst
.size_req
== 0)
15836 else if (inst
.size_req
== 4)
15838 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
15844 inst
.instruction
= opcode
->tvalue
;
15846 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15848 /* Prepare the it_insn_type for those encodings that don't set
15850 it_fsm_pre_encode ();
15852 opcode
->tencode ();
15854 it_fsm_post_encode ();
15857 if (!(inst
.error
|| inst
.relax
))
15859 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15860 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15861 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15863 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15868 /* Something has gone badly wrong if we try to relax a fixed size
15870 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15872 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15873 *opcode
->tvariant
);
15874 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15875 set those bits when Thumb-2 32-bit instructions are seen. ie.
15876 anything other than bl/blx and v6-M instructions.
15877 This is overly pessimistic for relaxable instructions. */
15878 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15880 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15881 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15882 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15885 check_neon_suffixes
;
15889 mapping_state (MAP_THUMB
);
15892 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15896 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15897 is_bx
= (opcode
->aencode
== do_bx
);
15899 /* Check that this instruction is supported for this CPU. */
15900 if (!(is_bx
&& fix_v4bx
)
15901 && !(opcode
->avariant
&&
15902 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15904 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
15909 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15913 inst
.instruction
= opcode
->avalue
;
15914 if (opcode
->tag
== OT_unconditionalF
)
15915 inst
.instruction
|= 0xF << 28;
15917 inst
.instruction
|= inst
.cond
<< 28;
15918 inst
.size
= INSN_SIZE
;
15919 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
15921 it_fsm_pre_encode ();
15922 opcode
->aencode ();
15923 it_fsm_post_encode ();
15925 /* Arm mode bx is marked as both v4T and v5 because it's still required
15926 on a hypothetical non-thumb v5 core. */
15928 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15930 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15931 *opcode
->avariant
);
15933 check_neon_suffixes
;
15937 mapping_state (MAP_ARM
);
15942 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15950 check_it_blocks_finished (void)
15955 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15956 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15957 == MANUAL_IT_BLOCK
)
15959 as_warn (_("section '%s' finished with an open IT block."),
15963 if (now_it
.state
== MANUAL_IT_BLOCK
)
15964 as_warn (_("file finished with an open IT block."));
15968 /* Various frobbings of labels and their addresses. */
15971 arm_start_line_hook (void)
15973 last_label_seen
= NULL
;
15977 arm_frob_label (symbolS
* sym
)
15979 last_label_seen
= sym
;
15981 ARM_SET_THUMB (sym
, thumb_mode
);
15983 #if defined OBJ_COFF || defined OBJ_ELF
15984 ARM_SET_INTERWORK (sym
, support_interwork
);
15987 force_automatic_it_block_close ();
15989 /* Note - do not allow local symbols (.Lxxx) to be labelled
15990 as Thumb functions. This is because these labels, whilst
15991 they exist inside Thumb code, are not the entry points for
15992 possible ARM->Thumb calls. Also, these labels can be used
15993 as part of a computed goto or switch statement. eg gcc
15994 can generate code that looks like this:
15996 ldr r2, [pc, .Laaa]
16006 The first instruction loads the address of the jump table.
16007 The second instruction converts a table index into a byte offset.
16008 The third instruction gets the jump address out of the table.
16009 The fourth instruction performs the jump.
16011 If the address stored at .Laaa is that of a symbol which has the
16012 Thumb_Func bit set, then the linker will arrange for this address
16013 to have the bottom bit set, which in turn would mean that the
16014 address computation performed by the third instruction would end
16015 up with the bottom bit set. Since the ARM is capable of unaligned
16016 word loads, the instruction would then load the incorrect address
16017 out of the jump table, and chaos would ensue. */
16018 if (label_is_thumb_function_name
16019 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16020 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16022 /* When the address of a Thumb function is taken the bottom
16023 bit of that address should be set. This will allow
16024 interworking between Arm and Thumb functions to work
16027 THUMB_SET_FUNC (sym
, 1);
16029 label_is_thumb_function_name
= FALSE
;
16032 dwarf2_emit_label (sym
);
16036 arm_data_in_code (void)
16038 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16040 *input_line_pointer
= '/';
16041 input_line_pointer
+= 5;
16042 *input_line_pointer
= 0;
16050 arm_canonicalize_symbol_name (char * name
)
16054 if (thumb_mode
&& (len
= strlen (name
)) > 5
16055 && streq (name
+ len
- 5, "/data"))
16056 *(name
+ len
- 5) = 0;
16061 /* Table of all register names defined by default. The user can
16062 define additional names with .req. Note that all register names
16063 should appear in both upper and lowercase variants. Some registers
16064 also have mixed-case names. */
16066 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16067 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16068 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16069 #define REGSET(p,t) \
16070 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16071 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16072 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16073 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16074 #define REGSETH(p,t) \
16075 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16076 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16077 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16078 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16079 #define REGSET2(p,t) \
16080 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16081 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16082 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16083 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16085 static const struct reg_entry reg_names
[] =
16087 /* ARM integer registers. */
16088 REGSET(r
, RN
), REGSET(R
, RN
),
16090 /* ATPCS synonyms. */
16091 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16092 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16093 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16095 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16096 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16097 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16099 /* Well-known aliases. */
16100 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16101 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16103 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16104 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16106 /* Coprocessor numbers. */
16107 REGSET(p
, CP
), REGSET(P
, CP
),
16109 /* Coprocessor register numbers. The "cr" variants are for backward
16111 REGSET(c
, CN
), REGSET(C
, CN
),
16112 REGSET(cr
, CN
), REGSET(CR
, CN
),
16114 /* FPA registers. */
16115 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16116 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16118 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16119 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16121 /* VFP SP registers. */
16122 REGSET(s
,VFS
), REGSET(S
,VFS
),
16123 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16125 /* VFP DP Registers. */
16126 REGSET(d
,VFD
), REGSET(D
,VFD
),
16127 /* Extra Neon DP registers. */
16128 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16130 /* Neon QP registers. */
16131 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16133 /* VFP control registers. */
16134 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16135 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16136 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16137 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16138 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16139 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16141 /* Maverick DSP coprocessor registers. */
16142 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16143 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16145 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16146 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16147 REGDEF(dspsc
,0,DSPSC
),
16149 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16150 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16151 REGDEF(DSPSC
,0,DSPSC
),
16153 /* iWMMXt data registers - p0, c0-15. */
16154 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16156 /* iWMMXt control registers - p1, c0-3. */
16157 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16158 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16159 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16160 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16162 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16163 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16164 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16165 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16166 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16168 /* XScale accumulator registers. */
16169 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16175 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16176 within psr_required_here. */
16177 static const struct asm_psr psrs
[] =
16179 /* Backward compatibility notation. Note that "all" is no longer
16180 truly all possible PSR bits. */
16181 {"all", PSR_c
| PSR_f
},
16185 /* Individual flags. */
16190 /* Combinations of flags. */
16191 {"fs", PSR_f
| PSR_s
},
16192 {"fx", PSR_f
| PSR_x
},
16193 {"fc", PSR_f
| PSR_c
},
16194 {"sf", PSR_s
| PSR_f
},
16195 {"sx", PSR_s
| PSR_x
},
16196 {"sc", PSR_s
| PSR_c
},
16197 {"xf", PSR_x
| PSR_f
},
16198 {"xs", PSR_x
| PSR_s
},
16199 {"xc", PSR_x
| PSR_c
},
16200 {"cf", PSR_c
| PSR_f
},
16201 {"cs", PSR_c
| PSR_s
},
16202 {"cx", PSR_c
| PSR_x
},
16203 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16204 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16205 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16206 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16207 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16208 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16209 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16210 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16211 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16212 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16213 {"scf", PSR_s
| PSR_c
| PSR_f
},
16214 {"scx", PSR_s
| PSR_c
| PSR_x
},
16215 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16216 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16217 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16218 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16219 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16220 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16221 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16222 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16223 {"csf", PSR_c
| PSR_s
| PSR_f
},
16224 {"csx", PSR_c
| PSR_s
| PSR_x
},
16225 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16226 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16227 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16228 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16229 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16230 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16231 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16232 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16233 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16234 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16235 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16236 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16237 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16238 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16239 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16240 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16241 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16242 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16243 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16244 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16245 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16246 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16247 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16248 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16249 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16250 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16253 /* Table of V7M psr names. */
16254 static const struct asm_psr v7m_psrs
[] =
16256 {"apsr", 0 }, {"APSR", 0 },
16257 {"iapsr", 1 }, {"IAPSR", 1 },
16258 {"eapsr", 2 }, {"EAPSR", 2 },
16259 {"psr", 3 }, {"PSR", 3 },
16260 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16261 {"ipsr", 5 }, {"IPSR", 5 },
16262 {"epsr", 6 }, {"EPSR", 6 },
16263 {"iepsr", 7 }, {"IEPSR", 7 },
16264 {"msp", 8 }, {"MSP", 8 },
16265 {"psp", 9 }, {"PSP", 9 },
16266 {"primask", 16}, {"PRIMASK", 16},
16267 {"basepri", 17}, {"BASEPRI", 17},
16268 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16269 {"faultmask", 19}, {"FAULTMASK", 19},
16270 {"control", 20}, {"CONTROL", 20}
16273 /* Table of all shift-in-operand names. */
16274 static const struct asm_shift_name shift_names
[] =
16276 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16277 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16278 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16279 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16280 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16281 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16284 /* Table of all explicit relocation names. */
16286 static struct reloc_entry reloc_names
[] =
16288 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16289 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16290 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16291 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16292 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16293 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16294 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16295 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16296 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16297 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16298 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16299 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16303 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16304 static const struct asm_cond conds
[] =
16308 {"cs", 0x2}, {"hs", 0x2},
16309 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16323 static struct asm_barrier_opt barrier_opt_names
[] =
16325 { "sy", 0xf }, { "SY", 0xf },
16326 { "un", 0x7 }, { "UN", 0x7 },
16327 { "st", 0xe }, { "ST", 0xe },
16328 { "unst", 0x6 }, { "UNST", 0x6 },
16329 { "ish", 0xb }, { "ISH", 0xb },
16330 { "sh", 0xb }, { "SH", 0xb },
16331 { "ishst", 0xa }, { "ISHST", 0xa },
16332 { "shst", 0xa }, { "SHST", 0xa },
16333 { "nsh", 0x7 }, { "NSH", 0x7 },
16334 { "nshst", 0x6 }, { "NSHST", 0x6 },
16335 { "osh", 0x3 }, { "OSH", 0x3 },
16336 { "oshst", 0x2 }, { "OSHST", 0x2 }
16339 /* Table of ARM-format instructions. */
16341 /* Macros for gluing together operand strings. N.B. In all cases
16342 other than OPS0, the trailing OP_stop comes from default
16343 zero-initialization of the unspecified elements of the array. */
16344 #define OPS0() { OP_stop, }
16345 #define OPS1(a) { OP_##a, }
16346 #define OPS2(a,b) { OP_##a,OP_##b, }
16347 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16348 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16349 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16350 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16352 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16353 This is useful when mixing operands for ARM and THUMB, i.e. using the
16354 MIX_ARM_THUMB_OPERANDS macro.
16355 In order to use these macros, prefix the number of operands with _
16357 #define OPS_1(a) { a, }
16358 #define OPS_2(a,b) { a,b, }
16359 #define OPS_3(a,b,c) { a,b,c, }
16360 #define OPS_4(a,b,c,d) { a,b,c,d, }
16361 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16362 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16364 /* These macros abstract out the exact format of the mnemonic table and
16365 save some repeated characters. */
16367 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16368 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16369 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16370 THUMB_VARIANT, do_##ae, do_##te }
16372 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16373 a T_MNEM_xyz enumerator. */
16374 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16375 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16376 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16377 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16379 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16380 infix after the third character. */
16381 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16382 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16383 THUMB_VARIANT, do_##ae, do_##te }
16384 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16385 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16386 THUMB_VARIANT, do_##ae, do_##te }
16387 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16388 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16389 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16390 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16391 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16392 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16393 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16394 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16396 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16397 appear in the condition table. */
16398 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16399 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16400 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16402 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16403 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16404 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16405 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16406 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16407 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16408 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16409 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16410 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16411 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16412 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16413 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16414 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16415 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16416 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16417 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16418 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16419 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16420 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16421 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16423 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16424 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16425 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16426 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16428 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16429 field is still 0xE. Many of the Thumb variants can be executed
16430 conditionally, so this is checked separately. */
16431 #define TUE(mnem, op, top, nops, ops, ae, te) \
16432 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16433 THUMB_VARIANT, do_##ae, do_##te }
16435 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16436 condition code field. */
16437 #define TUF(mnem, op, top, nops, ops, ae, te) \
16438 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16439 THUMB_VARIANT, do_##ae, do_##te }
16441 /* ARM-only variants of all the above. */
16442 #define CE(mnem, op, nops, ops, ae) \
16443 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16445 #define C3(mnem, op, nops, ops, ae) \
16446 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16448 /* Legacy mnemonics that always have conditional infix after the third
16450 #define CL(mnem, op, nops, ops, ae) \
16451 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16452 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16454 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16455 #define cCE(mnem, op, nops, ops, ae) \
16456 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16458 /* Legacy coprocessor instructions where conditional infix and conditional
16459 suffix are ambiguous. For consistency this includes all FPA instructions,
16460 not just the potentially ambiguous ones. */
16461 #define cCL(mnem, op, nops, ops, ae) \
16462 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16463 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16465 /* Coprocessor, takes either a suffix or a position-3 infix
16466 (for an FPA corner case). */
16467 #define C3E(mnem, op, nops, ops, ae) \
16468 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16469 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16471 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16472 { m1 #m2 m3, OPS##nops ops, \
16473 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16474 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16476 #define CM(m1, m2, op, nops, ops, ae) \
16477 xCM_ (m1, , m2, op, nops, ops, ae), \
16478 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16479 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16480 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16481 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16482 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16483 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16484 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16485 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16486 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16487 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16488 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16489 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16490 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16491 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16492 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16493 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16494 xCM_ (m1, le, m2, op, nops, ops, ae), \
16495 xCM_ (m1, al, m2, op, nops, ops, ae)
16497 #define UE(mnem, op, nops, ops, ae) \
16498 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16500 #define UF(mnem, op, nops, ops, ae) \
16501 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16503 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16504 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16505 use the same encoding function for each. */
16506 #define NUF(mnem, op, nops, ops, enc) \
16507 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16508 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16510 /* Neon data processing, version which indirects through neon_enc_tab for
16511 the various overloaded versions of opcodes. */
16512 #define nUF(mnem, op, nops, ops, enc) \
16513 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16514 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16516 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16518 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16519 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16520 THUMB_VARIANT, do_##enc, do_##enc }
16522 #define NCE(mnem, op, nops, ops, enc) \
16523 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16525 #define NCEF(mnem, op, nops, ops, enc) \
16526 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16528 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16529 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16530 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16531 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16533 #define nCE(mnem, op, nops, ops, enc) \
16534 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16536 #define nCEF(mnem, op, nops, ops, enc) \
16537 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16541 static const struct asm_opcode insns
[] =
16543 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16544 #define THUMB_VARIANT &arm_ext_v4t
16545 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16546 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16547 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16548 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16549 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16550 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16551 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16552 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16553 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16554 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16555 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16556 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16557 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16558 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16559 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16560 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16562 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16563 for setting PSR flag bits. They are obsolete in V6 and do not
16564 have Thumb equivalents. */
16565 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16566 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16567 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16568 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16569 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16570 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16571 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16572 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16573 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16575 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16576 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16577 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16578 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16580 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16581 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16582 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16584 OP_ADDRGLDR
),ldst
, t_ldst
),
16585 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16587 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16588 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16589 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16590 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16591 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16592 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16594 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16595 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16596 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16597 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16600 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16601 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16602 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16604 /* Thumb-compatibility pseudo ops. */
16605 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16606 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16607 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16608 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16609 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16610 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16611 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16612 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16613 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16614 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16615 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16616 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16618 /* These may simplify to neg. */
16619 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16620 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16622 #undef THUMB_VARIANT
16623 #define THUMB_VARIANT & arm_ext_v6
16625 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16627 /* V1 instructions with no Thumb analogue prior to V6T2. */
16628 #undef THUMB_VARIANT
16629 #define THUMB_VARIANT & arm_ext_v6t2
16631 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16632 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16633 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16635 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16636 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16637 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16638 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16640 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16641 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16643 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16644 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16646 /* V1 instructions with no Thumb analogue at all. */
16647 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16648 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16650 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16651 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16652 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16653 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16654 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16655 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16656 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16657 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16660 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16661 #undef THUMB_VARIANT
16662 #define THUMB_VARIANT & arm_ext_v4t
16664 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16665 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16667 #undef THUMB_VARIANT
16668 #define THUMB_VARIANT & arm_ext_v6t2
16670 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16671 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16673 /* Generic coprocessor instructions. */
16674 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16675 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16676 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16677 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16678 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16679 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16680 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16683 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16685 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16686 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16689 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16690 #undef THUMB_VARIANT
16691 #define THUMB_VARIANT & arm_ext_msr
16693 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16694 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16697 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16698 #undef THUMB_VARIANT
16699 #define THUMB_VARIANT & arm_ext_v6t2
16701 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16702 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16703 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16704 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16705 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16706 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16707 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16708 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16711 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16712 #undef THUMB_VARIANT
16713 #define THUMB_VARIANT & arm_ext_v4t
16715 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16716 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16717 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16718 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16719 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16720 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16723 #define ARM_VARIANT & arm_ext_v4t_5
16725 /* ARM Architecture 4T. */
16726 /* Note: bx (and blx) are required on V5, even if the processor does
16727 not support Thumb. */
16728 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16731 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16732 #undef THUMB_VARIANT
16733 #define THUMB_VARIANT & arm_ext_v5t
16735 /* Note: blx has 2 variants; the .value coded here is for
16736 BLX(2). Only this variant has conditional execution. */
16737 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16738 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16740 #undef THUMB_VARIANT
16741 #define THUMB_VARIANT & arm_ext_v6t2
16743 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16744 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16745 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16746 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16747 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16748 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16749 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16750 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16753 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16754 #undef THUMB_VARIANT
16755 #define THUMB_VARIANT &arm_ext_v5exp
16757 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16758 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16759 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16760 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16762 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16763 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16765 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16766 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16767 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16768 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16770 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16771 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16772 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16773 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16775 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16776 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16778 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16779 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16780 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16781 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16784 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16785 #undef THUMB_VARIANT
16786 #define THUMB_VARIANT &arm_ext_v6t2
16788 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16789 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16791 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16792 ADDRGLDRS
), ldrd
, t_ldstd
),
16794 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16795 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16798 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16800 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16803 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16804 #undef THUMB_VARIANT
16805 #define THUMB_VARIANT & arm_ext_v6
16807 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16808 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16809 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16810 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16811 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16812 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16813 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16814 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16815 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16816 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16818 #undef THUMB_VARIANT
16819 #define THUMB_VARIANT & arm_ext_v6t2
16821 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16822 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16824 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16825 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16827 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16828 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16830 /* ARM V6 not included in V7M. */
16831 #undef THUMB_VARIANT
16832 #define THUMB_VARIANT & arm_ext_v6_notm
16833 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16834 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16835 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16836 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16837 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16838 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16839 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16840 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16841 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16842 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16843 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16844 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16846 /* ARM V6 not included in V7M (eg. integer SIMD). */
16847 #undef THUMB_VARIANT
16848 #define THUMB_VARIANT & arm_ext_v6_dsp
16849 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16850 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16851 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16852 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16853 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16854 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16855 /* Old name for QASX. */
16856 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16857 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16858 /* Old name for QSAX. */
16859 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16860 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16861 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16862 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16863 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16864 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16865 /* Old name for SASX. */
16866 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16867 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16868 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16869 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16870 /* Old name for SHASX. */
16871 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16872 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16873 /* Old name for SHSAX. */
16874 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16875 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16876 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16877 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16878 /* Old name for SSAX. */
16879 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16880 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16881 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16882 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16883 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16884 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16885 /* Old name for UASX. */
16886 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16887 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16888 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16889 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16890 /* Old name for UHASX. */
16891 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16892 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16893 /* Old name for UHSAX. */
16894 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16895 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16896 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16897 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16898 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16899 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16900 /* Old name for UQASX. */
16901 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16902 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16903 /* Old name for UQSAX. */
16904 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16905 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16906 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16907 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16908 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16909 /* Old name for USAX. */
16910 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16911 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16912 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16913 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16914 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16915 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16916 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16917 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16918 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16919 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16920 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16921 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16922 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16923 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16924 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16925 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16926 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16927 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16928 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16929 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16930 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16931 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16932 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16933 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16934 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16935 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16936 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16937 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16938 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16939 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16940 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16941 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16942 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16943 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16946 #define ARM_VARIANT & arm_ext_v6k
16947 #undef THUMB_VARIANT
16948 #define THUMB_VARIANT & arm_ext_v6k
16950 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16951 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16952 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16953 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16955 #undef THUMB_VARIANT
16956 #define THUMB_VARIANT & arm_ext_v6_notm
16957 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
16959 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
16960 RRnpcb
), strexd
, t_strexd
),
16962 #undef THUMB_VARIANT
16963 #define THUMB_VARIANT & arm_ext_v6t2
16964 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
16966 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
16968 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16970 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16972 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16975 #define ARM_VARIANT & arm_ext_v6z
16977 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16980 #define ARM_VARIANT & arm_ext_v6t2
16982 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16983 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16984 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16985 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16987 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16988 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16989 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16990 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
16992 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16993 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16994 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16995 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
16997 /* Thumb-only instructions. */
16999 #define ARM_VARIANT NULL
17000 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17001 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17003 /* ARM does not really have an IT instruction, so always allow it.
17004 The opcode is copied from Thumb in order to allow warnings in
17005 -mimplicit-it=[never | arm] modes. */
17007 #define ARM_VARIANT & arm_ext_v1
17009 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17010 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17011 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17012 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17013 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17014 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17015 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17016 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17017 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17018 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17019 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17020 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17021 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17022 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17023 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17024 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17025 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17026 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17028 /* Thumb2 only instructions. */
17030 #define ARM_VARIANT NULL
17032 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17033 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17034 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17035 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17036 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17037 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17039 /* Thumb-2 hardware division instructions (R and M profiles only). */
17040 #undef THUMB_VARIANT
17041 #define THUMB_VARIANT & arm_ext_div
17043 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17044 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17046 /* ARM V6M/V7 instructions. */
17048 #define ARM_VARIANT & arm_ext_barrier
17049 #undef THUMB_VARIANT
17050 #define THUMB_VARIANT & arm_ext_barrier
17052 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17053 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17054 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17056 /* ARM V7 instructions. */
17058 #define ARM_VARIANT & arm_ext_v7
17059 #undef THUMB_VARIANT
17060 #define THUMB_VARIANT & arm_ext_v7
17062 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17063 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17066 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17068 cCE("wfs", e200110
, 1, (RR
), rd
),
17069 cCE("rfs", e300110
, 1, (RR
), rd
),
17070 cCE("wfc", e400110
, 1, (RR
), rd
),
17071 cCE("rfc", e500110
, 1, (RR
), rd
),
17073 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17074 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17075 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17076 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17078 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17079 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17080 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17081 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17083 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17084 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17085 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17086 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17087 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17088 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17089 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17090 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17091 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17092 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17093 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17094 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17096 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17097 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17098 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17099 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17100 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17101 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17102 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17103 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17104 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17105 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17106 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17107 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17109 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17110 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17111 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17112 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17113 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17114 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17115 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17116 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17117 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17118 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17119 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17120 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17122 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17123 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17124 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17125 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17126 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17127 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17128 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17129 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17130 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17131 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17132 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17133 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17135 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17136 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17137 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17138 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17139 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17140 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17141 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17142 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17143 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17144 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17145 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17146 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17148 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17149 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17150 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17151 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17152 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17153 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17154 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17155 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17156 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17157 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17158 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17159 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17161 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17162 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17163 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17164 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17165 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17166 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17167 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17168 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17169 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17170 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17171 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17172 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17174 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17175 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17176 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17177 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17178 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17179 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17180 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17181 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17182 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17183 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17184 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17185 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17187 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17188 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17189 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17190 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17191 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17192 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17193 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17194 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17195 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17196 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17197 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17198 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17200 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17201 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17202 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17203 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17204 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17205 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17206 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17207 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17208 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17209 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17210 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17211 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17213 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17214 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17215 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17216 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17217 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17218 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17219 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17220 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17221 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17222 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17223 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17224 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17226 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17227 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17228 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17229 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17230 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17231 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17232 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17233 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17234 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17235 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17236 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17237 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17239 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17240 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17241 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17242 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17243 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17244 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17245 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17246 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17247 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17248 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17249 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17250 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17252 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17253 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17254 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17255 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17256 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17257 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17258 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17259 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17260 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17261 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17262 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17263 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17265 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17266 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17267 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17268 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17269 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17270 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17271 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17272 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17273 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17274 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17275 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17276 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17278 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17279 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17280 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17281 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17282 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17283 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17284 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17285 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17286 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17287 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17288 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17289 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17291 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17292 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17293 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17294 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17295 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17296 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17297 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17298 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17299 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17300 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17301 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17302 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17304 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17305 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17306 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17307 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17308 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17309 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17310 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17311 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17312 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17313 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17314 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17315 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17317 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17318 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17319 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17320 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17321 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17322 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17323 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17324 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17325 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17326 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17327 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17328 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17330 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17331 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17332 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17333 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17334 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17335 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17336 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17337 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17338 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17339 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17340 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17341 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17343 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17344 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17345 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17346 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17347 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17348 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17349 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17350 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17351 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17352 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17353 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17354 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17356 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17357 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17358 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17359 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17360 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17361 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17362 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17363 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17364 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17365 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17366 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17367 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17369 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17370 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17371 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17372 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17373 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17374 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17375 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17376 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17377 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17378 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17379 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17380 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17382 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17383 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17384 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17385 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17386 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17387 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17388 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17389 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17390 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17391 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17392 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17393 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17395 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17396 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17397 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17398 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17399 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17400 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17401 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17402 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17403 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17404 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17405 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17406 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17408 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17409 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17410 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17411 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17412 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17413 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17414 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17415 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17416 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17417 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17418 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17419 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17421 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17422 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17423 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17424 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17425 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17426 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17427 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17428 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17429 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17430 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17431 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17432 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17434 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17435 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17436 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17437 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17438 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17439 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17440 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17441 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17442 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17443 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17444 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17445 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17447 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17448 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17449 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17450 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17451 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17452 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17453 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17454 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17455 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17456 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17457 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17458 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17460 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17461 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17462 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17463 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17465 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17466 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17467 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17468 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17469 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17470 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17471 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17472 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17473 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17474 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17475 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17476 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17478 /* The implementation of the FIX instruction is broken on some
17479 assemblers, in that it accepts a precision specifier as well as a
17480 rounding specifier, despite the fact that this is meaningless.
17481 To be more compatible, we accept it as well, though of course it
17482 does not set any bits. */
17483 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17484 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17485 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17486 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17487 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17488 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17489 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17490 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17491 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17492 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17493 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17494 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17495 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17497 /* Instructions that were new with the real FPA, call them V2. */
17499 #define ARM_VARIANT & fpu_fpa_ext_v2
17501 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17502 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17503 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17504 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17505 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17506 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17509 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17511 /* Moves and type conversions. */
17512 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17513 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17514 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17515 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17516 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17517 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17518 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17519 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17520 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17521 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17522 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17523 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17524 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17525 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17527 /* Memory operations. */
17528 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17529 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17530 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17531 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17532 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17533 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17534 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17535 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17536 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17537 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17538 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17539 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17540 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17541 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17542 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17543 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17544 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17545 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17547 /* Monadic operations. */
17548 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17549 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17550 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17552 /* Dyadic operations. */
17553 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17554 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17555 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17556 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17557 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17558 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17559 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17560 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17561 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17564 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17565 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17566 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17567 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17569 /* Double precision load/store are still present on single precision
17570 implementations. */
17571 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17572 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17573 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17574 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17575 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17576 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17577 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17578 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17579 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17580 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17583 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17585 /* Moves and type conversions. */
17586 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17587 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17588 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17589 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17590 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17591 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17592 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17593 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17594 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17595 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17596 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17597 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17598 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17600 /* Monadic operations. */
17601 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17602 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17603 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17605 /* Dyadic operations. */
17606 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17607 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17608 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17609 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17610 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17611 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17612 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17613 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17614 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17617 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17618 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17619 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17620 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17623 #define ARM_VARIANT & fpu_vfp_ext_v2
17625 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17626 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17627 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17628 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17630 /* Instructions which may belong to either the Neon or VFP instruction sets.
17631 Individual encoder functions perform additional architecture checks. */
17633 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17634 #undef THUMB_VARIANT
17635 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17637 /* These mnemonics are unique to VFP. */
17638 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17639 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17640 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17641 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17642 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17643 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17644 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17645 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17646 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17647 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17649 /* Mnemonics shared by Neon and VFP. */
17650 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17651 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17652 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17654 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17655 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17657 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17658 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17660 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17661 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17662 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17663 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17664 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17665 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17666 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17667 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17669 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17670 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17671 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17672 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17675 /* NOTE: All VMOV encoding is special-cased! */
17676 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17677 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17679 #undef THUMB_VARIANT
17680 #define THUMB_VARIANT & fpu_neon_ext_v1
17682 #define ARM_VARIANT & fpu_neon_ext_v1
17684 /* Data processing with three registers of the same length. */
17685 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17686 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17687 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17688 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17689 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17690 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17691 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17692 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17693 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17694 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17695 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17696 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17697 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17698 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17699 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17700 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17701 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17702 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17703 /* If not immediate, fall back to neon_dyadic_i64_su.
17704 shl_imm should accept I8 I16 I32 I64,
17705 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17706 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17707 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17708 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17709 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17710 /* Logic ops, types optional & ignored. */
17711 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17712 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17713 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17714 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17715 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17716 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17717 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17718 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17719 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17720 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17721 /* Bitfield ops, untyped. */
17722 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17723 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17724 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17725 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17726 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17727 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17728 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17729 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17730 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17731 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17732 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17733 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17734 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17735 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17736 back to neon_dyadic_if_su. */
17737 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17738 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17739 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17740 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17741 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17742 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17743 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17744 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17745 /* Comparison. Type I8 I16 I32 F32. */
17746 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17747 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17748 /* As above, D registers only. */
17749 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17750 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17751 /* Int and float variants, signedness unimportant. */
17752 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17753 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17754 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17755 /* Add/sub take types I8 I16 I32 I64 F32. */
17756 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17757 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17758 /* vtst takes sizes 8, 16, 32. */
17759 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17760 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17761 /* VMUL takes I8 I16 I32 F32 P8. */
17762 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17763 /* VQD{R}MULH takes S16 S32. */
17764 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17765 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17766 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17767 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17768 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17769 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17770 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17771 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17772 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17773 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17774 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17775 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17776 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17777 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17778 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17779 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17781 /* Two address, int/float. Types S8 S16 S32 F32. */
17782 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17783 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17785 /* Data processing with two registers and a shift amount. */
17786 /* Right shifts, and variants with rounding.
17787 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17788 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17789 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17790 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17791 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17792 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17793 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17794 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17795 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17796 /* Shift and insert. Sizes accepted 8 16 32 64. */
17797 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17798 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17799 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17800 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17801 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17802 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17803 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17804 /* Right shift immediate, saturating & narrowing, with rounding variants.
17805 Types accepted S16 S32 S64 U16 U32 U64. */
17806 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17807 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17808 /* As above, unsigned. Types accepted S16 S32 S64. */
17809 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17810 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17811 /* Right shift narrowing. Types accepted I16 I32 I64. */
17812 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17813 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17814 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17815 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17816 /* CVT with optional immediate for fixed-point variant. */
17817 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17819 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17820 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17822 /* Data processing, three registers of different lengths. */
17823 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17824 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17825 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17826 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17827 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17828 /* If not scalar, fall back to neon_dyadic_long.
17829 Vector types as above, scalar types S16 S32 U16 U32. */
17830 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17831 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17832 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17833 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17834 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17835 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17836 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17837 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17838 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17839 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17840 /* Saturating doubling multiplies. Types S16 S32. */
17841 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17842 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17843 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17844 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17845 S16 S32 U16 U32. */
17846 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17848 /* Extract. Size 8. */
17849 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17850 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17852 /* Two registers, miscellaneous. */
17853 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17854 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17855 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17856 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17857 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17858 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17859 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17860 /* Vector replicate. Sizes 8 16 32. */
17861 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17862 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17863 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17864 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17865 /* VMOVN. Types I16 I32 I64. */
17866 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17867 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17868 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17869 /* VQMOVUN. Types S16 S32 S64. */
17870 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17871 /* VZIP / VUZP. Sizes 8 16 32. */
17872 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17873 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17874 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17875 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17876 /* VQABS / VQNEG. Types S8 S16 S32. */
17877 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17878 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17879 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17880 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17881 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17882 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17883 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17884 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17885 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17886 /* Reciprocal estimates. Types U32 F32. */
17887 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17888 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17889 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17890 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17891 /* VCLS. Types S8 S16 S32. */
17892 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17893 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17894 /* VCLZ. Types I8 I16 I32. */
17895 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17896 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17897 /* VCNT. Size 8. */
17898 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17899 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17900 /* Two address, untyped. */
17901 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17902 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17903 /* VTRN. Sizes 8 16 32. */
17904 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17905 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17907 /* Table lookup. Size 8. */
17908 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17909 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17911 #undef THUMB_VARIANT
17912 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17914 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17916 /* Neon element/structure load/store. */
17917 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17918 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17919 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17920 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17921 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17922 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17923 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17924 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17926 #undef THUMB_VARIANT
17927 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17929 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17930 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17931 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17932 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17933 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17934 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17935 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17936 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17937 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17938 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17940 #undef THUMB_VARIANT
17941 #define THUMB_VARIANT & fpu_vfp_ext_v3
17943 #define ARM_VARIANT & fpu_vfp_ext_v3
17945 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17946 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17947 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17948 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17949 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17950 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17951 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17952 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17953 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17956 #define ARM_VARIANT &fpu_vfp_ext_fma
17957 #undef THUMB_VARIANT
17958 #define THUMB_VARIANT &fpu_vfp_ext_fma
17959 /* Mnemonics shared by Neon and VFP. These are included in the
17960 VFP FMA variant; NEON and VFP FMA always includes the NEON
17961 FMA instructions. */
17962 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17963 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17964 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17965 the v form should always be used. */
17966 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17967 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17968 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17969 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17970 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17971 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17973 #undef THUMB_VARIANT
17975 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17977 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17978 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17979 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17980 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17981 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17982 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17983 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17984 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17987 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17989 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17990 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
17991 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
17992 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
17993 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
17994 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
17995 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
17996 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
17997 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
17998 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
17999 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18000 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18001 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18002 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18003 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18004 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18005 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18006 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18007 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18008 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18009 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18010 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18011 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18012 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18013 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18014 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18015 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18016 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18017 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18018 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18019 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18020 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18021 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18022 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18023 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18024 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18025 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18026 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18027 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18028 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18029 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18030 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18031 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18032 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18033 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18034 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18035 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18036 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18037 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18038 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18039 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18040 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18041 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18042 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18043 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18044 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18045 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18046 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18047 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18048 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18049 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18050 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18051 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18052 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18053 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18054 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18055 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18056 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18057 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18058 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18059 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18060 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18061 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18062 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18063 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18064 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18065 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18066 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18067 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18068 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18069 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18070 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18071 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18072 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18073 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18074 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18075 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18076 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18077 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18078 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18079 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18080 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18081 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18082 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18083 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18084 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18085 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18086 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18087 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18088 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18089 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18090 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18091 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18092 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18093 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18094 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18095 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18096 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18097 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18098 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18099 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18100 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18101 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18102 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18103 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18104 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18105 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18106 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18107 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18108 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18109 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18110 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18111 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18112 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18113 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18114 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18115 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18116 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18117 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18118 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18119 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18120 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18121 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18122 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18123 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18124 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18125 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18126 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18127 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18128 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18129 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18130 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18131 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18132 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18133 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18134 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18135 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18136 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18137 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18138 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18139 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18140 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18141 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18142 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18143 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18144 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18145 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18146 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18147 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18148 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18149 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18150 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18153 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18155 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18156 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18157 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18158 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18159 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18160 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18161 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18162 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18163 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18164 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18165 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18166 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18167 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18168 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18169 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18170 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18171 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18172 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18173 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18174 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18175 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18176 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18177 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18178 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18179 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18180 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18181 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18182 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18183 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18184 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18185 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18186 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18187 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18188 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18189 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18190 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18191 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18192 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18193 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18194 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18195 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18196 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18197 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18198 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18199 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18200 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18201 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18202 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18203 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18204 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18205 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18206 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18207 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18208 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18209 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18210 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18211 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18214 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18216 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18217 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18218 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18219 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18220 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18221 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18222 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18223 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18224 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18225 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18226 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18227 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18228 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18229 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18230 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18231 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18232 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18233 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18234 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18235 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18236 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18237 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18238 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18239 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18240 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18241 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18242 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18243 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18244 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18245 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18246 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18247 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18248 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18249 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18250 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18251 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18252 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18253 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18254 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18255 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18256 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18257 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18258 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18259 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18260 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18261 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18262 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18263 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18264 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18265 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18266 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18267 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18268 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18269 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18270 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18271 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18272 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18273 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18274 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18275 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18276 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18277 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18278 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18279 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18280 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18281 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18282 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18283 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18284 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18285 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18286 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18287 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18288 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18289 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18290 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18291 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18294 #undef THUMB_VARIANT
18321 /* MD interface: bits in the object file. */
18323 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18324 for use in the a.out file, and stores them in the array pointed to by buf.
18325 This knows about the endian-ness of the target machine and does
18326 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18327 2 (short) and 4 (long) Floating numbers are put out as a series of
18328 LITTLENUMS (shorts, here at least). */
18331 md_number_to_chars (char * buf
, valueT val
, int n
)
18333 if (target_big_endian
)
18334 number_to_chars_bigendian (buf
, val
, n
);
18336 number_to_chars_littleendian (buf
, val
, n
);
18340 md_chars_to_number (char * buf
, int n
)
18343 unsigned char * where
= (unsigned char *) buf
;
18345 if (target_big_endian
)
18350 result
|= (*where
++ & 255);
18358 result
|= (where
[n
] & 255);
18365 /* MD interface: Sections. */
18367 /* Estimate the size of a frag before relaxing. Assume everything fits in
18371 md_estimate_size_before_relax (fragS
* fragp
,
18372 segT segtype ATTRIBUTE_UNUSED
)
18378 /* Convert a machine dependent frag. */
18381 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18383 unsigned long insn
;
18384 unsigned long old_op
;
18392 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18394 old_op
= bfd_get_16(abfd
, buf
);
18395 if (fragp
->fr_symbol
)
18397 exp
.X_op
= O_symbol
;
18398 exp
.X_add_symbol
= fragp
->fr_symbol
;
18402 exp
.X_op
= O_constant
;
18404 exp
.X_add_number
= fragp
->fr_offset
;
18405 opcode
= fragp
->fr_subtype
;
18408 case T_MNEM_ldr_pc
:
18409 case T_MNEM_ldr_pc2
:
18410 case T_MNEM_ldr_sp
:
18411 case T_MNEM_str_sp
:
18418 if (fragp
->fr_var
== 4)
18420 insn
= THUMB_OP32 (opcode
);
18421 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18423 insn
|= (old_op
& 0x700) << 4;
18427 insn
|= (old_op
& 7) << 12;
18428 insn
|= (old_op
& 0x38) << 13;
18430 insn
|= 0x00000c00;
18431 put_thumb32_insn (buf
, insn
);
18432 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18436 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18438 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18441 if (fragp
->fr_var
== 4)
18443 insn
= THUMB_OP32 (opcode
);
18444 insn
|= (old_op
& 0xf0) << 4;
18445 put_thumb32_insn (buf
, insn
);
18446 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18450 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18451 exp
.X_add_number
-= 4;
18459 if (fragp
->fr_var
== 4)
18461 int r0off
= (opcode
== T_MNEM_mov
18462 || opcode
== T_MNEM_movs
) ? 0 : 8;
18463 insn
= THUMB_OP32 (opcode
);
18464 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18465 insn
|= (old_op
& 0x700) << r0off
;
18466 put_thumb32_insn (buf
, insn
);
18467 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18471 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18476 if (fragp
->fr_var
== 4)
18478 insn
= THUMB_OP32(opcode
);
18479 put_thumb32_insn (buf
, insn
);
18480 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18483 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18487 if (fragp
->fr_var
== 4)
18489 insn
= THUMB_OP32(opcode
);
18490 insn
|= (old_op
& 0xf00) << 14;
18491 put_thumb32_insn (buf
, insn
);
18492 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18495 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18498 case T_MNEM_add_sp
:
18499 case T_MNEM_add_pc
:
18500 case T_MNEM_inc_sp
:
18501 case T_MNEM_dec_sp
:
18502 if (fragp
->fr_var
== 4)
18504 /* ??? Choose between add and addw. */
18505 insn
= THUMB_OP32 (opcode
);
18506 insn
|= (old_op
& 0xf0) << 4;
18507 put_thumb32_insn (buf
, insn
);
18508 if (opcode
== T_MNEM_add_pc
)
18509 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18511 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18514 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18522 if (fragp
->fr_var
== 4)
18524 insn
= THUMB_OP32 (opcode
);
18525 insn
|= (old_op
& 0xf0) << 4;
18526 insn
|= (old_op
& 0xf) << 16;
18527 put_thumb32_insn (buf
, insn
);
18528 if (insn
& (1 << 20))
18529 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18531 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18534 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18540 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18541 (enum bfd_reloc_code_real
) reloc_type
);
18542 fixp
->fx_file
= fragp
->fr_file
;
18543 fixp
->fx_line
= fragp
->fr_line
;
18544 fragp
->fr_fix
+= fragp
->fr_var
;
18547 /* Return the size of a relaxable immediate operand instruction.
18548 SHIFT and SIZE specify the form of the allowable immediate. */
18550 relax_immediate (fragS
*fragp
, int size
, int shift
)
18556 /* ??? Should be able to do better than this. */
18557 if (fragp
->fr_symbol
)
18560 low
= (1 << shift
) - 1;
18561 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18562 offset
= fragp
->fr_offset
;
18563 /* Force misaligned offsets to 32-bit variant. */
18566 if (offset
& ~mask
)
18571 /* Get the address of a symbol during relaxation. */
18573 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18579 sym
= fragp
->fr_symbol
;
18580 sym_frag
= symbol_get_frag (sym
);
18581 know (S_GET_SEGMENT (sym
) != absolute_section
18582 || sym_frag
== &zero_address_frag
);
18583 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18585 /* If frag has yet to be reached on this pass, assume it will
18586 move by STRETCH just as we did. If this is not so, it will
18587 be because some frag between grows, and that will force
18591 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18595 /* Adjust stretch for any alignment frag. Note that if have
18596 been expanding the earlier code, the symbol may be
18597 defined in what appears to be an earlier frag. FIXME:
18598 This doesn't handle the fr_subtype field, which specifies
18599 a maximum number of bytes to skip when doing an
18601 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18603 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18606 stretch
= - ((- stretch
)
18607 & ~ ((1 << (int) f
->fr_offset
) - 1));
18609 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18621 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18624 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18629 /* Assume worst case for symbols not known to be in the same section. */
18630 if (fragp
->fr_symbol
== NULL
18631 || !S_IS_DEFINED (fragp
->fr_symbol
)
18632 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18633 || S_IS_WEAK (fragp
->fr_symbol
))
18636 val
= relaxed_symbol_addr (fragp
, stretch
);
18637 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18638 addr
= (addr
+ 4) & ~3;
18639 /* Force misaligned targets to 32-bit variant. */
18643 if (val
< 0 || val
> 1020)
18648 /* Return the size of a relaxable add/sub immediate instruction. */
18650 relax_addsub (fragS
*fragp
, asection
*sec
)
18655 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18656 op
= bfd_get_16(sec
->owner
, buf
);
18657 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18658 return relax_immediate (fragp
, 8, 0);
18660 return relax_immediate (fragp
, 3, 0);
18664 /* Return the size of a relaxable branch instruction. BITS is the
18665 size of the offset field in the narrow instruction. */
18668 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18674 /* Assume worst case for symbols not known to be in the same section. */
18675 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18676 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18677 || S_IS_WEAK (fragp
->fr_symbol
))
18681 if (S_IS_DEFINED (fragp
->fr_symbol
)
18682 && ARM_IS_FUNC (fragp
->fr_symbol
))
18686 val
= relaxed_symbol_addr (fragp
, stretch
);
18687 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18690 /* Offset is a signed value *2 */
18692 if (val
>= limit
|| val
< -limit
)
18698 /* Relax a machine dependent frag. This returns the amount by which
18699 the current size of the frag should change. */
18702 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18707 oldsize
= fragp
->fr_var
;
18708 switch (fragp
->fr_subtype
)
18710 case T_MNEM_ldr_pc2
:
18711 newsize
= relax_adr (fragp
, sec
, stretch
);
18713 case T_MNEM_ldr_pc
:
18714 case T_MNEM_ldr_sp
:
18715 case T_MNEM_str_sp
:
18716 newsize
= relax_immediate (fragp
, 8, 2);
18720 newsize
= relax_immediate (fragp
, 5, 2);
18724 newsize
= relax_immediate (fragp
, 5, 1);
18728 newsize
= relax_immediate (fragp
, 5, 0);
18731 newsize
= relax_adr (fragp
, sec
, stretch
);
18737 newsize
= relax_immediate (fragp
, 8, 0);
18740 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18743 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18745 case T_MNEM_add_sp
:
18746 case T_MNEM_add_pc
:
18747 newsize
= relax_immediate (fragp
, 8, 2);
18749 case T_MNEM_inc_sp
:
18750 case T_MNEM_dec_sp
:
18751 newsize
= relax_immediate (fragp
, 7, 2);
18757 newsize
= relax_addsub (fragp
, sec
);
18763 fragp
->fr_var
= newsize
;
18764 /* Freeze wide instructions that are at or before the same location as
18765 in the previous pass. This avoids infinite loops.
18766 Don't freeze them unconditionally because targets may be artificially
18767 misaligned by the expansion of preceding frags. */
18768 if (stretch
<= 0 && newsize
> 2)
18770 md_convert_frag (sec
->owner
, sec
, fragp
);
18774 return newsize
- oldsize
;
18777 /* Round up a section size to the appropriate boundary. */
18780 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18783 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18784 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18786 /* For a.out, force the section size to be aligned. If we don't do
18787 this, BFD will align it for us, but it will not write out the
18788 final bytes of the section. This may be a bug in BFD, but it is
18789 easier to fix it here since that is how the other a.out targets
18793 align
= bfd_get_section_alignment (stdoutput
, segment
);
18794 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18801 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18802 of an rs_align_code fragment. */
18805 arm_handle_align (fragS
* fragP
)
18807 static char const arm_noop
[2][2][4] =
18810 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18811 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18814 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18815 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18818 static char const thumb_noop
[2][2][2] =
18821 {0xc0, 0x46}, /* LE */
18822 {0x46, 0xc0}, /* BE */
18825 {0x00, 0xbf}, /* LE */
18826 {0xbf, 0x00} /* BE */
18829 static char const wide_thumb_noop
[2][4] =
18830 { /* Wide Thumb-2 */
18831 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18832 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18835 unsigned bytes
, fix
, noop_size
;
18838 const char *narrow_noop
= NULL
;
18843 if (fragP
->fr_type
!= rs_align_code
)
18846 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18847 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18850 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18851 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18853 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18855 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18857 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18859 narrow_noop
= thumb_noop
[1][target_big_endian
];
18860 noop
= wide_thumb_noop
[target_big_endian
];
18863 noop
= thumb_noop
[0][target_big_endian
];
18871 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18872 [target_big_endian
];
18879 fragP
->fr_var
= noop_size
;
18881 if (bytes
& (noop_size
- 1))
18883 fix
= bytes
& (noop_size
- 1);
18885 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18887 memset (p
, 0, fix
);
18894 if (bytes
& noop_size
)
18896 /* Insert a narrow noop. */
18897 memcpy (p
, narrow_noop
, noop_size
);
18899 bytes
-= noop_size
;
18903 /* Use wide noops for the remainder */
18907 while (bytes
>= noop_size
)
18909 memcpy (p
, noop
, noop_size
);
18911 bytes
-= noop_size
;
18915 fragP
->fr_fix
+= fix
;
18918 /* Called from md_do_align. Used to create an alignment
18919 frag in a code section. */
18922 arm_frag_align_code (int n
, int max
)
18926 /* We assume that there will never be a requirement
18927 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18928 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18933 _("alignments greater than %d bytes not supported in .text sections."),
18934 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18935 as_fatal ("%s", err_msg
);
18938 p
= frag_var (rs_align_code
,
18939 MAX_MEM_FOR_RS_ALIGN_CODE
,
18941 (relax_substateT
) max
,
18948 /* Perform target specific initialisation of a frag.
18949 Note - despite the name this initialisation is not done when the frag
18950 is created, but only when its type is assigned. A frag can be created
18951 and used a long time before its type is set, so beware of assuming that
18952 this initialisationis performed first. */
18956 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18958 /* Record whether this frag is in an ARM or a THUMB area. */
18959 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18962 #else /* OBJ_ELF is defined. */
18964 arm_init_frag (fragS
* fragP
, int max_chars
)
18966 /* If the current ARM vs THUMB mode has not already
18967 been recorded into this frag then do so now. */
18968 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18970 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18972 /* Record a mapping symbol for alignment frags. We will delete this
18973 later if the alignment ends up empty. */
18974 switch (fragP
->fr_type
)
18977 case rs_align_test
:
18979 mapping_state_2 (MAP_DATA
, max_chars
);
18981 case rs_align_code
:
18982 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18990 /* When we change sections we need to issue a new mapping symbol. */
18993 arm_elf_change_section (void)
18995 /* Link an unlinked unwind index table section to the .text section. */
18996 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
18997 && elf_linked_to_section (now_seg
) == NULL
)
18998 elf_linked_to_section (now_seg
) = text_section
;
19002 arm_elf_section_type (const char * str
, size_t len
)
19004 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19005 return SHT_ARM_EXIDX
;
19010 /* Code to deal with unwinding tables. */
19012 static void add_unwind_adjustsp (offsetT
);
19014 /* Generate any deferred unwind frame offset. */
19017 flush_pending_unwind (void)
19021 offset
= unwind
.pending_offset
;
19022 unwind
.pending_offset
= 0;
19024 add_unwind_adjustsp (offset
);
19027 /* Add an opcode to this list for this function. Two-byte opcodes should
19028 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19032 add_unwind_opcode (valueT op
, int length
)
19034 /* Add any deferred stack adjustment. */
19035 if (unwind
.pending_offset
)
19036 flush_pending_unwind ();
19038 unwind
.sp_restored
= 0;
19040 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19042 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19043 if (unwind
.opcodes
)
19044 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19045 unwind
.opcode_alloc
);
19047 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19052 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19054 unwind
.opcode_count
++;
19058 /* Add unwind opcodes to adjust the stack pointer. */
19061 add_unwind_adjustsp (offsetT offset
)
19065 if (offset
> 0x200)
19067 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19072 /* Long form: 0xb2, uleb128. */
19073 /* This might not fit in a word so add the individual bytes,
19074 remembering the list is built in reverse order. */
19075 o
= (valueT
) ((offset
- 0x204) >> 2);
19077 add_unwind_opcode (0, 1);
19079 /* Calculate the uleb128 encoding of the offset. */
19083 bytes
[n
] = o
& 0x7f;
19089 /* Add the insn. */
19091 add_unwind_opcode (bytes
[n
- 1], 1);
19092 add_unwind_opcode (0xb2, 1);
19094 else if (offset
> 0x100)
19096 /* Two short opcodes. */
19097 add_unwind_opcode (0x3f, 1);
19098 op
= (offset
- 0x104) >> 2;
19099 add_unwind_opcode (op
, 1);
19101 else if (offset
> 0)
19103 /* Short opcode. */
19104 op
= (offset
- 4) >> 2;
19105 add_unwind_opcode (op
, 1);
19107 else if (offset
< 0)
19110 while (offset
> 0x100)
19112 add_unwind_opcode (0x7f, 1);
19115 op
= ((offset
- 4) >> 2) | 0x40;
19116 add_unwind_opcode (op
, 1);
19120 /* Finish the list of unwind opcodes for this function. */
19122 finish_unwind_opcodes (void)
19126 if (unwind
.fp_used
)
19128 /* Adjust sp as necessary. */
19129 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19130 flush_pending_unwind ();
19132 /* After restoring sp from the frame pointer. */
19133 op
= 0x90 | unwind
.fp_reg
;
19134 add_unwind_opcode (op
, 1);
19137 flush_pending_unwind ();
19141 /* Start an exception table entry. If idx is nonzero this is an index table
19145 start_unwind_section (const segT text_seg
, int idx
)
19147 const char * text_name
;
19148 const char * prefix
;
19149 const char * prefix_once
;
19150 const char * group_name
;
19154 size_t sec_name_len
;
19161 prefix
= ELF_STRING_ARM_unwind
;
19162 prefix_once
= ELF_STRING_ARM_unwind_once
;
19163 type
= SHT_ARM_EXIDX
;
19167 prefix
= ELF_STRING_ARM_unwind_info
;
19168 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19169 type
= SHT_PROGBITS
;
19172 text_name
= segment_name (text_seg
);
19173 if (streq (text_name
, ".text"))
19176 if (strncmp (text_name
, ".gnu.linkonce.t.",
19177 strlen (".gnu.linkonce.t.")) == 0)
19179 prefix
= prefix_once
;
19180 text_name
+= strlen (".gnu.linkonce.t.");
19183 prefix_len
= strlen (prefix
);
19184 text_len
= strlen (text_name
);
19185 sec_name_len
= prefix_len
+ text_len
;
19186 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19187 memcpy (sec_name
, prefix
, prefix_len
);
19188 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19189 sec_name
[prefix_len
+ text_len
] = '\0';
19195 /* Handle COMDAT group. */
19196 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19198 group_name
= elf_group_name (text_seg
);
19199 if (group_name
== NULL
)
19201 as_bad (_("Group section `%s' has no group signature"),
19202 segment_name (text_seg
));
19203 ignore_rest_of_line ();
19206 flags
|= SHF_GROUP
;
19210 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19212 /* Set the section link for index tables. */
19214 elf_linked_to_section (now_seg
) = text_seg
;
19218 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19219 personality routine data. Returns zero, or the index table value for
19220 and inline entry. */
19223 create_unwind_entry (int have_data
)
19228 /* The current word of data. */
19230 /* The number of bytes left in this word. */
19233 finish_unwind_opcodes ();
19235 /* Remember the current text section. */
19236 unwind
.saved_seg
= now_seg
;
19237 unwind
.saved_subseg
= now_subseg
;
19239 start_unwind_section (now_seg
, 0);
19241 if (unwind
.personality_routine
== NULL
)
19243 if (unwind
.personality_index
== -2)
19246 as_bad (_("handlerdata in cantunwind frame"));
19247 return 1; /* EXIDX_CANTUNWIND. */
19250 /* Use a default personality routine if none is specified. */
19251 if (unwind
.personality_index
== -1)
19253 if (unwind
.opcode_count
> 3)
19254 unwind
.personality_index
= 1;
19256 unwind
.personality_index
= 0;
19259 /* Space for the personality routine entry. */
19260 if (unwind
.personality_index
== 0)
19262 if (unwind
.opcode_count
> 3)
19263 as_bad (_("too many unwind opcodes for personality routine 0"));
19267 /* All the data is inline in the index table. */
19270 while (unwind
.opcode_count
> 0)
19272 unwind
.opcode_count
--;
19273 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19277 /* Pad with "finish" opcodes. */
19279 data
= (data
<< 8) | 0xb0;
19286 /* We get two opcodes "free" in the first word. */
19287 size
= unwind
.opcode_count
- 2;
19290 /* An extra byte is required for the opcode count. */
19291 size
= unwind
.opcode_count
+ 1;
19293 size
= (size
+ 3) >> 2;
19295 as_bad (_("too many unwind opcodes"));
19297 frag_align (2, 0, 0);
19298 record_alignment (now_seg
, 2);
19299 unwind
.table_entry
= expr_build_dot ();
19301 /* Allocate the table entry. */
19302 ptr
= frag_more ((size
<< 2) + 4);
19303 where
= frag_now_fix () - ((size
<< 2) + 4);
19305 switch (unwind
.personality_index
)
19308 /* ??? Should this be a PLT generating relocation? */
19309 /* Custom personality routine. */
19310 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19311 BFD_RELOC_ARM_PREL31
);
19316 /* Set the first byte to the number of additional words. */
19321 /* ABI defined personality routines. */
19323 /* Three opcodes bytes are packed into the first word. */
19330 /* The size and first two opcode bytes go in the first word. */
19331 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19336 /* Should never happen. */
19340 /* Pack the opcodes into words (MSB first), reversing the list at the same
19342 while (unwind
.opcode_count
> 0)
19346 md_number_to_chars (ptr
, data
, 4);
19351 unwind
.opcode_count
--;
19353 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19356 /* Finish off the last word. */
19359 /* Pad with "finish" opcodes. */
19361 data
= (data
<< 8) | 0xb0;
19363 md_number_to_chars (ptr
, data
, 4);
19368 /* Add an empty descriptor if there is no user-specified data. */
19369 ptr
= frag_more (4);
19370 md_number_to_chars (ptr
, 0, 4);
19377 /* Initialize the DWARF-2 unwind information for this procedure. */
19380 tc_arm_frame_initial_instructions (void)
19382 cfi_add_CFA_def_cfa (REG_SP
, 0);
19384 #endif /* OBJ_ELF */
19386 /* Convert REGNAME to a DWARF-2 register number. */
19389 tc_arm_regname_to_dw2regnum (char *regname
)
19391 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19401 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19405 exp
.X_op
= O_secrel
;
19406 exp
.X_add_symbol
= symbol
;
19407 exp
.X_add_number
= 0;
19408 emit_expr (&exp
, size
);
19412 /* MD interface: Symbol and relocation handling. */
19414 /* Return the address within the segment that a PC-relative fixup is
19415 relative to. For ARM, PC-relative fixups applied to instructions
19416 are generally relative to the location of the fixup plus 8 bytes.
19417 Thumb branches are offset by 4, and Thumb loads relative to PC
19418 require special handling. */
19421 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19423 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19425 /* If this is pc-relative and we are going to emit a relocation
19426 then we just want to put out any pipeline compensation that the linker
19427 will need. Otherwise we want to use the calculated base.
19428 For WinCE we skip the bias for externals as well, since this
19429 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19431 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19432 || (arm_force_relocation (fixP
)
19434 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19440 switch (fixP
->fx_r_type
)
19442 /* PC relative addressing on the Thumb is slightly odd as the
19443 bottom two bits of the PC are forced to zero for the
19444 calculation. This happens *after* application of the
19445 pipeline offset. However, Thumb adrl already adjusts for
19446 this, so we need not do it again. */
19447 case BFD_RELOC_ARM_THUMB_ADD
:
19450 case BFD_RELOC_ARM_THUMB_OFFSET
:
19451 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19452 case BFD_RELOC_ARM_T32_ADD_PC12
:
19453 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19454 return (base
+ 4) & ~3;
19456 /* Thumb branches are simply offset by +4. */
19457 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19458 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19459 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19460 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19461 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19464 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19466 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19467 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19468 && ARM_IS_FUNC (fixP
->fx_addsy
)
19469 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19470 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19473 /* BLX is like branches above, but forces the low two bits of PC to
19475 case BFD_RELOC_THUMB_PCREL_BLX
:
19477 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19478 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19479 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19480 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19481 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19482 return (base
+ 4) & ~3;
19484 /* ARM mode branches are offset by +8. However, the Windows CE
19485 loader expects the relocation not to take this into account. */
19486 case BFD_RELOC_ARM_PCREL_BLX
:
19488 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19489 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19490 && ARM_IS_FUNC (fixP
->fx_addsy
)
19491 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19492 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19495 case BFD_RELOC_ARM_PCREL_CALL
:
19497 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19498 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19499 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19500 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19501 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19504 case BFD_RELOC_ARM_PCREL_BRANCH
:
19505 case BFD_RELOC_ARM_PCREL_JUMP
:
19506 case BFD_RELOC_ARM_PLT32
:
19508 /* When handling fixups immediately, because we have already
19509 discovered the value of a symbol, or the address of the frag involved
19510 we must account for the offset by +8, as the OS loader will never see the reloc.
19511 see fixup_segment() in write.c
19512 The S_IS_EXTERNAL test handles the case of global symbols.
19513 Those need the calculated base, not just the pipe compensation the linker will need. */
19515 && fixP
->fx_addsy
!= NULL
19516 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19517 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19525 /* ARM mode loads relative to PC are also offset by +8. Unlike
19526 branches, the Windows CE loader *does* expect the relocation
19527 to take this into account. */
19528 case BFD_RELOC_ARM_OFFSET_IMM
:
19529 case BFD_RELOC_ARM_OFFSET_IMM8
:
19530 case BFD_RELOC_ARM_HWLITERAL
:
19531 case BFD_RELOC_ARM_LITERAL
:
19532 case BFD_RELOC_ARM_CP_OFF_IMM
:
19536 /* Other PC-relative relocations are un-offset. */
19542 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19543 Otherwise we have no need to default values of symbols. */
19546 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19549 if (name
[0] == '_' && name
[1] == 'G'
19550 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19554 if (symbol_find (name
))
19555 as_bad (_("GOT already in the symbol table"));
19557 GOT_symbol
= symbol_new (name
, undefined_section
,
19558 (valueT
) 0, & zero_address_frag
);
19568 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19569 computed as two separate immediate values, added together. We
19570 already know that this value cannot be computed by just one ARM
19573 static unsigned int
19574 validate_immediate_twopart (unsigned int val
,
19575 unsigned int * highpart
)
19580 for (i
= 0; i
< 32; i
+= 2)
19581 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19587 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19589 else if (a
& 0xff0000)
19591 if (a
& 0xff000000)
19593 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19597 gas_assert (a
& 0xff000000);
19598 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19601 return (a
& 0xff) | (i
<< 7);
19608 validate_offset_imm (unsigned int val
, int hwse
)
19610 if ((hwse
&& val
> 255) || val
> 4095)
19615 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19616 negative immediate constant by altering the instruction. A bit of
19621 by inverting the second operand, and
19624 by negating the second operand. */
19627 negate_data_op (unsigned long * instruction
,
19628 unsigned long value
)
19631 unsigned long negated
, inverted
;
19633 negated
= encode_arm_immediate (-value
);
19634 inverted
= encode_arm_immediate (~value
);
19636 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19639 /* First negates. */
19640 case OPCODE_SUB
: /* ADD <-> SUB */
19641 new_inst
= OPCODE_ADD
;
19646 new_inst
= OPCODE_SUB
;
19650 case OPCODE_CMP
: /* CMP <-> CMN */
19651 new_inst
= OPCODE_CMN
;
19656 new_inst
= OPCODE_CMP
;
19660 /* Now Inverted ops. */
19661 case OPCODE_MOV
: /* MOV <-> MVN */
19662 new_inst
= OPCODE_MVN
;
19667 new_inst
= OPCODE_MOV
;
19671 case OPCODE_AND
: /* AND <-> BIC */
19672 new_inst
= OPCODE_BIC
;
19677 new_inst
= OPCODE_AND
;
19681 case OPCODE_ADC
: /* ADC <-> SBC */
19682 new_inst
= OPCODE_SBC
;
19687 new_inst
= OPCODE_ADC
;
19691 /* We cannot do anything. */
19696 if (value
== (unsigned) FAIL
)
19699 *instruction
&= OPCODE_MASK
;
19700 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19704 /* Like negate_data_op, but for Thumb-2. */
19706 static unsigned int
19707 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19711 unsigned int negated
, inverted
;
19713 negated
= encode_thumb32_immediate (-value
);
19714 inverted
= encode_thumb32_immediate (~value
);
19716 rd
= (*instruction
>> 8) & 0xf;
19717 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19720 /* ADD <-> SUB. Includes CMP <-> CMN. */
19721 case T2_OPCODE_SUB
:
19722 new_inst
= T2_OPCODE_ADD
;
19726 case T2_OPCODE_ADD
:
19727 new_inst
= T2_OPCODE_SUB
;
19731 /* ORR <-> ORN. Includes MOV <-> MVN. */
19732 case T2_OPCODE_ORR
:
19733 new_inst
= T2_OPCODE_ORN
;
19737 case T2_OPCODE_ORN
:
19738 new_inst
= T2_OPCODE_ORR
;
19742 /* AND <-> BIC. TST has no inverted equivalent. */
19743 case T2_OPCODE_AND
:
19744 new_inst
= T2_OPCODE_BIC
;
19751 case T2_OPCODE_BIC
:
19752 new_inst
= T2_OPCODE_AND
;
19757 case T2_OPCODE_ADC
:
19758 new_inst
= T2_OPCODE_SBC
;
19762 case T2_OPCODE_SBC
:
19763 new_inst
= T2_OPCODE_ADC
;
19767 /* We cannot do anything. */
19772 if (value
== (unsigned int)FAIL
)
19775 *instruction
&= T2_OPCODE_MASK
;
19776 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19780 /* Read a 32-bit thumb instruction from buf. */
19781 static unsigned long
19782 get_thumb32_insn (char * buf
)
19784 unsigned long insn
;
19785 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19786 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19792 /* We usually want to set the low bit on the address of thumb function
19793 symbols. In particular .word foo - . should have the low bit set.
19794 Generic code tries to fold the difference of two symbols to
19795 a constant. Prevent this and force a relocation when the first symbols
19796 is a thumb function. */
19799 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19801 if (op
== O_subtract
19802 && l
->X_op
== O_symbol
19803 && r
->X_op
== O_symbol
19804 && THUMB_IS_FUNC (l
->X_add_symbol
))
19806 l
->X_op
= O_subtract
;
19807 l
->X_op_symbol
= r
->X_add_symbol
;
19808 l
->X_add_number
-= r
->X_add_number
;
19812 /* Process as normal. */
19816 /* Encode Thumb2 unconditional branches and calls. The encoding
19817 for the 2 are identical for the immediate values. */
19820 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19822 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19825 addressT S
, I1
, I2
, lo
, hi
;
19827 S
= (value
>> 24) & 0x01;
19828 I1
= (value
>> 23) & 0x01;
19829 I2
= (value
>> 22) & 0x01;
19830 hi
= (value
>> 12) & 0x3ff;
19831 lo
= (value
>> 1) & 0x7ff;
19832 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19833 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19834 newval
|= (S
<< 10) | hi
;
19835 newval2
&= ~T2I1I2MASK
;
19836 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19837 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19838 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19842 md_apply_fix (fixS
* fixP
,
19846 offsetT value
= * valP
;
19848 unsigned int newimm
;
19849 unsigned long temp
;
19851 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19853 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19855 /* Note whether this will delete the relocation. */
19857 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19860 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19861 consistency with the behaviour on 32-bit hosts. Remember value
19863 value
&= 0xffffffff;
19864 value
^= 0x80000000;
19865 value
-= 0x80000000;
19868 fixP
->fx_addnumber
= value
;
19870 /* Same treatment for fixP->fx_offset. */
19871 fixP
->fx_offset
&= 0xffffffff;
19872 fixP
->fx_offset
^= 0x80000000;
19873 fixP
->fx_offset
-= 0x80000000;
19875 switch (fixP
->fx_r_type
)
19877 case BFD_RELOC_NONE
:
19878 /* This will need to go in the object file. */
19882 case BFD_RELOC_ARM_IMMEDIATE
:
19883 /* We claim that this fixup has been processed here,
19884 even if in fact we generate an error because we do
19885 not have a reloc for it, so tc_gen_reloc will reject it. */
19888 if (fixP
->fx_addsy
)
19890 const char *msg
= 0;
19892 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19893 msg
= _("undefined symbol %s used as an immediate value");
19894 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19895 msg
= _("symbol %s is in a different section");
19896 else if (S_IS_WEAK (fixP
->fx_addsy
))
19897 msg
= _("symbol %s is weak and may be overridden later");
19901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19902 msg
, S_GET_NAME (fixP
->fx_addsy
));
19907 newimm
= encode_arm_immediate (value
);
19908 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19910 /* If the instruction will fail, see if we can fix things up by
19911 changing the opcode. */
19912 if (newimm
== (unsigned int) FAIL
19913 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19916 _("invalid constant (%lx) after fixup"),
19917 (unsigned long) value
);
19921 newimm
|= (temp
& 0xfffff000);
19922 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19925 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19927 unsigned int highpart
= 0;
19928 unsigned int newinsn
= 0xe1a00000; /* nop. */
19930 if (fixP
->fx_addsy
)
19932 const char *msg
= 0;
19934 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19935 msg
= _("undefined symbol %s used as an immediate value");
19936 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19937 msg
= _("symbol %s is in a different section");
19938 else if (S_IS_WEAK (fixP
->fx_addsy
))
19939 msg
= _("symbol %s is weak and may be overridden later");
19943 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19944 msg
, S_GET_NAME (fixP
->fx_addsy
));
19949 newimm
= encode_arm_immediate (value
);
19950 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19952 /* If the instruction will fail, see if we can fix things up by
19953 changing the opcode. */
19954 if (newimm
== (unsigned int) FAIL
19955 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19957 /* No ? OK - try using two ADD instructions to generate
19959 newimm
= validate_immediate_twopart (value
, & highpart
);
19961 /* Yes - then make sure that the second instruction is
19963 if (newimm
!= (unsigned int) FAIL
)
19965 /* Still No ? Try using a negated value. */
19966 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19967 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19968 /* Otherwise - give up. */
19971 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19972 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19977 /* Replace the first operand in the 2nd instruction (which
19978 is the PC) with the destination register. We have
19979 already added in the PC in the first instruction and we
19980 do not want to do it again. */
19981 newinsn
&= ~ 0xf0000;
19982 newinsn
|= ((newinsn
& 0x0f000) << 4);
19985 newimm
|= (temp
& 0xfffff000);
19986 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19988 highpart
|= (newinsn
& 0xfffff000);
19989 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
19993 case BFD_RELOC_ARM_OFFSET_IMM
:
19994 if (!fixP
->fx_done
&& seg
->use_rela_p
)
19997 case BFD_RELOC_ARM_LITERAL
:
20003 if (validate_offset_imm (value
, 0) == FAIL
)
20005 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20006 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20007 _("invalid literal constant: pool needs to be closer"));
20009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20010 _("bad immediate value for offset (%ld)"),
20015 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20016 newval
&= 0xff7ff000;
20017 newval
|= value
| (sign
? INDEX_UP
: 0);
20018 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20021 case BFD_RELOC_ARM_OFFSET_IMM8
:
20022 case BFD_RELOC_ARM_HWLITERAL
:
20028 if (validate_offset_imm (value
, 1) == FAIL
)
20030 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20032 _("invalid literal constant: pool needs to be closer"));
20034 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20039 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20040 newval
&= 0xff7ff0f0;
20041 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20042 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20045 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20046 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20048 _("bad immediate value for offset (%ld)"), (long) value
);
20051 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20053 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20056 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20057 /* This is a complicated relocation used for all varieties of Thumb32
20058 load/store instruction with immediate offset:
20060 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20061 *4, optional writeback(W)
20062 (doubleword load/store)
20064 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20065 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20066 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20067 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20068 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20070 Uppercase letters indicate bits that are already encoded at
20071 this point. Lowercase letters are our problem. For the
20072 second block of instructions, the secondary opcode nybble
20073 (bits 8..11) is present, and bit 23 is zero, even if this is
20074 a PC-relative operation. */
20075 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20077 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20079 if ((newval
& 0xf0000000) == 0xe0000000)
20081 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20083 newval
|= (1 << 23);
20086 if (value
% 4 != 0)
20088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20089 _("offset not a multiple of 4"));
20095 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20096 _("offset out of range"));
20101 else if ((newval
& 0x000f0000) == 0x000f0000)
20103 /* PC-relative, 12-bit offset. */
20105 newval
|= (1 << 23);
20110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20111 _("offset out of range"));
20116 else if ((newval
& 0x00000100) == 0x00000100)
20118 /* Writeback: 8-bit, +/- offset. */
20120 newval
|= (1 << 9);
20125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20126 _("offset out of range"));
20131 else if ((newval
& 0x00000f00) == 0x00000e00)
20133 /* T-instruction: positive 8-bit offset. */
20134 if (value
< 0 || value
> 0xff)
20136 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20137 _("offset out of range"));
20145 /* Positive 12-bit or negative 8-bit offset. */
20149 newval
|= (1 << 23);
20159 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20160 _("offset out of range"));
20167 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20168 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20171 case BFD_RELOC_ARM_SHIFT_IMM
:
20172 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20173 if (((unsigned long) value
) > 32
20175 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20177 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20178 _("shift expression is too large"));
20183 /* Shifts of zero must be done as lsl. */
20185 else if (value
== 32)
20187 newval
&= 0xfffff07f;
20188 newval
|= (value
& 0x1f) << 7;
20189 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20192 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20193 case BFD_RELOC_ARM_T32_ADD_IMM
:
20194 case BFD_RELOC_ARM_T32_IMM12
:
20195 case BFD_RELOC_ARM_T32_ADD_PC12
:
20196 /* We claim that this fixup has been processed here,
20197 even if in fact we generate an error because we do
20198 not have a reloc for it, so tc_gen_reloc will reject it. */
20202 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20205 _("undefined symbol %s used as an immediate value"),
20206 S_GET_NAME (fixP
->fx_addsy
));
20210 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20212 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20215 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20216 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20218 newimm
= encode_thumb32_immediate (value
);
20219 if (newimm
== (unsigned int) FAIL
)
20220 newimm
= thumb32_negate_data_op (&newval
, value
);
20222 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20223 && newimm
== (unsigned int) FAIL
)
20225 /* Turn add/sum into addw/subw. */
20226 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20227 newval
= (newval
& 0xfeffffff) | 0x02000000;
20229 /* 12 bit immediate for addw/subw. */
20233 newval
^= 0x00a00000;
20236 newimm
= (unsigned int) FAIL
;
20241 if (newimm
== (unsigned int)FAIL
)
20243 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20244 _("invalid constant (%lx) after fixup"),
20245 (unsigned long) value
);
20249 newval
|= (newimm
& 0x800) << 15;
20250 newval
|= (newimm
& 0x700) << 4;
20251 newval
|= (newimm
& 0x0ff);
20253 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20254 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20257 case BFD_RELOC_ARM_SMC
:
20258 if (((unsigned long) value
) > 0xffff)
20259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20260 _("invalid smc expression"));
20261 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20262 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20263 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20266 case BFD_RELOC_ARM_SWI
:
20267 if (fixP
->tc_fix_data
!= 0)
20269 if (((unsigned long) value
) > 0xff)
20270 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20271 _("invalid swi expression"));
20272 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20274 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20278 if (((unsigned long) value
) > 0x00ffffff)
20279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20280 _("invalid swi expression"));
20281 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20283 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20287 case BFD_RELOC_ARM_MULTI
:
20288 if (((unsigned long) value
) > 0xffff)
20289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20290 _("invalid expression in load/store multiple"));
20291 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20292 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20296 case BFD_RELOC_ARM_PCREL_CALL
:
20298 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20300 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20301 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20302 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20303 /* Flip the bl to blx. This is a simple flip
20304 bit here because we generate PCREL_CALL for
20305 unconditional bls. */
20307 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20308 newval
= newval
| 0x10000000;
20309 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20315 goto arm_branch_common
;
20317 case BFD_RELOC_ARM_PCREL_JUMP
:
20318 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20320 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20321 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20322 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20324 /* This would map to a bl<cond>, b<cond>,
20325 b<always> to a Thumb function. We
20326 need to force a relocation for this particular
20328 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20332 case BFD_RELOC_ARM_PLT32
:
20334 case BFD_RELOC_ARM_PCREL_BRANCH
:
20336 goto arm_branch_common
;
20338 case BFD_RELOC_ARM_PCREL_BLX
:
20341 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20343 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20344 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20345 && ARM_IS_FUNC (fixP
->fx_addsy
))
20347 /* Flip the blx to a bl and warn. */
20348 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20349 newval
= 0xeb000000;
20350 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20351 _("blx to '%s' an ARM ISA state function changed to bl"),
20353 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20359 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20360 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20364 /* We are going to store value (shifted right by two) in the
20365 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20366 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20367 also be be clear. */
20369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20370 _("misaligned branch destination"));
20371 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20372 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20373 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20374 _("branch out of range"));
20376 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20378 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20379 newval
|= (value
>> 2) & 0x00ffffff;
20380 /* Set the H bit on BLX instructions. */
20384 newval
|= 0x01000000;
20386 newval
&= ~0x01000000;
20388 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20392 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20393 /* CBZ can only branch forward. */
20395 /* Attempts to use CBZ to branch to the next instruction
20396 (which, strictly speaking, are prohibited) will be turned into
20399 FIXME: It may be better to remove the instruction completely and
20400 perform relaxation. */
20403 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20404 newval
= 0xbf00; /* NOP encoding T1 */
20405 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20411 _("branch out of range"));
20413 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20415 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20416 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20417 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20422 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20423 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20425 _("branch out of range"));
20427 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20429 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20430 newval
|= (value
& 0x1ff) >> 1;
20431 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20435 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20436 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20438 _("branch out of range"));
20440 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20442 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20443 newval
|= (value
& 0xfff) >> 1;
20444 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20448 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20450 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20451 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20452 && S_IS_DEFINED (fixP
->fx_addsy
)
20453 && ARM_IS_FUNC (fixP
->fx_addsy
)
20454 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20456 /* Force a relocation for a branch 20 bits wide. */
20459 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20461 _("conditional branch out of range"));
20463 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20466 addressT S
, J1
, J2
, lo
, hi
;
20468 S
= (value
& 0x00100000) >> 20;
20469 J2
= (value
& 0x00080000) >> 19;
20470 J1
= (value
& 0x00040000) >> 18;
20471 hi
= (value
& 0x0003f000) >> 12;
20472 lo
= (value
& 0x00000ffe) >> 1;
20474 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20475 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20476 newval
|= (S
<< 10) | hi
;
20477 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20478 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20479 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20483 case BFD_RELOC_THUMB_PCREL_BLX
:
20485 /* If there is a blx from a thumb state function to
20486 another thumb function flip this to a bl and warn
20490 && S_IS_DEFINED (fixP
->fx_addsy
)
20491 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20492 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20493 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20495 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20496 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20497 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20499 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20500 newval
= newval
| 0x1000;
20501 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20502 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20507 goto thumb_bl_common
;
20509 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20511 /* A bl from Thumb state ISA to an internal ARM state function
20512 is converted to a blx. */
20514 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20515 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20516 && S_IS_DEFINED (fixP
->fx_addsy
)
20517 && ARM_IS_FUNC (fixP
->fx_addsy
)
20518 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20520 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20521 newval
= newval
& ~0x1000;
20522 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20523 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20530 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20531 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20532 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20535 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20536 /* For a BLX instruction, make sure that the relocation is rounded up
20537 to a word boundary. This follows the semantics of the instruction
20538 which specifies that bit 1 of the target address will come from bit
20539 1 of the base address. */
20540 value
= (value
+ 1) & ~ 1;
20543 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20545 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20547 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20548 _("branch out of range"));
20550 else if ((value
& ~0x1ffffff)
20551 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20554 _("Thumb2 branch out of range"));
20558 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20559 encode_thumb2_b_bl_offset (buf
, value
);
20563 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20564 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20566 _("branch out of range"));
20568 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20569 encode_thumb2_b_bl_offset (buf
, value
);
20574 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20575 md_number_to_chars (buf
, value
, 1);
20579 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20580 md_number_to_chars (buf
, value
, 2);
20584 case BFD_RELOC_ARM_TLS_GD32
:
20585 case BFD_RELOC_ARM_TLS_LE32
:
20586 case BFD_RELOC_ARM_TLS_IE32
:
20587 case BFD_RELOC_ARM_TLS_LDM32
:
20588 case BFD_RELOC_ARM_TLS_LDO32
:
20589 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20592 case BFD_RELOC_ARM_GOT32
:
20593 case BFD_RELOC_ARM_GOTOFF
:
20594 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20595 md_number_to_chars (buf
, 0, 4);
20598 case BFD_RELOC_ARM_GOT_PREL
:
20599 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20600 md_number_to_chars (buf
, value
, 4);
20603 case BFD_RELOC_ARM_TARGET2
:
20604 /* TARGET2 is not partial-inplace, so we need to write the
20605 addend here for REL targets, because it won't be written out
20606 during reloc processing later. */
20607 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20608 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20612 case BFD_RELOC_RVA
:
20614 case BFD_RELOC_ARM_TARGET1
:
20615 case BFD_RELOC_ARM_ROSEGREL32
:
20616 case BFD_RELOC_ARM_SBREL32
:
20617 case BFD_RELOC_32_PCREL
:
20619 case BFD_RELOC_32_SECREL
:
20621 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20623 /* For WinCE we only do this for pcrel fixups. */
20624 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20626 md_number_to_chars (buf
, value
, 4);
20630 case BFD_RELOC_ARM_PREL31
:
20631 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20633 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20634 if ((value
^ (value
>> 1)) & 0x40000000)
20636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20637 _("rel31 relocation overflow"));
20639 newval
|= value
& 0x7fffffff;
20640 md_number_to_chars (buf
, newval
, 4);
20645 case BFD_RELOC_ARM_CP_OFF_IMM
:
20646 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20647 if (value
< -1023 || value
> 1023 || (value
& 3))
20648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20649 _("co-processor offset out of range"));
20654 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20655 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20656 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20658 newval
= get_thumb32_insn (buf
);
20659 newval
&= 0xff7fff00;
20660 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20661 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20662 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20663 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20665 put_thumb32_insn (buf
, newval
);
20668 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20669 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20670 if (value
< -255 || value
> 255)
20671 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20672 _("co-processor offset out of range"));
20674 goto cp_off_common
;
20676 case BFD_RELOC_ARM_THUMB_OFFSET
:
20677 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20678 /* Exactly what ranges, and where the offset is inserted depends
20679 on the type of instruction, we can establish this from the
20681 switch (newval
>> 12)
20683 case 4: /* PC load. */
20684 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20685 forced to zero for these loads; md_pcrel_from has already
20686 compensated for this. */
20688 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20689 _("invalid offset, target not word aligned (0x%08lX)"),
20690 (((unsigned long) fixP
->fx_frag
->fr_address
20691 + (unsigned long) fixP
->fx_where
) & ~3)
20692 + (unsigned long) value
);
20694 if (value
& ~0x3fc)
20695 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20696 _("invalid offset, value too big (0x%08lX)"),
20699 newval
|= value
>> 2;
20702 case 9: /* SP load/store. */
20703 if (value
& ~0x3fc)
20704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20705 _("invalid offset, value too big (0x%08lX)"),
20707 newval
|= value
>> 2;
20710 case 6: /* Word load/store. */
20712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20713 _("invalid offset, value too big (0x%08lX)"),
20715 newval
|= value
<< 4; /* 6 - 2. */
20718 case 7: /* Byte load/store. */
20720 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20721 _("invalid offset, value too big (0x%08lX)"),
20723 newval
|= value
<< 6;
20726 case 8: /* Halfword load/store. */
20728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20729 _("invalid offset, value too big (0x%08lX)"),
20731 newval
|= value
<< 5; /* 6 - 1. */
20735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20736 "Unable to process relocation for thumb opcode: %lx",
20737 (unsigned long) newval
);
20740 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20743 case BFD_RELOC_ARM_THUMB_ADD
:
20744 /* This is a complicated relocation, since we use it for all of
20745 the following immediate relocations:
20749 9bit ADD/SUB SP word-aligned
20750 10bit ADD PC/SP word-aligned
20752 The type of instruction being processed is encoded in the
20759 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20761 int rd
= (newval
>> 4) & 0xf;
20762 int rs
= newval
& 0xf;
20763 int subtract
= !!(newval
& 0x8000);
20765 /* Check for HI regs, only very restricted cases allowed:
20766 Adjusting SP, and using PC or SP to get an address. */
20767 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20768 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20770 _("invalid Hi register with immediate"));
20772 /* If value is negative, choose the opposite instruction. */
20776 subtract
= !subtract
;
20778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20779 _("immediate value out of range"));
20784 if (value
& ~0x1fc)
20785 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20786 _("invalid immediate for stack address calculation"));
20787 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20788 newval
|= value
>> 2;
20790 else if (rs
== REG_PC
|| rs
== REG_SP
)
20792 if (subtract
|| value
& ~0x3fc)
20793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20794 _("invalid immediate for address calculation (value = 0x%08lX)"),
20795 (unsigned long) value
);
20796 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20798 newval
|= value
>> 2;
20803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20804 _("immediate value out of range"));
20805 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20806 newval
|= (rd
<< 8) | value
;
20811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20812 _("immediate value out of range"));
20813 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20814 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20817 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20820 case BFD_RELOC_ARM_THUMB_IMM
:
20821 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20822 if (value
< 0 || value
> 255)
20823 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20824 _("invalid immediate: %ld is out of range"),
20827 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20830 case BFD_RELOC_ARM_THUMB_SHIFT
:
20831 /* 5bit shift value (0..32). LSL cannot take 32. */
20832 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20833 temp
= newval
& 0xf800;
20834 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20836 _("invalid shift value: %ld"), (long) value
);
20837 /* Shifts of zero must be encoded as LSL. */
20839 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20840 /* Shifts of 32 are encoded as zero. */
20841 else if (value
== 32)
20843 newval
|= value
<< 6;
20844 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20847 case BFD_RELOC_VTABLE_INHERIT
:
20848 case BFD_RELOC_VTABLE_ENTRY
:
20852 case BFD_RELOC_ARM_MOVW
:
20853 case BFD_RELOC_ARM_MOVT
:
20854 case BFD_RELOC_ARM_THUMB_MOVW
:
20855 case BFD_RELOC_ARM_THUMB_MOVT
:
20856 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20858 /* REL format relocations are limited to a 16-bit addend. */
20859 if (!fixP
->fx_done
)
20861 if (value
< -0x8000 || value
> 0x7fff)
20862 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20863 _("offset out of range"));
20865 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20866 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20871 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20872 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20874 newval
= get_thumb32_insn (buf
);
20875 newval
&= 0xfbf08f00;
20876 newval
|= (value
& 0xf000) << 4;
20877 newval
|= (value
& 0x0800) << 15;
20878 newval
|= (value
& 0x0700) << 4;
20879 newval
|= (value
& 0x00ff);
20880 put_thumb32_insn (buf
, newval
);
20884 newval
= md_chars_to_number (buf
, 4);
20885 newval
&= 0xfff0f000;
20886 newval
|= value
& 0x0fff;
20887 newval
|= (value
& 0xf000) << 4;
20888 md_number_to_chars (buf
, newval
, 4);
20893 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20894 case BFD_RELOC_ARM_ALU_PC_G0
:
20895 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20896 case BFD_RELOC_ARM_ALU_PC_G1
:
20897 case BFD_RELOC_ARM_ALU_PC_G2
:
20898 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20899 case BFD_RELOC_ARM_ALU_SB_G0
:
20900 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20901 case BFD_RELOC_ARM_ALU_SB_G1
:
20902 case BFD_RELOC_ARM_ALU_SB_G2
:
20903 gas_assert (!fixP
->fx_done
);
20904 if (!seg
->use_rela_p
)
20907 bfd_vma encoded_addend
;
20908 bfd_vma addend_abs
= abs (value
);
20910 /* Check that the absolute value of the addend can be
20911 expressed as an 8-bit constant plus a rotation. */
20912 encoded_addend
= encode_arm_immediate (addend_abs
);
20913 if (encoded_addend
== (unsigned int) FAIL
)
20914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20915 _("the offset 0x%08lX is not representable"),
20916 (unsigned long) addend_abs
);
20918 /* Extract the instruction. */
20919 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20921 /* If the addend is positive, use an ADD instruction.
20922 Otherwise use a SUB. Take care not to destroy the S bit. */
20923 insn
&= 0xff1fffff;
20929 /* Place the encoded addend into the first 12 bits of the
20931 insn
&= 0xfffff000;
20932 insn
|= encoded_addend
;
20934 /* Update the instruction. */
20935 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20939 case BFD_RELOC_ARM_LDR_PC_G0
:
20940 case BFD_RELOC_ARM_LDR_PC_G1
:
20941 case BFD_RELOC_ARM_LDR_PC_G2
:
20942 case BFD_RELOC_ARM_LDR_SB_G0
:
20943 case BFD_RELOC_ARM_LDR_SB_G1
:
20944 case BFD_RELOC_ARM_LDR_SB_G2
:
20945 gas_assert (!fixP
->fx_done
);
20946 if (!seg
->use_rela_p
)
20949 bfd_vma addend_abs
= abs (value
);
20951 /* Check that the absolute value of the addend can be
20952 encoded in 12 bits. */
20953 if (addend_abs
>= 0x1000)
20954 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20955 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20956 (unsigned long) addend_abs
);
20958 /* Extract the instruction. */
20959 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20961 /* If the addend is negative, clear bit 23 of the instruction.
20962 Otherwise set it. */
20964 insn
&= ~(1 << 23);
20968 /* Place the absolute value of the addend into the first 12 bits
20969 of the instruction. */
20970 insn
&= 0xfffff000;
20971 insn
|= addend_abs
;
20973 /* Update the instruction. */
20974 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20978 case BFD_RELOC_ARM_LDRS_PC_G0
:
20979 case BFD_RELOC_ARM_LDRS_PC_G1
:
20980 case BFD_RELOC_ARM_LDRS_PC_G2
:
20981 case BFD_RELOC_ARM_LDRS_SB_G0
:
20982 case BFD_RELOC_ARM_LDRS_SB_G1
:
20983 case BFD_RELOC_ARM_LDRS_SB_G2
:
20984 gas_assert (!fixP
->fx_done
);
20985 if (!seg
->use_rela_p
)
20988 bfd_vma addend_abs
= abs (value
);
20990 /* Check that the absolute value of the addend can be
20991 encoded in 8 bits. */
20992 if (addend_abs
>= 0x100)
20993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20994 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
20995 (unsigned long) addend_abs
);
20997 /* Extract the instruction. */
20998 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21000 /* If the addend is negative, clear bit 23 of the instruction.
21001 Otherwise set it. */
21003 insn
&= ~(1 << 23);
21007 /* Place the first four bits of the absolute value of the addend
21008 into the first 4 bits of the instruction, and the remaining
21009 four into bits 8 .. 11. */
21010 insn
&= 0xfffff0f0;
21011 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21013 /* Update the instruction. */
21014 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21018 case BFD_RELOC_ARM_LDC_PC_G0
:
21019 case BFD_RELOC_ARM_LDC_PC_G1
:
21020 case BFD_RELOC_ARM_LDC_PC_G2
:
21021 case BFD_RELOC_ARM_LDC_SB_G0
:
21022 case BFD_RELOC_ARM_LDC_SB_G1
:
21023 case BFD_RELOC_ARM_LDC_SB_G2
:
21024 gas_assert (!fixP
->fx_done
);
21025 if (!seg
->use_rela_p
)
21028 bfd_vma addend_abs
= abs (value
);
21030 /* Check that the absolute value of the addend is a multiple of
21031 four and, when divided by four, fits in 8 bits. */
21032 if (addend_abs
& 0x3)
21033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21034 _("bad offset 0x%08lX (must be word-aligned)"),
21035 (unsigned long) addend_abs
);
21037 if ((addend_abs
>> 2) > 0xff)
21038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21039 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21040 (unsigned long) addend_abs
);
21042 /* Extract the instruction. */
21043 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21045 /* If the addend is negative, clear bit 23 of the instruction.
21046 Otherwise set it. */
21048 insn
&= ~(1 << 23);
21052 /* Place the addend (divided by four) into the first eight
21053 bits of the instruction. */
21054 insn
&= 0xfffffff0;
21055 insn
|= addend_abs
>> 2;
21057 /* Update the instruction. */
21058 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21062 case BFD_RELOC_ARM_V4BX
:
21063 /* This will need to go in the object file. */
21067 case BFD_RELOC_UNUSED
:
21069 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21070 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21074 /* Translate internal representation of relocation info to BFD target
21078 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21081 bfd_reloc_code_real_type code
;
21083 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21085 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21086 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21087 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21089 if (fixp
->fx_pcrel
)
21091 if (section
->use_rela_p
)
21092 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21094 fixp
->fx_offset
= reloc
->address
;
21096 reloc
->addend
= fixp
->fx_offset
;
21098 switch (fixp
->fx_r_type
)
21101 if (fixp
->fx_pcrel
)
21103 code
= BFD_RELOC_8_PCREL
;
21108 if (fixp
->fx_pcrel
)
21110 code
= BFD_RELOC_16_PCREL
;
21115 if (fixp
->fx_pcrel
)
21117 code
= BFD_RELOC_32_PCREL
;
21121 case BFD_RELOC_ARM_MOVW
:
21122 if (fixp
->fx_pcrel
)
21124 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21128 case BFD_RELOC_ARM_MOVT
:
21129 if (fixp
->fx_pcrel
)
21131 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21135 case BFD_RELOC_ARM_THUMB_MOVW
:
21136 if (fixp
->fx_pcrel
)
21138 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21142 case BFD_RELOC_ARM_THUMB_MOVT
:
21143 if (fixp
->fx_pcrel
)
21145 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21149 case BFD_RELOC_NONE
:
21150 case BFD_RELOC_ARM_PCREL_BRANCH
:
21151 case BFD_RELOC_ARM_PCREL_BLX
:
21152 case BFD_RELOC_RVA
:
21153 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21154 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21155 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21156 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21157 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21158 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21159 case BFD_RELOC_VTABLE_ENTRY
:
21160 case BFD_RELOC_VTABLE_INHERIT
:
21162 case BFD_RELOC_32_SECREL
:
21164 code
= fixp
->fx_r_type
;
21167 case BFD_RELOC_THUMB_PCREL_BLX
:
21169 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21170 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21173 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21176 case BFD_RELOC_ARM_LITERAL
:
21177 case BFD_RELOC_ARM_HWLITERAL
:
21178 /* If this is called then the a literal has
21179 been referenced across a section boundary. */
21180 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21181 _("literal referenced across section boundary"));
21185 case BFD_RELOC_ARM_GOT32
:
21186 case BFD_RELOC_ARM_GOTOFF
:
21187 case BFD_RELOC_ARM_GOT_PREL
:
21188 case BFD_RELOC_ARM_PLT32
:
21189 case BFD_RELOC_ARM_TARGET1
:
21190 case BFD_RELOC_ARM_ROSEGREL32
:
21191 case BFD_RELOC_ARM_SBREL32
:
21192 case BFD_RELOC_ARM_PREL31
:
21193 case BFD_RELOC_ARM_TARGET2
:
21194 case BFD_RELOC_ARM_TLS_LE32
:
21195 case BFD_RELOC_ARM_TLS_LDO32
:
21196 case BFD_RELOC_ARM_PCREL_CALL
:
21197 case BFD_RELOC_ARM_PCREL_JUMP
:
21198 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21199 case BFD_RELOC_ARM_ALU_PC_G0
:
21200 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21201 case BFD_RELOC_ARM_ALU_PC_G1
:
21202 case BFD_RELOC_ARM_ALU_PC_G2
:
21203 case BFD_RELOC_ARM_LDR_PC_G0
:
21204 case BFD_RELOC_ARM_LDR_PC_G1
:
21205 case BFD_RELOC_ARM_LDR_PC_G2
:
21206 case BFD_RELOC_ARM_LDRS_PC_G0
:
21207 case BFD_RELOC_ARM_LDRS_PC_G1
:
21208 case BFD_RELOC_ARM_LDRS_PC_G2
:
21209 case BFD_RELOC_ARM_LDC_PC_G0
:
21210 case BFD_RELOC_ARM_LDC_PC_G1
:
21211 case BFD_RELOC_ARM_LDC_PC_G2
:
21212 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21213 case BFD_RELOC_ARM_ALU_SB_G0
:
21214 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21215 case BFD_RELOC_ARM_ALU_SB_G1
:
21216 case BFD_RELOC_ARM_ALU_SB_G2
:
21217 case BFD_RELOC_ARM_LDR_SB_G0
:
21218 case BFD_RELOC_ARM_LDR_SB_G1
:
21219 case BFD_RELOC_ARM_LDR_SB_G2
:
21220 case BFD_RELOC_ARM_LDRS_SB_G0
:
21221 case BFD_RELOC_ARM_LDRS_SB_G1
:
21222 case BFD_RELOC_ARM_LDRS_SB_G2
:
21223 case BFD_RELOC_ARM_LDC_SB_G0
:
21224 case BFD_RELOC_ARM_LDC_SB_G1
:
21225 case BFD_RELOC_ARM_LDC_SB_G2
:
21226 case BFD_RELOC_ARM_V4BX
:
21227 code
= fixp
->fx_r_type
;
21230 case BFD_RELOC_ARM_TLS_GD32
:
21231 case BFD_RELOC_ARM_TLS_IE32
:
21232 case BFD_RELOC_ARM_TLS_LDM32
:
21233 /* BFD will include the symbol's address in the addend.
21234 But we don't want that, so subtract it out again here. */
21235 if (!S_IS_COMMON (fixp
->fx_addsy
))
21236 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21237 code
= fixp
->fx_r_type
;
21241 case BFD_RELOC_ARM_IMMEDIATE
:
21242 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21243 _("internal relocation (type: IMMEDIATE) not fixed up"));
21246 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21247 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21248 _("ADRL used for a symbol not defined in the same file"));
21251 case BFD_RELOC_ARM_OFFSET_IMM
:
21252 if (section
->use_rela_p
)
21254 code
= fixp
->fx_r_type
;
21258 if (fixp
->fx_addsy
!= NULL
21259 && !S_IS_DEFINED (fixp
->fx_addsy
)
21260 && S_IS_LOCAL (fixp
->fx_addsy
))
21262 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21263 _("undefined local label `%s'"),
21264 S_GET_NAME (fixp
->fx_addsy
));
21268 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21269 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21276 switch (fixp
->fx_r_type
)
21278 case BFD_RELOC_NONE
: type
= "NONE"; break;
21279 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21280 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21281 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21282 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21283 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21284 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21285 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21286 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21287 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21288 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21289 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21290 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21291 default: type
= _("<unknown>"); break;
21293 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21294 _("cannot represent %s relocation in this object file format"),
21301 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21303 && fixp
->fx_addsy
== GOT_symbol
)
21305 code
= BFD_RELOC_ARM_GOTPC
;
21306 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21310 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21312 if (reloc
->howto
== NULL
)
21314 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21315 _("cannot represent %s relocation in this object file format"),
21316 bfd_get_reloc_code_name (code
));
21320 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21321 vtable entry to be used in the relocation's section offset. */
21322 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21323 reloc
->address
= fixp
->fx_offset
;
21328 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21331 cons_fix_new_arm (fragS
* frag
,
21336 bfd_reloc_code_real_type type
;
21340 FIXME: @@ Should look at CPU word size. */
21344 type
= BFD_RELOC_8
;
21347 type
= BFD_RELOC_16
;
21351 type
= BFD_RELOC_32
;
21354 type
= BFD_RELOC_64
;
21359 if (exp
->X_op
== O_secrel
)
21361 exp
->X_op
= O_symbol
;
21362 type
= BFD_RELOC_32_SECREL
;
21366 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21369 #if defined (OBJ_COFF)
21371 arm_validate_fix (fixS
* fixP
)
21373 /* If the destination of the branch is a defined symbol which does not have
21374 the THUMB_FUNC attribute, then we must be calling a function which has
21375 the (interfacearm) attribute. We look for the Thumb entry point to that
21376 function and change the branch to refer to that function instead. */
21377 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21378 && fixP
->fx_addsy
!= NULL
21379 && S_IS_DEFINED (fixP
->fx_addsy
)
21380 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21382 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21389 arm_force_relocation (struct fix
* fixp
)
21391 #if defined (OBJ_COFF) && defined (TE_PE)
21392 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21396 /* In case we have a call or a branch to a function in ARM ISA mode from
21397 a thumb function or vice-versa force the relocation. These relocations
21398 are cleared off for some cores that might have blx and simple transformations
21402 switch (fixp
->fx_r_type
)
21404 case BFD_RELOC_ARM_PCREL_JUMP
:
21405 case BFD_RELOC_ARM_PCREL_CALL
:
21406 case BFD_RELOC_THUMB_PCREL_BLX
:
21407 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21411 case BFD_RELOC_ARM_PCREL_BLX
:
21412 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21413 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21414 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21415 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21424 /* Resolve these relocations even if the symbol is extern or weak. */
21425 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21426 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21427 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21428 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21429 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21430 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21431 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21434 /* Always leave these relocations for the linker. */
21435 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21436 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21437 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21440 /* Always generate relocations against function symbols. */
21441 if (fixp
->fx_r_type
== BFD_RELOC_32
21443 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21446 return generic_force_reloc (fixp
);
21449 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21450 /* Relocations against function names must be left unadjusted,
21451 so that the linker can use this information to generate interworking
21452 stubs. The MIPS version of this function
21453 also prevents relocations that are mips-16 specific, but I do not
21454 know why it does this.
21457 There is one other problem that ought to be addressed here, but
21458 which currently is not: Taking the address of a label (rather
21459 than a function) and then later jumping to that address. Such
21460 addresses also ought to have their bottom bit set (assuming that
21461 they reside in Thumb code), but at the moment they will not. */
21464 arm_fix_adjustable (fixS
* fixP
)
21466 if (fixP
->fx_addsy
== NULL
)
21469 /* Preserve relocations against symbols with function type. */
21470 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21473 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21474 && fixP
->fx_subsy
== NULL
)
21477 /* We need the symbol name for the VTABLE entries. */
21478 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21479 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21482 /* Don't allow symbols to be discarded on GOT related relocs. */
21483 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21484 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21485 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21486 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21487 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21488 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21489 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21490 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21491 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21494 /* Similarly for group relocations. */
21495 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21496 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21497 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21500 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21501 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21502 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21503 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21504 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21505 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21506 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21507 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21508 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21513 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21518 elf32_arm_target_format (void)
21521 return (target_big_endian
21522 ? "elf32-bigarm-symbian"
21523 : "elf32-littlearm-symbian");
21524 #elif defined (TE_VXWORKS)
21525 return (target_big_endian
21526 ? "elf32-bigarm-vxworks"
21527 : "elf32-littlearm-vxworks");
21529 if (target_big_endian
)
21530 return "elf32-bigarm";
21532 return "elf32-littlearm";
21537 armelf_frob_symbol (symbolS
* symp
,
21540 elf_frob_symbol (symp
, puntp
);
21544 /* MD interface: Finalization. */
21549 literal_pool
* pool
;
21551 /* Ensure that all the IT blocks are properly closed. */
21552 check_it_blocks_finished ();
21554 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21556 /* Put it at the end of the relevant section. */
21557 subseg_set (pool
->section
, pool
->sub_section
);
21559 arm_elf_change_section ();
21566 /* Remove any excess mapping symbols generated for alignment frags in
21567 SEC. We may have created a mapping symbol before a zero byte
21568 alignment; remove it if there's a mapping symbol after the
21571 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21572 void *dummy ATTRIBUTE_UNUSED
)
21574 segment_info_type
*seginfo
= seg_info (sec
);
21577 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21580 for (fragp
= seginfo
->frchainP
->frch_root
;
21582 fragp
= fragp
->fr_next
)
21584 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21585 fragS
*next
= fragp
->fr_next
;
21587 /* Variable-sized frags have been converted to fixed size by
21588 this point. But if this was variable-sized to start with,
21589 there will be a fixed-size frag after it. So don't handle
21591 if (sym
== NULL
|| next
== NULL
)
21594 if (S_GET_VALUE (sym
) < next
->fr_address
)
21595 /* Not at the end of this frag. */
21597 know (S_GET_VALUE (sym
) == next
->fr_address
);
21601 if (next
->tc_frag_data
.first_map
!= NULL
)
21603 /* Next frag starts with a mapping symbol. Discard this
21605 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21609 if (next
->fr_next
== NULL
)
21611 /* This mapping symbol is at the end of the section. Discard
21613 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21614 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21618 /* As long as we have empty frags without any mapping symbols,
21620 /* If the next frag is non-empty and does not start with a
21621 mapping symbol, then this mapping symbol is required. */
21622 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21625 next
= next
->fr_next
;
21627 while (next
!= NULL
);
21632 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21636 arm_adjust_symtab (void)
21641 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21643 if (ARM_IS_THUMB (sym
))
21645 if (THUMB_IS_FUNC (sym
))
21647 /* Mark the symbol as a Thumb function. */
21648 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21649 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21650 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21652 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21653 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21655 as_bad (_("%s: unexpected function type: %d"),
21656 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21658 else switch (S_GET_STORAGE_CLASS (sym
))
21661 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21664 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21667 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21675 if (ARM_IS_INTERWORK (sym
))
21676 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21683 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21685 if (ARM_IS_THUMB (sym
))
21687 elf_symbol_type
* elf_sym
;
21689 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21690 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21692 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21693 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21695 /* If it's a .thumb_func, declare it as so,
21696 otherwise tag label as .code 16. */
21697 if (THUMB_IS_FUNC (sym
))
21698 elf_sym
->internal_elf_sym
.st_info
=
21699 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21700 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21701 elf_sym
->internal_elf_sym
.st_info
=
21702 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21707 /* Remove any overlapping mapping symbols generated by alignment frags. */
21708 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21712 /* MD interface: Initialization. */
21715 set_constant_flonums (void)
21719 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21720 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21724 /* Auto-select Thumb mode if it's the only available instruction set for the
21725 given architecture. */
21728 autoselect_thumb_from_cpu_variant (void)
21730 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21731 opcode_select (16);
21740 if ( (arm_ops_hsh
= hash_new ()) == NULL
21741 || (arm_cond_hsh
= hash_new ()) == NULL
21742 || (arm_shift_hsh
= hash_new ()) == NULL
21743 || (arm_psr_hsh
= hash_new ()) == NULL
21744 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21745 || (arm_reg_hsh
= hash_new ()) == NULL
21746 || (arm_reloc_hsh
= hash_new ()) == NULL
21747 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21748 as_fatal (_("virtual memory exhausted"));
21750 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21751 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21752 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21753 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21754 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21755 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21756 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21757 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21758 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21759 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21760 (void *) (v7m_psrs
+ i
));
21761 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21762 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21764 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21766 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21767 (void *) (barrier_opt_names
+ i
));
21769 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21770 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21773 set_constant_flonums ();
21775 /* Set the cpu variant based on the command-line options. We prefer
21776 -mcpu= over -march= if both are set (as for GCC); and we prefer
21777 -mfpu= over any other way of setting the floating point unit.
21778 Use of legacy options with new options are faulted. */
21781 if (mcpu_cpu_opt
|| march_cpu_opt
)
21782 as_bad (_("use of old and new-style options to set CPU type"));
21784 mcpu_cpu_opt
= legacy_cpu
;
21786 else if (!mcpu_cpu_opt
)
21787 mcpu_cpu_opt
= march_cpu_opt
;
21792 as_bad (_("use of old and new-style options to set FPU type"));
21794 mfpu_opt
= legacy_fpu
;
21796 else if (!mfpu_opt
)
21798 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21799 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21800 /* Some environments specify a default FPU. If they don't, infer it
21801 from the processor. */
21803 mfpu_opt
= mcpu_fpu_opt
;
21805 mfpu_opt
= march_fpu_opt
;
21807 mfpu_opt
= &fpu_default
;
21813 if (mcpu_cpu_opt
!= NULL
)
21814 mfpu_opt
= &fpu_default
;
21815 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21816 mfpu_opt
= &fpu_arch_vfp_v2
;
21818 mfpu_opt
= &fpu_arch_fpa
;
21824 mcpu_cpu_opt
= &cpu_default
;
21825 selected_cpu
= cpu_default
;
21829 selected_cpu
= *mcpu_cpu_opt
;
21831 mcpu_cpu_opt
= &arm_arch_any
;
21834 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21836 autoselect_thumb_from_cpu_variant ();
21838 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21840 #if defined OBJ_COFF || defined OBJ_ELF
21842 unsigned int flags
= 0;
21844 #if defined OBJ_ELF
21845 flags
= meabi_flags
;
21847 switch (meabi_flags
)
21849 case EF_ARM_EABI_UNKNOWN
:
21851 /* Set the flags in the private structure. */
21852 if (uses_apcs_26
) flags
|= F_APCS26
;
21853 if (support_interwork
) flags
|= F_INTERWORK
;
21854 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21855 if (pic_code
) flags
|= F_PIC
;
21856 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21857 flags
|= F_SOFT_FLOAT
;
21859 switch (mfloat_abi_opt
)
21861 case ARM_FLOAT_ABI_SOFT
:
21862 case ARM_FLOAT_ABI_SOFTFP
:
21863 flags
|= F_SOFT_FLOAT
;
21866 case ARM_FLOAT_ABI_HARD
:
21867 if (flags
& F_SOFT_FLOAT
)
21868 as_bad (_("hard-float conflicts with specified fpu"));
21872 /* Using pure-endian doubles (even if soft-float). */
21873 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21874 flags
|= F_VFP_FLOAT
;
21876 #if defined OBJ_ELF
21877 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21878 flags
|= EF_ARM_MAVERICK_FLOAT
;
21881 case EF_ARM_EABI_VER4
:
21882 case EF_ARM_EABI_VER5
:
21883 /* No additional flags to set. */
21890 bfd_set_private_flags (stdoutput
, flags
);
21892 /* We have run out flags in the COFF header to encode the
21893 status of ATPCS support, so instead we create a dummy,
21894 empty, debug section called .arm.atpcs. */
21899 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21903 bfd_set_section_flags
21904 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21905 bfd_set_section_size (stdoutput
, sec
, 0);
21906 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21912 /* Record the CPU type as well. */
21913 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21914 mach
= bfd_mach_arm_iWMMXt2
;
21915 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21916 mach
= bfd_mach_arm_iWMMXt
;
21917 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21918 mach
= bfd_mach_arm_XScale
;
21919 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21920 mach
= bfd_mach_arm_ep9312
;
21921 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21922 mach
= bfd_mach_arm_5TE
;
21923 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21925 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21926 mach
= bfd_mach_arm_5T
;
21928 mach
= bfd_mach_arm_5
;
21930 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21932 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21933 mach
= bfd_mach_arm_4T
;
21935 mach
= bfd_mach_arm_4
;
21937 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21938 mach
= bfd_mach_arm_3M
;
21939 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21940 mach
= bfd_mach_arm_3
;
21941 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21942 mach
= bfd_mach_arm_2a
;
21943 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21944 mach
= bfd_mach_arm_2
;
21946 mach
= bfd_mach_arm_unknown
;
21948 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21951 /* Command line processing. */
21954 Invocation line includes a switch not recognized by the base assembler.
21955 See if it's a processor-specific option.
21957 This routine is somewhat complicated by the need for backwards
21958 compatibility (since older releases of gcc can't be changed).
21959 The new options try to make the interface as compatible as
21962 New options (supported) are:
21964 -mcpu=<cpu name> Assemble for selected processor
21965 -march=<architecture name> Assemble for selected architecture
21966 -mfpu=<fpu architecture> Assemble for selected FPU.
21967 -EB/-mbig-endian Big-endian
21968 -EL/-mlittle-endian Little-endian
21969 -k Generate PIC code
21970 -mthumb Start in Thumb mode
21971 -mthumb-interwork Code supports ARM/Thumb interworking
21973 -m[no-]warn-deprecated Warn about deprecated features
21975 For now we will also provide support for:
21977 -mapcs-32 32-bit Program counter
21978 -mapcs-26 26-bit Program counter
21979 -macps-float Floats passed in FP registers
21980 -mapcs-reentrant Reentrant code
21982 (sometime these will probably be replaced with -mapcs=<list of options>
21983 and -matpcs=<list of options>)
21985 The remaining options are only supported for back-wards compatibility.
21986 Cpu variants, the arm part is optional:
21987 -m[arm]1 Currently not supported.
21988 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21989 -m[arm]3 Arm 3 processor
21990 -m[arm]6[xx], Arm 6 processors
21991 -m[arm]7[xx][t][[d]m] Arm 7 processors
21992 -m[arm]8[10] Arm 8 processors
21993 -m[arm]9[20][tdmi] Arm 9 processors
21994 -mstrongarm[110[0]] StrongARM processors
21995 -mxscale XScale processors
21996 -m[arm]v[2345[t[e]]] Arm architectures
21997 -mall All (except the ARM1)
21999 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22000 -mfpe-old (No float load/store multiples)
22001 -mvfpxd VFP Single precision
22003 -mno-fpu Disable all floating point instructions
22005 The following CPU names are recognized:
22006 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22007 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22008 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22009 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22010 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22011 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22012 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22016 const char * md_shortopts
= "m:k";
22018 #ifdef ARM_BI_ENDIAN
22019 #define OPTION_EB (OPTION_MD_BASE + 0)
22020 #define OPTION_EL (OPTION_MD_BASE + 1)
22022 #if TARGET_BYTES_BIG_ENDIAN
22023 #define OPTION_EB (OPTION_MD_BASE + 0)
22025 #define OPTION_EL (OPTION_MD_BASE + 1)
22028 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22030 struct option md_longopts
[] =
22033 {"EB", no_argument
, NULL
, OPTION_EB
},
22036 {"EL", no_argument
, NULL
, OPTION_EL
},
22038 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22039 {NULL
, no_argument
, NULL
, 0}
22042 size_t md_longopts_size
= sizeof (md_longopts
);
22044 struct arm_option_table
22046 char *option
; /* Option name to match. */
22047 char *help
; /* Help information. */
22048 int *var
; /* Variable to change. */
22049 int value
; /* What to change it to. */
22050 char *deprecated
; /* If non-null, print this message. */
22053 struct arm_option_table arm_opts
[] =
22055 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22056 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22057 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22058 &support_interwork
, 1, NULL
},
22059 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22060 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22061 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22063 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22064 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22065 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22066 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22069 /* These are recognized by the assembler, but have no affect on code. */
22070 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22071 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22073 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22074 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22075 &warn_on_deprecated
, 0, NULL
},
22076 {NULL
, NULL
, NULL
, 0, NULL
}
22079 struct arm_legacy_option_table
22081 char *option
; /* Option name to match. */
22082 const arm_feature_set
**var
; /* Variable to change. */
22083 const arm_feature_set value
; /* What to change it to. */
22084 char *deprecated
; /* If non-null, print this message. */
22087 const struct arm_legacy_option_table arm_legacy_opts
[] =
22089 /* DON'T add any new processors to this list -- we want the whole list
22090 to go away... Add them to the processors table instead. */
22091 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22092 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22093 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22094 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22095 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22096 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22097 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22098 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22099 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22100 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22101 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22102 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22103 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22104 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22105 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22106 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22107 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22108 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22109 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22110 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22111 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22112 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22113 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22114 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22115 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22116 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22117 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22118 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22119 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22120 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22121 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22122 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22123 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22124 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22125 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22126 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22127 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22128 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22129 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22130 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22131 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22132 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22133 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22134 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22135 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22136 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22137 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22138 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22139 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22140 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22141 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22142 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22143 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22144 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22145 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22146 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22147 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22148 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22149 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22150 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22151 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22152 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22153 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22154 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22155 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22156 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22157 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22158 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22159 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22160 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22161 N_("use -mcpu=strongarm110")},
22162 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22163 N_("use -mcpu=strongarm1100")},
22164 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22165 N_("use -mcpu=strongarm1110")},
22166 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22167 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22168 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22170 /* Architecture variants -- don't add any more to this list either. */
22171 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22172 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22173 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22174 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22175 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22176 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22177 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22178 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22179 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22180 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22181 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22182 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22183 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22184 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22185 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22186 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22187 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22188 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22190 /* Floating point variants -- don't add any more to this list either. */
22191 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22192 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22193 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22194 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22195 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22197 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22200 struct arm_cpu_option_table
22203 const arm_feature_set value
;
22204 /* For some CPUs we assume an FPU unless the user explicitly sets
22206 const arm_feature_set default_fpu
;
22207 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22209 const char *canonical_name
;
22212 /* This list should, at a minimum, contain all the cpu names
22213 recognized by GCC. */
22214 static const struct arm_cpu_option_table arm_cpus
[] =
22216 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22217 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22218 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22219 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22220 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22221 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22222 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22223 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22224 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22225 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22226 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22227 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22228 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22229 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22230 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22231 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22232 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22233 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22234 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22235 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22236 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22237 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22238 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22239 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22240 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22241 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22242 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22243 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22244 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22245 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22246 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22247 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22248 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22249 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22250 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22251 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22252 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22253 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22254 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22255 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22256 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22257 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22258 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22259 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22260 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22261 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22262 /* For V5 or later processors we default to using VFP; but the user
22263 should really set the FPU type explicitly. */
22264 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22265 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22266 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22267 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22268 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22269 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22270 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22271 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22272 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22273 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22274 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22275 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22276 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22277 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22278 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22279 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22280 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22281 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22282 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22283 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22284 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22285 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22286 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22287 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22288 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22289 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22290 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22291 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
22292 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
22293 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22294 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22295 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22296 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22297 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
22298 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22299 | FPU_NEON_EXT_V1
),
22301 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22302 | FPU_NEON_EXT_V1
),
22304 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
22305 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
22306 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, NULL
},
22307 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
22308 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22309 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22310 /* ??? XSCALE is really an architecture. */
22311 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22312 /* ??? iwmmxt is not a processor. */
22313 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22314 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22315 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22317 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22318 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22321 struct arm_arch_option_table
22324 const arm_feature_set value
;
22325 const arm_feature_set default_fpu
;
22328 /* This list should, at a minimum, contain all the architecture names
22329 recognized by GCC. */
22330 static const struct arm_arch_option_table arm_archs
[] =
22332 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22333 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22334 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22335 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22336 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22337 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22338 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22339 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22340 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22341 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22342 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22343 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22344 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22345 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22346 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22347 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22348 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22349 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22350 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22351 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22352 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22353 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22354 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22355 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22356 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22357 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22358 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22359 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22360 /* The official spelling of the ARMv7 profile variants is the dashed form.
22361 Accept the non-dashed form for compatibility with old toolchains. */
22362 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22363 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22364 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22365 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22366 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22367 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22368 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22369 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22370 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22371 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22372 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22375 /* ISA extensions in the co-processor space. */
22376 struct arm_option_cpu_value_table
22379 const arm_feature_set value
;
22382 static const struct arm_option_cpu_value_table arm_extensions
[] =
22384 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22385 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22386 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22387 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22388 {NULL
, ARM_ARCH_NONE
}
22391 /* This list should, at a minimum, contain all the fpu names
22392 recognized by GCC. */
22393 static const struct arm_option_cpu_value_table arm_fpus
[] =
22395 {"softfpa", FPU_NONE
},
22396 {"fpe", FPU_ARCH_FPE
},
22397 {"fpe2", FPU_ARCH_FPE
},
22398 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22399 {"fpa", FPU_ARCH_FPA
},
22400 {"fpa10", FPU_ARCH_FPA
},
22401 {"fpa11", FPU_ARCH_FPA
},
22402 {"arm7500fe", FPU_ARCH_FPA
},
22403 {"softvfp", FPU_ARCH_VFP
},
22404 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22405 {"vfp", FPU_ARCH_VFP_V2
},
22406 {"vfp9", FPU_ARCH_VFP_V2
},
22407 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22408 {"vfp10", FPU_ARCH_VFP_V2
},
22409 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22410 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22411 {"vfpv2", FPU_ARCH_VFP_V2
},
22412 {"vfpv3", FPU_ARCH_VFP_V3
},
22413 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22414 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22415 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22416 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22417 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22418 {"arm1020t", FPU_ARCH_VFP_V1
},
22419 {"arm1020e", FPU_ARCH_VFP_V2
},
22420 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22421 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22422 {"maverick", FPU_ARCH_MAVERICK
},
22423 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22424 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22425 {"vfpv4", FPU_ARCH_VFP_V4
},
22426 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22427 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22428 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22429 {NULL
, ARM_ARCH_NONE
}
22432 struct arm_option_value_table
22438 static const struct arm_option_value_table arm_float_abis
[] =
22440 {"hard", ARM_FLOAT_ABI_HARD
},
22441 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22442 {"soft", ARM_FLOAT_ABI_SOFT
},
22447 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22448 static const struct arm_option_value_table arm_eabis
[] =
22450 {"gnu", EF_ARM_EABI_UNKNOWN
},
22451 {"4", EF_ARM_EABI_VER4
},
22452 {"5", EF_ARM_EABI_VER5
},
22457 struct arm_long_option_table
22459 char * option
; /* Substring to match. */
22460 char * help
; /* Help information. */
22461 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22462 char * deprecated
; /* If non-null, print this message. */
22466 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22468 arm_feature_set
*ext_set
= (arm_feature_set
*)
22469 xmalloc (sizeof (arm_feature_set
));
22471 /* Copy the feature set, so that we can modify it. */
22472 *ext_set
= **opt_p
;
22475 while (str
!= NULL
&& *str
!= 0)
22477 const struct arm_option_cpu_value_table
* opt
;
22483 as_bad (_("invalid architectural extension"));
22488 ext
= strchr (str
, '+');
22491 optlen
= ext
- str
;
22493 optlen
= strlen (str
);
22497 as_bad (_("missing architectural extension"));
22501 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22502 if (strncmp (opt
->name
, str
, optlen
) == 0)
22504 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22508 if (opt
->name
== NULL
)
22510 as_bad (_("unknown architectural extension `%s'"), str
);
22521 arm_parse_cpu (char * str
)
22523 const struct arm_cpu_option_table
* opt
;
22524 char * ext
= strchr (str
, '+');
22528 optlen
= ext
- str
;
22530 optlen
= strlen (str
);
22534 as_bad (_("missing cpu name `%s'"), str
);
22538 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22539 if (strncmp (opt
->name
, str
, optlen
) == 0)
22541 mcpu_cpu_opt
= &opt
->value
;
22542 mcpu_fpu_opt
= &opt
->default_fpu
;
22543 if (opt
->canonical_name
)
22544 strcpy (selected_cpu_name
, opt
->canonical_name
);
22549 for (i
= 0; i
< optlen
; i
++)
22550 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22551 selected_cpu_name
[i
] = 0;
22555 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22560 as_bad (_("unknown cpu `%s'"), str
);
22565 arm_parse_arch (char * str
)
22567 const struct arm_arch_option_table
*opt
;
22568 char *ext
= strchr (str
, '+');
22572 optlen
= ext
- str
;
22574 optlen
= strlen (str
);
22578 as_bad (_("missing architecture name `%s'"), str
);
22582 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22583 if (streq (opt
->name
, str
))
22585 march_cpu_opt
= &opt
->value
;
22586 march_fpu_opt
= &opt
->default_fpu
;
22587 strcpy (selected_cpu_name
, opt
->name
);
22590 return arm_parse_extension (ext
, &march_cpu_opt
);
22595 as_bad (_("unknown architecture `%s'\n"), str
);
22600 arm_parse_fpu (char * str
)
22602 const struct arm_option_cpu_value_table
* opt
;
22604 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22605 if (streq (opt
->name
, str
))
22607 mfpu_opt
= &opt
->value
;
22611 as_bad (_("unknown floating point format `%s'\n"), str
);
22616 arm_parse_float_abi (char * str
)
22618 const struct arm_option_value_table
* opt
;
22620 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22621 if (streq (opt
->name
, str
))
22623 mfloat_abi_opt
= opt
->value
;
22627 as_bad (_("unknown floating point abi `%s'\n"), str
);
22633 arm_parse_eabi (char * str
)
22635 const struct arm_option_value_table
*opt
;
22637 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22638 if (streq (opt
->name
, str
))
22640 meabi_flags
= opt
->value
;
22643 as_bad (_("unknown EABI `%s'\n"), str
);
22649 arm_parse_it_mode (char * str
)
22651 bfd_boolean ret
= TRUE
;
22653 if (streq ("arm", str
))
22654 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22655 else if (streq ("thumb", str
))
22656 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22657 else if (streq ("always", str
))
22658 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22659 else if (streq ("never", str
))
22660 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22663 as_bad (_("unknown implicit IT mode `%s', should be "\
22664 "arm, thumb, always, or never."), str
);
22671 struct arm_long_option_table arm_long_opts
[] =
22673 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22674 arm_parse_cpu
, NULL
},
22675 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22676 arm_parse_arch
, NULL
},
22677 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22678 arm_parse_fpu
, NULL
},
22679 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22680 arm_parse_float_abi
, NULL
},
22682 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22683 arm_parse_eabi
, NULL
},
22685 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22686 arm_parse_it_mode
, NULL
},
22687 {NULL
, NULL
, 0, NULL
}
22691 md_parse_option (int c
, char * arg
)
22693 struct arm_option_table
*opt
;
22694 const struct arm_legacy_option_table
*fopt
;
22695 struct arm_long_option_table
*lopt
;
22701 target_big_endian
= 1;
22707 target_big_endian
= 0;
22711 case OPTION_FIX_V4BX
:
22716 /* Listing option. Just ignore these, we don't support additional
22721 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22723 if (c
== opt
->option
[0]
22724 && ((arg
== NULL
&& opt
->option
[1] == 0)
22725 || streq (arg
, opt
->option
+ 1)))
22727 /* If the option is deprecated, tell the user. */
22728 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22729 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22730 arg
? arg
: "", _(opt
->deprecated
));
22732 if (opt
->var
!= NULL
)
22733 *opt
->var
= opt
->value
;
22739 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22741 if (c
== fopt
->option
[0]
22742 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22743 || streq (arg
, fopt
->option
+ 1)))
22745 /* If the option is deprecated, tell the user. */
22746 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22747 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22748 arg
? arg
: "", _(fopt
->deprecated
));
22750 if (fopt
->var
!= NULL
)
22751 *fopt
->var
= &fopt
->value
;
22757 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22759 /* These options are expected to have an argument. */
22760 if (c
== lopt
->option
[0]
22762 && strncmp (arg
, lopt
->option
+ 1,
22763 strlen (lopt
->option
+ 1)) == 0)
22765 /* If the option is deprecated, tell the user. */
22766 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22767 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22768 _(lopt
->deprecated
));
22770 /* Call the sup-option parser. */
22771 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22782 md_show_usage (FILE * fp
)
22784 struct arm_option_table
*opt
;
22785 struct arm_long_option_table
*lopt
;
22787 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22789 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22790 if (opt
->help
!= NULL
)
22791 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22793 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22794 if (lopt
->help
!= NULL
)
22795 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22799 -EB assemble code for a big-endian cpu\n"));
22804 -EL assemble code for a little-endian cpu\n"));
22808 --fix-v4bx Allow BX in ARMv4 code\n"));
22816 arm_feature_set flags
;
22817 } cpu_arch_ver_table
;
22819 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22820 least features first. */
22821 static const cpu_arch_ver_table cpu_arch_ver
[] =
22827 {4, ARM_ARCH_V5TE
},
22828 {5, ARM_ARCH_V5TEJ
},
22832 {11, ARM_ARCH_V6M
},
22833 {8, ARM_ARCH_V6T2
},
22834 {10, ARM_ARCH_V7A
},
22835 {10, ARM_ARCH_V7R
},
22836 {10, ARM_ARCH_V7M
},
22840 /* Set an attribute if it has not already been set by the user. */
22842 aeabi_set_attribute_int (int tag
, int value
)
22845 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22846 || !attributes_set_explicitly
[tag
])
22847 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22851 aeabi_set_attribute_string (int tag
, const char *value
)
22854 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22855 || !attributes_set_explicitly
[tag
])
22856 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22859 /* Set the public EABI object attributes. */
22861 aeabi_set_public_attributes (void)
22864 arm_feature_set flags
;
22865 arm_feature_set tmp
;
22866 const cpu_arch_ver_table
*p
;
22868 /* Choose the architecture based on the capabilities of the requested cpu
22869 (if any) and/or the instructions actually used. */
22870 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22871 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22872 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22873 /*Allow the user to override the reported architecture. */
22876 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22877 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22882 for (p
= cpu_arch_ver
; p
->val
; p
++)
22884 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22887 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22891 /* The table lookup above finds the last architecture to contribute
22892 a new feature. Unfortunately, Tag13 is a subset of the union of
22893 v6T2 and v7-M, so it is never seen as contributing a new feature.
22894 We can not search for the last entry which is entirely used,
22895 because if no CPU is specified we build up only those flags
22896 actually used. Perhaps we should separate out the specified
22897 and implicit cases. Avoid taking this path for -march=all by
22898 checking for contradictory v7-A / v7-M features. */
22900 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22901 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22902 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22905 /* Tag_CPU_name. */
22906 if (selected_cpu_name
[0])
22910 q
= selected_cpu_name
;
22911 if (strncmp (q
, "armv", 4) == 0)
22916 for (i
= 0; q
[i
]; i
++)
22917 q
[i
] = TOUPPER (q
[i
]);
22919 aeabi_set_attribute_string (Tag_CPU_name
, q
);
22922 /* Tag_CPU_arch. */
22923 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22925 /* Tag_CPU_arch_profile. */
22926 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22927 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22928 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22929 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22930 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22931 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22933 /* Tag_ARM_ISA_use. */
22934 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22936 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22938 /* Tag_THUMB_ISA_use. */
22939 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22941 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22942 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22944 /* Tag_VFP_arch. */
22945 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22946 aeabi_set_attribute_int (Tag_VFP_arch
,
22947 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22949 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22950 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22951 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
22952 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22953 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22954 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22955 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22956 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22957 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22959 /* Tag_ABI_HardFP_use. */
22960 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
22961 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
22962 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
22964 /* Tag_WMMX_arch. */
22965 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22966 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22967 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22968 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22970 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22971 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22972 aeabi_set_attribute_int
22973 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22976 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22977 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22978 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22981 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
22982 aeabi_set_attribute_int (Tag_DIV_use
, 0);
22983 /* Fill this in when gas supports v7a sdiv/udiv.
22984 else if (... v7a with div extension used ...)
22985 aeabi_set_attribute_int (Tag_DIV_use, 2); */
22987 aeabi_set_attribute_int (Tag_DIV_use
, 1);
22990 /* Add the default contents for the .ARM.attributes section. */
22994 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22997 aeabi_set_public_attributes ();
22999 #endif /* OBJ_ELF */
23002 /* Parse a .cpu directive. */
23005 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23007 const struct arm_cpu_option_table
*opt
;
23011 name
= input_line_pointer
;
23012 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23013 input_line_pointer
++;
23014 saved_char
= *input_line_pointer
;
23015 *input_line_pointer
= 0;
23017 /* Skip the first "all" entry. */
23018 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23019 if (streq (opt
->name
, name
))
23021 mcpu_cpu_opt
= &opt
->value
;
23022 selected_cpu
= opt
->value
;
23023 if (opt
->canonical_name
)
23024 strcpy (selected_cpu_name
, opt
->canonical_name
);
23028 for (i
= 0; opt
->name
[i
]; i
++)
23029 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23030 selected_cpu_name
[i
] = 0;
23032 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23033 *input_line_pointer
= saved_char
;
23034 demand_empty_rest_of_line ();
23037 as_bad (_("unknown cpu `%s'"), name
);
23038 *input_line_pointer
= saved_char
;
23039 ignore_rest_of_line ();
23043 /* Parse a .arch directive. */
23046 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23048 const struct arm_arch_option_table
*opt
;
23052 name
= input_line_pointer
;
23053 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23054 input_line_pointer
++;
23055 saved_char
= *input_line_pointer
;
23056 *input_line_pointer
= 0;
23058 /* Skip the first "all" entry. */
23059 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23060 if (streq (opt
->name
, name
))
23062 mcpu_cpu_opt
= &opt
->value
;
23063 selected_cpu
= opt
->value
;
23064 strcpy (selected_cpu_name
, opt
->name
);
23065 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23066 *input_line_pointer
= saved_char
;
23067 demand_empty_rest_of_line ();
23071 as_bad (_("unknown architecture `%s'\n"), name
);
23072 *input_line_pointer
= saved_char
;
23073 ignore_rest_of_line ();
23077 /* Parse a .object_arch directive. */
23080 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23082 const struct arm_arch_option_table
*opt
;
23086 name
= input_line_pointer
;
23087 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23088 input_line_pointer
++;
23089 saved_char
= *input_line_pointer
;
23090 *input_line_pointer
= 0;
23092 /* Skip the first "all" entry. */
23093 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23094 if (streq (opt
->name
, name
))
23096 object_arch
= &opt
->value
;
23097 *input_line_pointer
= saved_char
;
23098 demand_empty_rest_of_line ();
23102 as_bad (_("unknown architecture `%s'\n"), name
);
23103 *input_line_pointer
= saved_char
;
23104 ignore_rest_of_line ();
23107 /* Parse a .fpu directive. */
23110 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23112 const struct arm_option_cpu_value_table
*opt
;
23116 name
= input_line_pointer
;
23117 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23118 input_line_pointer
++;
23119 saved_char
= *input_line_pointer
;
23120 *input_line_pointer
= 0;
23122 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23123 if (streq (opt
->name
, name
))
23125 mfpu_opt
= &opt
->value
;
23126 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23127 *input_line_pointer
= saved_char
;
23128 demand_empty_rest_of_line ();
23132 as_bad (_("unknown floating point format `%s'\n"), name
);
23133 *input_line_pointer
= saved_char
;
23134 ignore_rest_of_line ();
23137 /* Copy symbol information. */
23140 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23142 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23146 /* Given a symbolic attribute NAME, return the proper integer value.
23147 Returns -1 if the attribute is not known. */
23150 arm_convert_symbolic_attribute (const char *name
)
23152 static const struct
23157 attribute_table
[] =
23159 /* When you modify this table you should
23160 also modify the list in doc/c-arm.texi. */
23161 #define T(tag) {#tag, tag}
23162 T (Tag_CPU_raw_name
),
23165 T (Tag_CPU_arch_profile
),
23166 T (Tag_ARM_ISA_use
),
23167 T (Tag_THUMB_ISA_use
),
23171 T (Tag_Advanced_SIMD_arch
),
23172 T (Tag_PCS_config
),
23173 T (Tag_ABI_PCS_R9_use
),
23174 T (Tag_ABI_PCS_RW_data
),
23175 T (Tag_ABI_PCS_RO_data
),
23176 T (Tag_ABI_PCS_GOT_use
),
23177 T (Tag_ABI_PCS_wchar_t
),
23178 T (Tag_ABI_FP_rounding
),
23179 T (Tag_ABI_FP_denormal
),
23180 T (Tag_ABI_FP_exceptions
),
23181 T (Tag_ABI_FP_user_exceptions
),
23182 T (Tag_ABI_FP_number_model
),
23183 T (Tag_ABI_align_needed
),
23184 T (Tag_ABI_align8_needed
),
23185 T (Tag_ABI_align_preserved
),
23186 T (Tag_ABI_align8_preserved
),
23187 T (Tag_ABI_enum_size
),
23188 T (Tag_ABI_HardFP_use
),
23189 T (Tag_ABI_VFP_args
),
23190 T (Tag_ABI_WMMX_args
),
23191 T (Tag_ABI_optimization_goals
),
23192 T (Tag_ABI_FP_optimization_goals
),
23193 T (Tag_compatibility
),
23194 T (Tag_CPU_unaligned_access
),
23195 T (Tag_FP_HP_extension
),
23196 T (Tag_VFP_HP_extension
),
23197 T (Tag_ABI_FP_16bit_format
),
23198 T (Tag_MPextension_use
),
23200 T (Tag_nodefaults
),
23201 T (Tag_also_compatible_with
),
23202 T (Tag_conformance
),
23204 T (Tag_Virtualization_use
),
23205 /* We deliberately do not include Tag_MPextension_use_legacy. */
23213 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23214 if (streq (name
, attribute_table
[i
].name
))
23215 return attribute_table
[i
].tag
;
23221 /* Apply sym value for relocations only in the case that
23222 they are for local symbols and you have the respective
23223 architectural feature for blx and simple switches. */
23225 arm_apply_sym_value (struct fix
* fixP
)
23228 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23229 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23231 switch (fixP
->fx_r_type
)
23233 case BFD_RELOC_ARM_PCREL_BLX
:
23234 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23235 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23239 case BFD_RELOC_ARM_PCREL_CALL
:
23240 case BFD_RELOC_THUMB_PCREL_BLX
:
23241 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23252 #endif /* OBJ_ELF */