1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
189 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
190 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
191 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
192 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
193 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
194 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
195 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
196 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
197 static const arm_feature_set arm_ext_m
=
198 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
200 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_arch_any
= ARM_ANY
;
203 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
204 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
205 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
207 static const arm_feature_set arm_cext_iwmmxt2
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
209 static const arm_feature_set arm_cext_iwmmxt
=
210 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
211 static const arm_feature_set arm_cext_xscale
=
212 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
213 static const arm_feature_set arm_cext_maverick
=
214 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
215 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
216 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
217 static const arm_feature_set fpu_vfp_ext_v1xd
=
218 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
219 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
220 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
221 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
222 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
223 static const arm_feature_set fpu_vfp_ext_d32
=
224 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
225 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
226 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
227 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
229 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
230 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
244 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
249 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
254 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
255 symbolS
* GOT_symbol
;
258 /* 0: assemble for ARM,
259 1: assemble for Thumb,
260 2: assemble for Thumb even though target CPU does not support thumb
262 static int thumb_mode
= 0;
263 /* A value distinct from the possible values for thumb_mode that we
264 can use to record whether thumb_mode has been copied into the
265 tc_frag_data field of a frag. */
266 #define MODE_RECORDED (1 << 4)
268 /* Specifies the intrinsic IT insn behavior mode. */
269 enum implicit_it_mode
271 IMPLICIT_IT_MODE_NEVER
= 0x00,
272 IMPLICIT_IT_MODE_ARM
= 0x01,
273 IMPLICIT_IT_MODE_THUMB
= 0x02,
274 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
276 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
278 /* If unified_syntax is true, we are processing the new unified
279 ARM/Thumb syntax. Important differences from the old ARM mode:
281 - Immediate operands do not require a # prefix.
282 - Conditional affixes always appear at the end of the
283 instruction. (For backward compatibility, those instructions
284 that formerly had them in the middle, continue to accept them
286 - The IT instruction may appear, and if it does is validated
287 against subsequent conditional affixes. It does not generate
290 Important differences from the old Thumb mode:
292 - Immediate operands do not require a # prefix.
293 - Most of the V6T2 instructions are only available in unified mode.
294 - The .N and .W suffixes are recognized and honored (it is an error
295 if they cannot be honored).
296 - All instructions set the flags if and only if they have an 's' affix.
297 - Conditional affixes may be used. They are validated against
298 preceding IT instructions. Unlike ARM mode, you cannot use a
299 conditional affix except in the scope of an IT instruction. */
301 static bfd_boolean unified_syntax
= FALSE
;
316 enum neon_el_type type
;
320 #define NEON_MAX_TYPE_ELS 4
324 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
328 enum it_instruction_type
333 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
334 if inside, should be the last one. */
335 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
336 i.e. BKPT and NOP. */
337 IT_INSN
/* The IT insn has been parsed. */
343 unsigned long instruction
;
347 /* "uncond_value" is set to the value in place of the conditional field in
348 unconditional versions of the instruction, or -1 if nothing is
351 struct neon_type vectype
;
352 /* This does not indicate an actual NEON instruction, only that
353 the mnemonic accepts neon-style type suffixes. */
355 /* Set to the opcode if the instruction needs relaxation.
356 Zero if the instruction is not relaxed. */
360 bfd_reloc_code_real_type type
;
365 enum it_instruction_type it_insn_type
;
371 struct neon_type_el vectype
;
372 unsigned present
: 1; /* Operand present. */
373 unsigned isreg
: 1; /* Operand was a register. */
374 unsigned immisreg
: 1; /* .imm field is a second register. */
375 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
376 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
377 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
378 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
379 instructions. This allows us to disambiguate ARM <-> vector insns. */
380 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
381 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
382 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
383 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
384 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
385 unsigned writeback
: 1; /* Operand has trailing ! */
386 unsigned preind
: 1; /* Preindexed address. */
387 unsigned postind
: 1; /* Postindexed address. */
388 unsigned negative
: 1; /* Index register was negated. */
389 unsigned shifted
: 1; /* Shift applied to operation. */
390 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
394 static struct arm_it inst
;
396 #define NUM_FLOAT_VALS 8
398 const char * fp_const
[] =
400 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
403 /* Number of littlenums required to hold an extended precision number. */
404 #define MAX_LITTLENUMS 6
406 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
416 #define CP_T_X 0x00008000
417 #define CP_T_Y 0x00400000
419 #define CONDS_BIT 0x00100000
420 #define LOAD_BIT 0x00100000
422 #define DOUBLE_LOAD_FLAG 0x00000001
426 const char * template_name
;
430 #define COND_ALWAYS 0xE
434 const char * template_name
;
438 struct asm_barrier_opt
440 const char * template_name
;
444 /* The bit that distinguishes CPSR and SPSR. */
445 #define SPSR_BIT (1 << 22)
447 /* The individual PSR flag bits. */
448 #define PSR_c (1 << 16)
449 #define PSR_x (1 << 17)
450 #define PSR_s (1 << 18)
451 #define PSR_f (1 << 19)
456 bfd_reloc_code_real_type reloc
;
461 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
462 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
467 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
470 /* Bits for DEFINED field in neon_typed_alias. */
471 #define NTA_HASTYPE 1
472 #define NTA_HASINDEX 2
474 struct neon_typed_alias
476 unsigned char defined
;
478 struct neon_type_el eltype
;
481 /* ARM register categories. This includes coprocessor numbers and various
482 architecture extensions' registers. */
508 /* Structure for a hash table entry for a register.
509 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
510 information which states whether a vector type or index is specified (for a
511 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
515 unsigned char number
;
517 unsigned char builtin
;
518 struct neon_typed_alias
* neon
;
521 /* Diagnostics used when we don't get a register of the expected type. */
522 const char * const reg_expected_msgs
[] =
524 N_("ARM register expected"),
525 N_("bad or missing co-processor number"),
526 N_("co-processor register expected"),
527 N_("FPA register expected"),
528 N_("VFP single precision register expected"),
529 N_("VFP/Neon double precision register expected"),
530 N_("Neon quad precision register expected"),
531 N_("VFP single or double precision register expected"),
532 N_("Neon double or quad precision register expected"),
533 N_("VFP single, double or Neon quad precision register expected"),
534 N_("VFP system register expected"),
535 N_("Maverick MVF register expected"),
536 N_("Maverick MVD register expected"),
537 N_("Maverick MVFX register expected"),
538 N_("Maverick MVDX register expected"),
539 N_("Maverick MVAX register expected"),
540 N_("Maverick DSPSC register expected"),
541 N_("iWMMXt data register expected"),
542 N_("iWMMXt control register expected"),
543 N_("iWMMXt scalar register expected"),
544 N_("XScale accumulator register expected"),
547 /* Some well known registers that we refer to directly elsewhere. */
552 /* ARM instructions take 4bytes in the object file, Thumb instructions
558 /* Basic string to match. */
559 const char * template_name
;
561 /* Parameters to instruction. */
562 unsigned int operands
[8];
564 /* Conditional tag - see opcode_lookup. */
565 unsigned int tag
: 4;
567 /* Basic instruction code. */
568 unsigned int avalue
: 28;
570 /* Thumb-format instruction code. */
573 /* Which architecture variant provides this instruction. */
574 const arm_feature_set
* avariant
;
575 const arm_feature_set
* tvariant
;
577 /* Function to call to encode instruction in ARM format. */
578 void (* aencode
) (void);
580 /* Function to call to encode instruction in Thumb format. */
581 void (* tencode
) (void);
584 /* Defines for various bits that we will want to toggle. */
585 #define INST_IMMEDIATE 0x02000000
586 #define OFFSET_REG 0x02000000
587 #define HWOFFSET_IMM 0x00400000
588 #define SHIFT_BY_REG 0x00000010
589 #define PRE_INDEX 0x01000000
590 #define INDEX_UP 0x00800000
591 #define WRITE_BACK 0x00200000
592 #define LDM_TYPE_2_OR_3 0x00400000
593 #define CPSI_MMOD 0x00020000
595 #define LITERAL_MASK 0xf000f000
596 #define OPCODE_MASK 0xfe1fffff
597 #define V4_STR_BIT 0x00000020
599 #define T2_SUBS_PC_LR 0xf3de8f00
601 #define DATA_OP_SHIFT 21
603 #define T2_OPCODE_MASK 0xfe1fffff
604 #define T2_DATA_OP_SHIFT 21
606 /* Codes to distinguish the arithmetic instructions. */
617 #define OPCODE_CMP 10
618 #define OPCODE_CMN 11
619 #define OPCODE_ORR 12
620 #define OPCODE_MOV 13
621 #define OPCODE_BIC 14
622 #define OPCODE_MVN 15
624 #define T2_OPCODE_AND 0
625 #define T2_OPCODE_BIC 1
626 #define T2_OPCODE_ORR 2
627 #define T2_OPCODE_ORN 3
628 #define T2_OPCODE_EOR 4
629 #define T2_OPCODE_ADD 8
630 #define T2_OPCODE_ADC 10
631 #define T2_OPCODE_SBC 11
632 #define T2_OPCODE_SUB 13
633 #define T2_OPCODE_RSB 14
635 #define T_OPCODE_MUL 0x4340
636 #define T_OPCODE_TST 0x4200
637 #define T_OPCODE_CMN 0x42c0
638 #define T_OPCODE_NEG 0x4240
639 #define T_OPCODE_MVN 0x43c0
641 #define T_OPCODE_ADD_R3 0x1800
642 #define T_OPCODE_SUB_R3 0x1a00
643 #define T_OPCODE_ADD_HI 0x4400
644 #define T_OPCODE_ADD_ST 0xb000
645 #define T_OPCODE_SUB_ST 0xb080
646 #define T_OPCODE_ADD_SP 0xa800
647 #define T_OPCODE_ADD_PC 0xa000
648 #define T_OPCODE_ADD_I8 0x3000
649 #define T_OPCODE_SUB_I8 0x3800
650 #define T_OPCODE_ADD_I3 0x1c00
651 #define T_OPCODE_SUB_I3 0x1e00
653 #define T_OPCODE_ASR_R 0x4100
654 #define T_OPCODE_LSL_R 0x4080
655 #define T_OPCODE_LSR_R 0x40c0
656 #define T_OPCODE_ROR_R 0x41c0
657 #define T_OPCODE_ASR_I 0x1000
658 #define T_OPCODE_LSL_I 0x0000
659 #define T_OPCODE_LSR_I 0x0800
661 #define T_OPCODE_MOV_I8 0x2000
662 #define T_OPCODE_CMP_I8 0x2800
663 #define T_OPCODE_CMP_LR 0x4280
664 #define T_OPCODE_MOV_HR 0x4600
665 #define T_OPCODE_CMP_HR 0x4500
667 #define T_OPCODE_LDR_PC 0x4800
668 #define T_OPCODE_LDR_SP 0x9800
669 #define T_OPCODE_STR_SP 0x9000
670 #define T_OPCODE_LDR_IW 0x6800
671 #define T_OPCODE_STR_IW 0x6000
672 #define T_OPCODE_LDR_IH 0x8800
673 #define T_OPCODE_STR_IH 0x8000
674 #define T_OPCODE_LDR_IB 0x7800
675 #define T_OPCODE_STR_IB 0x7000
676 #define T_OPCODE_LDR_RW 0x5800
677 #define T_OPCODE_STR_RW 0x5000
678 #define T_OPCODE_LDR_RH 0x5a00
679 #define T_OPCODE_STR_RH 0x5200
680 #define T_OPCODE_LDR_RB 0x5c00
681 #define T_OPCODE_STR_RB 0x5400
683 #define T_OPCODE_PUSH 0xb400
684 #define T_OPCODE_POP 0xbc00
686 #define T_OPCODE_BRANCH 0xe000
688 #define THUMB_SIZE 2 /* Size of thumb instruction. */
689 #define THUMB_PP_PC_LR 0x0100
690 #define THUMB_LOAD_BIT 0x0800
691 #define THUMB2_LOAD_BIT 0x00100000
693 #define BAD_ARGS _("bad arguments to instruction")
694 #define BAD_SP _("r13 not allowed here")
695 #define BAD_PC _("r15 not allowed here")
696 #define BAD_COND _("instruction cannot be conditional")
697 #define BAD_OVERLAP _("registers may not be the same")
698 #define BAD_HIREG _("lo register required")
699 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
700 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
701 #define BAD_BRANCH _("branch must be last instruction in IT block")
702 #define BAD_NOT_IT _("instruction not allowed in IT block")
703 #define BAD_FPU _("selected FPU does not support instruction")
704 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
705 #define BAD_IT_COND _("incorrect condition in IT block")
706 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
707 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
708 #define BAD_PC_ADDRESSING \
709 _("cannot use register index with PC-relative addressing")
710 #define BAD_PC_WRITEBACK \
711 _("cannot use writeback with PC-relative addressing")
713 static struct hash_control
* arm_ops_hsh
;
714 static struct hash_control
* arm_cond_hsh
;
715 static struct hash_control
* arm_shift_hsh
;
716 static struct hash_control
* arm_psr_hsh
;
717 static struct hash_control
* arm_v7m_psr_hsh
;
718 static struct hash_control
* arm_reg_hsh
;
719 static struct hash_control
* arm_reloc_hsh
;
720 static struct hash_control
* arm_barrier_opt_hsh
;
722 /* Stuff needed to resolve the label ambiguity
731 symbolS
* last_label_seen
;
732 static int label_is_thumb_function_name
= FALSE
;
734 /* Literal pool structure. Held on a per-section
735 and per-sub-section basis. */
737 #define MAX_LITERAL_POOL_SIZE 1024
738 typedef struct literal_pool
740 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
741 unsigned int next_free_entry
;
746 struct literal_pool
* next
;
749 /* Pointer to a linked list of literal pools. */
750 literal_pool
* list_of_pools
= NULL
;
753 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
755 static struct current_it now_it
;
759 now_it_compatible (int cond
)
761 return (cond
& ~1) == (now_it
.cc
& ~1);
765 conditional_insn (void)
767 return inst
.cond
!= COND_ALWAYS
;
770 static int in_it_block (void);
772 static int handle_it_state (void);
774 static void force_automatic_it_block_close (void);
776 static void it_fsm_post_encode (void);
778 #define set_it_insn_type(type) \
781 inst.it_insn_type = type; \
782 if (handle_it_state () == FAIL) \
787 #define set_it_insn_type_nonvoid(type, failret) \
790 inst.it_insn_type = type; \
791 if (handle_it_state () == FAIL) \
796 #define set_it_insn_type_last() \
799 if (inst.cond == COND_ALWAYS) \
800 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
802 set_it_insn_type (INSIDE_IT_LAST_INSN); \
808 /* This array holds the chars that always start a comment. If the
809 pre-processor is disabled, these aren't very useful. */
810 const char comment_chars
[] = "@";
812 /* This array holds the chars that only start a comment at the beginning of
813 a line. If the line seems to have the form '# 123 filename'
814 .line and .file directives will appear in the pre-processed output. */
815 /* Note that input_file.c hand checks for '#' at the beginning of the
816 first line of the input file. This is because the compiler outputs
817 #NO_APP at the beginning of its output. */
818 /* Also note that comments like this one will always work. */
819 const char line_comment_chars
[] = "#";
821 const char line_separator_chars
[] = ";";
823 /* Chars that can be used to separate mant
824 from exp in floating point numbers. */
825 const char EXP_CHARS
[] = "eE";
827 /* Chars that mean this number is a floating point constant. */
831 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
833 /* Prefix characters that indicate the start of an immediate
835 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
837 /* Separator character handling. */
839 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
842 skip_past_char (char ** str
, char c
)
853 #define skip_past_comma(str) skip_past_char (str, ',')
855 /* Arithmetic expressions (possibly involving symbols). */
857 /* Return TRUE if anything in the expression is a bignum. */
860 walk_no_bignums (symbolS
* sp
)
862 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
865 if (symbol_get_value_expression (sp
)->X_add_symbol
)
867 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
868 || (symbol_get_value_expression (sp
)->X_op_symbol
869 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
875 static int in_my_get_expression
= 0;
877 /* Third argument to my_get_expression. */
878 #define GE_NO_PREFIX 0
879 #define GE_IMM_PREFIX 1
880 #define GE_OPT_PREFIX 2
881 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
882 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
883 #define GE_OPT_PREFIX_BIG 3
886 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
891 /* In unified syntax, all prefixes are optional. */
893 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
898 case GE_NO_PREFIX
: break;
900 if (!is_immediate_prefix (**str
))
902 inst
.error
= _("immediate expression requires a # prefix");
908 case GE_OPT_PREFIX_BIG
:
909 if (is_immediate_prefix (**str
))
915 memset (ep
, 0, sizeof (expressionS
));
917 save_in
= input_line_pointer
;
918 input_line_pointer
= *str
;
919 in_my_get_expression
= 1;
920 seg
= expression (ep
);
921 in_my_get_expression
= 0;
923 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
925 /* We found a bad or missing expression in md_operand(). */
926 *str
= input_line_pointer
;
927 input_line_pointer
= save_in
;
928 if (inst
.error
== NULL
)
929 inst
.error
= (ep
->X_op
== O_absent
930 ? _("missing expression") :_("bad expression"));
935 if (seg
!= absolute_section
936 && seg
!= text_section
937 && seg
!= data_section
938 && seg
!= bss_section
939 && seg
!= undefined_section
)
941 inst
.error
= _("bad segment");
942 *str
= input_line_pointer
;
943 input_line_pointer
= save_in
;
950 /* Get rid of any bignums now, so that we don't generate an error for which
951 we can't establish a line number later on. Big numbers are never valid
952 in instructions, which is where this routine is always called. */
953 if (prefix_mode
!= GE_OPT_PREFIX_BIG
954 && (ep
->X_op
== O_big
956 && (walk_no_bignums (ep
->X_add_symbol
)
958 && walk_no_bignums (ep
->X_op_symbol
))))))
960 inst
.error
= _("invalid constant");
961 *str
= input_line_pointer
;
962 input_line_pointer
= save_in
;
966 *str
= input_line_pointer
;
967 input_line_pointer
= save_in
;
971 /* Turn a string in input_line_pointer into a floating point constant
972 of type TYPE, and store the appropriate bytes in *LITP. The number
973 of LITTLENUMS emitted is stored in *SIZEP. An error message is
974 returned, or NULL on OK.
976 Note that fp constants aren't represent in the normal way on the ARM.
977 In big endian mode, things are as expected. However, in little endian
978 mode fp constants are big-endian word-wise, and little-endian byte-wise
979 within the words. For example, (double) 1.1 in big endian mode is
980 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
981 the byte sequence 99 99 f1 3f 9a 99 99 99.
983 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
986 md_atof (int type
, char * litP
, int * sizeP
)
989 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1021 return _("Unrecognized or unsupported floating point constant");
1024 t
= atof_ieee (input_line_pointer
, type
, words
);
1026 input_line_pointer
= t
;
1027 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1029 if (target_big_endian
)
1031 for (i
= 0; i
< prec
; i
++)
1033 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1034 litP
+= sizeof (LITTLENUM_TYPE
);
1039 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1040 for (i
= prec
- 1; i
>= 0; i
--)
1042 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1043 litP
+= sizeof (LITTLENUM_TYPE
);
1046 /* For a 4 byte float the order of elements in `words' is 1 0.
1047 For an 8 byte float the order is 1 0 3 2. */
1048 for (i
= 0; i
< prec
; i
+= 2)
1050 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1051 sizeof (LITTLENUM_TYPE
));
1052 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1053 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1054 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1061 /* We handle all bad expressions here, so that we can report the faulty
1062 instruction in the error message. */
1064 md_operand (expressionS
* exp
)
1066 if (in_my_get_expression
)
1067 exp
->X_op
= O_illegal
;
1070 /* Immediate values. */
1072 /* Generic immediate-value read function for use in directives.
1073 Accepts anything that 'expression' can fold to a constant.
1074 *val receives the number. */
1077 immediate_for_directive (int *val
)
1080 exp
.X_op
= O_illegal
;
1082 if (is_immediate_prefix (*input_line_pointer
))
1084 input_line_pointer
++;
1088 if (exp
.X_op
!= O_constant
)
1090 as_bad (_("expected #constant"));
1091 ignore_rest_of_line ();
1094 *val
= exp
.X_add_number
;
1099 /* Register parsing. */
1101 /* Generic register parser. CCP points to what should be the
1102 beginning of a register name. If it is indeed a valid register
1103 name, advance CCP over it and return the reg_entry structure;
1104 otherwise return NULL. Does not issue diagnostics. */
1106 static struct reg_entry
*
1107 arm_reg_parse_multi (char **ccp
)
1111 struct reg_entry
*reg
;
1113 #ifdef REGISTER_PREFIX
1114 if (*start
!= REGISTER_PREFIX
)
1118 #ifdef OPTIONAL_REGISTER_PREFIX
1119 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1124 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1129 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1131 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1141 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1142 enum arm_reg_type type
)
1144 /* Alternative syntaxes are accepted for a few register classes. */
1151 /* Generic coprocessor register names are allowed for these. */
1152 if (reg
&& reg
->type
== REG_TYPE_CN
)
1157 /* For backward compatibility, a bare number is valid here. */
1159 unsigned long processor
= strtoul (start
, ccp
, 10);
1160 if (*ccp
!= start
&& processor
<= 15)
1164 case REG_TYPE_MMXWC
:
1165 /* WC includes WCG. ??? I'm not sure this is true for all
1166 instructions that take WC registers. */
1167 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1178 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1179 return value is the register number or FAIL. */
1182 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1185 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1188 /* Do not allow a scalar (reg+index) to parse as a register. */
1189 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1192 if (reg
&& reg
->type
== type
)
1195 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1202 /* Parse a Neon type specifier. *STR should point at the leading '.'
1203 character. Does no verification at this stage that the type fits the opcode
1210 Can all be legally parsed by this function.
1212 Fills in neon_type struct pointer with parsed information, and updates STR
1213 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1214 type, FAIL if not. */
1217 parse_neon_type (struct neon_type
*type
, char **str
)
1224 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1226 enum neon_el_type thistype
= NT_untyped
;
1227 unsigned thissize
= -1u;
1234 /* Just a size without an explicit type. */
1238 switch (TOLOWER (*ptr
))
1240 case 'i': thistype
= NT_integer
; break;
1241 case 'f': thistype
= NT_float
; break;
1242 case 'p': thistype
= NT_poly
; break;
1243 case 's': thistype
= NT_signed
; break;
1244 case 'u': thistype
= NT_unsigned
; break;
1246 thistype
= NT_float
;
1251 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1257 /* .f is an abbreviation for .f32. */
1258 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1263 thissize
= strtoul (ptr
, &ptr
, 10);
1265 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1268 as_bad (_("bad size %d in type specifier"), thissize
);
1276 type
->el
[type
->elems
].type
= thistype
;
1277 type
->el
[type
->elems
].size
= thissize
;
1282 /* Empty/missing type is not a successful parse. */
1283 if (type
->elems
== 0)
1291 /* Errors may be set multiple times during parsing or bit encoding
1292 (particularly in the Neon bits), but usually the earliest error which is set
1293 will be the most meaningful. Avoid overwriting it with later (cascading)
1294 errors by calling this function. */
1297 first_error (const char *err
)
1303 /* Parse a single type, e.g. ".s32", leading period included. */
1305 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1308 struct neon_type optype
;
1312 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1314 if (optype
.elems
== 1)
1315 *vectype
= optype
.el
[0];
1318 first_error (_("only one type should be specified for operand"));
1324 first_error (_("vector type expected"));
1336 /* Special meanings for indices (which have a range of 0-7), which will fit into
1339 #define NEON_ALL_LANES 15
1340 #define NEON_INTERLEAVE_LANES 14
1342 /* Parse either a register or a scalar, with an optional type. Return the
1343 register number, and optionally fill in the actual type of the register
1344 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1345 type/index information in *TYPEINFO. */
1348 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1349 enum arm_reg_type
*rtype
,
1350 struct neon_typed_alias
*typeinfo
)
1353 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1354 struct neon_typed_alias atype
;
1355 struct neon_type_el parsetype
;
1359 atype
.eltype
.type
= NT_invtype
;
1360 atype
.eltype
.size
= -1;
1362 /* Try alternate syntax for some types of register. Note these are mutually
1363 exclusive with the Neon syntax extensions. */
1366 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1374 /* Undo polymorphism when a set of register types may be accepted. */
1375 if ((type
== REG_TYPE_NDQ
1376 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1377 || (type
== REG_TYPE_VFSD
1378 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1379 || (type
== REG_TYPE_NSDQ
1380 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1381 || reg
->type
== REG_TYPE_NQ
))
1382 || (type
== REG_TYPE_MMXWC
1383 && (reg
->type
== REG_TYPE_MMXWCG
)))
1384 type
= (enum arm_reg_type
) reg
->type
;
1386 if (type
!= reg
->type
)
1392 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1394 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1396 first_error (_("can't redefine type for operand"));
1399 atype
.defined
|= NTA_HASTYPE
;
1400 atype
.eltype
= parsetype
;
1403 if (skip_past_char (&str
, '[') == SUCCESS
)
1405 if (type
!= REG_TYPE_VFD
)
1407 first_error (_("only D registers may be indexed"));
1411 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1413 first_error (_("can't change index for operand"));
1417 atype
.defined
|= NTA_HASINDEX
;
1419 if (skip_past_char (&str
, ']') == SUCCESS
)
1420 atype
.index
= NEON_ALL_LANES
;
1425 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1427 if (exp
.X_op
!= O_constant
)
1429 first_error (_("constant expression required"));
1433 if (skip_past_char (&str
, ']') == FAIL
)
1436 atype
.index
= exp
.X_add_number
;
1451 /* Like arm_reg_parse, but allow allow the following extra features:
1452 - If RTYPE is non-zero, return the (possibly restricted) type of the
1453 register (e.g. Neon double or quad reg when either has been requested).
1454 - If this is a Neon vector type with additional type information, fill
1455 in the struct pointed to by VECTYPE (if non-NULL).
1456 This function will fault on encountering a scalar. */
1459 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1460 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1462 struct neon_typed_alias atype
;
1464 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1469 /* Do not allow a scalar (reg+index) to parse as a register. */
1470 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1472 first_error (_("register operand expected, but got scalar"));
1477 *vectype
= atype
.eltype
;
1484 #define NEON_SCALAR_REG(X) ((X) >> 4)
1485 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1487 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1488 have enough information to be able to do a good job bounds-checking. So, we
1489 just do easy checks here, and do further checks later. */
1492 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1496 struct neon_typed_alias atype
;
1498 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1500 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1503 if (atype
.index
== NEON_ALL_LANES
)
1505 first_error (_("scalar must have an index"));
1508 else if (atype
.index
>= 64 / elsize
)
1510 first_error (_("scalar index out of range"));
1515 *type
= atype
.eltype
;
1519 return reg
* 16 + atype
.index
;
1522 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1525 parse_reg_list (char ** strp
)
1527 char * str
= * strp
;
1531 /* We come back here if we get ranges concatenated by '+' or '|'. */
1546 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1548 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1558 first_error (_("bad range in register list"));
1562 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1564 if (range
& (1 << i
))
1566 (_("Warning: duplicated register (r%d) in register list"),
1574 if (range
& (1 << reg
))
1575 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1577 else if (reg
<= cur_reg
)
1578 as_tsktsk (_("Warning: register range not in ascending order"));
1583 while (skip_past_comma (&str
) != FAIL
1584 || (in_range
= 1, *str
++ == '-'));
1589 first_error (_("missing `}'"));
1597 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1600 if (exp
.X_op
== O_constant
)
1602 if (exp
.X_add_number
1603 != (exp
.X_add_number
& 0x0000ffff))
1605 inst
.error
= _("invalid register mask");
1609 if ((range
& exp
.X_add_number
) != 0)
1611 int regno
= range
& exp
.X_add_number
;
1614 regno
= (1 << regno
) - 1;
1616 (_("Warning: duplicated register (r%d) in register list"),
1620 range
|= exp
.X_add_number
;
1624 if (inst
.reloc
.type
!= 0)
1626 inst
.error
= _("expression too complex");
1630 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1631 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1632 inst
.reloc
.pc_rel
= 0;
1636 if (*str
== '|' || *str
== '+')
1642 while (another_range
);
1648 /* Types of registers in a list. */
1657 /* Parse a VFP register list. If the string is invalid return FAIL.
1658 Otherwise return the number of registers, and set PBASE to the first
1659 register. Parses registers of type ETYPE.
1660 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1661 - Q registers can be used to specify pairs of D registers
1662 - { } can be omitted from around a singleton register list
1663 FIXME: This is not implemented, as it would require backtracking in
1666 This could be done (the meaning isn't really ambiguous), but doesn't
1667 fit in well with the current parsing framework.
1668 - 32 D registers may be used (also true for VFPv3).
1669 FIXME: Types are ignored in these register lists, which is probably a
1673 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1678 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1682 unsigned long mask
= 0;
1687 inst
.error
= _("expecting {");
1696 regtype
= REG_TYPE_VFS
;
1701 regtype
= REG_TYPE_VFD
;
1704 case REGLIST_NEON_D
:
1705 regtype
= REG_TYPE_NDQ
;
1709 if (etype
!= REGLIST_VFP_S
)
1711 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1712 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1716 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1719 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1726 base_reg
= max_regs
;
1730 int setmask
= 1, addregs
= 1;
1732 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1734 if (new_base
== FAIL
)
1736 first_error (_(reg_expected_msgs
[regtype
]));
1740 if (new_base
>= max_regs
)
1742 first_error (_("register out of range in list"));
1746 /* Note: a value of 2 * n is returned for the register Q<n>. */
1747 if (regtype
== REG_TYPE_NQ
)
1753 if (new_base
< base_reg
)
1754 base_reg
= new_base
;
1756 if (mask
& (setmask
<< new_base
))
1758 first_error (_("invalid register list"));
1762 if ((mask
>> new_base
) != 0 && ! warned
)
1764 as_tsktsk (_("register list not in ascending order"));
1768 mask
|= setmask
<< new_base
;
1771 if (*str
== '-') /* We have the start of a range expression */
1777 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1780 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1784 if (high_range
>= max_regs
)
1786 first_error (_("register out of range in list"));
1790 if (regtype
== REG_TYPE_NQ
)
1791 high_range
= high_range
+ 1;
1793 if (high_range
<= new_base
)
1795 inst
.error
= _("register range not in ascending order");
1799 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1801 if (mask
& (setmask
<< new_base
))
1803 inst
.error
= _("invalid register list");
1807 mask
|= setmask
<< new_base
;
1812 while (skip_past_comma (&str
) != FAIL
);
1816 /* Sanity check -- should have raised a parse error above. */
1817 if (count
== 0 || count
> max_regs
)
1822 /* Final test -- the registers must be consecutive. */
1824 for (i
= 0; i
< count
; i
++)
1826 if ((mask
& (1u << i
)) == 0)
1828 inst
.error
= _("non-contiguous register range");
1838 /* True if two alias types are the same. */
1841 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1849 if (a
->defined
!= b
->defined
)
1852 if ((a
->defined
& NTA_HASTYPE
) != 0
1853 && (a
->eltype
.type
!= b
->eltype
.type
1854 || a
->eltype
.size
!= b
->eltype
.size
))
1857 if ((a
->defined
& NTA_HASINDEX
) != 0
1858 && (a
->index
!= b
->index
))
1864 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1865 The base register is put in *PBASE.
1866 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1868 The register stride (minus one) is put in bit 4 of the return value.
1869 Bits [6:5] encode the list length (minus one).
1870 The type of the list elements is put in *ELTYPE, if non-NULL. */
1872 #define NEON_LANE(X) ((X) & 0xf)
1873 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1874 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1877 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1878 struct neon_type_el
*eltype
)
1885 int leading_brace
= 0;
1886 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1887 const char *const incr_error
= _("register stride must be 1 or 2");
1888 const char *const type_error
= _("mismatched element/structure types in list");
1889 struct neon_typed_alias firsttype
;
1891 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1896 struct neon_typed_alias atype
;
1897 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1901 first_error (_(reg_expected_msgs
[rtype
]));
1908 if (rtype
== REG_TYPE_NQ
)
1914 else if (reg_incr
== -1)
1916 reg_incr
= getreg
- base_reg
;
1917 if (reg_incr
< 1 || reg_incr
> 2)
1919 first_error (_(incr_error
));
1923 else if (getreg
!= base_reg
+ reg_incr
* count
)
1925 first_error (_(incr_error
));
1929 if (! neon_alias_types_same (&atype
, &firsttype
))
1931 first_error (_(type_error
));
1935 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1939 struct neon_typed_alias htype
;
1940 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1942 lane
= NEON_INTERLEAVE_LANES
;
1943 else if (lane
!= NEON_INTERLEAVE_LANES
)
1945 first_error (_(type_error
));
1950 else if (reg_incr
!= 1)
1952 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1956 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1959 first_error (_(reg_expected_msgs
[rtype
]));
1962 if (! neon_alias_types_same (&htype
, &firsttype
))
1964 first_error (_(type_error
));
1967 count
+= hireg
+ dregs
- getreg
;
1971 /* If we're using Q registers, we can't use [] or [n] syntax. */
1972 if (rtype
== REG_TYPE_NQ
)
1978 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1982 else if (lane
!= atype
.index
)
1984 first_error (_(type_error
));
1988 else if (lane
== -1)
1989 lane
= NEON_INTERLEAVE_LANES
;
1990 else if (lane
!= NEON_INTERLEAVE_LANES
)
1992 first_error (_(type_error
));
1997 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1999 /* No lane set by [x]. We must be interleaving structures. */
2001 lane
= NEON_INTERLEAVE_LANES
;
2004 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2005 || (count
> 1 && reg_incr
== -1))
2007 first_error (_("error parsing element/structure list"));
2011 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2013 first_error (_("expected }"));
2021 *eltype
= firsttype
.eltype
;
2026 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2029 /* Parse an explicit relocation suffix on an expression. This is
2030 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2031 arm_reloc_hsh contains no entries, so this function can only
2032 succeed if there is no () after the word. Returns -1 on error,
2033 BFD_RELOC_UNUSED if there wasn't any suffix. */
2035 parse_reloc (char **str
)
2037 struct reloc_entry
*r
;
2041 return BFD_RELOC_UNUSED
;
2046 while (*q
&& *q
!= ')' && *q
!= ',')
2051 if ((r
= (struct reloc_entry
*)
2052 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2059 /* Directives: register aliases. */
2061 static struct reg_entry
*
2062 insert_reg_alias (char *str
, int number
, int type
)
2064 struct reg_entry
*new_reg
;
2067 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2069 if (new_reg
->builtin
)
2070 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2072 /* Only warn about a redefinition if it's not defined as the
2074 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2075 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2080 name
= xstrdup (str
);
2081 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2083 new_reg
->name
= name
;
2084 new_reg
->number
= number
;
2085 new_reg
->type
= type
;
2086 new_reg
->builtin
= FALSE
;
2087 new_reg
->neon
= NULL
;
2089 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2096 insert_neon_reg_alias (char *str
, int number
, int type
,
2097 struct neon_typed_alias
*atype
)
2099 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2103 first_error (_("attempt to redefine typed alias"));
2109 reg
->neon
= (struct neon_typed_alias
*)
2110 xmalloc (sizeof (struct neon_typed_alias
));
2111 *reg
->neon
= *atype
;
2115 /* Look for the .req directive. This is of the form:
2117 new_register_name .req existing_register_name
2119 If we find one, or if it looks sufficiently like one that we want to
2120 handle any error here, return TRUE. Otherwise return FALSE. */
2123 create_register_alias (char * newname
, char *p
)
2125 struct reg_entry
*old
;
2126 char *oldname
, *nbuf
;
2129 /* The input scrubber ensures that whitespace after the mnemonic is
2130 collapsed to single spaces. */
2132 if (strncmp (oldname
, " .req ", 6) != 0)
2136 if (*oldname
== '\0')
2139 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2142 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2146 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2147 the desired alias name, and p points to its end. If not, then
2148 the desired alias name is in the global original_case_string. */
2149 #ifdef TC_CASE_SENSITIVE
2152 newname
= original_case_string
;
2153 nlen
= strlen (newname
);
2156 nbuf
= (char *) alloca (nlen
+ 1);
2157 memcpy (nbuf
, newname
, nlen
);
2160 /* Create aliases under the new name as stated; an all-lowercase
2161 version of the new name; and an all-uppercase version of the new
2163 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2165 for (p
= nbuf
; *p
; p
++)
2168 if (strncmp (nbuf
, newname
, nlen
))
2170 /* If this attempt to create an additional alias fails, do not bother
2171 trying to create the all-lower case alias. We will fail and issue
2172 a second, duplicate error message. This situation arises when the
2173 programmer does something like:
2176 The second .req creates the "Foo" alias but then fails to create
2177 the artificial FOO alias because it has already been created by the
2179 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2183 for (p
= nbuf
; *p
; p
++)
2186 if (strncmp (nbuf
, newname
, nlen
))
2187 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2193 /* Create a Neon typed/indexed register alias using directives, e.g.:
2198 These typed registers can be used instead of the types specified after the
2199 Neon mnemonic, so long as all operands given have types. Types can also be
2200 specified directly, e.g.:
2201 vadd d0.s32, d1.s32, d2.s32 */
2204 create_neon_reg_alias (char *newname
, char *p
)
2206 enum arm_reg_type basetype
;
2207 struct reg_entry
*basereg
;
2208 struct reg_entry mybasereg
;
2209 struct neon_type ntype
;
2210 struct neon_typed_alias typeinfo
;
2211 char *namebuf
, *nameend
;
2214 typeinfo
.defined
= 0;
2215 typeinfo
.eltype
.type
= NT_invtype
;
2216 typeinfo
.eltype
.size
= -1;
2217 typeinfo
.index
= -1;
2221 if (strncmp (p
, " .dn ", 5) == 0)
2222 basetype
= REG_TYPE_VFD
;
2223 else if (strncmp (p
, " .qn ", 5) == 0)
2224 basetype
= REG_TYPE_NQ
;
2233 basereg
= arm_reg_parse_multi (&p
);
2235 if (basereg
&& basereg
->type
!= basetype
)
2237 as_bad (_("bad type for register"));
2241 if (basereg
== NULL
)
2244 /* Try parsing as an integer. */
2245 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2246 if (exp
.X_op
!= O_constant
)
2248 as_bad (_("expression must be constant"));
2251 basereg
= &mybasereg
;
2252 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2258 typeinfo
= *basereg
->neon
;
2260 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2262 /* We got a type. */
2263 if (typeinfo
.defined
& NTA_HASTYPE
)
2265 as_bad (_("can't redefine the type of a register alias"));
2269 typeinfo
.defined
|= NTA_HASTYPE
;
2270 if (ntype
.elems
!= 1)
2272 as_bad (_("you must specify a single type only"));
2275 typeinfo
.eltype
= ntype
.el
[0];
2278 if (skip_past_char (&p
, '[') == SUCCESS
)
2281 /* We got a scalar index. */
2283 if (typeinfo
.defined
& NTA_HASINDEX
)
2285 as_bad (_("can't redefine the index of a scalar alias"));
2289 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2291 if (exp
.X_op
!= O_constant
)
2293 as_bad (_("scalar index must be constant"));
2297 typeinfo
.defined
|= NTA_HASINDEX
;
2298 typeinfo
.index
= exp
.X_add_number
;
2300 if (skip_past_char (&p
, ']') == FAIL
)
2302 as_bad (_("expecting ]"));
2307 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2308 the desired alias name, and p points to its end. If not, then
2309 the desired alias name is in the global original_case_string. */
2310 #ifdef TC_CASE_SENSITIVE
2311 namelen
= nameend
- newname
;
2313 newname
= original_case_string
;
2314 namelen
= strlen (newname
);
2317 namebuf
= (char *) alloca (namelen
+ 1);
2318 strncpy (namebuf
, newname
, namelen
);
2319 namebuf
[namelen
] = '\0';
2321 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2322 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2324 /* Insert name in all uppercase. */
2325 for (p
= namebuf
; *p
; p
++)
2328 if (strncmp (namebuf
, newname
, namelen
))
2329 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2330 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2332 /* Insert name in all lowercase. */
2333 for (p
= namebuf
; *p
; p
++)
2336 if (strncmp (namebuf
, newname
, namelen
))
2337 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2338 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2343 /* Should never be called, as .req goes between the alias and the
2344 register name, not at the beginning of the line. */
2347 s_req (int a ATTRIBUTE_UNUSED
)
2349 as_bad (_("invalid syntax for .req directive"));
2353 s_dn (int a ATTRIBUTE_UNUSED
)
2355 as_bad (_("invalid syntax for .dn directive"));
2359 s_qn (int a ATTRIBUTE_UNUSED
)
2361 as_bad (_("invalid syntax for .qn directive"));
2364 /* The .unreq directive deletes an alias which was previously defined
2365 by .req. For example:
2371 s_unreq (int a ATTRIBUTE_UNUSED
)
2376 name
= input_line_pointer
;
2378 while (*input_line_pointer
!= 0
2379 && *input_line_pointer
!= ' '
2380 && *input_line_pointer
!= '\n')
2381 ++input_line_pointer
;
2383 saved_char
= *input_line_pointer
;
2384 *input_line_pointer
= 0;
2387 as_bad (_("invalid syntax for .unreq directive"));
2390 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2394 as_bad (_("unknown register alias '%s'"), name
);
2395 else if (reg
->builtin
)
2396 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2403 hash_delete (arm_reg_hsh
, name
, FALSE
);
2404 free ((char *) reg
->name
);
2409 /* Also locate the all upper case and all lower case versions.
2410 Do not complain if we cannot find one or the other as it
2411 was probably deleted above. */
2413 nbuf
= strdup (name
);
2414 for (p
= nbuf
; *p
; p
++)
2416 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2419 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2420 free ((char *) reg
->name
);
2426 for (p
= nbuf
; *p
; p
++)
2428 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2431 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2432 free ((char *) reg
->name
);
2442 *input_line_pointer
= saved_char
;
2443 demand_empty_rest_of_line ();
2446 /* Directives: Instruction set selection. */
2449 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2450 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2451 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2452 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2454 /* Create a new mapping symbol for the transition to STATE. */
2457 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2460 const char * symname
;
2467 type
= BSF_NO_FLAGS
;
2471 type
= BSF_NO_FLAGS
;
2475 type
= BSF_NO_FLAGS
;
2481 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2482 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2487 THUMB_SET_FUNC (symbolP
, 0);
2488 ARM_SET_THUMB (symbolP
, 0);
2489 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2493 THUMB_SET_FUNC (symbolP
, 1);
2494 ARM_SET_THUMB (symbolP
, 1);
2495 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2503 /* Save the mapping symbols for future reference. Also check that
2504 we do not place two mapping symbols at the same offset within a
2505 frag. We'll handle overlap between frags in
2506 check_mapping_symbols.
2508 If .fill or other data filling directive generates zero sized data,
2509 the mapping symbol for the following code will have the same value
2510 as the one generated for the data filling directive. In this case,
2511 we replace the old symbol with the new one at the same address. */
2514 if (frag
->tc_frag_data
.first_map
!= NULL
)
2516 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2517 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2519 frag
->tc_frag_data
.first_map
= symbolP
;
2521 if (frag
->tc_frag_data
.last_map
!= NULL
)
2523 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2524 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2525 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2527 frag
->tc_frag_data
.last_map
= symbolP
;
2530 /* We must sometimes convert a region marked as code to data during
2531 code alignment, if an odd number of bytes have to be padded. The
2532 code mapping symbol is pushed to an aligned address. */
2535 insert_data_mapping_symbol (enum mstate state
,
2536 valueT value
, fragS
*frag
, offsetT bytes
)
2538 /* If there was already a mapping symbol, remove it. */
2539 if (frag
->tc_frag_data
.last_map
!= NULL
2540 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2542 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2546 know (frag
->tc_frag_data
.first_map
== symp
);
2547 frag
->tc_frag_data
.first_map
= NULL
;
2549 frag
->tc_frag_data
.last_map
= NULL
;
2550 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2553 make_mapping_symbol (MAP_DATA
, value
, frag
);
2554 make_mapping_symbol (state
, value
+ bytes
, frag
);
2557 static void mapping_state_2 (enum mstate state
, int max_chars
);
2559 /* Set the mapping state to STATE. Only call this when about to
2560 emit some STATE bytes to the file. */
2563 mapping_state (enum mstate state
)
2565 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2567 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2569 if (mapstate
== state
)
2570 /* The mapping symbol has already been emitted.
2571 There is nothing else to do. */
2573 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2574 /* This case will be evaluated later in the next else. */
2576 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2577 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2579 /* Only add the symbol if the offset is > 0:
2580 if we're at the first frag, check it's size > 0;
2581 if we're not at the first frag, then for sure
2582 the offset is > 0. */
2583 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2584 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2587 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2590 mapping_state_2 (state
, 0);
2594 /* Same as mapping_state, but MAX_CHARS bytes have already been
2595 allocated. Put the mapping symbol that far back. */
2598 mapping_state_2 (enum mstate state
, int max_chars
)
2600 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2602 if (!SEG_NORMAL (now_seg
))
2605 if (mapstate
== state
)
2606 /* The mapping symbol has already been emitted.
2607 There is nothing else to do. */
2610 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2611 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2614 #define mapping_state(x) ((void)0)
2615 #define mapping_state_2(x, y) ((void)0)
2618 /* Find the real, Thumb encoded start of a Thumb function. */
2622 find_real_start (symbolS
* symbolP
)
2625 const char * name
= S_GET_NAME (symbolP
);
2626 symbolS
* new_target
;
2628 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2629 #define STUB_NAME ".real_start_of"
2634 /* The compiler may generate BL instructions to local labels because
2635 it needs to perform a branch to a far away location. These labels
2636 do not have a corresponding ".real_start_of" label. We check
2637 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2638 the ".real_start_of" convention for nonlocal branches. */
2639 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2642 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2643 new_target
= symbol_find (real_start
);
2645 if (new_target
== NULL
)
2647 as_warn (_("Failed to find real start of function: %s\n"), name
);
2648 new_target
= symbolP
;
2656 opcode_select (int width
)
2663 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2664 as_bad (_("selected processor does not support THUMB opcodes"));
2667 /* No need to force the alignment, since we will have been
2668 coming from ARM mode, which is word-aligned. */
2669 record_alignment (now_seg
, 1);
2676 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2677 as_bad (_("selected processor does not support ARM opcodes"));
2682 frag_align (2, 0, 0);
2684 record_alignment (now_seg
, 1);
2689 as_bad (_("invalid instruction size selected (%d)"), width
);
2694 s_arm (int ignore ATTRIBUTE_UNUSED
)
2697 demand_empty_rest_of_line ();
2701 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2704 demand_empty_rest_of_line ();
2708 s_code (int unused ATTRIBUTE_UNUSED
)
2712 temp
= get_absolute_expression ();
2717 opcode_select (temp
);
2721 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2726 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2728 /* If we are not already in thumb mode go into it, EVEN if
2729 the target processor does not support thumb instructions.
2730 This is used by gcc/config/arm/lib1funcs.asm for example
2731 to compile interworking support functions even if the
2732 target processor should not support interworking. */
2736 record_alignment (now_seg
, 1);
2739 demand_empty_rest_of_line ();
2743 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2747 /* The following label is the name/address of the start of a Thumb function.
2748 We need to know this for the interworking support. */
2749 label_is_thumb_function_name
= TRUE
;
2752 /* Perform a .set directive, but also mark the alias as
2753 being a thumb function. */
2756 s_thumb_set (int equiv
)
2758 /* XXX the following is a duplicate of the code for s_set() in read.c
2759 We cannot just call that code as we need to get at the symbol that
2766 /* Especial apologies for the random logic:
2767 This just grew, and could be parsed much more simply!
2769 name
= input_line_pointer
;
2770 delim
= get_symbol_end ();
2771 end_name
= input_line_pointer
;
2774 if (*input_line_pointer
!= ',')
2777 as_bad (_("expected comma after name \"%s\""), name
);
2779 ignore_rest_of_line ();
2783 input_line_pointer
++;
2786 if (name
[0] == '.' && name
[1] == '\0')
2788 /* XXX - this should not happen to .thumb_set. */
2792 if ((symbolP
= symbol_find (name
)) == NULL
2793 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2796 /* When doing symbol listings, play games with dummy fragments living
2797 outside the normal fragment chain to record the file and line info
2799 if (listing
& LISTING_SYMBOLS
)
2801 extern struct list_info_struct
* listing_tail
;
2802 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2804 memset (dummy_frag
, 0, sizeof (fragS
));
2805 dummy_frag
->fr_type
= rs_fill
;
2806 dummy_frag
->line
= listing_tail
;
2807 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2808 dummy_frag
->fr_symbol
= symbolP
;
2812 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2815 /* "set" symbols are local unless otherwise specified. */
2816 SF_SET_LOCAL (symbolP
);
2817 #endif /* OBJ_COFF */
2818 } /* Make a new symbol. */
2820 symbol_table_insert (symbolP
);
2825 && S_IS_DEFINED (symbolP
)
2826 && S_GET_SEGMENT (symbolP
) != reg_section
)
2827 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2829 pseudo_set (symbolP
);
2831 demand_empty_rest_of_line ();
2833 /* XXX Now we come to the Thumb specific bit of code. */
2835 THUMB_SET_FUNC (symbolP
, 1);
2836 ARM_SET_THUMB (symbolP
, 1);
2837 #if defined OBJ_ELF || defined OBJ_COFF
2838 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2842 /* Directives: Mode selection. */
2844 /* .syntax [unified|divided] - choose the new unified syntax
2845 (same for Arm and Thumb encoding, modulo slight differences in what
2846 can be represented) or the old divergent syntax for each mode. */
2848 s_syntax (int unused ATTRIBUTE_UNUSED
)
2852 name
= input_line_pointer
;
2853 delim
= get_symbol_end ();
2855 if (!strcasecmp (name
, "unified"))
2856 unified_syntax
= TRUE
;
2857 else if (!strcasecmp (name
, "divided"))
2858 unified_syntax
= FALSE
;
2861 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2864 *input_line_pointer
= delim
;
2865 demand_empty_rest_of_line ();
2868 /* Directives: sectioning and alignment. */
2870 /* Same as s_align_ptwo but align 0 => align 2. */
2873 s_align (int unused ATTRIBUTE_UNUSED
)
2878 long max_alignment
= 15;
2880 temp
= get_absolute_expression ();
2881 if (temp
> max_alignment
)
2882 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2885 as_bad (_("alignment negative. 0 assumed."));
2889 if (*input_line_pointer
== ',')
2891 input_line_pointer
++;
2892 temp_fill
= get_absolute_expression ();
2904 /* Only make a frag if we HAVE to. */
2905 if (temp
&& !need_pass_2
)
2907 if (!fill_p
&& subseg_text_p (now_seg
))
2908 frag_align_code (temp
, 0);
2910 frag_align (temp
, (int) temp_fill
, 0);
2912 demand_empty_rest_of_line ();
2914 record_alignment (now_seg
, temp
);
2918 s_bss (int ignore ATTRIBUTE_UNUSED
)
2920 /* We don't support putting frags in the BSS segment, we fake it by
2921 marking in_bss, then looking at s_skip for clues. */
2922 subseg_set (bss_section
, 0);
2923 demand_empty_rest_of_line ();
2925 #ifdef md_elf_section_change_hook
2926 md_elf_section_change_hook ();
2931 s_even (int ignore ATTRIBUTE_UNUSED
)
2933 /* Never make frag if expect extra pass. */
2935 frag_align (1, 0, 0);
2937 record_alignment (now_seg
, 1);
2939 demand_empty_rest_of_line ();
2942 /* Directives: Literal pools. */
2944 static literal_pool
*
2945 find_literal_pool (void)
2947 literal_pool
* pool
;
2949 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2951 if (pool
->section
== now_seg
2952 && pool
->sub_section
== now_subseg
)
2959 static literal_pool
*
2960 find_or_make_literal_pool (void)
2962 /* Next literal pool ID number. */
2963 static unsigned int latest_pool_num
= 1;
2964 literal_pool
* pool
;
2966 pool
= find_literal_pool ();
2970 /* Create a new pool. */
2971 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2975 pool
->next_free_entry
= 0;
2976 pool
->section
= now_seg
;
2977 pool
->sub_section
= now_subseg
;
2978 pool
->next
= list_of_pools
;
2979 pool
->symbol
= NULL
;
2981 /* Add it to the list. */
2982 list_of_pools
= pool
;
2985 /* New pools, and emptied pools, will have a NULL symbol. */
2986 if (pool
->symbol
== NULL
)
2988 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2989 (valueT
) 0, &zero_address_frag
);
2990 pool
->id
= latest_pool_num
++;
2997 /* Add the literal in the global 'inst'
2998 structure to the relevant literal pool. */
3001 add_to_lit_pool (void)
3003 literal_pool
* pool
;
3006 pool
= find_or_make_literal_pool ();
3008 /* Check if this literal value is already in the pool. */
3009 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3011 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3012 && (inst
.reloc
.exp
.X_op
== O_constant
)
3013 && (pool
->literals
[entry
].X_add_number
3014 == inst
.reloc
.exp
.X_add_number
)
3015 && (pool
->literals
[entry
].X_unsigned
3016 == inst
.reloc
.exp
.X_unsigned
))
3019 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3020 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3021 && (pool
->literals
[entry
].X_add_number
3022 == inst
.reloc
.exp
.X_add_number
)
3023 && (pool
->literals
[entry
].X_add_symbol
3024 == inst
.reloc
.exp
.X_add_symbol
)
3025 && (pool
->literals
[entry
].X_op_symbol
3026 == inst
.reloc
.exp
.X_op_symbol
))
3030 /* Do we need to create a new entry? */
3031 if (entry
== pool
->next_free_entry
)
3033 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3035 inst
.error
= _("literal pool overflow");
3039 pool
->literals
[entry
] = inst
.reloc
.exp
;
3040 pool
->next_free_entry
+= 1;
3043 inst
.reloc
.exp
.X_op
= O_symbol
;
3044 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3045 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3050 /* Can't use symbol_new here, so have to create a symbol and then at
3051 a later date assign it a value. Thats what these functions do. */
3054 symbol_locate (symbolS
* symbolP
,
3055 const char * name
, /* It is copied, the caller can modify. */
3056 segT segment
, /* Segment identifier (SEG_<something>). */
3057 valueT valu
, /* Symbol value. */
3058 fragS
* frag
) /* Associated fragment. */
3060 unsigned int name_length
;
3061 char * preserved_copy_of_name
;
3063 name_length
= strlen (name
) + 1; /* +1 for \0. */
3064 obstack_grow (¬es
, name
, name_length
);
3065 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3067 #ifdef tc_canonicalize_symbol_name
3068 preserved_copy_of_name
=
3069 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3072 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3074 S_SET_SEGMENT (symbolP
, segment
);
3075 S_SET_VALUE (symbolP
, valu
);
3076 symbol_clear_list_pointers (symbolP
);
3078 symbol_set_frag (symbolP
, frag
);
3080 /* Link to end of symbol chain. */
3082 extern int symbol_table_frozen
;
3084 if (symbol_table_frozen
)
3088 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3090 obj_symbol_new_hook (symbolP
);
3092 #ifdef tc_symbol_new_hook
3093 tc_symbol_new_hook (symbolP
);
3097 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3098 #endif /* DEBUG_SYMS */
3103 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3106 literal_pool
* pool
;
3109 pool
= find_literal_pool ();
3111 || pool
->symbol
== NULL
3112 || pool
->next_free_entry
== 0)
3115 mapping_state (MAP_DATA
);
3117 /* Align pool as you have word accesses.
3118 Only make a frag if we have to. */
3120 frag_align (2, 0, 0);
3122 record_alignment (now_seg
, 2);
3124 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3126 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3127 (valueT
) frag_now_fix (), frag_now
);
3128 symbol_table_insert (pool
->symbol
);
3130 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3132 #if defined OBJ_COFF || defined OBJ_ELF
3133 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3136 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3137 /* First output the expression in the instruction to the pool. */
3138 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3140 /* Mark the pool as empty. */
3141 pool
->next_free_entry
= 0;
3142 pool
->symbol
= NULL
;
3146 /* Forward declarations for functions below, in the MD interface
3148 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3149 static valueT
create_unwind_entry (int);
3150 static void start_unwind_section (const segT
, int);
3151 static void add_unwind_opcode (valueT
, int);
3152 static void flush_pending_unwind (void);
3154 /* Directives: Data. */
3157 s_arm_elf_cons (int nbytes
)
3161 #ifdef md_flush_pending_output
3162 md_flush_pending_output ();
3165 if (is_it_end_of_statement ())
3167 demand_empty_rest_of_line ();
3171 #ifdef md_cons_align
3172 md_cons_align (nbytes
);
3175 mapping_state (MAP_DATA
);
3179 char *base
= input_line_pointer
;
3183 if (exp
.X_op
!= O_symbol
)
3184 emit_expr (&exp
, (unsigned int) nbytes
);
3187 char *before_reloc
= input_line_pointer
;
3188 reloc
= parse_reloc (&input_line_pointer
);
3191 as_bad (_("unrecognized relocation suffix"));
3192 ignore_rest_of_line ();
3195 else if (reloc
== BFD_RELOC_UNUSED
)
3196 emit_expr (&exp
, (unsigned int) nbytes
);
3199 reloc_howto_type
*howto
= (reloc_howto_type
*)
3200 bfd_reloc_type_lookup (stdoutput
,
3201 (bfd_reloc_code_real_type
) reloc
);
3202 int size
= bfd_get_reloc_size (howto
);
3204 if (reloc
== BFD_RELOC_ARM_PLT32
)
3206 as_bad (_("(plt) is only valid on branch targets"));
3207 reloc
= BFD_RELOC_UNUSED
;
3212 as_bad (_("%s relocations do not fit in %d bytes"),
3213 howto
->name
, nbytes
);
3216 /* We've parsed an expression stopping at O_symbol.
3217 But there may be more expression left now that we
3218 have parsed the relocation marker. Parse it again.
3219 XXX Surely there is a cleaner way to do this. */
3220 char *p
= input_line_pointer
;
3222 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3223 memcpy (save_buf
, base
, input_line_pointer
- base
);
3224 memmove (base
+ (input_line_pointer
- before_reloc
),
3225 base
, before_reloc
- base
);
3227 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3229 memcpy (base
, save_buf
, p
- base
);
3231 offset
= nbytes
- size
;
3232 p
= frag_more ((int) nbytes
);
3233 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3234 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3239 while (*input_line_pointer
++ == ',');
3241 /* Put terminator back into stream. */
3242 input_line_pointer
--;
3243 demand_empty_rest_of_line ();
3246 /* Emit an expression containing a 32-bit thumb instruction.
3247 Implementation based on put_thumb32_insn. */
3250 emit_thumb32_expr (expressionS
* exp
)
3252 expressionS exp_high
= *exp
;
3254 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3255 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3256 exp
->X_add_number
&= 0xffff;
3257 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3260 /* Guess the instruction size based on the opcode. */
3263 thumb_insn_size (int opcode
)
3265 if ((unsigned int) opcode
< 0xe800u
)
3267 else if ((unsigned int) opcode
>= 0xe8000000u
)
3274 emit_insn (expressionS
*exp
, int nbytes
)
3278 if (exp
->X_op
== O_constant
)
3283 size
= thumb_insn_size (exp
->X_add_number
);
3287 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3289 as_bad (_(".inst.n operand too big. "\
3290 "Use .inst.w instead"));
3295 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3296 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3298 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3300 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3301 emit_thumb32_expr (exp
);
3303 emit_expr (exp
, (unsigned int) size
);
3305 it_fsm_post_encode ();
3309 as_bad (_("cannot determine Thumb instruction size. " \
3310 "Use .inst.n/.inst.w instead"));
3313 as_bad (_("constant expression required"));
3318 /* Like s_arm_elf_cons but do not use md_cons_align and
3319 set the mapping state to MAP_ARM/MAP_THUMB. */
3322 s_arm_elf_inst (int nbytes
)
3324 if (is_it_end_of_statement ())
3326 demand_empty_rest_of_line ();
3330 /* Calling mapping_state () here will not change ARM/THUMB,
3331 but will ensure not to be in DATA state. */
3334 mapping_state (MAP_THUMB
);
3339 as_bad (_("width suffixes are invalid in ARM mode"));
3340 ignore_rest_of_line ();
3346 mapping_state (MAP_ARM
);
3355 if (! emit_insn (& exp
, nbytes
))
3357 ignore_rest_of_line ();
3361 while (*input_line_pointer
++ == ',');
3363 /* Put terminator back into stream. */
3364 input_line_pointer
--;
3365 demand_empty_rest_of_line ();
3368 /* Parse a .rel31 directive. */
3371 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3378 if (*input_line_pointer
== '1')
3379 highbit
= 0x80000000;
3380 else if (*input_line_pointer
!= '0')
3381 as_bad (_("expected 0 or 1"));
3383 input_line_pointer
++;
3384 if (*input_line_pointer
!= ',')
3385 as_bad (_("missing comma"));
3386 input_line_pointer
++;
3388 #ifdef md_flush_pending_output
3389 md_flush_pending_output ();
3392 #ifdef md_cons_align
3396 mapping_state (MAP_DATA
);
3401 md_number_to_chars (p
, highbit
, 4);
3402 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3403 BFD_RELOC_ARM_PREL31
);
3405 demand_empty_rest_of_line ();
3408 /* Directives: AEABI stack-unwind tables. */
3410 /* Parse an unwind_fnstart directive. Simply records the current location. */
3413 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3415 demand_empty_rest_of_line ();
3416 if (unwind
.proc_start
)
3418 as_bad (_("duplicate .fnstart directive"));
3422 /* Mark the start of the function. */
3423 unwind
.proc_start
= expr_build_dot ();
3425 /* Reset the rest of the unwind info. */
3426 unwind
.opcode_count
= 0;
3427 unwind
.table_entry
= NULL
;
3428 unwind
.personality_routine
= NULL
;
3429 unwind
.personality_index
= -1;
3430 unwind
.frame_size
= 0;
3431 unwind
.fp_offset
= 0;
3432 unwind
.fp_reg
= REG_SP
;
3434 unwind
.sp_restored
= 0;
3438 /* Parse a handlerdata directive. Creates the exception handling table entry
3439 for the function. */
3442 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3444 demand_empty_rest_of_line ();
3445 if (!unwind
.proc_start
)
3446 as_bad (MISSING_FNSTART
);
3448 if (unwind
.table_entry
)
3449 as_bad (_("duplicate .handlerdata directive"));
3451 create_unwind_entry (1);
3454 /* Parse an unwind_fnend directive. Generates the index table entry. */
3457 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3462 unsigned int marked_pr_dependency
;
3464 demand_empty_rest_of_line ();
3466 if (!unwind
.proc_start
)
3468 as_bad (_(".fnend directive without .fnstart"));
3472 /* Add eh table entry. */
3473 if (unwind
.table_entry
== NULL
)
3474 val
= create_unwind_entry (0);
3478 /* Add index table entry. This is two words. */
3479 start_unwind_section (unwind
.saved_seg
, 1);
3480 frag_align (2, 0, 0);
3481 record_alignment (now_seg
, 2);
3483 ptr
= frag_more (8);
3484 where
= frag_now_fix () - 8;
3486 /* Self relative offset of the function start. */
3487 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3488 BFD_RELOC_ARM_PREL31
);
3490 /* Indicate dependency on EHABI-defined personality routines to the
3491 linker, if it hasn't been done already. */
3492 marked_pr_dependency
3493 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3494 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3495 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3497 static const char *const name
[] =
3499 "__aeabi_unwind_cpp_pr0",
3500 "__aeabi_unwind_cpp_pr1",
3501 "__aeabi_unwind_cpp_pr2"
3503 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3504 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3505 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3506 |= 1 << unwind
.personality_index
;
3510 /* Inline exception table entry. */
3511 md_number_to_chars (ptr
+ 4, val
, 4);
3513 /* Self relative offset of the table entry. */
3514 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3515 BFD_RELOC_ARM_PREL31
);
3517 /* Restore the original section. */
3518 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3520 unwind
.proc_start
= NULL
;
3524 /* Parse an unwind_cantunwind directive. */
3527 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3529 demand_empty_rest_of_line ();
3530 if (!unwind
.proc_start
)
3531 as_bad (MISSING_FNSTART
);
3533 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3534 as_bad (_("personality routine specified for cantunwind frame"));
3536 unwind
.personality_index
= -2;
3540 /* Parse a personalityindex directive. */
3543 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3547 if (!unwind
.proc_start
)
3548 as_bad (MISSING_FNSTART
);
3550 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3551 as_bad (_("duplicate .personalityindex directive"));
3555 if (exp
.X_op
!= O_constant
3556 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3558 as_bad (_("bad personality routine number"));
3559 ignore_rest_of_line ();
3563 unwind
.personality_index
= exp
.X_add_number
;
3565 demand_empty_rest_of_line ();
3569 /* Parse a personality directive. */
3572 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3576 if (!unwind
.proc_start
)
3577 as_bad (MISSING_FNSTART
);
3579 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3580 as_bad (_("duplicate .personality directive"));
3582 name
= input_line_pointer
;
3583 c
= get_symbol_end ();
3584 p
= input_line_pointer
;
3585 unwind
.personality_routine
= symbol_find_or_make (name
);
3587 demand_empty_rest_of_line ();
3591 /* Parse a directive saving core registers. */
3594 s_arm_unwind_save_core (void)
3600 range
= parse_reg_list (&input_line_pointer
);
3603 as_bad (_("expected register list"));
3604 ignore_rest_of_line ();
3608 demand_empty_rest_of_line ();
3610 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3611 into .unwind_save {..., sp...}. We aren't bothered about the value of
3612 ip because it is clobbered by calls. */
3613 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3614 && (range
& 0x3000) == 0x1000)
3616 unwind
.opcode_count
--;
3617 unwind
.sp_restored
= 0;
3618 range
= (range
| 0x2000) & ~0x1000;
3619 unwind
.pending_offset
= 0;
3625 /* See if we can use the short opcodes. These pop a block of up to 8
3626 registers starting with r4, plus maybe r14. */
3627 for (n
= 0; n
< 8; n
++)
3629 /* Break at the first non-saved register. */
3630 if ((range
& (1 << (n
+ 4))) == 0)
3633 /* See if there are any other bits set. */
3634 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3636 /* Use the long form. */
3637 op
= 0x8000 | ((range
>> 4) & 0xfff);
3638 add_unwind_opcode (op
, 2);
3642 /* Use the short form. */
3644 op
= 0xa8; /* Pop r14. */
3646 op
= 0xa0; /* Do not pop r14. */
3648 add_unwind_opcode (op
, 1);
3655 op
= 0xb100 | (range
& 0xf);
3656 add_unwind_opcode (op
, 2);
3659 /* Record the number of bytes pushed. */
3660 for (n
= 0; n
< 16; n
++)
3662 if (range
& (1 << n
))
3663 unwind
.frame_size
+= 4;
3668 /* Parse a directive saving FPA registers. */
3671 s_arm_unwind_save_fpa (int reg
)
3677 /* Get Number of registers to transfer. */
3678 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3681 exp
.X_op
= O_illegal
;
3683 if (exp
.X_op
!= O_constant
)
3685 as_bad (_("expected , <constant>"));
3686 ignore_rest_of_line ();
3690 num_regs
= exp
.X_add_number
;
3692 if (num_regs
< 1 || num_regs
> 4)
3694 as_bad (_("number of registers must be in the range [1:4]"));
3695 ignore_rest_of_line ();
3699 demand_empty_rest_of_line ();
3704 op
= 0xb4 | (num_regs
- 1);
3705 add_unwind_opcode (op
, 1);
3710 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3711 add_unwind_opcode (op
, 2);
3713 unwind
.frame_size
+= num_regs
* 12;
3717 /* Parse a directive saving VFP registers for ARMv6 and above. */
3720 s_arm_unwind_save_vfp_armv6 (void)
3725 int num_vfpv3_regs
= 0;
3726 int num_regs_below_16
;
3728 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3731 as_bad (_("expected register list"));
3732 ignore_rest_of_line ();
3736 demand_empty_rest_of_line ();
3738 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3739 than FSTMX/FLDMX-style ones). */
3741 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3743 num_vfpv3_regs
= count
;
3744 else if (start
+ count
> 16)
3745 num_vfpv3_regs
= start
+ count
- 16;
3747 if (num_vfpv3_regs
> 0)
3749 int start_offset
= start
> 16 ? start
- 16 : 0;
3750 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3751 add_unwind_opcode (op
, 2);
3754 /* Generate opcode for registers numbered in the range 0 .. 15. */
3755 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3756 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3757 if (num_regs_below_16
> 0)
3759 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3760 add_unwind_opcode (op
, 2);
3763 unwind
.frame_size
+= count
* 8;
3767 /* Parse a directive saving VFP registers for pre-ARMv6. */
3770 s_arm_unwind_save_vfp (void)
3776 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3779 as_bad (_("expected register list"));
3780 ignore_rest_of_line ();
3784 demand_empty_rest_of_line ();
3789 op
= 0xb8 | (count
- 1);
3790 add_unwind_opcode (op
, 1);
3795 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3796 add_unwind_opcode (op
, 2);
3798 unwind
.frame_size
+= count
* 8 + 4;
3802 /* Parse a directive saving iWMMXt data registers. */
3805 s_arm_unwind_save_mmxwr (void)
3813 if (*input_line_pointer
== '{')
3814 input_line_pointer
++;
3818 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3822 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3827 as_tsktsk (_("register list not in ascending order"));
3830 if (*input_line_pointer
== '-')
3832 input_line_pointer
++;
3833 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3836 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3839 else if (reg
>= hi_reg
)
3841 as_bad (_("bad register range"));
3844 for (; reg
< hi_reg
; reg
++)
3848 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3850 if (*input_line_pointer
== '}')
3851 input_line_pointer
++;
3853 demand_empty_rest_of_line ();
3855 /* Generate any deferred opcodes because we're going to be looking at
3857 flush_pending_unwind ();
3859 for (i
= 0; i
< 16; i
++)
3861 if (mask
& (1 << i
))
3862 unwind
.frame_size
+= 8;
3865 /* Attempt to combine with a previous opcode. We do this because gcc
3866 likes to output separate unwind directives for a single block of
3868 if (unwind
.opcode_count
> 0)
3870 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3871 if ((i
& 0xf8) == 0xc0)
3874 /* Only merge if the blocks are contiguous. */
3877 if ((mask
& 0xfe00) == (1 << 9))
3879 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3880 unwind
.opcode_count
--;
3883 else if (i
== 6 && unwind
.opcode_count
>= 2)
3885 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3889 op
= 0xffff << (reg
- 1);
3891 && ((mask
& op
) == (1u << (reg
- 1))))
3893 op
= (1 << (reg
+ i
+ 1)) - 1;
3894 op
&= ~((1 << reg
) - 1);
3896 unwind
.opcode_count
-= 2;
3903 /* We want to generate opcodes in the order the registers have been
3904 saved, ie. descending order. */
3905 for (reg
= 15; reg
>= -1; reg
--)
3907 /* Save registers in blocks. */
3909 || !(mask
& (1 << reg
)))
3911 /* We found an unsaved reg. Generate opcodes to save the
3918 op
= 0xc0 | (hi_reg
- 10);
3919 add_unwind_opcode (op
, 1);
3924 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3925 add_unwind_opcode (op
, 2);
3934 ignore_rest_of_line ();
3938 s_arm_unwind_save_mmxwcg (void)
3945 if (*input_line_pointer
== '{')
3946 input_line_pointer
++;
3950 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3954 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3960 as_tsktsk (_("register list not in ascending order"));
3963 if (*input_line_pointer
== '-')
3965 input_line_pointer
++;
3966 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3969 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3972 else if (reg
>= hi_reg
)
3974 as_bad (_("bad register range"));
3977 for (; reg
< hi_reg
; reg
++)
3981 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3983 if (*input_line_pointer
== '}')
3984 input_line_pointer
++;
3986 demand_empty_rest_of_line ();
3988 /* Generate any deferred opcodes because we're going to be looking at
3990 flush_pending_unwind ();
3992 for (reg
= 0; reg
< 16; reg
++)
3994 if (mask
& (1 << reg
))
3995 unwind
.frame_size
+= 4;
3998 add_unwind_opcode (op
, 2);
4001 ignore_rest_of_line ();
4005 /* Parse an unwind_save directive.
4006 If the argument is non-zero, this is a .vsave directive. */
4009 s_arm_unwind_save (int arch_v6
)
4012 struct reg_entry
*reg
;
4013 bfd_boolean had_brace
= FALSE
;
4015 if (!unwind
.proc_start
)
4016 as_bad (MISSING_FNSTART
);
4018 /* Figure out what sort of save we have. */
4019 peek
= input_line_pointer
;
4027 reg
= arm_reg_parse_multi (&peek
);
4031 as_bad (_("register expected"));
4032 ignore_rest_of_line ();
4041 as_bad (_("FPA .unwind_save does not take a register list"));
4042 ignore_rest_of_line ();
4045 input_line_pointer
= peek
;
4046 s_arm_unwind_save_fpa (reg
->number
);
4049 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4052 s_arm_unwind_save_vfp_armv6 ();
4054 s_arm_unwind_save_vfp ();
4056 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4057 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4060 as_bad (_(".unwind_save does not support this kind of register"));
4061 ignore_rest_of_line ();
4066 /* Parse an unwind_movsp directive. */
4069 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4075 if (!unwind
.proc_start
)
4076 as_bad (MISSING_FNSTART
);
4078 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4081 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4082 ignore_rest_of_line ();
4086 /* Optional constant. */
4087 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4089 if (immediate_for_directive (&offset
) == FAIL
)
4095 demand_empty_rest_of_line ();
4097 if (reg
== REG_SP
|| reg
== REG_PC
)
4099 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4103 if (unwind
.fp_reg
!= REG_SP
)
4104 as_bad (_("unexpected .unwind_movsp directive"));
4106 /* Generate opcode to restore the value. */
4108 add_unwind_opcode (op
, 1);
4110 /* Record the information for later. */
4111 unwind
.fp_reg
= reg
;
4112 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4113 unwind
.sp_restored
= 1;
4116 /* Parse an unwind_pad directive. */
4119 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4123 if (!unwind
.proc_start
)
4124 as_bad (MISSING_FNSTART
);
4126 if (immediate_for_directive (&offset
) == FAIL
)
4131 as_bad (_("stack increment must be multiple of 4"));
4132 ignore_rest_of_line ();
4136 /* Don't generate any opcodes, just record the details for later. */
4137 unwind
.frame_size
+= offset
;
4138 unwind
.pending_offset
+= offset
;
4140 demand_empty_rest_of_line ();
4143 /* Parse an unwind_setfp directive. */
4146 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4152 if (!unwind
.proc_start
)
4153 as_bad (MISSING_FNSTART
);
4155 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4156 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4159 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4161 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4163 as_bad (_("expected <reg>, <reg>"));
4164 ignore_rest_of_line ();
4168 /* Optional constant. */
4169 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4171 if (immediate_for_directive (&offset
) == FAIL
)
4177 demand_empty_rest_of_line ();
4179 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4181 as_bad (_("register must be either sp or set by a previous"
4182 "unwind_movsp directive"));
4186 /* Don't generate any opcodes, just record the information for later. */
4187 unwind
.fp_reg
= fp_reg
;
4189 if (sp_reg
== REG_SP
)
4190 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4192 unwind
.fp_offset
-= offset
;
4195 /* Parse an unwind_raw directive. */
4198 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4201 /* This is an arbitrary limit. */
4202 unsigned char op
[16];
4205 if (!unwind
.proc_start
)
4206 as_bad (MISSING_FNSTART
);
4209 if (exp
.X_op
== O_constant
4210 && skip_past_comma (&input_line_pointer
) != FAIL
)
4212 unwind
.frame_size
+= exp
.X_add_number
;
4216 exp
.X_op
= O_illegal
;
4218 if (exp
.X_op
!= O_constant
)
4220 as_bad (_("expected <offset>, <opcode>"));
4221 ignore_rest_of_line ();
4227 /* Parse the opcode. */
4232 as_bad (_("unwind opcode too long"));
4233 ignore_rest_of_line ();
4235 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4237 as_bad (_("invalid unwind opcode"));
4238 ignore_rest_of_line ();
4241 op
[count
++] = exp
.X_add_number
;
4243 /* Parse the next byte. */
4244 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4250 /* Add the opcode bytes in reverse order. */
4252 add_unwind_opcode (op
[count
], 1);
4254 demand_empty_rest_of_line ();
4258 /* Parse a .eabi_attribute directive. */
4261 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4263 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4265 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4266 attributes_set_explicitly
[tag
] = 1;
4268 #endif /* OBJ_ELF */
4270 static void s_arm_arch (int);
4271 static void s_arm_object_arch (int);
4272 static void s_arm_cpu (int);
4273 static void s_arm_fpu (int);
4274 static void s_arm_arch_extension (int);
4279 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4286 if (exp
.X_op
== O_symbol
)
4287 exp
.X_op
= O_secrel
;
4289 emit_expr (&exp
, 4);
4291 while (*input_line_pointer
++ == ',');
4293 input_line_pointer
--;
4294 demand_empty_rest_of_line ();
4298 /* This table describes all the machine specific pseudo-ops the assembler
4299 has to support. The fields are:
4300 pseudo-op name without dot
4301 function to call to execute this pseudo-op
4302 Integer arg to pass to the function. */
4304 const pseudo_typeS md_pseudo_table
[] =
4306 /* Never called because '.req' does not start a line. */
4307 { "req", s_req
, 0 },
4308 /* Following two are likewise never called. */
4311 { "unreq", s_unreq
, 0 },
4312 { "bss", s_bss
, 0 },
4313 { "align", s_align
, 0 },
4314 { "arm", s_arm
, 0 },
4315 { "thumb", s_thumb
, 0 },
4316 { "code", s_code
, 0 },
4317 { "force_thumb", s_force_thumb
, 0 },
4318 { "thumb_func", s_thumb_func
, 0 },
4319 { "thumb_set", s_thumb_set
, 0 },
4320 { "even", s_even
, 0 },
4321 { "ltorg", s_ltorg
, 0 },
4322 { "pool", s_ltorg
, 0 },
4323 { "syntax", s_syntax
, 0 },
4324 { "cpu", s_arm_cpu
, 0 },
4325 { "arch", s_arm_arch
, 0 },
4326 { "object_arch", s_arm_object_arch
, 0 },
4327 { "fpu", s_arm_fpu
, 0 },
4328 { "arch_extension", s_arm_arch_extension
, 0 },
4330 { "word", s_arm_elf_cons
, 4 },
4331 { "long", s_arm_elf_cons
, 4 },
4332 { "inst.n", s_arm_elf_inst
, 2 },
4333 { "inst.w", s_arm_elf_inst
, 4 },
4334 { "inst", s_arm_elf_inst
, 0 },
4335 { "rel31", s_arm_rel31
, 0 },
4336 { "fnstart", s_arm_unwind_fnstart
, 0 },
4337 { "fnend", s_arm_unwind_fnend
, 0 },
4338 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4339 { "personality", s_arm_unwind_personality
, 0 },
4340 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4341 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4342 { "save", s_arm_unwind_save
, 0 },
4343 { "vsave", s_arm_unwind_save
, 1 },
4344 { "movsp", s_arm_unwind_movsp
, 0 },
4345 { "pad", s_arm_unwind_pad
, 0 },
4346 { "setfp", s_arm_unwind_setfp
, 0 },
4347 { "unwind_raw", s_arm_unwind_raw
, 0 },
4348 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4352 /* These are used for dwarf. */
4356 /* These are used for dwarf2. */
4357 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4358 { "loc", dwarf2_directive_loc
, 0 },
4359 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4361 { "extend", float_cons
, 'x' },
4362 { "ldouble", float_cons
, 'x' },
4363 { "packed", float_cons
, 'p' },
4365 {"secrel32", pe_directive_secrel
, 0},
4370 /* Parser functions used exclusively in instruction operands. */
4372 /* Generic immediate-value read function for use in insn parsing.
4373 STR points to the beginning of the immediate (the leading #);
4374 VAL receives the value; if the value is outside [MIN, MAX]
4375 issue an error. PREFIX_OPT is true if the immediate prefix is
4379 parse_immediate (char **str
, int *val
, int min
, int max
,
4380 bfd_boolean prefix_opt
)
4383 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4384 if (exp
.X_op
!= O_constant
)
4386 inst
.error
= _("constant expression required");
4390 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4392 inst
.error
= _("immediate value out of range");
4396 *val
= exp
.X_add_number
;
4400 /* Less-generic immediate-value read function with the possibility of loading a
4401 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4402 instructions. Puts the result directly in inst.operands[i]. */
4405 parse_big_immediate (char **str
, int i
)
4410 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4412 if (exp
.X_op
== O_constant
)
4414 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4415 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4416 O_constant. We have to be careful not to break compilation for
4417 32-bit X_add_number, though. */
4418 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4420 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4421 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4422 inst
.operands
[i
].regisimm
= 1;
4425 else if (exp
.X_op
== O_big
4426 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4428 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4430 /* Bignums have their least significant bits in
4431 generic_bignum[0]. Make sure we put 32 bits in imm and
4432 32 bits in reg, in a (hopefully) portable way. */
4433 gas_assert (parts
!= 0);
4435 /* Make sure that the number is not too big.
4436 PR 11972: Bignums can now be sign-extended to the
4437 size of a .octa so check that the out of range bits
4438 are all zero or all one. */
4439 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4441 LITTLENUM_TYPE m
= -1;
4443 if (generic_bignum
[parts
* 2] != 0
4444 && generic_bignum
[parts
* 2] != m
)
4447 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4448 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4452 inst
.operands
[i
].imm
= 0;
4453 for (j
= 0; j
< parts
; j
++, idx
++)
4454 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4455 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4456 inst
.operands
[i
].reg
= 0;
4457 for (j
= 0; j
< parts
; j
++, idx
++)
4458 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4459 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4460 inst
.operands
[i
].regisimm
= 1;
4470 /* Returns the pseudo-register number of an FPA immediate constant,
4471 or FAIL if there isn't a valid constant here. */
4474 parse_fpa_immediate (char ** str
)
4476 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4482 /* First try and match exact strings, this is to guarantee
4483 that some formats will work even for cross assembly. */
4485 for (i
= 0; fp_const
[i
]; i
++)
4487 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4491 *str
+= strlen (fp_const
[i
]);
4492 if (is_end_of_line
[(unsigned char) **str
])
4498 /* Just because we didn't get a match doesn't mean that the constant
4499 isn't valid, just that it is in a format that we don't
4500 automatically recognize. Try parsing it with the standard
4501 expression routines. */
4503 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4505 /* Look for a raw floating point number. */
4506 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4507 && is_end_of_line
[(unsigned char) *save_in
])
4509 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4511 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4513 if (words
[j
] != fp_values
[i
][j
])
4517 if (j
== MAX_LITTLENUMS
)
4525 /* Try and parse a more complex expression, this will probably fail
4526 unless the code uses a floating point prefix (eg "0f"). */
4527 save_in
= input_line_pointer
;
4528 input_line_pointer
= *str
;
4529 if (expression (&exp
) == absolute_section
4530 && exp
.X_op
== O_big
4531 && exp
.X_add_number
< 0)
4533 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4535 if (gen_to_words (words
, 5, (long) 15) == 0)
4537 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4539 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4541 if (words
[j
] != fp_values
[i
][j
])
4545 if (j
== MAX_LITTLENUMS
)
4547 *str
= input_line_pointer
;
4548 input_line_pointer
= save_in
;
4555 *str
= input_line_pointer
;
4556 input_line_pointer
= save_in
;
4557 inst
.error
= _("invalid FPA immediate expression");
4561 /* Returns 1 if a number has "quarter-precision" float format
4562 0baBbbbbbc defgh000 00000000 00000000. */
4565 is_quarter_float (unsigned imm
)
4567 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4568 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4571 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4572 0baBbbbbbc defgh000 00000000 00000000.
4573 The zero and minus-zero cases need special handling, since they can't be
4574 encoded in the "quarter-precision" float format, but can nonetheless be
4575 loaded as integer constants. */
4578 parse_qfloat_immediate (char **ccp
, int *immed
)
4582 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4583 int found_fpchar
= 0;
4585 skip_past_char (&str
, '#');
4587 /* We must not accidentally parse an integer as a floating-point number. Make
4588 sure that the value we parse is not an integer by checking for special
4589 characters '.' or 'e'.
4590 FIXME: This is a horrible hack, but doing better is tricky because type
4591 information isn't in a very usable state at parse time. */
4593 skip_whitespace (fpnum
);
4595 if (strncmp (fpnum
, "0x", 2) == 0)
4599 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4600 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4610 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4612 unsigned fpword
= 0;
4615 /* Our FP word must be 32 bits (single-precision FP). */
4616 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4618 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4622 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4635 /* Shift operands. */
4638 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4641 struct asm_shift_name
4644 enum shift_kind kind
;
4647 /* Third argument to parse_shift. */
4648 enum parse_shift_mode
4650 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4651 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4652 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4653 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4654 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4657 /* Parse a <shift> specifier on an ARM data processing instruction.
4658 This has three forms:
4660 (LSL|LSR|ASL|ASR|ROR) Rs
4661 (LSL|LSR|ASL|ASR|ROR) #imm
4664 Note that ASL is assimilated to LSL in the instruction encoding, and
4665 RRX to ROR #0 (which cannot be written as such). */
4668 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4670 const struct asm_shift_name
*shift_name
;
4671 enum shift_kind shift
;
4676 for (p
= *str
; ISALPHA (*p
); p
++)
4681 inst
.error
= _("shift expression expected");
4685 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4688 if (shift_name
== NULL
)
4690 inst
.error
= _("shift expression expected");
4694 shift
= shift_name
->kind
;
4698 case NO_SHIFT_RESTRICT
:
4699 case SHIFT_IMMEDIATE
: break;
4701 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4702 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4704 inst
.error
= _("'LSL' or 'ASR' required");
4709 case SHIFT_LSL_IMMEDIATE
:
4710 if (shift
!= SHIFT_LSL
)
4712 inst
.error
= _("'LSL' required");
4717 case SHIFT_ASR_IMMEDIATE
:
4718 if (shift
!= SHIFT_ASR
)
4720 inst
.error
= _("'ASR' required");
4728 if (shift
!= SHIFT_RRX
)
4730 /* Whitespace can appear here if the next thing is a bare digit. */
4731 skip_whitespace (p
);
4733 if (mode
== NO_SHIFT_RESTRICT
4734 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4736 inst
.operands
[i
].imm
= reg
;
4737 inst
.operands
[i
].immisreg
= 1;
4739 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4742 inst
.operands
[i
].shift_kind
= shift
;
4743 inst
.operands
[i
].shifted
= 1;
4748 /* Parse a <shifter_operand> for an ARM data processing instruction:
4751 #<immediate>, <rotate>
4755 where <shift> is defined by parse_shift above, and <rotate> is a
4756 multiple of 2 between 0 and 30. Validation of immediate operands
4757 is deferred to md_apply_fix. */
4760 parse_shifter_operand (char **str
, int i
)
4765 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4767 inst
.operands
[i
].reg
= value
;
4768 inst
.operands
[i
].isreg
= 1;
4770 /* parse_shift will override this if appropriate */
4771 inst
.reloc
.exp
.X_op
= O_constant
;
4772 inst
.reloc
.exp
.X_add_number
= 0;
4774 if (skip_past_comma (str
) == FAIL
)
4777 /* Shift operation on register. */
4778 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4781 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4784 if (skip_past_comma (str
) == SUCCESS
)
4786 /* #x, y -- ie explicit rotation by Y. */
4787 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4790 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4792 inst
.error
= _("constant expression expected");
4796 value
= exp
.X_add_number
;
4797 if (value
< 0 || value
> 30 || value
% 2 != 0)
4799 inst
.error
= _("invalid rotation");
4802 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4804 inst
.error
= _("invalid constant");
4808 /* Convert to decoded value. md_apply_fix will put it back. */
4809 inst
.reloc
.exp
.X_add_number
4810 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4811 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4814 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4815 inst
.reloc
.pc_rel
= 0;
4819 /* Group relocation information. Each entry in the table contains the
4820 textual name of the relocation as may appear in assembler source
4821 and must end with a colon.
4822 Along with this textual name are the relocation codes to be used if
4823 the corresponding instruction is an ALU instruction (ADD or SUB only),
4824 an LDR, an LDRS, or an LDC. */
4826 struct group_reloc_table_entry
4837 /* Varieties of non-ALU group relocation. */
4844 static struct group_reloc_table_entry group_reloc_table
[] =
4845 { /* Program counter relative: */
4847 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4852 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4853 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4854 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4855 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4857 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4862 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4863 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4864 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4865 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4867 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4868 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4869 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4870 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4871 /* Section base relative */
4873 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4878 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4879 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4880 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4881 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4883 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4888 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4889 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4890 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4891 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4893 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4894 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4895 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4896 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4898 /* Given the address of a pointer pointing to the textual name of a group
4899 relocation as may appear in assembler source, attempt to find its details
4900 in group_reloc_table. The pointer will be updated to the character after
4901 the trailing colon. On failure, FAIL will be returned; SUCCESS
4902 otherwise. On success, *entry will be updated to point at the relevant
4903 group_reloc_table entry. */
4906 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4909 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4911 int length
= strlen (group_reloc_table
[i
].name
);
4913 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4914 && (*str
)[length
] == ':')
4916 *out
= &group_reloc_table
[i
];
4917 *str
+= (length
+ 1);
4925 /* Parse a <shifter_operand> for an ARM data processing instruction
4926 (as for parse_shifter_operand) where group relocations are allowed:
4929 #<immediate>, <rotate>
4930 #:<group_reloc>:<expression>
4934 where <group_reloc> is one of the strings defined in group_reloc_table.
4935 The hashes are optional.
4937 Everything else is as for parse_shifter_operand. */
4939 static parse_operand_result
4940 parse_shifter_operand_group_reloc (char **str
, int i
)
4942 /* Determine if we have the sequence of characters #: or just :
4943 coming next. If we do, then we check for a group relocation.
4944 If we don't, punt the whole lot to parse_shifter_operand. */
4946 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4947 || (*str
)[0] == ':')
4949 struct group_reloc_table_entry
*entry
;
4951 if ((*str
)[0] == '#')
4956 /* Try to parse a group relocation. Anything else is an error. */
4957 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4959 inst
.error
= _("unknown group relocation");
4960 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4963 /* We now have the group relocation table entry corresponding to
4964 the name in the assembler source. Next, we parse the expression. */
4965 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4966 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4968 /* Record the relocation type (always the ALU variant here). */
4969 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4970 gas_assert (inst
.reloc
.type
!= 0);
4972 return PARSE_OPERAND_SUCCESS
;
4975 return parse_shifter_operand (str
, i
) == SUCCESS
4976 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4978 /* Never reached. */
4981 /* Parse a Neon alignment expression. Information is written to
4982 inst.operands[i]. We assume the initial ':' has been skipped.
4984 align .imm = align << 8, .immisalign=1, .preind=0 */
4985 static parse_operand_result
4986 parse_neon_alignment (char **str
, int i
)
4991 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4993 if (exp
.X_op
!= O_constant
)
4995 inst
.error
= _("alignment must be constant");
4996 return PARSE_OPERAND_FAIL
;
4999 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5000 inst
.operands
[i
].immisalign
= 1;
5001 /* Alignments are not pre-indexes. */
5002 inst
.operands
[i
].preind
= 0;
5005 return PARSE_OPERAND_SUCCESS
;
5008 /* Parse all forms of an ARM address expression. Information is written
5009 to inst.operands[i] and/or inst.reloc.
5011 Preindexed addressing (.preind=1):
5013 [Rn, #offset] .reg=Rn .reloc.exp=offset
5014 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5015 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5016 .shift_kind=shift .reloc.exp=shift_imm
5018 These three may have a trailing ! which causes .writeback to be set also.
5020 Postindexed addressing (.postind=1, .writeback=1):
5022 [Rn], #offset .reg=Rn .reloc.exp=offset
5023 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5024 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5025 .shift_kind=shift .reloc.exp=shift_imm
5027 Unindexed addressing (.preind=0, .postind=0):
5029 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5033 [Rn]{!} shorthand for [Rn,#0]{!}
5034 =immediate .isreg=0 .reloc.exp=immediate
5035 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5037 It is the caller's responsibility to check for addressing modes not
5038 supported by the instruction, and to set inst.reloc.type. */
5040 static parse_operand_result
5041 parse_address_main (char **str
, int i
, int group_relocations
,
5042 group_reloc_type group_type
)
5047 if (skip_past_char (&p
, '[') == FAIL
)
5049 if (skip_past_char (&p
, '=') == FAIL
)
5051 /* Bare address - translate to PC-relative offset. */
5052 inst
.reloc
.pc_rel
= 1;
5053 inst
.operands
[i
].reg
= REG_PC
;
5054 inst
.operands
[i
].isreg
= 1;
5055 inst
.operands
[i
].preind
= 1;
5057 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5059 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5060 return PARSE_OPERAND_FAIL
;
5063 return PARSE_OPERAND_SUCCESS
;
5066 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5068 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5069 return PARSE_OPERAND_FAIL
;
5071 inst
.operands
[i
].reg
= reg
;
5072 inst
.operands
[i
].isreg
= 1;
5074 if (skip_past_comma (&p
) == SUCCESS
)
5076 inst
.operands
[i
].preind
= 1;
5079 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5081 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5083 inst
.operands
[i
].imm
= reg
;
5084 inst
.operands
[i
].immisreg
= 1;
5086 if (skip_past_comma (&p
) == SUCCESS
)
5087 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5088 return PARSE_OPERAND_FAIL
;
5090 else if (skip_past_char (&p
, ':') == SUCCESS
)
5092 /* FIXME: '@' should be used here, but it's filtered out by generic
5093 code before we get to see it here. This may be subject to
5095 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5097 if (result
!= PARSE_OPERAND_SUCCESS
)
5102 if (inst
.operands
[i
].negative
)
5104 inst
.operands
[i
].negative
= 0;
5108 if (group_relocations
5109 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5111 struct group_reloc_table_entry
*entry
;
5113 /* Skip over the #: or : sequence. */
5119 /* Try to parse a group relocation. Anything else is an
5121 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5123 inst
.error
= _("unknown group relocation");
5124 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5127 /* We now have the group relocation table entry corresponding to
5128 the name in the assembler source. Next, we parse the
5130 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5131 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5133 /* Record the relocation type. */
5137 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5141 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5145 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5152 if (inst
.reloc
.type
== 0)
5154 inst
.error
= _("this group relocation is not allowed on this instruction");
5155 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5159 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5160 return PARSE_OPERAND_FAIL
;
5163 else if (skip_past_char (&p
, ':') == SUCCESS
)
5165 /* FIXME: '@' should be used here, but it's filtered out by generic code
5166 before we get to see it here. This may be subject to change. */
5167 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5169 if (result
!= PARSE_OPERAND_SUCCESS
)
5173 if (skip_past_char (&p
, ']') == FAIL
)
5175 inst
.error
= _("']' expected");
5176 return PARSE_OPERAND_FAIL
;
5179 if (skip_past_char (&p
, '!') == SUCCESS
)
5180 inst
.operands
[i
].writeback
= 1;
5182 else if (skip_past_comma (&p
) == SUCCESS
)
5184 if (skip_past_char (&p
, '{') == SUCCESS
)
5186 /* [Rn], {expr} - unindexed, with option */
5187 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5188 0, 255, TRUE
) == FAIL
)
5189 return PARSE_OPERAND_FAIL
;
5191 if (skip_past_char (&p
, '}') == FAIL
)
5193 inst
.error
= _("'}' expected at end of 'option' field");
5194 return PARSE_OPERAND_FAIL
;
5196 if (inst
.operands
[i
].preind
)
5198 inst
.error
= _("cannot combine index with option");
5199 return PARSE_OPERAND_FAIL
;
5202 return PARSE_OPERAND_SUCCESS
;
5206 inst
.operands
[i
].postind
= 1;
5207 inst
.operands
[i
].writeback
= 1;
5209 if (inst
.operands
[i
].preind
)
5211 inst
.error
= _("cannot combine pre- and post-indexing");
5212 return PARSE_OPERAND_FAIL
;
5216 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5218 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5220 /* We might be using the immediate for alignment already. If we
5221 are, OR the register number into the low-order bits. */
5222 if (inst
.operands
[i
].immisalign
)
5223 inst
.operands
[i
].imm
|= reg
;
5225 inst
.operands
[i
].imm
= reg
;
5226 inst
.operands
[i
].immisreg
= 1;
5228 if (skip_past_comma (&p
) == SUCCESS
)
5229 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5230 return PARSE_OPERAND_FAIL
;
5234 if (inst
.operands
[i
].negative
)
5236 inst
.operands
[i
].negative
= 0;
5239 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5240 return PARSE_OPERAND_FAIL
;
5245 /* If at this point neither .preind nor .postind is set, we have a
5246 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5247 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5249 inst
.operands
[i
].preind
= 1;
5250 inst
.reloc
.exp
.X_op
= O_constant
;
5251 inst
.reloc
.exp
.X_add_number
= 0;
5254 return PARSE_OPERAND_SUCCESS
;
5258 parse_address (char **str
, int i
)
5260 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5264 static parse_operand_result
5265 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5267 return parse_address_main (str
, i
, 1, type
);
5270 /* Parse an operand for a MOVW or MOVT instruction. */
5272 parse_half (char **str
)
5277 skip_past_char (&p
, '#');
5278 if (strncasecmp (p
, ":lower16:", 9) == 0)
5279 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5280 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5281 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5283 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5286 skip_whitespace (p
);
5289 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5292 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5294 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5296 inst
.error
= _("constant expression expected");
5299 if (inst
.reloc
.exp
.X_add_number
< 0
5300 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5302 inst
.error
= _("immediate value out of range");
5310 /* Miscellaneous. */
5312 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5313 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5315 parse_psr (char **str
)
5318 unsigned long psr_field
;
5319 const struct asm_psr
*psr
;
5322 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5323 feature for ease of use and backwards compatibility. */
5325 if (strncasecmp (p
, "SPSR", 4) == 0)
5326 psr_field
= SPSR_BIT
;
5327 else if (strncasecmp (p
, "CPSR", 4) == 0
5328 || (strncasecmp (p
, "APSR", 4) == 0
5329 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
)))
5336 while (ISALNUM (*p
) || *p
== '_');
5338 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5350 /* A suffix follows. */
5356 while (ISALNUM (*p
) || *p
== '_');
5358 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5363 psr_field
|= psr
->field
;
5368 goto error
; /* Garbage after "[CS]PSR". */
5370 psr_field
|= (PSR_c
| PSR_f
);
5376 inst
.error
= _("flag for {c}psr instruction expected");
5380 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5381 value suitable for splatting into the AIF field of the instruction. */
5384 parse_cps_flags (char **str
)
5393 case '\0': case ',':
5396 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5397 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5398 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5401 inst
.error
= _("unrecognized CPS flag");
5406 if (saw_a_flag
== 0)
5408 inst
.error
= _("missing CPS flags");
5416 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5417 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5420 parse_endian_specifier (char **str
)
5425 if (strncasecmp (s
, "BE", 2))
5427 else if (strncasecmp (s
, "LE", 2))
5431 inst
.error
= _("valid endian specifiers are be or le");
5435 if (ISALNUM (s
[2]) || s
[2] == '_')
5437 inst
.error
= _("valid endian specifiers are be or le");
5442 return little_endian
;
5445 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5446 value suitable for poking into the rotate field of an sxt or sxta
5447 instruction, or FAIL on error. */
5450 parse_ror (char **str
)
5455 if (strncasecmp (s
, "ROR", 3) == 0)
5459 inst
.error
= _("missing rotation field after comma");
5463 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5468 case 0: *str
= s
; return 0x0;
5469 case 8: *str
= s
; return 0x1;
5470 case 16: *str
= s
; return 0x2;
5471 case 24: *str
= s
; return 0x3;
5474 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5479 /* Parse a conditional code (from conds[] below). The value returned is in the
5480 range 0 .. 14, or FAIL. */
5482 parse_cond (char **str
)
5485 const struct asm_cond
*c
;
5487 /* Condition codes are always 2 characters, so matching up to
5488 3 characters is sufficient. */
5493 while (ISALPHA (*q
) && n
< 3)
5495 cond
[n
] = TOLOWER (*q
);
5500 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5503 inst
.error
= _("condition required");
5511 /* Parse an option for a barrier instruction. Returns the encoding for the
5514 parse_barrier (char **str
)
5517 const struct asm_barrier_opt
*o
;
5520 while (ISALPHA (*q
))
5523 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5532 /* Parse the operands of a table branch instruction. Similar to a memory
5535 parse_tb (char **str
)
5540 if (skip_past_char (&p
, '[') == FAIL
)
5542 inst
.error
= _("'[' expected");
5546 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5548 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5551 inst
.operands
[0].reg
= reg
;
5553 if (skip_past_comma (&p
) == FAIL
)
5555 inst
.error
= _("',' expected");
5559 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5561 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5564 inst
.operands
[0].imm
= reg
;
5566 if (skip_past_comma (&p
) == SUCCESS
)
5568 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5570 if (inst
.reloc
.exp
.X_add_number
!= 1)
5572 inst
.error
= _("invalid shift");
5575 inst
.operands
[0].shifted
= 1;
5578 if (skip_past_char (&p
, ']') == FAIL
)
5580 inst
.error
= _("']' expected");
5587 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5588 information on the types the operands can take and how they are encoded.
5589 Up to four operands may be read; this function handles setting the
5590 ".present" field for each read operand itself.
5591 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5592 else returns FAIL. */
5595 parse_neon_mov (char **str
, int *which_operand
)
5597 int i
= *which_operand
, val
;
5598 enum arm_reg_type rtype
;
5600 struct neon_type_el optype
;
5602 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5604 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5605 inst
.operands
[i
].reg
= val
;
5606 inst
.operands
[i
].isscalar
= 1;
5607 inst
.operands
[i
].vectype
= optype
;
5608 inst
.operands
[i
++].present
= 1;
5610 if (skip_past_comma (&ptr
) == FAIL
)
5613 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5616 inst
.operands
[i
].reg
= val
;
5617 inst
.operands
[i
].isreg
= 1;
5618 inst
.operands
[i
].present
= 1;
5620 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5623 /* Cases 0, 1, 2, 3, 5 (D only). */
5624 if (skip_past_comma (&ptr
) == FAIL
)
5627 inst
.operands
[i
].reg
= val
;
5628 inst
.operands
[i
].isreg
= 1;
5629 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5630 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5631 inst
.operands
[i
].isvec
= 1;
5632 inst
.operands
[i
].vectype
= optype
;
5633 inst
.operands
[i
++].present
= 1;
5635 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5637 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5638 Case 13: VMOV <Sd>, <Rm> */
5639 inst
.operands
[i
].reg
= val
;
5640 inst
.operands
[i
].isreg
= 1;
5641 inst
.operands
[i
].present
= 1;
5643 if (rtype
== REG_TYPE_NQ
)
5645 first_error (_("can't use Neon quad register here"));
5648 else if (rtype
!= REG_TYPE_VFS
)
5651 if (skip_past_comma (&ptr
) == FAIL
)
5653 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5655 inst
.operands
[i
].reg
= val
;
5656 inst
.operands
[i
].isreg
= 1;
5657 inst
.operands
[i
].present
= 1;
5660 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5663 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5664 Case 1: VMOV<c><q> <Dd>, <Dm>
5665 Case 8: VMOV.F32 <Sd>, <Sm>
5666 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5668 inst
.operands
[i
].reg
= val
;
5669 inst
.operands
[i
].isreg
= 1;
5670 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5671 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5672 inst
.operands
[i
].isvec
= 1;
5673 inst
.operands
[i
].vectype
= optype
;
5674 inst
.operands
[i
].present
= 1;
5676 if (skip_past_comma (&ptr
) == SUCCESS
)
5681 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5684 inst
.operands
[i
].reg
= val
;
5685 inst
.operands
[i
].isreg
= 1;
5686 inst
.operands
[i
++].present
= 1;
5688 if (skip_past_comma (&ptr
) == FAIL
)
5691 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5694 inst
.operands
[i
].reg
= val
;
5695 inst
.operands
[i
].isreg
= 1;
5696 inst
.operands
[i
++].present
= 1;
5699 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5700 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5701 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5702 Case 10: VMOV.F32 <Sd>, #<imm>
5703 Case 11: VMOV.F64 <Dd>, #<imm> */
5704 inst
.operands
[i
].immisfloat
= 1;
5705 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5706 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5707 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5711 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5715 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5718 inst
.operands
[i
].reg
= val
;
5719 inst
.operands
[i
].isreg
= 1;
5720 inst
.operands
[i
++].present
= 1;
5722 if (skip_past_comma (&ptr
) == FAIL
)
5725 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5727 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5728 inst
.operands
[i
].reg
= val
;
5729 inst
.operands
[i
].isscalar
= 1;
5730 inst
.operands
[i
].present
= 1;
5731 inst
.operands
[i
].vectype
= optype
;
5733 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5735 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5736 inst
.operands
[i
].reg
= val
;
5737 inst
.operands
[i
].isreg
= 1;
5738 inst
.operands
[i
++].present
= 1;
5740 if (skip_past_comma (&ptr
) == FAIL
)
5743 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5746 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5750 inst
.operands
[i
].reg
= val
;
5751 inst
.operands
[i
].isreg
= 1;
5752 inst
.operands
[i
].isvec
= 1;
5753 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5754 inst
.operands
[i
].vectype
= optype
;
5755 inst
.operands
[i
].present
= 1;
5757 if (rtype
== REG_TYPE_VFS
)
5761 if (skip_past_comma (&ptr
) == FAIL
)
5763 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5766 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5769 inst
.operands
[i
].reg
= val
;
5770 inst
.operands
[i
].isreg
= 1;
5771 inst
.operands
[i
].isvec
= 1;
5772 inst
.operands
[i
].issingle
= 1;
5773 inst
.operands
[i
].vectype
= optype
;
5774 inst
.operands
[i
].present
= 1;
5777 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5781 inst
.operands
[i
].reg
= val
;
5782 inst
.operands
[i
].isreg
= 1;
5783 inst
.operands
[i
].isvec
= 1;
5784 inst
.operands
[i
].issingle
= 1;
5785 inst
.operands
[i
].vectype
= optype
;
5786 inst
.operands
[i
++].present
= 1;
5791 first_error (_("parse error"));
5795 /* Successfully parsed the operands. Update args. */
5801 first_error (_("expected comma"));
5805 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5809 /* Use this macro when the operand constraints are different
5810 for ARM and THUMB (e.g. ldrd). */
5811 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5812 ((arm_operand) | ((thumb_operand) << 16))
5814 /* Matcher codes for parse_operands. */
5815 enum operand_parse_code
5817 OP_stop
, /* end of line */
5819 OP_RR
, /* ARM register */
5820 OP_RRnpc
, /* ARM register, not r15 */
5821 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5822 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5823 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5824 optional trailing ! */
5825 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5826 OP_RCP
, /* Coprocessor number */
5827 OP_RCN
, /* Coprocessor register */
5828 OP_RF
, /* FPA register */
5829 OP_RVS
, /* VFP single precision register */
5830 OP_RVD
, /* VFP double precision register (0..15) */
5831 OP_RND
, /* Neon double precision register (0..31) */
5832 OP_RNQ
, /* Neon quad precision register */
5833 OP_RVSD
, /* VFP single or double precision register */
5834 OP_RNDQ
, /* Neon double or quad precision register */
5835 OP_RNSDQ
, /* Neon single, double or quad precision register */
5836 OP_RNSC
, /* Neon scalar D[X] */
5837 OP_RVC
, /* VFP control register */
5838 OP_RMF
, /* Maverick F register */
5839 OP_RMD
, /* Maverick D register */
5840 OP_RMFX
, /* Maverick FX register */
5841 OP_RMDX
, /* Maverick DX register */
5842 OP_RMAX
, /* Maverick AX register */
5843 OP_RMDS
, /* Maverick DSPSC register */
5844 OP_RIWR
, /* iWMMXt wR register */
5845 OP_RIWC
, /* iWMMXt wC register */
5846 OP_RIWG
, /* iWMMXt wCG register */
5847 OP_RXA
, /* XScale accumulator register */
5849 OP_REGLST
, /* ARM register list */
5850 OP_VRSLST
, /* VFP single-precision register list */
5851 OP_VRDLST
, /* VFP double-precision register list */
5852 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5853 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5854 OP_NSTRLST
, /* Neon element/structure list */
5856 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5857 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5858 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5859 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5860 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5861 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5862 OP_VMOV
, /* Neon VMOV operands. */
5863 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5864 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5865 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5867 OP_I0
, /* immediate zero */
5868 OP_I7
, /* immediate value 0 .. 7 */
5869 OP_I15
, /* 0 .. 15 */
5870 OP_I16
, /* 1 .. 16 */
5871 OP_I16z
, /* 0 .. 16 */
5872 OP_I31
, /* 0 .. 31 */
5873 OP_I31w
, /* 0 .. 31, optional trailing ! */
5874 OP_I32
, /* 1 .. 32 */
5875 OP_I32z
, /* 0 .. 32 */
5876 OP_I63
, /* 0 .. 63 */
5877 OP_I63s
, /* -64 .. 63 */
5878 OP_I64
, /* 1 .. 64 */
5879 OP_I64z
, /* 0 .. 64 */
5880 OP_I255
, /* 0 .. 255 */
5882 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5883 OP_I7b
, /* 0 .. 7 */
5884 OP_I15b
, /* 0 .. 15 */
5885 OP_I31b
, /* 0 .. 31 */
5887 OP_SH
, /* shifter operand */
5888 OP_SHG
, /* shifter operand with possible group relocation */
5889 OP_ADDR
, /* Memory address expression (any mode) */
5890 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5891 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5892 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5893 OP_EXP
, /* arbitrary expression */
5894 OP_EXPi
, /* same, with optional immediate prefix */
5895 OP_EXPr
, /* same, with optional relocation suffix */
5896 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5898 OP_CPSF
, /* CPS flags */
5899 OP_ENDI
, /* Endianness specifier */
5900 OP_PSR
, /* CPSR/SPSR mask for msr */
5901 OP_COND
, /* conditional code */
5902 OP_TB
, /* Table branch. */
5904 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5905 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5907 OP_RRnpc_I0
, /* ARM register or literal 0 */
5908 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5909 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5910 OP_RF_IF
, /* FPA register or immediate */
5911 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5912 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5914 /* Optional operands. */
5915 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5916 OP_oI31b
, /* 0 .. 31 */
5917 OP_oI32b
, /* 1 .. 32 */
5918 OP_oIffffb
, /* 0 .. 65535 */
5919 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5921 OP_oRR
, /* ARM register */
5922 OP_oRRnpc
, /* ARM register, not the PC */
5923 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5924 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5925 OP_oRND
, /* Optional Neon double precision register */
5926 OP_oRNQ
, /* Optional Neon quad precision register */
5927 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5928 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5929 OP_oSHll
, /* LSL immediate */
5930 OP_oSHar
, /* ASR immediate */
5931 OP_oSHllar
, /* LSL or ASR immediate */
5932 OP_oROR
, /* ROR 0/8/16/24 */
5933 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
5935 /* Some pre-defined mixed (ARM/THUMB) operands. */
5936 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5937 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5938 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5940 OP_FIRST_OPTIONAL
= OP_oI7b
5943 /* Generic instruction operand parser. This does no encoding and no
5944 semantic validation; it merely squirrels values away in the inst
5945 structure. Returns SUCCESS or FAIL depending on whether the
5946 specified grammar matched. */
5948 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5950 unsigned const int *upat
= pattern
;
5951 char *backtrack_pos
= 0;
5952 const char *backtrack_error
= 0;
5953 int i
, val
, backtrack_index
= 0;
5954 enum arm_reg_type rtype
;
5955 parse_operand_result result
;
5956 unsigned int op_parse_code
;
5958 #define po_char_or_fail(chr) \
5961 if (skip_past_char (&str, chr) == FAIL) \
5966 #define po_reg_or_fail(regtype) \
5969 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5970 & inst.operands[i].vectype); \
5973 first_error (_(reg_expected_msgs[regtype])); \
5976 inst.operands[i].reg = val; \
5977 inst.operands[i].isreg = 1; \
5978 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5979 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5980 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5981 || rtype == REG_TYPE_VFD \
5982 || rtype == REG_TYPE_NQ); \
5986 #define po_reg_or_goto(regtype, label) \
5989 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5990 & inst.operands[i].vectype); \
5994 inst.operands[i].reg = val; \
5995 inst.operands[i].isreg = 1; \
5996 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5997 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5998 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5999 || rtype == REG_TYPE_VFD \
6000 || rtype == REG_TYPE_NQ); \
6004 #define po_imm_or_fail(min, max, popt) \
6007 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6009 inst.operands[i].imm = val; \
6013 #define po_scalar_or_goto(elsz, label) \
6016 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6019 inst.operands[i].reg = val; \
6020 inst.operands[i].isscalar = 1; \
6024 #define po_misc_or_fail(expr) \
6032 #define po_misc_or_fail_no_backtrack(expr) \
6036 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6037 backtrack_pos = 0; \
6038 if (result != PARSE_OPERAND_SUCCESS) \
6043 #define po_barrier_or_imm(str) \
6046 val = parse_barrier (&str); \
6049 if (ISALPHA (*str)) \
6056 if ((inst.instruction & 0xf0) == 0x60 \
6059 /* ISB can only take SY as an option. */ \
6060 inst.error = _("invalid barrier type"); \
6067 skip_whitespace (str
);
6069 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6071 op_parse_code
= upat
[i
];
6072 if (op_parse_code
>= 1<<16)
6073 op_parse_code
= thumb
? (op_parse_code
>> 16)
6074 : (op_parse_code
& ((1<<16)-1));
6076 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6078 /* Remember where we are in case we need to backtrack. */
6079 gas_assert (!backtrack_pos
);
6080 backtrack_pos
= str
;
6081 backtrack_error
= inst
.error
;
6082 backtrack_index
= i
;
6085 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6086 po_char_or_fail (',');
6088 switch (op_parse_code
)
6096 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6097 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6098 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6099 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6100 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6101 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6103 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6105 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6107 /* Also accept generic coprocessor regs for unknown registers. */
6109 po_reg_or_fail (REG_TYPE_CN
);
6111 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6112 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6113 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6114 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6115 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6116 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6117 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6118 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6119 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6120 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6122 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6124 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6125 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6127 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6129 /* Neon scalar. Using an element size of 8 means that some invalid
6130 scalars are accepted here, so deal with those in later code. */
6131 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6135 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6138 po_imm_or_fail (0, 0, TRUE
);
6143 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6148 po_scalar_or_goto (8, try_rr
);
6151 po_reg_or_fail (REG_TYPE_RN
);
6157 po_scalar_or_goto (8, try_nsdq
);
6160 po_reg_or_fail (REG_TYPE_NSDQ
);
6166 po_scalar_or_goto (8, try_ndq
);
6169 po_reg_or_fail (REG_TYPE_NDQ
);
6175 po_scalar_or_goto (8, try_vfd
);
6178 po_reg_or_fail (REG_TYPE_VFD
);
6183 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6184 not careful then bad things might happen. */
6185 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6190 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6193 /* There's a possibility of getting a 64-bit immediate here, so
6194 we need special handling. */
6195 if (parse_big_immediate (&str
, i
) == FAIL
)
6197 inst
.error
= _("immediate value is out of range");
6205 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6208 po_imm_or_fail (0, 63, TRUE
);
6213 po_char_or_fail ('[');
6214 po_reg_or_fail (REG_TYPE_RN
);
6215 po_char_or_fail (']');
6221 po_reg_or_fail (REG_TYPE_RN
);
6222 if (skip_past_char (&str
, '!') == SUCCESS
)
6223 inst
.operands
[i
].writeback
= 1;
6227 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6228 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6229 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6230 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6231 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6232 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6233 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6234 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6235 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6236 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6237 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6238 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6240 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6242 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6243 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6245 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6246 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6247 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6249 /* Immediate variants */
6251 po_char_or_fail ('{');
6252 po_imm_or_fail (0, 255, TRUE
);
6253 po_char_or_fail ('}');
6257 /* The expression parser chokes on a trailing !, so we have
6258 to find it first and zap it. */
6261 while (*s
&& *s
!= ',')
6266 inst
.operands
[i
].writeback
= 1;
6268 po_imm_or_fail (0, 31, TRUE
);
6276 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6281 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6286 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6288 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6290 val
= parse_reloc (&str
);
6293 inst
.error
= _("unrecognized relocation suffix");
6296 else if (val
!= BFD_RELOC_UNUSED
)
6298 inst
.operands
[i
].imm
= val
;
6299 inst
.operands
[i
].hasreloc
= 1;
6304 /* Operand for MOVW or MOVT. */
6306 po_misc_or_fail (parse_half (&str
));
6309 /* Register or expression. */
6310 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6311 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6313 /* Register or immediate. */
6314 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6315 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6317 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6319 if (!is_immediate_prefix (*str
))
6322 val
= parse_fpa_immediate (&str
);
6325 /* FPA immediates are encoded as registers 8-15.
6326 parse_fpa_immediate has already applied the offset. */
6327 inst
.operands
[i
].reg
= val
;
6328 inst
.operands
[i
].isreg
= 1;
6331 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6332 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6334 /* Two kinds of register. */
6337 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6339 || (rege
->type
!= REG_TYPE_MMXWR
6340 && rege
->type
!= REG_TYPE_MMXWC
6341 && rege
->type
!= REG_TYPE_MMXWCG
))
6343 inst
.error
= _("iWMMXt data or control register expected");
6346 inst
.operands
[i
].reg
= rege
->number
;
6347 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6353 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6355 || (rege
->type
!= REG_TYPE_MMXWC
6356 && rege
->type
!= REG_TYPE_MMXWCG
))
6358 inst
.error
= _("iWMMXt control register expected");
6361 inst
.operands
[i
].reg
= rege
->number
;
6362 inst
.operands
[i
].isreg
= 1;
6367 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6368 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6369 case OP_oROR
: val
= parse_ror (&str
); break;
6370 case OP_PSR
: val
= parse_psr (&str
); break;
6371 case OP_COND
: val
= parse_cond (&str
); break;
6372 case OP_oBARRIER_I15
:
6373 po_barrier_or_imm (str
); break;
6375 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6380 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6381 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6384 val
= parse_psr (&str
);
6388 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6391 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6393 if (strncasecmp (str
, "APSR_", 5) == 0)
6400 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6401 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6402 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6403 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6404 default: found
= 16;
6408 inst
.operands
[i
].isvec
= 1;
6409 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6410 inst
.operands
[i
].reg
= REG_PC
;
6417 po_misc_or_fail (parse_tb (&str
));
6420 /* Register lists. */
6422 val
= parse_reg_list (&str
);
6425 inst
.operands
[1].writeback
= 1;
6431 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6435 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6439 /* Allow Q registers too. */
6440 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6445 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6447 inst
.operands
[i
].issingle
= 1;
6452 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6457 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6458 &inst
.operands
[i
].vectype
);
6461 /* Addressing modes */
6463 po_misc_or_fail (parse_address (&str
, i
));
6467 po_misc_or_fail_no_backtrack (
6468 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6472 po_misc_or_fail_no_backtrack (
6473 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6477 po_misc_or_fail_no_backtrack (
6478 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6482 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6486 po_misc_or_fail_no_backtrack (
6487 parse_shifter_operand_group_reloc (&str
, i
));
6491 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6495 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6499 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6503 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6506 /* Various value-based sanity checks and shared operations. We
6507 do not signal immediate failures for the register constraints;
6508 this allows a syntax error to take precedence. */
6509 switch (op_parse_code
)
6517 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6518 inst
.error
= BAD_PC
;
6523 if (inst
.operands
[i
].isreg
)
6525 if (inst
.operands
[i
].reg
== REG_PC
)
6526 inst
.error
= BAD_PC
;
6527 else if (inst
.operands
[i
].reg
== REG_SP
)
6528 inst
.error
= BAD_SP
;
6533 if (inst
.operands
[i
].isreg
6534 && inst
.operands
[i
].reg
== REG_PC
6535 && (inst
.operands
[i
].writeback
|| thumb
))
6536 inst
.error
= BAD_PC
;
6545 case OP_oBARRIER_I15
:
6554 inst
.operands
[i
].imm
= val
;
6561 /* If we get here, this operand was successfully parsed. */
6562 inst
.operands
[i
].present
= 1;
6566 inst
.error
= BAD_ARGS
;
6571 /* The parse routine should already have set inst.error, but set a
6572 default here just in case. */
6574 inst
.error
= _("syntax error");
6578 /* Do not backtrack over a trailing optional argument that
6579 absorbed some text. We will only fail again, with the
6580 'garbage following instruction' error message, which is
6581 probably less helpful than the current one. */
6582 if (backtrack_index
== i
&& backtrack_pos
!= str
6583 && upat
[i
+1] == OP_stop
)
6586 inst
.error
= _("syntax error");
6590 /* Try again, skipping the optional argument at backtrack_pos. */
6591 str
= backtrack_pos
;
6592 inst
.error
= backtrack_error
;
6593 inst
.operands
[backtrack_index
].present
= 0;
6594 i
= backtrack_index
;
6598 /* Check that we have parsed all the arguments. */
6599 if (*str
!= '\0' && !inst
.error
)
6600 inst
.error
= _("garbage following instruction");
6602 return inst
.error
? FAIL
: SUCCESS
;
6605 #undef po_char_or_fail
6606 #undef po_reg_or_fail
6607 #undef po_reg_or_goto
6608 #undef po_imm_or_fail
6609 #undef po_scalar_or_fail
6610 #undef po_barrier_or_imm
6612 /* Shorthand macro for instruction encoding functions issuing errors. */
6613 #define constraint(expr, err) \
6624 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6625 instructions are unpredictable if these registers are used. This
6626 is the BadReg predicate in ARM's Thumb-2 documentation. */
6627 #define reject_bad_reg(reg) \
6629 if (reg == REG_SP || reg == REG_PC) \
6631 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6636 /* If REG is R13 (the stack pointer), warn that its use is
6638 #define warn_deprecated_sp(reg) \
6640 if (warn_on_deprecated && reg == REG_SP) \
6641 as_warn (_("use of r13 is deprecated")); \
6644 /* Functions for operand encoding. ARM, then Thumb. */
6646 #define rotate_left(v, n) (v << n | v >> (32 - n))
6648 /* If VAL can be encoded in the immediate field of an ARM instruction,
6649 return the encoded form. Otherwise, return FAIL. */
6652 encode_arm_immediate (unsigned int val
)
6656 for (i
= 0; i
< 32; i
+= 2)
6657 if ((a
= rotate_left (val
, i
)) <= 0xff)
6658 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6663 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6664 return the encoded form. Otherwise, return FAIL. */
6666 encode_thumb32_immediate (unsigned int val
)
6673 for (i
= 1; i
<= 24; i
++)
6676 if ((val
& ~(0xff << i
)) == 0)
6677 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6681 if (val
== ((a
<< 16) | a
))
6683 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6687 if (val
== ((a
<< 16) | a
))
6688 return 0x200 | (a
>> 8);
6692 /* Encode a VFP SP or DP register number into inst.instruction. */
6695 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6697 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6700 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6703 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6706 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6711 first_error (_("D register out of range for selected VFP version"));
6719 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6723 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6727 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6731 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6735 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6739 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6747 /* Encode a <shift> in an ARM-format instruction. The immediate,
6748 if any, is handled by md_apply_fix. */
6750 encode_arm_shift (int i
)
6752 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6753 inst
.instruction
|= SHIFT_ROR
<< 5;
6756 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6757 if (inst
.operands
[i
].immisreg
)
6759 inst
.instruction
|= SHIFT_BY_REG
;
6760 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6763 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6768 encode_arm_shifter_operand (int i
)
6770 if (inst
.operands
[i
].isreg
)
6772 inst
.instruction
|= inst
.operands
[i
].reg
;
6773 encode_arm_shift (i
);
6776 inst
.instruction
|= INST_IMMEDIATE
;
6779 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6781 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6783 gas_assert (inst
.operands
[i
].isreg
);
6784 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6786 if (inst
.operands
[i
].preind
)
6790 inst
.error
= _("instruction does not accept preindexed addressing");
6793 inst
.instruction
|= PRE_INDEX
;
6794 if (inst
.operands
[i
].writeback
)
6795 inst
.instruction
|= WRITE_BACK
;
6798 else if (inst
.operands
[i
].postind
)
6800 gas_assert (inst
.operands
[i
].writeback
);
6802 inst
.instruction
|= WRITE_BACK
;
6804 else /* unindexed - only for coprocessor */
6806 inst
.error
= _("instruction does not accept unindexed addressing");
6810 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6811 && (((inst
.instruction
& 0x000f0000) >> 16)
6812 == ((inst
.instruction
& 0x0000f000) >> 12)))
6813 as_warn ((inst
.instruction
& LOAD_BIT
)
6814 ? _("destination register same as write-back base")
6815 : _("source register same as write-back base"));
6818 /* inst.operands[i] was set up by parse_address. Encode it into an
6819 ARM-format mode 2 load or store instruction. If is_t is true,
6820 reject forms that cannot be used with a T instruction (i.e. not
6823 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6825 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6827 encode_arm_addr_mode_common (i
, is_t
);
6829 if (inst
.operands
[i
].immisreg
)
6831 constraint ((inst
.operands
[i
].imm
== REG_PC
6832 || (is_pc
&& inst
.operands
[i
].writeback
)),
6834 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6835 inst
.instruction
|= inst
.operands
[i
].imm
;
6836 if (!inst
.operands
[i
].negative
)
6837 inst
.instruction
|= INDEX_UP
;
6838 if (inst
.operands
[i
].shifted
)
6840 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6841 inst
.instruction
|= SHIFT_ROR
<< 5;
6844 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6845 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6849 else /* immediate offset in inst.reloc */
6851 if (is_pc
&& !inst
.reloc
.pc_rel
)
6853 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6855 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
6856 cannot use PC in addressing.
6857 PC cannot be used in writeback addressing, either. */
6858 constraint ((is_t
|| inst
.operands
[i
].writeback
),
6861 /* Use of PC in str is deprecated for ARMv7. */
6862 if (warn_on_deprecated
6864 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
6865 as_warn (_("use of PC in this instruction is deprecated"));
6868 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6869 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6873 /* inst.operands[i] was set up by parse_address. Encode it into an
6874 ARM-format mode 3 load or store instruction. Reject forms that
6875 cannot be used with such instructions. If is_t is true, reject
6876 forms that cannot be used with a T instruction (i.e. not
6879 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6881 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6883 inst
.error
= _("instruction does not accept scaled register index");
6887 encode_arm_addr_mode_common (i
, is_t
);
6889 if (inst
.operands
[i
].immisreg
)
6891 constraint ((inst
.operands
[i
].imm
== REG_PC
6892 || inst
.operands
[i
].reg
== REG_PC
),
6894 inst
.instruction
|= inst
.operands
[i
].imm
;
6895 if (!inst
.operands
[i
].negative
)
6896 inst
.instruction
|= INDEX_UP
;
6898 else /* immediate offset in inst.reloc */
6900 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6901 && inst
.operands
[i
].writeback
),
6903 inst
.instruction
|= HWOFFSET_IMM
;
6904 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6905 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6909 /* inst.operands[i] was set up by parse_address. Encode it into an
6910 ARM-format instruction. Reject all forms which cannot be encoded
6911 into a coprocessor load/store instruction. If wb_ok is false,
6912 reject use of writeback; if unind_ok is false, reject use of
6913 unindexed addressing. If reloc_override is not 0, use it instead
6914 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6915 (in which case it is preserved). */
6918 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6920 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6922 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6924 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6926 gas_assert (!inst
.operands
[i
].writeback
);
6929 inst
.error
= _("instruction does not support unindexed addressing");
6932 inst
.instruction
|= inst
.operands
[i
].imm
;
6933 inst
.instruction
|= INDEX_UP
;
6937 if (inst
.operands
[i
].preind
)
6938 inst
.instruction
|= PRE_INDEX
;
6940 if (inst
.operands
[i
].writeback
)
6942 if (inst
.operands
[i
].reg
== REG_PC
)
6944 inst
.error
= _("pc may not be used with write-back");
6949 inst
.error
= _("instruction does not support writeback");
6952 inst
.instruction
|= WRITE_BACK
;
6956 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6957 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6958 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6959 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6962 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6964 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6970 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6971 Determine whether it can be performed with a move instruction; if
6972 it can, convert inst.instruction to that move instruction and
6973 return TRUE; if it can't, convert inst.instruction to a literal-pool
6974 load and return FALSE. If this is not a valid thing to do in the
6975 current context, set inst.error and return TRUE.
6977 inst.operands[i] describes the destination register. */
6980 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6985 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6989 if ((inst
.instruction
& tbit
) == 0)
6991 inst
.error
= _("invalid pseudo operation");
6994 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6996 inst
.error
= _("constant expression expected");
6999 if (inst
.reloc
.exp
.X_op
== O_constant
)
7003 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7005 /* This can be done with a mov(1) instruction. */
7006 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7007 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7013 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7016 /* This can be done with a mov instruction. */
7017 inst
.instruction
&= LITERAL_MASK
;
7018 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7019 inst
.instruction
|= value
& 0xfff;
7023 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7026 /* This can be done with a mvn instruction. */
7027 inst
.instruction
&= LITERAL_MASK
;
7028 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7029 inst
.instruction
|= value
& 0xfff;
7035 if (add_to_lit_pool () == FAIL
)
7037 inst
.error
= _("literal pool insertion failed");
7040 inst
.operands
[1].reg
= REG_PC
;
7041 inst
.operands
[1].isreg
= 1;
7042 inst
.operands
[1].preind
= 1;
7043 inst
.reloc
.pc_rel
= 1;
7044 inst
.reloc
.type
= (thumb_p
7045 ? BFD_RELOC_ARM_THUMB_OFFSET
7047 ? BFD_RELOC_ARM_HWLITERAL
7048 : BFD_RELOC_ARM_LITERAL
));
7052 /* Functions for instruction encoding, sorted by sub-architecture.
7053 First some generics; their names are taken from the conventional
7054 bit positions for register arguments in ARM format instructions. */
7064 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7070 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7071 inst
.instruction
|= inst
.operands
[1].reg
;
7077 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7078 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7084 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7085 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7091 unsigned Rn
= inst
.operands
[2].reg
;
7092 /* Enforce restrictions on SWP instruction. */
7093 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7095 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7096 _("Rn must not overlap other operands"));
7098 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7099 if (warn_on_deprecated
7100 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7101 as_warn (_("swp{b} use is deprecated for this architecture"));
7104 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7105 inst
.instruction
|= inst
.operands
[1].reg
;
7106 inst
.instruction
|= Rn
<< 16;
7112 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7113 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7114 inst
.instruction
|= inst
.operands
[2].reg
;
7120 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7121 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7122 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7123 || inst
.reloc
.exp
.X_add_number
!= 0),
7125 inst
.instruction
|= inst
.operands
[0].reg
;
7126 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7127 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7133 inst
.instruction
|= inst
.operands
[0].imm
;
7139 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7140 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7143 /* ARM instructions, in alphabetical order by function name (except
7144 that wrapper functions appear immediately after the function they
7147 /* This is a pseudo-op of the form "adr rd, label" to be converted
7148 into a relative address of the form "add rd, pc, #label-.-8". */
7153 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7155 /* Frag hacking will turn this into a sub instruction if the offset turns
7156 out to be negative. */
7157 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7158 inst
.reloc
.pc_rel
= 1;
7159 inst
.reloc
.exp
.X_add_number
-= 8;
7162 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7163 into a relative address of the form:
7164 add rd, pc, #low(label-.-8)"
7165 add rd, rd, #high(label-.-8)" */
7170 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7172 /* Frag hacking will turn this into a sub instruction if the offset turns
7173 out to be negative. */
7174 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7175 inst
.reloc
.pc_rel
= 1;
7176 inst
.size
= INSN_SIZE
* 2;
7177 inst
.reloc
.exp
.X_add_number
-= 8;
7183 if (!inst
.operands
[1].present
)
7184 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7185 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7186 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7187 encode_arm_shifter_operand (2);
7193 if (inst
.operands
[0].present
)
7195 constraint ((inst
.instruction
& 0xf0) != 0x40
7196 && inst
.operands
[0].imm
> 0xf
7197 && inst
.operands
[0].imm
< 0x0,
7198 _("bad barrier type"));
7199 inst
.instruction
|= inst
.operands
[0].imm
;
7202 inst
.instruction
|= 0xf;
7208 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7209 constraint (msb
> 32, _("bit-field extends past end of register"));
7210 /* The instruction encoding stores the LSB and MSB,
7211 not the LSB and width. */
7212 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7213 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7214 inst
.instruction
|= (msb
- 1) << 16;
7222 /* #0 in second position is alternative syntax for bfc, which is
7223 the same instruction but with REG_PC in the Rm field. */
7224 if (!inst
.operands
[1].isreg
)
7225 inst
.operands
[1].reg
= REG_PC
;
7227 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7228 constraint (msb
> 32, _("bit-field extends past end of register"));
7229 /* The instruction encoding stores the LSB and MSB,
7230 not the LSB and width. */
7231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7232 inst
.instruction
|= inst
.operands
[1].reg
;
7233 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7234 inst
.instruction
|= (msb
- 1) << 16;
7240 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7241 _("bit-field extends past end of register"));
7242 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7243 inst
.instruction
|= inst
.operands
[1].reg
;
7244 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7245 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7248 /* ARM V5 breakpoint instruction (argument parse)
7249 BKPT <16 bit unsigned immediate>
7250 Instruction is not conditional.
7251 The bit pattern given in insns[] has the COND_ALWAYS condition,
7252 and it is an error if the caller tried to override that. */
7257 /* Top 12 of 16 bits to bits 19:8. */
7258 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7260 /* Bottom 4 of 16 bits to bits 3:0. */
7261 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7265 encode_branch (int default_reloc
)
7267 if (inst
.operands
[0].hasreloc
)
7269 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7270 _("the only suffix valid here is '(plt)'"));
7271 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7275 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7277 inst
.reloc
.pc_rel
= 1;
7284 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7285 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7288 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7295 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7297 if (inst
.cond
== COND_ALWAYS
)
7298 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7300 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7304 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7307 /* ARM V5 branch-link-exchange instruction (argument parse)
7308 BLX <target_addr> ie BLX(1)
7309 BLX{<condition>} <Rm> ie BLX(2)
7310 Unfortunately, there are two different opcodes for this mnemonic.
7311 So, the insns[].value is not used, and the code here zaps values
7312 into inst.instruction.
7313 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7318 if (inst
.operands
[0].isreg
)
7320 /* Arg is a register; the opcode provided by insns[] is correct.
7321 It is not illegal to do "blx pc", just useless. */
7322 if (inst
.operands
[0].reg
== REG_PC
)
7323 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7325 inst
.instruction
|= inst
.operands
[0].reg
;
7329 /* Arg is an address; this instruction cannot be executed
7330 conditionally, and the opcode must be adjusted.
7331 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7332 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7333 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7334 inst
.instruction
= 0xfa000000;
7335 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7342 bfd_boolean want_reloc
;
7344 if (inst
.operands
[0].reg
== REG_PC
)
7345 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7347 inst
.instruction
|= inst
.operands
[0].reg
;
7348 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7349 it is for ARMv4t or earlier. */
7350 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7351 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7355 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7360 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7364 /* ARM v5TEJ. Jump to Jazelle code. */
7369 if (inst
.operands
[0].reg
== REG_PC
)
7370 as_tsktsk (_("use of r15 in bxj is not really useful"));
7372 inst
.instruction
|= inst
.operands
[0].reg
;
7375 /* Co-processor data operation:
7376 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7377 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7381 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7382 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7383 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7384 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7385 inst
.instruction
|= inst
.operands
[4].reg
;
7386 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7392 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7393 encode_arm_shifter_operand (1);
7396 /* Transfer between coprocessor and ARM registers.
7397 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7402 No special properties. */
7409 Rd
= inst
.operands
[2].reg
;
7412 if (inst
.instruction
== 0xee000010
7413 || inst
.instruction
== 0xfe000010)
7415 reject_bad_reg (Rd
);
7418 constraint (Rd
== REG_SP
, BAD_SP
);
7423 if (inst
.instruction
== 0xe000010)
7424 constraint (Rd
== REG_PC
, BAD_PC
);
7428 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7429 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7430 inst
.instruction
|= Rd
<< 12;
7431 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7432 inst
.instruction
|= inst
.operands
[4].reg
;
7433 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7436 /* Transfer between coprocessor register and pair of ARM registers.
7437 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7442 Two XScale instructions are special cases of these:
7444 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7445 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7447 Result unpredictable if Rd or Rn is R15. */
7454 Rd
= inst
.operands
[2].reg
;
7455 Rn
= inst
.operands
[3].reg
;
7459 reject_bad_reg (Rd
);
7460 reject_bad_reg (Rn
);
7464 constraint (Rd
== REG_PC
, BAD_PC
);
7465 constraint (Rn
== REG_PC
, BAD_PC
);
7468 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7469 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7470 inst
.instruction
|= Rd
<< 12;
7471 inst
.instruction
|= Rn
<< 16;
7472 inst
.instruction
|= inst
.operands
[4].reg
;
7478 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7479 if (inst
.operands
[1].present
)
7481 inst
.instruction
|= CPSI_MMOD
;
7482 inst
.instruction
|= inst
.operands
[1].imm
;
7489 inst
.instruction
|= inst
.operands
[0].imm
;
7495 /* There is no IT instruction in ARM mode. We
7496 process it to do the validation as if in
7497 thumb mode, just in case the code gets
7498 assembled for thumb using the unified syntax. */
7503 set_it_insn_type (IT_INSN
);
7504 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7505 now_it
.cc
= inst
.operands
[0].imm
;
7512 int base_reg
= inst
.operands
[0].reg
;
7513 int range
= inst
.operands
[1].imm
;
7515 inst
.instruction
|= base_reg
<< 16;
7516 inst
.instruction
|= range
;
7518 if (inst
.operands
[1].writeback
)
7519 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7521 if (inst
.operands
[0].writeback
)
7523 inst
.instruction
|= WRITE_BACK
;
7524 /* Check for unpredictable uses of writeback. */
7525 if (inst
.instruction
& LOAD_BIT
)
7527 /* Not allowed in LDM type 2. */
7528 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7529 && ((range
& (1 << REG_PC
)) == 0))
7530 as_warn (_("writeback of base register is UNPREDICTABLE"));
7531 /* Only allowed if base reg not in list for other types. */
7532 else if (range
& (1 << base_reg
))
7533 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7537 /* Not allowed for type 2. */
7538 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7539 as_warn (_("writeback of base register is UNPREDICTABLE"));
7540 /* Only allowed if base reg not in list, or first in list. */
7541 else if ((range
& (1 << base_reg
))
7542 && (range
& ((1 << base_reg
) - 1)))
7543 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7548 /* ARMv5TE load-consecutive (argument parse)
7557 constraint (inst
.operands
[0].reg
% 2 != 0,
7558 _("first destination register must be even"));
7559 constraint (inst
.operands
[1].present
7560 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7561 _("can only load two consecutive registers"));
7562 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7563 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7565 if (!inst
.operands
[1].present
)
7566 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7568 if (inst
.instruction
& LOAD_BIT
)
7570 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7571 register and the first register written; we have to diagnose
7572 overlap between the base and the second register written here. */
7574 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7575 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7576 as_warn (_("base register written back, and overlaps "
7577 "second destination register"));
7579 /* For an index-register load, the index register must not overlap the
7580 destination (even if not write-back). */
7581 else if (inst
.operands
[2].immisreg
7582 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7583 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7584 as_warn (_("index register overlaps destination register"));
7587 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7588 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7594 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7595 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7596 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7597 || inst
.operands
[1].negative
7598 /* This can arise if the programmer has written
7600 or if they have mistakenly used a register name as the last
7603 It is very difficult to distinguish between these two cases
7604 because "rX" might actually be a label. ie the register
7605 name has been occluded by a symbol of the same name. So we
7606 just generate a general 'bad addressing mode' type error
7607 message and leave it up to the programmer to discover the
7608 true cause and fix their mistake. */
7609 || (inst
.operands
[1].reg
== REG_PC
),
7612 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7613 || inst
.reloc
.exp
.X_add_number
!= 0,
7614 _("offset must be zero in ARM encoding"));
7616 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7618 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7619 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7620 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7626 constraint (inst
.operands
[0].reg
% 2 != 0,
7627 _("even register required"));
7628 constraint (inst
.operands
[1].present
7629 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7630 _("can only load two consecutive registers"));
7631 /* If op 1 were present and equal to PC, this function wouldn't
7632 have been called in the first place. */
7633 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7635 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7636 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7642 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7643 if (!inst
.operands
[1].isreg
)
7644 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7646 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7652 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7654 if (inst
.operands
[1].preind
)
7656 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7657 || inst
.reloc
.exp
.X_add_number
!= 0,
7658 _("this instruction requires a post-indexed address"));
7660 inst
.operands
[1].preind
= 0;
7661 inst
.operands
[1].postind
= 1;
7662 inst
.operands
[1].writeback
= 1;
7664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7665 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7668 /* Halfword and signed-byte load/store operations. */
7673 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7675 if (!inst
.operands
[1].isreg
)
7676 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7678 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7684 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7686 if (inst
.operands
[1].preind
)
7688 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7689 || inst
.reloc
.exp
.X_add_number
!= 0,
7690 _("this instruction requires a post-indexed address"));
7692 inst
.operands
[1].preind
= 0;
7693 inst
.operands
[1].postind
= 1;
7694 inst
.operands
[1].writeback
= 1;
7696 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7697 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7700 /* Co-processor register load/store.
7701 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7705 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7706 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7707 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7713 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7714 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7715 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7716 && !(inst
.instruction
& 0x00400000))
7717 as_tsktsk (_("Rd and Rm should be different in mla"));
7719 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7720 inst
.instruction
|= inst
.operands
[1].reg
;
7721 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7722 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7728 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7729 encode_arm_shifter_operand (1);
7732 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7739 top
= (inst
.instruction
& 0x00400000) != 0;
7740 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7741 _(":lower16: not allowed this instruction"));
7742 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7743 _(":upper16: not allowed instruction"));
7744 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7745 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7747 imm
= inst
.reloc
.exp
.X_add_number
;
7748 /* The value is in two pieces: 0:11, 16:19. */
7749 inst
.instruction
|= (imm
& 0x00000fff);
7750 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7754 static void do_vfp_nsyn_opcode (const char *);
7757 do_vfp_nsyn_mrs (void)
7759 if (inst
.operands
[0].isvec
)
7761 if (inst
.operands
[1].reg
!= 1)
7762 first_error (_("operand 1 must be FPSCR"));
7763 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7764 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7765 do_vfp_nsyn_opcode ("fmstat");
7767 else if (inst
.operands
[1].isvec
)
7768 do_vfp_nsyn_opcode ("fmrx");
7776 do_vfp_nsyn_msr (void)
7778 if (inst
.operands
[0].isvec
)
7779 do_vfp_nsyn_opcode ("fmxr");
7789 unsigned Rt
= inst
.operands
[0].reg
;
7791 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7793 inst
.error
= BAD_SP
;
7797 /* APSR_ sets isvec. All other refs to PC are illegal. */
7798 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7800 inst
.error
= BAD_PC
;
7804 if (inst
.operands
[1].reg
!= 1)
7805 first_error (_("operand 1 must be FPSCR"));
7807 inst
.instruction
|= (Rt
<< 12);
7813 unsigned Rt
= inst
.operands
[1].reg
;
7816 reject_bad_reg (Rt
);
7817 else if (Rt
== REG_PC
)
7819 inst
.error
= BAD_PC
;
7823 if (inst
.operands
[0].reg
!= 1)
7824 first_error (_("operand 0 must be FPSCR"));
7826 inst
.instruction
|= (Rt
<< 12);
7832 if (do_vfp_nsyn_mrs () == SUCCESS
)
7835 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7836 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7838 _("'CPSR' or 'SPSR' expected"));
7839 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7840 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7841 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7844 /* Two possible forms:
7845 "{C|S}PSR_<field>, Rm",
7846 "{C|S}PSR_f, #expression". */
7851 if (do_vfp_nsyn_msr () == SUCCESS
)
7854 inst
.instruction
|= inst
.operands
[0].imm
;
7855 if (inst
.operands
[1].isreg
)
7856 inst
.instruction
|= inst
.operands
[1].reg
;
7859 inst
.instruction
|= INST_IMMEDIATE
;
7860 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7861 inst
.reloc
.pc_rel
= 0;
7868 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7870 if (!inst
.operands
[2].present
)
7871 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7872 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7873 inst
.instruction
|= inst
.operands
[1].reg
;
7874 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7876 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7877 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7878 as_tsktsk (_("Rd and Rm should be different in mul"));
7881 /* Long Multiply Parser
7882 UMULL RdLo, RdHi, Rm, Rs
7883 SMULL RdLo, RdHi, Rm, Rs
7884 UMLAL RdLo, RdHi, Rm, Rs
7885 SMLAL RdLo, RdHi, Rm, Rs. */
7890 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7891 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7892 inst
.instruction
|= inst
.operands
[2].reg
;
7893 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7895 /* rdhi and rdlo must be different. */
7896 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7897 as_tsktsk (_("rdhi and rdlo must be different"));
7899 /* rdhi, rdlo and rm must all be different before armv6. */
7900 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7901 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7902 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7903 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7909 if (inst
.operands
[0].present
7910 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7912 /* Architectural NOP hints are CPSR sets with no bits selected. */
7913 inst
.instruction
&= 0xf0000000;
7914 inst
.instruction
|= 0x0320f000;
7915 if (inst
.operands
[0].present
)
7916 inst
.instruction
|= inst
.operands
[0].imm
;
7920 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7921 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7922 Condition defaults to COND_ALWAYS.
7923 Error if Rd, Rn or Rm are R15. */
7928 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7929 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7930 inst
.instruction
|= inst
.operands
[2].reg
;
7931 if (inst
.operands
[3].present
)
7932 encode_arm_shift (3);
7935 /* ARM V6 PKHTB (Argument Parse). */
7940 if (!inst
.operands
[3].present
)
7942 /* If the shift specifier is omitted, turn the instruction
7943 into pkhbt rd, rm, rn. */
7944 inst
.instruction
&= 0xfff00010;
7945 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7946 inst
.instruction
|= inst
.operands
[1].reg
;
7947 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7951 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7952 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7953 inst
.instruction
|= inst
.operands
[2].reg
;
7954 encode_arm_shift (3);
7958 /* ARMv5TE: Preload-Cache
7959 MP Extensions: Preload for write
7963 Syntactically, like LDR with B=1, W=0, L=1. */
7968 constraint (!inst
.operands
[0].isreg
,
7969 _("'[' expected after PLD mnemonic"));
7970 constraint (inst
.operands
[0].postind
,
7971 _("post-indexed expression used in preload instruction"));
7972 constraint (inst
.operands
[0].writeback
,
7973 _("writeback used in preload instruction"));
7974 constraint (!inst
.operands
[0].preind
,
7975 _("unindexed addressing used in preload instruction"));
7976 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7979 /* ARMv7: PLI <addr_mode> */
7983 constraint (!inst
.operands
[0].isreg
,
7984 _("'[' expected after PLI mnemonic"));
7985 constraint (inst
.operands
[0].postind
,
7986 _("post-indexed expression used in preload instruction"));
7987 constraint (inst
.operands
[0].writeback
,
7988 _("writeback used in preload instruction"));
7989 constraint (!inst
.operands
[0].preind
,
7990 _("unindexed addressing used in preload instruction"));
7991 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7992 inst
.instruction
&= ~PRE_INDEX
;
7998 inst
.operands
[1] = inst
.operands
[0];
7999 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8000 inst
.operands
[0].isreg
= 1;
8001 inst
.operands
[0].writeback
= 1;
8002 inst
.operands
[0].reg
= REG_SP
;
8006 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8007 word at the specified address and the following word
8009 Unconditionally executed.
8010 Error if Rn is R15. */
8015 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8016 if (inst
.operands
[0].writeback
)
8017 inst
.instruction
|= WRITE_BACK
;
8020 /* ARM V6 ssat (argument parse). */
8025 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8026 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8027 inst
.instruction
|= inst
.operands
[2].reg
;
8029 if (inst
.operands
[3].present
)
8030 encode_arm_shift (3);
8033 /* ARM V6 usat (argument parse). */
8038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8039 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8040 inst
.instruction
|= inst
.operands
[2].reg
;
8042 if (inst
.operands
[3].present
)
8043 encode_arm_shift (3);
8046 /* ARM V6 ssat16 (argument parse). */
8051 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8052 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8053 inst
.instruction
|= inst
.operands
[2].reg
;
8059 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8060 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8061 inst
.instruction
|= inst
.operands
[2].reg
;
8064 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8065 preserving the other bits.
8067 setend <endian_specifier>, where <endian_specifier> is either
8073 if (inst
.operands
[0].imm
)
8074 inst
.instruction
|= 0x200;
8080 unsigned int Rm
= (inst
.operands
[1].present
8081 ? inst
.operands
[1].reg
8082 : inst
.operands
[0].reg
);
8084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8085 inst
.instruction
|= Rm
;
8086 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8088 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8089 inst
.instruction
|= SHIFT_BY_REG
;
8092 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8098 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8099 inst
.reloc
.pc_rel
= 0;
8105 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8106 inst
.reloc
.pc_rel
= 0;
8109 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8110 SMLAxy{cond} Rd,Rm,Rs,Rn
8111 SMLAWy{cond} Rd,Rm,Rs,Rn
8112 Error if any register is R15. */
8117 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8118 inst
.instruction
|= inst
.operands
[1].reg
;
8119 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8120 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8123 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8124 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8125 Error if any register is R15.
8126 Warning if Rdlo == Rdhi. */
8131 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8132 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8133 inst
.instruction
|= inst
.operands
[2].reg
;
8134 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8136 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8137 as_tsktsk (_("rdhi and rdlo must be different"));
8140 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8141 SMULxy{cond} Rd,Rm,Rs
8142 Error if any register is R15. */
8147 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8148 inst
.instruction
|= inst
.operands
[1].reg
;
8149 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8152 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8153 the same for both ARM and Thumb-2. */
8160 if (inst
.operands
[0].present
)
8162 reg
= inst
.operands
[0].reg
;
8163 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8168 inst
.instruction
|= reg
<< 16;
8169 inst
.instruction
|= inst
.operands
[1].imm
;
8170 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8171 inst
.instruction
|= WRITE_BACK
;
8174 /* ARM V6 strex (argument parse). */
8179 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8180 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8181 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8182 || inst
.operands
[2].negative
8183 /* See comment in do_ldrex(). */
8184 || (inst
.operands
[2].reg
== REG_PC
),
8187 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8188 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8190 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8191 || inst
.reloc
.exp
.X_add_number
!= 0,
8192 _("offset must be zero in ARM encoding"));
8194 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8195 inst
.instruction
|= inst
.operands
[1].reg
;
8196 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8197 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8203 constraint (inst
.operands
[1].reg
% 2 != 0,
8204 _("even register required"));
8205 constraint (inst
.operands
[2].present
8206 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8207 _("can only store two consecutive registers"));
8208 /* If op 2 were present and equal to PC, this function wouldn't
8209 have been called in the first place. */
8210 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8212 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8213 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8214 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8217 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8218 inst
.instruction
|= inst
.operands
[1].reg
;
8219 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8222 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8223 extends it to 32-bits, and adds the result to a value in another
8224 register. You can specify a rotation by 0, 8, 16, or 24 bits
8225 before extracting the 16-bit value.
8226 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8227 Condition defaults to COND_ALWAYS.
8228 Error if any register uses R15. */
8233 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8234 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8235 inst
.instruction
|= inst
.operands
[2].reg
;
8236 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8241 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8242 Condition defaults to COND_ALWAYS.
8243 Error if any register uses R15. */
8248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8249 inst
.instruction
|= inst
.operands
[1].reg
;
8250 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8253 /* VFP instructions. In a logical order: SP variant first, monad
8254 before dyad, arithmetic then move then load/store. */
8257 do_vfp_sp_monadic (void)
8259 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8260 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8264 do_vfp_sp_dyadic (void)
8266 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8267 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8268 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8272 do_vfp_sp_compare_z (void)
8274 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8278 do_vfp_dp_sp_cvt (void)
8280 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8281 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8285 do_vfp_sp_dp_cvt (void)
8287 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8288 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8292 do_vfp_reg_from_sp (void)
8294 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8295 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8299 do_vfp_reg2_from_sp2 (void)
8301 constraint (inst
.operands
[2].imm
!= 2,
8302 _("only two consecutive VFP SP registers allowed here"));
8303 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8304 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8305 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8309 do_vfp_sp_from_reg (void)
8311 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8312 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8316 do_vfp_sp2_from_reg2 (void)
8318 constraint (inst
.operands
[0].imm
!= 2,
8319 _("only two consecutive VFP SP registers allowed here"));
8320 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8321 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8322 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8326 do_vfp_sp_ldst (void)
8328 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8329 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8333 do_vfp_dp_ldst (void)
8335 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8336 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8341 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8343 if (inst
.operands
[0].writeback
)
8344 inst
.instruction
|= WRITE_BACK
;
8346 constraint (ldstm_type
!= VFP_LDSTMIA
,
8347 _("this addressing mode requires base-register writeback"));
8348 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8349 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8350 inst
.instruction
|= inst
.operands
[1].imm
;
8354 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8358 if (inst
.operands
[0].writeback
)
8359 inst
.instruction
|= WRITE_BACK
;
8361 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8362 _("this addressing mode requires base-register writeback"));
8364 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8365 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8367 count
= inst
.operands
[1].imm
<< 1;
8368 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8371 inst
.instruction
|= count
;
8375 do_vfp_sp_ldstmia (void)
8377 vfp_sp_ldstm (VFP_LDSTMIA
);
8381 do_vfp_sp_ldstmdb (void)
8383 vfp_sp_ldstm (VFP_LDSTMDB
);
8387 do_vfp_dp_ldstmia (void)
8389 vfp_dp_ldstm (VFP_LDSTMIA
);
8393 do_vfp_dp_ldstmdb (void)
8395 vfp_dp_ldstm (VFP_LDSTMDB
);
8399 do_vfp_xp_ldstmia (void)
8401 vfp_dp_ldstm (VFP_LDSTMIAX
);
8405 do_vfp_xp_ldstmdb (void)
8407 vfp_dp_ldstm (VFP_LDSTMDBX
);
8411 do_vfp_dp_rd_rm (void)
8413 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8414 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8418 do_vfp_dp_rn_rd (void)
8420 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8421 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8425 do_vfp_dp_rd_rn (void)
8427 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8428 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8432 do_vfp_dp_rd_rn_rm (void)
8434 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8435 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8436 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8442 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8446 do_vfp_dp_rm_rd_rn (void)
8448 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8449 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8450 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8453 /* VFPv3 instructions. */
8455 do_vfp_sp_const (void)
8457 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8458 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8459 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8463 do_vfp_dp_const (void)
8465 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8466 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8467 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8471 vfp_conv (int srcsize
)
8473 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8474 inst
.instruction
|= (immbits
& 1) << 5;
8475 inst
.instruction
|= (immbits
>> 1);
8479 do_vfp_sp_conv_16 (void)
8481 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8486 do_vfp_dp_conv_16 (void)
8488 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8493 do_vfp_sp_conv_32 (void)
8495 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8500 do_vfp_dp_conv_32 (void)
8502 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8506 /* FPA instructions. Also in a logical order. */
8511 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8512 inst
.instruction
|= inst
.operands
[1].reg
;
8516 do_fpa_ldmstm (void)
8518 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8519 switch (inst
.operands
[1].imm
)
8521 case 1: inst
.instruction
|= CP_T_X
; break;
8522 case 2: inst
.instruction
|= CP_T_Y
; break;
8523 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8528 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8530 /* The instruction specified "ea" or "fd", so we can only accept
8531 [Rn]{!}. The instruction does not really support stacking or
8532 unstacking, so we have to emulate these by setting appropriate
8533 bits and offsets. */
8534 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8535 || inst
.reloc
.exp
.X_add_number
!= 0,
8536 _("this instruction does not support indexing"));
8538 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8539 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8541 if (!(inst
.instruction
& INDEX_UP
))
8542 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8544 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8546 inst
.operands
[2].preind
= 0;
8547 inst
.operands
[2].postind
= 1;
8551 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8554 /* iWMMXt instructions: strictly in alphabetical order. */
8557 do_iwmmxt_tandorc (void)
8559 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8563 do_iwmmxt_textrc (void)
8565 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8566 inst
.instruction
|= inst
.operands
[1].imm
;
8570 do_iwmmxt_textrm (void)
8572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8573 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8574 inst
.instruction
|= inst
.operands
[2].imm
;
8578 do_iwmmxt_tinsr (void)
8580 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8581 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8582 inst
.instruction
|= inst
.operands
[2].imm
;
8586 do_iwmmxt_tmia (void)
8588 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8589 inst
.instruction
|= inst
.operands
[1].reg
;
8590 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8594 do_iwmmxt_waligni (void)
8596 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8597 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8598 inst
.instruction
|= inst
.operands
[2].reg
;
8599 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8603 do_iwmmxt_wmerge (void)
8605 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8606 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8607 inst
.instruction
|= inst
.operands
[2].reg
;
8608 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8612 do_iwmmxt_wmov (void)
8614 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8615 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8616 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8617 inst
.instruction
|= inst
.operands
[1].reg
;
8621 do_iwmmxt_wldstbh (void)
8624 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8626 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8628 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8629 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8633 do_iwmmxt_wldstw (void)
8635 /* RIWR_RIWC clears .isreg for a control register. */
8636 if (!inst
.operands
[0].isreg
)
8638 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8639 inst
.instruction
|= 0xf0000000;
8642 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8643 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8647 do_iwmmxt_wldstd (void)
8649 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8650 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8651 && inst
.operands
[1].immisreg
)
8653 inst
.instruction
&= ~0x1a000ff;
8654 inst
.instruction
|= (0xf << 28);
8655 if (inst
.operands
[1].preind
)
8656 inst
.instruction
|= PRE_INDEX
;
8657 if (!inst
.operands
[1].negative
)
8658 inst
.instruction
|= INDEX_UP
;
8659 if (inst
.operands
[1].writeback
)
8660 inst
.instruction
|= WRITE_BACK
;
8661 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8662 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8663 inst
.instruction
|= inst
.operands
[1].imm
;
8666 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8670 do_iwmmxt_wshufh (void)
8672 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8673 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8674 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8675 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8679 do_iwmmxt_wzero (void)
8681 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8682 inst
.instruction
|= inst
.operands
[0].reg
;
8683 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8684 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8688 do_iwmmxt_wrwrwr_or_imm5 (void)
8690 if (inst
.operands
[2].isreg
)
8693 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8694 _("immediate operand requires iWMMXt2"));
8696 if (inst
.operands
[2].imm
== 0)
8698 switch ((inst
.instruction
>> 20) & 0xf)
8704 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8705 inst
.operands
[2].imm
= 16;
8706 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8712 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8713 inst
.operands
[2].imm
= 32;
8714 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8721 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8723 wrn
= (inst
.instruction
>> 16) & 0xf;
8724 inst
.instruction
&= 0xff0fff0f;
8725 inst
.instruction
|= wrn
;
8726 /* Bail out here; the instruction is now assembled. */
8731 /* Map 32 -> 0, etc. */
8732 inst
.operands
[2].imm
&= 0x1f;
8733 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8737 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8738 operations first, then control, shift, and load/store. */
8740 /* Insns like "foo X,Y,Z". */
8743 do_mav_triple (void)
8745 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8746 inst
.instruction
|= inst
.operands
[1].reg
;
8747 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8750 /* Insns like "foo W,X,Y,Z".
8751 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8756 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8757 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8758 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8759 inst
.instruction
|= inst
.operands
[3].reg
;
8762 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8766 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8769 /* Maverick shift immediate instructions.
8770 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8771 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8776 int imm
= inst
.operands
[2].imm
;
8778 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8779 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8781 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8782 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8783 Bit 4 should be 0. */
8784 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8786 inst
.instruction
|= imm
;
8789 /* XScale instructions. Also sorted arithmetic before move. */
8791 /* Xscale multiply-accumulate (argument parse)
8794 MIAxycc acc0,Rm,Rs. */
8799 inst
.instruction
|= inst
.operands
[1].reg
;
8800 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8803 /* Xscale move-accumulator-register (argument parse)
8805 MARcc acc0,RdLo,RdHi. */
8810 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8811 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8814 /* Xscale move-register-accumulator (argument parse)
8816 MRAcc RdLo,RdHi,acc0. */
8821 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8822 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8823 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8826 /* Encoding functions relevant only to Thumb. */
8828 /* inst.operands[i] is a shifted-register operand; encode
8829 it into inst.instruction in the format used by Thumb32. */
8832 encode_thumb32_shifted_operand (int i
)
8834 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8835 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8837 constraint (inst
.operands
[i
].immisreg
,
8838 _("shift by register not allowed in thumb mode"));
8839 inst
.instruction
|= inst
.operands
[i
].reg
;
8840 if (shift
== SHIFT_RRX
)
8841 inst
.instruction
|= SHIFT_ROR
<< 4;
8844 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8845 _("expression too complex"));
8847 constraint (value
> 32
8848 || (value
== 32 && (shift
== SHIFT_LSL
8849 || shift
== SHIFT_ROR
)),
8850 _("shift expression is too large"));
8854 else if (value
== 32)
8857 inst
.instruction
|= shift
<< 4;
8858 inst
.instruction
|= (value
& 0x1c) << 10;
8859 inst
.instruction
|= (value
& 0x03) << 6;
8864 /* inst.operands[i] was set up by parse_address. Encode it into a
8865 Thumb32 format load or store instruction. Reject forms that cannot
8866 be used with such instructions. If is_t is true, reject forms that
8867 cannot be used with a T instruction; if is_d is true, reject forms
8868 that cannot be used with a D instruction. If it is a store insn,
8872 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8874 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8876 constraint (!inst
.operands
[i
].isreg
,
8877 _("Instruction does not support =N addresses"));
8879 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8880 if (inst
.operands
[i
].immisreg
)
8882 constraint (is_pc
, BAD_PC_ADDRESSING
);
8883 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8884 constraint (inst
.operands
[i
].negative
,
8885 _("Thumb does not support negative register indexing"));
8886 constraint (inst
.operands
[i
].postind
,
8887 _("Thumb does not support register post-indexing"));
8888 constraint (inst
.operands
[i
].writeback
,
8889 _("Thumb does not support register indexing with writeback"));
8890 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8891 _("Thumb supports only LSL in shifted register indexing"));
8893 inst
.instruction
|= inst
.operands
[i
].imm
;
8894 if (inst
.operands
[i
].shifted
)
8896 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8897 _("expression too complex"));
8898 constraint (inst
.reloc
.exp
.X_add_number
< 0
8899 || inst
.reloc
.exp
.X_add_number
> 3,
8900 _("shift out of range"));
8901 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8903 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8905 else if (inst
.operands
[i
].preind
)
8907 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8908 constraint (is_t
&& inst
.operands
[i
].writeback
,
8909 _("cannot use writeback with this instruction"));
8910 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8911 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8915 inst
.instruction
|= 0x01000000;
8916 if (inst
.operands
[i
].writeback
)
8917 inst
.instruction
|= 0x00200000;
8921 inst
.instruction
|= 0x00000c00;
8922 if (inst
.operands
[i
].writeback
)
8923 inst
.instruction
|= 0x00000100;
8925 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8927 else if (inst
.operands
[i
].postind
)
8929 gas_assert (inst
.operands
[i
].writeback
);
8930 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8931 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8934 inst
.instruction
|= 0x00200000;
8936 inst
.instruction
|= 0x00000900;
8937 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8939 else /* unindexed - only for coprocessor */
8940 inst
.error
= _("instruction does not accept unindexed addressing");
8943 /* Table of Thumb instructions which exist in both 16- and 32-bit
8944 encodings (the latter only in post-V6T2 cores). The index is the
8945 value used in the insns table below. When there is more than one
8946 possible 16-bit encoding for the instruction, this table always
8948 Also contains several pseudo-instructions used during relaxation. */
8949 #define T16_32_TAB \
8950 X(_adc, 4140, eb400000), \
8951 X(_adcs, 4140, eb500000), \
8952 X(_add, 1c00, eb000000), \
8953 X(_adds, 1c00, eb100000), \
8954 X(_addi, 0000, f1000000), \
8955 X(_addis, 0000, f1100000), \
8956 X(_add_pc,000f, f20f0000), \
8957 X(_add_sp,000d, f10d0000), \
8958 X(_adr, 000f, f20f0000), \
8959 X(_and, 4000, ea000000), \
8960 X(_ands, 4000, ea100000), \
8961 X(_asr, 1000, fa40f000), \
8962 X(_asrs, 1000, fa50f000), \
8963 X(_b, e000, f000b000), \
8964 X(_bcond, d000, f0008000), \
8965 X(_bic, 4380, ea200000), \
8966 X(_bics, 4380, ea300000), \
8967 X(_cmn, 42c0, eb100f00), \
8968 X(_cmp, 2800, ebb00f00), \
8969 X(_cpsie, b660, f3af8400), \
8970 X(_cpsid, b670, f3af8600), \
8971 X(_cpy, 4600, ea4f0000), \
8972 X(_dec_sp,80dd, f1ad0d00), \
8973 X(_eor, 4040, ea800000), \
8974 X(_eors, 4040, ea900000), \
8975 X(_inc_sp,00dd, f10d0d00), \
8976 X(_ldmia, c800, e8900000), \
8977 X(_ldr, 6800, f8500000), \
8978 X(_ldrb, 7800, f8100000), \
8979 X(_ldrh, 8800, f8300000), \
8980 X(_ldrsb, 5600, f9100000), \
8981 X(_ldrsh, 5e00, f9300000), \
8982 X(_ldr_pc,4800, f85f0000), \
8983 X(_ldr_pc2,4800, f85f0000), \
8984 X(_ldr_sp,9800, f85d0000), \
8985 X(_lsl, 0000, fa00f000), \
8986 X(_lsls, 0000, fa10f000), \
8987 X(_lsr, 0800, fa20f000), \
8988 X(_lsrs, 0800, fa30f000), \
8989 X(_mov, 2000, ea4f0000), \
8990 X(_movs, 2000, ea5f0000), \
8991 X(_mul, 4340, fb00f000), \
8992 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8993 X(_mvn, 43c0, ea6f0000), \
8994 X(_mvns, 43c0, ea7f0000), \
8995 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8996 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8997 X(_orr, 4300, ea400000), \
8998 X(_orrs, 4300, ea500000), \
8999 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9000 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9001 X(_rev, ba00, fa90f080), \
9002 X(_rev16, ba40, fa90f090), \
9003 X(_revsh, bac0, fa90f0b0), \
9004 X(_ror, 41c0, fa60f000), \
9005 X(_rors, 41c0, fa70f000), \
9006 X(_sbc, 4180, eb600000), \
9007 X(_sbcs, 4180, eb700000), \
9008 X(_stmia, c000, e8800000), \
9009 X(_str, 6000, f8400000), \
9010 X(_strb, 7000, f8000000), \
9011 X(_strh, 8000, f8200000), \
9012 X(_str_sp,9000, f84d0000), \
9013 X(_sub, 1e00, eba00000), \
9014 X(_subs, 1e00, ebb00000), \
9015 X(_subi, 8000, f1a00000), \
9016 X(_subis, 8000, f1b00000), \
9017 X(_sxtb, b240, fa4ff080), \
9018 X(_sxth, b200, fa0ff080), \
9019 X(_tst, 4200, ea100f00), \
9020 X(_uxtb, b2c0, fa5ff080), \
9021 X(_uxth, b280, fa1ff080), \
9022 X(_nop, bf00, f3af8000), \
9023 X(_yield, bf10, f3af8001), \
9024 X(_wfe, bf20, f3af8002), \
9025 X(_wfi, bf30, f3af8003), \
9026 X(_sev, bf40, f3af8004),
9028 /* To catch errors in encoding functions, the codes are all offset by
9029 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9030 as 16-bit instructions. */
9031 #define X(a,b,c) T_MNEM##a
9032 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9035 #define X(a,b,c) 0x##b
9036 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9037 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9040 #define X(a,b,c) 0x##c
9041 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9042 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9043 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9047 /* Thumb instruction encoders, in alphabetical order. */
9052 do_t_add_sub_w (void)
9056 Rd
= inst
.operands
[0].reg
;
9057 Rn
= inst
.operands
[1].reg
;
9059 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9060 is the SP-{plus,minus}-immediate form of the instruction. */
9062 constraint (Rd
== REG_PC
, BAD_PC
);
9064 reject_bad_reg (Rd
);
9066 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9067 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9070 /* Parse an add or subtract instruction. We get here with inst.instruction
9071 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9078 Rd
= inst
.operands
[0].reg
;
9079 Rs
= (inst
.operands
[1].present
9080 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9081 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9084 set_it_insn_type_last ();
9092 flags
= (inst
.instruction
== T_MNEM_adds
9093 || inst
.instruction
== T_MNEM_subs
);
9095 narrow
= !in_it_block ();
9097 narrow
= in_it_block ();
9098 if (!inst
.operands
[2].isreg
)
9102 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9104 add
= (inst
.instruction
== T_MNEM_add
9105 || inst
.instruction
== T_MNEM_adds
);
9107 if (inst
.size_req
!= 4)
9109 /* Attempt to use a narrow opcode, with relaxation if
9111 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9112 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9113 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9114 opcode
= T_MNEM_add_sp
;
9115 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9116 opcode
= T_MNEM_add_pc
;
9117 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9120 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9122 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9126 inst
.instruction
= THUMB_OP16(opcode
);
9127 inst
.instruction
|= (Rd
<< 4) | Rs
;
9128 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9129 if (inst
.size_req
!= 2)
9130 inst
.relax
= opcode
;
9133 constraint (inst
.size_req
== 2, BAD_HIREG
);
9135 if (inst
.size_req
== 4
9136 || (inst
.size_req
!= 2 && !opcode
))
9140 constraint (add
, BAD_PC
);
9141 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9142 _("only SUBS PC, LR, #const allowed"));
9143 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9144 _("expression too complex"));
9145 constraint (inst
.reloc
.exp
.X_add_number
< 0
9146 || inst
.reloc
.exp
.X_add_number
> 0xff,
9147 _("immediate value out of range"));
9148 inst
.instruction
= T2_SUBS_PC_LR
9149 | inst
.reloc
.exp
.X_add_number
;
9150 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9153 else if (Rs
== REG_PC
)
9155 /* Always use addw/subw. */
9156 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9157 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9161 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9162 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9165 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9167 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9169 inst
.instruction
|= Rd
<< 8;
9170 inst
.instruction
|= Rs
<< 16;
9175 Rn
= inst
.operands
[2].reg
;
9176 /* See if we can do this with a 16-bit instruction. */
9177 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9179 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9184 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9185 || inst
.instruction
== T_MNEM_add
)
9188 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9192 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9194 /* Thumb-1 cores (except v6-M) require at least one high
9195 register in a narrow non flag setting add. */
9196 if (Rd
> 7 || Rn
> 7
9197 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9198 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9205 inst
.instruction
= T_OPCODE_ADD_HI
;
9206 inst
.instruction
|= (Rd
& 8) << 4;
9207 inst
.instruction
|= (Rd
& 7);
9208 inst
.instruction
|= Rn
<< 3;
9214 constraint (Rd
== REG_PC
, BAD_PC
);
9215 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9216 constraint (Rs
== REG_PC
, BAD_PC
);
9217 reject_bad_reg (Rn
);
9219 /* If we get here, it can't be done in 16 bits. */
9220 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9221 _("shift must be constant"));
9222 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9223 inst
.instruction
|= Rd
<< 8;
9224 inst
.instruction
|= Rs
<< 16;
9225 encode_thumb32_shifted_operand (2);
9230 constraint (inst
.instruction
== T_MNEM_adds
9231 || inst
.instruction
== T_MNEM_subs
,
9234 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9236 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9237 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9240 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9242 inst
.instruction
|= (Rd
<< 4) | Rs
;
9243 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9247 Rn
= inst
.operands
[2].reg
;
9248 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9250 /* We now have Rd, Rs, and Rn set to registers. */
9251 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9253 /* Can't do this for SUB. */
9254 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9255 inst
.instruction
= T_OPCODE_ADD_HI
;
9256 inst
.instruction
|= (Rd
& 8) << 4;
9257 inst
.instruction
|= (Rd
& 7);
9259 inst
.instruction
|= Rn
<< 3;
9261 inst
.instruction
|= Rs
<< 3;
9263 constraint (1, _("dest must overlap one source register"));
9267 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9268 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9269 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9279 Rd
= inst
.operands
[0].reg
;
9280 reject_bad_reg (Rd
);
9282 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9284 /* Defer to section relaxation. */
9285 inst
.relax
= inst
.instruction
;
9286 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9287 inst
.instruction
|= Rd
<< 4;
9289 else if (unified_syntax
&& inst
.size_req
!= 2)
9291 /* Generate a 32-bit opcode. */
9292 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9293 inst
.instruction
|= Rd
<< 8;
9294 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9295 inst
.reloc
.pc_rel
= 1;
9299 /* Generate a 16-bit opcode. */
9300 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9301 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9302 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9303 inst
.reloc
.pc_rel
= 1;
9305 inst
.instruction
|= Rd
<< 4;
9309 /* Arithmetic instructions for which there is just one 16-bit
9310 instruction encoding, and it allows only two low registers.
9311 For maximal compatibility with ARM syntax, we allow three register
9312 operands even when Thumb-32 instructions are not available, as long
9313 as the first two are identical. For instance, both "sbc r0,r1" and
9314 "sbc r0,r0,r1" are allowed. */
9320 Rd
= inst
.operands
[0].reg
;
9321 Rs
= (inst
.operands
[1].present
9322 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9323 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9324 Rn
= inst
.operands
[2].reg
;
9326 reject_bad_reg (Rd
);
9327 reject_bad_reg (Rs
);
9328 if (inst
.operands
[2].isreg
)
9329 reject_bad_reg (Rn
);
9333 if (!inst
.operands
[2].isreg
)
9335 /* For an immediate, we always generate a 32-bit opcode;
9336 section relaxation will shrink it later if possible. */
9337 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9338 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9339 inst
.instruction
|= Rd
<< 8;
9340 inst
.instruction
|= Rs
<< 16;
9341 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9347 /* See if we can do this with a 16-bit instruction. */
9348 if (THUMB_SETS_FLAGS (inst
.instruction
))
9349 narrow
= !in_it_block ();
9351 narrow
= in_it_block ();
9353 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9355 if (inst
.operands
[2].shifted
)
9357 if (inst
.size_req
== 4)
9363 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9364 inst
.instruction
|= Rd
;
9365 inst
.instruction
|= Rn
<< 3;
9369 /* If we get here, it can't be done in 16 bits. */
9370 constraint (inst
.operands
[2].shifted
9371 && inst
.operands
[2].immisreg
,
9372 _("shift must be constant"));
9373 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9374 inst
.instruction
|= Rd
<< 8;
9375 inst
.instruction
|= Rs
<< 16;
9376 encode_thumb32_shifted_operand (2);
9381 /* On its face this is a lie - the instruction does set the
9382 flags. However, the only supported mnemonic in this mode
9384 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9386 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9387 _("unshifted register required"));
9388 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9389 constraint (Rd
!= Rs
,
9390 _("dest and source1 must be the same register"));
9392 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9393 inst
.instruction
|= Rd
;
9394 inst
.instruction
|= Rn
<< 3;
9398 /* Similarly, but for instructions where the arithmetic operation is
9399 commutative, so we can allow either of them to be different from
9400 the destination operand in a 16-bit instruction. For instance, all
9401 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9408 Rd
= inst
.operands
[0].reg
;
9409 Rs
= (inst
.operands
[1].present
9410 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9411 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9412 Rn
= inst
.operands
[2].reg
;
9414 reject_bad_reg (Rd
);
9415 reject_bad_reg (Rs
);
9416 if (inst
.operands
[2].isreg
)
9417 reject_bad_reg (Rn
);
9421 if (!inst
.operands
[2].isreg
)
9423 /* For an immediate, we always generate a 32-bit opcode;
9424 section relaxation will shrink it later if possible. */
9425 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9426 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9427 inst
.instruction
|= Rd
<< 8;
9428 inst
.instruction
|= Rs
<< 16;
9429 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9435 /* See if we can do this with a 16-bit instruction. */
9436 if (THUMB_SETS_FLAGS (inst
.instruction
))
9437 narrow
= !in_it_block ();
9439 narrow
= in_it_block ();
9441 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9443 if (inst
.operands
[2].shifted
)
9445 if (inst
.size_req
== 4)
9452 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9453 inst
.instruction
|= Rd
;
9454 inst
.instruction
|= Rn
<< 3;
9459 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9460 inst
.instruction
|= Rd
;
9461 inst
.instruction
|= Rs
<< 3;
9466 /* If we get here, it can't be done in 16 bits. */
9467 constraint (inst
.operands
[2].shifted
9468 && inst
.operands
[2].immisreg
,
9469 _("shift must be constant"));
9470 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9471 inst
.instruction
|= Rd
<< 8;
9472 inst
.instruction
|= Rs
<< 16;
9473 encode_thumb32_shifted_operand (2);
9478 /* On its face this is a lie - the instruction does set the
9479 flags. However, the only supported mnemonic in this mode
9481 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9483 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9484 _("unshifted register required"));
9485 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9487 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9488 inst
.instruction
|= Rd
;
9491 inst
.instruction
|= Rn
<< 3;
9493 inst
.instruction
|= Rs
<< 3;
9495 constraint (1, _("dest must overlap one source register"));
9502 if (inst
.operands
[0].present
)
9504 constraint ((inst
.instruction
& 0xf0) != 0x40
9505 && inst
.operands
[0].imm
> 0xf
9506 && inst
.operands
[0].imm
< 0x0,
9507 _("bad barrier type"));
9508 inst
.instruction
|= inst
.operands
[0].imm
;
9511 inst
.instruction
|= 0xf;
9518 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9519 constraint (msb
> 32, _("bit-field extends past end of register"));
9520 /* The instruction encoding stores the LSB and MSB,
9521 not the LSB and width. */
9522 Rd
= inst
.operands
[0].reg
;
9523 reject_bad_reg (Rd
);
9524 inst
.instruction
|= Rd
<< 8;
9525 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9526 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9527 inst
.instruction
|= msb
- 1;
9536 Rd
= inst
.operands
[0].reg
;
9537 reject_bad_reg (Rd
);
9539 /* #0 in second position is alternative syntax for bfc, which is
9540 the same instruction but with REG_PC in the Rm field. */
9541 if (!inst
.operands
[1].isreg
)
9545 Rn
= inst
.operands
[1].reg
;
9546 reject_bad_reg (Rn
);
9549 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9550 constraint (msb
> 32, _("bit-field extends past end of register"));
9551 /* The instruction encoding stores the LSB and MSB,
9552 not the LSB and width. */
9553 inst
.instruction
|= Rd
<< 8;
9554 inst
.instruction
|= Rn
<< 16;
9555 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9556 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9557 inst
.instruction
|= msb
- 1;
9565 Rd
= inst
.operands
[0].reg
;
9566 Rn
= inst
.operands
[1].reg
;
9568 reject_bad_reg (Rd
);
9569 reject_bad_reg (Rn
);
9571 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9572 _("bit-field extends past end of register"));
9573 inst
.instruction
|= Rd
<< 8;
9574 inst
.instruction
|= Rn
<< 16;
9575 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9576 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9577 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9580 /* ARM V5 Thumb BLX (argument parse)
9581 BLX <target_addr> which is BLX(1)
9582 BLX <Rm> which is BLX(2)
9583 Unfortunately, there are two different opcodes for this mnemonic.
9584 So, the insns[].value is not used, and the code here zaps values
9585 into inst.instruction.
9587 ??? How to take advantage of the additional two bits of displacement
9588 available in Thumb32 mode? Need new relocation? */
9593 set_it_insn_type_last ();
9595 if (inst
.operands
[0].isreg
)
9597 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9598 /* We have a register, so this is BLX(2). */
9599 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9603 /* No register. This must be BLX(1). */
9604 inst
.instruction
= 0xf000e800;
9605 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9606 inst
.reloc
.pc_rel
= 1;
9617 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9621 /* Conditional branches inside IT blocks are encoded as unconditional
9628 if (cond
!= COND_ALWAYS
)
9629 opcode
= T_MNEM_bcond
;
9631 opcode
= inst
.instruction
;
9633 if (unified_syntax
&& inst
.size_req
== 4)
9635 inst
.instruction
= THUMB_OP32(opcode
);
9636 if (cond
== COND_ALWAYS
)
9637 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9640 gas_assert (cond
!= 0xF);
9641 inst
.instruction
|= cond
<< 22;
9642 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9647 inst
.instruction
= THUMB_OP16(opcode
);
9648 if (cond
== COND_ALWAYS
)
9649 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9652 inst
.instruction
|= cond
<< 8;
9653 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9655 /* Allow section relaxation. */
9656 if (unified_syntax
&& inst
.size_req
!= 2)
9657 inst
.relax
= opcode
;
9660 inst
.reloc
.pc_rel
= 1;
9666 constraint (inst
.cond
!= COND_ALWAYS
,
9667 _("instruction is always unconditional"));
9668 if (inst
.operands
[0].present
)
9670 constraint (inst
.operands
[0].imm
> 255,
9671 _("immediate value out of range"));
9672 inst
.instruction
|= inst
.operands
[0].imm
;
9673 set_it_insn_type (NEUTRAL_IT_INSN
);
9678 do_t_branch23 (void)
9680 set_it_insn_type_last ();
9681 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9682 inst
.reloc
.pc_rel
= 1;
9684 #if defined(OBJ_COFF)
9685 /* If the destination of the branch is a defined symbol which does not have
9686 the THUMB_FUNC attribute, then we must be calling a function which has
9687 the (interfacearm) attribute. We look for the Thumb entry point to that
9688 function and change the branch to refer to that function instead. */
9689 if ( inst
.reloc
.exp
.X_op
== O_symbol
9690 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9691 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9692 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9693 inst
.reloc
.exp
.X_add_symbol
=
9694 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9701 set_it_insn_type_last ();
9702 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9703 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9704 should cause the alignment to be checked once it is known. This is
9705 because BX PC only works if the instruction is word aligned. */
9713 set_it_insn_type_last ();
9714 Rm
= inst
.operands
[0].reg
;
9715 reject_bad_reg (Rm
);
9716 inst
.instruction
|= Rm
<< 16;
9725 Rd
= inst
.operands
[0].reg
;
9726 Rm
= inst
.operands
[1].reg
;
9728 reject_bad_reg (Rd
);
9729 reject_bad_reg (Rm
);
9731 inst
.instruction
|= Rd
<< 8;
9732 inst
.instruction
|= Rm
<< 16;
9733 inst
.instruction
|= Rm
;
9739 set_it_insn_type (OUTSIDE_IT_INSN
);
9740 inst
.instruction
|= inst
.operands
[0].imm
;
9746 set_it_insn_type (OUTSIDE_IT_INSN
);
9748 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9749 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9751 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9752 inst
.instruction
= 0xf3af8000;
9753 inst
.instruction
|= imod
<< 9;
9754 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9755 if (inst
.operands
[1].present
)
9756 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9760 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9761 && (inst
.operands
[0].imm
& 4),
9762 _("selected processor does not support 'A' form "
9763 "of this instruction"));
9764 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9765 _("Thumb does not support the 2-argument "
9766 "form of this instruction"));
9767 inst
.instruction
|= inst
.operands
[0].imm
;
9771 /* THUMB CPY instruction (argument parse). */
9776 if (inst
.size_req
== 4)
9778 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9779 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9780 inst
.instruction
|= inst
.operands
[1].reg
;
9784 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9785 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9786 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9793 set_it_insn_type (OUTSIDE_IT_INSN
);
9794 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9795 inst
.instruction
|= inst
.operands
[0].reg
;
9796 inst
.reloc
.pc_rel
= 1;
9797 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9803 inst
.instruction
|= inst
.operands
[0].imm
;
9809 unsigned Rd
, Rn
, Rm
;
9811 Rd
= inst
.operands
[0].reg
;
9812 Rn
= (inst
.operands
[1].present
9813 ? inst
.operands
[1].reg
: Rd
);
9814 Rm
= inst
.operands
[2].reg
;
9816 reject_bad_reg (Rd
);
9817 reject_bad_reg (Rn
);
9818 reject_bad_reg (Rm
);
9820 inst
.instruction
|= Rd
<< 8;
9821 inst
.instruction
|= Rn
<< 16;
9822 inst
.instruction
|= Rm
;
9828 if (unified_syntax
&& inst
.size_req
== 4)
9829 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9831 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9837 unsigned int cond
= inst
.operands
[0].imm
;
9839 set_it_insn_type (IT_INSN
);
9840 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9843 /* If the condition is a negative condition, invert the mask. */
9844 if ((cond
& 0x1) == 0x0)
9846 unsigned int mask
= inst
.instruction
& 0x000f;
9848 if ((mask
& 0x7) == 0)
9849 /* no conversion needed */;
9850 else if ((mask
& 0x3) == 0)
9852 else if ((mask
& 0x1) == 0)
9857 inst
.instruction
&= 0xfff0;
9858 inst
.instruction
|= mask
;
9861 inst
.instruction
|= cond
<< 4;
9864 /* Helper function used for both push/pop and ldm/stm. */
9866 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9870 load
= (inst
.instruction
& (1 << 20)) != 0;
9872 if (mask
& (1 << 13))
9873 inst
.error
= _("SP not allowed in register list");
9875 if ((mask
& (1 << base
)) != 0
9877 inst
.error
= _("having the base register in the register list when "
9878 "using write back is UNPREDICTABLE");
9882 if (mask
& (1 << 15))
9884 if (mask
& (1 << 14))
9885 inst
.error
= _("LR and PC should not both be in register list");
9887 set_it_insn_type_last ();
9892 if (mask
& (1 << 15))
9893 inst
.error
= _("PC not allowed in register list");
9896 if ((mask
& (mask
- 1)) == 0)
9898 /* Single register transfers implemented as str/ldr. */
9901 if (inst
.instruction
& (1 << 23))
9902 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9904 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9908 if (inst
.instruction
& (1 << 23))
9909 inst
.instruction
= 0x00800000; /* ia -> [base] */
9911 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9914 inst
.instruction
|= 0xf8400000;
9916 inst
.instruction
|= 0x00100000;
9918 mask
= ffs (mask
) - 1;
9922 inst
.instruction
|= WRITE_BACK
;
9924 inst
.instruction
|= mask
;
9925 inst
.instruction
|= base
<< 16;
9931 /* This really doesn't seem worth it. */
9932 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9933 _("expression too complex"));
9934 constraint (inst
.operands
[1].writeback
,
9935 _("Thumb load/store multiple does not support {reglist}^"));
9943 /* See if we can use a 16-bit instruction. */
9944 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9945 && inst
.size_req
!= 4
9946 && !(inst
.operands
[1].imm
& ~0xff))
9948 mask
= 1 << inst
.operands
[0].reg
;
9950 if (inst
.operands
[0].reg
<= 7)
9952 if (inst
.instruction
== T_MNEM_stmia
9953 ? inst
.operands
[0].writeback
9954 : (inst
.operands
[0].writeback
9955 == !(inst
.operands
[1].imm
& mask
)))
9957 if (inst
.instruction
== T_MNEM_stmia
9958 && (inst
.operands
[1].imm
& mask
)
9959 && (inst
.operands
[1].imm
& (mask
- 1)))
9960 as_warn (_("value stored for r%d is UNKNOWN"),
9961 inst
.operands
[0].reg
);
9963 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9964 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9965 inst
.instruction
|= inst
.operands
[1].imm
;
9968 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
9970 /* This means 1 register in reg list one of 3 situations:
9971 1. Instruction is stmia, but without writeback.
9972 2. lmdia without writeback, but with Rn not in
9974 3. ldmia with writeback, but with Rn in reglist.
9975 Case 3 is UNPREDICTABLE behaviour, so we handle
9976 case 1 and 2 which can be converted into a 16-bit
9977 str or ldr. The SP cases are handled below. */
9978 unsigned long opcode
;
9979 /* First, record an error for Case 3. */
9980 if (inst
.operands
[1].imm
& mask
9981 && inst
.operands
[0].writeback
)
9983 _("having the base register in the register list when "
9984 "using write back is UNPREDICTABLE");
9986 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
9988 inst
.instruction
= THUMB_OP16 (opcode
);
9989 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9990 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
9994 else if (inst
.operands
[0] .reg
== REG_SP
)
9996 if (inst
.operands
[0].writeback
)
9999 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10000 ? T_MNEM_push
: T_MNEM_pop
);
10001 inst
.instruction
|= inst
.operands
[1].imm
;
10004 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10007 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10008 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10009 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10017 if (inst
.instruction
< 0xffff)
10018 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10020 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10021 inst
.operands
[0].writeback
);
10026 constraint (inst
.operands
[0].reg
> 7
10027 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10028 constraint (inst
.instruction
!= T_MNEM_ldmia
10029 && inst
.instruction
!= T_MNEM_stmia
,
10030 _("Thumb-2 instruction only valid in unified syntax"));
10031 if (inst
.instruction
== T_MNEM_stmia
)
10033 if (!inst
.operands
[0].writeback
)
10034 as_warn (_("this instruction will write back the base register"));
10035 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10036 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10037 as_warn (_("value stored for r%d is UNKNOWN"),
10038 inst
.operands
[0].reg
);
10042 if (!inst
.operands
[0].writeback
10043 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10044 as_warn (_("this instruction will write back the base register"));
10045 else if (inst
.operands
[0].writeback
10046 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10047 as_warn (_("this instruction will not write back the base register"));
10050 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10051 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10052 inst
.instruction
|= inst
.operands
[1].imm
;
10059 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10060 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10061 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10062 || inst
.operands
[1].negative
,
10065 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10067 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10068 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10069 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10075 if (!inst
.operands
[1].present
)
10077 constraint (inst
.operands
[0].reg
== REG_LR
,
10078 _("r14 not allowed as first register "
10079 "when second register is omitted"));
10080 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10082 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10085 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10086 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10087 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10093 unsigned long opcode
;
10096 if (inst
.operands
[0].isreg
10097 && !inst
.operands
[0].preind
10098 && inst
.operands
[0].reg
== REG_PC
)
10099 set_it_insn_type_last ();
10101 opcode
= inst
.instruction
;
10102 if (unified_syntax
)
10104 if (!inst
.operands
[1].isreg
)
10106 if (opcode
<= 0xffff)
10107 inst
.instruction
= THUMB_OP32 (opcode
);
10108 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10111 if (inst
.operands
[1].isreg
10112 && !inst
.operands
[1].writeback
10113 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10114 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10115 && opcode
<= 0xffff
10116 && inst
.size_req
!= 4)
10118 /* Insn may have a 16-bit form. */
10119 Rn
= inst
.operands
[1].reg
;
10120 if (inst
.operands
[1].immisreg
)
10122 inst
.instruction
= THUMB_OP16 (opcode
);
10124 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10126 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10127 reject_bad_reg (inst
.operands
[1].imm
);
10129 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10130 && opcode
!= T_MNEM_ldrsb
)
10131 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10132 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10139 if (inst
.reloc
.pc_rel
)
10140 opcode
= T_MNEM_ldr_pc2
;
10142 opcode
= T_MNEM_ldr_pc
;
10146 if (opcode
== T_MNEM_ldr
)
10147 opcode
= T_MNEM_ldr_sp
;
10149 opcode
= T_MNEM_str_sp
;
10151 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10155 inst
.instruction
= inst
.operands
[0].reg
;
10156 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10158 inst
.instruction
|= THUMB_OP16 (opcode
);
10159 if (inst
.size_req
== 2)
10160 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10162 inst
.relax
= opcode
;
10166 /* Definitely a 32-bit variant. */
10168 /* Do some validations regarding addressing modes. */
10169 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10170 && opcode
!= T_MNEM_str
)
10171 reject_bad_reg (inst
.operands
[1].imm
);
10173 inst
.instruction
= THUMB_OP32 (opcode
);
10174 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10175 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10179 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10181 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10183 /* Only [Rn,Rm] is acceptable. */
10184 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10185 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10186 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10187 || inst
.operands
[1].negative
,
10188 _("Thumb does not support this addressing mode"));
10189 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10193 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10194 if (!inst
.operands
[1].isreg
)
10195 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10198 constraint (!inst
.operands
[1].preind
10199 || inst
.operands
[1].shifted
10200 || inst
.operands
[1].writeback
,
10201 _("Thumb does not support this addressing mode"));
10202 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10204 constraint (inst
.instruction
& 0x0600,
10205 _("byte or halfword not valid for base register"));
10206 constraint (inst
.operands
[1].reg
== REG_PC
10207 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10208 _("r15 based store not allowed"));
10209 constraint (inst
.operands
[1].immisreg
,
10210 _("invalid base register for register offset"));
10212 if (inst
.operands
[1].reg
== REG_PC
)
10213 inst
.instruction
= T_OPCODE_LDR_PC
;
10214 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10215 inst
.instruction
= T_OPCODE_LDR_SP
;
10217 inst
.instruction
= T_OPCODE_STR_SP
;
10219 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10220 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10224 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10225 if (!inst
.operands
[1].immisreg
)
10227 /* Immediate offset. */
10228 inst
.instruction
|= inst
.operands
[0].reg
;
10229 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10230 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10234 /* Register offset. */
10235 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10236 constraint (inst
.operands
[1].negative
,
10237 _("Thumb does not support this addressing mode"));
10240 switch (inst
.instruction
)
10242 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10243 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10244 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10245 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10246 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10247 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10248 case 0x5600 /* ldrsb */:
10249 case 0x5e00 /* ldrsh */: break;
10253 inst
.instruction
|= inst
.operands
[0].reg
;
10254 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10255 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10261 if (!inst
.operands
[1].present
)
10263 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10264 constraint (inst
.operands
[0].reg
== REG_LR
,
10265 _("r14 not allowed here"));
10267 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10268 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10269 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10275 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10276 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10282 unsigned Rd
, Rn
, Rm
, Ra
;
10284 Rd
= inst
.operands
[0].reg
;
10285 Rn
= inst
.operands
[1].reg
;
10286 Rm
= inst
.operands
[2].reg
;
10287 Ra
= inst
.operands
[3].reg
;
10289 reject_bad_reg (Rd
);
10290 reject_bad_reg (Rn
);
10291 reject_bad_reg (Rm
);
10292 reject_bad_reg (Ra
);
10294 inst
.instruction
|= Rd
<< 8;
10295 inst
.instruction
|= Rn
<< 16;
10296 inst
.instruction
|= Rm
;
10297 inst
.instruction
|= Ra
<< 12;
10303 unsigned RdLo
, RdHi
, Rn
, Rm
;
10305 RdLo
= inst
.operands
[0].reg
;
10306 RdHi
= inst
.operands
[1].reg
;
10307 Rn
= inst
.operands
[2].reg
;
10308 Rm
= inst
.operands
[3].reg
;
10310 reject_bad_reg (RdLo
);
10311 reject_bad_reg (RdHi
);
10312 reject_bad_reg (Rn
);
10313 reject_bad_reg (Rm
);
10315 inst
.instruction
|= RdLo
<< 12;
10316 inst
.instruction
|= RdHi
<< 8;
10317 inst
.instruction
|= Rn
<< 16;
10318 inst
.instruction
|= Rm
;
10322 do_t_mov_cmp (void)
10326 Rn
= inst
.operands
[0].reg
;
10327 Rm
= inst
.operands
[1].reg
;
10330 set_it_insn_type_last ();
10332 if (unified_syntax
)
10334 int r0off
= (inst
.instruction
== T_MNEM_mov
10335 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10336 unsigned long opcode
;
10337 bfd_boolean narrow
;
10338 bfd_boolean low_regs
;
10340 low_regs
= (Rn
<= 7 && Rm
<= 7);
10341 opcode
= inst
.instruction
;
10342 if (in_it_block ())
10343 narrow
= opcode
!= T_MNEM_movs
;
10345 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10346 if (inst
.size_req
== 4
10347 || inst
.operands
[1].shifted
)
10350 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10351 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10352 && !inst
.operands
[1].shifted
10356 inst
.instruction
= T2_SUBS_PC_LR
;
10360 if (opcode
== T_MNEM_cmp
)
10362 constraint (Rn
== REG_PC
, BAD_PC
);
10365 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10367 warn_deprecated_sp (Rm
);
10368 /* R15 was documented as a valid choice for Rm in ARMv6,
10369 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10370 tools reject R15, so we do too. */
10371 constraint (Rm
== REG_PC
, BAD_PC
);
10374 reject_bad_reg (Rm
);
10376 else if (opcode
== T_MNEM_mov
10377 || opcode
== T_MNEM_movs
)
10379 if (inst
.operands
[1].isreg
)
10381 if (opcode
== T_MNEM_movs
)
10383 reject_bad_reg (Rn
);
10384 reject_bad_reg (Rm
);
10388 /* This is mov.n. */
10389 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10390 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10392 as_warn (_("Use of r%u as a source register is "
10393 "deprecated when r%u is the destination "
10394 "register."), Rm
, Rn
);
10399 /* This is mov.w. */
10400 constraint (Rn
== REG_PC
, BAD_PC
);
10401 constraint (Rm
== REG_PC
, BAD_PC
);
10402 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10406 reject_bad_reg (Rn
);
10409 if (!inst
.operands
[1].isreg
)
10411 /* Immediate operand. */
10412 if (!in_it_block () && opcode
== T_MNEM_mov
)
10414 if (low_regs
&& narrow
)
10416 inst
.instruction
= THUMB_OP16 (opcode
);
10417 inst
.instruction
|= Rn
<< 8;
10418 if (inst
.size_req
== 2)
10419 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10421 inst
.relax
= opcode
;
10425 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10426 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10427 inst
.instruction
|= Rn
<< r0off
;
10428 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10431 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10432 && (inst
.instruction
== T_MNEM_mov
10433 || inst
.instruction
== T_MNEM_movs
))
10435 /* Register shifts are encoded as separate shift instructions. */
10436 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10438 if (in_it_block ())
10443 if (inst
.size_req
== 4)
10446 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10452 switch (inst
.operands
[1].shift_kind
)
10455 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10458 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10461 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10464 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10470 inst
.instruction
= opcode
;
10473 inst
.instruction
|= Rn
;
10474 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10479 inst
.instruction
|= CONDS_BIT
;
10481 inst
.instruction
|= Rn
<< 8;
10482 inst
.instruction
|= Rm
<< 16;
10483 inst
.instruction
|= inst
.operands
[1].imm
;
10488 /* Some mov with immediate shift have narrow variants.
10489 Register shifts are handled above. */
10490 if (low_regs
&& inst
.operands
[1].shifted
10491 && (inst
.instruction
== T_MNEM_mov
10492 || inst
.instruction
== T_MNEM_movs
))
10494 if (in_it_block ())
10495 narrow
= (inst
.instruction
== T_MNEM_mov
);
10497 narrow
= (inst
.instruction
== T_MNEM_movs
);
10502 switch (inst
.operands
[1].shift_kind
)
10504 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10505 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10506 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10507 default: narrow
= FALSE
; break;
10513 inst
.instruction
|= Rn
;
10514 inst
.instruction
|= Rm
<< 3;
10515 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10519 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10520 inst
.instruction
|= Rn
<< r0off
;
10521 encode_thumb32_shifted_operand (1);
10525 switch (inst
.instruction
)
10528 inst
.instruction
= T_OPCODE_MOV_HR
;
10529 inst
.instruction
|= (Rn
& 0x8) << 4;
10530 inst
.instruction
|= (Rn
& 0x7);
10531 inst
.instruction
|= Rm
<< 3;
10535 /* We know we have low registers at this point.
10536 Generate LSLS Rd, Rs, #0. */
10537 inst
.instruction
= T_OPCODE_LSL_I
;
10538 inst
.instruction
|= Rn
;
10539 inst
.instruction
|= Rm
<< 3;
10545 inst
.instruction
= T_OPCODE_CMP_LR
;
10546 inst
.instruction
|= Rn
;
10547 inst
.instruction
|= Rm
<< 3;
10551 inst
.instruction
= T_OPCODE_CMP_HR
;
10552 inst
.instruction
|= (Rn
& 0x8) << 4;
10553 inst
.instruction
|= (Rn
& 0x7);
10554 inst
.instruction
|= Rm
<< 3;
10561 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10563 /* PR 10443: Do not silently ignore shifted operands. */
10564 constraint (inst
.operands
[1].shifted
,
10565 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10567 if (inst
.operands
[1].isreg
)
10569 if (Rn
< 8 && Rm
< 8)
10571 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10572 since a MOV instruction produces unpredictable results. */
10573 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10574 inst
.instruction
= T_OPCODE_ADD_I3
;
10576 inst
.instruction
= T_OPCODE_CMP_LR
;
10578 inst
.instruction
|= Rn
;
10579 inst
.instruction
|= Rm
<< 3;
10583 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10584 inst
.instruction
= T_OPCODE_MOV_HR
;
10586 inst
.instruction
= T_OPCODE_CMP_HR
;
10592 constraint (Rn
> 7,
10593 _("only lo regs allowed with immediate"));
10594 inst
.instruction
|= Rn
<< 8;
10595 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10606 top
= (inst
.instruction
& 0x00800000) != 0;
10607 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10609 constraint (top
, _(":lower16: not allowed this instruction"));
10610 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10612 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10614 constraint (!top
, _(":upper16: not allowed this instruction"));
10615 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10618 Rd
= inst
.operands
[0].reg
;
10619 reject_bad_reg (Rd
);
10621 inst
.instruction
|= Rd
<< 8;
10622 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10624 imm
= inst
.reloc
.exp
.X_add_number
;
10625 inst
.instruction
|= (imm
& 0xf000) << 4;
10626 inst
.instruction
|= (imm
& 0x0800) << 15;
10627 inst
.instruction
|= (imm
& 0x0700) << 4;
10628 inst
.instruction
|= (imm
& 0x00ff);
10633 do_t_mvn_tst (void)
10637 Rn
= inst
.operands
[0].reg
;
10638 Rm
= inst
.operands
[1].reg
;
10640 if (inst
.instruction
== T_MNEM_cmp
10641 || inst
.instruction
== T_MNEM_cmn
)
10642 constraint (Rn
== REG_PC
, BAD_PC
);
10644 reject_bad_reg (Rn
);
10645 reject_bad_reg (Rm
);
10647 if (unified_syntax
)
10649 int r0off
= (inst
.instruction
== T_MNEM_mvn
10650 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10651 bfd_boolean narrow
;
10653 if (inst
.size_req
== 4
10654 || inst
.instruction
> 0xffff
10655 || inst
.operands
[1].shifted
10656 || Rn
> 7 || Rm
> 7)
10658 else if (inst
.instruction
== T_MNEM_cmn
)
10660 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10661 narrow
= !in_it_block ();
10663 narrow
= in_it_block ();
10665 if (!inst
.operands
[1].isreg
)
10667 /* For an immediate, we always generate a 32-bit opcode;
10668 section relaxation will shrink it later if possible. */
10669 if (inst
.instruction
< 0xffff)
10670 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10671 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10672 inst
.instruction
|= Rn
<< r0off
;
10673 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10677 /* See if we can do this with a 16-bit instruction. */
10680 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10681 inst
.instruction
|= Rn
;
10682 inst
.instruction
|= Rm
<< 3;
10686 constraint (inst
.operands
[1].shifted
10687 && inst
.operands
[1].immisreg
,
10688 _("shift must be constant"));
10689 if (inst
.instruction
< 0xffff)
10690 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10691 inst
.instruction
|= Rn
<< r0off
;
10692 encode_thumb32_shifted_operand (1);
10698 constraint (inst
.instruction
> 0xffff
10699 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10700 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10701 _("unshifted register required"));
10702 constraint (Rn
> 7 || Rm
> 7,
10705 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10706 inst
.instruction
|= Rn
;
10707 inst
.instruction
|= Rm
<< 3;
10717 if (do_vfp_nsyn_mrs () == SUCCESS
)
10720 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10723 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10724 _("selected processor does not support "
10725 "requested special purpose register"));
10729 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10730 _("selected processor does not support "
10731 "requested special purpose register"));
10732 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10733 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10734 _("'CPSR' or 'SPSR' expected"));
10737 Rd
= inst
.operands
[0].reg
;
10738 reject_bad_reg (Rd
);
10740 inst
.instruction
|= Rd
<< 8;
10741 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10742 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10751 if (do_vfp_nsyn_msr () == SUCCESS
)
10754 constraint (!inst
.operands
[1].isreg
,
10755 _("Thumb encoding does not support an immediate here"));
10756 flags
= inst
.operands
[0].imm
;
10759 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10760 _("selected processor does not support "
10761 "requested special purpose register"));
10765 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10766 _("selected processor does not support "
10767 "requested special purpose register"));
10771 Rn
= inst
.operands
[1].reg
;
10772 reject_bad_reg (Rn
);
10774 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10775 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10776 inst
.instruction
|= (flags
& 0xff);
10777 inst
.instruction
|= Rn
<< 16;
10783 bfd_boolean narrow
;
10784 unsigned Rd
, Rn
, Rm
;
10786 if (!inst
.operands
[2].present
)
10787 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10789 Rd
= inst
.operands
[0].reg
;
10790 Rn
= inst
.operands
[1].reg
;
10791 Rm
= inst
.operands
[2].reg
;
10793 if (unified_syntax
)
10795 if (inst
.size_req
== 4
10801 else if (inst
.instruction
== T_MNEM_muls
)
10802 narrow
= !in_it_block ();
10804 narrow
= in_it_block ();
10808 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10809 constraint (Rn
> 7 || Rm
> 7,
10816 /* 16-bit MULS/Conditional MUL. */
10817 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10818 inst
.instruction
|= Rd
;
10821 inst
.instruction
|= Rm
<< 3;
10823 inst
.instruction
|= Rn
<< 3;
10825 constraint (1, _("dest must overlap one source register"));
10829 constraint (inst
.instruction
!= T_MNEM_mul
,
10830 _("Thumb-2 MUL must not set flags"));
10832 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10833 inst
.instruction
|= Rd
<< 8;
10834 inst
.instruction
|= Rn
<< 16;
10835 inst
.instruction
|= Rm
<< 0;
10837 reject_bad_reg (Rd
);
10838 reject_bad_reg (Rn
);
10839 reject_bad_reg (Rm
);
10846 unsigned RdLo
, RdHi
, Rn
, Rm
;
10848 RdLo
= inst
.operands
[0].reg
;
10849 RdHi
= inst
.operands
[1].reg
;
10850 Rn
= inst
.operands
[2].reg
;
10851 Rm
= inst
.operands
[3].reg
;
10853 reject_bad_reg (RdLo
);
10854 reject_bad_reg (RdHi
);
10855 reject_bad_reg (Rn
);
10856 reject_bad_reg (Rm
);
10858 inst
.instruction
|= RdLo
<< 12;
10859 inst
.instruction
|= RdHi
<< 8;
10860 inst
.instruction
|= Rn
<< 16;
10861 inst
.instruction
|= Rm
;
10864 as_tsktsk (_("rdhi and rdlo must be different"));
10870 set_it_insn_type (NEUTRAL_IT_INSN
);
10872 if (unified_syntax
)
10874 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10876 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10877 inst
.instruction
|= inst
.operands
[0].imm
;
10881 /* PR9722: Check for Thumb2 availability before
10882 generating a thumb2 nop instruction. */
10883 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10885 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10886 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10889 inst
.instruction
= 0x46c0;
10894 constraint (inst
.operands
[0].present
,
10895 _("Thumb does not support NOP with hints"));
10896 inst
.instruction
= 0x46c0;
10903 if (unified_syntax
)
10905 bfd_boolean narrow
;
10907 if (THUMB_SETS_FLAGS (inst
.instruction
))
10908 narrow
= !in_it_block ();
10910 narrow
= in_it_block ();
10911 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10913 if (inst
.size_req
== 4)
10918 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10919 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10920 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10924 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10925 inst
.instruction
|= inst
.operands
[0].reg
;
10926 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10931 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10933 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10935 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10936 inst
.instruction
|= inst
.operands
[0].reg
;
10937 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10946 Rd
= inst
.operands
[0].reg
;
10947 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10949 reject_bad_reg (Rd
);
10950 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10951 reject_bad_reg (Rn
);
10953 inst
.instruction
|= Rd
<< 8;
10954 inst
.instruction
|= Rn
<< 16;
10956 if (!inst
.operands
[2].isreg
)
10958 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10959 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10965 Rm
= inst
.operands
[2].reg
;
10966 reject_bad_reg (Rm
);
10968 constraint (inst
.operands
[2].shifted
10969 && inst
.operands
[2].immisreg
,
10970 _("shift must be constant"));
10971 encode_thumb32_shifted_operand (2);
10978 unsigned Rd
, Rn
, Rm
;
10980 Rd
= inst
.operands
[0].reg
;
10981 Rn
= inst
.operands
[1].reg
;
10982 Rm
= inst
.operands
[2].reg
;
10984 reject_bad_reg (Rd
);
10985 reject_bad_reg (Rn
);
10986 reject_bad_reg (Rm
);
10988 inst
.instruction
|= Rd
<< 8;
10989 inst
.instruction
|= Rn
<< 16;
10990 inst
.instruction
|= Rm
;
10991 if (inst
.operands
[3].present
)
10993 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10994 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10995 _("expression too complex"));
10996 inst
.instruction
|= (val
& 0x1c) << 10;
10997 inst
.instruction
|= (val
& 0x03) << 6;
11004 if (!inst
.operands
[3].present
)
11008 inst
.instruction
&= ~0x00000020;
11010 /* PR 10168. Swap the Rm and Rn registers. */
11011 Rtmp
= inst
.operands
[1].reg
;
11012 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11013 inst
.operands
[2].reg
= Rtmp
;
11021 if (inst
.operands
[0].immisreg
)
11022 reject_bad_reg (inst
.operands
[0].imm
);
11024 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11028 do_t_push_pop (void)
11032 constraint (inst
.operands
[0].writeback
,
11033 _("push/pop do not support {reglist}^"));
11034 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11035 _("expression too complex"));
11037 mask
= inst
.operands
[0].imm
;
11038 if ((mask
& ~0xff) == 0)
11039 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11040 else if ((inst
.instruction
== T_MNEM_push
11041 && (mask
& ~0xff) == 1 << REG_LR
)
11042 || (inst
.instruction
== T_MNEM_pop
11043 && (mask
& ~0xff) == 1 << REG_PC
))
11045 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11046 inst
.instruction
|= THUMB_PP_PC_LR
;
11047 inst
.instruction
|= mask
& 0xff;
11049 else if (unified_syntax
)
11051 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11052 encode_thumb2_ldmstm (13, mask
, TRUE
);
11056 inst
.error
= _("invalid register list to push/pop instruction");
11066 Rd
= inst
.operands
[0].reg
;
11067 Rm
= inst
.operands
[1].reg
;
11069 reject_bad_reg (Rd
);
11070 reject_bad_reg (Rm
);
11072 inst
.instruction
|= Rd
<< 8;
11073 inst
.instruction
|= Rm
<< 16;
11074 inst
.instruction
|= Rm
;
11082 Rd
= inst
.operands
[0].reg
;
11083 Rm
= inst
.operands
[1].reg
;
11085 reject_bad_reg (Rd
);
11086 reject_bad_reg (Rm
);
11088 if (Rd
<= 7 && Rm
<= 7
11089 && inst
.size_req
!= 4)
11091 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11092 inst
.instruction
|= Rd
;
11093 inst
.instruction
|= Rm
<< 3;
11095 else if (unified_syntax
)
11097 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11098 inst
.instruction
|= Rd
<< 8;
11099 inst
.instruction
|= Rm
<< 16;
11100 inst
.instruction
|= Rm
;
11103 inst
.error
= BAD_HIREG
;
11111 Rd
= inst
.operands
[0].reg
;
11112 Rm
= inst
.operands
[1].reg
;
11114 reject_bad_reg (Rd
);
11115 reject_bad_reg (Rm
);
11117 inst
.instruction
|= Rd
<< 8;
11118 inst
.instruction
|= Rm
;
11126 Rd
= inst
.operands
[0].reg
;
11127 Rs
= (inst
.operands
[1].present
11128 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11129 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11131 reject_bad_reg (Rd
);
11132 reject_bad_reg (Rs
);
11133 if (inst
.operands
[2].isreg
)
11134 reject_bad_reg (inst
.operands
[2].reg
);
11136 inst
.instruction
|= Rd
<< 8;
11137 inst
.instruction
|= Rs
<< 16;
11138 if (!inst
.operands
[2].isreg
)
11140 bfd_boolean narrow
;
11142 if ((inst
.instruction
& 0x00100000) != 0)
11143 narrow
= !in_it_block ();
11145 narrow
= in_it_block ();
11147 if (Rd
> 7 || Rs
> 7)
11150 if (inst
.size_req
== 4 || !unified_syntax
)
11153 if (inst
.reloc
.exp
.X_op
!= O_constant
11154 || inst
.reloc
.exp
.X_add_number
!= 0)
11157 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11158 relaxation, but it doesn't seem worth the hassle. */
11161 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11162 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11163 inst
.instruction
|= Rs
<< 3;
11164 inst
.instruction
|= Rd
;
11168 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11169 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11173 encode_thumb32_shifted_operand (2);
11179 set_it_insn_type (OUTSIDE_IT_INSN
);
11180 if (inst
.operands
[0].imm
)
11181 inst
.instruction
|= 0x8;
11187 if (!inst
.operands
[1].present
)
11188 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11190 if (unified_syntax
)
11192 bfd_boolean narrow
;
11195 switch (inst
.instruction
)
11198 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11200 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11202 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11204 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11208 if (THUMB_SETS_FLAGS (inst
.instruction
))
11209 narrow
= !in_it_block ();
11211 narrow
= in_it_block ();
11212 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11214 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11216 if (inst
.operands
[2].isreg
11217 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11218 || inst
.operands
[2].reg
> 7))
11220 if (inst
.size_req
== 4)
11223 reject_bad_reg (inst
.operands
[0].reg
);
11224 reject_bad_reg (inst
.operands
[1].reg
);
11228 if (inst
.operands
[2].isreg
)
11230 reject_bad_reg (inst
.operands
[2].reg
);
11231 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11232 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11233 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11234 inst
.instruction
|= inst
.operands
[2].reg
;
11238 inst
.operands
[1].shifted
= 1;
11239 inst
.operands
[1].shift_kind
= shift_kind
;
11240 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11241 ? T_MNEM_movs
: T_MNEM_mov
);
11242 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11243 encode_thumb32_shifted_operand (1);
11244 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11245 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11250 if (inst
.operands
[2].isreg
)
11252 switch (shift_kind
)
11254 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11255 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11256 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11257 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11261 inst
.instruction
|= inst
.operands
[0].reg
;
11262 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11266 switch (shift_kind
)
11268 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11269 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11270 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11273 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11274 inst
.instruction
|= inst
.operands
[0].reg
;
11275 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11281 constraint (inst
.operands
[0].reg
> 7
11282 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11283 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11285 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11287 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11288 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11289 _("source1 and dest must be same register"));
11291 switch (inst
.instruction
)
11293 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11294 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11295 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11296 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11300 inst
.instruction
|= inst
.operands
[0].reg
;
11301 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11305 switch (inst
.instruction
)
11307 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11308 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11309 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11310 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11313 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11314 inst
.instruction
|= inst
.operands
[0].reg
;
11315 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11323 unsigned Rd
, Rn
, Rm
;
11325 Rd
= inst
.operands
[0].reg
;
11326 Rn
= inst
.operands
[1].reg
;
11327 Rm
= inst
.operands
[2].reg
;
11329 reject_bad_reg (Rd
);
11330 reject_bad_reg (Rn
);
11331 reject_bad_reg (Rm
);
11333 inst
.instruction
|= Rd
<< 8;
11334 inst
.instruction
|= Rn
<< 16;
11335 inst
.instruction
|= Rm
;
11341 unsigned Rd
, Rn
, Rm
;
11343 Rd
= inst
.operands
[0].reg
;
11344 Rm
= inst
.operands
[1].reg
;
11345 Rn
= inst
.operands
[2].reg
;
11347 reject_bad_reg (Rd
);
11348 reject_bad_reg (Rn
);
11349 reject_bad_reg (Rm
);
11351 inst
.instruction
|= Rd
<< 8;
11352 inst
.instruction
|= Rn
<< 16;
11353 inst
.instruction
|= Rm
;
11359 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11360 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11361 _("SMC is not permitted on this architecture"));
11362 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11363 _("expression too complex"));
11364 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11365 inst
.instruction
|= (value
& 0xf000) >> 12;
11366 inst
.instruction
|= (value
& 0x0ff0);
11367 inst
.instruction
|= (value
& 0x000f) << 16;
11371 do_t_ssat_usat (int bias
)
11375 Rd
= inst
.operands
[0].reg
;
11376 Rn
= inst
.operands
[2].reg
;
11378 reject_bad_reg (Rd
);
11379 reject_bad_reg (Rn
);
11381 inst
.instruction
|= Rd
<< 8;
11382 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11383 inst
.instruction
|= Rn
<< 16;
11385 if (inst
.operands
[3].present
)
11387 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11389 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11391 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11392 _("expression too complex"));
11394 if (shift_amount
!= 0)
11396 constraint (shift_amount
> 31,
11397 _("shift expression is too large"));
11399 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11400 inst
.instruction
|= 0x00200000; /* sh bit. */
11402 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11403 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11411 do_t_ssat_usat (1);
11419 Rd
= inst
.operands
[0].reg
;
11420 Rn
= inst
.operands
[2].reg
;
11422 reject_bad_reg (Rd
);
11423 reject_bad_reg (Rn
);
11425 inst
.instruction
|= Rd
<< 8;
11426 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11427 inst
.instruction
|= Rn
<< 16;
11433 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11434 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11435 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11436 || inst
.operands
[2].negative
,
11439 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11441 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11442 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11443 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11444 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11450 if (!inst
.operands
[2].present
)
11451 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11453 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11454 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11455 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11458 inst
.instruction
|= inst
.operands
[0].reg
;
11459 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11460 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11461 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11467 unsigned Rd
, Rn
, Rm
;
11469 Rd
= inst
.operands
[0].reg
;
11470 Rn
= inst
.operands
[1].reg
;
11471 Rm
= inst
.operands
[2].reg
;
11473 reject_bad_reg (Rd
);
11474 reject_bad_reg (Rn
);
11475 reject_bad_reg (Rm
);
11477 inst
.instruction
|= Rd
<< 8;
11478 inst
.instruction
|= Rn
<< 16;
11479 inst
.instruction
|= Rm
;
11480 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11488 Rd
= inst
.operands
[0].reg
;
11489 Rm
= inst
.operands
[1].reg
;
11491 reject_bad_reg (Rd
);
11492 reject_bad_reg (Rm
);
11494 if (inst
.instruction
<= 0xffff
11495 && inst
.size_req
!= 4
11496 && Rd
<= 7 && Rm
<= 7
11497 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11499 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11500 inst
.instruction
|= Rd
;
11501 inst
.instruction
|= Rm
<< 3;
11503 else if (unified_syntax
)
11505 if (inst
.instruction
<= 0xffff)
11506 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11507 inst
.instruction
|= Rd
<< 8;
11508 inst
.instruction
|= Rm
;
11509 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11513 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11514 _("Thumb encoding does not support rotation"));
11515 constraint (1, BAD_HIREG
);
11522 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11531 half
= (inst
.instruction
& 0x10) != 0;
11532 set_it_insn_type_last ();
11533 constraint (inst
.operands
[0].immisreg
,
11534 _("instruction requires register index"));
11536 Rn
= inst
.operands
[0].reg
;
11537 Rm
= inst
.operands
[0].imm
;
11539 constraint (Rn
== REG_SP
, BAD_SP
);
11540 reject_bad_reg (Rm
);
11542 constraint (!half
&& inst
.operands
[0].shifted
,
11543 _("instruction does not allow shifted index"));
11544 inst
.instruction
|= (Rn
<< 16) | Rm
;
11550 do_t_ssat_usat (0);
11558 Rd
= inst
.operands
[0].reg
;
11559 Rn
= inst
.operands
[2].reg
;
11561 reject_bad_reg (Rd
);
11562 reject_bad_reg (Rn
);
11564 inst
.instruction
|= Rd
<< 8;
11565 inst
.instruction
|= inst
.operands
[1].imm
;
11566 inst
.instruction
|= Rn
<< 16;
11569 /* Neon instruction encoder helpers. */
11571 /* Encodings for the different types for various Neon opcodes. */
11573 /* An "invalid" code for the following tables. */
11576 struct neon_tab_entry
11579 unsigned float_or_poly
;
11580 unsigned scalar_or_imm
;
11583 /* Map overloaded Neon opcodes to their respective encodings. */
11584 #define NEON_ENC_TAB \
11585 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11586 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11587 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11588 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11589 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11590 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11591 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11592 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11593 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11594 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11595 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11596 /* Register variants of the following two instructions are encoded as
11597 vcge / vcgt with the operands reversed. */ \
11598 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11599 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11600 X(vfma, N_INV, 0x0000c10, N_INV), \
11601 X(vfms, N_INV, 0x0200c10, N_INV), \
11602 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11603 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11604 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11605 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11606 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11607 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11608 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11609 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11610 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11611 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11612 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11613 X(vshl, 0x0000400, N_INV, 0x0800510), \
11614 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11615 X(vand, 0x0000110, N_INV, 0x0800030), \
11616 X(vbic, 0x0100110, N_INV, 0x0800030), \
11617 X(veor, 0x1000110, N_INV, N_INV), \
11618 X(vorn, 0x0300110, N_INV, 0x0800010), \
11619 X(vorr, 0x0200110, N_INV, 0x0800010), \
11620 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11621 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11622 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11623 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11624 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11625 X(vst1, 0x0000000, 0x0800000, N_INV), \
11626 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11627 X(vst2, 0x0000100, 0x0800100, N_INV), \
11628 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11629 X(vst3, 0x0000200, 0x0800200, N_INV), \
11630 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11631 X(vst4, 0x0000300, 0x0800300, N_INV), \
11632 X(vmovn, 0x1b20200, N_INV, N_INV), \
11633 X(vtrn, 0x1b20080, N_INV, N_INV), \
11634 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11635 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11636 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11637 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11638 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11639 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11640 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11641 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11642 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11643 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11644 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11648 #define X(OPC,I,F,S) N_MNEM_##OPC
11653 static const struct neon_tab_entry neon_enc_tab
[] =
11655 #define X(OPC,I,F,S) { (I), (F), (S) }
11660 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11661 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11662 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11663 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11664 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11665 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11666 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11667 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11668 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11669 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11670 #define NEON_ENC_SINGLE_(X) \
11671 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11672 #define NEON_ENC_DOUBLE_(X) \
11673 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11675 #define NEON_ENCODE(type, inst) \
11678 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11679 inst.is_neon = 1; \
11683 #define check_neon_suffixes \
11686 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11688 as_bad (_("invalid neon suffix for non neon instruction")); \
11694 /* Define shapes for instruction operands. The following mnemonic characters
11695 are used in this table:
11697 F - VFP S<n> register
11698 D - Neon D<n> register
11699 Q - Neon Q<n> register
11703 L - D<n> register list
11705 This table is used to generate various data:
11706 - enumerations of the form NS_DDR to be used as arguments to
11708 - a table classifying shapes into single, double, quad, mixed.
11709 - a table used to drive neon_select_shape. */
11711 #define NEON_SHAPE_DEF \
11712 X(3, (D, D, D), DOUBLE), \
11713 X(3, (Q, Q, Q), QUAD), \
11714 X(3, (D, D, I), DOUBLE), \
11715 X(3, (Q, Q, I), QUAD), \
11716 X(3, (D, D, S), DOUBLE), \
11717 X(3, (Q, Q, S), QUAD), \
11718 X(2, (D, D), DOUBLE), \
11719 X(2, (Q, Q), QUAD), \
11720 X(2, (D, S), DOUBLE), \
11721 X(2, (Q, S), QUAD), \
11722 X(2, (D, R), DOUBLE), \
11723 X(2, (Q, R), QUAD), \
11724 X(2, (D, I), DOUBLE), \
11725 X(2, (Q, I), QUAD), \
11726 X(3, (D, L, D), DOUBLE), \
11727 X(2, (D, Q), MIXED), \
11728 X(2, (Q, D), MIXED), \
11729 X(3, (D, Q, I), MIXED), \
11730 X(3, (Q, D, I), MIXED), \
11731 X(3, (Q, D, D), MIXED), \
11732 X(3, (D, Q, Q), MIXED), \
11733 X(3, (Q, Q, D), MIXED), \
11734 X(3, (Q, D, S), MIXED), \
11735 X(3, (D, Q, S), MIXED), \
11736 X(4, (D, D, D, I), DOUBLE), \
11737 X(4, (Q, Q, Q, I), QUAD), \
11738 X(2, (F, F), SINGLE), \
11739 X(3, (F, F, F), SINGLE), \
11740 X(2, (F, I), SINGLE), \
11741 X(2, (F, D), MIXED), \
11742 X(2, (D, F), MIXED), \
11743 X(3, (F, F, I), MIXED), \
11744 X(4, (R, R, F, F), SINGLE), \
11745 X(4, (F, F, R, R), SINGLE), \
11746 X(3, (D, R, R), DOUBLE), \
11747 X(3, (R, R, D), DOUBLE), \
11748 X(2, (S, R), SINGLE), \
11749 X(2, (R, S), SINGLE), \
11750 X(2, (F, R), SINGLE), \
11751 X(2, (R, F), SINGLE)
11753 #define S2(A,B) NS_##A##B
11754 #define S3(A,B,C) NS_##A##B##C
11755 #define S4(A,B,C,D) NS_##A##B##C##D
11757 #define X(N, L, C) S##N L
11770 enum neon_shape_class
11778 #define X(N, L, C) SC_##C
11780 static enum neon_shape_class neon_shape_class
[] =
11798 /* Register widths of above. */
11799 static unsigned neon_shape_el_size
[] =
11810 struct neon_shape_info
11813 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11816 #define S2(A,B) { SE_##A, SE_##B }
11817 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11818 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11820 #define X(N, L, C) { N, S##N L }
11822 static struct neon_shape_info neon_shape_tab
[] =
11832 /* Bit masks used in type checking given instructions.
11833 'N_EQK' means the type must be the same as (or based on in some way) the key
11834 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11835 set, various other bits can be set as well in order to modify the meaning of
11836 the type constraint. */
11838 enum neon_type_mask
11861 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11862 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11863 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11864 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11865 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11866 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11867 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11868 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11869 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11870 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11872 N_MAX_NONSPECIAL
= N_F64
11875 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11877 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11878 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11879 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11880 #define N_SUF_32 (N_SU_32 | N_F32)
11881 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11882 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11884 /* Pass this as the first type argument to neon_check_type to ignore types
11886 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11888 /* Select a "shape" for the current instruction (describing register types or
11889 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11890 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11891 function of operand parsing, so this function doesn't need to be called.
11892 Shapes should be listed in order of decreasing length. */
11894 static enum neon_shape
11895 neon_select_shape (enum neon_shape shape
, ...)
11898 enum neon_shape first_shape
= shape
;
11900 /* Fix missing optional operands. FIXME: we don't know at this point how
11901 many arguments we should have, so this makes the assumption that we have
11902 > 1. This is true of all current Neon opcodes, I think, but may not be
11903 true in the future. */
11904 if (!inst
.operands
[1].present
)
11905 inst
.operands
[1] = inst
.operands
[0];
11907 va_start (ap
, shape
);
11909 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11914 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11916 if (!inst
.operands
[j
].present
)
11922 switch (neon_shape_tab
[shape
].el
[j
])
11925 if (!(inst
.operands
[j
].isreg
11926 && inst
.operands
[j
].isvec
11927 && inst
.operands
[j
].issingle
11928 && !inst
.operands
[j
].isquad
))
11933 if (!(inst
.operands
[j
].isreg
11934 && inst
.operands
[j
].isvec
11935 && !inst
.operands
[j
].isquad
11936 && !inst
.operands
[j
].issingle
))
11941 if (!(inst
.operands
[j
].isreg
11942 && !inst
.operands
[j
].isvec
))
11947 if (!(inst
.operands
[j
].isreg
11948 && inst
.operands
[j
].isvec
11949 && inst
.operands
[j
].isquad
11950 && !inst
.operands
[j
].issingle
))
11955 if (!(!inst
.operands
[j
].isreg
11956 && !inst
.operands
[j
].isscalar
))
11961 if (!(!inst
.operands
[j
].isreg
11962 && inst
.operands
[j
].isscalar
))
11978 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11979 first_error (_("invalid instruction shape"));
11984 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11985 means the Q bit should be set). */
11988 neon_quad (enum neon_shape shape
)
11990 return neon_shape_class
[shape
] == SC_QUAD
;
11994 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11997 /* Allow modification to be made to types which are constrained to be
11998 based on the key element, based on bits set alongside N_EQK. */
11999 if ((typebits
& N_EQK
) != 0)
12001 if ((typebits
& N_HLF
) != 0)
12003 else if ((typebits
& N_DBL
) != 0)
12005 if ((typebits
& N_SGN
) != 0)
12006 *g_type
= NT_signed
;
12007 else if ((typebits
& N_UNS
) != 0)
12008 *g_type
= NT_unsigned
;
12009 else if ((typebits
& N_INT
) != 0)
12010 *g_type
= NT_integer
;
12011 else if ((typebits
& N_FLT
) != 0)
12012 *g_type
= NT_float
;
12013 else if ((typebits
& N_SIZ
) != 0)
12014 *g_type
= NT_untyped
;
12018 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12019 operand type, i.e. the single type specified in a Neon instruction when it
12020 is the only one given. */
12022 static struct neon_type_el
12023 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12025 struct neon_type_el dest
= *key
;
12027 gas_assert ((thisarg
& N_EQK
) != 0);
12029 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12034 /* Convert Neon type and size into compact bitmask representation. */
12036 static enum neon_type_mask
12037 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12044 case 8: return N_8
;
12045 case 16: return N_16
;
12046 case 32: return N_32
;
12047 case 64: return N_64
;
12055 case 8: return N_I8
;
12056 case 16: return N_I16
;
12057 case 32: return N_I32
;
12058 case 64: return N_I64
;
12066 case 16: return N_F16
;
12067 case 32: return N_F32
;
12068 case 64: return N_F64
;
12076 case 8: return N_P8
;
12077 case 16: return N_P16
;
12085 case 8: return N_S8
;
12086 case 16: return N_S16
;
12087 case 32: return N_S32
;
12088 case 64: return N_S64
;
12096 case 8: return N_U8
;
12097 case 16: return N_U16
;
12098 case 32: return N_U32
;
12099 case 64: return N_U64
;
12110 /* Convert compact Neon bitmask type representation to a type and size. Only
12111 handles the case where a single bit is set in the mask. */
12114 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12115 enum neon_type_mask mask
)
12117 if ((mask
& N_EQK
) != 0)
12120 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12122 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12124 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12126 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12131 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12133 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12134 *type
= NT_unsigned
;
12135 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12136 *type
= NT_integer
;
12137 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12138 *type
= NT_untyped
;
12139 else if ((mask
& (N_P8
| N_P16
)) != 0)
12141 else if ((mask
& (N_F32
| N_F64
)) != 0)
12149 /* Modify a bitmask of allowed types. This is only needed for type
12153 modify_types_allowed (unsigned allowed
, unsigned mods
)
12156 enum neon_el_type type
;
12162 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12164 if (el_type_of_type_chk (&type
, &size
,
12165 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12167 neon_modify_type_size (mods
, &type
, &size
);
12168 destmask
|= type_chk_of_el_type (type
, size
);
12175 /* Check type and return type classification.
12176 The manual states (paraphrase): If one datatype is given, it indicates the
12178 - the second operand, if there is one
12179 - the operand, if there is no second operand
12180 - the result, if there are no operands.
12181 This isn't quite good enough though, so we use a concept of a "key" datatype
12182 which is set on a per-instruction basis, which is the one which matters when
12183 only one data type is written.
12184 Note: this function has side-effects (e.g. filling in missing operands). All
12185 Neon instructions should call it before performing bit encoding. */
12187 static struct neon_type_el
12188 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12191 unsigned i
, pass
, key_el
= 0;
12192 unsigned types
[NEON_MAX_TYPE_ELS
];
12193 enum neon_el_type k_type
= NT_invtype
;
12194 unsigned k_size
= -1u;
12195 struct neon_type_el badtype
= {NT_invtype
, -1};
12196 unsigned key_allowed
= 0;
12198 /* Optional registers in Neon instructions are always (not) in operand 1.
12199 Fill in the missing operand here, if it was omitted. */
12200 if (els
> 1 && !inst
.operands
[1].present
)
12201 inst
.operands
[1] = inst
.operands
[0];
12203 /* Suck up all the varargs. */
12205 for (i
= 0; i
< els
; i
++)
12207 unsigned thisarg
= va_arg (ap
, unsigned);
12208 if (thisarg
== N_IGNORE_TYPE
)
12213 types
[i
] = thisarg
;
12214 if ((thisarg
& N_KEY
) != 0)
12219 if (inst
.vectype
.elems
> 0)
12220 for (i
= 0; i
< els
; i
++)
12221 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12223 first_error (_("types specified in both the mnemonic and operands"));
12227 /* Duplicate inst.vectype elements here as necessary.
12228 FIXME: No idea if this is exactly the same as the ARM assembler,
12229 particularly when an insn takes one register and one non-register
12231 if (inst
.vectype
.elems
== 1 && els
> 1)
12234 inst
.vectype
.elems
= els
;
12235 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12236 for (j
= 0; j
< els
; j
++)
12238 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12241 else if (inst
.vectype
.elems
== 0 && els
> 0)
12244 /* No types were given after the mnemonic, so look for types specified
12245 after each operand. We allow some flexibility here; as long as the
12246 "key" operand has a type, we can infer the others. */
12247 for (j
= 0; j
< els
; j
++)
12248 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12249 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12251 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12253 for (j
= 0; j
< els
; j
++)
12254 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12255 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12260 first_error (_("operand types can't be inferred"));
12264 else if (inst
.vectype
.elems
!= els
)
12266 first_error (_("type specifier has the wrong number of parts"));
12270 for (pass
= 0; pass
< 2; pass
++)
12272 for (i
= 0; i
< els
; i
++)
12274 unsigned thisarg
= types
[i
];
12275 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12276 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12277 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12278 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12280 /* Decay more-specific signed & unsigned types to sign-insensitive
12281 integer types if sign-specific variants are unavailable. */
12282 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12283 && (types_allowed
& N_SU_ALL
) == 0)
12284 g_type
= NT_integer
;
12286 /* If only untyped args are allowed, decay any more specific types to
12287 them. Some instructions only care about signs for some element
12288 sizes, so handle that properly. */
12289 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12290 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12291 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12292 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12293 g_type
= NT_untyped
;
12297 if ((thisarg
& N_KEY
) != 0)
12301 key_allowed
= thisarg
& ~N_KEY
;
12306 if ((thisarg
& N_VFP
) != 0)
12308 enum neon_shape_el regshape
;
12309 unsigned regwidth
, match
;
12311 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12314 first_error (_("invalid instruction shape"));
12317 regshape
= neon_shape_tab
[ns
].el
[i
];
12318 regwidth
= neon_shape_el_size
[regshape
];
12320 /* In VFP mode, operands must match register widths. If we
12321 have a key operand, use its width, else use the width of
12322 the current operand. */
12328 if (regwidth
!= match
)
12330 first_error (_("operand size must match register width"));
12335 if ((thisarg
& N_EQK
) == 0)
12337 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12339 if ((given_type
& types_allowed
) == 0)
12341 first_error (_("bad type in Neon instruction"));
12347 enum neon_el_type mod_k_type
= k_type
;
12348 unsigned mod_k_size
= k_size
;
12349 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12350 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12352 first_error (_("inconsistent types in Neon instruction"));
12360 return inst
.vectype
.el
[key_el
];
12363 /* Neon-style VFP instruction forwarding. */
12365 /* Thumb VFP instructions have 0xE in the condition field. */
12368 do_vfp_cond_or_thumb (void)
12373 inst
.instruction
|= 0xe0000000;
12375 inst
.instruction
|= inst
.cond
<< 28;
12378 /* Look up and encode a simple mnemonic, for use as a helper function for the
12379 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12380 etc. It is assumed that operand parsing has already been done, and that the
12381 operands are in the form expected by the given opcode (this isn't necessarily
12382 the same as the form in which they were parsed, hence some massaging must
12383 take place before this function is called).
12384 Checks current arch version against that in the looked-up opcode. */
12387 do_vfp_nsyn_opcode (const char *opname
)
12389 const struct asm_opcode
*opcode
;
12391 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12396 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12397 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12404 inst
.instruction
= opcode
->tvalue
;
12405 opcode
->tencode ();
12409 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12410 opcode
->aencode ();
12415 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12417 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12422 do_vfp_nsyn_opcode ("fadds");
12424 do_vfp_nsyn_opcode ("fsubs");
12429 do_vfp_nsyn_opcode ("faddd");
12431 do_vfp_nsyn_opcode ("fsubd");
12435 /* Check operand types to see if this is a VFP instruction, and if so call
12439 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12441 enum neon_shape rs
;
12442 struct neon_type_el et
;
12447 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12448 et
= neon_check_type (2, rs
,
12449 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12453 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12454 et
= neon_check_type (3, rs
,
12455 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12462 if (et
.type
!= NT_invtype
)
12473 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12475 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12480 do_vfp_nsyn_opcode ("fmacs");
12482 do_vfp_nsyn_opcode ("fnmacs");
12487 do_vfp_nsyn_opcode ("fmacd");
12489 do_vfp_nsyn_opcode ("fnmacd");
12494 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12496 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12501 do_vfp_nsyn_opcode ("ffmas");
12503 do_vfp_nsyn_opcode ("ffnmas");
12508 do_vfp_nsyn_opcode ("ffmad");
12510 do_vfp_nsyn_opcode ("ffnmad");
12515 do_vfp_nsyn_mul (enum neon_shape rs
)
12518 do_vfp_nsyn_opcode ("fmuls");
12520 do_vfp_nsyn_opcode ("fmuld");
12524 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12526 int is_neg
= (inst
.instruction
& 0x80) != 0;
12527 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12532 do_vfp_nsyn_opcode ("fnegs");
12534 do_vfp_nsyn_opcode ("fabss");
12539 do_vfp_nsyn_opcode ("fnegd");
12541 do_vfp_nsyn_opcode ("fabsd");
12545 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12546 insns belong to Neon, and are handled elsewhere. */
12549 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12551 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12555 do_vfp_nsyn_opcode ("fldmdbs");
12557 do_vfp_nsyn_opcode ("fldmias");
12562 do_vfp_nsyn_opcode ("fstmdbs");
12564 do_vfp_nsyn_opcode ("fstmias");
12569 do_vfp_nsyn_sqrt (void)
12571 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12572 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12575 do_vfp_nsyn_opcode ("fsqrts");
12577 do_vfp_nsyn_opcode ("fsqrtd");
12581 do_vfp_nsyn_div (void)
12583 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12584 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12585 N_F32
| N_F64
| N_KEY
| N_VFP
);
12588 do_vfp_nsyn_opcode ("fdivs");
12590 do_vfp_nsyn_opcode ("fdivd");
12594 do_vfp_nsyn_nmul (void)
12596 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12597 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12598 N_F32
| N_F64
| N_KEY
| N_VFP
);
12602 NEON_ENCODE (SINGLE
, inst
);
12603 do_vfp_sp_dyadic ();
12607 NEON_ENCODE (DOUBLE
, inst
);
12608 do_vfp_dp_rd_rn_rm ();
12610 do_vfp_cond_or_thumb ();
12614 do_vfp_nsyn_cmp (void)
12616 if (inst
.operands
[1].isreg
)
12618 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12619 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12623 NEON_ENCODE (SINGLE
, inst
);
12624 do_vfp_sp_monadic ();
12628 NEON_ENCODE (DOUBLE
, inst
);
12629 do_vfp_dp_rd_rm ();
12634 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12635 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12637 switch (inst
.instruction
& 0x0fffffff)
12640 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12643 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12651 NEON_ENCODE (SINGLE
, inst
);
12652 do_vfp_sp_compare_z ();
12656 NEON_ENCODE (DOUBLE
, inst
);
12660 do_vfp_cond_or_thumb ();
12664 nsyn_insert_sp (void)
12666 inst
.operands
[1] = inst
.operands
[0];
12667 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12668 inst
.operands
[0].reg
= REG_SP
;
12669 inst
.operands
[0].isreg
= 1;
12670 inst
.operands
[0].writeback
= 1;
12671 inst
.operands
[0].present
= 1;
12675 do_vfp_nsyn_push (void)
12678 if (inst
.operands
[1].issingle
)
12679 do_vfp_nsyn_opcode ("fstmdbs");
12681 do_vfp_nsyn_opcode ("fstmdbd");
12685 do_vfp_nsyn_pop (void)
12688 if (inst
.operands
[1].issingle
)
12689 do_vfp_nsyn_opcode ("fldmias");
12691 do_vfp_nsyn_opcode ("fldmiad");
12694 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12695 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12698 neon_dp_fixup (struct arm_it
* insn
)
12700 unsigned int i
= insn
->instruction
;
12705 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12716 insn
->instruction
= i
;
12719 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12723 neon_logbits (unsigned x
)
12725 return ffs (x
) - 4;
12728 #define LOW4(R) ((R) & 0xf)
12729 #define HI1(R) (((R) >> 4) & 1)
12731 /* Encode insns with bit pattern:
12733 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12734 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12736 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12737 different meaning for some instruction. */
12740 neon_three_same (int isquad
, int ubit
, int size
)
12742 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12743 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12744 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12745 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12746 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12747 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12748 inst
.instruction
|= (isquad
!= 0) << 6;
12749 inst
.instruction
|= (ubit
!= 0) << 24;
12751 inst
.instruction
|= neon_logbits (size
) << 20;
12753 neon_dp_fixup (&inst
);
12756 /* Encode instructions of the form:
12758 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12759 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12761 Don't write size if SIZE == -1. */
12764 neon_two_same (int qbit
, int ubit
, int size
)
12766 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12767 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12768 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12769 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12770 inst
.instruction
|= (qbit
!= 0) << 6;
12771 inst
.instruction
|= (ubit
!= 0) << 24;
12774 inst
.instruction
|= neon_logbits (size
) << 18;
12776 neon_dp_fixup (&inst
);
12779 /* Neon instruction encoders, in approximate order of appearance. */
12782 do_neon_dyadic_i_su (void)
12784 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12785 struct neon_type_el et
= neon_check_type (3, rs
,
12786 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12787 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12791 do_neon_dyadic_i64_su (void)
12793 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12794 struct neon_type_el et
= neon_check_type (3, rs
,
12795 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12796 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12800 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12803 unsigned size
= et
.size
>> 3;
12804 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12805 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12806 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12807 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12808 inst
.instruction
|= (isquad
!= 0) << 6;
12809 inst
.instruction
|= immbits
<< 16;
12810 inst
.instruction
|= (size
>> 3) << 7;
12811 inst
.instruction
|= (size
& 0x7) << 19;
12813 inst
.instruction
|= (uval
!= 0) << 24;
12815 neon_dp_fixup (&inst
);
12819 do_neon_shl_imm (void)
12821 if (!inst
.operands
[2].isreg
)
12823 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12824 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12825 NEON_ENCODE (IMMED
, inst
);
12826 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12830 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12831 struct neon_type_el et
= neon_check_type (3, rs
,
12832 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12835 /* VSHL/VQSHL 3-register variants have syntax such as:
12837 whereas other 3-register operations encoded by neon_three_same have
12840 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12842 tmp
= inst
.operands
[2].reg
;
12843 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12844 inst
.operands
[1].reg
= tmp
;
12845 NEON_ENCODE (INTEGER
, inst
);
12846 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12851 do_neon_qshl_imm (void)
12853 if (!inst
.operands
[2].isreg
)
12855 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12856 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12858 NEON_ENCODE (IMMED
, inst
);
12859 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12860 inst
.operands
[2].imm
);
12864 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12865 struct neon_type_el et
= neon_check_type (3, rs
,
12866 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12869 /* See note in do_neon_shl_imm. */
12870 tmp
= inst
.operands
[2].reg
;
12871 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12872 inst
.operands
[1].reg
= tmp
;
12873 NEON_ENCODE (INTEGER
, inst
);
12874 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12879 do_neon_rshl (void)
12881 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12882 struct neon_type_el et
= neon_check_type (3, rs
,
12883 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12886 tmp
= inst
.operands
[2].reg
;
12887 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12888 inst
.operands
[1].reg
= tmp
;
12889 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12893 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12895 /* Handle .I8 pseudo-instructions. */
12898 /* Unfortunately, this will make everything apart from zero out-of-range.
12899 FIXME is this the intended semantics? There doesn't seem much point in
12900 accepting .I8 if so. */
12901 immediate
|= immediate
<< 8;
12907 if (immediate
== (immediate
& 0x000000ff))
12909 *immbits
= immediate
;
12912 else if (immediate
== (immediate
& 0x0000ff00))
12914 *immbits
= immediate
>> 8;
12917 else if (immediate
== (immediate
& 0x00ff0000))
12919 *immbits
= immediate
>> 16;
12922 else if (immediate
== (immediate
& 0xff000000))
12924 *immbits
= immediate
>> 24;
12927 if ((immediate
& 0xffff) != (immediate
>> 16))
12928 goto bad_immediate
;
12929 immediate
&= 0xffff;
12932 if (immediate
== (immediate
& 0x000000ff))
12934 *immbits
= immediate
;
12937 else if (immediate
== (immediate
& 0x0000ff00))
12939 *immbits
= immediate
>> 8;
12944 first_error (_("immediate value out of range"));
12948 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12952 neon_bits_same_in_bytes (unsigned imm
)
12954 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12955 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12956 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12957 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12960 /* For immediate of above form, return 0bABCD. */
12963 neon_squash_bits (unsigned imm
)
12965 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12966 | ((imm
& 0x01000000) >> 21);
12969 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12972 neon_qfloat_bits (unsigned imm
)
12974 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12977 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12978 the instruction. *OP is passed as the initial value of the op field, and
12979 may be set to a different value depending on the constant (i.e.
12980 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12981 MVN). If the immediate looks like a repeated pattern then also
12982 try smaller element sizes. */
12985 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12986 unsigned *immbits
, int *op
, int size
,
12987 enum neon_el_type type
)
12989 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12991 if (type
== NT_float
&& !float_p
)
12994 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12996 if (size
!= 32 || *op
== 1)
12998 *immbits
= neon_qfloat_bits (immlo
);
13004 if (neon_bits_same_in_bytes (immhi
)
13005 && neon_bits_same_in_bytes (immlo
))
13009 *immbits
= (neon_squash_bits (immhi
) << 4)
13010 | neon_squash_bits (immlo
);
13015 if (immhi
!= immlo
)
13021 if (immlo
== (immlo
& 0x000000ff))
13026 else if (immlo
== (immlo
& 0x0000ff00))
13028 *immbits
= immlo
>> 8;
13031 else if (immlo
== (immlo
& 0x00ff0000))
13033 *immbits
= immlo
>> 16;
13036 else if (immlo
== (immlo
& 0xff000000))
13038 *immbits
= immlo
>> 24;
13041 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13043 *immbits
= (immlo
>> 8) & 0xff;
13046 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13048 *immbits
= (immlo
>> 16) & 0xff;
13052 if ((immlo
& 0xffff) != (immlo
>> 16))
13059 if (immlo
== (immlo
& 0x000000ff))
13064 else if (immlo
== (immlo
& 0x0000ff00))
13066 *immbits
= immlo
>> 8;
13070 if ((immlo
& 0xff) != (immlo
>> 8))
13075 if (immlo
== (immlo
& 0x000000ff))
13077 /* Don't allow MVN with 8-bit immediate. */
13087 /* Write immediate bits [7:0] to the following locations:
13089 |28/24|23 19|18 16|15 4|3 0|
13090 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13092 This function is used by VMOV/VMVN/VORR/VBIC. */
13095 neon_write_immbits (unsigned immbits
)
13097 inst
.instruction
|= immbits
& 0xf;
13098 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13099 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13102 /* Invert low-order SIZE bits of XHI:XLO. */
13105 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13107 unsigned immlo
= xlo
? *xlo
: 0;
13108 unsigned immhi
= xhi
? *xhi
: 0;
13113 immlo
= (~immlo
) & 0xff;
13117 immlo
= (~immlo
) & 0xffff;
13121 immhi
= (~immhi
) & 0xffffffff;
13122 /* fall through. */
13125 immlo
= (~immlo
) & 0xffffffff;
13140 do_neon_logic (void)
13142 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13144 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13145 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13146 /* U bit and size field were set as part of the bitmask. */
13147 NEON_ENCODE (INTEGER
, inst
);
13148 neon_three_same (neon_quad (rs
), 0, -1);
13152 const int three_ops_form
= (inst
.operands
[2].present
13153 && !inst
.operands
[2].isreg
);
13154 const int immoperand
= (three_ops_form
? 2 : 1);
13155 enum neon_shape rs
= (three_ops_form
13156 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13157 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13158 struct neon_type_el et
= neon_check_type (2, rs
,
13159 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13160 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13164 if (et
.type
== NT_invtype
)
13167 if (three_ops_form
)
13168 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13169 _("first and second operands shall be the same register"));
13171 NEON_ENCODE (IMMED
, inst
);
13173 immbits
= inst
.operands
[immoperand
].imm
;
13176 /* .i64 is a pseudo-op, so the immediate must be a repeating
13178 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13179 inst
.operands
[immoperand
].reg
: 0))
13181 /* Set immbits to an invalid constant. */
13182 immbits
= 0xdeadbeef;
13189 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13193 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13197 /* Pseudo-instruction for VBIC. */
13198 neon_invert_size (&immbits
, 0, et
.size
);
13199 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13203 /* Pseudo-instruction for VORR. */
13204 neon_invert_size (&immbits
, 0, et
.size
);
13205 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13215 inst
.instruction
|= neon_quad (rs
) << 6;
13216 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13217 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13218 inst
.instruction
|= cmode
<< 8;
13219 neon_write_immbits (immbits
);
13221 neon_dp_fixup (&inst
);
13226 do_neon_bitfield (void)
13228 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13229 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13230 neon_three_same (neon_quad (rs
), 0, -1);
13234 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13237 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13238 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13240 if (et
.type
== NT_float
)
13242 NEON_ENCODE (FLOAT
, inst
);
13243 neon_three_same (neon_quad (rs
), 0, -1);
13247 NEON_ENCODE (INTEGER
, inst
);
13248 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13253 do_neon_dyadic_if_su (void)
13255 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13259 do_neon_dyadic_if_su_d (void)
13261 /* This version only allow D registers, but that constraint is enforced during
13262 operand parsing so we don't need to do anything extra here. */
13263 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13267 do_neon_dyadic_if_i_d (void)
13269 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13270 affected if we specify unsigned args. */
13271 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13274 enum vfp_or_neon_is_neon_bits
13277 NEON_CHECK_ARCH
= 2
13280 /* Call this function if an instruction which may have belonged to the VFP or
13281 Neon instruction sets, but turned out to be a Neon instruction (due to the
13282 operand types involved, etc.). We have to check and/or fix-up a couple of
13285 - Make sure the user hasn't attempted to make a Neon instruction
13287 - Alter the value in the condition code field if necessary.
13288 - Make sure that the arch supports Neon instructions.
13290 Which of these operations take place depends on bits from enum
13291 vfp_or_neon_is_neon_bits.
13293 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13294 current instruction's condition is COND_ALWAYS, the condition field is
13295 changed to inst.uncond_value. This is necessary because instructions shared
13296 between VFP and Neon may be conditional for the VFP variants only, and the
13297 unconditional Neon version must have, e.g., 0xF in the condition field. */
13300 vfp_or_neon_is_neon (unsigned check
)
13302 /* Conditions are always legal in Thumb mode (IT blocks). */
13303 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13305 if (inst
.cond
!= COND_ALWAYS
)
13307 first_error (_(BAD_COND
));
13310 if (inst
.uncond_value
!= -1)
13311 inst
.instruction
|= inst
.uncond_value
<< 28;
13314 if ((check
& NEON_CHECK_ARCH
)
13315 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13317 first_error (_(BAD_FPU
));
13325 do_neon_addsub_if_i (void)
13327 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13330 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13333 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13334 affected if we specify unsigned args. */
13335 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13338 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13340 V<op> A,B (A is operand 0, B is operand 2)
13345 so handle that case specially. */
13348 neon_exchange_operands (void)
13350 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13351 if (inst
.operands
[1].present
)
13353 /* Swap operands[1] and operands[2]. */
13354 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13355 inst
.operands
[1] = inst
.operands
[2];
13356 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13360 inst
.operands
[1] = inst
.operands
[2];
13361 inst
.operands
[2] = inst
.operands
[0];
13366 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13368 if (inst
.operands
[2].isreg
)
13371 neon_exchange_operands ();
13372 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13376 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13377 struct neon_type_el et
= neon_check_type (2, rs
,
13378 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13380 NEON_ENCODE (IMMED
, inst
);
13381 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13382 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13383 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13384 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13385 inst
.instruction
|= neon_quad (rs
) << 6;
13386 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13387 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13389 neon_dp_fixup (&inst
);
13396 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13400 do_neon_cmp_inv (void)
13402 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13408 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13411 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13412 scalars, which are encoded in 5 bits, M : Rm.
13413 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13414 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13418 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13420 unsigned regno
= NEON_SCALAR_REG (scalar
);
13421 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13426 if (regno
> 7 || elno
> 3)
13428 return regno
| (elno
<< 3);
13431 if (regno
> 15 || elno
> 1)
13433 return regno
| (elno
<< 4);
13437 first_error (_("scalar out of range for multiply instruction"));
13443 /* Encode multiply / multiply-accumulate scalar instructions. */
13446 neon_mul_mac (struct neon_type_el et
, int ubit
)
13450 /* Give a more helpful error message if we have an invalid type. */
13451 if (et
.type
== NT_invtype
)
13454 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13455 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13456 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13457 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13458 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13459 inst
.instruction
|= LOW4 (scalar
);
13460 inst
.instruction
|= HI1 (scalar
) << 5;
13461 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13462 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13463 inst
.instruction
|= (ubit
!= 0) << 24;
13465 neon_dp_fixup (&inst
);
13469 do_neon_mac_maybe_scalar (void)
13471 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13474 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13477 if (inst
.operands
[2].isscalar
)
13479 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13480 struct neon_type_el et
= neon_check_type (3, rs
,
13481 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13482 NEON_ENCODE (SCALAR
, inst
);
13483 neon_mul_mac (et
, neon_quad (rs
));
13487 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13488 affected if we specify unsigned args. */
13489 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13494 do_neon_fmac (void)
13496 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13499 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13502 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13508 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13509 struct neon_type_el et
= neon_check_type (3, rs
,
13510 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13511 neon_three_same (neon_quad (rs
), 0, et
.size
);
13514 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13515 same types as the MAC equivalents. The polynomial type for this instruction
13516 is encoded the same as the integer type. */
13521 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13524 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13527 if (inst
.operands
[2].isscalar
)
13528 do_neon_mac_maybe_scalar ();
13530 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13534 do_neon_qdmulh (void)
13536 if (inst
.operands
[2].isscalar
)
13538 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13539 struct neon_type_el et
= neon_check_type (3, rs
,
13540 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13541 NEON_ENCODE (SCALAR
, inst
);
13542 neon_mul_mac (et
, neon_quad (rs
));
13546 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13547 struct neon_type_el et
= neon_check_type (3, rs
,
13548 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13549 NEON_ENCODE (INTEGER
, inst
);
13550 /* The U bit (rounding) comes from bit mask. */
13551 neon_three_same (neon_quad (rs
), 0, et
.size
);
13556 do_neon_fcmp_absolute (void)
13558 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13559 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13560 /* Size field comes from bit mask. */
13561 neon_three_same (neon_quad (rs
), 1, -1);
13565 do_neon_fcmp_absolute_inv (void)
13567 neon_exchange_operands ();
13568 do_neon_fcmp_absolute ();
13572 do_neon_step (void)
13574 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13575 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13576 neon_three_same (neon_quad (rs
), 0, -1);
13580 do_neon_abs_neg (void)
13582 enum neon_shape rs
;
13583 struct neon_type_el et
;
13585 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13588 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13591 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13592 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13594 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13595 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13596 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13597 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13598 inst
.instruction
|= neon_quad (rs
) << 6;
13599 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13600 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13602 neon_dp_fixup (&inst
);
13608 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13609 struct neon_type_el et
= neon_check_type (2, rs
,
13610 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13611 int imm
= inst
.operands
[2].imm
;
13612 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13613 _("immediate out of range for insert"));
13614 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13620 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13621 struct neon_type_el et
= neon_check_type (2, rs
,
13622 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13623 int imm
= inst
.operands
[2].imm
;
13624 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13625 _("immediate out of range for insert"));
13626 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13630 do_neon_qshlu_imm (void)
13632 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13633 struct neon_type_el et
= neon_check_type (2, rs
,
13634 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13635 int imm
= inst
.operands
[2].imm
;
13636 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13637 _("immediate out of range for shift"));
13638 /* Only encodes the 'U present' variant of the instruction.
13639 In this case, signed types have OP (bit 8) set to 0.
13640 Unsigned types have OP set to 1. */
13641 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13642 /* The rest of the bits are the same as other immediate shifts. */
13643 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13647 do_neon_qmovn (void)
13649 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13650 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13651 /* Saturating move where operands can be signed or unsigned, and the
13652 destination has the same signedness. */
13653 NEON_ENCODE (INTEGER
, inst
);
13654 if (et
.type
== NT_unsigned
)
13655 inst
.instruction
|= 0xc0;
13657 inst
.instruction
|= 0x80;
13658 neon_two_same (0, 1, et
.size
/ 2);
13662 do_neon_qmovun (void)
13664 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13665 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13666 /* Saturating move with unsigned results. Operands must be signed. */
13667 NEON_ENCODE (INTEGER
, inst
);
13668 neon_two_same (0, 1, et
.size
/ 2);
13672 do_neon_rshift_sat_narrow (void)
13674 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13675 or unsigned. If operands are unsigned, results must also be unsigned. */
13676 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13677 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13678 int imm
= inst
.operands
[2].imm
;
13679 /* This gets the bounds check, size encoding and immediate bits calculation
13683 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13684 VQMOVN.I<size> <Dd>, <Qm>. */
13687 inst
.operands
[2].present
= 0;
13688 inst
.instruction
= N_MNEM_vqmovn
;
13693 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13694 _("immediate out of range"));
13695 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13699 do_neon_rshift_sat_narrow_u (void)
13701 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13702 or unsigned. If operands are unsigned, results must also be unsigned. */
13703 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13704 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13705 int imm
= inst
.operands
[2].imm
;
13706 /* This gets the bounds check, size encoding and immediate bits calculation
13710 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13711 VQMOVUN.I<size> <Dd>, <Qm>. */
13714 inst
.operands
[2].present
= 0;
13715 inst
.instruction
= N_MNEM_vqmovun
;
13720 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13721 _("immediate out of range"));
13722 /* FIXME: The manual is kind of unclear about what value U should have in
13723 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13725 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13729 do_neon_movn (void)
13731 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13732 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13733 NEON_ENCODE (INTEGER
, inst
);
13734 neon_two_same (0, 1, et
.size
/ 2);
13738 do_neon_rshift_narrow (void)
13740 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13741 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13742 int imm
= inst
.operands
[2].imm
;
13743 /* This gets the bounds check, size encoding and immediate bits calculation
13747 /* If immediate is zero then we are a pseudo-instruction for
13748 VMOVN.I<size> <Dd>, <Qm> */
13751 inst
.operands
[2].present
= 0;
13752 inst
.instruction
= N_MNEM_vmovn
;
13757 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13758 _("immediate out of range for narrowing operation"));
13759 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13763 do_neon_shll (void)
13765 /* FIXME: Type checking when lengthening. */
13766 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13767 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13768 unsigned imm
= inst
.operands
[2].imm
;
13770 if (imm
== et
.size
)
13772 /* Maximum shift variant. */
13773 NEON_ENCODE (INTEGER
, inst
);
13774 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13775 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13776 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13777 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13778 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13780 neon_dp_fixup (&inst
);
13784 /* A more-specific type check for non-max versions. */
13785 et
= neon_check_type (2, NS_QDI
,
13786 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13787 NEON_ENCODE (IMMED
, inst
);
13788 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13792 /* Check the various types for the VCVT instruction, and return which version
13793 the current instruction is. */
13796 neon_cvt_flavour (enum neon_shape rs
)
13798 #define CVT_VAR(C,X,Y) \
13799 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13800 if (et.type != NT_invtype) \
13802 inst.error = NULL; \
13805 struct neon_type_el et
;
13806 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13807 || rs
== NS_FF
) ? N_VFP
: 0;
13808 /* The instruction versions which take an immediate take one register
13809 argument, which is extended to the width of the full register. Thus the
13810 "source" and "destination" registers must have the same width. Hack that
13811 here by making the size equal to the key (wider, in this case) operand. */
13812 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13814 CVT_VAR (0, N_S32
, N_F32
);
13815 CVT_VAR (1, N_U32
, N_F32
);
13816 CVT_VAR (2, N_F32
, N_S32
);
13817 CVT_VAR (3, N_F32
, N_U32
);
13818 /* Half-precision conversions. */
13819 CVT_VAR (4, N_F32
, N_F16
);
13820 CVT_VAR (5, N_F16
, N_F32
);
13824 /* VFP instructions. */
13825 CVT_VAR (6, N_F32
, N_F64
);
13826 CVT_VAR (7, N_F64
, N_F32
);
13827 CVT_VAR (8, N_S32
, N_F64
| key
);
13828 CVT_VAR (9, N_U32
, N_F64
| key
);
13829 CVT_VAR (10, N_F64
| key
, N_S32
);
13830 CVT_VAR (11, N_F64
| key
, N_U32
);
13831 /* VFP instructions with bitshift. */
13832 CVT_VAR (12, N_F32
| key
, N_S16
);
13833 CVT_VAR (13, N_F32
| key
, N_U16
);
13834 CVT_VAR (14, N_F64
| key
, N_S16
);
13835 CVT_VAR (15, N_F64
| key
, N_U16
);
13836 CVT_VAR (16, N_S16
, N_F32
| key
);
13837 CVT_VAR (17, N_U16
, N_F32
| key
);
13838 CVT_VAR (18, N_S16
, N_F64
| key
);
13839 CVT_VAR (19, N_U16
, N_F64
| key
);
13845 /* Neon-syntax VFP conversions. */
13848 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13850 const char *opname
= 0;
13852 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13854 /* Conversions with immediate bitshift. */
13855 const char *enc
[] =
13879 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13881 opname
= enc
[flavour
];
13882 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13883 _("operands 0 and 1 must be the same register"));
13884 inst
.operands
[1] = inst
.operands
[2];
13885 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13890 /* Conversions without bitshift. */
13891 const char *enc
[] =
13907 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13908 opname
= enc
[flavour
];
13912 do_vfp_nsyn_opcode (opname
);
13916 do_vfp_nsyn_cvtz (void)
13918 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13919 int flavour
= neon_cvt_flavour (rs
);
13920 const char *enc
[] =
13934 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13935 do_vfp_nsyn_opcode (enc
[flavour
]);
13939 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13941 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13942 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13943 int flavour
= neon_cvt_flavour (rs
);
13945 /* PR11109: Handle round-to-zero for VCVT conversions. */
13947 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13948 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13949 && (rs
== NS_FD
|| rs
== NS_FF
))
13951 do_vfp_nsyn_cvtz ();
13955 /* VFP rather than Neon conversions. */
13958 do_vfp_nsyn_cvt (rs
, flavour
);
13968 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13970 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13973 /* Fixed-point conversion with #0 immediate is encoded as an
13974 integer conversion. */
13975 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13977 immbits
= 32 - inst
.operands
[2].imm
;
13978 NEON_ENCODE (IMMED
, inst
);
13980 inst
.instruction
|= enctab
[flavour
];
13981 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13982 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13983 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13984 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13985 inst
.instruction
|= neon_quad (rs
) << 6;
13986 inst
.instruction
|= 1 << 21;
13987 inst
.instruction
|= immbits
<< 16;
13989 neon_dp_fixup (&inst
);
13997 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13999 NEON_ENCODE (INTEGER
, inst
);
14001 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14005 inst
.instruction
|= enctab
[flavour
];
14007 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14008 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14009 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14010 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14011 inst
.instruction
|= neon_quad (rs
) << 6;
14012 inst
.instruction
|= 2 << 18;
14014 neon_dp_fixup (&inst
);
14018 /* Half-precision conversions for Advanced SIMD -- neon. */
14023 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14025 as_bad (_("operand size must match register width"));
14030 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14032 as_bad (_("operand size must match register width"));
14037 inst
.instruction
= 0x3b60600;
14039 inst
.instruction
= 0x3b60700;
14041 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14042 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14043 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14044 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14045 neon_dp_fixup (&inst
);
14049 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14050 do_vfp_nsyn_cvt (rs
, flavour
);
14055 do_neon_cvtr (void)
14057 do_neon_cvt_1 (FALSE
);
14063 do_neon_cvt_1 (TRUE
);
14067 do_neon_cvtb (void)
14069 inst
.instruction
= 0xeb20a40;
14071 /* The sizes are attached to the mnemonic. */
14072 if (inst
.vectype
.el
[0].type
!= NT_invtype
14073 && inst
.vectype
.el
[0].size
== 16)
14074 inst
.instruction
|= 0x00010000;
14076 /* Programmer's syntax: the sizes are attached to the operands. */
14077 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14078 && inst
.operands
[0].vectype
.size
== 16)
14079 inst
.instruction
|= 0x00010000;
14081 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14082 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14083 do_vfp_cond_or_thumb ();
14088 do_neon_cvtt (void)
14091 inst
.instruction
|= 0x80;
14095 neon_move_immediate (void)
14097 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14098 struct neon_type_el et
= neon_check_type (2, rs
,
14099 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14100 unsigned immlo
, immhi
= 0, immbits
;
14101 int op
, cmode
, float_p
;
14103 constraint (et
.type
== NT_invtype
,
14104 _("operand size must be specified for immediate VMOV"));
14106 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14107 op
= (inst
.instruction
& (1 << 5)) != 0;
14109 immlo
= inst
.operands
[1].imm
;
14110 if (inst
.operands
[1].regisimm
)
14111 immhi
= inst
.operands
[1].reg
;
14113 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14114 _("immediate has bits set outside the operand size"));
14116 float_p
= inst
.operands
[1].immisfloat
;
14118 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14119 et
.size
, et
.type
)) == FAIL
)
14121 /* Invert relevant bits only. */
14122 neon_invert_size (&immlo
, &immhi
, et
.size
);
14123 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14124 with one or the other; those cases are caught by
14125 neon_cmode_for_move_imm. */
14127 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14128 &op
, et
.size
, et
.type
)) == FAIL
)
14130 first_error (_("immediate out of range"));
14135 inst
.instruction
&= ~(1 << 5);
14136 inst
.instruction
|= op
<< 5;
14138 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14139 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14140 inst
.instruction
|= neon_quad (rs
) << 6;
14141 inst
.instruction
|= cmode
<< 8;
14143 neon_write_immbits (immbits
);
14149 if (inst
.operands
[1].isreg
)
14151 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14153 NEON_ENCODE (INTEGER
, inst
);
14154 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14155 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14156 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14157 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14158 inst
.instruction
|= neon_quad (rs
) << 6;
14162 NEON_ENCODE (IMMED
, inst
);
14163 neon_move_immediate ();
14166 neon_dp_fixup (&inst
);
14169 /* Encode instructions of form:
14171 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14172 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14175 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14177 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14178 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14179 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14180 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14181 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14182 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14183 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14184 inst
.instruction
|= neon_logbits (size
) << 20;
14186 neon_dp_fixup (&inst
);
14190 do_neon_dyadic_long (void)
14192 /* FIXME: Type checking for lengthening op. */
14193 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14194 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14195 neon_mixed_length (et
, et
.size
);
14199 do_neon_abal (void)
14201 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14202 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14203 neon_mixed_length (et
, et
.size
);
14207 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14209 if (inst
.operands
[2].isscalar
)
14211 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14212 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14213 NEON_ENCODE (SCALAR
, inst
);
14214 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14218 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14219 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14220 NEON_ENCODE (INTEGER
, inst
);
14221 neon_mixed_length (et
, et
.size
);
14226 do_neon_mac_maybe_scalar_long (void)
14228 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14232 do_neon_dyadic_wide (void)
14234 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14235 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14236 neon_mixed_length (et
, et
.size
);
14240 do_neon_dyadic_narrow (void)
14242 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14243 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14244 /* Operand sign is unimportant, and the U bit is part of the opcode,
14245 so force the operand type to integer. */
14246 et
.type
= NT_integer
;
14247 neon_mixed_length (et
, et
.size
/ 2);
14251 do_neon_mul_sat_scalar_long (void)
14253 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14257 do_neon_vmull (void)
14259 if (inst
.operands
[2].isscalar
)
14260 do_neon_mac_maybe_scalar_long ();
14263 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14264 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14265 if (et
.type
== NT_poly
)
14266 NEON_ENCODE (POLY
, inst
);
14268 NEON_ENCODE (INTEGER
, inst
);
14269 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14270 zero. Should be OK as-is. */
14271 neon_mixed_length (et
, et
.size
);
14278 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14279 struct neon_type_el et
= neon_check_type (3, rs
,
14280 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14281 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14283 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14284 _("shift out of range"));
14285 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14286 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14287 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14288 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14289 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14290 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14291 inst
.instruction
|= neon_quad (rs
) << 6;
14292 inst
.instruction
|= imm
<< 8;
14294 neon_dp_fixup (&inst
);
14300 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14301 struct neon_type_el et
= neon_check_type (2, rs
,
14302 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14303 unsigned op
= (inst
.instruction
>> 7) & 3;
14304 /* N (width of reversed regions) is encoded as part of the bitmask. We
14305 extract it here to check the elements to be reversed are smaller.
14306 Otherwise we'd get a reserved instruction. */
14307 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14308 gas_assert (elsize
!= 0);
14309 constraint (et
.size
>= elsize
,
14310 _("elements must be smaller than reversal region"));
14311 neon_two_same (neon_quad (rs
), 1, et
.size
);
14317 if (inst
.operands
[1].isscalar
)
14319 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14320 struct neon_type_el et
= neon_check_type (2, rs
,
14321 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14322 unsigned sizebits
= et
.size
>> 3;
14323 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14324 int logsize
= neon_logbits (et
.size
);
14325 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14327 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14330 NEON_ENCODE (SCALAR
, inst
);
14331 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14332 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14333 inst
.instruction
|= LOW4 (dm
);
14334 inst
.instruction
|= HI1 (dm
) << 5;
14335 inst
.instruction
|= neon_quad (rs
) << 6;
14336 inst
.instruction
|= x
<< 17;
14337 inst
.instruction
|= sizebits
<< 16;
14339 neon_dp_fixup (&inst
);
14343 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14344 struct neon_type_el et
= neon_check_type (2, rs
,
14345 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14346 /* Duplicate ARM register to lanes of vector. */
14347 NEON_ENCODE (ARMREG
, inst
);
14350 case 8: inst
.instruction
|= 0x400000; break;
14351 case 16: inst
.instruction
|= 0x000020; break;
14352 case 32: inst
.instruction
|= 0x000000; break;
14355 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14356 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14357 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14358 inst
.instruction
|= neon_quad (rs
) << 21;
14359 /* The encoding for this instruction is identical for the ARM and Thumb
14360 variants, except for the condition field. */
14361 do_vfp_cond_or_thumb ();
14365 /* VMOV has particularly many variations. It can be one of:
14366 0. VMOV<c><q> <Qd>, <Qm>
14367 1. VMOV<c><q> <Dd>, <Dm>
14368 (Register operations, which are VORR with Rm = Rn.)
14369 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14370 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14372 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14373 (ARM register to scalar.)
14374 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14375 (Two ARM registers to vector.)
14376 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14377 (Scalar to ARM register.)
14378 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14379 (Vector to two ARM registers.)
14380 8. VMOV.F32 <Sd>, <Sm>
14381 9. VMOV.F64 <Dd>, <Dm>
14382 (VFP register moves.)
14383 10. VMOV.F32 <Sd>, #imm
14384 11. VMOV.F64 <Dd>, #imm
14385 (VFP float immediate load.)
14386 12. VMOV <Rd>, <Sm>
14387 (VFP single to ARM reg.)
14388 13. VMOV <Sd>, <Rm>
14389 (ARM reg to VFP single.)
14390 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14391 (Two ARM regs to two VFP singles.)
14392 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14393 (Two VFP singles to two ARM regs.)
14395 These cases can be disambiguated using neon_select_shape, except cases 1/9
14396 and 3/11 which depend on the operand type too.
14398 All the encoded bits are hardcoded by this function.
14400 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14401 Cases 5, 7 may be used with VFPv2 and above.
14403 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14404 can specify a type where it doesn't make sense to, and is ignored). */
14409 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14410 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14412 struct neon_type_el et
;
14413 const char *ldconst
= 0;
14417 case NS_DD
: /* case 1/9. */
14418 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14419 /* It is not an error here if no type is given. */
14421 if (et
.type
== NT_float
&& et
.size
== 64)
14423 do_vfp_nsyn_opcode ("fcpyd");
14426 /* fall through. */
14428 case NS_QQ
: /* case 0/1. */
14430 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14432 /* The architecture manual I have doesn't explicitly state which
14433 value the U bit should have for register->register moves, but
14434 the equivalent VORR instruction has U = 0, so do that. */
14435 inst
.instruction
= 0x0200110;
14436 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14437 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14438 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14439 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14440 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14441 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14442 inst
.instruction
|= neon_quad (rs
) << 6;
14444 neon_dp_fixup (&inst
);
14448 case NS_DI
: /* case 3/11. */
14449 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14451 if (et
.type
== NT_float
&& et
.size
== 64)
14453 /* case 11 (fconstd). */
14454 ldconst
= "fconstd";
14455 goto encode_fconstd
;
14457 /* fall through. */
14459 case NS_QI
: /* case 2/3. */
14460 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14462 inst
.instruction
= 0x0800010;
14463 neon_move_immediate ();
14464 neon_dp_fixup (&inst
);
14467 case NS_SR
: /* case 4. */
14469 unsigned bcdebits
= 0;
14471 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14472 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14474 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14475 logsize
= neon_logbits (et
.size
);
14477 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14479 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14480 && et
.size
!= 32, _(BAD_FPU
));
14481 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14482 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14486 case 8: bcdebits
= 0x8; break;
14487 case 16: bcdebits
= 0x1; break;
14488 case 32: bcdebits
= 0x0; break;
14492 bcdebits
|= x
<< logsize
;
14494 inst
.instruction
= 0xe000b10;
14495 do_vfp_cond_or_thumb ();
14496 inst
.instruction
|= LOW4 (dn
) << 16;
14497 inst
.instruction
|= HI1 (dn
) << 7;
14498 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14499 inst
.instruction
|= (bcdebits
& 3) << 5;
14500 inst
.instruction
|= (bcdebits
>> 2) << 21;
14504 case NS_DRR
: /* case 5 (fmdrr). */
14505 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14508 inst
.instruction
= 0xc400b10;
14509 do_vfp_cond_or_thumb ();
14510 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14511 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14512 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14513 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14516 case NS_RS
: /* case 6. */
14519 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14520 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14521 unsigned abcdebits
= 0;
14523 et
= neon_check_type (2, NS_NULL
,
14524 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14525 logsize
= neon_logbits (et
.size
);
14527 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14529 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14530 && et
.size
!= 32, _(BAD_FPU
));
14531 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14532 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14536 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14537 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14538 case 32: abcdebits
= 0x00; break;
14542 abcdebits
|= x
<< logsize
;
14543 inst
.instruction
= 0xe100b10;
14544 do_vfp_cond_or_thumb ();
14545 inst
.instruction
|= LOW4 (dn
) << 16;
14546 inst
.instruction
|= HI1 (dn
) << 7;
14547 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14548 inst
.instruction
|= (abcdebits
& 3) << 5;
14549 inst
.instruction
|= (abcdebits
>> 2) << 21;
14553 case NS_RRD
: /* case 7 (fmrrd). */
14554 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14557 inst
.instruction
= 0xc500b10;
14558 do_vfp_cond_or_thumb ();
14559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14560 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14561 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14562 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14565 case NS_FF
: /* case 8 (fcpys). */
14566 do_vfp_nsyn_opcode ("fcpys");
14569 case NS_FI
: /* case 10 (fconsts). */
14570 ldconst
= "fconsts";
14572 if (is_quarter_float (inst
.operands
[1].imm
))
14574 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14575 do_vfp_nsyn_opcode (ldconst
);
14578 first_error (_("immediate out of range"));
14581 case NS_RF
: /* case 12 (fmrs). */
14582 do_vfp_nsyn_opcode ("fmrs");
14585 case NS_FR
: /* case 13 (fmsr). */
14586 do_vfp_nsyn_opcode ("fmsr");
14589 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14590 (one of which is a list), but we have parsed four. Do some fiddling to
14591 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14593 case NS_RRFF
: /* case 14 (fmrrs). */
14594 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14595 _("VFP registers must be adjacent"));
14596 inst
.operands
[2].imm
= 2;
14597 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14598 do_vfp_nsyn_opcode ("fmrrs");
14601 case NS_FFRR
: /* case 15 (fmsrr). */
14602 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14603 _("VFP registers must be adjacent"));
14604 inst
.operands
[1] = inst
.operands
[2];
14605 inst
.operands
[2] = inst
.operands
[3];
14606 inst
.operands
[0].imm
= 2;
14607 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14608 do_vfp_nsyn_opcode ("fmsrr");
14617 do_neon_rshift_round_imm (void)
14619 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14620 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14621 int imm
= inst
.operands
[2].imm
;
14623 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14626 inst
.operands
[2].present
= 0;
14631 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14632 _("immediate out of range for shift"));
14633 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14638 do_neon_movl (void)
14640 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14641 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14642 unsigned sizebits
= et
.size
>> 3;
14643 inst
.instruction
|= sizebits
<< 19;
14644 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14650 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14651 struct neon_type_el et
= neon_check_type (2, rs
,
14652 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14653 NEON_ENCODE (INTEGER
, inst
);
14654 neon_two_same (neon_quad (rs
), 1, et
.size
);
14658 do_neon_zip_uzp (void)
14660 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14661 struct neon_type_el et
= neon_check_type (2, rs
,
14662 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14663 if (rs
== NS_DD
&& et
.size
== 32)
14665 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14666 inst
.instruction
= N_MNEM_vtrn
;
14670 neon_two_same (neon_quad (rs
), 1, et
.size
);
14674 do_neon_sat_abs_neg (void)
14676 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14677 struct neon_type_el et
= neon_check_type (2, rs
,
14678 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14679 neon_two_same (neon_quad (rs
), 1, et
.size
);
14683 do_neon_pair_long (void)
14685 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14686 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14687 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14688 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14689 neon_two_same (neon_quad (rs
), 1, et
.size
);
14693 do_neon_recip_est (void)
14695 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14696 struct neon_type_el et
= neon_check_type (2, rs
,
14697 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14698 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14699 neon_two_same (neon_quad (rs
), 1, et
.size
);
14705 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14706 struct neon_type_el et
= neon_check_type (2, rs
,
14707 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14708 neon_two_same (neon_quad (rs
), 1, et
.size
);
14714 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14715 struct neon_type_el et
= neon_check_type (2, rs
,
14716 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14717 neon_two_same (neon_quad (rs
), 1, et
.size
);
14723 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14724 struct neon_type_el et
= neon_check_type (2, rs
,
14725 N_EQK
| N_INT
, N_8
| N_KEY
);
14726 neon_two_same (neon_quad (rs
), 1, et
.size
);
14732 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14733 neon_two_same (neon_quad (rs
), 1, -1);
14737 do_neon_tbl_tbx (void)
14739 unsigned listlenbits
;
14740 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14742 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14744 first_error (_("bad list length for table lookup"));
14748 listlenbits
= inst
.operands
[1].imm
- 1;
14749 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14750 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14751 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14752 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14753 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14754 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14755 inst
.instruction
|= listlenbits
<< 8;
14757 neon_dp_fixup (&inst
);
14761 do_neon_ldm_stm (void)
14763 /* P, U and L bits are part of bitmask. */
14764 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14765 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14767 if (inst
.operands
[1].issingle
)
14769 do_vfp_nsyn_ldm_stm (is_dbmode
);
14773 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14774 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14776 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14777 _("register list must contain at least 1 and at most 16 "
14780 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14781 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14782 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14783 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14785 inst
.instruction
|= offsetbits
;
14787 do_vfp_cond_or_thumb ();
14791 do_neon_ldr_str (void)
14793 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14795 if (inst
.operands
[0].issingle
)
14798 do_vfp_nsyn_opcode ("flds");
14800 do_vfp_nsyn_opcode ("fsts");
14805 do_vfp_nsyn_opcode ("fldd");
14807 do_vfp_nsyn_opcode ("fstd");
14811 /* "interleave" version also handles non-interleaving register VLD1/VST1
14815 do_neon_ld_st_interleave (void)
14817 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14818 N_8
| N_16
| N_32
| N_64
);
14819 unsigned alignbits
= 0;
14821 /* The bits in this table go:
14822 0: register stride of one (0) or two (1)
14823 1,2: register list length, minus one (1, 2, 3, 4).
14824 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14825 We use -1 for invalid entries. */
14826 const int typetable
[] =
14828 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14829 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14830 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14831 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14835 if (et
.type
== NT_invtype
)
14838 if (inst
.operands
[1].immisalign
)
14839 switch (inst
.operands
[1].imm
>> 8)
14841 case 64: alignbits
= 1; break;
14843 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14844 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14845 goto bad_alignment
;
14849 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14850 goto bad_alignment
;
14855 first_error (_("bad alignment"));
14859 inst
.instruction
|= alignbits
<< 4;
14860 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14862 /* Bits [4:6] of the immediate in a list specifier encode register stride
14863 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14864 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14865 up the right value for "type" in a table based on this value and the given
14866 list style, then stick it back. */
14867 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14868 | (((inst
.instruction
>> 8) & 3) << 3);
14870 typebits
= typetable
[idx
];
14872 constraint (typebits
== -1, _("bad list type for instruction"));
14874 inst
.instruction
&= ~0xf00;
14875 inst
.instruction
|= typebits
<< 8;
14878 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14879 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14880 otherwise. The variable arguments are a list of pairs of legal (size, align)
14881 values, terminated with -1. */
14884 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14887 int result
= FAIL
, thissize
, thisalign
;
14889 if (!inst
.operands
[1].immisalign
)
14895 va_start (ap
, do_align
);
14899 thissize
= va_arg (ap
, int);
14900 if (thissize
== -1)
14902 thisalign
= va_arg (ap
, int);
14904 if (size
== thissize
&& align
== thisalign
)
14907 while (result
!= SUCCESS
);
14911 if (result
== SUCCESS
)
14914 first_error (_("unsupported alignment for instruction"));
14920 do_neon_ld_st_lane (void)
14922 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14923 int align_good
, do_align
= 0;
14924 int logsize
= neon_logbits (et
.size
);
14925 int align
= inst
.operands
[1].imm
>> 8;
14926 int n
= (inst
.instruction
>> 8) & 3;
14927 int max_el
= 64 / et
.size
;
14929 if (et
.type
== NT_invtype
)
14932 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14933 _("bad list length"));
14934 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14935 _("scalar index out of range"));
14936 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14938 _("stride of 2 unavailable when element size is 8"));
14942 case 0: /* VLD1 / VST1. */
14943 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14945 if (align_good
== FAIL
)
14949 unsigned alignbits
= 0;
14952 case 16: alignbits
= 0x1; break;
14953 case 32: alignbits
= 0x3; break;
14956 inst
.instruction
|= alignbits
<< 4;
14960 case 1: /* VLD2 / VST2. */
14961 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14963 if (align_good
== FAIL
)
14966 inst
.instruction
|= 1 << 4;
14969 case 2: /* VLD3 / VST3. */
14970 constraint (inst
.operands
[1].immisalign
,
14971 _("can't use alignment with this instruction"));
14974 case 3: /* VLD4 / VST4. */
14975 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14976 16, 64, 32, 64, 32, 128, -1);
14977 if (align_good
== FAIL
)
14981 unsigned alignbits
= 0;
14984 case 8: alignbits
= 0x1; break;
14985 case 16: alignbits
= 0x1; break;
14986 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14989 inst
.instruction
|= alignbits
<< 4;
14996 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14997 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14998 inst
.instruction
|= 1 << (4 + logsize
);
15000 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15001 inst
.instruction
|= logsize
<< 10;
15004 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15007 do_neon_ld_dup (void)
15009 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15010 int align_good
, do_align
= 0;
15012 if (et
.type
== NT_invtype
)
15015 switch ((inst
.instruction
>> 8) & 3)
15017 case 0: /* VLD1. */
15018 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15019 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15020 &do_align
, 16, 16, 32, 32, -1);
15021 if (align_good
== FAIL
)
15023 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15026 case 2: inst
.instruction
|= 1 << 5; break;
15027 default: first_error (_("bad list length")); return;
15029 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15032 case 1: /* VLD2. */
15033 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15034 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15035 if (align_good
== FAIL
)
15037 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15038 _("bad list length"));
15039 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15040 inst
.instruction
|= 1 << 5;
15041 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15044 case 2: /* VLD3. */
15045 constraint (inst
.operands
[1].immisalign
,
15046 _("can't use alignment with this instruction"));
15047 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15048 _("bad list length"));
15049 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15050 inst
.instruction
|= 1 << 5;
15051 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15054 case 3: /* VLD4. */
15056 int align
= inst
.operands
[1].imm
>> 8;
15057 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15058 16, 64, 32, 64, 32, 128, -1);
15059 if (align_good
== FAIL
)
15061 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15062 _("bad list length"));
15063 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15064 inst
.instruction
|= 1 << 5;
15065 if (et
.size
== 32 && align
== 128)
15066 inst
.instruction
|= 0x3 << 6;
15068 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15075 inst
.instruction
|= do_align
<< 4;
15078 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15079 apart from bits [11:4]. */
15082 do_neon_ldx_stx (void)
15084 if (inst
.operands
[1].isreg
)
15085 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15087 switch (NEON_LANE (inst
.operands
[0].imm
))
15089 case NEON_INTERLEAVE_LANES
:
15090 NEON_ENCODE (INTERLV
, inst
);
15091 do_neon_ld_st_interleave ();
15094 case NEON_ALL_LANES
:
15095 NEON_ENCODE (DUP
, inst
);
15100 NEON_ENCODE (LANE
, inst
);
15101 do_neon_ld_st_lane ();
15104 /* L bit comes from bit mask. */
15105 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15106 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15107 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15109 if (inst
.operands
[1].postind
)
15111 int postreg
= inst
.operands
[1].imm
& 0xf;
15112 constraint (!inst
.operands
[1].immisreg
,
15113 _("post-index must be a register"));
15114 constraint (postreg
== 0xd || postreg
== 0xf,
15115 _("bad register for post-index"));
15116 inst
.instruction
|= postreg
;
15118 else if (inst
.operands
[1].writeback
)
15120 inst
.instruction
|= 0xd;
15123 inst
.instruction
|= 0xf;
15126 inst
.instruction
|= 0xf9000000;
15128 inst
.instruction
|= 0xf4000000;
15131 /* Overall per-instruction processing. */
15133 /* We need to be able to fix up arbitrary expressions in some statements.
15134 This is so that we can handle symbols that are an arbitrary distance from
15135 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15136 which returns part of an address in a form which will be valid for
15137 a data instruction. We do this by pushing the expression into a symbol
15138 in the expr_section, and creating a fix for that. */
15141 fix_new_arm (fragS
* frag
,
15156 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15157 (enum bfd_reloc_code_real
) reloc
);
15161 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15162 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15166 /* Mark whether the fix is to a THUMB instruction, or an ARM
15168 new_fix
->tc_fix_data
= thumb_mode
;
15171 /* Create a frg for an instruction requiring relaxation. */
15173 output_relax_insn (void)
15179 /* The size of the instruction is unknown, so tie the debug info to the
15180 start of the instruction. */
15181 dwarf2_emit_insn (0);
15183 switch (inst
.reloc
.exp
.X_op
)
15186 sym
= inst
.reloc
.exp
.X_add_symbol
;
15187 offset
= inst
.reloc
.exp
.X_add_number
;
15191 offset
= inst
.reloc
.exp
.X_add_number
;
15194 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15198 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15199 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15200 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15203 /* Write a 32-bit thumb instruction to buf. */
15205 put_thumb32_insn (char * buf
, unsigned long insn
)
15207 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15208 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15212 output_inst (const char * str
)
15218 as_bad ("%s -- `%s'", inst
.error
, str
);
15223 output_relax_insn ();
15226 if (inst
.size
== 0)
15229 to
= frag_more (inst
.size
);
15230 /* PR 9814: Record the thumb mode into the current frag so that we know
15231 what type of NOP padding to use, if necessary. We override any previous
15232 setting so that if the mode has changed then the NOPS that we use will
15233 match the encoding of the last instruction in the frag. */
15234 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15236 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15238 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15239 put_thumb32_insn (to
, inst
.instruction
);
15241 else if (inst
.size
> INSN_SIZE
)
15243 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15244 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15245 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15248 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15250 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15251 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15252 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15255 dwarf2_emit_insn (inst
.size
);
15259 output_it_inst (int cond
, int mask
, char * to
)
15261 unsigned long instruction
= 0xbf00;
15264 instruction
|= mask
;
15265 instruction
|= cond
<< 4;
15269 to
= frag_more (2);
15271 dwarf2_emit_insn (2);
15275 md_number_to_chars (to
, instruction
, 2);
15280 /* Tag values used in struct asm_opcode's tag field. */
15283 OT_unconditional
, /* Instruction cannot be conditionalized.
15284 The ARM condition field is still 0xE. */
15285 OT_unconditionalF
, /* Instruction cannot be conditionalized
15286 and carries 0xF in its ARM condition field. */
15287 OT_csuffix
, /* Instruction takes a conditional suffix. */
15288 OT_csuffixF
, /* Some forms of the instruction take a conditional
15289 suffix, others place 0xF where the condition field
15291 OT_cinfix3
, /* Instruction takes a conditional infix,
15292 beginning at character index 3. (In
15293 unified mode, it becomes a suffix.) */
15294 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15295 tsts, cmps, cmns, and teqs. */
15296 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15297 character index 3, even in unified mode. Used for
15298 legacy instructions where suffix and infix forms
15299 may be ambiguous. */
15300 OT_csuf_or_in3
, /* Instruction takes either a conditional
15301 suffix or an infix at character index 3. */
15302 OT_odd_infix_unc
, /* This is the unconditional variant of an
15303 instruction that takes a conditional infix
15304 at an unusual position. In unified mode,
15305 this variant will accept a suffix. */
15306 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15307 are the conditional variants of instructions that
15308 take conditional infixes in unusual positions.
15309 The infix appears at character index
15310 (tag - OT_odd_infix_0). These are not accepted
15311 in unified mode. */
15314 /* Subroutine of md_assemble, responsible for looking up the primary
15315 opcode from the mnemonic the user wrote. STR points to the
15316 beginning of the mnemonic.
15318 This is not simply a hash table lookup, because of conditional
15319 variants. Most instructions have conditional variants, which are
15320 expressed with a _conditional affix_ to the mnemonic. If we were
15321 to encode each conditional variant as a literal string in the opcode
15322 table, it would have approximately 20,000 entries.
15324 Most mnemonics take this affix as a suffix, and in unified syntax,
15325 'most' is upgraded to 'all'. However, in the divided syntax, some
15326 instructions take the affix as an infix, notably the s-variants of
15327 the arithmetic instructions. Of those instructions, all but six
15328 have the infix appear after the third character of the mnemonic.
15330 Accordingly, the algorithm for looking up primary opcodes given
15333 1. Look up the identifier in the opcode table.
15334 If we find a match, go to step U.
15336 2. Look up the last two characters of the identifier in the
15337 conditions table. If we find a match, look up the first N-2
15338 characters of the identifier in the opcode table. If we
15339 find a match, go to step CE.
15341 3. Look up the fourth and fifth characters of the identifier in
15342 the conditions table. If we find a match, extract those
15343 characters from the identifier, and look up the remaining
15344 characters in the opcode table. If we find a match, go
15349 U. Examine the tag field of the opcode structure, in case this is
15350 one of the six instructions with its conditional infix in an
15351 unusual place. If it is, the tag tells us where to find the
15352 infix; look it up in the conditions table and set inst.cond
15353 accordingly. Otherwise, this is an unconditional instruction.
15354 Again set inst.cond accordingly. Return the opcode structure.
15356 CE. Examine the tag field to make sure this is an instruction that
15357 should receive a conditional suffix. If it is not, fail.
15358 Otherwise, set inst.cond from the suffix we already looked up,
15359 and return the opcode structure.
15361 CM. Examine the tag field to make sure this is an instruction that
15362 should receive a conditional infix after the third character.
15363 If it is not, fail. Otherwise, undo the edits to the current
15364 line of input and proceed as for case CE. */
15366 static const struct asm_opcode
*
15367 opcode_lookup (char **str
)
15371 const struct asm_opcode
*opcode
;
15372 const struct asm_cond
*cond
;
15375 /* Scan up to the end of the mnemonic, which must end in white space,
15376 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15377 for (base
= end
= *str
; *end
!= '\0'; end
++)
15378 if (*end
== ' ' || *end
== '.')
15384 /* Handle a possible width suffix and/or Neon type suffix. */
15389 /* The .w and .n suffixes are only valid if the unified syntax is in
15391 if (unified_syntax
&& end
[1] == 'w')
15393 else if (unified_syntax
&& end
[1] == 'n')
15398 inst
.vectype
.elems
= 0;
15400 *str
= end
+ offset
;
15402 if (end
[offset
] == '.')
15404 /* See if we have a Neon type suffix (possible in either unified or
15405 non-unified ARM syntax mode). */
15406 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15409 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15415 /* Look for unaffixed or special-case affixed mnemonic. */
15416 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15421 if (opcode
->tag
< OT_odd_infix_0
)
15423 inst
.cond
= COND_ALWAYS
;
15427 if (warn_on_deprecated
&& unified_syntax
)
15428 as_warn (_("conditional infixes are deprecated in unified syntax"));
15429 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15430 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15433 inst
.cond
= cond
->value
;
15437 /* Cannot have a conditional suffix on a mnemonic of less than two
15439 if (end
- base
< 3)
15442 /* Look for suffixed mnemonic. */
15444 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15445 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15447 if (opcode
&& cond
)
15450 switch (opcode
->tag
)
15452 case OT_cinfix3_legacy
:
15453 /* Ignore conditional suffixes matched on infix only mnemonics. */
15457 case OT_cinfix3_deprecated
:
15458 case OT_odd_infix_unc
:
15459 if (!unified_syntax
)
15461 /* else fall through */
15465 case OT_csuf_or_in3
:
15466 inst
.cond
= cond
->value
;
15469 case OT_unconditional
:
15470 case OT_unconditionalF
:
15472 inst
.cond
= cond
->value
;
15475 /* Delayed diagnostic. */
15476 inst
.error
= BAD_COND
;
15477 inst
.cond
= COND_ALWAYS
;
15486 /* Cannot have a usual-position infix on a mnemonic of less than
15487 six characters (five would be a suffix). */
15488 if (end
- base
< 6)
15491 /* Look for infixed mnemonic in the usual position. */
15493 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15497 memcpy (save
, affix
, 2);
15498 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15499 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15501 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15502 memcpy (affix
, save
, 2);
15505 && (opcode
->tag
== OT_cinfix3
15506 || opcode
->tag
== OT_cinfix3_deprecated
15507 || opcode
->tag
== OT_csuf_or_in3
15508 || opcode
->tag
== OT_cinfix3_legacy
))
15511 if (warn_on_deprecated
&& unified_syntax
15512 && (opcode
->tag
== OT_cinfix3
15513 || opcode
->tag
== OT_cinfix3_deprecated
))
15514 as_warn (_("conditional infixes are deprecated in unified syntax"));
15516 inst
.cond
= cond
->value
;
15523 /* This function generates an initial IT instruction, leaving its block
15524 virtually open for the new instructions. Eventually,
15525 the mask will be updated by now_it_add_mask () each time
15526 a new instruction needs to be included in the IT block.
15527 Finally, the block is closed with close_automatic_it_block ().
15528 The block closure can be requested either from md_assemble (),
15529 a tencode (), or due to a label hook. */
15532 new_automatic_it_block (int cond
)
15534 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15535 now_it
.mask
= 0x18;
15537 now_it
.block_length
= 1;
15538 mapping_state (MAP_THUMB
);
15539 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15542 /* Close an automatic IT block.
15543 See comments in new_automatic_it_block (). */
15546 close_automatic_it_block (void)
15548 now_it
.mask
= 0x10;
15549 now_it
.block_length
= 0;
15552 /* Update the mask of the current automatically-generated IT
15553 instruction. See comments in new_automatic_it_block (). */
15556 now_it_add_mask (int cond
)
15558 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15559 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15560 | ((bitvalue) << (nbit)))
15561 const int resulting_bit
= (cond
& 1);
15563 now_it
.mask
&= 0xf;
15564 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15566 (5 - now_it
.block_length
));
15567 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15569 ((5 - now_it
.block_length
) - 1) );
15570 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15573 #undef SET_BIT_VALUE
15576 /* The IT blocks handling machinery is accessed through the these functions:
15577 it_fsm_pre_encode () from md_assemble ()
15578 set_it_insn_type () optional, from the tencode functions
15579 set_it_insn_type_last () ditto
15580 in_it_block () ditto
15581 it_fsm_post_encode () from md_assemble ()
15582 force_automatic_it_block_close () from label habdling functions
15585 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15586 initializing the IT insn type with a generic initial value depending
15587 on the inst.condition.
15588 2) During the tencode function, two things may happen:
15589 a) The tencode function overrides the IT insn type by
15590 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15591 b) The tencode function queries the IT block state by
15592 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15594 Both set_it_insn_type and in_it_block run the internal FSM state
15595 handling function (handle_it_state), because: a) setting the IT insn
15596 type may incur in an invalid state (exiting the function),
15597 and b) querying the state requires the FSM to be updated.
15598 Specifically we want to avoid creating an IT block for conditional
15599 branches, so it_fsm_pre_encode is actually a guess and we can't
15600 determine whether an IT block is required until the tencode () routine
15601 has decided what type of instruction this actually it.
15602 Because of this, if set_it_insn_type and in_it_block have to be used,
15603 set_it_insn_type has to be called first.
15605 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15606 determines the insn IT type depending on the inst.cond code.
15607 When a tencode () routine encodes an instruction that can be
15608 either outside an IT block, or, in the case of being inside, has to be
15609 the last one, set_it_insn_type_last () will determine the proper
15610 IT instruction type based on the inst.cond code. Otherwise,
15611 set_it_insn_type can be called for overriding that logic or
15612 for covering other cases.
15614 Calling handle_it_state () may not transition the IT block state to
15615 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15616 still queried. Instead, if the FSM determines that the state should
15617 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15618 after the tencode () function: that's what it_fsm_post_encode () does.
15620 Since in_it_block () calls the state handling function to get an
15621 updated state, an error may occur (due to invalid insns combination).
15622 In that case, inst.error is set.
15623 Therefore, inst.error has to be checked after the execution of
15624 the tencode () routine.
15626 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15627 any pending state change (if any) that didn't take place in
15628 handle_it_state () as explained above. */
15631 it_fsm_pre_encode (void)
15633 if (inst
.cond
!= COND_ALWAYS
)
15634 inst
.it_insn_type
= INSIDE_IT_INSN
;
15636 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15638 now_it
.state_handled
= 0;
15641 /* IT state FSM handling function. */
15644 handle_it_state (void)
15646 now_it
.state_handled
= 1;
15648 switch (now_it
.state
)
15650 case OUTSIDE_IT_BLOCK
:
15651 switch (inst
.it_insn_type
)
15653 case OUTSIDE_IT_INSN
:
15656 case INSIDE_IT_INSN
:
15657 case INSIDE_IT_LAST_INSN
:
15658 if (thumb_mode
== 0)
15661 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15662 as_tsktsk (_("Warning: conditional outside an IT block"\
15667 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15668 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15670 /* Automatically generate the IT instruction. */
15671 new_automatic_it_block (inst
.cond
);
15672 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15673 close_automatic_it_block ();
15677 inst
.error
= BAD_OUT_IT
;
15683 case IF_INSIDE_IT_LAST_INSN
:
15684 case NEUTRAL_IT_INSN
:
15688 now_it
.state
= MANUAL_IT_BLOCK
;
15689 now_it
.block_length
= 0;
15694 case AUTOMATIC_IT_BLOCK
:
15695 /* Three things may happen now:
15696 a) We should increment current it block size;
15697 b) We should close current it block (closing insn or 4 insns);
15698 c) We should close current it block and start a new one (due
15699 to incompatible conditions or
15700 4 insns-length block reached). */
15702 switch (inst
.it_insn_type
)
15704 case OUTSIDE_IT_INSN
:
15705 /* The closure of the block shall happen immediatelly,
15706 so any in_it_block () call reports the block as closed. */
15707 force_automatic_it_block_close ();
15710 case INSIDE_IT_INSN
:
15711 case INSIDE_IT_LAST_INSN
:
15712 case IF_INSIDE_IT_LAST_INSN
:
15713 now_it
.block_length
++;
15715 if (now_it
.block_length
> 4
15716 || !now_it_compatible (inst
.cond
))
15718 force_automatic_it_block_close ();
15719 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15720 new_automatic_it_block (inst
.cond
);
15724 now_it_add_mask (inst
.cond
);
15727 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15728 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15729 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15730 close_automatic_it_block ();
15733 case NEUTRAL_IT_INSN
:
15734 now_it
.block_length
++;
15736 if (now_it
.block_length
> 4)
15737 force_automatic_it_block_close ();
15739 now_it_add_mask (now_it
.cc
& 1);
15743 close_automatic_it_block ();
15744 now_it
.state
= MANUAL_IT_BLOCK
;
15749 case MANUAL_IT_BLOCK
:
15751 /* Check conditional suffixes. */
15752 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15755 now_it
.mask
&= 0x1f;
15756 is_last
= (now_it
.mask
== 0x10);
15758 switch (inst
.it_insn_type
)
15760 case OUTSIDE_IT_INSN
:
15761 inst
.error
= BAD_NOT_IT
;
15764 case INSIDE_IT_INSN
:
15765 if (cond
!= inst
.cond
)
15767 inst
.error
= BAD_IT_COND
;
15772 case INSIDE_IT_LAST_INSN
:
15773 case IF_INSIDE_IT_LAST_INSN
:
15774 if (cond
!= inst
.cond
)
15776 inst
.error
= BAD_IT_COND
;
15781 inst
.error
= BAD_BRANCH
;
15786 case NEUTRAL_IT_INSN
:
15787 /* The BKPT instruction is unconditional even in an IT block. */
15791 inst
.error
= BAD_IT_IT
;
15802 it_fsm_post_encode (void)
15806 if (!now_it
.state_handled
)
15807 handle_it_state ();
15809 is_last
= (now_it
.mask
== 0x10);
15812 now_it
.state
= OUTSIDE_IT_BLOCK
;
15818 force_automatic_it_block_close (void)
15820 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15822 close_automatic_it_block ();
15823 now_it
.state
= OUTSIDE_IT_BLOCK
;
15831 if (!now_it
.state_handled
)
15832 handle_it_state ();
15834 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15838 md_assemble (char *str
)
15841 const struct asm_opcode
* opcode
;
15843 /* Align the previous label if needed. */
15844 if (last_label_seen
!= NULL
)
15846 symbol_set_frag (last_label_seen
, frag_now
);
15847 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15848 S_SET_SEGMENT (last_label_seen
, now_seg
);
15851 memset (&inst
, '\0', sizeof (inst
));
15852 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15854 opcode
= opcode_lookup (&p
);
15857 /* It wasn't an instruction, but it might be a register alias of
15858 the form alias .req reg, or a Neon .dn/.qn directive. */
15859 if (! create_register_alias (str
, p
)
15860 && ! create_neon_reg_alias (str
, p
))
15861 as_bad (_("bad instruction `%s'"), str
);
15866 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15867 as_warn (_("s suffix on comparison instruction is deprecated"));
15869 /* The value which unconditional instructions should have in place of the
15870 condition field. */
15871 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15875 arm_feature_set variant
;
15877 variant
= cpu_variant
;
15878 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15879 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15880 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15881 /* Check that this instruction is supported for this CPU. */
15882 if (!opcode
->tvariant
15883 || (thumb_mode
== 1
15884 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15886 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15889 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15890 && opcode
->tencode
!= do_t_branch
)
15892 as_bad (_("Thumb does not support conditional execution"));
15896 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15898 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15899 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15900 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15902 /* Two things are addressed here.
15903 1) Implicit require narrow instructions on Thumb-1.
15904 This avoids relaxation accidentally introducing Thumb-2
15906 2) Reject wide instructions in non Thumb-2 cores. */
15907 if (inst
.size_req
== 0)
15909 else if (inst
.size_req
== 4)
15911 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
15917 inst
.instruction
= opcode
->tvalue
;
15919 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15921 /* Prepare the it_insn_type for those encodings that don't set
15923 it_fsm_pre_encode ();
15925 opcode
->tencode ();
15927 it_fsm_post_encode ();
15930 if (!(inst
.error
|| inst
.relax
))
15932 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15933 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15934 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15936 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15941 /* Something has gone badly wrong if we try to relax a fixed size
15943 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15945 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15946 *opcode
->tvariant
);
15947 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15948 set those bits when Thumb-2 32-bit instructions are seen. ie.
15949 anything other than bl/blx and v6-M instructions.
15950 This is overly pessimistic for relaxable instructions. */
15951 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15953 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15954 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15955 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15958 check_neon_suffixes
;
15962 mapping_state (MAP_THUMB
);
15965 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15969 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15970 is_bx
= (opcode
->aencode
== do_bx
);
15972 /* Check that this instruction is supported for this CPU. */
15973 if (!(is_bx
&& fix_v4bx
)
15974 && !(opcode
->avariant
&&
15975 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15977 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
15982 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15986 inst
.instruction
= opcode
->avalue
;
15987 if (opcode
->tag
== OT_unconditionalF
)
15988 inst
.instruction
|= 0xF << 28;
15990 inst
.instruction
|= inst
.cond
<< 28;
15991 inst
.size
= INSN_SIZE
;
15992 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
15994 it_fsm_pre_encode ();
15995 opcode
->aencode ();
15996 it_fsm_post_encode ();
15998 /* Arm mode bx is marked as both v4T and v5 because it's still required
15999 on a hypothetical non-thumb v5 core. */
16001 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16003 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16004 *opcode
->avariant
);
16006 check_neon_suffixes
;
16010 mapping_state (MAP_ARM
);
16015 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16023 check_it_blocks_finished (void)
16028 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16029 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16030 == MANUAL_IT_BLOCK
)
16032 as_warn (_("section '%s' finished with an open IT block."),
16036 if (now_it
.state
== MANUAL_IT_BLOCK
)
16037 as_warn (_("file finished with an open IT block."));
16041 /* Various frobbings of labels and their addresses. */
16044 arm_start_line_hook (void)
16046 last_label_seen
= NULL
;
16050 arm_frob_label (symbolS
* sym
)
16052 last_label_seen
= sym
;
16054 ARM_SET_THUMB (sym
, thumb_mode
);
16056 #if defined OBJ_COFF || defined OBJ_ELF
16057 ARM_SET_INTERWORK (sym
, support_interwork
);
16060 force_automatic_it_block_close ();
16062 /* Note - do not allow local symbols (.Lxxx) to be labelled
16063 as Thumb functions. This is because these labels, whilst
16064 they exist inside Thumb code, are not the entry points for
16065 possible ARM->Thumb calls. Also, these labels can be used
16066 as part of a computed goto or switch statement. eg gcc
16067 can generate code that looks like this:
16069 ldr r2, [pc, .Laaa]
16079 The first instruction loads the address of the jump table.
16080 The second instruction converts a table index into a byte offset.
16081 The third instruction gets the jump address out of the table.
16082 The fourth instruction performs the jump.
16084 If the address stored at .Laaa is that of a symbol which has the
16085 Thumb_Func bit set, then the linker will arrange for this address
16086 to have the bottom bit set, which in turn would mean that the
16087 address computation performed by the third instruction would end
16088 up with the bottom bit set. Since the ARM is capable of unaligned
16089 word loads, the instruction would then load the incorrect address
16090 out of the jump table, and chaos would ensue. */
16091 if (label_is_thumb_function_name
16092 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16093 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16095 /* When the address of a Thumb function is taken the bottom
16096 bit of that address should be set. This will allow
16097 interworking between Arm and Thumb functions to work
16100 THUMB_SET_FUNC (sym
, 1);
16102 label_is_thumb_function_name
= FALSE
;
16105 dwarf2_emit_label (sym
);
16109 arm_data_in_code (void)
16111 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16113 *input_line_pointer
= '/';
16114 input_line_pointer
+= 5;
16115 *input_line_pointer
= 0;
16123 arm_canonicalize_symbol_name (char * name
)
16127 if (thumb_mode
&& (len
= strlen (name
)) > 5
16128 && streq (name
+ len
- 5, "/data"))
16129 *(name
+ len
- 5) = 0;
16134 /* Table of all register names defined by default. The user can
16135 define additional names with .req. Note that all register names
16136 should appear in both upper and lowercase variants. Some registers
16137 also have mixed-case names. */
16139 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16140 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16141 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16142 #define REGSET(p,t) \
16143 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16144 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16145 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16146 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16147 #define REGSETH(p,t) \
16148 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16149 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16150 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16151 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16152 #define REGSET2(p,t) \
16153 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16154 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16155 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16156 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16158 static const struct reg_entry reg_names
[] =
16160 /* ARM integer registers. */
16161 REGSET(r
, RN
), REGSET(R
, RN
),
16163 /* ATPCS synonyms. */
16164 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16165 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16166 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16168 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16169 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16170 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16172 /* Well-known aliases. */
16173 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16174 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16176 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16177 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16179 /* Coprocessor numbers. */
16180 REGSET(p
, CP
), REGSET(P
, CP
),
16182 /* Coprocessor register numbers. The "cr" variants are for backward
16184 REGSET(c
, CN
), REGSET(C
, CN
),
16185 REGSET(cr
, CN
), REGSET(CR
, CN
),
16187 /* FPA registers. */
16188 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16189 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16191 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16192 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16194 /* VFP SP registers. */
16195 REGSET(s
,VFS
), REGSET(S
,VFS
),
16196 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16198 /* VFP DP Registers. */
16199 REGSET(d
,VFD
), REGSET(D
,VFD
),
16200 /* Extra Neon DP registers. */
16201 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16203 /* Neon QP registers. */
16204 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16206 /* VFP control registers. */
16207 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16208 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16209 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16210 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16211 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16212 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16214 /* Maverick DSP coprocessor registers. */
16215 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16216 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16218 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16219 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16220 REGDEF(dspsc
,0,DSPSC
),
16222 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16223 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16224 REGDEF(DSPSC
,0,DSPSC
),
16226 /* iWMMXt data registers - p0, c0-15. */
16227 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16229 /* iWMMXt control registers - p1, c0-3. */
16230 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16231 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16232 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16233 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16235 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16236 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16237 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16238 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16239 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16241 /* XScale accumulator registers. */
16242 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16248 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16249 within psr_required_here. */
16250 static const struct asm_psr psrs
[] =
16252 /* Backward compatibility notation. Note that "all" is no longer
16253 truly all possible PSR bits. */
16254 {"all", PSR_c
| PSR_f
},
16258 /* Individual flags. */
16265 /* Combinations of flags. */
16266 {"fs", PSR_f
| PSR_s
},
16267 {"fx", PSR_f
| PSR_x
},
16268 {"fc", PSR_f
| PSR_c
},
16269 {"sf", PSR_s
| PSR_f
},
16270 {"sx", PSR_s
| PSR_x
},
16271 {"sc", PSR_s
| PSR_c
},
16272 {"xf", PSR_x
| PSR_f
},
16273 {"xs", PSR_x
| PSR_s
},
16274 {"xc", PSR_x
| PSR_c
},
16275 {"cf", PSR_c
| PSR_f
},
16276 {"cs", PSR_c
| PSR_s
},
16277 {"cx", PSR_c
| PSR_x
},
16278 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16279 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16280 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16281 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16282 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16283 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16284 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16285 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16286 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16287 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16288 {"scf", PSR_s
| PSR_c
| PSR_f
},
16289 {"scx", PSR_s
| PSR_c
| PSR_x
},
16290 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16291 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16292 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16293 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16294 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16295 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16296 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16297 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16298 {"csf", PSR_c
| PSR_s
| PSR_f
},
16299 {"csx", PSR_c
| PSR_s
| PSR_x
},
16300 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16301 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16302 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16303 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16304 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16305 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16306 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16307 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16308 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16309 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16310 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16311 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16312 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16313 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16314 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16315 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16316 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16317 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16318 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16319 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16320 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16321 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16322 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16323 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16324 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16325 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16329 {"nzcvqg", PSR_s
| PSR_f
}
16332 /* Table of V7M psr names. */
16333 static const struct asm_psr v7m_psrs
[] =
16335 {"apsr", 0 }, {"APSR", 0 },
16336 {"iapsr", 1 }, {"IAPSR", 1 },
16337 {"eapsr", 2 }, {"EAPSR", 2 },
16338 {"psr", 3 }, {"PSR", 3 },
16339 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16340 {"ipsr", 5 }, {"IPSR", 5 },
16341 {"epsr", 6 }, {"EPSR", 6 },
16342 {"iepsr", 7 }, {"IEPSR", 7 },
16343 {"msp", 8 }, {"MSP", 8 },
16344 {"psp", 9 }, {"PSP", 9 },
16345 {"primask", 16}, {"PRIMASK", 16},
16346 {"basepri", 17}, {"BASEPRI", 17},
16347 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16348 {"faultmask", 19}, {"FAULTMASK", 19},
16349 {"control", 20}, {"CONTROL", 20}
16352 /* Table of all shift-in-operand names. */
16353 static const struct asm_shift_name shift_names
[] =
16355 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16356 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16357 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16358 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16359 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16360 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16363 /* Table of all explicit relocation names. */
16365 static struct reloc_entry reloc_names
[] =
16367 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16368 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16369 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16370 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16371 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16372 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16373 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16374 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16375 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16376 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16377 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16378 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16382 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16383 static const struct asm_cond conds
[] =
16387 {"cs", 0x2}, {"hs", 0x2},
16388 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16402 static struct asm_barrier_opt barrier_opt_names
[] =
16404 { "sy", 0xf }, { "SY", 0xf },
16405 { "un", 0x7 }, { "UN", 0x7 },
16406 { "st", 0xe }, { "ST", 0xe },
16407 { "unst", 0x6 }, { "UNST", 0x6 },
16408 { "ish", 0xb }, { "ISH", 0xb },
16409 { "sh", 0xb }, { "SH", 0xb },
16410 { "ishst", 0xa }, { "ISHST", 0xa },
16411 { "shst", 0xa }, { "SHST", 0xa },
16412 { "nsh", 0x7 }, { "NSH", 0x7 },
16413 { "nshst", 0x6 }, { "NSHST", 0x6 },
16414 { "osh", 0x3 }, { "OSH", 0x3 },
16415 { "oshst", 0x2 }, { "OSHST", 0x2 }
16418 /* Table of ARM-format instructions. */
16420 /* Macros for gluing together operand strings. N.B. In all cases
16421 other than OPS0, the trailing OP_stop comes from default
16422 zero-initialization of the unspecified elements of the array. */
16423 #define OPS0() { OP_stop, }
16424 #define OPS1(a) { OP_##a, }
16425 #define OPS2(a,b) { OP_##a,OP_##b, }
16426 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16427 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16428 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16429 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16431 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16432 This is useful when mixing operands for ARM and THUMB, i.e. using the
16433 MIX_ARM_THUMB_OPERANDS macro.
16434 In order to use these macros, prefix the number of operands with _
16436 #define OPS_1(a) { a, }
16437 #define OPS_2(a,b) { a,b, }
16438 #define OPS_3(a,b,c) { a,b,c, }
16439 #define OPS_4(a,b,c,d) { a,b,c,d, }
16440 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16441 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16443 /* These macros abstract out the exact format of the mnemonic table and
16444 save some repeated characters. */
16446 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16447 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16448 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16449 THUMB_VARIANT, do_##ae, do_##te }
16451 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16452 a T_MNEM_xyz enumerator. */
16453 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16454 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16455 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16456 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16458 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16459 infix after the third character. */
16460 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16461 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16462 THUMB_VARIANT, do_##ae, do_##te }
16463 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16464 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16465 THUMB_VARIANT, do_##ae, do_##te }
16466 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16467 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16468 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16469 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16470 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16471 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16472 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16473 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16475 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16476 appear in the condition table. */
16477 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16478 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16479 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16481 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16482 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16483 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16484 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16485 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16486 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16487 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16488 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16489 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16490 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16491 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16492 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16493 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16494 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16495 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16496 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16497 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16498 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16499 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16500 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16502 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16503 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16504 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16505 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16507 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16508 field is still 0xE. Many of the Thumb variants can be executed
16509 conditionally, so this is checked separately. */
16510 #define TUE(mnem, op, top, nops, ops, ae, te) \
16511 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16512 THUMB_VARIANT, do_##ae, do_##te }
16514 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16515 condition code field. */
16516 #define TUF(mnem, op, top, nops, ops, ae, te) \
16517 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16518 THUMB_VARIANT, do_##ae, do_##te }
16520 /* ARM-only variants of all the above. */
16521 #define CE(mnem, op, nops, ops, ae) \
16522 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16524 #define C3(mnem, op, nops, ops, ae) \
16525 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16527 /* Legacy mnemonics that always have conditional infix after the third
16529 #define CL(mnem, op, nops, ops, ae) \
16530 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16531 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16533 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16534 #define cCE(mnem, op, nops, ops, ae) \
16535 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16537 /* Legacy coprocessor instructions where conditional infix and conditional
16538 suffix are ambiguous. For consistency this includes all FPA instructions,
16539 not just the potentially ambiguous ones. */
16540 #define cCL(mnem, op, nops, ops, ae) \
16541 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16542 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16544 /* Coprocessor, takes either a suffix or a position-3 infix
16545 (for an FPA corner case). */
16546 #define C3E(mnem, op, nops, ops, ae) \
16547 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16548 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16550 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16551 { m1 #m2 m3, OPS##nops ops, \
16552 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16553 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16555 #define CM(m1, m2, op, nops, ops, ae) \
16556 xCM_ (m1, , m2, op, nops, ops, ae), \
16557 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16558 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16559 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16560 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16561 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16562 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16563 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16564 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16565 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16566 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16567 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16568 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16569 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16570 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16571 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16572 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16573 xCM_ (m1, le, m2, op, nops, ops, ae), \
16574 xCM_ (m1, al, m2, op, nops, ops, ae)
16576 #define UE(mnem, op, nops, ops, ae) \
16577 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16579 #define UF(mnem, op, nops, ops, ae) \
16580 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16582 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16583 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16584 use the same encoding function for each. */
16585 #define NUF(mnem, op, nops, ops, enc) \
16586 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16587 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16589 /* Neon data processing, version which indirects through neon_enc_tab for
16590 the various overloaded versions of opcodes. */
16591 #define nUF(mnem, op, nops, ops, enc) \
16592 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16593 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16595 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16597 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16598 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16599 THUMB_VARIANT, do_##enc, do_##enc }
16601 #define NCE(mnem, op, nops, ops, enc) \
16602 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16604 #define NCEF(mnem, op, nops, ops, enc) \
16605 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16607 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16608 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16609 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16610 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16612 #define nCE(mnem, op, nops, ops, enc) \
16613 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16615 #define nCEF(mnem, op, nops, ops, enc) \
16616 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16620 static const struct asm_opcode insns
[] =
16622 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16623 #define THUMB_VARIANT &arm_ext_v4t
16624 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16625 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16626 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16627 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16628 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16629 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16630 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16631 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16632 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16633 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16634 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16635 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16636 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16637 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16638 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16639 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16641 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16642 for setting PSR flag bits. They are obsolete in V6 and do not
16643 have Thumb equivalents. */
16644 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16645 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16646 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16647 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16648 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16649 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16650 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16651 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16652 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16654 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16655 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16656 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16657 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16659 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16660 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16661 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16663 OP_ADDRGLDR
),ldst
, t_ldst
),
16664 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16666 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16667 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16668 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16669 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16670 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16671 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16673 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16674 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16675 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16676 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16679 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16680 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16681 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16683 /* Thumb-compatibility pseudo ops. */
16684 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16685 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16686 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16687 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16688 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16689 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16690 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16691 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16692 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16693 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16694 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16695 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16697 /* These may simplify to neg. */
16698 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16699 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16701 #undef THUMB_VARIANT
16702 #define THUMB_VARIANT & arm_ext_v6
16704 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16706 /* V1 instructions with no Thumb analogue prior to V6T2. */
16707 #undef THUMB_VARIANT
16708 #define THUMB_VARIANT & arm_ext_v6t2
16710 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16711 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16712 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16714 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16715 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16716 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16717 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16719 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16720 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16722 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16723 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16725 /* V1 instructions with no Thumb analogue at all. */
16726 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16727 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16729 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16730 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16731 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16732 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16733 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16734 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16735 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16736 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16739 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16740 #undef THUMB_VARIANT
16741 #define THUMB_VARIANT & arm_ext_v4t
16743 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16744 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16746 #undef THUMB_VARIANT
16747 #define THUMB_VARIANT & arm_ext_v6t2
16749 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16750 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16752 /* Generic coprocessor instructions. */
16753 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16754 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16755 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16756 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16757 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16758 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16759 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16762 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16764 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16765 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16768 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16769 #undef THUMB_VARIANT
16770 #define THUMB_VARIANT & arm_ext_msr
16772 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16773 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16776 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16777 #undef THUMB_VARIANT
16778 #define THUMB_VARIANT & arm_ext_v6t2
16780 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16781 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16782 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16783 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16784 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16785 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16786 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16787 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16790 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16791 #undef THUMB_VARIANT
16792 #define THUMB_VARIANT & arm_ext_v4t
16794 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16795 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16796 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16797 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16798 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16799 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16802 #define ARM_VARIANT & arm_ext_v4t_5
16804 /* ARM Architecture 4T. */
16805 /* Note: bx (and blx) are required on V5, even if the processor does
16806 not support Thumb. */
16807 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16810 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16811 #undef THUMB_VARIANT
16812 #define THUMB_VARIANT & arm_ext_v5t
16814 /* Note: blx has 2 variants; the .value coded here is for
16815 BLX(2). Only this variant has conditional execution. */
16816 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16817 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16819 #undef THUMB_VARIANT
16820 #define THUMB_VARIANT & arm_ext_v6t2
16822 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16823 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16824 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16825 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16826 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16827 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16828 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16829 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16832 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16833 #undef THUMB_VARIANT
16834 #define THUMB_VARIANT &arm_ext_v5exp
16836 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16837 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16838 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16839 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16841 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16842 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16844 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16845 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16846 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16847 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16849 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16850 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16851 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16852 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16854 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16855 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16857 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16858 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16859 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16860 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16863 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16864 #undef THUMB_VARIANT
16865 #define THUMB_VARIANT &arm_ext_v6t2
16867 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16868 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16870 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16871 ADDRGLDRS
), ldrd
, t_ldstd
),
16873 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16874 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16877 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16879 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16882 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16883 #undef THUMB_VARIANT
16884 #define THUMB_VARIANT & arm_ext_v6
16886 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16887 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16888 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16889 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16890 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16891 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16892 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16893 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16894 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16895 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16897 #undef THUMB_VARIANT
16898 #define THUMB_VARIANT & arm_ext_v6t2
16900 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16901 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16903 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16904 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16906 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16907 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16909 /* ARM V6 not included in V7M. */
16910 #undef THUMB_VARIANT
16911 #define THUMB_VARIANT & arm_ext_v6_notm
16912 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16913 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16914 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16915 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16916 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16917 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16918 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16919 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16920 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16921 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16922 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16923 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16925 /* ARM V6 not included in V7M (eg. integer SIMD). */
16926 #undef THUMB_VARIANT
16927 #define THUMB_VARIANT & arm_ext_v6_dsp
16928 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16929 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16930 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16931 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16932 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16933 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16934 /* Old name for QASX. */
16935 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16936 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16937 /* Old name for QSAX. */
16938 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16939 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16940 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16941 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16942 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16943 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16944 /* Old name for SASX. */
16945 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16946 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16947 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16948 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16949 /* Old name for SHASX. */
16950 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16951 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16952 /* Old name for SHSAX. */
16953 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16954 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16955 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16956 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16957 /* Old name for SSAX. */
16958 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16959 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16960 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16961 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16962 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16963 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16964 /* Old name for UASX. */
16965 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16966 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16967 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16968 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16969 /* Old name for UHASX. */
16970 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16971 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16972 /* Old name for UHSAX. */
16973 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16974 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16975 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16976 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16977 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16978 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16979 /* Old name for UQASX. */
16980 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16981 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16982 /* Old name for UQSAX. */
16983 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16984 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16985 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16986 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16987 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16988 /* Old name for USAX. */
16989 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16990 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16991 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16992 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16993 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16994 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16995 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16996 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16997 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16998 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16999 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17000 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17001 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17002 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17003 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17004 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17005 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17006 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17007 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17008 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17009 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17010 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17011 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17012 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17013 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17014 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17015 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17016 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17017 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17018 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17019 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17020 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17021 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17022 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17025 #define ARM_VARIANT & arm_ext_v6k
17026 #undef THUMB_VARIANT
17027 #define THUMB_VARIANT & arm_ext_v6k
17029 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17030 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17031 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17032 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17034 #undef THUMB_VARIANT
17035 #define THUMB_VARIANT & arm_ext_v6_notm
17036 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17038 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17039 RRnpcb
), strexd
, t_strexd
),
17041 #undef THUMB_VARIANT
17042 #define THUMB_VARIANT & arm_ext_v6t2
17043 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17045 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17047 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17049 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17051 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17054 #define ARM_VARIANT & arm_ext_sec
17055 #undef THUMB_VARIANT
17056 #define THUMB_VARIANT & arm_ext_sec
17058 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17061 #define ARM_VARIANT & arm_ext_v6t2
17062 #undef THUMB_VARIANT
17063 #define THUMB_VARIANT & arm_ext_v6t2
17065 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17066 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17067 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17068 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17070 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17071 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17072 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17073 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17075 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17076 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17077 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17078 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17080 /* Thumb-only instructions. */
17082 #define ARM_VARIANT NULL
17083 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17084 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17086 /* ARM does not really have an IT instruction, so always allow it.
17087 The opcode is copied from Thumb in order to allow warnings in
17088 -mimplicit-it=[never | arm] modes. */
17090 #define ARM_VARIANT & arm_ext_v1
17092 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17093 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17094 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17095 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17096 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17097 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17098 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17099 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17100 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17101 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17102 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17103 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17104 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17105 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17106 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17107 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17108 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17109 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17111 /* Thumb2 only instructions. */
17113 #define ARM_VARIANT NULL
17115 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17116 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17117 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17118 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17119 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17120 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17122 /* Thumb-2 hardware division instructions (R and M profiles only). */
17123 #undef THUMB_VARIANT
17124 #define THUMB_VARIANT & arm_ext_div
17126 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17127 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17129 /* ARM V6M/V7 instructions. */
17131 #define ARM_VARIANT & arm_ext_barrier
17132 #undef THUMB_VARIANT
17133 #define THUMB_VARIANT & arm_ext_barrier
17135 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17136 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17137 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17139 /* ARM V7 instructions. */
17141 #define ARM_VARIANT & arm_ext_v7
17142 #undef THUMB_VARIANT
17143 #define THUMB_VARIANT & arm_ext_v7
17145 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17146 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17149 #define ARM_VARIANT & arm_ext_mp
17150 #undef THUMB_VARIANT
17151 #define THUMB_VARIANT & arm_ext_mp
17153 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17156 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17158 cCE("wfs", e200110
, 1, (RR
), rd
),
17159 cCE("rfs", e300110
, 1, (RR
), rd
),
17160 cCE("wfc", e400110
, 1, (RR
), rd
),
17161 cCE("rfc", e500110
, 1, (RR
), rd
),
17163 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17164 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17165 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17166 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17168 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17169 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17170 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17171 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17173 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17174 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17175 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17176 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17177 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17178 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17179 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17180 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17181 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17182 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17183 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17184 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17186 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17187 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17188 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17189 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17190 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17191 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17192 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17193 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17194 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17195 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17196 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17197 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17199 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17200 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17201 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17202 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17203 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17204 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17205 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17206 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17207 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17208 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17209 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17210 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17212 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17213 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17214 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17215 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17216 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17217 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17218 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17219 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17220 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17221 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17222 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17223 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17225 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17226 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17227 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17228 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17229 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17230 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17231 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17232 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17233 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17234 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17235 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17236 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17238 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17239 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17240 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17241 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17242 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17243 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17244 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17245 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17246 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17247 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17248 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17249 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17251 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17252 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17253 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17254 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17255 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17256 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17257 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17258 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17259 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17260 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17261 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17262 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17264 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17265 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17266 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17267 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17268 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17269 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17270 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17271 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17272 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17273 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17274 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17275 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17277 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17278 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17279 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17280 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17281 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17282 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17283 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17284 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17285 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17286 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17287 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17288 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17290 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17291 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17292 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17293 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17294 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17295 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17296 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17297 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17298 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17299 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17300 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17301 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17303 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17304 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17305 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17306 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17307 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17308 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17309 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17310 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17311 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17312 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17313 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17314 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17316 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17317 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17318 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17319 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17320 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17321 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17322 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17323 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17324 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17325 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17326 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17327 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17329 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17330 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17331 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17332 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17333 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17334 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17335 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17336 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17337 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17338 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17339 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17340 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17342 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17343 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17344 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17345 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17346 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17347 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17348 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17349 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17350 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17351 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17352 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17353 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17355 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17356 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17357 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17358 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17359 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17360 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17361 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17362 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17363 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17364 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17365 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17366 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17368 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17369 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17370 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17371 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17372 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17373 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17374 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17375 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17376 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17377 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17378 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17379 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17381 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17382 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17383 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17384 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17385 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17386 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17387 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17388 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17389 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17390 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17391 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17392 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17394 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17395 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17396 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17397 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17398 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17399 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17400 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17401 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17402 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17403 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17404 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17405 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17407 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17408 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17409 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17410 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17411 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17412 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17413 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17414 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17415 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17416 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17417 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17418 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17420 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17421 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17422 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17423 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17424 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17425 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17426 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17427 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17428 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17429 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17430 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17431 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17433 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17434 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17435 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17436 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17437 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17438 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17439 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17440 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17441 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17442 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17443 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17444 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17446 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17447 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17448 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17449 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17450 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17451 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17452 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17453 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17454 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17455 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17456 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17457 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17459 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17460 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17461 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17462 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17463 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17464 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17465 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17466 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17467 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17468 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17469 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17470 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17472 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17473 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17474 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17475 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17476 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17477 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17478 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17479 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17480 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17481 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17482 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17483 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17485 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17486 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17487 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17488 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17489 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17490 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17491 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17492 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17493 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17494 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17495 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17496 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17498 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17499 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17500 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17501 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17502 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17503 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17504 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17505 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17506 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17507 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17508 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17509 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17511 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17512 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17513 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17514 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17515 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17516 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17517 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17518 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17519 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17520 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17521 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17522 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17524 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17525 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17526 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17527 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17528 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17529 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17530 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17531 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17532 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17533 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17534 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17535 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17537 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17538 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17539 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17540 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17541 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17542 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17543 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17544 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17545 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17546 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17547 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17548 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17550 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17551 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17552 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17553 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17555 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17556 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17557 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17558 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17559 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17560 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17561 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17562 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17563 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17564 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17565 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17566 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17568 /* The implementation of the FIX instruction is broken on some
17569 assemblers, in that it accepts a precision specifier as well as a
17570 rounding specifier, despite the fact that this is meaningless.
17571 To be more compatible, we accept it as well, though of course it
17572 does not set any bits. */
17573 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17574 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17575 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17576 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17577 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17578 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17579 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17580 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17581 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17582 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17583 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17584 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17585 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17587 /* Instructions that were new with the real FPA, call them V2. */
17589 #define ARM_VARIANT & fpu_fpa_ext_v2
17591 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17592 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17593 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17594 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17595 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17596 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17599 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17601 /* Moves and type conversions. */
17602 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17603 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17604 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17605 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17606 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17607 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17608 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17609 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17610 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17611 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17612 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17613 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17614 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17615 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17617 /* Memory operations. */
17618 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17619 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17620 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17621 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17622 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17623 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17624 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17625 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17626 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17627 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17628 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17629 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17630 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17631 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17632 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17633 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17634 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17635 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17637 /* Monadic operations. */
17638 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17639 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17640 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17642 /* Dyadic operations. */
17643 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17644 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17645 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17646 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17647 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17648 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17649 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17650 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17651 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17654 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17655 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17656 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17657 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17659 /* Double precision load/store are still present on single precision
17660 implementations. */
17661 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17662 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17663 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17664 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17665 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17666 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17667 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17668 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17669 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17670 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17673 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17675 /* Moves and type conversions. */
17676 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17677 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17678 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17679 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17680 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17681 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17682 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17683 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17684 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17685 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17686 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17687 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17688 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17690 /* Monadic operations. */
17691 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17692 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17693 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17695 /* Dyadic operations. */
17696 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17697 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17698 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17699 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17700 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17701 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17702 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17703 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17704 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17707 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17708 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17709 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17710 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17713 #define ARM_VARIANT & fpu_vfp_ext_v2
17715 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17716 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17717 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17718 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17720 /* Instructions which may belong to either the Neon or VFP instruction sets.
17721 Individual encoder functions perform additional architecture checks. */
17723 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17724 #undef THUMB_VARIANT
17725 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17727 /* These mnemonics are unique to VFP. */
17728 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17729 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17730 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17731 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17732 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17733 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17734 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17735 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17736 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17737 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17739 /* Mnemonics shared by Neon and VFP. */
17740 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17741 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17742 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17744 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17745 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17747 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17748 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17750 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17751 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17752 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17753 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17754 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17755 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17756 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17757 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17759 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17760 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17761 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17762 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17765 /* NOTE: All VMOV encoding is special-cased! */
17766 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17767 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17769 #undef THUMB_VARIANT
17770 #define THUMB_VARIANT & fpu_neon_ext_v1
17772 #define ARM_VARIANT & fpu_neon_ext_v1
17774 /* Data processing with three registers of the same length. */
17775 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17776 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17777 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17778 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17779 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17780 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17781 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17782 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17783 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17784 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17785 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17786 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17787 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17788 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17789 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17790 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17791 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17792 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17793 /* If not immediate, fall back to neon_dyadic_i64_su.
17794 shl_imm should accept I8 I16 I32 I64,
17795 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17796 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17797 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17798 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17799 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17800 /* Logic ops, types optional & ignored. */
17801 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17802 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17803 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17804 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17805 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17806 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17807 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17808 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17809 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17810 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17811 /* Bitfield ops, untyped. */
17812 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17813 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17814 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17815 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17816 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17817 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17818 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17819 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17820 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17821 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17822 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17823 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17824 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17825 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17826 back to neon_dyadic_if_su. */
17827 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17828 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17829 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17830 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17831 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17832 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17833 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17834 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17835 /* Comparison. Type I8 I16 I32 F32. */
17836 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17837 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17838 /* As above, D registers only. */
17839 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17840 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17841 /* Int and float variants, signedness unimportant. */
17842 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17843 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17844 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17845 /* Add/sub take types I8 I16 I32 I64 F32. */
17846 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17847 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17848 /* vtst takes sizes 8, 16, 32. */
17849 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17850 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17851 /* VMUL takes I8 I16 I32 F32 P8. */
17852 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17853 /* VQD{R}MULH takes S16 S32. */
17854 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17855 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17856 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17857 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17858 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17859 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17860 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17861 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17862 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17863 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17864 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17865 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17866 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17867 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17868 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17869 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17871 /* Two address, int/float. Types S8 S16 S32 F32. */
17872 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17873 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17875 /* Data processing with two registers and a shift amount. */
17876 /* Right shifts, and variants with rounding.
17877 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17878 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17879 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17880 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17881 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17882 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17883 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17884 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17885 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17886 /* Shift and insert. Sizes accepted 8 16 32 64. */
17887 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17888 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17889 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17890 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17891 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17892 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17893 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17894 /* Right shift immediate, saturating & narrowing, with rounding variants.
17895 Types accepted S16 S32 S64 U16 U32 U64. */
17896 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17897 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17898 /* As above, unsigned. Types accepted S16 S32 S64. */
17899 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17900 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17901 /* Right shift narrowing. Types accepted I16 I32 I64. */
17902 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17903 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17904 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17905 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17906 /* CVT with optional immediate for fixed-point variant. */
17907 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17909 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17910 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17912 /* Data processing, three registers of different lengths. */
17913 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17914 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17915 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17916 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17917 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17918 /* If not scalar, fall back to neon_dyadic_long.
17919 Vector types as above, scalar types S16 S32 U16 U32. */
17920 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17921 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17922 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17923 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17924 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17925 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17926 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17927 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17928 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17929 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17930 /* Saturating doubling multiplies. Types S16 S32. */
17931 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17932 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17933 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17934 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17935 S16 S32 U16 U32. */
17936 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17938 /* Extract. Size 8. */
17939 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17940 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17942 /* Two registers, miscellaneous. */
17943 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17944 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17945 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17946 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17947 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17948 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17949 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17950 /* Vector replicate. Sizes 8 16 32. */
17951 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17952 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17953 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17954 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17955 /* VMOVN. Types I16 I32 I64. */
17956 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17957 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17958 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17959 /* VQMOVUN. Types S16 S32 S64. */
17960 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17961 /* VZIP / VUZP. Sizes 8 16 32. */
17962 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17963 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17964 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17965 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17966 /* VQABS / VQNEG. Types S8 S16 S32. */
17967 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17968 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17969 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17970 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17971 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17972 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17973 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17974 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17975 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17976 /* Reciprocal estimates. Types U32 F32. */
17977 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17978 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17979 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17980 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17981 /* VCLS. Types S8 S16 S32. */
17982 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17983 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17984 /* VCLZ. Types I8 I16 I32. */
17985 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17986 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17987 /* VCNT. Size 8. */
17988 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17989 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17990 /* Two address, untyped. */
17991 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17992 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17993 /* VTRN. Sizes 8 16 32. */
17994 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17995 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17997 /* Table lookup. Size 8. */
17998 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17999 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18001 #undef THUMB_VARIANT
18002 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18004 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18006 /* Neon element/structure load/store. */
18007 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18008 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18009 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18010 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18011 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18012 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18013 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18014 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18016 #undef THUMB_VARIANT
18017 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18019 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18020 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18021 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18022 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18023 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18024 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18025 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18026 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18027 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18028 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18030 #undef THUMB_VARIANT
18031 #define THUMB_VARIANT & fpu_vfp_ext_v3
18033 #define ARM_VARIANT & fpu_vfp_ext_v3
18035 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18036 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18037 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18038 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18039 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18040 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18041 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18042 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18043 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18046 #define ARM_VARIANT &fpu_vfp_ext_fma
18047 #undef THUMB_VARIANT
18048 #define THUMB_VARIANT &fpu_vfp_ext_fma
18049 /* Mnemonics shared by Neon and VFP. These are included in the
18050 VFP FMA variant; NEON and VFP FMA always includes the NEON
18051 FMA instructions. */
18052 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18053 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18054 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18055 the v form should always be used. */
18056 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18057 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18058 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18059 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18060 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18061 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18063 #undef THUMB_VARIANT
18065 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18067 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18068 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18069 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18070 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18071 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18072 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18073 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18074 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18077 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18079 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18080 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18081 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18082 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18083 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18084 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18085 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18086 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18087 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18088 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18089 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18090 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18091 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18092 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18093 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18094 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18095 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18096 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18097 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18098 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18099 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18100 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18101 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18102 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18103 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18104 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18105 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18106 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18107 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18108 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18109 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18110 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18111 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18112 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18113 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18114 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18115 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18116 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18117 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18118 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18119 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18120 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18121 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18122 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18123 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18124 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18125 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18126 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18127 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18128 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18129 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18130 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18131 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18132 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18133 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18134 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18135 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18136 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18137 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18138 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18139 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18140 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18141 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18142 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18143 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18144 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18145 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18146 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18147 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18148 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18149 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18150 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18151 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18152 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18153 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18154 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18155 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18156 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18157 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18158 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18159 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18160 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18161 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18162 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18163 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18164 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18165 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18166 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18167 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18168 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18169 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18170 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18171 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18172 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18173 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18174 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18175 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18176 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18177 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18178 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18179 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18180 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18181 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18182 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18183 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18184 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18185 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18186 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18187 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18188 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18189 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18190 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18191 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18192 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18193 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18194 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18195 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18196 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18197 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18198 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18199 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18200 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18201 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18202 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18203 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18204 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18205 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18206 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18207 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18208 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18209 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18210 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18211 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18212 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18213 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18214 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18215 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18216 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18217 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18218 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18219 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18220 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18221 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18222 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18223 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18224 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18225 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18226 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18227 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18228 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18229 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18230 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18231 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18232 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18233 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18234 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18235 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18236 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18237 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18238 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18239 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18240 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18243 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18245 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18246 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18247 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18248 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18249 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18250 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18251 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18252 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18253 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18254 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18255 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18256 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18257 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18258 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18259 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18260 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18261 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18262 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18263 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18264 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18265 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18266 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18267 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18268 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18269 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18270 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18271 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18272 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18273 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18274 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18275 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18276 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18277 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18278 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18279 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18280 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18281 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18282 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18283 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18284 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18285 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18286 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18287 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18288 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18289 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18290 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18291 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18292 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18293 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18294 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18295 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18296 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18297 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18298 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18299 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18300 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18301 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18304 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18306 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18307 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18308 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18309 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18310 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18311 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18312 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18313 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18314 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18315 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18316 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18317 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18318 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18319 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18320 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18321 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18322 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18323 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18324 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18325 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18326 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18327 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18328 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18329 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18330 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18331 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18332 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18333 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18334 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18335 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18336 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18337 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18338 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18339 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18340 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18341 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18342 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18343 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18344 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18345 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18346 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18347 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18348 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18349 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18350 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18351 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18352 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18353 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18354 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18355 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18356 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18357 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18358 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18359 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18360 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18361 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18362 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18363 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18364 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18365 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18366 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18367 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18368 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18369 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18370 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18371 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18372 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18373 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18374 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18375 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18376 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18377 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18378 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18379 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18380 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18381 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18384 #undef THUMB_VARIANT
18411 /* MD interface: bits in the object file. */
18413 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18414 for use in the a.out file, and stores them in the array pointed to by buf.
18415 This knows about the endian-ness of the target machine and does
18416 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18417 2 (short) and 4 (long) Floating numbers are put out as a series of
18418 LITTLENUMS (shorts, here at least). */
18421 md_number_to_chars (char * buf
, valueT val
, int n
)
18423 if (target_big_endian
)
18424 number_to_chars_bigendian (buf
, val
, n
);
18426 number_to_chars_littleendian (buf
, val
, n
);
18430 md_chars_to_number (char * buf
, int n
)
18433 unsigned char * where
= (unsigned char *) buf
;
18435 if (target_big_endian
)
18440 result
|= (*where
++ & 255);
18448 result
|= (where
[n
] & 255);
18455 /* MD interface: Sections. */
18457 /* Estimate the size of a frag before relaxing. Assume everything fits in
18461 md_estimate_size_before_relax (fragS
* fragp
,
18462 segT segtype ATTRIBUTE_UNUSED
)
18468 /* Convert a machine dependent frag. */
18471 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18473 unsigned long insn
;
18474 unsigned long old_op
;
18482 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18484 old_op
= bfd_get_16(abfd
, buf
);
18485 if (fragp
->fr_symbol
)
18487 exp
.X_op
= O_symbol
;
18488 exp
.X_add_symbol
= fragp
->fr_symbol
;
18492 exp
.X_op
= O_constant
;
18494 exp
.X_add_number
= fragp
->fr_offset
;
18495 opcode
= fragp
->fr_subtype
;
18498 case T_MNEM_ldr_pc
:
18499 case T_MNEM_ldr_pc2
:
18500 case T_MNEM_ldr_sp
:
18501 case T_MNEM_str_sp
:
18508 if (fragp
->fr_var
== 4)
18510 insn
= THUMB_OP32 (opcode
);
18511 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18513 insn
|= (old_op
& 0x700) << 4;
18517 insn
|= (old_op
& 7) << 12;
18518 insn
|= (old_op
& 0x38) << 13;
18520 insn
|= 0x00000c00;
18521 put_thumb32_insn (buf
, insn
);
18522 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18526 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18528 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18531 if (fragp
->fr_var
== 4)
18533 insn
= THUMB_OP32 (opcode
);
18534 insn
|= (old_op
& 0xf0) << 4;
18535 put_thumb32_insn (buf
, insn
);
18536 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18540 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18541 exp
.X_add_number
-= 4;
18549 if (fragp
->fr_var
== 4)
18551 int r0off
= (opcode
== T_MNEM_mov
18552 || opcode
== T_MNEM_movs
) ? 0 : 8;
18553 insn
= THUMB_OP32 (opcode
);
18554 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18555 insn
|= (old_op
& 0x700) << r0off
;
18556 put_thumb32_insn (buf
, insn
);
18557 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18561 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18566 if (fragp
->fr_var
== 4)
18568 insn
= THUMB_OP32(opcode
);
18569 put_thumb32_insn (buf
, insn
);
18570 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18573 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18577 if (fragp
->fr_var
== 4)
18579 insn
= THUMB_OP32(opcode
);
18580 insn
|= (old_op
& 0xf00) << 14;
18581 put_thumb32_insn (buf
, insn
);
18582 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18585 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18588 case T_MNEM_add_sp
:
18589 case T_MNEM_add_pc
:
18590 case T_MNEM_inc_sp
:
18591 case T_MNEM_dec_sp
:
18592 if (fragp
->fr_var
== 4)
18594 /* ??? Choose between add and addw. */
18595 insn
= THUMB_OP32 (opcode
);
18596 insn
|= (old_op
& 0xf0) << 4;
18597 put_thumb32_insn (buf
, insn
);
18598 if (opcode
== T_MNEM_add_pc
)
18599 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18601 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18604 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18612 if (fragp
->fr_var
== 4)
18614 insn
= THUMB_OP32 (opcode
);
18615 insn
|= (old_op
& 0xf0) << 4;
18616 insn
|= (old_op
& 0xf) << 16;
18617 put_thumb32_insn (buf
, insn
);
18618 if (insn
& (1 << 20))
18619 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18621 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18624 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18630 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18631 (enum bfd_reloc_code_real
) reloc_type
);
18632 fixp
->fx_file
= fragp
->fr_file
;
18633 fixp
->fx_line
= fragp
->fr_line
;
18634 fragp
->fr_fix
+= fragp
->fr_var
;
18637 /* Return the size of a relaxable immediate operand instruction.
18638 SHIFT and SIZE specify the form of the allowable immediate. */
18640 relax_immediate (fragS
*fragp
, int size
, int shift
)
18646 /* ??? Should be able to do better than this. */
18647 if (fragp
->fr_symbol
)
18650 low
= (1 << shift
) - 1;
18651 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18652 offset
= fragp
->fr_offset
;
18653 /* Force misaligned offsets to 32-bit variant. */
18656 if (offset
& ~mask
)
18661 /* Get the address of a symbol during relaxation. */
18663 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18669 sym
= fragp
->fr_symbol
;
18670 sym_frag
= symbol_get_frag (sym
);
18671 know (S_GET_SEGMENT (sym
) != absolute_section
18672 || sym_frag
== &zero_address_frag
);
18673 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18675 /* If frag has yet to be reached on this pass, assume it will
18676 move by STRETCH just as we did. If this is not so, it will
18677 be because some frag between grows, and that will force
18681 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18685 /* Adjust stretch for any alignment frag. Note that if have
18686 been expanding the earlier code, the symbol may be
18687 defined in what appears to be an earlier frag. FIXME:
18688 This doesn't handle the fr_subtype field, which specifies
18689 a maximum number of bytes to skip when doing an
18691 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18693 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18696 stretch
= - ((- stretch
)
18697 & ~ ((1 << (int) f
->fr_offset
) - 1));
18699 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18711 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18714 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18719 /* Assume worst case for symbols not known to be in the same section. */
18720 if (fragp
->fr_symbol
== NULL
18721 || !S_IS_DEFINED (fragp
->fr_symbol
)
18722 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18723 || S_IS_WEAK (fragp
->fr_symbol
))
18726 val
= relaxed_symbol_addr (fragp
, stretch
);
18727 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18728 addr
= (addr
+ 4) & ~3;
18729 /* Force misaligned targets to 32-bit variant. */
18733 if (val
< 0 || val
> 1020)
18738 /* Return the size of a relaxable add/sub immediate instruction. */
18740 relax_addsub (fragS
*fragp
, asection
*sec
)
18745 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18746 op
= bfd_get_16(sec
->owner
, buf
);
18747 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18748 return relax_immediate (fragp
, 8, 0);
18750 return relax_immediate (fragp
, 3, 0);
18754 /* Return the size of a relaxable branch instruction. BITS is the
18755 size of the offset field in the narrow instruction. */
18758 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18764 /* Assume worst case for symbols not known to be in the same section. */
18765 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18766 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18767 || S_IS_WEAK (fragp
->fr_symbol
))
18771 if (S_IS_DEFINED (fragp
->fr_symbol
)
18772 && ARM_IS_FUNC (fragp
->fr_symbol
))
18776 val
= relaxed_symbol_addr (fragp
, stretch
);
18777 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18780 /* Offset is a signed value *2 */
18782 if (val
>= limit
|| val
< -limit
)
18788 /* Relax a machine dependent frag. This returns the amount by which
18789 the current size of the frag should change. */
18792 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18797 oldsize
= fragp
->fr_var
;
18798 switch (fragp
->fr_subtype
)
18800 case T_MNEM_ldr_pc2
:
18801 newsize
= relax_adr (fragp
, sec
, stretch
);
18803 case T_MNEM_ldr_pc
:
18804 case T_MNEM_ldr_sp
:
18805 case T_MNEM_str_sp
:
18806 newsize
= relax_immediate (fragp
, 8, 2);
18810 newsize
= relax_immediate (fragp
, 5, 2);
18814 newsize
= relax_immediate (fragp
, 5, 1);
18818 newsize
= relax_immediate (fragp
, 5, 0);
18821 newsize
= relax_adr (fragp
, sec
, stretch
);
18827 newsize
= relax_immediate (fragp
, 8, 0);
18830 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18833 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18835 case T_MNEM_add_sp
:
18836 case T_MNEM_add_pc
:
18837 newsize
= relax_immediate (fragp
, 8, 2);
18839 case T_MNEM_inc_sp
:
18840 case T_MNEM_dec_sp
:
18841 newsize
= relax_immediate (fragp
, 7, 2);
18847 newsize
= relax_addsub (fragp
, sec
);
18853 fragp
->fr_var
= newsize
;
18854 /* Freeze wide instructions that are at or before the same location as
18855 in the previous pass. This avoids infinite loops.
18856 Don't freeze them unconditionally because targets may be artificially
18857 misaligned by the expansion of preceding frags. */
18858 if (stretch
<= 0 && newsize
> 2)
18860 md_convert_frag (sec
->owner
, sec
, fragp
);
18864 return newsize
- oldsize
;
18867 /* Round up a section size to the appropriate boundary. */
18870 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18873 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18874 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18876 /* For a.out, force the section size to be aligned. If we don't do
18877 this, BFD will align it for us, but it will not write out the
18878 final bytes of the section. This may be a bug in BFD, but it is
18879 easier to fix it here since that is how the other a.out targets
18883 align
= bfd_get_section_alignment (stdoutput
, segment
);
18884 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18891 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18892 of an rs_align_code fragment. */
18895 arm_handle_align (fragS
* fragP
)
18897 static char const arm_noop
[2][2][4] =
18900 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18901 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18904 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18905 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18908 static char const thumb_noop
[2][2][2] =
18911 {0xc0, 0x46}, /* LE */
18912 {0x46, 0xc0}, /* BE */
18915 {0x00, 0xbf}, /* LE */
18916 {0xbf, 0x00} /* BE */
18919 static char const wide_thumb_noop
[2][4] =
18920 { /* Wide Thumb-2 */
18921 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18922 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18925 unsigned bytes
, fix
, noop_size
;
18928 const char *narrow_noop
= NULL
;
18933 if (fragP
->fr_type
!= rs_align_code
)
18936 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18937 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18940 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18941 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18943 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18945 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18947 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18949 narrow_noop
= thumb_noop
[1][target_big_endian
];
18950 noop
= wide_thumb_noop
[target_big_endian
];
18953 noop
= thumb_noop
[0][target_big_endian
];
18961 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18962 [target_big_endian
];
18969 fragP
->fr_var
= noop_size
;
18971 if (bytes
& (noop_size
- 1))
18973 fix
= bytes
& (noop_size
- 1);
18975 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18977 memset (p
, 0, fix
);
18984 if (bytes
& noop_size
)
18986 /* Insert a narrow noop. */
18987 memcpy (p
, narrow_noop
, noop_size
);
18989 bytes
-= noop_size
;
18993 /* Use wide noops for the remainder */
18997 while (bytes
>= noop_size
)
18999 memcpy (p
, noop
, noop_size
);
19001 bytes
-= noop_size
;
19005 fragP
->fr_fix
+= fix
;
19008 /* Called from md_do_align. Used to create an alignment
19009 frag in a code section. */
19012 arm_frag_align_code (int n
, int max
)
19016 /* We assume that there will never be a requirement
19017 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19018 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19023 _("alignments greater than %d bytes not supported in .text sections."),
19024 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19025 as_fatal ("%s", err_msg
);
19028 p
= frag_var (rs_align_code
,
19029 MAX_MEM_FOR_RS_ALIGN_CODE
,
19031 (relax_substateT
) max
,
19038 /* Perform target specific initialisation of a frag.
19039 Note - despite the name this initialisation is not done when the frag
19040 is created, but only when its type is assigned. A frag can be created
19041 and used a long time before its type is set, so beware of assuming that
19042 this initialisationis performed first. */
19046 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19048 /* Record whether this frag is in an ARM or a THUMB area. */
19049 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19052 #else /* OBJ_ELF is defined. */
19054 arm_init_frag (fragS
* fragP
, int max_chars
)
19056 /* If the current ARM vs THUMB mode has not already
19057 been recorded into this frag then do so now. */
19058 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19060 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19062 /* Record a mapping symbol for alignment frags. We will delete this
19063 later if the alignment ends up empty. */
19064 switch (fragP
->fr_type
)
19067 case rs_align_test
:
19069 mapping_state_2 (MAP_DATA
, max_chars
);
19071 case rs_align_code
:
19072 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19080 /* When we change sections we need to issue a new mapping symbol. */
19083 arm_elf_change_section (void)
19085 /* Link an unlinked unwind index table section to the .text section. */
19086 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19087 && elf_linked_to_section (now_seg
) == NULL
)
19088 elf_linked_to_section (now_seg
) = text_section
;
19092 arm_elf_section_type (const char * str
, size_t len
)
19094 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19095 return SHT_ARM_EXIDX
;
19100 /* Code to deal with unwinding tables. */
19102 static void add_unwind_adjustsp (offsetT
);
19104 /* Generate any deferred unwind frame offset. */
19107 flush_pending_unwind (void)
19111 offset
= unwind
.pending_offset
;
19112 unwind
.pending_offset
= 0;
19114 add_unwind_adjustsp (offset
);
19117 /* Add an opcode to this list for this function. Two-byte opcodes should
19118 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19122 add_unwind_opcode (valueT op
, int length
)
19124 /* Add any deferred stack adjustment. */
19125 if (unwind
.pending_offset
)
19126 flush_pending_unwind ();
19128 unwind
.sp_restored
= 0;
19130 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19132 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19133 if (unwind
.opcodes
)
19134 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19135 unwind
.opcode_alloc
);
19137 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19142 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19144 unwind
.opcode_count
++;
19148 /* Add unwind opcodes to adjust the stack pointer. */
19151 add_unwind_adjustsp (offsetT offset
)
19155 if (offset
> 0x200)
19157 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19162 /* Long form: 0xb2, uleb128. */
19163 /* This might not fit in a word so add the individual bytes,
19164 remembering the list is built in reverse order. */
19165 o
= (valueT
) ((offset
- 0x204) >> 2);
19167 add_unwind_opcode (0, 1);
19169 /* Calculate the uleb128 encoding of the offset. */
19173 bytes
[n
] = o
& 0x7f;
19179 /* Add the insn. */
19181 add_unwind_opcode (bytes
[n
- 1], 1);
19182 add_unwind_opcode (0xb2, 1);
19184 else if (offset
> 0x100)
19186 /* Two short opcodes. */
19187 add_unwind_opcode (0x3f, 1);
19188 op
= (offset
- 0x104) >> 2;
19189 add_unwind_opcode (op
, 1);
19191 else if (offset
> 0)
19193 /* Short opcode. */
19194 op
= (offset
- 4) >> 2;
19195 add_unwind_opcode (op
, 1);
19197 else if (offset
< 0)
19200 while (offset
> 0x100)
19202 add_unwind_opcode (0x7f, 1);
19205 op
= ((offset
- 4) >> 2) | 0x40;
19206 add_unwind_opcode (op
, 1);
19210 /* Finish the list of unwind opcodes for this function. */
19212 finish_unwind_opcodes (void)
19216 if (unwind
.fp_used
)
19218 /* Adjust sp as necessary. */
19219 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19220 flush_pending_unwind ();
19222 /* After restoring sp from the frame pointer. */
19223 op
= 0x90 | unwind
.fp_reg
;
19224 add_unwind_opcode (op
, 1);
19227 flush_pending_unwind ();
19231 /* Start an exception table entry. If idx is nonzero this is an index table
19235 start_unwind_section (const segT text_seg
, int idx
)
19237 const char * text_name
;
19238 const char * prefix
;
19239 const char * prefix_once
;
19240 const char * group_name
;
19244 size_t sec_name_len
;
19251 prefix
= ELF_STRING_ARM_unwind
;
19252 prefix_once
= ELF_STRING_ARM_unwind_once
;
19253 type
= SHT_ARM_EXIDX
;
19257 prefix
= ELF_STRING_ARM_unwind_info
;
19258 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19259 type
= SHT_PROGBITS
;
19262 text_name
= segment_name (text_seg
);
19263 if (streq (text_name
, ".text"))
19266 if (strncmp (text_name
, ".gnu.linkonce.t.",
19267 strlen (".gnu.linkonce.t.")) == 0)
19269 prefix
= prefix_once
;
19270 text_name
+= strlen (".gnu.linkonce.t.");
19273 prefix_len
= strlen (prefix
);
19274 text_len
= strlen (text_name
);
19275 sec_name_len
= prefix_len
+ text_len
;
19276 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19277 memcpy (sec_name
, prefix
, prefix_len
);
19278 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19279 sec_name
[prefix_len
+ text_len
] = '\0';
19285 /* Handle COMDAT group. */
19286 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19288 group_name
= elf_group_name (text_seg
);
19289 if (group_name
== NULL
)
19291 as_bad (_("Group section `%s' has no group signature"),
19292 segment_name (text_seg
));
19293 ignore_rest_of_line ();
19296 flags
|= SHF_GROUP
;
19300 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19302 /* Set the section link for index tables. */
19304 elf_linked_to_section (now_seg
) = text_seg
;
19308 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19309 personality routine data. Returns zero, or the index table value for
19310 and inline entry. */
19313 create_unwind_entry (int have_data
)
19318 /* The current word of data. */
19320 /* The number of bytes left in this word. */
19323 finish_unwind_opcodes ();
19325 /* Remember the current text section. */
19326 unwind
.saved_seg
= now_seg
;
19327 unwind
.saved_subseg
= now_subseg
;
19329 start_unwind_section (now_seg
, 0);
19331 if (unwind
.personality_routine
== NULL
)
19333 if (unwind
.personality_index
== -2)
19336 as_bad (_("handlerdata in cantunwind frame"));
19337 return 1; /* EXIDX_CANTUNWIND. */
19340 /* Use a default personality routine if none is specified. */
19341 if (unwind
.personality_index
== -1)
19343 if (unwind
.opcode_count
> 3)
19344 unwind
.personality_index
= 1;
19346 unwind
.personality_index
= 0;
19349 /* Space for the personality routine entry. */
19350 if (unwind
.personality_index
== 0)
19352 if (unwind
.opcode_count
> 3)
19353 as_bad (_("too many unwind opcodes for personality routine 0"));
19357 /* All the data is inline in the index table. */
19360 while (unwind
.opcode_count
> 0)
19362 unwind
.opcode_count
--;
19363 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19367 /* Pad with "finish" opcodes. */
19369 data
= (data
<< 8) | 0xb0;
19376 /* We get two opcodes "free" in the first word. */
19377 size
= unwind
.opcode_count
- 2;
19380 /* An extra byte is required for the opcode count. */
19381 size
= unwind
.opcode_count
+ 1;
19383 size
= (size
+ 3) >> 2;
19385 as_bad (_("too many unwind opcodes"));
19387 frag_align (2, 0, 0);
19388 record_alignment (now_seg
, 2);
19389 unwind
.table_entry
= expr_build_dot ();
19391 /* Allocate the table entry. */
19392 ptr
= frag_more ((size
<< 2) + 4);
19393 where
= frag_now_fix () - ((size
<< 2) + 4);
19395 switch (unwind
.personality_index
)
19398 /* ??? Should this be a PLT generating relocation? */
19399 /* Custom personality routine. */
19400 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19401 BFD_RELOC_ARM_PREL31
);
19406 /* Set the first byte to the number of additional words. */
19411 /* ABI defined personality routines. */
19413 /* Three opcodes bytes are packed into the first word. */
19420 /* The size and first two opcode bytes go in the first word. */
19421 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19426 /* Should never happen. */
19430 /* Pack the opcodes into words (MSB first), reversing the list at the same
19432 while (unwind
.opcode_count
> 0)
19436 md_number_to_chars (ptr
, data
, 4);
19441 unwind
.opcode_count
--;
19443 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19446 /* Finish off the last word. */
19449 /* Pad with "finish" opcodes. */
19451 data
= (data
<< 8) | 0xb0;
19453 md_number_to_chars (ptr
, data
, 4);
19458 /* Add an empty descriptor if there is no user-specified data. */
19459 ptr
= frag_more (4);
19460 md_number_to_chars (ptr
, 0, 4);
19467 /* Initialize the DWARF-2 unwind information for this procedure. */
19470 tc_arm_frame_initial_instructions (void)
19472 cfi_add_CFA_def_cfa (REG_SP
, 0);
19474 #endif /* OBJ_ELF */
19476 /* Convert REGNAME to a DWARF-2 register number. */
19479 tc_arm_regname_to_dw2regnum (char *regname
)
19481 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19491 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19495 exp
.X_op
= O_secrel
;
19496 exp
.X_add_symbol
= symbol
;
19497 exp
.X_add_number
= 0;
19498 emit_expr (&exp
, size
);
19502 /* MD interface: Symbol and relocation handling. */
19504 /* Return the address within the segment that a PC-relative fixup is
19505 relative to. For ARM, PC-relative fixups applied to instructions
19506 are generally relative to the location of the fixup plus 8 bytes.
19507 Thumb branches are offset by 4, and Thumb loads relative to PC
19508 require special handling. */
19511 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19513 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19515 /* If this is pc-relative and we are going to emit a relocation
19516 then we just want to put out any pipeline compensation that the linker
19517 will need. Otherwise we want to use the calculated base.
19518 For WinCE we skip the bias for externals as well, since this
19519 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19521 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19522 || (arm_force_relocation (fixP
)
19524 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19530 switch (fixP
->fx_r_type
)
19532 /* PC relative addressing on the Thumb is slightly odd as the
19533 bottom two bits of the PC are forced to zero for the
19534 calculation. This happens *after* application of the
19535 pipeline offset. However, Thumb adrl already adjusts for
19536 this, so we need not do it again. */
19537 case BFD_RELOC_ARM_THUMB_ADD
:
19540 case BFD_RELOC_ARM_THUMB_OFFSET
:
19541 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19542 case BFD_RELOC_ARM_T32_ADD_PC12
:
19543 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19544 return (base
+ 4) & ~3;
19546 /* Thumb branches are simply offset by +4. */
19547 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19548 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19549 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19550 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19551 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19554 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19556 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19557 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19558 && ARM_IS_FUNC (fixP
->fx_addsy
)
19559 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19560 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19563 /* BLX is like branches above, but forces the low two bits of PC to
19565 case BFD_RELOC_THUMB_PCREL_BLX
:
19567 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19568 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19569 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19570 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19571 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19572 return (base
+ 4) & ~3;
19574 /* ARM mode branches are offset by +8. However, the Windows CE
19575 loader expects the relocation not to take this into account. */
19576 case BFD_RELOC_ARM_PCREL_BLX
:
19578 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19579 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19580 && ARM_IS_FUNC (fixP
->fx_addsy
)
19581 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19582 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19585 case BFD_RELOC_ARM_PCREL_CALL
:
19587 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19588 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19589 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19590 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19591 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19594 case BFD_RELOC_ARM_PCREL_BRANCH
:
19595 case BFD_RELOC_ARM_PCREL_JUMP
:
19596 case BFD_RELOC_ARM_PLT32
:
19598 /* When handling fixups immediately, because we have already
19599 discovered the value of a symbol, or the address of the frag involved
19600 we must account for the offset by +8, as the OS loader will never see the reloc.
19601 see fixup_segment() in write.c
19602 The S_IS_EXTERNAL test handles the case of global symbols.
19603 Those need the calculated base, not just the pipe compensation the linker will need. */
19605 && fixP
->fx_addsy
!= NULL
19606 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19607 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19615 /* ARM mode loads relative to PC are also offset by +8. Unlike
19616 branches, the Windows CE loader *does* expect the relocation
19617 to take this into account. */
19618 case BFD_RELOC_ARM_OFFSET_IMM
:
19619 case BFD_RELOC_ARM_OFFSET_IMM8
:
19620 case BFD_RELOC_ARM_HWLITERAL
:
19621 case BFD_RELOC_ARM_LITERAL
:
19622 case BFD_RELOC_ARM_CP_OFF_IMM
:
19626 /* Other PC-relative relocations are un-offset. */
19632 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19633 Otherwise we have no need to default values of symbols. */
19636 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19639 if (name
[0] == '_' && name
[1] == 'G'
19640 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19644 if (symbol_find (name
))
19645 as_bad (_("GOT already in the symbol table"));
19647 GOT_symbol
= symbol_new (name
, undefined_section
,
19648 (valueT
) 0, & zero_address_frag
);
19658 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19659 computed as two separate immediate values, added together. We
19660 already know that this value cannot be computed by just one ARM
19663 static unsigned int
19664 validate_immediate_twopart (unsigned int val
,
19665 unsigned int * highpart
)
19670 for (i
= 0; i
< 32; i
+= 2)
19671 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19677 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19679 else if (a
& 0xff0000)
19681 if (a
& 0xff000000)
19683 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19687 gas_assert (a
& 0xff000000);
19688 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19691 return (a
& 0xff) | (i
<< 7);
19698 validate_offset_imm (unsigned int val
, int hwse
)
19700 if ((hwse
&& val
> 255) || val
> 4095)
19705 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19706 negative immediate constant by altering the instruction. A bit of
19711 by inverting the second operand, and
19714 by negating the second operand. */
19717 negate_data_op (unsigned long * instruction
,
19718 unsigned long value
)
19721 unsigned long negated
, inverted
;
19723 negated
= encode_arm_immediate (-value
);
19724 inverted
= encode_arm_immediate (~value
);
19726 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19729 /* First negates. */
19730 case OPCODE_SUB
: /* ADD <-> SUB */
19731 new_inst
= OPCODE_ADD
;
19736 new_inst
= OPCODE_SUB
;
19740 case OPCODE_CMP
: /* CMP <-> CMN */
19741 new_inst
= OPCODE_CMN
;
19746 new_inst
= OPCODE_CMP
;
19750 /* Now Inverted ops. */
19751 case OPCODE_MOV
: /* MOV <-> MVN */
19752 new_inst
= OPCODE_MVN
;
19757 new_inst
= OPCODE_MOV
;
19761 case OPCODE_AND
: /* AND <-> BIC */
19762 new_inst
= OPCODE_BIC
;
19767 new_inst
= OPCODE_AND
;
19771 case OPCODE_ADC
: /* ADC <-> SBC */
19772 new_inst
= OPCODE_SBC
;
19777 new_inst
= OPCODE_ADC
;
19781 /* We cannot do anything. */
19786 if (value
== (unsigned) FAIL
)
19789 *instruction
&= OPCODE_MASK
;
19790 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19794 /* Like negate_data_op, but for Thumb-2. */
19796 static unsigned int
19797 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19801 unsigned int negated
, inverted
;
19803 negated
= encode_thumb32_immediate (-value
);
19804 inverted
= encode_thumb32_immediate (~value
);
19806 rd
= (*instruction
>> 8) & 0xf;
19807 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19810 /* ADD <-> SUB. Includes CMP <-> CMN. */
19811 case T2_OPCODE_SUB
:
19812 new_inst
= T2_OPCODE_ADD
;
19816 case T2_OPCODE_ADD
:
19817 new_inst
= T2_OPCODE_SUB
;
19821 /* ORR <-> ORN. Includes MOV <-> MVN. */
19822 case T2_OPCODE_ORR
:
19823 new_inst
= T2_OPCODE_ORN
;
19827 case T2_OPCODE_ORN
:
19828 new_inst
= T2_OPCODE_ORR
;
19832 /* AND <-> BIC. TST has no inverted equivalent. */
19833 case T2_OPCODE_AND
:
19834 new_inst
= T2_OPCODE_BIC
;
19841 case T2_OPCODE_BIC
:
19842 new_inst
= T2_OPCODE_AND
;
19847 case T2_OPCODE_ADC
:
19848 new_inst
= T2_OPCODE_SBC
;
19852 case T2_OPCODE_SBC
:
19853 new_inst
= T2_OPCODE_ADC
;
19857 /* We cannot do anything. */
19862 if (value
== (unsigned int)FAIL
)
19865 *instruction
&= T2_OPCODE_MASK
;
19866 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19870 /* Read a 32-bit thumb instruction from buf. */
19871 static unsigned long
19872 get_thumb32_insn (char * buf
)
19874 unsigned long insn
;
19875 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19876 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19882 /* We usually want to set the low bit on the address of thumb function
19883 symbols. In particular .word foo - . should have the low bit set.
19884 Generic code tries to fold the difference of two symbols to
19885 a constant. Prevent this and force a relocation when the first symbols
19886 is a thumb function. */
19889 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19891 if (op
== O_subtract
19892 && l
->X_op
== O_symbol
19893 && r
->X_op
== O_symbol
19894 && THUMB_IS_FUNC (l
->X_add_symbol
))
19896 l
->X_op
= O_subtract
;
19897 l
->X_op_symbol
= r
->X_add_symbol
;
19898 l
->X_add_number
-= r
->X_add_number
;
19902 /* Process as normal. */
19906 /* Encode Thumb2 unconditional branches and calls. The encoding
19907 for the 2 are identical for the immediate values. */
19910 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19912 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19915 addressT S
, I1
, I2
, lo
, hi
;
19917 S
= (value
>> 24) & 0x01;
19918 I1
= (value
>> 23) & 0x01;
19919 I2
= (value
>> 22) & 0x01;
19920 hi
= (value
>> 12) & 0x3ff;
19921 lo
= (value
>> 1) & 0x7ff;
19922 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19923 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19924 newval
|= (S
<< 10) | hi
;
19925 newval2
&= ~T2I1I2MASK
;
19926 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19927 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19928 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19932 md_apply_fix (fixS
* fixP
,
19936 offsetT value
= * valP
;
19938 unsigned int newimm
;
19939 unsigned long temp
;
19941 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19943 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19945 /* Note whether this will delete the relocation. */
19947 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19950 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19951 consistency with the behaviour on 32-bit hosts. Remember value
19953 value
&= 0xffffffff;
19954 value
^= 0x80000000;
19955 value
-= 0x80000000;
19958 fixP
->fx_addnumber
= value
;
19960 /* Same treatment for fixP->fx_offset. */
19961 fixP
->fx_offset
&= 0xffffffff;
19962 fixP
->fx_offset
^= 0x80000000;
19963 fixP
->fx_offset
-= 0x80000000;
19965 switch (fixP
->fx_r_type
)
19967 case BFD_RELOC_NONE
:
19968 /* This will need to go in the object file. */
19972 case BFD_RELOC_ARM_IMMEDIATE
:
19973 /* We claim that this fixup has been processed here,
19974 even if in fact we generate an error because we do
19975 not have a reloc for it, so tc_gen_reloc will reject it. */
19978 if (fixP
->fx_addsy
)
19980 const char *msg
= 0;
19982 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19983 msg
= _("undefined symbol %s used as an immediate value");
19984 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19985 msg
= _("symbol %s is in a different section");
19986 else if (S_IS_WEAK (fixP
->fx_addsy
))
19987 msg
= _("symbol %s is weak and may be overridden later");
19991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19992 msg
, S_GET_NAME (fixP
->fx_addsy
));
19997 newimm
= encode_arm_immediate (value
);
19998 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20000 /* If the instruction will fail, see if we can fix things up by
20001 changing the opcode. */
20002 if (newimm
== (unsigned int) FAIL
20003 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20005 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20006 _("invalid constant (%lx) after fixup"),
20007 (unsigned long) value
);
20011 newimm
|= (temp
& 0xfffff000);
20012 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20015 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20017 unsigned int highpart
= 0;
20018 unsigned int newinsn
= 0xe1a00000; /* nop. */
20020 if (fixP
->fx_addsy
)
20022 const char *msg
= 0;
20024 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20025 msg
= _("undefined symbol %s used as an immediate value");
20026 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20027 msg
= _("symbol %s is in a different section");
20028 else if (S_IS_WEAK (fixP
->fx_addsy
))
20029 msg
= _("symbol %s is weak and may be overridden later");
20033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20034 msg
, S_GET_NAME (fixP
->fx_addsy
));
20039 newimm
= encode_arm_immediate (value
);
20040 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20042 /* If the instruction will fail, see if we can fix things up by
20043 changing the opcode. */
20044 if (newimm
== (unsigned int) FAIL
20045 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20047 /* No ? OK - try using two ADD instructions to generate
20049 newimm
= validate_immediate_twopart (value
, & highpart
);
20051 /* Yes - then make sure that the second instruction is
20053 if (newimm
!= (unsigned int) FAIL
)
20055 /* Still No ? Try using a negated value. */
20056 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20057 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20058 /* Otherwise - give up. */
20061 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20062 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20067 /* Replace the first operand in the 2nd instruction (which
20068 is the PC) with the destination register. We have
20069 already added in the PC in the first instruction and we
20070 do not want to do it again. */
20071 newinsn
&= ~ 0xf0000;
20072 newinsn
|= ((newinsn
& 0x0f000) << 4);
20075 newimm
|= (temp
& 0xfffff000);
20076 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20078 highpart
|= (newinsn
& 0xfffff000);
20079 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20083 case BFD_RELOC_ARM_OFFSET_IMM
:
20084 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20087 case BFD_RELOC_ARM_LITERAL
:
20093 if (validate_offset_imm (value
, 0) == FAIL
)
20095 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20097 _("invalid literal constant: pool needs to be closer"));
20099 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20100 _("bad immediate value for offset (%ld)"),
20105 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20106 newval
&= 0xff7ff000;
20107 newval
|= value
| (sign
? INDEX_UP
: 0);
20108 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20111 case BFD_RELOC_ARM_OFFSET_IMM8
:
20112 case BFD_RELOC_ARM_HWLITERAL
:
20118 if (validate_offset_imm (value
, 1) == FAIL
)
20120 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20121 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20122 _("invalid literal constant: pool needs to be closer"));
20124 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20129 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20130 newval
&= 0xff7ff0f0;
20131 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20132 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20135 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20136 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20138 _("bad immediate value for offset (%ld)"), (long) value
);
20141 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20143 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20146 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20147 /* This is a complicated relocation used for all varieties of Thumb32
20148 load/store instruction with immediate offset:
20150 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20151 *4, optional writeback(W)
20152 (doubleword load/store)
20154 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20155 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20156 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20157 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20158 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20160 Uppercase letters indicate bits that are already encoded at
20161 this point. Lowercase letters are our problem. For the
20162 second block of instructions, the secondary opcode nybble
20163 (bits 8..11) is present, and bit 23 is zero, even if this is
20164 a PC-relative operation. */
20165 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20167 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20169 if ((newval
& 0xf0000000) == 0xe0000000)
20171 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20173 newval
|= (1 << 23);
20176 if (value
% 4 != 0)
20178 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20179 _("offset not a multiple of 4"));
20185 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20186 _("offset out of range"));
20191 else if ((newval
& 0x000f0000) == 0x000f0000)
20193 /* PC-relative, 12-bit offset. */
20195 newval
|= (1 << 23);
20200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20201 _("offset out of range"));
20206 else if ((newval
& 0x00000100) == 0x00000100)
20208 /* Writeback: 8-bit, +/- offset. */
20210 newval
|= (1 << 9);
20215 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20216 _("offset out of range"));
20221 else if ((newval
& 0x00000f00) == 0x00000e00)
20223 /* T-instruction: positive 8-bit offset. */
20224 if (value
< 0 || value
> 0xff)
20226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20227 _("offset out of range"));
20235 /* Positive 12-bit or negative 8-bit offset. */
20239 newval
|= (1 << 23);
20249 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20250 _("offset out of range"));
20257 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20258 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20261 case BFD_RELOC_ARM_SHIFT_IMM
:
20262 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20263 if (((unsigned long) value
) > 32
20265 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20267 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20268 _("shift expression is too large"));
20273 /* Shifts of zero must be done as lsl. */
20275 else if (value
== 32)
20277 newval
&= 0xfffff07f;
20278 newval
|= (value
& 0x1f) << 7;
20279 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20282 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20283 case BFD_RELOC_ARM_T32_ADD_IMM
:
20284 case BFD_RELOC_ARM_T32_IMM12
:
20285 case BFD_RELOC_ARM_T32_ADD_PC12
:
20286 /* We claim that this fixup has been processed here,
20287 even if in fact we generate an error because we do
20288 not have a reloc for it, so tc_gen_reloc will reject it. */
20292 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20294 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20295 _("undefined symbol %s used as an immediate value"),
20296 S_GET_NAME (fixP
->fx_addsy
));
20300 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20302 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20305 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20306 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20308 newimm
= encode_thumb32_immediate (value
);
20309 if (newimm
== (unsigned int) FAIL
)
20310 newimm
= thumb32_negate_data_op (&newval
, value
);
20312 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20313 && newimm
== (unsigned int) FAIL
)
20315 /* Turn add/sum into addw/subw. */
20316 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20317 newval
= (newval
& 0xfeffffff) | 0x02000000;
20318 /* No flat 12-bit imm encoding for addsw/subsw. */
20319 if ((newval
& 0x00100000) == 0)
20321 /* 12 bit immediate for addw/subw. */
20325 newval
^= 0x00a00000;
20328 newimm
= (unsigned int) FAIL
;
20334 if (newimm
== (unsigned int)FAIL
)
20336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20337 _("invalid constant (%lx) after fixup"),
20338 (unsigned long) value
);
20342 newval
|= (newimm
& 0x800) << 15;
20343 newval
|= (newimm
& 0x700) << 4;
20344 newval
|= (newimm
& 0x0ff);
20346 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20347 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20350 case BFD_RELOC_ARM_SMC
:
20351 if (((unsigned long) value
) > 0xffff)
20352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20353 _("invalid smc expression"));
20354 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20355 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20356 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20359 case BFD_RELOC_ARM_SWI
:
20360 if (fixP
->tc_fix_data
!= 0)
20362 if (((unsigned long) value
) > 0xff)
20363 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20364 _("invalid swi expression"));
20365 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20367 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20371 if (((unsigned long) value
) > 0x00ffffff)
20372 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20373 _("invalid swi expression"));
20374 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20376 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20380 case BFD_RELOC_ARM_MULTI
:
20381 if (((unsigned long) value
) > 0xffff)
20382 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20383 _("invalid expression in load/store multiple"));
20384 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20385 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20389 case BFD_RELOC_ARM_PCREL_CALL
:
20391 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20393 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20394 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20395 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20396 /* Flip the bl to blx. This is a simple flip
20397 bit here because we generate PCREL_CALL for
20398 unconditional bls. */
20400 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20401 newval
= newval
| 0x10000000;
20402 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20408 goto arm_branch_common
;
20410 case BFD_RELOC_ARM_PCREL_JUMP
:
20411 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20413 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20414 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20415 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20417 /* This would map to a bl<cond>, b<cond>,
20418 b<always> to a Thumb function. We
20419 need to force a relocation for this particular
20421 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20425 case BFD_RELOC_ARM_PLT32
:
20427 case BFD_RELOC_ARM_PCREL_BRANCH
:
20429 goto arm_branch_common
;
20431 case BFD_RELOC_ARM_PCREL_BLX
:
20434 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20436 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20437 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20438 && ARM_IS_FUNC (fixP
->fx_addsy
))
20440 /* Flip the blx to a bl and warn. */
20441 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20442 newval
= 0xeb000000;
20443 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20444 _("blx to '%s' an ARM ISA state function changed to bl"),
20446 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20452 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20453 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20457 /* We are going to store value (shifted right by two) in the
20458 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20459 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20460 also be be clear. */
20462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20463 _("misaligned branch destination"));
20464 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20465 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20467 _("branch out of range"));
20469 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20471 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20472 newval
|= (value
>> 2) & 0x00ffffff;
20473 /* Set the H bit on BLX instructions. */
20477 newval
|= 0x01000000;
20479 newval
&= ~0x01000000;
20481 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20485 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20486 /* CBZ can only branch forward. */
20488 /* Attempts to use CBZ to branch to the next instruction
20489 (which, strictly speaking, are prohibited) will be turned into
20492 FIXME: It may be better to remove the instruction completely and
20493 perform relaxation. */
20496 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20497 newval
= 0xbf00; /* NOP encoding T1 */
20498 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20504 _("branch out of range"));
20506 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20508 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20509 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20510 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20515 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20516 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20518 _("branch out of range"));
20520 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20522 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20523 newval
|= (value
& 0x1ff) >> 1;
20524 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20528 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20529 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20531 _("branch out of range"));
20533 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20535 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20536 newval
|= (value
& 0xfff) >> 1;
20537 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20541 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20543 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20544 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20545 && S_IS_DEFINED (fixP
->fx_addsy
)
20546 && ARM_IS_FUNC (fixP
->fx_addsy
)
20547 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20549 /* Force a relocation for a branch 20 bits wide. */
20552 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20554 _("conditional branch out of range"));
20556 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20559 addressT S
, J1
, J2
, lo
, hi
;
20561 S
= (value
& 0x00100000) >> 20;
20562 J2
= (value
& 0x00080000) >> 19;
20563 J1
= (value
& 0x00040000) >> 18;
20564 hi
= (value
& 0x0003f000) >> 12;
20565 lo
= (value
& 0x00000ffe) >> 1;
20567 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20568 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20569 newval
|= (S
<< 10) | hi
;
20570 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20571 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20572 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20576 case BFD_RELOC_THUMB_PCREL_BLX
:
20578 /* If there is a blx from a thumb state function to
20579 another thumb function flip this to a bl and warn
20583 && S_IS_DEFINED (fixP
->fx_addsy
)
20584 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20585 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20586 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20588 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20589 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20590 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20592 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20593 newval
= newval
| 0x1000;
20594 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20595 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20600 goto thumb_bl_common
;
20602 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20604 /* A bl from Thumb state ISA to an internal ARM state function
20605 is converted to a blx. */
20607 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20608 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20609 && S_IS_DEFINED (fixP
->fx_addsy
)
20610 && ARM_IS_FUNC (fixP
->fx_addsy
)
20611 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20613 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20614 newval
= newval
& ~0x1000;
20615 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20616 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20623 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20624 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20625 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20628 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20629 /* For a BLX instruction, make sure that the relocation is rounded up
20630 to a word boundary. This follows the semantics of the instruction
20631 which specifies that bit 1 of the target address will come from bit
20632 1 of the base address. */
20633 value
= (value
+ 1) & ~ 1;
20636 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20638 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20641 _("branch out of range"));
20643 else if ((value
& ~0x1ffffff)
20644 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20646 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20647 _("Thumb2 branch out of range"));
20651 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20652 encode_thumb2_b_bl_offset (buf
, value
);
20656 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20657 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20659 _("branch out of range"));
20661 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20662 encode_thumb2_b_bl_offset (buf
, value
);
20667 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20668 md_number_to_chars (buf
, value
, 1);
20672 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20673 md_number_to_chars (buf
, value
, 2);
20677 case BFD_RELOC_ARM_TLS_GD32
:
20678 case BFD_RELOC_ARM_TLS_LE32
:
20679 case BFD_RELOC_ARM_TLS_IE32
:
20680 case BFD_RELOC_ARM_TLS_LDM32
:
20681 case BFD_RELOC_ARM_TLS_LDO32
:
20682 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20685 case BFD_RELOC_ARM_GOT32
:
20686 case BFD_RELOC_ARM_GOTOFF
:
20687 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20688 md_number_to_chars (buf
, 0, 4);
20691 case BFD_RELOC_ARM_GOT_PREL
:
20692 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20693 md_number_to_chars (buf
, value
, 4);
20696 case BFD_RELOC_ARM_TARGET2
:
20697 /* TARGET2 is not partial-inplace, so we need to write the
20698 addend here for REL targets, because it won't be written out
20699 during reloc processing later. */
20700 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20701 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20705 case BFD_RELOC_RVA
:
20707 case BFD_RELOC_ARM_TARGET1
:
20708 case BFD_RELOC_ARM_ROSEGREL32
:
20709 case BFD_RELOC_ARM_SBREL32
:
20710 case BFD_RELOC_32_PCREL
:
20712 case BFD_RELOC_32_SECREL
:
20714 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20716 /* For WinCE we only do this for pcrel fixups. */
20717 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20719 md_number_to_chars (buf
, value
, 4);
20723 case BFD_RELOC_ARM_PREL31
:
20724 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20726 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20727 if ((value
^ (value
>> 1)) & 0x40000000)
20729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20730 _("rel31 relocation overflow"));
20732 newval
|= value
& 0x7fffffff;
20733 md_number_to_chars (buf
, newval
, 4);
20738 case BFD_RELOC_ARM_CP_OFF_IMM
:
20739 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20740 if (value
< -1023 || value
> 1023 || (value
& 3))
20741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20742 _("co-processor offset out of range"));
20747 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20748 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20749 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20751 newval
= get_thumb32_insn (buf
);
20752 newval
&= 0xff7fff00;
20753 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20754 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20755 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20756 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20758 put_thumb32_insn (buf
, newval
);
20761 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20762 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20763 if (value
< -255 || value
> 255)
20764 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20765 _("co-processor offset out of range"));
20767 goto cp_off_common
;
20769 case BFD_RELOC_ARM_THUMB_OFFSET
:
20770 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20771 /* Exactly what ranges, and where the offset is inserted depends
20772 on the type of instruction, we can establish this from the
20774 switch (newval
>> 12)
20776 case 4: /* PC load. */
20777 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20778 forced to zero for these loads; md_pcrel_from has already
20779 compensated for this. */
20781 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20782 _("invalid offset, target not word aligned (0x%08lX)"),
20783 (((unsigned long) fixP
->fx_frag
->fr_address
20784 + (unsigned long) fixP
->fx_where
) & ~3)
20785 + (unsigned long) value
);
20787 if (value
& ~0x3fc)
20788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20789 _("invalid offset, value too big (0x%08lX)"),
20792 newval
|= value
>> 2;
20795 case 9: /* SP load/store. */
20796 if (value
& ~0x3fc)
20797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20798 _("invalid offset, value too big (0x%08lX)"),
20800 newval
|= value
>> 2;
20803 case 6: /* Word load/store. */
20805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20806 _("invalid offset, value too big (0x%08lX)"),
20808 newval
|= value
<< 4; /* 6 - 2. */
20811 case 7: /* Byte load/store. */
20813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20814 _("invalid offset, value too big (0x%08lX)"),
20816 newval
|= value
<< 6;
20819 case 8: /* Halfword load/store. */
20821 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20822 _("invalid offset, value too big (0x%08lX)"),
20824 newval
|= value
<< 5; /* 6 - 1. */
20828 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20829 "Unable to process relocation for thumb opcode: %lx",
20830 (unsigned long) newval
);
20833 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20836 case BFD_RELOC_ARM_THUMB_ADD
:
20837 /* This is a complicated relocation, since we use it for all of
20838 the following immediate relocations:
20842 9bit ADD/SUB SP word-aligned
20843 10bit ADD PC/SP word-aligned
20845 The type of instruction being processed is encoded in the
20852 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20854 int rd
= (newval
>> 4) & 0xf;
20855 int rs
= newval
& 0xf;
20856 int subtract
= !!(newval
& 0x8000);
20858 /* Check for HI regs, only very restricted cases allowed:
20859 Adjusting SP, and using PC or SP to get an address. */
20860 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20861 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20862 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20863 _("invalid Hi register with immediate"));
20865 /* If value is negative, choose the opposite instruction. */
20869 subtract
= !subtract
;
20871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20872 _("immediate value out of range"));
20877 if (value
& ~0x1fc)
20878 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20879 _("invalid immediate for stack address calculation"));
20880 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20881 newval
|= value
>> 2;
20883 else if (rs
== REG_PC
|| rs
== REG_SP
)
20885 if (subtract
|| value
& ~0x3fc)
20886 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20887 _("invalid immediate for address calculation (value = 0x%08lX)"),
20888 (unsigned long) value
);
20889 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20891 newval
|= value
>> 2;
20896 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20897 _("immediate value out of range"));
20898 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20899 newval
|= (rd
<< 8) | value
;
20904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20905 _("immediate value out of range"));
20906 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20907 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20910 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20913 case BFD_RELOC_ARM_THUMB_IMM
:
20914 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20915 if (value
< 0 || value
> 255)
20916 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20917 _("invalid immediate: %ld is out of range"),
20920 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20923 case BFD_RELOC_ARM_THUMB_SHIFT
:
20924 /* 5bit shift value (0..32). LSL cannot take 32. */
20925 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20926 temp
= newval
& 0xf800;
20927 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20929 _("invalid shift value: %ld"), (long) value
);
20930 /* Shifts of zero must be encoded as LSL. */
20932 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20933 /* Shifts of 32 are encoded as zero. */
20934 else if (value
== 32)
20936 newval
|= value
<< 6;
20937 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20940 case BFD_RELOC_VTABLE_INHERIT
:
20941 case BFD_RELOC_VTABLE_ENTRY
:
20945 case BFD_RELOC_ARM_MOVW
:
20946 case BFD_RELOC_ARM_MOVT
:
20947 case BFD_RELOC_ARM_THUMB_MOVW
:
20948 case BFD_RELOC_ARM_THUMB_MOVT
:
20949 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20951 /* REL format relocations are limited to a 16-bit addend. */
20952 if (!fixP
->fx_done
)
20954 if (value
< -0x8000 || value
> 0x7fff)
20955 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20956 _("offset out of range"));
20958 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20959 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20964 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20965 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20967 newval
= get_thumb32_insn (buf
);
20968 newval
&= 0xfbf08f00;
20969 newval
|= (value
& 0xf000) << 4;
20970 newval
|= (value
& 0x0800) << 15;
20971 newval
|= (value
& 0x0700) << 4;
20972 newval
|= (value
& 0x00ff);
20973 put_thumb32_insn (buf
, newval
);
20977 newval
= md_chars_to_number (buf
, 4);
20978 newval
&= 0xfff0f000;
20979 newval
|= value
& 0x0fff;
20980 newval
|= (value
& 0xf000) << 4;
20981 md_number_to_chars (buf
, newval
, 4);
20986 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20987 case BFD_RELOC_ARM_ALU_PC_G0
:
20988 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20989 case BFD_RELOC_ARM_ALU_PC_G1
:
20990 case BFD_RELOC_ARM_ALU_PC_G2
:
20991 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20992 case BFD_RELOC_ARM_ALU_SB_G0
:
20993 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20994 case BFD_RELOC_ARM_ALU_SB_G1
:
20995 case BFD_RELOC_ARM_ALU_SB_G2
:
20996 gas_assert (!fixP
->fx_done
);
20997 if (!seg
->use_rela_p
)
21000 bfd_vma encoded_addend
;
21001 bfd_vma addend_abs
= abs (value
);
21003 /* Check that the absolute value of the addend can be
21004 expressed as an 8-bit constant plus a rotation. */
21005 encoded_addend
= encode_arm_immediate (addend_abs
);
21006 if (encoded_addend
== (unsigned int) FAIL
)
21007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21008 _("the offset 0x%08lX is not representable"),
21009 (unsigned long) addend_abs
);
21011 /* Extract the instruction. */
21012 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21014 /* If the addend is positive, use an ADD instruction.
21015 Otherwise use a SUB. Take care not to destroy the S bit. */
21016 insn
&= 0xff1fffff;
21022 /* Place the encoded addend into the first 12 bits of the
21024 insn
&= 0xfffff000;
21025 insn
|= encoded_addend
;
21027 /* Update the instruction. */
21028 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21032 case BFD_RELOC_ARM_LDR_PC_G0
:
21033 case BFD_RELOC_ARM_LDR_PC_G1
:
21034 case BFD_RELOC_ARM_LDR_PC_G2
:
21035 case BFD_RELOC_ARM_LDR_SB_G0
:
21036 case BFD_RELOC_ARM_LDR_SB_G1
:
21037 case BFD_RELOC_ARM_LDR_SB_G2
:
21038 gas_assert (!fixP
->fx_done
);
21039 if (!seg
->use_rela_p
)
21042 bfd_vma addend_abs
= abs (value
);
21044 /* Check that the absolute value of the addend can be
21045 encoded in 12 bits. */
21046 if (addend_abs
>= 0x1000)
21047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21048 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21049 (unsigned long) addend_abs
);
21051 /* Extract the instruction. */
21052 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21054 /* If the addend is negative, clear bit 23 of the instruction.
21055 Otherwise set it. */
21057 insn
&= ~(1 << 23);
21061 /* Place the absolute value of the addend into the first 12 bits
21062 of the instruction. */
21063 insn
&= 0xfffff000;
21064 insn
|= addend_abs
;
21066 /* Update the instruction. */
21067 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21071 case BFD_RELOC_ARM_LDRS_PC_G0
:
21072 case BFD_RELOC_ARM_LDRS_PC_G1
:
21073 case BFD_RELOC_ARM_LDRS_PC_G2
:
21074 case BFD_RELOC_ARM_LDRS_SB_G0
:
21075 case BFD_RELOC_ARM_LDRS_SB_G1
:
21076 case BFD_RELOC_ARM_LDRS_SB_G2
:
21077 gas_assert (!fixP
->fx_done
);
21078 if (!seg
->use_rela_p
)
21081 bfd_vma addend_abs
= abs (value
);
21083 /* Check that the absolute value of the addend can be
21084 encoded in 8 bits. */
21085 if (addend_abs
>= 0x100)
21086 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21087 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21088 (unsigned long) addend_abs
);
21090 /* Extract the instruction. */
21091 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21093 /* If the addend is negative, clear bit 23 of the instruction.
21094 Otherwise set it. */
21096 insn
&= ~(1 << 23);
21100 /* Place the first four bits of the absolute value of the addend
21101 into the first 4 bits of the instruction, and the remaining
21102 four into bits 8 .. 11. */
21103 insn
&= 0xfffff0f0;
21104 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21106 /* Update the instruction. */
21107 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21111 case BFD_RELOC_ARM_LDC_PC_G0
:
21112 case BFD_RELOC_ARM_LDC_PC_G1
:
21113 case BFD_RELOC_ARM_LDC_PC_G2
:
21114 case BFD_RELOC_ARM_LDC_SB_G0
:
21115 case BFD_RELOC_ARM_LDC_SB_G1
:
21116 case BFD_RELOC_ARM_LDC_SB_G2
:
21117 gas_assert (!fixP
->fx_done
);
21118 if (!seg
->use_rela_p
)
21121 bfd_vma addend_abs
= abs (value
);
21123 /* Check that the absolute value of the addend is a multiple of
21124 four and, when divided by four, fits in 8 bits. */
21125 if (addend_abs
& 0x3)
21126 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21127 _("bad offset 0x%08lX (must be word-aligned)"),
21128 (unsigned long) addend_abs
);
21130 if ((addend_abs
>> 2) > 0xff)
21131 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21132 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21133 (unsigned long) addend_abs
);
21135 /* Extract the instruction. */
21136 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21138 /* If the addend is negative, clear bit 23 of the instruction.
21139 Otherwise set it. */
21141 insn
&= ~(1 << 23);
21145 /* Place the addend (divided by four) into the first eight
21146 bits of the instruction. */
21147 insn
&= 0xfffffff0;
21148 insn
|= addend_abs
>> 2;
21150 /* Update the instruction. */
21151 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21155 case BFD_RELOC_ARM_V4BX
:
21156 /* This will need to go in the object file. */
21160 case BFD_RELOC_UNUSED
:
21162 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21163 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21167 /* Translate internal representation of relocation info to BFD target
21171 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21174 bfd_reloc_code_real_type code
;
21176 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21178 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21179 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21180 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21182 if (fixp
->fx_pcrel
)
21184 if (section
->use_rela_p
)
21185 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21187 fixp
->fx_offset
= reloc
->address
;
21189 reloc
->addend
= fixp
->fx_offset
;
21191 switch (fixp
->fx_r_type
)
21194 if (fixp
->fx_pcrel
)
21196 code
= BFD_RELOC_8_PCREL
;
21201 if (fixp
->fx_pcrel
)
21203 code
= BFD_RELOC_16_PCREL
;
21208 if (fixp
->fx_pcrel
)
21210 code
= BFD_RELOC_32_PCREL
;
21214 case BFD_RELOC_ARM_MOVW
:
21215 if (fixp
->fx_pcrel
)
21217 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21221 case BFD_RELOC_ARM_MOVT
:
21222 if (fixp
->fx_pcrel
)
21224 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21228 case BFD_RELOC_ARM_THUMB_MOVW
:
21229 if (fixp
->fx_pcrel
)
21231 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21235 case BFD_RELOC_ARM_THUMB_MOVT
:
21236 if (fixp
->fx_pcrel
)
21238 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21242 case BFD_RELOC_NONE
:
21243 case BFD_RELOC_ARM_PCREL_BRANCH
:
21244 case BFD_RELOC_ARM_PCREL_BLX
:
21245 case BFD_RELOC_RVA
:
21246 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21247 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21248 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21249 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21250 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21251 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21252 case BFD_RELOC_VTABLE_ENTRY
:
21253 case BFD_RELOC_VTABLE_INHERIT
:
21255 case BFD_RELOC_32_SECREL
:
21257 code
= fixp
->fx_r_type
;
21260 case BFD_RELOC_THUMB_PCREL_BLX
:
21262 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21263 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21266 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21269 case BFD_RELOC_ARM_LITERAL
:
21270 case BFD_RELOC_ARM_HWLITERAL
:
21271 /* If this is called then the a literal has
21272 been referenced across a section boundary. */
21273 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21274 _("literal referenced across section boundary"));
21278 case BFD_RELOC_ARM_GOT32
:
21279 case BFD_RELOC_ARM_GOTOFF
:
21280 case BFD_RELOC_ARM_GOT_PREL
:
21281 case BFD_RELOC_ARM_PLT32
:
21282 case BFD_RELOC_ARM_TARGET1
:
21283 case BFD_RELOC_ARM_ROSEGREL32
:
21284 case BFD_RELOC_ARM_SBREL32
:
21285 case BFD_RELOC_ARM_PREL31
:
21286 case BFD_RELOC_ARM_TARGET2
:
21287 case BFD_RELOC_ARM_TLS_LE32
:
21288 case BFD_RELOC_ARM_TLS_LDO32
:
21289 case BFD_RELOC_ARM_PCREL_CALL
:
21290 case BFD_RELOC_ARM_PCREL_JUMP
:
21291 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21292 case BFD_RELOC_ARM_ALU_PC_G0
:
21293 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21294 case BFD_RELOC_ARM_ALU_PC_G1
:
21295 case BFD_RELOC_ARM_ALU_PC_G2
:
21296 case BFD_RELOC_ARM_LDR_PC_G0
:
21297 case BFD_RELOC_ARM_LDR_PC_G1
:
21298 case BFD_RELOC_ARM_LDR_PC_G2
:
21299 case BFD_RELOC_ARM_LDRS_PC_G0
:
21300 case BFD_RELOC_ARM_LDRS_PC_G1
:
21301 case BFD_RELOC_ARM_LDRS_PC_G2
:
21302 case BFD_RELOC_ARM_LDC_PC_G0
:
21303 case BFD_RELOC_ARM_LDC_PC_G1
:
21304 case BFD_RELOC_ARM_LDC_PC_G2
:
21305 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21306 case BFD_RELOC_ARM_ALU_SB_G0
:
21307 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21308 case BFD_RELOC_ARM_ALU_SB_G1
:
21309 case BFD_RELOC_ARM_ALU_SB_G2
:
21310 case BFD_RELOC_ARM_LDR_SB_G0
:
21311 case BFD_RELOC_ARM_LDR_SB_G1
:
21312 case BFD_RELOC_ARM_LDR_SB_G2
:
21313 case BFD_RELOC_ARM_LDRS_SB_G0
:
21314 case BFD_RELOC_ARM_LDRS_SB_G1
:
21315 case BFD_RELOC_ARM_LDRS_SB_G2
:
21316 case BFD_RELOC_ARM_LDC_SB_G0
:
21317 case BFD_RELOC_ARM_LDC_SB_G1
:
21318 case BFD_RELOC_ARM_LDC_SB_G2
:
21319 case BFD_RELOC_ARM_V4BX
:
21320 code
= fixp
->fx_r_type
;
21323 case BFD_RELOC_ARM_TLS_GD32
:
21324 case BFD_RELOC_ARM_TLS_IE32
:
21325 case BFD_RELOC_ARM_TLS_LDM32
:
21326 /* BFD will include the symbol's address in the addend.
21327 But we don't want that, so subtract it out again here. */
21328 if (!S_IS_COMMON (fixp
->fx_addsy
))
21329 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21330 code
= fixp
->fx_r_type
;
21334 case BFD_RELOC_ARM_IMMEDIATE
:
21335 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21336 _("internal relocation (type: IMMEDIATE) not fixed up"));
21339 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21340 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21341 _("ADRL used for a symbol not defined in the same file"));
21344 case BFD_RELOC_ARM_OFFSET_IMM
:
21345 if (section
->use_rela_p
)
21347 code
= fixp
->fx_r_type
;
21351 if (fixp
->fx_addsy
!= NULL
21352 && !S_IS_DEFINED (fixp
->fx_addsy
)
21353 && S_IS_LOCAL (fixp
->fx_addsy
))
21355 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21356 _("undefined local label `%s'"),
21357 S_GET_NAME (fixp
->fx_addsy
));
21361 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21362 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21369 switch (fixp
->fx_r_type
)
21371 case BFD_RELOC_NONE
: type
= "NONE"; break;
21372 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21373 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21374 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21375 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21376 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21377 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21378 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21379 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21380 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21381 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21382 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21383 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21384 default: type
= _("<unknown>"); break;
21386 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21387 _("cannot represent %s relocation in this object file format"),
21394 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21396 && fixp
->fx_addsy
== GOT_symbol
)
21398 code
= BFD_RELOC_ARM_GOTPC
;
21399 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21403 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21405 if (reloc
->howto
== NULL
)
21407 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21408 _("cannot represent %s relocation in this object file format"),
21409 bfd_get_reloc_code_name (code
));
21413 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21414 vtable entry to be used in the relocation's section offset. */
21415 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21416 reloc
->address
= fixp
->fx_offset
;
21421 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21424 cons_fix_new_arm (fragS
* frag
,
21429 bfd_reloc_code_real_type type
;
21433 FIXME: @@ Should look at CPU word size. */
21437 type
= BFD_RELOC_8
;
21440 type
= BFD_RELOC_16
;
21444 type
= BFD_RELOC_32
;
21447 type
= BFD_RELOC_64
;
21452 if (exp
->X_op
== O_secrel
)
21454 exp
->X_op
= O_symbol
;
21455 type
= BFD_RELOC_32_SECREL
;
21459 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21462 #if defined (OBJ_COFF)
21464 arm_validate_fix (fixS
* fixP
)
21466 /* If the destination of the branch is a defined symbol which does not have
21467 the THUMB_FUNC attribute, then we must be calling a function which has
21468 the (interfacearm) attribute. We look for the Thumb entry point to that
21469 function and change the branch to refer to that function instead. */
21470 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21471 && fixP
->fx_addsy
!= NULL
21472 && S_IS_DEFINED (fixP
->fx_addsy
)
21473 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21475 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21482 arm_force_relocation (struct fix
* fixp
)
21484 #if defined (OBJ_COFF) && defined (TE_PE)
21485 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21489 /* In case we have a call or a branch to a function in ARM ISA mode from
21490 a thumb function or vice-versa force the relocation. These relocations
21491 are cleared off for some cores that might have blx and simple transformations
21495 switch (fixp
->fx_r_type
)
21497 case BFD_RELOC_ARM_PCREL_JUMP
:
21498 case BFD_RELOC_ARM_PCREL_CALL
:
21499 case BFD_RELOC_THUMB_PCREL_BLX
:
21500 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21504 case BFD_RELOC_ARM_PCREL_BLX
:
21505 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21506 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21507 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21508 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21517 /* Resolve these relocations even if the symbol is extern or weak. */
21518 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21519 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21520 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21521 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21522 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21523 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21524 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21527 /* Always leave these relocations for the linker. */
21528 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21529 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21530 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21533 /* Always generate relocations against function symbols. */
21534 if (fixp
->fx_r_type
== BFD_RELOC_32
21536 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21539 return generic_force_reloc (fixp
);
21542 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21543 /* Relocations against function names must be left unadjusted,
21544 so that the linker can use this information to generate interworking
21545 stubs. The MIPS version of this function
21546 also prevents relocations that are mips-16 specific, but I do not
21547 know why it does this.
21550 There is one other problem that ought to be addressed here, but
21551 which currently is not: Taking the address of a label (rather
21552 than a function) and then later jumping to that address. Such
21553 addresses also ought to have their bottom bit set (assuming that
21554 they reside in Thumb code), but at the moment they will not. */
21557 arm_fix_adjustable (fixS
* fixP
)
21559 if (fixP
->fx_addsy
== NULL
)
21562 /* Preserve relocations against symbols with function type. */
21563 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21566 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21567 && fixP
->fx_subsy
== NULL
)
21570 /* We need the symbol name for the VTABLE entries. */
21571 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21572 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21575 /* Don't allow symbols to be discarded on GOT related relocs. */
21576 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21577 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21578 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21579 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21580 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21581 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21582 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21583 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21584 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21587 /* Similarly for group relocations. */
21588 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21589 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21590 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21593 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21594 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21595 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21596 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21597 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21598 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21599 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21600 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21601 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21606 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21611 elf32_arm_target_format (void)
21614 return (target_big_endian
21615 ? "elf32-bigarm-symbian"
21616 : "elf32-littlearm-symbian");
21617 #elif defined (TE_VXWORKS)
21618 return (target_big_endian
21619 ? "elf32-bigarm-vxworks"
21620 : "elf32-littlearm-vxworks");
21622 if (target_big_endian
)
21623 return "elf32-bigarm";
21625 return "elf32-littlearm";
21630 armelf_frob_symbol (symbolS
* symp
,
21633 elf_frob_symbol (symp
, puntp
);
21637 /* MD interface: Finalization. */
21642 literal_pool
* pool
;
21644 /* Ensure that all the IT blocks are properly closed. */
21645 check_it_blocks_finished ();
21647 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21649 /* Put it at the end of the relevant section. */
21650 subseg_set (pool
->section
, pool
->sub_section
);
21652 arm_elf_change_section ();
21659 /* Remove any excess mapping symbols generated for alignment frags in
21660 SEC. We may have created a mapping symbol before a zero byte
21661 alignment; remove it if there's a mapping symbol after the
21664 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21665 void *dummy ATTRIBUTE_UNUSED
)
21667 segment_info_type
*seginfo
= seg_info (sec
);
21670 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21673 for (fragp
= seginfo
->frchainP
->frch_root
;
21675 fragp
= fragp
->fr_next
)
21677 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21678 fragS
*next
= fragp
->fr_next
;
21680 /* Variable-sized frags have been converted to fixed size by
21681 this point. But if this was variable-sized to start with,
21682 there will be a fixed-size frag after it. So don't handle
21684 if (sym
== NULL
|| next
== NULL
)
21687 if (S_GET_VALUE (sym
) < next
->fr_address
)
21688 /* Not at the end of this frag. */
21690 know (S_GET_VALUE (sym
) == next
->fr_address
);
21694 if (next
->tc_frag_data
.first_map
!= NULL
)
21696 /* Next frag starts with a mapping symbol. Discard this
21698 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21702 if (next
->fr_next
== NULL
)
21704 /* This mapping symbol is at the end of the section. Discard
21706 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21707 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21711 /* As long as we have empty frags without any mapping symbols,
21713 /* If the next frag is non-empty and does not start with a
21714 mapping symbol, then this mapping symbol is required. */
21715 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21718 next
= next
->fr_next
;
21720 while (next
!= NULL
);
21725 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21729 arm_adjust_symtab (void)
21734 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21736 if (ARM_IS_THUMB (sym
))
21738 if (THUMB_IS_FUNC (sym
))
21740 /* Mark the symbol as a Thumb function. */
21741 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21742 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21743 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21745 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21746 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21748 as_bad (_("%s: unexpected function type: %d"),
21749 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21751 else switch (S_GET_STORAGE_CLASS (sym
))
21754 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21757 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21760 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21768 if (ARM_IS_INTERWORK (sym
))
21769 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21776 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21778 if (ARM_IS_THUMB (sym
))
21780 elf_symbol_type
* elf_sym
;
21782 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21783 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21785 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21786 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21788 /* If it's a .thumb_func, declare it as so,
21789 otherwise tag label as .code 16. */
21790 if (THUMB_IS_FUNC (sym
))
21791 elf_sym
->internal_elf_sym
.st_info
=
21792 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21793 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21794 elf_sym
->internal_elf_sym
.st_info
=
21795 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21800 /* Remove any overlapping mapping symbols generated by alignment frags. */
21801 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21805 /* MD interface: Initialization. */
21808 set_constant_flonums (void)
21812 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21813 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21817 /* Auto-select Thumb mode if it's the only available instruction set for the
21818 given architecture. */
21821 autoselect_thumb_from_cpu_variant (void)
21823 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21824 opcode_select (16);
21833 if ( (arm_ops_hsh
= hash_new ()) == NULL
21834 || (arm_cond_hsh
= hash_new ()) == NULL
21835 || (arm_shift_hsh
= hash_new ()) == NULL
21836 || (arm_psr_hsh
= hash_new ()) == NULL
21837 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21838 || (arm_reg_hsh
= hash_new ()) == NULL
21839 || (arm_reloc_hsh
= hash_new ()) == NULL
21840 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21841 as_fatal (_("virtual memory exhausted"));
21843 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21844 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21845 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21846 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21847 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21848 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21849 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21850 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21851 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21852 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21853 (void *) (v7m_psrs
+ i
));
21854 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21855 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21857 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21859 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21860 (void *) (barrier_opt_names
+ i
));
21862 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21863 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21866 set_constant_flonums ();
21868 /* Set the cpu variant based on the command-line options. We prefer
21869 -mcpu= over -march= if both are set (as for GCC); and we prefer
21870 -mfpu= over any other way of setting the floating point unit.
21871 Use of legacy options with new options are faulted. */
21874 if (mcpu_cpu_opt
|| march_cpu_opt
)
21875 as_bad (_("use of old and new-style options to set CPU type"));
21877 mcpu_cpu_opt
= legacy_cpu
;
21879 else if (!mcpu_cpu_opt
)
21880 mcpu_cpu_opt
= march_cpu_opt
;
21885 as_bad (_("use of old and new-style options to set FPU type"));
21887 mfpu_opt
= legacy_fpu
;
21889 else if (!mfpu_opt
)
21891 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21892 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21893 /* Some environments specify a default FPU. If they don't, infer it
21894 from the processor. */
21896 mfpu_opt
= mcpu_fpu_opt
;
21898 mfpu_opt
= march_fpu_opt
;
21900 mfpu_opt
= &fpu_default
;
21906 if (mcpu_cpu_opt
!= NULL
)
21907 mfpu_opt
= &fpu_default
;
21908 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21909 mfpu_opt
= &fpu_arch_vfp_v2
;
21911 mfpu_opt
= &fpu_arch_fpa
;
21917 mcpu_cpu_opt
= &cpu_default
;
21918 selected_cpu
= cpu_default
;
21922 selected_cpu
= *mcpu_cpu_opt
;
21924 mcpu_cpu_opt
= &arm_arch_any
;
21927 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21929 autoselect_thumb_from_cpu_variant ();
21931 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21933 #if defined OBJ_COFF || defined OBJ_ELF
21935 unsigned int flags
= 0;
21937 #if defined OBJ_ELF
21938 flags
= meabi_flags
;
21940 switch (meabi_flags
)
21942 case EF_ARM_EABI_UNKNOWN
:
21944 /* Set the flags in the private structure. */
21945 if (uses_apcs_26
) flags
|= F_APCS26
;
21946 if (support_interwork
) flags
|= F_INTERWORK
;
21947 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21948 if (pic_code
) flags
|= F_PIC
;
21949 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21950 flags
|= F_SOFT_FLOAT
;
21952 switch (mfloat_abi_opt
)
21954 case ARM_FLOAT_ABI_SOFT
:
21955 case ARM_FLOAT_ABI_SOFTFP
:
21956 flags
|= F_SOFT_FLOAT
;
21959 case ARM_FLOAT_ABI_HARD
:
21960 if (flags
& F_SOFT_FLOAT
)
21961 as_bad (_("hard-float conflicts with specified fpu"));
21965 /* Using pure-endian doubles (even if soft-float). */
21966 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21967 flags
|= F_VFP_FLOAT
;
21969 #if defined OBJ_ELF
21970 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21971 flags
|= EF_ARM_MAVERICK_FLOAT
;
21974 case EF_ARM_EABI_VER4
:
21975 case EF_ARM_EABI_VER5
:
21976 /* No additional flags to set. */
21983 bfd_set_private_flags (stdoutput
, flags
);
21985 /* We have run out flags in the COFF header to encode the
21986 status of ATPCS support, so instead we create a dummy,
21987 empty, debug section called .arm.atpcs. */
21992 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21996 bfd_set_section_flags
21997 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21998 bfd_set_section_size (stdoutput
, sec
, 0);
21999 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22005 /* Record the CPU type as well. */
22006 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22007 mach
= bfd_mach_arm_iWMMXt2
;
22008 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22009 mach
= bfd_mach_arm_iWMMXt
;
22010 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22011 mach
= bfd_mach_arm_XScale
;
22012 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22013 mach
= bfd_mach_arm_ep9312
;
22014 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22015 mach
= bfd_mach_arm_5TE
;
22016 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22018 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22019 mach
= bfd_mach_arm_5T
;
22021 mach
= bfd_mach_arm_5
;
22023 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22025 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22026 mach
= bfd_mach_arm_4T
;
22028 mach
= bfd_mach_arm_4
;
22030 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22031 mach
= bfd_mach_arm_3M
;
22032 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22033 mach
= bfd_mach_arm_3
;
22034 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22035 mach
= bfd_mach_arm_2a
;
22036 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22037 mach
= bfd_mach_arm_2
;
22039 mach
= bfd_mach_arm_unknown
;
22041 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22044 /* Command line processing. */
22047 Invocation line includes a switch not recognized by the base assembler.
22048 See if it's a processor-specific option.
22050 This routine is somewhat complicated by the need for backwards
22051 compatibility (since older releases of gcc can't be changed).
22052 The new options try to make the interface as compatible as
22055 New options (supported) are:
22057 -mcpu=<cpu name> Assemble for selected processor
22058 -march=<architecture name> Assemble for selected architecture
22059 -mfpu=<fpu architecture> Assemble for selected FPU.
22060 -EB/-mbig-endian Big-endian
22061 -EL/-mlittle-endian Little-endian
22062 -k Generate PIC code
22063 -mthumb Start in Thumb mode
22064 -mthumb-interwork Code supports ARM/Thumb interworking
22066 -m[no-]warn-deprecated Warn about deprecated features
22068 For now we will also provide support for:
22070 -mapcs-32 32-bit Program counter
22071 -mapcs-26 26-bit Program counter
22072 -macps-float Floats passed in FP registers
22073 -mapcs-reentrant Reentrant code
22075 (sometime these will probably be replaced with -mapcs=<list of options>
22076 and -matpcs=<list of options>)
22078 The remaining options are only supported for back-wards compatibility.
22079 Cpu variants, the arm part is optional:
22080 -m[arm]1 Currently not supported.
22081 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22082 -m[arm]3 Arm 3 processor
22083 -m[arm]6[xx], Arm 6 processors
22084 -m[arm]7[xx][t][[d]m] Arm 7 processors
22085 -m[arm]8[10] Arm 8 processors
22086 -m[arm]9[20][tdmi] Arm 9 processors
22087 -mstrongarm[110[0]] StrongARM processors
22088 -mxscale XScale processors
22089 -m[arm]v[2345[t[e]]] Arm architectures
22090 -mall All (except the ARM1)
22092 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22093 -mfpe-old (No float load/store multiples)
22094 -mvfpxd VFP Single precision
22096 -mno-fpu Disable all floating point instructions
22098 The following CPU names are recognized:
22099 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22100 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22101 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22102 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22103 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22104 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22105 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22109 const char * md_shortopts
= "m:k";
22111 #ifdef ARM_BI_ENDIAN
22112 #define OPTION_EB (OPTION_MD_BASE + 0)
22113 #define OPTION_EL (OPTION_MD_BASE + 1)
22115 #if TARGET_BYTES_BIG_ENDIAN
22116 #define OPTION_EB (OPTION_MD_BASE + 0)
22118 #define OPTION_EL (OPTION_MD_BASE + 1)
22121 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22123 struct option md_longopts
[] =
22126 {"EB", no_argument
, NULL
, OPTION_EB
},
22129 {"EL", no_argument
, NULL
, OPTION_EL
},
22131 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22132 {NULL
, no_argument
, NULL
, 0}
22135 size_t md_longopts_size
= sizeof (md_longopts
);
22137 struct arm_option_table
22139 char *option
; /* Option name to match. */
22140 char *help
; /* Help information. */
22141 int *var
; /* Variable to change. */
22142 int value
; /* What to change it to. */
22143 char *deprecated
; /* If non-null, print this message. */
22146 struct arm_option_table arm_opts
[] =
22148 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22149 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22150 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22151 &support_interwork
, 1, NULL
},
22152 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22153 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22154 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22156 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22157 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22158 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22159 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22162 /* These are recognized by the assembler, but have no affect on code. */
22163 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22164 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22166 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22167 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22168 &warn_on_deprecated
, 0, NULL
},
22169 {NULL
, NULL
, NULL
, 0, NULL
}
22172 struct arm_legacy_option_table
22174 char *option
; /* Option name to match. */
22175 const arm_feature_set
**var
; /* Variable to change. */
22176 const arm_feature_set value
; /* What to change it to. */
22177 char *deprecated
; /* If non-null, print this message. */
22180 const struct arm_legacy_option_table arm_legacy_opts
[] =
22182 /* DON'T add any new processors to this list -- we want the whole list
22183 to go away... Add them to the processors table instead. */
22184 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22185 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22186 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22187 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22188 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22189 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22190 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22191 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22192 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22193 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22194 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22195 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22196 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22197 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22198 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22199 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22200 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22201 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22202 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22203 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22204 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22205 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22206 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22207 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22208 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22209 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22210 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22211 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22212 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22213 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22214 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22215 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22216 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22217 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22218 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22219 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22220 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22221 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22222 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22223 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22224 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22225 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22226 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22227 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22228 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22229 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22230 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22231 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22232 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22233 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22234 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22235 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22236 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22237 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22238 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22239 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22240 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22241 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22242 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22243 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22244 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22245 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22246 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22247 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22248 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22249 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22250 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22251 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22252 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22253 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22254 N_("use -mcpu=strongarm110")},
22255 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22256 N_("use -mcpu=strongarm1100")},
22257 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22258 N_("use -mcpu=strongarm1110")},
22259 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22260 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22261 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22263 /* Architecture variants -- don't add any more to this list either. */
22264 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22265 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22266 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22267 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22268 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22269 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22270 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22271 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22272 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22273 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22274 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22275 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22276 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22277 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22278 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22279 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22280 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22281 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22283 /* Floating point variants -- don't add any more to this list either. */
22284 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22285 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22286 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22287 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22288 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22290 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22293 struct arm_cpu_option_table
22296 const arm_feature_set value
;
22297 /* For some CPUs we assume an FPU unless the user explicitly sets
22299 const arm_feature_set default_fpu
;
22300 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22302 const char *canonical_name
;
22305 /* This list should, at a minimum, contain all the cpu names
22306 recognized by GCC. */
22307 static const struct arm_cpu_option_table arm_cpus
[] =
22309 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22310 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22311 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22312 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22313 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22314 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22315 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22316 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22317 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22318 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22319 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22320 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22321 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22322 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22323 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22324 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22325 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22326 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22327 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22328 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22329 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22330 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22331 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22332 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22333 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22334 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22335 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22336 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22337 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22338 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22339 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22340 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22341 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22342 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22343 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22344 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22345 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22346 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22347 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22348 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22349 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22350 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22351 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22352 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22353 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22354 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22355 /* For V5 or later processors we default to using VFP; but the user
22356 should really set the FPU type explicitly. */
22357 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22358 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22359 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22360 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22361 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22362 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22363 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22364 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22365 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22366 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22367 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22368 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22369 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22370 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22371 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22372 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22373 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22374 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22375 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22376 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22377 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22378 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22379 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22380 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22381 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22382 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22383 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22384 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22385 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22386 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22387 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22388 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22389 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22390 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22391 FPU_NONE
, "Cortex-A5"},
22392 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22393 ARM_FEATURE (0, FPU_VFP_V3
22394 | FPU_NEON_EXT_V1
),
22396 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22397 ARM_FEATURE (0, FPU_VFP_V3
22398 | FPU_NEON_EXT_V1
),
22400 {"cortex-a15", ARM_ARCH_V7A_MP_SEC
,
22401 FPU_ARCH_NEON_VFP_V4
,
22403 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22404 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22406 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22407 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22408 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, "Cortex-M1"},
22409 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, "Cortex-M0"},
22410 /* ??? XSCALE is really an architecture. */
22411 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22412 /* ??? iwmmxt is not a processor. */
22413 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22414 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22415 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22417 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22418 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22421 struct arm_arch_option_table
22424 const arm_feature_set value
;
22425 const arm_feature_set default_fpu
;
22428 /* This list should, at a minimum, contain all the architecture names
22429 recognized by GCC. */
22430 static const struct arm_arch_option_table arm_archs
[] =
22432 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22433 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22434 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22435 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22436 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22437 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22438 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22439 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22440 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22441 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22442 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22443 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22444 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22445 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22446 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22447 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22448 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22449 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22450 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22451 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22452 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22453 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22454 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22455 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22456 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22457 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22458 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22459 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22460 /* The official spelling of the ARMv7 profile variants is the dashed form.
22461 Accept the non-dashed form for compatibility with old toolchains. */
22462 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22463 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22464 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22465 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22466 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22467 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22468 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22469 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22470 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22471 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22472 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22475 /* ISA extensions in the co-processor and main instruction set space. */
22476 struct arm_option_extension_value_table
22479 const arm_feature_set value
;
22480 const arm_feature_set allowed_archs
;
22483 /* The following table must be in alphabetical order with a NULL last entry.
22485 static const struct arm_option_extension_value_table arm_extensions
[] =
22487 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
22488 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
22489 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
22490 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
22491 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22492 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
22493 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
22494 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
22495 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22498 /* ISA floating-point and Advanced SIMD extensions. */
22499 struct arm_option_fpu_value_table
22502 const arm_feature_set value
;
22505 /* This list should, at a minimum, contain all the fpu names
22506 recognized by GCC. */
22507 static const struct arm_option_fpu_value_table arm_fpus
[] =
22509 {"softfpa", FPU_NONE
},
22510 {"fpe", FPU_ARCH_FPE
},
22511 {"fpe2", FPU_ARCH_FPE
},
22512 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22513 {"fpa", FPU_ARCH_FPA
},
22514 {"fpa10", FPU_ARCH_FPA
},
22515 {"fpa11", FPU_ARCH_FPA
},
22516 {"arm7500fe", FPU_ARCH_FPA
},
22517 {"softvfp", FPU_ARCH_VFP
},
22518 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22519 {"vfp", FPU_ARCH_VFP_V2
},
22520 {"vfp9", FPU_ARCH_VFP_V2
},
22521 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22522 {"vfp10", FPU_ARCH_VFP_V2
},
22523 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22524 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22525 {"vfpv2", FPU_ARCH_VFP_V2
},
22526 {"vfpv3", FPU_ARCH_VFP_V3
},
22527 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22528 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22529 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22530 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22531 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22532 {"arm1020t", FPU_ARCH_VFP_V1
},
22533 {"arm1020e", FPU_ARCH_VFP_V2
},
22534 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22535 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22536 {"maverick", FPU_ARCH_MAVERICK
},
22537 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22538 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22539 {"vfpv4", FPU_ARCH_VFP_V4
},
22540 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22541 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22542 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22543 {NULL
, ARM_ARCH_NONE
}
22546 struct arm_option_value_table
22552 static const struct arm_option_value_table arm_float_abis
[] =
22554 {"hard", ARM_FLOAT_ABI_HARD
},
22555 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22556 {"soft", ARM_FLOAT_ABI_SOFT
},
22561 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22562 static const struct arm_option_value_table arm_eabis
[] =
22564 {"gnu", EF_ARM_EABI_UNKNOWN
},
22565 {"4", EF_ARM_EABI_VER4
},
22566 {"5", EF_ARM_EABI_VER5
},
22571 struct arm_long_option_table
22573 char * option
; /* Substring to match. */
22574 char * help
; /* Help information. */
22575 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22576 char * deprecated
; /* If non-null, print this message. */
22580 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22582 arm_feature_set
*ext_set
= (arm_feature_set
*)
22583 xmalloc (sizeof (arm_feature_set
));
22585 /* We insist on extensions being specified in alphabetical order, and with
22586 extensions being added before being removed. We achieve this by having
22587 the global ARM_EXTENSIONS table in alphabetical order, and using the
22588 ADDING_VALUE variable to indicate whether we are adding an extension (1)
22589 or removing it (0) and only allowing it to change in the order
22591 const struct arm_option_extension_value_table
* opt
= NULL
;
22592 int adding_value
= -1;
22594 /* Copy the feature set, so that we can modify it. */
22595 *ext_set
= **opt_p
;
22598 while (str
!= NULL
&& *str
!= 0)
22605 as_bad (_("invalid architectural extension"));
22610 ext
= strchr (str
, '+');
22613 optlen
= ext
- str
;
22615 optlen
= strlen (str
);
22618 && strncmp (str
, "no", 2) == 0)
22620 if (adding_value
!= 0)
22623 opt
= arm_extensions
;
22629 else if (optlen
> 0)
22631 if (adding_value
== -1)
22634 opt
= arm_extensions
;
22636 else if (adding_value
!= 1)
22638 as_bad (_("must specify extensions to add before specifying "
22639 "those to remove"));
22646 as_bad (_("missing architectural extension"));
22650 gas_assert (adding_value
!= -1);
22651 gas_assert (opt
!= NULL
);
22653 /* Scan over the options table trying to find an exact match. */
22654 for (; opt
->name
!= NULL
; opt
++)
22655 if (strncmp (opt
->name
, str
, optlen
) == 0
22656 && strlen (opt
->name
) == optlen
)
22658 /* Check we can apply the extension to this architecture. */
22659 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
22661 as_bad (_("extension does not apply to the base architecture"));
22665 /* Add or remove the extension. */
22667 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22669 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
22674 if (opt
->name
== NULL
)
22676 /* Did we fail to find an extension because it wasn't specified in
22677 alphabetical order, or because it does not exist? */
22679 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22680 if (strncmp (opt
->name
, str
, optlen
) == 0)
22683 if (opt
->name
== NULL
)
22684 as_bad (_("unknown architectural extension `%s'"), str
);
22686 as_bad (_("architectural extensions must be specified in "
22687 "alphabetical order"));
22693 /* We should skip the extension we've just matched the next time
22705 arm_parse_cpu (char * str
)
22707 const struct arm_cpu_option_table
* opt
;
22708 char * ext
= strchr (str
, '+');
22712 optlen
= ext
- str
;
22714 optlen
= strlen (str
);
22718 as_bad (_("missing cpu name `%s'"), str
);
22722 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22723 if (strncmp (opt
->name
, str
, optlen
) == 0)
22725 mcpu_cpu_opt
= &opt
->value
;
22726 mcpu_fpu_opt
= &opt
->default_fpu
;
22727 if (opt
->canonical_name
)
22728 strcpy (selected_cpu_name
, opt
->canonical_name
);
22733 for (i
= 0; i
< optlen
; i
++)
22734 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22735 selected_cpu_name
[i
] = 0;
22739 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22744 as_bad (_("unknown cpu `%s'"), str
);
22749 arm_parse_arch (char * str
)
22751 const struct arm_arch_option_table
*opt
;
22752 char *ext
= strchr (str
, '+');
22756 optlen
= ext
- str
;
22758 optlen
= strlen (str
);
22762 as_bad (_("missing architecture name `%s'"), str
);
22766 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22767 if (strncmp (opt
->name
, str
, optlen
) == 0)
22769 march_cpu_opt
= &opt
->value
;
22770 march_fpu_opt
= &opt
->default_fpu
;
22771 strcpy (selected_cpu_name
, opt
->name
);
22774 return arm_parse_extension (ext
, &march_cpu_opt
);
22779 as_bad (_("unknown architecture `%s'\n"), str
);
22784 arm_parse_fpu (char * str
)
22786 const struct arm_option_fpu_value_table
* opt
;
22788 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22789 if (streq (opt
->name
, str
))
22791 mfpu_opt
= &opt
->value
;
22795 as_bad (_("unknown floating point format `%s'\n"), str
);
22800 arm_parse_float_abi (char * str
)
22802 const struct arm_option_value_table
* opt
;
22804 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22805 if (streq (opt
->name
, str
))
22807 mfloat_abi_opt
= opt
->value
;
22811 as_bad (_("unknown floating point abi `%s'\n"), str
);
22817 arm_parse_eabi (char * str
)
22819 const struct arm_option_value_table
*opt
;
22821 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22822 if (streq (opt
->name
, str
))
22824 meabi_flags
= opt
->value
;
22827 as_bad (_("unknown EABI `%s'\n"), str
);
22833 arm_parse_it_mode (char * str
)
22835 bfd_boolean ret
= TRUE
;
22837 if (streq ("arm", str
))
22838 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22839 else if (streq ("thumb", str
))
22840 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22841 else if (streq ("always", str
))
22842 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22843 else if (streq ("never", str
))
22844 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22847 as_bad (_("unknown implicit IT mode `%s', should be "\
22848 "arm, thumb, always, or never."), str
);
22855 struct arm_long_option_table arm_long_opts
[] =
22857 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22858 arm_parse_cpu
, NULL
},
22859 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22860 arm_parse_arch
, NULL
},
22861 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22862 arm_parse_fpu
, NULL
},
22863 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22864 arm_parse_float_abi
, NULL
},
22866 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22867 arm_parse_eabi
, NULL
},
22869 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22870 arm_parse_it_mode
, NULL
},
22871 {NULL
, NULL
, 0, NULL
}
22875 md_parse_option (int c
, char * arg
)
22877 struct arm_option_table
*opt
;
22878 const struct arm_legacy_option_table
*fopt
;
22879 struct arm_long_option_table
*lopt
;
22885 target_big_endian
= 1;
22891 target_big_endian
= 0;
22895 case OPTION_FIX_V4BX
:
22900 /* Listing option. Just ignore these, we don't support additional
22905 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22907 if (c
== opt
->option
[0]
22908 && ((arg
== NULL
&& opt
->option
[1] == 0)
22909 || streq (arg
, opt
->option
+ 1)))
22911 /* If the option is deprecated, tell the user. */
22912 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22913 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22914 arg
? arg
: "", _(opt
->deprecated
));
22916 if (opt
->var
!= NULL
)
22917 *opt
->var
= opt
->value
;
22923 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22925 if (c
== fopt
->option
[0]
22926 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22927 || streq (arg
, fopt
->option
+ 1)))
22929 /* If the option is deprecated, tell the user. */
22930 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22931 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22932 arg
? arg
: "", _(fopt
->deprecated
));
22934 if (fopt
->var
!= NULL
)
22935 *fopt
->var
= &fopt
->value
;
22941 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22943 /* These options are expected to have an argument. */
22944 if (c
== lopt
->option
[0]
22946 && strncmp (arg
, lopt
->option
+ 1,
22947 strlen (lopt
->option
+ 1)) == 0)
22949 /* If the option is deprecated, tell the user. */
22950 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22951 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22952 _(lopt
->deprecated
));
22954 /* Call the sup-option parser. */
22955 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22966 md_show_usage (FILE * fp
)
22968 struct arm_option_table
*opt
;
22969 struct arm_long_option_table
*lopt
;
22971 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22973 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22974 if (opt
->help
!= NULL
)
22975 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22977 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22978 if (lopt
->help
!= NULL
)
22979 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22983 -EB assemble code for a big-endian cpu\n"));
22988 -EL assemble code for a little-endian cpu\n"));
22992 --fix-v4bx Allow BX in ARMv4 code\n"));
23000 arm_feature_set flags
;
23001 } cpu_arch_ver_table
;
23003 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23004 least features first. */
23005 static const cpu_arch_ver_table cpu_arch_ver
[] =
23011 {4, ARM_ARCH_V5TE
},
23012 {5, ARM_ARCH_V5TEJ
},
23016 {11, ARM_ARCH_V6M
},
23017 {8, ARM_ARCH_V6T2
},
23018 {10, ARM_ARCH_V7A
},
23019 {10, ARM_ARCH_V7R
},
23020 {10, ARM_ARCH_V7M
},
23024 /* Set an attribute if it has not already been set by the user. */
23026 aeabi_set_attribute_int (int tag
, int value
)
23029 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23030 || !attributes_set_explicitly
[tag
])
23031 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23035 aeabi_set_attribute_string (int tag
, const char *value
)
23038 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23039 || !attributes_set_explicitly
[tag
])
23040 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23043 /* Set the public EABI object attributes. */
23045 aeabi_set_public_attributes (void)
23048 arm_feature_set flags
;
23049 arm_feature_set tmp
;
23050 const cpu_arch_ver_table
*p
;
23052 /* Choose the architecture based on the capabilities of the requested cpu
23053 (if any) and/or the instructions actually used. */
23054 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23055 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23056 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23057 /*Allow the user to override the reported architecture. */
23060 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23061 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23066 for (p
= cpu_arch_ver
; p
->val
; p
++)
23068 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23071 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23075 /* The table lookup above finds the last architecture to contribute
23076 a new feature. Unfortunately, Tag13 is a subset of the union of
23077 v6T2 and v7-M, so it is never seen as contributing a new feature.
23078 We can not search for the last entry which is entirely used,
23079 because if no CPU is specified we build up only those flags
23080 actually used. Perhaps we should separate out the specified
23081 and implicit cases. Avoid taking this path for -march=all by
23082 checking for contradictory v7-A / v7-M features. */
23084 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23085 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23086 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23089 /* Tag_CPU_name. */
23090 if (selected_cpu_name
[0])
23094 q
= selected_cpu_name
;
23095 if (strncmp (q
, "armv", 4) == 0)
23100 for (i
= 0; q
[i
]; i
++)
23101 q
[i
] = TOUPPER (q
[i
]);
23103 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23106 /* Tag_CPU_arch. */
23107 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23109 /* Tag_CPU_arch_profile. */
23110 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23111 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23112 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23113 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23114 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23115 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23117 /* Tag_ARM_ISA_use. */
23118 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23120 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23122 /* Tag_THUMB_ISA_use. */
23123 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23125 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23126 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23128 /* Tag_VFP_arch. */
23129 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23130 aeabi_set_attribute_int (Tag_VFP_arch
,
23131 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23133 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23134 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23135 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23136 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23137 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23138 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23139 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23140 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23141 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23143 /* Tag_ABI_HardFP_use. */
23144 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23145 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23146 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23148 /* Tag_WMMX_arch. */
23149 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23150 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23151 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23152 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23154 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23155 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23156 aeabi_set_attribute_int
23157 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23160 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23161 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23162 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23165 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23166 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23167 /* Fill this in when gas supports v7a sdiv/udiv.
23168 else if (... v7a with div extension used ...)
23169 aeabi_set_attribute_int (Tag_DIV_use, 2); */
23171 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23173 /* Tag_MP_extension_use. */
23174 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23175 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23177 /* Tag Virtualization_use. */
23178 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23179 aeabi_set_attribute_int (Tag_Virtualization_use
, 1);
23182 /* Add the default contents for the .ARM.attributes section. */
23186 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23189 aeabi_set_public_attributes ();
23191 #endif /* OBJ_ELF */
23194 /* Parse a .cpu directive. */
23197 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23199 const struct arm_cpu_option_table
*opt
;
23203 name
= input_line_pointer
;
23204 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23205 input_line_pointer
++;
23206 saved_char
= *input_line_pointer
;
23207 *input_line_pointer
= 0;
23209 /* Skip the first "all" entry. */
23210 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23211 if (streq (opt
->name
, name
))
23213 mcpu_cpu_opt
= &opt
->value
;
23214 selected_cpu
= opt
->value
;
23215 if (opt
->canonical_name
)
23216 strcpy (selected_cpu_name
, opt
->canonical_name
);
23220 for (i
= 0; opt
->name
[i
]; i
++)
23221 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23222 selected_cpu_name
[i
] = 0;
23224 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23225 *input_line_pointer
= saved_char
;
23226 demand_empty_rest_of_line ();
23229 as_bad (_("unknown cpu `%s'"), name
);
23230 *input_line_pointer
= saved_char
;
23231 ignore_rest_of_line ();
23235 /* Parse a .arch directive. */
23238 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23240 const struct arm_arch_option_table
*opt
;
23244 name
= input_line_pointer
;
23245 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23246 input_line_pointer
++;
23247 saved_char
= *input_line_pointer
;
23248 *input_line_pointer
= 0;
23250 /* Skip the first "all" entry. */
23251 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23252 if (streq (opt
->name
, name
))
23254 mcpu_cpu_opt
= &opt
->value
;
23255 selected_cpu
= opt
->value
;
23256 strcpy (selected_cpu_name
, opt
->name
);
23257 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23258 *input_line_pointer
= saved_char
;
23259 demand_empty_rest_of_line ();
23263 as_bad (_("unknown architecture `%s'\n"), name
);
23264 *input_line_pointer
= saved_char
;
23265 ignore_rest_of_line ();
23269 /* Parse a .object_arch directive. */
23272 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23274 const struct arm_arch_option_table
*opt
;
23278 name
= input_line_pointer
;
23279 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23280 input_line_pointer
++;
23281 saved_char
= *input_line_pointer
;
23282 *input_line_pointer
= 0;
23284 /* Skip the first "all" entry. */
23285 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23286 if (streq (opt
->name
, name
))
23288 object_arch
= &opt
->value
;
23289 *input_line_pointer
= saved_char
;
23290 demand_empty_rest_of_line ();
23294 as_bad (_("unknown architecture `%s'\n"), name
);
23295 *input_line_pointer
= saved_char
;
23296 ignore_rest_of_line ();
23299 /* Parse a .arch_extension directive. */
23302 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23304 const struct arm_option_extension_value_table
*opt
;
23307 int adding_value
= 1;
23309 name
= input_line_pointer
;
23310 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23311 input_line_pointer
++;
23312 saved_char
= *input_line_pointer
;
23313 *input_line_pointer
= 0;
23315 if (strlen (name
) >= 2
23316 && strncmp (name
, "no", 2) == 0)
23322 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23323 if (streq (opt
->name
, name
))
23325 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23327 as_bad (_("architectural extension `%s' is not allowed for the "
23328 "current base architecture"), name
);
23333 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23335 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23337 mcpu_cpu_opt
= &selected_cpu
;
23338 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23339 *input_line_pointer
= saved_char
;
23340 demand_empty_rest_of_line ();
23344 if (opt
->name
== NULL
)
23345 as_bad (_("unknown architecture `%s'\n"), name
);
23347 *input_line_pointer
= saved_char
;
23348 ignore_rest_of_line ();
23351 /* Parse a .fpu directive. */
23354 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23356 const struct arm_option_fpu_value_table
*opt
;
23360 name
= input_line_pointer
;
23361 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23362 input_line_pointer
++;
23363 saved_char
= *input_line_pointer
;
23364 *input_line_pointer
= 0;
23366 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23367 if (streq (opt
->name
, name
))
23369 mfpu_opt
= &opt
->value
;
23370 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23371 *input_line_pointer
= saved_char
;
23372 demand_empty_rest_of_line ();
23376 as_bad (_("unknown floating point format `%s'\n"), name
);
23377 *input_line_pointer
= saved_char
;
23378 ignore_rest_of_line ();
23381 /* Copy symbol information. */
23384 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23386 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23390 /* Given a symbolic attribute NAME, return the proper integer value.
23391 Returns -1 if the attribute is not known. */
23394 arm_convert_symbolic_attribute (const char *name
)
23396 static const struct
23401 attribute_table
[] =
23403 /* When you modify this table you should
23404 also modify the list in doc/c-arm.texi. */
23405 #define T(tag) {#tag, tag}
23406 T (Tag_CPU_raw_name
),
23409 T (Tag_CPU_arch_profile
),
23410 T (Tag_ARM_ISA_use
),
23411 T (Tag_THUMB_ISA_use
),
23415 T (Tag_Advanced_SIMD_arch
),
23416 T (Tag_PCS_config
),
23417 T (Tag_ABI_PCS_R9_use
),
23418 T (Tag_ABI_PCS_RW_data
),
23419 T (Tag_ABI_PCS_RO_data
),
23420 T (Tag_ABI_PCS_GOT_use
),
23421 T (Tag_ABI_PCS_wchar_t
),
23422 T (Tag_ABI_FP_rounding
),
23423 T (Tag_ABI_FP_denormal
),
23424 T (Tag_ABI_FP_exceptions
),
23425 T (Tag_ABI_FP_user_exceptions
),
23426 T (Tag_ABI_FP_number_model
),
23427 T (Tag_ABI_align_needed
),
23428 T (Tag_ABI_align8_needed
),
23429 T (Tag_ABI_align_preserved
),
23430 T (Tag_ABI_align8_preserved
),
23431 T (Tag_ABI_enum_size
),
23432 T (Tag_ABI_HardFP_use
),
23433 T (Tag_ABI_VFP_args
),
23434 T (Tag_ABI_WMMX_args
),
23435 T (Tag_ABI_optimization_goals
),
23436 T (Tag_ABI_FP_optimization_goals
),
23437 T (Tag_compatibility
),
23438 T (Tag_CPU_unaligned_access
),
23439 T (Tag_FP_HP_extension
),
23440 T (Tag_VFP_HP_extension
),
23441 T (Tag_ABI_FP_16bit_format
),
23442 T (Tag_MPextension_use
),
23444 T (Tag_nodefaults
),
23445 T (Tag_also_compatible_with
),
23446 T (Tag_conformance
),
23448 T (Tag_Virtualization_use
),
23449 /* We deliberately do not include Tag_MPextension_use_legacy. */
23457 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23458 if (streq (name
, attribute_table
[i
].name
))
23459 return attribute_table
[i
].tag
;
23465 /* Apply sym value for relocations only in the case that
23466 they are for local symbols and you have the respective
23467 architectural feature for blx and simple switches. */
23469 arm_apply_sym_value (struct fix
* fixP
)
23472 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23473 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23475 switch (fixP
->fx_r_type
)
23477 case BFD_RELOC_ARM_PCREL_BLX
:
23478 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23479 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23483 case BFD_RELOC_ARM_PCREL_CALL
:
23484 case BFD_RELOC_THUMB_PCREL_BLX
:
23485 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23496 #endif /* OBJ_ELF */