1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
157 static int warn_on_restrict_it
= FALSE
;
159 /* Understand CodeComposer Studio assembly syntax. */
160 bfd_boolean codecomposer_syntax
= FALSE
;
162 /* Variables that we set while parsing command-line options. Once all
163 options have been read we re-process these values to set the real
166 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167 instead of -mcpu=arm1). */
168 static const arm_feature_set
*legacy_cpu
= NULL
;
169 static const arm_feature_set
*legacy_fpu
= NULL
;
171 /* CPU, extension and FPU feature bits selected by -mcpu. */
172 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
173 static arm_feature_set
*mcpu_ext_opt
= NULL
;
174 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
176 /* CPU, extension and FPU feature bits selected by -march. */
177 static const arm_feature_set
*march_cpu_opt
= NULL
;
178 static arm_feature_set
*march_ext_opt
= NULL
;
179 static const arm_feature_set
*march_fpu_opt
= NULL
;
181 /* Feature bits selected by -mfpu. */
182 static const arm_feature_set
*mfpu_opt
= NULL
;
184 /* Constants for known architecture features. */
185 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
186 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
187 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
188 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
189 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
190 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
191 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
193 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
195 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
198 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
201 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
202 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
203 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
204 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
205 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
206 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
207 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
208 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
209 static const arm_feature_set arm_ext_v4t_5
=
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
211 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
212 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
213 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
214 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
215 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
216 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
217 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
218 /* Only for compatability of hint instructions. */
219 static const arm_feature_set arm_ext_v6k_v6t2
=
220 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
221 static const arm_feature_set arm_ext_v6_notm
=
222 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
223 static const arm_feature_set arm_ext_v6_dsp
=
224 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
225 static const arm_feature_set arm_ext_barrier
=
226 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
227 static const arm_feature_set arm_ext_msr
=
228 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
229 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
230 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
231 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
232 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
233 static const arm_feature_set arm_ext_v8r
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R
);
235 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
237 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
238 static const arm_feature_set arm_ext_m
=
239 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
240 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
241 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
242 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
243 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
244 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
245 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
246 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
247 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
248 static const arm_feature_set arm_ext_v8m_main
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
250 static const arm_feature_set arm_ext_v8_1m_main
=
251 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
252 /* Instructions in ARMv8-M only found in M profile architectures. */
253 static const arm_feature_set arm_ext_v8m_m_only
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
255 static const arm_feature_set arm_ext_v6t2_v8m
=
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
257 /* Instructions shared between ARMv8-A and ARMv8-M. */
258 static const arm_feature_set arm_ext_atomics
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
261 /* DSP instructions Tag_DSP_extension refers to. */
262 static const arm_feature_set arm_ext_dsp
=
263 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
265 static const arm_feature_set arm_ext_ras
=
266 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
267 /* FP16 instructions. */
268 static const arm_feature_set arm_ext_fp16
=
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
270 static const arm_feature_set arm_ext_fp16_fml
=
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
272 static const arm_feature_set arm_ext_v8_2
=
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
274 static const arm_feature_set arm_ext_v8_3
=
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
276 static const arm_feature_set arm_ext_sb
=
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
278 static const arm_feature_set arm_ext_predres
=
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
280 static const arm_feature_set arm_ext_bf16
=
281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
282 static const arm_feature_set arm_ext_i8mm
=
283 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
);
284 static const arm_feature_set arm_ext_crc
=
285 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
);
286 static const arm_feature_set arm_ext_cde
=
287 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
);
288 static const arm_feature_set arm_ext_cde0
=
289 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0
);
290 static const arm_feature_set arm_ext_cde1
=
291 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1
);
292 static const arm_feature_set arm_ext_cde2
=
293 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2
);
294 static const arm_feature_set arm_ext_cde3
=
295 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3
);
296 static const arm_feature_set arm_ext_cde4
=
297 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4
);
298 static const arm_feature_set arm_ext_cde5
=
299 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5
);
300 static const arm_feature_set arm_ext_cde6
=
301 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6
);
302 static const arm_feature_set arm_ext_cde7
=
303 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7
);
305 static const arm_feature_set arm_arch_any
= ARM_ANY
;
306 static const arm_feature_set fpu_any
= FPU_ANY
;
307 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
308 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
309 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
311 static const arm_feature_set arm_cext_iwmmxt2
=
312 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
313 static const arm_feature_set arm_cext_iwmmxt
=
314 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
315 static const arm_feature_set arm_cext_xscale
=
316 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
317 static const arm_feature_set arm_cext_maverick
=
318 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
319 static const arm_feature_set fpu_fpa_ext_v1
=
320 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
321 static const arm_feature_set fpu_fpa_ext_v2
=
322 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
323 static const arm_feature_set fpu_vfp_ext_v1xd
=
324 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
325 static const arm_feature_set fpu_vfp_ext_v1
=
326 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
327 static const arm_feature_set fpu_vfp_ext_v2
=
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
329 static const arm_feature_set fpu_vfp_ext_v3xd
=
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
331 static const arm_feature_set fpu_vfp_ext_v3
=
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
333 static const arm_feature_set fpu_vfp_ext_d32
=
334 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
335 static const arm_feature_set fpu_neon_ext_v1
=
336 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
337 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
338 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
339 static const arm_feature_set mve_ext
=
340 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
);
341 static const arm_feature_set mve_fp_ext
=
342 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
);
343 /* Note: This has more than one bit set, which means using it with
344 mark_feature_used (which returns if *any* of the bits are set in the current
345 cpu variant) can give surprising results. */
346 static const arm_feature_set armv8m_fp
=
347 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16
);
349 static const arm_feature_set fpu_vfp_fp16
=
350 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
351 static const arm_feature_set fpu_neon_ext_fma
=
352 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
354 static const arm_feature_set fpu_vfp_ext_fma
=
355 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
356 static const arm_feature_set fpu_vfp_ext_armv8
=
357 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
358 static const arm_feature_set fpu_vfp_ext_armv8xd
=
359 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
360 static const arm_feature_set fpu_neon_ext_armv8
=
361 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
362 static const arm_feature_set fpu_crypto_ext_armv8
=
363 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
364 static const arm_feature_set fpu_neon_ext_v8_1
=
365 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
366 static const arm_feature_set fpu_neon_ext_dotprod
=
367 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
369 static int mfloat_abi_opt
= -1;
370 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
372 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
373 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
375 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
376 /* Feature bits selected by the last -mcpu/-march or by the combination of the
377 last .cpu/.arch directive .arch_extension directives since that
379 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
380 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
381 static arm_feature_set selected_fpu
= FPU_NONE
;
382 /* Feature bits selected by the last .object_arch directive. */
383 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
384 /* Must be long enough to hold any of the names in arm_cpus. */
385 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
386 static char selected_cpu_name
[20];
388 extern FLONUM_TYPE generic_floating_point_number
;
390 /* Return if no cpu was selected on command-line. */
392 no_cpu_selected (void)
394 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
399 static int meabi_flags
= EABI_DEFAULT
;
401 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
404 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
409 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
414 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
415 symbolS
* GOT_symbol
;
418 /* 0: assemble for ARM,
419 1: assemble for Thumb,
420 2: assemble for Thumb even though target CPU does not support thumb
422 static int thumb_mode
= 0;
423 /* A value distinct from the possible values for thumb_mode that we
424 can use to record whether thumb_mode has been copied into the
425 tc_frag_data field of a frag. */
426 #define MODE_RECORDED (1 << 4)
428 /* Specifies the intrinsic IT insn behavior mode. */
429 enum implicit_it_mode
431 IMPLICIT_IT_MODE_NEVER
= 0x00,
432 IMPLICIT_IT_MODE_ARM
= 0x01,
433 IMPLICIT_IT_MODE_THUMB
= 0x02,
434 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
436 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
438 /* If unified_syntax is true, we are processing the new unified
439 ARM/Thumb syntax. Important differences from the old ARM mode:
441 - Immediate operands do not require a # prefix.
442 - Conditional affixes always appear at the end of the
443 instruction. (For backward compatibility, those instructions
444 that formerly had them in the middle, continue to accept them
446 - The IT instruction may appear, and if it does is validated
447 against subsequent conditional affixes. It does not generate
450 Important differences from the old Thumb mode:
452 - Immediate operands do not require a # prefix.
453 - Most of the V6T2 instructions are only available in unified mode.
454 - The .N and .W suffixes are recognized and honored (it is an error
455 if they cannot be honored).
456 - All instructions set the flags if and only if they have an 's' affix.
457 - Conditional affixes may be used. They are validated against
458 preceding IT instructions. Unlike ARM mode, you cannot use a
459 conditional affix except in the scope of an IT instruction. */
461 static bfd_boolean unified_syntax
= FALSE
;
463 /* An immediate operand can start with #, and ld*, st*, pld operands
464 can contain [ and ]. We need to tell APP not to elide whitespace
465 before a [, which can appear as the first operand for pld.
466 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
467 const char arm_symbol_chars
[] = "#[]{}";
483 enum neon_el_type type
;
487 #define NEON_MAX_TYPE_ELS 5
491 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
495 enum pred_instruction_type
501 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
502 if inside, should be the last one. */
503 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
504 i.e. BKPT and NOP. */
505 IT_INSN
, /* The IT insn has been parsed. */
506 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
507 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
508 a predication code. */
509 MVE_UNPREDICABLE_INSN
, /* MVE instruction that is non-predicable. */
512 /* The maximum number of operands we need. */
513 #define ARM_IT_MAX_OPERANDS 6
514 #define ARM_IT_MAX_RELOCS 3
519 unsigned long instruction
;
523 /* "uncond_value" is set to the value in place of the conditional field in
524 unconditional versions of the instruction, or -1 if nothing is
527 struct neon_type vectype
;
528 /* This does not indicate an actual NEON instruction, only that
529 the mnemonic accepts neon-style type suffixes. */
531 /* Set to the opcode if the instruction needs relaxation.
532 Zero if the instruction is not relaxed. */
536 bfd_reloc_code_real_type type
;
539 } relocs
[ARM_IT_MAX_RELOCS
];
541 enum pred_instruction_type pred_insn_type
;
547 struct neon_type_el vectype
;
548 unsigned present
: 1; /* Operand present. */
549 unsigned isreg
: 1; /* Operand was a register. */
550 unsigned immisreg
: 2; /* .imm field is a second register.
551 0: imm, 1: gpr, 2: MVE Q-register. */
552 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
556 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
557 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
558 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
559 instructions. This allows us to disambiguate ARM <-> vector insns. */
560 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
561 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
562 unsigned isquad
: 1; /* Operand is SIMD quad register. */
563 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
564 unsigned iszr
: 1; /* Operand is ZR register. */
565 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
566 unsigned writeback
: 1; /* Operand has trailing ! */
567 unsigned preind
: 1; /* Preindexed address. */
568 unsigned postind
: 1; /* Postindexed address. */
569 unsigned negative
: 1; /* Index register was negated. */
570 unsigned shifted
: 1; /* Shift applied to operation. */
571 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
572 } operands
[ARM_IT_MAX_OPERANDS
];
575 static struct arm_it inst
;
577 #define NUM_FLOAT_VALS 8
579 const char * fp_const
[] =
581 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
584 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
594 #define CP_T_X 0x00008000
595 #define CP_T_Y 0x00400000
597 #define CONDS_BIT 0x00100000
598 #define LOAD_BIT 0x00100000
600 #define DOUBLE_LOAD_FLAG 0x00000001
604 const char * template_name
;
608 #define COND_ALWAYS 0xE
612 const char * template_name
;
616 struct asm_barrier_opt
618 const char * template_name
;
620 const arm_feature_set arch
;
623 /* The bit that distinguishes CPSR and SPSR. */
624 #define SPSR_BIT (1 << 22)
626 /* The individual PSR flag bits. */
627 #define PSR_c (1 << 16)
628 #define PSR_x (1 << 17)
629 #define PSR_s (1 << 18)
630 #define PSR_f (1 << 19)
635 bfd_reloc_code_real_type reloc
;
640 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
641 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
646 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
649 /* Bits for DEFINED field in neon_typed_alias. */
650 #define NTA_HASTYPE 1
651 #define NTA_HASINDEX 2
653 struct neon_typed_alias
655 unsigned char defined
;
657 struct neon_type_el eltype
;
660 /* ARM register categories. This includes coprocessor numbers and various
661 architecture extensions' registers. Each entry should have an error message
662 in reg_expected_msgs below. */
692 /* Structure for a hash table entry for a register.
693 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
694 information which states whether a vector type or index is specified (for a
695 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
701 unsigned char builtin
;
702 struct neon_typed_alias
* neon
;
705 /* Diagnostics used when we don't get a register of the expected type. */
706 const char * const reg_expected_msgs
[] =
708 [REG_TYPE_RN
] = N_("ARM register expected"),
709 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
710 [REG_TYPE_CN
] = N_("co-processor register expected"),
711 [REG_TYPE_FN
] = N_("FPA register expected"),
712 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
713 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
714 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
715 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
716 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
717 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
718 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
720 [REG_TYPE_VFC
] = N_("VFP system register expected"),
721 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
722 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
723 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
724 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
725 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
726 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
727 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
728 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
729 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
730 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
731 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
735 /* Some well known registers that we refer to directly elsewhere. */
741 /* ARM instructions take 4bytes in the object file, Thumb instructions
747 /* Basic string to match. */
748 const char * template_name
;
750 /* Parameters to instruction. */
751 unsigned int operands
[8];
753 /* Conditional tag - see opcode_lookup. */
754 unsigned int tag
: 4;
756 /* Basic instruction code. */
759 /* Thumb-format instruction code. */
762 /* Which architecture variant provides this instruction. */
763 const arm_feature_set
* avariant
;
764 const arm_feature_set
* tvariant
;
766 /* Function to call to encode instruction in ARM format. */
767 void (* aencode
) (void);
769 /* Function to call to encode instruction in Thumb format. */
770 void (* tencode
) (void);
772 /* Indicates whether this instruction may be vector predicated. */
773 unsigned int mayBeVecPred
: 1;
776 /* Defines for various bits that we will want to toggle. */
777 #define INST_IMMEDIATE 0x02000000
778 #define OFFSET_REG 0x02000000
779 #define HWOFFSET_IMM 0x00400000
780 #define SHIFT_BY_REG 0x00000010
781 #define PRE_INDEX 0x01000000
782 #define INDEX_UP 0x00800000
783 #define WRITE_BACK 0x00200000
784 #define LDM_TYPE_2_OR_3 0x00400000
785 #define CPSI_MMOD 0x00020000
787 #define LITERAL_MASK 0xf000f000
788 #define OPCODE_MASK 0xfe1fffff
789 #define V4_STR_BIT 0x00000020
790 #define VLDR_VMOV_SAME 0x0040f000
792 #define T2_SUBS_PC_LR 0xf3de8f00
794 #define DATA_OP_SHIFT 21
795 #define SBIT_SHIFT 20
797 #define T2_OPCODE_MASK 0xfe1fffff
798 #define T2_DATA_OP_SHIFT 21
799 #define T2_SBIT_SHIFT 20
801 #define A_COND_MASK 0xf0000000
802 #define A_PUSH_POP_OP_MASK 0x0fff0000
804 /* Opcodes for pushing/poping registers to/from the stack. */
805 #define A1_OPCODE_PUSH 0x092d0000
806 #define A2_OPCODE_PUSH 0x052d0004
807 #define A2_OPCODE_POP 0x049d0004
809 /* Codes to distinguish the arithmetic instructions. */
820 #define OPCODE_CMP 10
821 #define OPCODE_CMN 11
822 #define OPCODE_ORR 12
823 #define OPCODE_MOV 13
824 #define OPCODE_BIC 14
825 #define OPCODE_MVN 15
827 #define T2_OPCODE_AND 0
828 #define T2_OPCODE_BIC 1
829 #define T2_OPCODE_ORR 2
830 #define T2_OPCODE_ORN 3
831 #define T2_OPCODE_EOR 4
832 #define T2_OPCODE_ADD 8
833 #define T2_OPCODE_ADC 10
834 #define T2_OPCODE_SBC 11
835 #define T2_OPCODE_SUB 13
836 #define T2_OPCODE_RSB 14
838 #define T_OPCODE_MUL 0x4340
839 #define T_OPCODE_TST 0x4200
840 #define T_OPCODE_CMN 0x42c0
841 #define T_OPCODE_NEG 0x4240
842 #define T_OPCODE_MVN 0x43c0
844 #define T_OPCODE_ADD_R3 0x1800
845 #define T_OPCODE_SUB_R3 0x1a00
846 #define T_OPCODE_ADD_HI 0x4400
847 #define T_OPCODE_ADD_ST 0xb000
848 #define T_OPCODE_SUB_ST 0xb080
849 #define T_OPCODE_ADD_SP 0xa800
850 #define T_OPCODE_ADD_PC 0xa000
851 #define T_OPCODE_ADD_I8 0x3000
852 #define T_OPCODE_SUB_I8 0x3800
853 #define T_OPCODE_ADD_I3 0x1c00
854 #define T_OPCODE_SUB_I3 0x1e00
856 #define T_OPCODE_ASR_R 0x4100
857 #define T_OPCODE_LSL_R 0x4080
858 #define T_OPCODE_LSR_R 0x40c0
859 #define T_OPCODE_ROR_R 0x41c0
860 #define T_OPCODE_ASR_I 0x1000
861 #define T_OPCODE_LSL_I 0x0000
862 #define T_OPCODE_LSR_I 0x0800
864 #define T_OPCODE_MOV_I8 0x2000
865 #define T_OPCODE_CMP_I8 0x2800
866 #define T_OPCODE_CMP_LR 0x4280
867 #define T_OPCODE_MOV_HR 0x4600
868 #define T_OPCODE_CMP_HR 0x4500
870 #define T_OPCODE_LDR_PC 0x4800
871 #define T_OPCODE_LDR_SP 0x9800
872 #define T_OPCODE_STR_SP 0x9000
873 #define T_OPCODE_LDR_IW 0x6800
874 #define T_OPCODE_STR_IW 0x6000
875 #define T_OPCODE_LDR_IH 0x8800
876 #define T_OPCODE_STR_IH 0x8000
877 #define T_OPCODE_LDR_IB 0x7800
878 #define T_OPCODE_STR_IB 0x7000
879 #define T_OPCODE_LDR_RW 0x5800
880 #define T_OPCODE_STR_RW 0x5000
881 #define T_OPCODE_LDR_RH 0x5a00
882 #define T_OPCODE_STR_RH 0x5200
883 #define T_OPCODE_LDR_RB 0x5c00
884 #define T_OPCODE_STR_RB 0x5400
886 #define T_OPCODE_PUSH 0xb400
887 #define T_OPCODE_POP 0xbc00
889 #define T_OPCODE_BRANCH 0xe000
891 #define THUMB_SIZE 2 /* Size of thumb instruction. */
892 #define THUMB_PP_PC_LR 0x0100
893 #define THUMB_LOAD_BIT 0x0800
894 #define THUMB2_LOAD_BIT 0x00100000
896 #define BAD_SYNTAX _("syntax error")
897 #define BAD_ARGS _("bad arguments to instruction")
898 #define BAD_SP _("r13 not allowed here")
899 #define BAD_PC _("r15 not allowed here")
900 #define BAD_ODD _("Odd register not allowed here")
901 #define BAD_EVEN _("Even register not allowed here")
902 #define BAD_COND _("instruction cannot be conditional")
903 #define BAD_OVERLAP _("registers may not be the same")
904 #define BAD_HIREG _("lo register required")
905 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
906 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
907 #define BAD_BRANCH _("branch must be last instruction in IT block")
908 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
909 #define BAD_NO_VPT _("instruction not allowed in VPT block")
910 #define BAD_NOT_IT _("instruction not allowed in IT block")
911 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
912 #define BAD_FPU _("selected FPU does not support instruction")
913 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
914 #define BAD_OUT_VPT \
915 _("vector predicated instruction should be in VPT/VPST block")
916 #define BAD_IT_COND _("incorrect condition in IT block")
917 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
918 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
919 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
920 #define BAD_PC_ADDRESSING \
921 _("cannot use register index with PC-relative addressing")
922 #define BAD_PC_WRITEBACK \
923 _("cannot use writeback with PC-relative addressing")
924 #define BAD_RANGE _("branch out of range")
925 #define BAD_FP16 _("selected processor does not support fp16 instruction")
926 #define BAD_BF16 _("selected processor does not support bf16 instruction")
927 #define BAD_CDE _("selected processor does not support cde instruction")
928 #define BAD_CDE_COPROC _("coprocessor for insn is not enabled for cde")
929 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
930 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
931 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
933 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
935 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
937 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
939 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
940 #define BAD_MVE_AUTO \
941 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
942 " use a valid -march or -mcpu option.")
943 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
944 "and source operands makes instruction UNPREDICTABLE")
945 #define BAD_EL_TYPE _("bad element type for instruction")
946 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
948 static htab_t arm_ops_hsh
;
949 static htab_t arm_cond_hsh
;
950 static htab_t arm_vcond_hsh
;
951 static htab_t arm_shift_hsh
;
952 static htab_t arm_psr_hsh
;
953 static htab_t arm_v7m_psr_hsh
;
954 static htab_t arm_reg_hsh
;
955 static htab_t arm_reloc_hsh
;
956 static htab_t arm_barrier_opt_hsh
;
958 /* Stuff needed to resolve the label ambiguity
967 symbolS
* last_label_seen
;
968 static int label_is_thumb_function_name
= FALSE
;
970 /* Literal pool structure. Held on a per-section
971 and per-sub-section basis. */
973 #define MAX_LITERAL_POOL_SIZE 1024
974 typedef struct literal_pool
976 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
977 unsigned int next_free_entry
;
983 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
985 struct literal_pool
* next
;
986 unsigned int alignment
;
989 /* Pointer to a linked list of literal pools. */
990 literal_pool
* list_of_pools
= NULL
;
992 typedef enum asmfunc_states
995 WAITING_ASMFUNC_NAME
,
999 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
1002 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
1004 static struct current_pred now_pred
;
1008 now_pred_compatible (int cond
)
1010 return (cond
& ~1) == (now_pred
.cc
& ~1);
1014 conditional_insn (void)
1016 return inst
.cond
!= COND_ALWAYS
;
1019 static int in_pred_block (void);
1021 static int handle_pred_state (void);
1023 static void force_automatic_it_block_close (void);
1025 static void it_fsm_post_encode (void);
1027 #define set_pred_insn_type(type) \
1030 inst.pred_insn_type = type; \
1031 if (handle_pred_state () == FAIL) \
1036 #define set_pred_insn_type_nonvoid(type, failret) \
1039 inst.pred_insn_type = type; \
1040 if (handle_pred_state () == FAIL) \
1045 #define set_pred_insn_type_last() \
1048 if (inst.cond == COND_ALWAYS) \
1049 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1051 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1055 /* Toggle value[pos]. */
1056 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1060 /* This array holds the chars that always start a comment. If the
1061 pre-processor is disabled, these aren't very useful. */
1062 char arm_comment_chars
[] = "@";
1064 /* This array holds the chars that only start a comment at the beginning of
1065 a line. If the line seems to have the form '# 123 filename'
1066 .line and .file directives will appear in the pre-processed output. */
1067 /* Note that input_file.c hand checks for '#' at the beginning of the
1068 first line of the input file. This is because the compiler outputs
1069 #NO_APP at the beginning of its output. */
1070 /* Also note that comments like this one will always work. */
1071 const char line_comment_chars
[] = "#";
1073 char arm_line_separator_chars
[] = ";";
1075 /* Chars that can be used to separate mant
1076 from exp in floating point numbers. */
1077 const char EXP_CHARS
[] = "eE";
1079 /* Chars that mean this number is a floating point constant. */
1080 /* As in 0f12.456 */
1081 /* or 0d1.2345e12 */
1083 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1085 /* Prefix characters that indicate the start of an immediate
1087 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1089 /* Separator character handling. */
1091 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1093 enum fp_16bit_format
1095 ARM_FP16_FORMAT_IEEE
= 0x1,
1096 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1097 ARM_FP16_FORMAT_DEFAULT
= 0x3
1100 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1104 skip_past_char (char ** str
, char c
)
1106 /* PR gas/14987: Allow for whitespace before the expected character. */
1107 skip_whitespace (*str
);
1118 #define skip_past_comma(str) skip_past_char (str, ',')
1120 /* Arithmetic expressions (possibly involving symbols). */
1122 /* Return TRUE if anything in the expression is a bignum. */
1125 walk_no_bignums (symbolS
* sp
)
1127 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1130 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1132 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1133 || (symbol_get_value_expression (sp
)->X_op_symbol
1134 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1140 static bfd_boolean in_my_get_expression
= FALSE
;
1142 /* Third argument to my_get_expression. */
1143 #define GE_NO_PREFIX 0
1144 #define GE_IMM_PREFIX 1
1145 #define GE_OPT_PREFIX 2
1146 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1147 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1148 #define GE_OPT_PREFIX_BIG 3
1151 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1155 /* In unified syntax, all prefixes are optional. */
1157 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1160 switch (prefix_mode
)
1162 case GE_NO_PREFIX
: break;
1164 if (!is_immediate_prefix (**str
))
1166 inst
.error
= _("immediate expression requires a # prefix");
1172 case GE_OPT_PREFIX_BIG
:
1173 if (is_immediate_prefix (**str
))
1180 memset (ep
, 0, sizeof (expressionS
));
1182 save_in
= input_line_pointer
;
1183 input_line_pointer
= *str
;
1184 in_my_get_expression
= TRUE
;
1186 in_my_get_expression
= FALSE
;
1188 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1190 /* We found a bad or missing expression in md_operand(). */
1191 *str
= input_line_pointer
;
1192 input_line_pointer
= save_in
;
1193 if (inst
.error
== NULL
)
1194 inst
.error
= (ep
->X_op
== O_absent
1195 ? _("missing expression") :_("bad expression"));
1199 /* Get rid of any bignums now, so that we don't generate an error for which
1200 we can't establish a line number later on. Big numbers are never valid
1201 in instructions, which is where this routine is always called. */
1202 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1203 && (ep
->X_op
== O_big
1204 || (ep
->X_add_symbol
1205 && (walk_no_bignums (ep
->X_add_symbol
)
1207 && walk_no_bignums (ep
->X_op_symbol
))))))
1209 inst
.error
= _("invalid constant");
1210 *str
= input_line_pointer
;
1211 input_line_pointer
= save_in
;
1215 *str
= input_line_pointer
;
1216 input_line_pointer
= save_in
;
1220 /* Turn a string in input_line_pointer into a floating point constant
1221 of type TYPE, and store the appropriate bytes in *LITP. The number
1222 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1223 returned, or NULL on OK.
1225 Note that fp constants aren't represent in the normal way on the ARM.
1226 In big endian mode, things are as expected. However, in little endian
1227 mode fp constants are big-endian word-wise, and little-endian byte-wise
1228 within the words. For example, (double) 1.1 in big endian mode is
1229 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1230 the byte sequence 99 99 f1 3f 9a 99 99 99.
1232 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1235 md_atof (int type
, char * litP
, int * sizeP
)
1238 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1249 /* If this is a bfloat16, then parse it slightly differently, as it
1250 does not follow the IEEE specification for floating point numbers
1254 FLONUM_TYPE generic_float
;
1256 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
1259 input_line_pointer
= t
;
1261 return _("invalid floating point number");
1263 switch (generic_float
.sign
)
1276 /* bfloat16 has two types of NaN - quiet and signalling.
1277 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1278 signalling NaN's have bit[0] == 0 && fraction != 0.
1279 Chosen this specific encoding as it is the same form
1280 as used by other IEEE 754 encodings in GAS. */
1291 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
1321 return _("Unrecognized or unsupported floating point constant");
1324 t
= atof_ieee (input_line_pointer
, type
, words
);
1326 input_line_pointer
= t
;
1327 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1329 if (target_big_endian
|| prec
== 1)
1330 for (i
= 0; i
< prec
; i
++)
1332 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1333 litP
+= sizeof (LITTLENUM_TYPE
);
1335 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1336 for (i
= prec
- 1; i
>= 0; i
--)
1338 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1339 litP
+= sizeof (LITTLENUM_TYPE
);
1342 /* For a 4 byte float the order of elements in `words' is 1 0.
1343 For an 8 byte float the order is 1 0 3 2. */
1344 for (i
= 0; i
< prec
; i
+= 2)
1346 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1347 sizeof (LITTLENUM_TYPE
));
1348 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1349 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1350 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1356 /* We handle all bad expressions here, so that we can report the faulty
1357 instruction in the error message. */
1360 md_operand (expressionS
* exp
)
1362 if (in_my_get_expression
)
1363 exp
->X_op
= O_illegal
;
1366 /* Immediate values. */
1369 /* Generic immediate-value read function for use in directives.
1370 Accepts anything that 'expression' can fold to a constant.
1371 *val receives the number. */
1374 immediate_for_directive (int *val
)
1377 exp
.X_op
= O_illegal
;
1379 if (is_immediate_prefix (*input_line_pointer
))
1381 input_line_pointer
++;
1385 if (exp
.X_op
!= O_constant
)
1387 as_bad (_("expected #constant"));
1388 ignore_rest_of_line ();
1391 *val
= exp
.X_add_number
;
1396 /* Register parsing. */
1398 /* Generic register parser. CCP points to what should be the
1399 beginning of a register name. If it is indeed a valid register
1400 name, advance CCP over it and return the reg_entry structure;
1401 otherwise return NULL. Does not issue diagnostics. */
1403 static struct reg_entry
*
1404 arm_reg_parse_multi (char **ccp
)
1408 struct reg_entry
*reg
;
1410 skip_whitespace (start
);
1412 #ifdef REGISTER_PREFIX
1413 if (*start
!= REGISTER_PREFIX
)
1417 #ifdef OPTIONAL_REGISTER_PREFIX
1418 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1423 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1428 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1430 reg
= (struct reg_entry
*) str_hash_find_n (arm_reg_hsh
, start
, p
- start
);
1440 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1441 enum arm_reg_type type
)
1443 /* Alternative syntaxes are accepted for a few register classes. */
1450 /* Generic coprocessor register names are allowed for these. */
1451 if (reg
&& reg
->type
== REG_TYPE_CN
)
1456 /* For backward compatibility, a bare number is valid here. */
1458 unsigned long processor
= strtoul (start
, ccp
, 10);
1459 if (*ccp
!= start
&& processor
<= 15)
1464 case REG_TYPE_MMXWC
:
1465 /* WC includes WCG. ??? I'm not sure this is true for all
1466 instructions that take WC registers. */
1467 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1478 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1479 return value is the register number or FAIL. */
1482 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1485 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1492 if (reg
&& reg
->type
== type
)
1495 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1502 /* Parse a Neon type specifier. *STR should point at the leading '.'
1503 character. Does no verification at this stage that the type fits the opcode
1510 Can all be legally parsed by this function.
1512 Fills in neon_type struct pointer with parsed information, and updates STR
1513 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1514 type, FAIL if not. */
1517 parse_neon_type (struct neon_type
*type
, char **str
)
1524 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1526 enum neon_el_type thistype
= NT_untyped
;
1527 unsigned thissize
= -1u;
1534 /* Just a size without an explicit type. */
1538 switch (TOLOWER (*ptr
))
1540 case 'i': thistype
= NT_integer
; break;
1541 case 'f': thistype
= NT_float
; break;
1542 case 'p': thistype
= NT_poly
; break;
1543 case 's': thistype
= NT_signed
; break;
1544 case 'u': thistype
= NT_unsigned
; break;
1546 thistype
= NT_float
;
1551 thistype
= NT_bfloat
;
1552 switch (TOLOWER (*(++ptr
)))
1556 thissize
= strtoul (ptr
, &ptr
, 10);
1559 as_bad (_("bad size %d in type specifier"), thissize
);
1563 case '0': case '1': case '2': case '3': case '4':
1564 case '5': case '6': case '7': case '8': case '9':
1566 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1573 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1579 /* .f is an abbreviation for .f32. */
1580 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1585 thissize
= strtoul (ptr
, &ptr
, 10);
1587 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1590 as_bad (_("bad size %d in type specifier"), thissize
);
1598 type
->el
[type
->elems
].type
= thistype
;
1599 type
->el
[type
->elems
].size
= thissize
;
1604 /* Empty/missing type is not a successful parse. */
1605 if (type
->elems
== 0)
1613 /* Errors may be set multiple times during parsing or bit encoding
1614 (particularly in the Neon bits), but usually the earliest error which is set
1615 will be the most meaningful. Avoid overwriting it with later (cascading)
1616 errors by calling this function. */
1619 first_error (const char *err
)
1625 /* Parse a single type, e.g. ".s32", leading period included. */
1627 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1630 struct neon_type optype
;
1634 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1636 if (optype
.elems
== 1)
1637 *vectype
= optype
.el
[0];
1640 first_error (_("only one type should be specified for operand"));
1646 first_error (_("vector type expected"));
1658 /* Special meanings for indices (which have a range of 0-7), which will fit into
1661 #define NEON_ALL_LANES 15
1662 #define NEON_INTERLEAVE_LANES 14
1664 /* Record a use of the given feature. */
1666 record_feature_use (const arm_feature_set
*feature
)
1669 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1671 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1674 /* If the given feature available in the selected CPU, mark it as used.
1675 Returns TRUE iff feature is available. */
1677 mark_feature_used (const arm_feature_set
*feature
)
1680 /* Do not support the use of MVE only instructions when in auto-detection or
1682 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1683 && ARM_CPU_IS_ANY (cpu_variant
))
1685 first_error (BAD_MVE_AUTO
);
1688 /* Ensure the option is valid on the current architecture. */
1689 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1692 /* Add the appropriate architecture feature for the barrier option used.
1694 record_feature_use (feature
);
1699 /* Parse either a register or a scalar, with an optional type. Return the
1700 register number, and optionally fill in the actual type of the register
1701 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1702 type/index information in *TYPEINFO. */
1705 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1706 enum arm_reg_type
*rtype
,
1707 struct neon_typed_alias
*typeinfo
)
1710 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1711 struct neon_typed_alias atype
;
1712 struct neon_type_el parsetype
;
1716 atype
.eltype
.type
= NT_invtype
;
1717 atype
.eltype
.size
= -1;
1719 /* Try alternate syntax for some types of register. Note these are mutually
1720 exclusive with the Neon syntax extensions. */
1723 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1731 /* Undo polymorphism when a set of register types may be accepted. */
1732 if ((type
== REG_TYPE_NDQ
1733 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1734 || (type
== REG_TYPE_VFSD
1735 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1736 || (type
== REG_TYPE_NSDQ
1737 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1738 || reg
->type
== REG_TYPE_NQ
))
1739 || (type
== REG_TYPE_NSD
1740 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1741 || (type
== REG_TYPE_MMXWC
1742 && (reg
->type
== REG_TYPE_MMXWCG
)))
1743 type
= (enum arm_reg_type
) reg
->type
;
1745 if (type
== REG_TYPE_MQ
)
1747 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1750 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1753 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1755 first_error (_("expected MVE register [q0..q7]"));
1760 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1761 && (type
== REG_TYPE_NQ
))
1765 if (type
!= reg
->type
)
1771 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1773 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1775 first_error (_("can't redefine type for operand"));
1778 atype
.defined
|= NTA_HASTYPE
;
1779 atype
.eltype
= parsetype
;
1782 if (skip_past_char (&str
, '[') == SUCCESS
)
1784 if (type
!= REG_TYPE_VFD
1785 && !(type
== REG_TYPE_VFS
1786 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1787 && !(type
== REG_TYPE_NQ
1788 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1790 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1791 first_error (_("only D and Q registers may be indexed"));
1793 first_error (_("only D registers may be indexed"));
1797 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1799 first_error (_("can't change index for operand"));
1803 atype
.defined
|= NTA_HASINDEX
;
1805 if (skip_past_char (&str
, ']') == SUCCESS
)
1806 atype
.index
= NEON_ALL_LANES
;
1811 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1813 if (exp
.X_op
!= O_constant
)
1815 first_error (_("constant expression required"));
1819 if (skip_past_char (&str
, ']') == FAIL
)
1822 atype
.index
= exp
.X_add_number
;
1837 /* Like arm_reg_parse, but also allow the following extra features:
1838 - If RTYPE is non-zero, return the (possibly restricted) type of the
1839 register (e.g. Neon double or quad reg when either has been requested).
1840 - If this is a Neon vector type with additional type information, fill
1841 in the struct pointed to by VECTYPE (if non-NULL).
1842 This function will fault on encountering a scalar. */
1845 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1846 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1848 struct neon_typed_alias atype
;
1850 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1855 /* Do not allow regname(... to parse as a register. */
1859 /* Do not allow a scalar (reg+index) to parse as a register. */
1860 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1862 first_error (_("register operand expected, but got scalar"));
1867 *vectype
= atype
.eltype
;
1874 #define NEON_SCALAR_REG(X) ((X) >> 4)
1875 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1877 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1878 have enough information to be able to do a good job bounds-checking. So, we
1879 just do easy checks here, and do further checks later. */
1882 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1883 arm_reg_type reg_type
)
1887 struct neon_typed_alias atype
;
1890 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1908 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1911 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1913 first_error (_("scalar must have an index"));
1916 else if (atype
.index
>= reg_size
/ elsize
)
1918 first_error (_("scalar index out of range"));
1923 *type
= atype
.eltype
;
1927 return reg
* 16 + atype
.index
;
1930 /* Types of registers in a list. */
1943 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1946 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1952 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1954 /* We come back here if we get ranges concatenated by '+' or '|'. */
1957 skip_whitespace (str
);
1970 const char apsr_str
[] = "apsr";
1971 int apsr_str_len
= strlen (apsr_str
);
1973 reg
= arm_reg_parse (&str
, REG_TYPE_RN
);
1974 if (etype
== REGLIST_CLRM
)
1976 if (reg
== REG_SP
|| reg
== REG_PC
)
1978 else if (reg
== FAIL
1979 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1980 && !ISALPHA (*(str
+ apsr_str_len
)))
1983 str
+= apsr_str_len
;
1988 first_error (_("r0-r12, lr or APSR expected"));
1992 else /* etype == REGLIST_RN. */
1996 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
2007 first_error (_("bad range in register list"));
2011 for (i
= cur_reg
+ 1; i
< reg
; i
++)
2013 if (range
& (1 << i
))
2015 (_("Warning: duplicated register (r%d) in register list"),
2023 if (range
& (1 << reg
))
2024 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2026 else if (reg
<= cur_reg
)
2027 as_tsktsk (_("Warning: register range not in ascending order"));
2032 while (skip_past_comma (&str
) != FAIL
2033 || (in_range
= 1, *str
++ == '-'));
2036 if (skip_past_char (&str
, '}') == FAIL
)
2038 first_error (_("missing `}'"));
2042 else if (etype
== REGLIST_RN
)
2046 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
2049 if (exp
.X_op
== O_constant
)
2051 if (exp
.X_add_number
2052 != (exp
.X_add_number
& 0x0000ffff))
2054 inst
.error
= _("invalid register mask");
2058 if ((range
& exp
.X_add_number
) != 0)
2060 int regno
= range
& exp
.X_add_number
;
2063 regno
= (1 << regno
) - 1;
2065 (_("Warning: duplicated register (r%d) in register list"),
2069 range
|= exp
.X_add_number
;
2073 if (inst
.relocs
[0].type
!= 0)
2075 inst
.error
= _("expression too complex");
2079 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2080 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2081 inst
.relocs
[0].pc_rel
= 0;
2085 if (*str
== '|' || *str
== '+')
2091 while (another_range
);
2097 /* Parse a VFP register list. If the string is invalid return FAIL.
2098 Otherwise return the number of registers, and set PBASE to the first
2099 register. Parses registers of type ETYPE.
2100 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2101 - Q registers can be used to specify pairs of D registers
2102 - { } can be omitted from around a singleton register list
2103 FIXME: This is not implemented, as it would require backtracking in
2106 This could be done (the meaning isn't really ambiguous), but doesn't
2107 fit in well with the current parsing framework.
2108 - 32 D registers may be used (also true for VFPv3).
2109 FIXME: Types are ignored in these register lists, which is probably a
2113 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2114 bfd_boolean
*partial_match
)
2119 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2123 unsigned long mask
= 0;
2125 bfd_boolean vpr_seen
= FALSE
;
2126 bfd_boolean expect_vpr
=
2127 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2129 if (skip_past_char (&str
, '{') == FAIL
)
2131 inst
.error
= _("expecting {");
2138 case REGLIST_VFP_S_VPR
:
2139 regtype
= REG_TYPE_VFS
;
2144 case REGLIST_VFP_D_VPR
:
2145 regtype
= REG_TYPE_VFD
;
2148 case REGLIST_NEON_D
:
2149 regtype
= REG_TYPE_NDQ
;
2156 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2158 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2159 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2163 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2166 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2173 base_reg
= max_regs
;
2174 *partial_match
= FALSE
;
2178 int setmask
= 1, addregs
= 1;
2179 const char vpr_str
[] = "vpr";
2180 int vpr_str_len
= strlen (vpr_str
);
2182 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2186 if (new_base
== FAIL
2187 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2188 && !ISALPHA (*(str
+ vpr_str_len
))
2194 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2198 first_error (_("VPR expected last"));
2201 else if (new_base
== FAIL
)
2203 if (regtype
== REG_TYPE_VFS
)
2204 first_error (_("VFP single precision register or VPR "
2206 else /* regtype == REG_TYPE_VFD. */
2207 first_error (_("VFP/Neon double precision register or VPR "
2212 else if (new_base
== FAIL
)
2214 first_error (_(reg_expected_msgs
[regtype
]));
2218 *partial_match
= TRUE
;
2222 if (new_base
>= max_regs
)
2224 first_error (_("register out of range in list"));
2228 /* Note: a value of 2 * n is returned for the register Q<n>. */
2229 if (regtype
== REG_TYPE_NQ
)
2235 if (new_base
< base_reg
)
2236 base_reg
= new_base
;
2238 if (mask
& (setmask
<< new_base
))
2240 first_error (_("invalid register list"));
2244 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2246 as_tsktsk (_("register list not in ascending order"));
2250 mask
|= setmask
<< new_base
;
2253 if (*str
== '-') /* We have the start of a range expression */
2259 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2262 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2266 if (high_range
>= max_regs
)
2268 first_error (_("register out of range in list"));
2272 if (regtype
== REG_TYPE_NQ
)
2273 high_range
= high_range
+ 1;
2275 if (high_range
<= new_base
)
2277 inst
.error
= _("register range not in ascending order");
2281 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2283 if (mask
& (setmask
<< new_base
))
2285 inst
.error
= _("invalid register list");
2289 mask
|= setmask
<< new_base
;
2294 while (skip_past_comma (&str
) != FAIL
);
2298 /* Sanity check -- should have raised a parse error above. */
2299 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2304 if (expect_vpr
&& !vpr_seen
)
2306 first_error (_("VPR expected last"));
2310 /* Final test -- the registers must be consecutive. */
2312 for (i
= 0; i
< count
; i
++)
2314 if ((mask
& (1u << i
)) == 0)
2316 inst
.error
= _("non-contiguous register range");
2326 /* True if two alias types are the same. */
2329 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2337 if (a
->defined
!= b
->defined
)
2340 if ((a
->defined
& NTA_HASTYPE
) != 0
2341 && (a
->eltype
.type
!= b
->eltype
.type
2342 || a
->eltype
.size
!= b
->eltype
.size
))
2345 if ((a
->defined
& NTA_HASINDEX
) != 0
2346 && (a
->index
!= b
->index
))
2352 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2353 The base register is put in *PBASE.
2354 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2356 The register stride (minus one) is put in bit 4 of the return value.
2357 Bits [6:5] encode the list length (minus one).
2358 The type of the list elements is put in *ELTYPE, if non-NULL. */
2360 #define NEON_LANE(X) ((X) & 0xf)
2361 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2362 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2365 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2367 struct neon_type_el
*eltype
)
2374 int leading_brace
= 0;
2375 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2376 const char *const incr_error
= mve
? _("register stride must be 1") :
2377 _("register stride must be 1 or 2");
2378 const char *const type_error
= _("mismatched element/structure types in list");
2379 struct neon_typed_alias firsttype
;
2380 firsttype
.defined
= 0;
2381 firsttype
.eltype
.type
= NT_invtype
;
2382 firsttype
.eltype
.size
= -1;
2383 firsttype
.index
= -1;
2385 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2390 struct neon_typed_alias atype
;
2392 rtype
= REG_TYPE_MQ
;
2393 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2397 first_error (_(reg_expected_msgs
[rtype
]));
2404 if (rtype
== REG_TYPE_NQ
)
2410 else if (reg_incr
== -1)
2412 reg_incr
= getreg
- base_reg
;
2413 if (reg_incr
< 1 || reg_incr
> 2)
2415 first_error (_(incr_error
));
2419 else if (getreg
!= base_reg
+ reg_incr
* count
)
2421 first_error (_(incr_error
));
2425 if (! neon_alias_types_same (&atype
, &firsttype
))
2427 first_error (_(type_error
));
2431 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2435 struct neon_typed_alias htype
;
2436 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2438 lane
= NEON_INTERLEAVE_LANES
;
2439 else if (lane
!= NEON_INTERLEAVE_LANES
)
2441 first_error (_(type_error
));
2446 else if (reg_incr
!= 1)
2448 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2452 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2455 first_error (_(reg_expected_msgs
[rtype
]));
2458 if (! neon_alias_types_same (&htype
, &firsttype
))
2460 first_error (_(type_error
));
2463 count
+= hireg
+ dregs
- getreg
;
2467 /* If we're using Q registers, we can't use [] or [n] syntax. */
2468 if (rtype
== REG_TYPE_NQ
)
2474 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2478 else if (lane
!= atype
.index
)
2480 first_error (_(type_error
));
2484 else if (lane
== -1)
2485 lane
= NEON_INTERLEAVE_LANES
;
2486 else if (lane
!= NEON_INTERLEAVE_LANES
)
2488 first_error (_(type_error
));
2493 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2495 /* No lane set by [x]. We must be interleaving structures. */
2497 lane
= NEON_INTERLEAVE_LANES
;
2500 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2501 || (count
> 1 && reg_incr
== -1))
2503 first_error (_("error parsing element/structure list"));
2507 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2509 first_error (_("expected }"));
2517 *eltype
= firsttype
.eltype
;
2522 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2525 /* Parse an explicit relocation suffix on an expression. This is
2526 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2527 arm_reloc_hsh contains no entries, so this function can only
2528 succeed if there is no () after the word. Returns -1 on error,
2529 BFD_RELOC_UNUSED if there wasn't any suffix. */
2532 parse_reloc (char **str
)
2534 struct reloc_entry
*r
;
2538 return BFD_RELOC_UNUSED
;
2543 while (*q
&& *q
!= ')' && *q
!= ',')
2548 if ((r
= (struct reloc_entry
*)
2549 str_hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2556 /* Directives: register aliases. */
2558 static struct reg_entry
*
2559 insert_reg_alias (char *str
, unsigned number
, int type
)
2561 struct reg_entry
*new_reg
;
2564 if ((new_reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, str
)) != 0)
2566 if (new_reg
->builtin
)
2567 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2569 /* Only warn about a redefinition if it's not defined as the
2571 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2572 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2577 name
= xstrdup (str
);
2578 new_reg
= XNEW (struct reg_entry
);
2580 new_reg
->name
= name
;
2581 new_reg
->number
= number
;
2582 new_reg
->type
= type
;
2583 new_reg
->builtin
= FALSE
;
2584 new_reg
->neon
= NULL
;
2586 str_hash_insert (arm_reg_hsh
, name
, new_reg
);
2592 insert_neon_reg_alias (char *str
, int number
, int type
,
2593 struct neon_typed_alias
*atype
)
2595 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2599 first_error (_("attempt to redefine typed alias"));
2605 reg
->neon
= XNEW (struct neon_typed_alias
);
2606 *reg
->neon
= *atype
;
2610 /* Look for the .req directive. This is of the form:
2612 new_register_name .req existing_register_name
2614 If we find one, or if it looks sufficiently like one that we want to
2615 handle any error here, return TRUE. Otherwise return FALSE. */
2618 create_register_alias (char * newname
, char *p
)
2620 struct reg_entry
*old
;
2621 char *oldname
, *nbuf
;
2624 /* The input scrubber ensures that whitespace after the mnemonic is
2625 collapsed to single spaces. */
2627 if (strncmp (oldname
, " .req ", 6) != 0)
2631 if (*oldname
== '\0')
2634 old
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, oldname
);
2637 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2641 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2642 the desired alias name, and p points to its end. If not, then
2643 the desired alias name is in the global original_case_string. */
2644 #ifdef TC_CASE_SENSITIVE
2647 newname
= original_case_string
;
2648 nlen
= strlen (newname
);
2651 nbuf
= xmemdup0 (newname
, nlen
);
2653 /* Create aliases under the new name as stated; an all-lowercase
2654 version of the new name; and an all-uppercase version of the new
2656 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2658 for (p
= nbuf
; *p
; p
++)
2661 if (strncmp (nbuf
, newname
, nlen
))
2663 /* If this attempt to create an additional alias fails, do not bother
2664 trying to create the all-lower case alias. We will fail and issue
2665 a second, duplicate error message. This situation arises when the
2666 programmer does something like:
2669 The second .req creates the "Foo" alias but then fails to create
2670 the artificial FOO alias because it has already been created by the
2672 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2679 for (p
= nbuf
; *p
; p
++)
2682 if (strncmp (nbuf
, newname
, nlen
))
2683 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2690 /* Create a Neon typed/indexed register alias using directives, e.g.:
2695 These typed registers can be used instead of the types specified after the
2696 Neon mnemonic, so long as all operands given have types. Types can also be
2697 specified directly, e.g.:
2698 vadd d0.s32, d1.s32, d2.s32 */
2701 create_neon_reg_alias (char *newname
, char *p
)
2703 enum arm_reg_type basetype
;
2704 struct reg_entry
*basereg
;
2705 struct reg_entry mybasereg
;
2706 struct neon_type ntype
;
2707 struct neon_typed_alias typeinfo
;
2708 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2711 typeinfo
.defined
= 0;
2712 typeinfo
.eltype
.type
= NT_invtype
;
2713 typeinfo
.eltype
.size
= -1;
2714 typeinfo
.index
= -1;
2718 if (strncmp (p
, " .dn ", 5) == 0)
2719 basetype
= REG_TYPE_VFD
;
2720 else if (strncmp (p
, " .qn ", 5) == 0)
2721 basetype
= REG_TYPE_NQ
;
2730 basereg
= arm_reg_parse_multi (&p
);
2732 if (basereg
&& basereg
->type
!= basetype
)
2734 as_bad (_("bad type for register"));
2738 if (basereg
== NULL
)
2741 /* Try parsing as an integer. */
2742 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2743 if (exp
.X_op
!= O_constant
)
2745 as_bad (_("expression must be constant"));
2748 basereg
= &mybasereg
;
2749 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2755 typeinfo
= *basereg
->neon
;
2757 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2759 /* We got a type. */
2760 if (typeinfo
.defined
& NTA_HASTYPE
)
2762 as_bad (_("can't redefine the type of a register alias"));
2766 typeinfo
.defined
|= NTA_HASTYPE
;
2767 if (ntype
.elems
!= 1)
2769 as_bad (_("you must specify a single type only"));
2772 typeinfo
.eltype
= ntype
.el
[0];
2775 if (skip_past_char (&p
, '[') == SUCCESS
)
2778 /* We got a scalar index. */
2780 if (typeinfo
.defined
& NTA_HASINDEX
)
2782 as_bad (_("can't redefine the index of a scalar alias"));
2786 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2788 if (exp
.X_op
!= O_constant
)
2790 as_bad (_("scalar index must be constant"));
2794 typeinfo
.defined
|= NTA_HASINDEX
;
2795 typeinfo
.index
= exp
.X_add_number
;
2797 if (skip_past_char (&p
, ']') == FAIL
)
2799 as_bad (_("expecting ]"));
2804 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2805 the desired alias name, and p points to its end. If not, then
2806 the desired alias name is in the global original_case_string. */
2807 #ifdef TC_CASE_SENSITIVE
2808 namelen
= nameend
- newname
;
2810 newname
= original_case_string
;
2811 namelen
= strlen (newname
);
2814 namebuf
= xmemdup0 (newname
, namelen
);
2816 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2817 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2819 /* Insert name in all uppercase. */
2820 for (p
= namebuf
; *p
; p
++)
2823 if (strncmp (namebuf
, newname
, namelen
))
2824 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2825 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2827 /* Insert name in all lowercase. */
2828 for (p
= namebuf
; *p
; p
++)
2831 if (strncmp (namebuf
, newname
, namelen
))
2832 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2833 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2839 /* Should never be called, as .req goes between the alias and the
2840 register name, not at the beginning of the line. */
2843 s_req (int a ATTRIBUTE_UNUSED
)
2845 as_bad (_("invalid syntax for .req directive"));
2849 s_dn (int a ATTRIBUTE_UNUSED
)
2851 as_bad (_("invalid syntax for .dn directive"));
2855 s_qn (int a ATTRIBUTE_UNUSED
)
2857 as_bad (_("invalid syntax for .qn directive"));
2860 /* The .unreq directive deletes an alias which was previously defined
2861 by .req. For example:
2867 s_unreq (int a ATTRIBUTE_UNUSED
)
2872 name
= input_line_pointer
;
2874 while (*input_line_pointer
!= 0
2875 && *input_line_pointer
!= ' '
2876 && *input_line_pointer
!= '\n')
2877 ++input_line_pointer
;
2879 saved_char
= *input_line_pointer
;
2880 *input_line_pointer
= 0;
2883 as_bad (_("invalid syntax for .unreq directive"));
2886 struct reg_entry
*reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
,
2890 as_bad (_("unknown register alias '%s'"), name
);
2891 else if (reg
->builtin
)
2892 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2899 str_hash_delete (arm_reg_hsh
, name
);
2900 free ((char *) reg
->name
);
2904 /* Also locate the all upper case and all lower case versions.
2905 Do not complain if we cannot find one or the other as it
2906 was probably deleted above. */
2908 nbuf
= strdup (name
);
2909 for (p
= nbuf
; *p
; p
++)
2911 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2914 str_hash_delete (arm_reg_hsh
, nbuf
);
2915 free ((char *) reg
->name
);
2920 for (p
= nbuf
; *p
; p
++)
2922 reg
= (struct reg_entry
*) str_hash_find (arm_reg_hsh
, nbuf
);
2925 str_hash_delete (arm_reg_hsh
, nbuf
);
2926 free ((char *) reg
->name
);
2935 *input_line_pointer
= saved_char
;
2936 demand_empty_rest_of_line ();
2939 /* Directives: Instruction set selection. */
2942 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2943 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2944 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2945 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2947 /* Create a new mapping symbol for the transition to STATE. */
2950 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2953 const char * symname
;
2960 type
= BSF_NO_FLAGS
;
2964 type
= BSF_NO_FLAGS
;
2968 type
= BSF_NO_FLAGS
;
2974 symbolP
= symbol_new (symname
, now_seg
, frag
, value
);
2975 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2980 THUMB_SET_FUNC (symbolP
, 0);
2981 ARM_SET_THUMB (symbolP
, 0);
2982 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2986 THUMB_SET_FUNC (symbolP
, 1);
2987 ARM_SET_THUMB (symbolP
, 1);
2988 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2996 /* Save the mapping symbols for future reference. Also check that
2997 we do not place two mapping symbols at the same offset within a
2998 frag. We'll handle overlap between frags in
2999 check_mapping_symbols.
3001 If .fill or other data filling directive generates zero sized data,
3002 the mapping symbol for the following code will have the same value
3003 as the one generated for the data filling directive. In this case,
3004 we replace the old symbol with the new one at the same address. */
3007 if (frag
->tc_frag_data
.first_map
!= NULL
)
3009 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
3010 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
3012 frag
->tc_frag_data
.first_map
= symbolP
;
3014 if (frag
->tc_frag_data
.last_map
!= NULL
)
3016 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
3017 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
3018 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
3020 frag
->tc_frag_data
.last_map
= symbolP
;
3023 /* We must sometimes convert a region marked as code to data during
3024 code alignment, if an odd number of bytes have to be padded. The
3025 code mapping symbol is pushed to an aligned address. */
3028 insert_data_mapping_symbol (enum mstate state
,
3029 valueT value
, fragS
*frag
, offsetT bytes
)
3031 /* If there was already a mapping symbol, remove it. */
3032 if (frag
->tc_frag_data
.last_map
!= NULL
3033 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
3035 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
3039 know (frag
->tc_frag_data
.first_map
== symp
);
3040 frag
->tc_frag_data
.first_map
= NULL
;
3042 frag
->tc_frag_data
.last_map
= NULL
;
3043 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
3046 make_mapping_symbol (MAP_DATA
, value
, frag
);
3047 make_mapping_symbol (state
, value
+ bytes
, frag
);
3050 static void mapping_state_2 (enum mstate state
, int max_chars
);
3052 /* Set the mapping state to STATE. Only call this when about to
3053 emit some STATE bytes to the file. */
3055 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
3057 mapping_state (enum mstate state
)
3059 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3061 if (mapstate
== state
)
3062 /* The mapping symbol has already been emitted.
3063 There is nothing else to do. */
3066 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
3068 All ARM instructions require 4-byte alignment.
3069 (Almost) all Thumb instructions require 2-byte alignment.
3071 When emitting instructions into any section, mark the section
3074 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3075 but themselves require 2-byte alignment; this applies to some
3076 PC- relative forms. However, these cases will involve implicit
3077 literal pool generation or an explicit .align >=2, both of
3078 which will cause the section to me marked with sufficient
3079 alignment. Thus, we don't handle those cases here. */
3080 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3082 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3083 /* This case will be evaluated later. */
3086 mapping_state_2 (state
, 0);
3089 /* Same as mapping_state, but MAX_CHARS bytes have already been
3090 allocated. Put the mapping symbol that far back. */
3093 mapping_state_2 (enum mstate state
, int max_chars
)
3095 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3097 if (!SEG_NORMAL (now_seg
))
3100 if (mapstate
== state
)
3101 /* The mapping symbol has already been emitted.
3102 There is nothing else to do. */
3105 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3106 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3108 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3109 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3112 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3115 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3116 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3120 #define mapping_state(x) ((void)0)
3121 #define mapping_state_2(x, y) ((void)0)
3124 /* Find the real, Thumb encoded start of a Thumb function. */
3128 find_real_start (symbolS
* symbolP
)
3131 const char * name
= S_GET_NAME (symbolP
);
3132 symbolS
* new_target
;
3134 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3135 #define STUB_NAME ".real_start_of"
3140 /* The compiler may generate BL instructions to local labels because
3141 it needs to perform a branch to a far away location. These labels
3142 do not have a corresponding ".real_start_of" label. We check
3143 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3144 the ".real_start_of" convention for nonlocal branches. */
3145 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3148 real_start
= concat (STUB_NAME
, name
, NULL
);
3149 new_target
= symbol_find (real_start
);
3152 if (new_target
== NULL
)
3154 as_warn (_("Failed to find real start of function: %s\n"), name
);
3155 new_target
= symbolP
;
3163 opcode_select (int width
)
3170 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3171 as_bad (_("selected processor does not support THUMB opcodes"));
3174 /* No need to force the alignment, since we will have been
3175 coming from ARM mode, which is word-aligned. */
3176 record_alignment (now_seg
, 1);
3183 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3184 as_bad (_("selected processor does not support ARM opcodes"));
3189 frag_align (2, 0, 0);
3191 record_alignment (now_seg
, 1);
3196 as_bad (_("invalid instruction size selected (%d)"), width
);
3201 s_arm (int ignore ATTRIBUTE_UNUSED
)
3204 demand_empty_rest_of_line ();
3208 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3211 demand_empty_rest_of_line ();
3215 s_code (int unused ATTRIBUTE_UNUSED
)
3219 temp
= get_absolute_expression ();
3224 opcode_select (temp
);
3228 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3233 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3235 /* If we are not already in thumb mode go into it, EVEN if
3236 the target processor does not support thumb instructions.
3237 This is used by gcc/config/arm/lib1funcs.asm for example
3238 to compile interworking support functions even if the
3239 target processor should not support interworking. */
3243 record_alignment (now_seg
, 1);
3246 demand_empty_rest_of_line ();
3250 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3254 /* The following label is the name/address of the start of a Thumb function.
3255 We need to know this for the interworking support. */
3256 label_is_thumb_function_name
= TRUE
;
3259 /* Perform a .set directive, but also mark the alias as
3260 being a thumb function. */
3263 s_thumb_set (int equiv
)
3265 /* XXX the following is a duplicate of the code for s_set() in read.c
3266 We cannot just call that code as we need to get at the symbol that
3273 /* Especial apologies for the random logic:
3274 This just grew, and could be parsed much more simply!
3276 delim
= get_symbol_name (& name
);
3277 end_name
= input_line_pointer
;
3278 (void) restore_line_pointer (delim
);
3280 if (*input_line_pointer
!= ',')
3283 as_bad (_("expected comma after name \"%s\""), name
);
3285 ignore_rest_of_line ();
3289 input_line_pointer
++;
3292 if (name
[0] == '.' && name
[1] == '\0')
3294 /* XXX - this should not happen to .thumb_set. */
3298 if ((symbolP
= symbol_find (name
)) == NULL
3299 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3302 /* When doing symbol listings, play games with dummy fragments living
3303 outside the normal fragment chain to record the file and line info
3305 if (listing
& LISTING_SYMBOLS
)
3307 extern struct list_info_struct
* listing_tail
;
3308 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3310 memset (dummy_frag
, 0, sizeof (fragS
));
3311 dummy_frag
->fr_type
= rs_fill
;
3312 dummy_frag
->line
= listing_tail
;
3313 symbolP
= symbol_new (name
, undefined_section
, dummy_frag
, 0);
3314 dummy_frag
->fr_symbol
= symbolP
;
3318 symbolP
= symbol_new (name
, undefined_section
, &zero_address_frag
, 0);
3321 /* "set" symbols are local unless otherwise specified. */
3322 SF_SET_LOCAL (symbolP
);
3323 #endif /* OBJ_COFF */
3324 } /* Make a new symbol. */
3326 symbol_table_insert (symbolP
);
3331 && S_IS_DEFINED (symbolP
)
3332 && S_GET_SEGMENT (symbolP
) != reg_section
)
3333 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3335 pseudo_set (symbolP
);
3337 demand_empty_rest_of_line ();
3339 /* XXX Now we come to the Thumb specific bit of code. */
3341 THUMB_SET_FUNC (symbolP
, 1);
3342 ARM_SET_THUMB (symbolP
, 1);
3343 #if defined OBJ_ELF || defined OBJ_COFF
3344 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3348 /* Directives: Mode selection. */
3350 /* .syntax [unified|divided] - choose the new unified syntax
3351 (same for Arm and Thumb encoding, modulo slight differences in what
3352 can be represented) or the old divergent syntax for each mode. */
3354 s_syntax (int unused ATTRIBUTE_UNUSED
)
3358 delim
= get_symbol_name (& name
);
3360 if (!strcasecmp (name
, "unified"))
3361 unified_syntax
= TRUE
;
3362 else if (!strcasecmp (name
, "divided"))
3363 unified_syntax
= FALSE
;
3366 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3369 (void) restore_line_pointer (delim
);
3370 demand_empty_rest_of_line ();
3373 /* Directives: sectioning and alignment. */
3376 s_bss (int ignore ATTRIBUTE_UNUSED
)
3378 /* We don't support putting frags in the BSS segment, we fake it by
3379 marking in_bss, then looking at s_skip for clues. */
3380 subseg_set (bss_section
, 0);
3381 demand_empty_rest_of_line ();
3383 #ifdef md_elf_section_change_hook
3384 md_elf_section_change_hook ();
3389 s_even (int ignore ATTRIBUTE_UNUSED
)
3391 /* Never make frag if expect extra pass. */
3393 frag_align (1, 0, 0);
3395 record_alignment (now_seg
, 1);
3397 demand_empty_rest_of_line ();
3400 /* Directives: CodeComposer Studio. */
3402 /* .ref (for CodeComposer Studio syntax only). */
3404 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3406 if (codecomposer_syntax
)
3407 ignore_rest_of_line ();
3409 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3412 /* If name is not NULL, then it is used for marking the beginning of a
3413 function, whereas if it is NULL then it means the function end. */
3415 asmfunc_debug (const char * name
)
3417 static const char * last_name
= NULL
;
3421 gas_assert (last_name
== NULL
);
3424 if (debug_type
== DEBUG_STABS
)
3425 stabs_generate_asm_func (name
, name
);
3429 gas_assert (last_name
!= NULL
);
3431 if (debug_type
== DEBUG_STABS
)
3432 stabs_generate_asm_endfunc (last_name
, last_name
);
3439 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3441 if (codecomposer_syntax
)
3443 switch (asmfunc_state
)
3445 case OUTSIDE_ASMFUNC
:
3446 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3449 case WAITING_ASMFUNC_NAME
:
3450 as_bad (_(".asmfunc repeated."));
3453 case WAITING_ENDASMFUNC
:
3454 as_bad (_(".asmfunc without function."));
3457 demand_empty_rest_of_line ();
3460 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3464 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3466 if (codecomposer_syntax
)
3468 switch (asmfunc_state
)
3470 case OUTSIDE_ASMFUNC
:
3471 as_bad (_(".endasmfunc without a .asmfunc."));
3474 case WAITING_ASMFUNC_NAME
:
3475 as_bad (_(".endasmfunc without function."));
3478 case WAITING_ENDASMFUNC
:
3479 asmfunc_state
= OUTSIDE_ASMFUNC
;
3480 asmfunc_debug (NULL
);
3483 demand_empty_rest_of_line ();
3486 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3490 s_ccs_def (int name
)
3492 if (codecomposer_syntax
)
3495 as_bad (_(".def pseudo-op only available with -mccs flag."));
3498 /* Directives: Literal pools. */
3500 static literal_pool
*
3501 find_literal_pool (void)
3503 literal_pool
* pool
;
3505 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3507 if (pool
->section
== now_seg
3508 && pool
->sub_section
== now_subseg
)
3515 static literal_pool
*
3516 find_or_make_literal_pool (void)
3518 /* Next literal pool ID number. */
3519 static unsigned int latest_pool_num
= 1;
3520 literal_pool
* pool
;
3522 pool
= find_literal_pool ();
3526 /* Create a new pool. */
3527 pool
= XNEW (literal_pool
);
3531 pool
->next_free_entry
= 0;
3532 pool
->section
= now_seg
;
3533 pool
->sub_section
= now_subseg
;
3534 pool
->next
= list_of_pools
;
3535 pool
->symbol
= NULL
;
3536 pool
->alignment
= 2;
3538 /* Add it to the list. */
3539 list_of_pools
= pool
;
3542 /* New pools, and emptied pools, will have a NULL symbol. */
3543 if (pool
->symbol
== NULL
)
3545 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3546 &zero_address_frag
, 0);
3547 pool
->id
= latest_pool_num
++;
3554 /* Add the literal in the global 'inst'
3555 structure to the relevant literal pool. */
3558 add_to_lit_pool (unsigned int nbytes
)
3560 #define PADDING_SLOT 0x1
3561 #define LIT_ENTRY_SIZE_MASK 0xFF
3562 literal_pool
* pool
;
3563 unsigned int entry
, pool_size
= 0;
3564 bfd_boolean padding_slot_p
= FALSE
;
3570 imm1
= inst
.operands
[1].imm
;
3571 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3572 : inst
.relocs
[0].exp
.X_unsigned
? 0
3573 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3574 if (target_big_endian
)
3577 imm2
= inst
.operands
[1].imm
;
3581 pool
= find_or_make_literal_pool ();
3583 /* Check if this literal value is already in the pool. */
3584 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3588 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3589 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3590 && (pool
->literals
[entry
].X_add_number
3591 == inst
.relocs
[0].exp
.X_add_number
)
3592 && (pool
->literals
[entry
].X_md
== nbytes
)
3593 && (pool
->literals
[entry
].X_unsigned
3594 == inst
.relocs
[0].exp
.X_unsigned
))
3597 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3598 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3599 && (pool
->literals
[entry
].X_add_number
3600 == inst
.relocs
[0].exp
.X_add_number
)
3601 && (pool
->literals
[entry
].X_add_symbol
3602 == inst
.relocs
[0].exp
.X_add_symbol
)
3603 && (pool
->literals
[entry
].X_op_symbol
3604 == inst
.relocs
[0].exp
.X_op_symbol
)
3605 && (pool
->literals
[entry
].X_md
== nbytes
))
3608 else if ((nbytes
== 8)
3609 && !(pool_size
& 0x7)
3610 && ((entry
+ 1) != pool
->next_free_entry
)
3611 && (pool
->literals
[entry
].X_op
== O_constant
)
3612 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3613 && (pool
->literals
[entry
].X_unsigned
3614 == inst
.relocs
[0].exp
.X_unsigned
)
3615 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3616 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3617 && (pool
->literals
[entry
+ 1].X_unsigned
3618 == inst
.relocs
[0].exp
.X_unsigned
))
3621 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3622 if (padding_slot_p
&& (nbytes
== 4))
3628 /* Do we need to create a new entry? */
3629 if (entry
== pool
->next_free_entry
)
3631 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3633 inst
.error
= _("literal pool overflow");
3639 /* For 8-byte entries, we align to an 8-byte boundary,
3640 and split it into two 4-byte entries, because on 32-bit
3641 host, 8-byte constants are treated as big num, thus
3642 saved in "generic_bignum" which will be overwritten
3643 by later assignments.
3645 We also need to make sure there is enough space for
3648 We also check to make sure the literal operand is a
3650 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3651 || inst
.relocs
[0].exp
.X_op
== O_big
))
3653 inst
.error
= _("invalid type for literal pool");
3656 else if (pool_size
& 0x7)
3658 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3660 inst
.error
= _("literal pool overflow");
3664 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3665 pool
->literals
[entry
].X_op
= O_constant
;
3666 pool
->literals
[entry
].X_add_number
= 0;
3667 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3668 pool
->next_free_entry
+= 1;
3671 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3673 inst
.error
= _("literal pool overflow");
3677 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3678 pool
->literals
[entry
].X_op
= O_constant
;
3679 pool
->literals
[entry
].X_add_number
= imm1
;
3680 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3681 pool
->literals
[entry
++].X_md
= 4;
3682 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3683 pool
->literals
[entry
].X_op
= O_constant
;
3684 pool
->literals
[entry
].X_add_number
= imm2
;
3685 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3686 pool
->literals
[entry
].X_md
= 4;
3687 pool
->alignment
= 3;
3688 pool
->next_free_entry
+= 1;
3692 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3693 pool
->literals
[entry
].X_md
= 4;
3697 /* PR ld/12974: Record the location of the first source line to reference
3698 this entry in the literal pool. If it turns out during linking that the
3699 symbol does not exist we will be able to give an accurate line number for
3700 the (first use of the) missing reference. */
3701 if (debug_type
== DEBUG_DWARF2
)
3702 dwarf2_where (pool
->locs
+ entry
);
3704 pool
->next_free_entry
+= 1;
3706 else if (padding_slot_p
)
3708 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3709 pool
->literals
[entry
].X_md
= nbytes
;
3712 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3713 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3714 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3720 tc_start_label_without_colon (void)
3722 bfd_boolean ret
= TRUE
;
3724 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3726 const char *label
= input_line_pointer
;
3728 while (!is_end_of_line
[(int) label
[-1]])
3733 as_bad (_("Invalid label '%s'"), label
);
3737 asmfunc_debug (label
);
3739 asmfunc_state
= WAITING_ENDASMFUNC
;
3745 /* Can't use symbol_new here, so have to create a symbol and then at
3746 a later date assign it a value. That's what these functions do. */
3749 symbol_locate (symbolS
* symbolP
,
3750 const char * name
, /* It is copied, the caller can modify. */
3751 segT segment
, /* Segment identifier (SEG_<something>). */
3752 valueT valu
, /* Symbol value. */
3753 fragS
* frag
) /* Associated fragment. */
3756 char * preserved_copy_of_name
;
3758 name_length
= strlen (name
) + 1; /* +1 for \0. */
3759 obstack_grow (¬es
, name
, name_length
);
3760 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3762 #ifdef tc_canonicalize_symbol_name
3763 preserved_copy_of_name
=
3764 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3767 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3769 S_SET_SEGMENT (symbolP
, segment
);
3770 S_SET_VALUE (symbolP
, valu
);
3771 symbol_clear_list_pointers (symbolP
);
3773 symbol_set_frag (symbolP
, frag
);
3775 /* Link to end of symbol chain. */
3777 extern int symbol_table_frozen
;
3779 if (symbol_table_frozen
)
3783 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3785 obj_symbol_new_hook (symbolP
);
3787 #ifdef tc_symbol_new_hook
3788 tc_symbol_new_hook (symbolP
);
3792 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3793 #endif /* DEBUG_SYMS */
3797 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3800 literal_pool
* pool
;
3803 pool
= find_literal_pool ();
3805 || pool
->symbol
== NULL
3806 || pool
->next_free_entry
== 0)
3809 /* Align pool as you have word accesses.
3810 Only make a frag if we have to. */
3812 frag_align (pool
->alignment
, 0, 0);
3814 record_alignment (now_seg
, 2);
3817 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3818 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3820 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3822 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3823 (valueT
) frag_now_fix (), frag_now
);
3824 symbol_table_insert (pool
->symbol
);
3826 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3828 #if defined OBJ_COFF || defined OBJ_ELF
3829 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3832 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3835 if (debug_type
== DEBUG_DWARF2
)
3836 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3838 /* First output the expression in the instruction to the pool. */
3839 emit_expr (&(pool
->literals
[entry
]),
3840 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3843 /* Mark the pool as empty. */
3844 pool
->next_free_entry
= 0;
3845 pool
->symbol
= NULL
;
3849 /* Forward declarations for functions below, in the MD interface
3851 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3852 static valueT
create_unwind_entry (int);
3853 static void start_unwind_section (const segT
, int);
3854 static void add_unwind_opcode (valueT
, int);
3855 static void flush_pending_unwind (void);
3857 /* Directives: Data. */
3860 s_arm_elf_cons (int nbytes
)
3864 #ifdef md_flush_pending_output
3865 md_flush_pending_output ();
3868 if (is_it_end_of_statement ())
3870 demand_empty_rest_of_line ();
3874 #ifdef md_cons_align
3875 md_cons_align (nbytes
);
3878 mapping_state (MAP_DATA
);
3882 char *base
= input_line_pointer
;
3886 if (exp
.X_op
!= O_symbol
)
3887 emit_expr (&exp
, (unsigned int) nbytes
);
3890 char *before_reloc
= input_line_pointer
;
3891 reloc
= parse_reloc (&input_line_pointer
);
3894 as_bad (_("unrecognized relocation suffix"));
3895 ignore_rest_of_line ();
3898 else if (reloc
== BFD_RELOC_UNUSED
)
3899 emit_expr (&exp
, (unsigned int) nbytes
);
3902 reloc_howto_type
*howto
= (reloc_howto_type
*)
3903 bfd_reloc_type_lookup (stdoutput
,
3904 (bfd_reloc_code_real_type
) reloc
);
3905 int size
= bfd_get_reloc_size (howto
);
3907 if (reloc
== BFD_RELOC_ARM_PLT32
)
3909 as_bad (_("(plt) is only valid on branch targets"));
3910 reloc
= BFD_RELOC_UNUSED
;
3915 as_bad (ngettext ("%s relocations do not fit in %d byte",
3916 "%s relocations do not fit in %d bytes",
3918 howto
->name
, nbytes
);
3921 /* We've parsed an expression stopping at O_symbol.
3922 But there may be more expression left now that we
3923 have parsed the relocation marker. Parse it again.
3924 XXX Surely there is a cleaner way to do this. */
3925 char *p
= input_line_pointer
;
3927 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3929 memcpy (save_buf
, base
, input_line_pointer
- base
);
3930 memmove (base
+ (input_line_pointer
- before_reloc
),
3931 base
, before_reloc
- base
);
3933 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3935 memcpy (base
, save_buf
, p
- base
);
3937 offset
= nbytes
- size
;
3938 p
= frag_more (nbytes
);
3939 memset (p
, 0, nbytes
);
3940 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3941 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3947 while (*input_line_pointer
++ == ',');
3949 /* Put terminator back into stream. */
3950 input_line_pointer
--;
3951 demand_empty_rest_of_line ();
3954 /* Emit an expression containing a 32-bit thumb instruction.
3955 Implementation based on put_thumb32_insn. */
3958 emit_thumb32_expr (expressionS
* exp
)
3960 expressionS exp_high
= *exp
;
3962 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3963 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3964 exp
->X_add_number
&= 0xffff;
3965 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3968 /* Guess the instruction size based on the opcode. */
3971 thumb_insn_size (int opcode
)
3973 if ((unsigned int) opcode
< 0xe800u
)
3975 else if ((unsigned int) opcode
>= 0xe8000000u
)
3982 emit_insn (expressionS
*exp
, int nbytes
)
3986 if (exp
->X_op
== O_constant
)
3991 size
= thumb_insn_size (exp
->X_add_number
);
3995 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3997 as_bad (_(".inst.n operand too big. "\
3998 "Use .inst.w instead"));
4003 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
4004 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
4006 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
4008 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
4009 emit_thumb32_expr (exp
);
4011 emit_expr (exp
, (unsigned int) size
);
4013 it_fsm_post_encode ();
4017 as_bad (_("cannot determine Thumb instruction size. " \
4018 "Use .inst.n/.inst.w instead"));
4021 as_bad (_("constant expression required"));
4026 /* Like s_arm_elf_cons but do not use md_cons_align and
4027 set the mapping state to MAP_ARM/MAP_THUMB. */
4030 s_arm_elf_inst (int nbytes
)
4032 if (is_it_end_of_statement ())
4034 demand_empty_rest_of_line ();
4038 /* Calling mapping_state () here will not change ARM/THUMB,
4039 but will ensure not to be in DATA state. */
4042 mapping_state (MAP_THUMB
);
4047 as_bad (_("width suffixes are invalid in ARM mode"));
4048 ignore_rest_of_line ();
4054 mapping_state (MAP_ARM
);
4063 if (! emit_insn (& exp
, nbytes
))
4065 ignore_rest_of_line ();
4069 while (*input_line_pointer
++ == ',');
4071 /* Put terminator back into stream. */
4072 input_line_pointer
--;
4073 demand_empty_rest_of_line ();
4076 /* Parse a .rel31 directive. */
4079 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4086 if (*input_line_pointer
== '1')
4087 highbit
= 0x80000000;
4088 else if (*input_line_pointer
!= '0')
4089 as_bad (_("expected 0 or 1"));
4091 input_line_pointer
++;
4092 if (*input_line_pointer
!= ',')
4093 as_bad (_("missing comma"));
4094 input_line_pointer
++;
4096 #ifdef md_flush_pending_output
4097 md_flush_pending_output ();
4100 #ifdef md_cons_align
4104 mapping_state (MAP_DATA
);
4109 md_number_to_chars (p
, highbit
, 4);
4110 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4111 BFD_RELOC_ARM_PREL31
);
4113 demand_empty_rest_of_line ();
4116 /* Directives: AEABI stack-unwind tables. */
4118 /* Parse an unwind_fnstart directive. Simply records the current location. */
4121 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4123 demand_empty_rest_of_line ();
4124 if (unwind
.proc_start
)
4126 as_bad (_("duplicate .fnstart directive"));
4130 /* Mark the start of the function. */
4131 unwind
.proc_start
= expr_build_dot ();
4133 /* Reset the rest of the unwind info. */
4134 unwind
.opcode_count
= 0;
4135 unwind
.table_entry
= NULL
;
4136 unwind
.personality_routine
= NULL
;
4137 unwind
.personality_index
= -1;
4138 unwind
.frame_size
= 0;
4139 unwind
.fp_offset
= 0;
4140 unwind
.fp_reg
= REG_SP
;
4142 unwind
.sp_restored
= 0;
4146 /* Parse a handlerdata directive. Creates the exception handling table entry
4147 for the function. */
4150 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4152 demand_empty_rest_of_line ();
4153 if (!unwind
.proc_start
)
4154 as_bad (MISSING_FNSTART
);
4156 if (unwind
.table_entry
)
4157 as_bad (_("duplicate .handlerdata directive"));
4159 create_unwind_entry (1);
4162 /* Parse an unwind_fnend directive. Generates the index table entry. */
4165 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4170 unsigned int marked_pr_dependency
;
4172 demand_empty_rest_of_line ();
4174 if (!unwind
.proc_start
)
4176 as_bad (_(".fnend directive without .fnstart"));
4180 /* Add eh table entry. */
4181 if (unwind
.table_entry
== NULL
)
4182 val
= create_unwind_entry (0);
4186 /* Add index table entry. This is two words. */
4187 start_unwind_section (unwind
.saved_seg
, 1);
4188 frag_align (2, 0, 0);
4189 record_alignment (now_seg
, 2);
4191 ptr
= frag_more (8);
4193 where
= frag_now_fix () - 8;
4195 /* Self relative offset of the function start. */
4196 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4197 BFD_RELOC_ARM_PREL31
);
4199 /* Indicate dependency on EHABI-defined personality routines to the
4200 linker, if it hasn't been done already. */
4201 marked_pr_dependency
4202 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4203 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4204 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4206 static const char *const name
[] =
4208 "__aeabi_unwind_cpp_pr0",
4209 "__aeabi_unwind_cpp_pr1",
4210 "__aeabi_unwind_cpp_pr2"
4212 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4213 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4214 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4215 |= 1 << unwind
.personality_index
;
4219 /* Inline exception table entry. */
4220 md_number_to_chars (ptr
+ 4, val
, 4);
4222 /* Self relative offset of the table entry. */
4223 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4224 BFD_RELOC_ARM_PREL31
);
4226 /* Restore the original section. */
4227 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4229 unwind
.proc_start
= NULL
;
4233 /* Parse an unwind_cantunwind directive. */
4236 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4238 demand_empty_rest_of_line ();
4239 if (!unwind
.proc_start
)
4240 as_bad (MISSING_FNSTART
);
4242 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4243 as_bad (_("personality routine specified for cantunwind frame"));
4245 unwind
.personality_index
= -2;
4249 /* Parse a personalityindex directive. */
4252 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4256 if (!unwind
.proc_start
)
4257 as_bad (MISSING_FNSTART
);
4259 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4260 as_bad (_("duplicate .personalityindex directive"));
4264 if (exp
.X_op
!= O_constant
4265 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4267 as_bad (_("bad personality routine number"));
4268 ignore_rest_of_line ();
4272 unwind
.personality_index
= exp
.X_add_number
;
4274 demand_empty_rest_of_line ();
4278 /* Parse a personality directive. */
4281 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4285 if (!unwind
.proc_start
)
4286 as_bad (MISSING_FNSTART
);
4288 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4289 as_bad (_("duplicate .personality directive"));
4291 c
= get_symbol_name (& name
);
4292 p
= input_line_pointer
;
4294 ++ input_line_pointer
;
4295 unwind
.personality_routine
= symbol_find_or_make (name
);
4297 demand_empty_rest_of_line ();
4301 /* Parse a directive saving core registers. */
4304 s_arm_unwind_save_core (void)
4310 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4313 as_bad (_("expected register list"));
4314 ignore_rest_of_line ();
4318 demand_empty_rest_of_line ();
4320 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4321 into .unwind_save {..., sp...}. We aren't bothered about the value of
4322 ip because it is clobbered by calls. */
4323 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4324 && (range
& 0x3000) == 0x1000)
4326 unwind
.opcode_count
--;
4327 unwind
.sp_restored
= 0;
4328 range
= (range
| 0x2000) & ~0x1000;
4329 unwind
.pending_offset
= 0;
4335 /* See if we can use the short opcodes. These pop a block of up to 8
4336 registers starting with r4, plus maybe r14. */
4337 for (n
= 0; n
< 8; n
++)
4339 /* Break at the first non-saved register. */
4340 if ((range
& (1 << (n
+ 4))) == 0)
4343 /* See if there are any other bits set. */
4344 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4346 /* Use the long form. */
4347 op
= 0x8000 | ((range
>> 4) & 0xfff);
4348 add_unwind_opcode (op
, 2);
4352 /* Use the short form. */
4354 op
= 0xa8; /* Pop r14. */
4356 op
= 0xa0; /* Do not pop r14. */
4358 add_unwind_opcode (op
, 1);
4365 op
= 0xb100 | (range
& 0xf);
4366 add_unwind_opcode (op
, 2);
4369 /* Record the number of bytes pushed. */
4370 for (n
= 0; n
< 16; n
++)
4372 if (range
& (1 << n
))
4373 unwind
.frame_size
+= 4;
4378 /* Parse a directive saving FPA registers. */
4381 s_arm_unwind_save_fpa (int reg
)
4387 /* Get Number of registers to transfer. */
4388 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4391 exp
.X_op
= O_illegal
;
4393 if (exp
.X_op
!= O_constant
)
4395 as_bad (_("expected , <constant>"));
4396 ignore_rest_of_line ();
4400 num_regs
= exp
.X_add_number
;
4402 if (num_regs
< 1 || num_regs
> 4)
4404 as_bad (_("number of registers must be in the range [1:4]"));
4405 ignore_rest_of_line ();
4409 demand_empty_rest_of_line ();
4414 op
= 0xb4 | (num_regs
- 1);
4415 add_unwind_opcode (op
, 1);
4420 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4421 add_unwind_opcode (op
, 2);
4423 unwind
.frame_size
+= num_regs
* 12;
4427 /* Parse a directive saving VFP registers for ARMv6 and above. */
4430 s_arm_unwind_save_vfp_armv6 (void)
4435 int num_vfpv3_regs
= 0;
4436 int num_regs_below_16
;
4437 bfd_boolean partial_match
;
4439 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4443 as_bad (_("expected register list"));
4444 ignore_rest_of_line ();
4448 demand_empty_rest_of_line ();
4450 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4451 than FSTMX/FLDMX-style ones). */
4453 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4455 num_vfpv3_regs
= count
;
4456 else if (start
+ count
> 16)
4457 num_vfpv3_regs
= start
+ count
- 16;
4459 if (num_vfpv3_regs
> 0)
4461 int start_offset
= start
> 16 ? start
- 16 : 0;
4462 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4463 add_unwind_opcode (op
, 2);
4466 /* Generate opcode for registers numbered in the range 0 .. 15. */
4467 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4468 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4469 if (num_regs_below_16
> 0)
4471 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4472 add_unwind_opcode (op
, 2);
4475 unwind
.frame_size
+= count
* 8;
4479 /* Parse a directive saving VFP registers for pre-ARMv6. */
4482 s_arm_unwind_save_vfp (void)
4487 bfd_boolean partial_match
;
4489 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4493 as_bad (_("expected register list"));
4494 ignore_rest_of_line ();
4498 demand_empty_rest_of_line ();
4503 op
= 0xb8 | (count
- 1);
4504 add_unwind_opcode (op
, 1);
4509 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4510 add_unwind_opcode (op
, 2);
4512 unwind
.frame_size
+= count
* 8 + 4;
4516 /* Parse a directive saving iWMMXt data registers. */
4519 s_arm_unwind_save_mmxwr (void)
4527 if (*input_line_pointer
== '{')
4528 input_line_pointer
++;
4532 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4536 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4541 as_tsktsk (_("register list not in ascending order"));
4544 if (*input_line_pointer
== '-')
4546 input_line_pointer
++;
4547 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4550 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4553 else if (reg
>= hi_reg
)
4555 as_bad (_("bad register range"));
4558 for (; reg
< hi_reg
; reg
++)
4562 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4564 skip_past_char (&input_line_pointer
, '}');
4566 demand_empty_rest_of_line ();
4568 /* Generate any deferred opcodes because we're going to be looking at
4570 flush_pending_unwind ();
4572 for (i
= 0; i
< 16; i
++)
4574 if (mask
& (1 << i
))
4575 unwind
.frame_size
+= 8;
4578 /* Attempt to combine with a previous opcode. We do this because gcc
4579 likes to output separate unwind directives for a single block of
4581 if (unwind
.opcode_count
> 0)
4583 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4584 if ((i
& 0xf8) == 0xc0)
4587 /* Only merge if the blocks are contiguous. */
4590 if ((mask
& 0xfe00) == (1 << 9))
4592 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4593 unwind
.opcode_count
--;
4596 else if (i
== 6 && unwind
.opcode_count
>= 2)
4598 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4602 op
= 0xffff << (reg
- 1);
4604 && ((mask
& op
) == (1u << (reg
- 1))))
4606 op
= (1 << (reg
+ i
+ 1)) - 1;
4607 op
&= ~((1 << reg
) - 1);
4609 unwind
.opcode_count
-= 2;
4616 /* We want to generate opcodes in the order the registers have been
4617 saved, ie. descending order. */
4618 for (reg
= 15; reg
>= -1; reg
--)
4620 /* Save registers in blocks. */
4622 || !(mask
& (1 << reg
)))
4624 /* We found an unsaved reg. Generate opcodes to save the
4631 op
= 0xc0 | (hi_reg
- 10);
4632 add_unwind_opcode (op
, 1);
4637 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4638 add_unwind_opcode (op
, 2);
4647 ignore_rest_of_line ();
4651 s_arm_unwind_save_mmxwcg (void)
4658 if (*input_line_pointer
== '{')
4659 input_line_pointer
++;
4661 skip_whitespace (input_line_pointer
);
4665 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4669 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4675 as_tsktsk (_("register list not in ascending order"));
4678 if (*input_line_pointer
== '-')
4680 input_line_pointer
++;
4681 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4684 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4687 else if (reg
>= hi_reg
)
4689 as_bad (_("bad register range"));
4692 for (; reg
< hi_reg
; reg
++)
4696 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4698 skip_past_char (&input_line_pointer
, '}');
4700 demand_empty_rest_of_line ();
4702 /* Generate any deferred opcodes because we're going to be looking at
4704 flush_pending_unwind ();
4706 for (reg
= 0; reg
< 16; reg
++)
4708 if (mask
& (1 << reg
))
4709 unwind
.frame_size
+= 4;
4712 add_unwind_opcode (op
, 2);
4715 ignore_rest_of_line ();
4719 /* Parse an unwind_save directive.
4720 If the argument is non-zero, this is a .vsave directive. */
4723 s_arm_unwind_save (int arch_v6
)
4726 struct reg_entry
*reg
;
4727 bfd_boolean had_brace
= FALSE
;
4729 if (!unwind
.proc_start
)
4730 as_bad (MISSING_FNSTART
);
4732 /* Figure out what sort of save we have. */
4733 peek
= input_line_pointer
;
4741 reg
= arm_reg_parse_multi (&peek
);
4745 as_bad (_("register expected"));
4746 ignore_rest_of_line ();
4755 as_bad (_("FPA .unwind_save does not take a register list"));
4756 ignore_rest_of_line ();
4759 input_line_pointer
= peek
;
4760 s_arm_unwind_save_fpa (reg
->number
);
4764 s_arm_unwind_save_core ();
4769 s_arm_unwind_save_vfp_armv6 ();
4771 s_arm_unwind_save_vfp ();
4774 case REG_TYPE_MMXWR
:
4775 s_arm_unwind_save_mmxwr ();
4778 case REG_TYPE_MMXWCG
:
4779 s_arm_unwind_save_mmxwcg ();
4783 as_bad (_(".unwind_save does not support this kind of register"));
4784 ignore_rest_of_line ();
4789 /* Parse an unwind_movsp directive. */
4792 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4798 if (!unwind
.proc_start
)
4799 as_bad (MISSING_FNSTART
);
4801 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4804 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4805 ignore_rest_of_line ();
4809 /* Optional constant. */
4810 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4812 if (immediate_for_directive (&offset
) == FAIL
)
4818 demand_empty_rest_of_line ();
4820 if (reg
== REG_SP
|| reg
== REG_PC
)
4822 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4826 if (unwind
.fp_reg
!= REG_SP
)
4827 as_bad (_("unexpected .unwind_movsp directive"));
4829 /* Generate opcode to restore the value. */
4831 add_unwind_opcode (op
, 1);
4833 /* Record the information for later. */
4834 unwind
.fp_reg
= reg
;
4835 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4836 unwind
.sp_restored
= 1;
4839 /* Parse an unwind_pad directive. */
4842 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4846 if (!unwind
.proc_start
)
4847 as_bad (MISSING_FNSTART
);
4849 if (immediate_for_directive (&offset
) == FAIL
)
4854 as_bad (_("stack increment must be multiple of 4"));
4855 ignore_rest_of_line ();
4859 /* Don't generate any opcodes, just record the details for later. */
4860 unwind
.frame_size
+= offset
;
4861 unwind
.pending_offset
+= offset
;
4863 demand_empty_rest_of_line ();
4866 /* Parse an unwind_setfp directive. */
4869 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4875 if (!unwind
.proc_start
)
4876 as_bad (MISSING_FNSTART
);
4878 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4879 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4882 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4884 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4886 as_bad (_("expected <reg>, <reg>"));
4887 ignore_rest_of_line ();
4891 /* Optional constant. */
4892 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4894 if (immediate_for_directive (&offset
) == FAIL
)
4900 demand_empty_rest_of_line ();
4902 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4904 as_bad (_("register must be either sp or set by a previous"
4905 "unwind_movsp directive"));
4909 /* Don't generate any opcodes, just record the information for later. */
4910 unwind
.fp_reg
= fp_reg
;
4912 if (sp_reg
== REG_SP
)
4913 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4915 unwind
.fp_offset
-= offset
;
4918 /* Parse an unwind_raw directive. */
4921 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4924 /* This is an arbitrary limit. */
4925 unsigned char op
[16];
4928 if (!unwind
.proc_start
)
4929 as_bad (MISSING_FNSTART
);
4932 if (exp
.X_op
== O_constant
4933 && skip_past_comma (&input_line_pointer
) != FAIL
)
4935 unwind
.frame_size
+= exp
.X_add_number
;
4939 exp
.X_op
= O_illegal
;
4941 if (exp
.X_op
!= O_constant
)
4943 as_bad (_("expected <offset>, <opcode>"));
4944 ignore_rest_of_line ();
4950 /* Parse the opcode. */
4955 as_bad (_("unwind opcode too long"));
4956 ignore_rest_of_line ();
4958 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4960 as_bad (_("invalid unwind opcode"));
4961 ignore_rest_of_line ();
4964 op
[count
++] = exp
.X_add_number
;
4966 /* Parse the next byte. */
4967 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4973 /* Add the opcode bytes in reverse order. */
4975 add_unwind_opcode (op
[count
], 1);
4977 demand_empty_rest_of_line ();
4981 /* Parse a .eabi_attribute directive. */
4984 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4986 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4988 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4989 attributes_set_explicitly
[tag
] = 1;
4992 /* Emit a tls fix for the symbol. */
4995 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4999 #ifdef md_flush_pending_output
5000 md_flush_pending_output ();
5003 #ifdef md_cons_align
5007 /* Since we're just labelling the code, there's no need to define a
5010 p
= obstack_next_free (&frchain_now
->frch_obstack
);
5011 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
5012 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
5013 : BFD_RELOC_ARM_TLS_DESCSEQ
);
5015 #endif /* OBJ_ELF */
5017 static void s_arm_arch (int);
5018 static void s_arm_object_arch (int);
5019 static void s_arm_cpu (int);
5020 static void s_arm_fpu (int);
5021 static void s_arm_arch_extension (int);
5026 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
5033 if (exp
.X_op
== O_symbol
)
5034 exp
.X_op
= O_secrel
;
5036 emit_expr (&exp
, 4);
5038 while (*input_line_pointer
++ == ',');
5040 input_line_pointer
--;
5041 demand_empty_rest_of_line ();
5046 arm_is_largest_exponent_ok (int precision
)
5048 /* precision == 1 ensures that this will only return
5049 true for 16 bit floats. */
5050 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
5054 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
5058 enum fp_16bit_format new_format
;
5060 new_format
= ARM_FP16_FORMAT_DEFAULT
;
5062 name
= input_line_pointer
;
5063 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
5064 input_line_pointer
++;
5066 saved_char
= *input_line_pointer
;
5067 *input_line_pointer
= 0;
5069 if (strcasecmp (name
, "ieee") == 0)
5070 new_format
= ARM_FP16_FORMAT_IEEE
;
5071 else if (strcasecmp (name
, "alternative") == 0)
5072 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5075 as_bad (_("unrecognised float16 format \"%s\""), name
);
5079 /* Only set fp16_format if it is still the default (aka not already
5081 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5082 fp16_format
= new_format
;
5085 if (new_format
!= fp16_format
)
5086 as_warn (_("float16 format cannot be set more than once, ignoring."));
5090 *input_line_pointer
= saved_char
;
5091 ignore_rest_of_line ();
5094 /* This table describes all the machine specific pseudo-ops the assembler
5095 has to support. The fields are:
5096 pseudo-op name without dot
5097 function to call to execute this pseudo-op
5098 Integer arg to pass to the function. */
5100 const pseudo_typeS md_pseudo_table
[] =
5102 /* Never called because '.req' does not start a line. */
5103 { "req", s_req
, 0 },
5104 /* Following two are likewise never called. */
5107 { "unreq", s_unreq
, 0 },
5108 { "bss", s_bss
, 0 },
5109 { "align", s_align_ptwo
, 2 },
5110 { "arm", s_arm
, 0 },
5111 { "thumb", s_thumb
, 0 },
5112 { "code", s_code
, 0 },
5113 { "force_thumb", s_force_thumb
, 0 },
5114 { "thumb_func", s_thumb_func
, 0 },
5115 { "thumb_set", s_thumb_set
, 0 },
5116 { "even", s_even
, 0 },
5117 { "ltorg", s_ltorg
, 0 },
5118 { "pool", s_ltorg
, 0 },
5119 { "syntax", s_syntax
, 0 },
5120 { "cpu", s_arm_cpu
, 0 },
5121 { "arch", s_arm_arch
, 0 },
5122 { "object_arch", s_arm_object_arch
, 0 },
5123 { "fpu", s_arm_fpu
, 0 },
5124 { "arch_extension", s_arm_arch_extension
, 0 },
5126 { "word", s_arm_elf_cons
, 4 },
5127 { "long", s_arm_elf_cons
, 4 },
5128 { "inst.n", s_arm_elf_inst
, 2 },
5129 { "inst.w", s_arm_elf_inst
, 4 },
5130 { "inst", s_arm_elf_inst
, 0 },
5131 { "rel31", s_arm_rel31
, 0 },
5132 { "fnstart", s_arm_unwind_fnstart
, 0 },
5133 { "fnend", s_arm_unwind_fnend
, 0 },
5134 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5135 { "personality", s_arm_unwind_personality
, 0 },
5136 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5137 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5138 { "save", s_arm_unwind_save
, 0 },
5139 { "vsave", s_arm_unwind_save
, 1 },
5140 { "movsp", s_arm_unwind_movsp
, 0 },
5141 { "pad", s_arm_unwind_pad
, 0 },
5142 { "setfp", s_arm_unwind_setfp
, 0 },
5143 { "unwind_raw", s_arm_unwind_raw
, 0 },
5144 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5145 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5149 /* These are used for dwarf. */
5153 /* These are used for dwarf2. */
5154 { "file", dwarf2_directive_file
, 0 },
5155 { "loc", dwarf2_directive_loc
, 0 },
5156 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5158 { "extend", float_cons
, 'x' },
5159 { "ldouble", float_cons
, 'x' },
5160 { "packed", float_cons
, 'p' },
5161 { "bfloat16", float_cons
, 'b' },
5163 {"secrel32", pe_directive_secrel
, 0},
5166 /* These are for compatibility with CodeComposer Studio. */
5167 {"ref", s_ccs_ref
, 0},
5168 {"def", s_ccs_def
, 0},
5169 {"asmfunc", s_ccs_asmfunc
, 0},
5170 {"endasmfunc", s_ccs_endasmfunc
, 0},
5172 {"float16", float_cons
, 'h' },
5173 {"float16_format", set_fp16_format
, 0 },
5178 /* Parser functions used exclusively in instruction operands. */
5180 /* Generic immediate-value read function for use in insn parsing.
5181 STR points to the beginning of the immediate (the leading #);
5182 VAL receives the value; if the value is outside [MIN, MAX]
5183 issue an error. PREFIX_OPT is true if the immediate prefix is
5187 parse_immediate (char **str
, int *val
, int min
, int max
,
5188 bfd_boolean prefix_opt
)
5192 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5193 if (exp
.X_op
!= O_constant
)
5195 inst
.error
= _("constant expression required");
5199 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5201 inst
.error
= _("immediate value out of range");
5205 *val
= exp
.X_add_number
;
5209 /* Less-generic immediate-value read function with the possibility of loading a
5210 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5211 instructions. Puts the result directly in inst.operands[i]. */
5214 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5215 bfd_boolean allow_symbol_p
)
5218 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5221 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5223 if (exp_p
->X_op
== O_constant
)
5225 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5226 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5227 O_constant. We have to be careful not to break compilation for
5228 32-bit X_add_number, though. */
5229 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5231 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5232 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5234 inst
.operands
[i
].regisimm
= 1;
5237 else if (exp_p
->X_op
== O_big
5238 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5240 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5242 /* Bignums have their least significant bits in
5243 generic_bignum[0]. Make sure we put 32 bits in imm and
5244 32 bits in reg, in a (hopefully) portable way. */
5245 gas_assert (parts
!= 0);
5247 /* Make sure that the number is not too big.
5248 PR 11972: Bignums can now be sign-extended to the
5249 size of a .octa so check that the out of range bits
5250 are all zero or all one. */
5251 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5253 LITTLENUM_TYPE m
= -1;
5255 if (generic_bignum
[parts
* 2] != 0
5256 && generic_bignum
[parts
* 2] != m
)
5259 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5260 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5264 inst
.operands
[i
].imm
= 0;
5265 for (j
= 0; j
< parts
; j
++, idx
++)
5266 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5267 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5268 inst
.operands
[i
].reg
= 0;
5269 for (j
= 0; j
< parts
; j
++, idx
++)
5270 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5271 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5272 inst
.operands
[i
].regisimm
= 1;
5274 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5282 /* Returns the pseudo-register number of an FPA immediate constant,
5283 or FAIL if there isn't a valid constant here. */
5286 parse_fpa_immediate (char ** str
)
5288 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5294 /* First try and match exact strings, this is to guarantee
5295 that some formats will work even for cross assembly. */
5297 for (i
= 0; fp_const
[i
]; i
++)
5299 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5303 *str
+= strlen (fp_const
[i
]);
5304 if (is_end_of_line
[(unsigned char) **str
])
5310 /* Just because we didn't get a match doesn't mean that the constant
5311 isn't valid, just that it is in a format that we don't
5312 automatically recognize. Try parsing it with the standard
5313 expression routines. */
5315 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5317 /* Look for a raw floating point number. */
5318 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5319 && is_end_of_line
[(unsigned char) *save_in
])
5321 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5323 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5325 if (words
[j
] != fp_values
[i
][j
])
5329 if (j
== MAX_LITTLENUMS
)
5337 /* Try and parse a more complex expression, this will probably fail
5338 unless the code uses a floating point prefix (eg "0f"). */
5339 save_in
= input_line_pointer
;
5340 input_line_pointer
= *str
;
5341 if (expression (&exp
) == absolute_section
5342 && exp
.X_op
== O_big
5343 && exp
.X_add_number
< 0)
5345 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5347 #define X_PRECISION 5
5348 #define E_PRECISION 15L
5349 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5351 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5353 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5355 if (words
[j
] != fp_values
[i
][j
])
5359 if (j
== MAX_LITTLENUMS
)
5361 *str
= input_line_pointer
;
5362 input_line_pointer
= save_in
;
5369 *str
= input_line_pointer
;
5370 input_line_pointer
= save_in
;
5371 inst
.error
= _("invalid FPA immediate expression");
5375 /* Returns 1 if a number has "quarter-precision" float format
5376 0baBbbbbbc defgh000 00000000 00000000. */
5379 is_quarter_float (unsigned imm
)
5381 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5382 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5386 /* Detect the presence of a floating point or integer zero constant,
5390 parse_ifimm_zero (char **in
)
5394 if (!is_immediate_prefix (**in
))
5396 /* In unified syntax, all prefixes are optional. */
5397 if (!unified_syntax
)
5403 /* Accept #0x0 as a synonym for #0. */
5404 if (strncmp (*in
, "0x", 2) == 0)
5407 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5412 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5413 &generic_floating_point_number
);
5416 && generic_floating_point_number
.sign
== '+'
5417 && (generic_floating_point_number
.low
5418 > generic_floating_point_number
.leader
))
5424 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5425 0baBbbbbbc defgh000 00000000 00000000.
5426 The zero and minus-zero cases need special handling, since they can't be
5427 encoded in the "quarter-precision" float format, but can nonetheless be
5428 loaded as integer constants. */
5431 parse_qfloat_immediate (char **ccp
, int *immed
)
5435 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5436 int found_fpchar
= 0;
5438 skip_past_char (&str
, '#');
5440 /* We must not accidentally parse an integer as a floating-point number. Make
5441 sure that the value we parse is not an integer by checking for special
5442 characters '.' or 'e'.
5443 FIXME: This is a horrible hack, but doing better is tricky because type
5444 information isn't in a very usable state at parse time. */
5446 skip_whitespace (fpnum
);
5448 if (strncmp (fpnum
, "0x", 2) == 0)
5452 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5453 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5463 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5465 unsigned fpword
= 0;
5468 /* Our FP word must be 32 bits (single-precision FP). */
5469 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5471 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5475 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5488 /* Shift operands. */
5491 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5494 struct asm_shift_name
5497 enum shift_kind kind
;
5500 /* Third argument to parse_shift. */
5501 enum parse_shift_mode
5503 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5504 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5505 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5506 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5507 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5508 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5511 /* Parse a <shift> specifier on an ARM data processing instruction.
5512 This has three forms:
5514 (LSL|LSR|ASL|ASR|ROR) Rs
5515 (LSL|LSR|ASL|ASR|ROR) #imm
5518 Note that ASL is assimilated to LSL in the instruction encoding, and
5519 RRX to ROR #0 (which cannot be written as such). */
5522 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5524 const struct asm_shift_name
*shift_name
;
5525 enum shift_kind shift
;
5530 for (p
= *str
; ISALPHA (*p
); p
++)
5535 inst
.error
= _("shift expression expected");
5539 shift_name
= (const struct asm_shift_name
*) str_hash_find_n (arm_shift_hsh
, *str
,
5542 if (shift_name
== NULL
)
5544 inst
.error
= _("shift expression expected");
5548 shift
= shift_name
->kind
;
5552 case NO_SHIFT_RESTRICT
:
5553 case SHIFT_IMMEDIATE
:
5554 if (shift
== SHIFT_UXTW
)
5556 inst
.error
= _("'UXTW' not allowed here");
5561 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5562 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5564 inst
.error
= _("'LSL' or 'ASR' required");
5569 case SHIFT_LSL_IMMEDIATE
:
5570 if (shift
!= SHIFT_LSL
)
5572 inst
.error
= _("'LSL' required");
5577 case SHIFT_ASR_IMMEDIATE
:
5578 if (shift
!= SHIFT_ASR
)
5580 inst
.error
= _("'ASR' required");
5584 case SHIFT_UXTW_IMMEDIATE
:
5585 if (shift
!= SHIFT_UXTW
)
5587 inst
.error
= _("'UXTW' required");
5595 if (shift
!= SHIFT_RRX
)
5597 /* Whitespace can appear here if the next thing is a bare digit. */
5598 skip_whitespace (p
);
5600 if (mode
== NO_SHIFT_RESTRICT
5601 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5603 inst
.operands
[i
].imm
= reg
;
5604 inst
.operands
[i
].immisreg
= 1;
5606 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5609 inst
.operands
[i
].shift_kind
= shift
;
5610 inst
.operands
[i
].shifted
= 1;
5615 /* Parse a <shifter_operand> for an ARM data processing instruction:
5618 #<immediate>, <rotate>
5622 where <shift> is defined by parse_shift above, and <rotate> is a
5623 multiple of 2 between 0 and 30. Validation of immediate operands
5624 is deferred to md_apply_fix. */
5627 parse_shifter_operand (char **str
, int i
)
5632 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5634 inst
.operands
[i
].reg
= value
;
5635 inst
.operands
[i
].isreg
= 1;
5637 /* parse_shift will override this if appropriate */
5638 inst
.relocs
[0].exp
.X_op
= O_constant
;
5639 inst
.relocs
[0].exp
.X_add_number
= 0;
5641 if (skip_past_comma (str
) == FAIL
)
5644 /* Shift operation on register. */
5645 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5648 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5651 if (skip_past_comma (str
) == SUCCESS
)
5653 /* #x, y -- ie explicit rotation by Y. */
5654 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5657 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5659 inst
.error
= _("constant expression expected");
5663 value
= exp
.X_add_number
;
5664 if (value
< 0 || value
> 30 || value
% 2 != 0)
5666 inst
.error
= _("invalid rotation");
5669 if (inst
.relocs
[0].exp
.X_add_number
< 0
5670 || inst
.relocs
[0].exp
.X_add_number
> 255)
5672 inst
.error
= _("invalid constant");
5676 /* Encode as specified. */
5677 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5681 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5682 inst
.relocs
[0].pc_rel
= 0;
5686 /* Group relocation information. Each entry in the table contains the
5687 textual name of the relocation as may appear in assembler source
5688 and must end with a colon.
5689 Along with this textual name are the relocation codes to be used if
5690 the corresponding instruction is an ALU instruction (ADD or SUB only),
5691 an LDR, an LDRS, or an LDC. */
5693 struct group_reloc_table_entry
5704 /* Varieties of non-ALU group relocation. */
5712 static struct group_reloc_table_entry group_reloc_table
[] =
5713 { /* Program counter relative: */
5715 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5720 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5721 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5722 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5723 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5725 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5730 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5731 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5732 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5733 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5735 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5736 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5737 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5738 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5739 /* Section base relative */
5741 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5746 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5747 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5748 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5749 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5751 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5756 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5757 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5758 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5759 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5761 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5762 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5763 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5764 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5765 /* Absolute thumb alu relocations. */
5767 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5772 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5777 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5782 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5787 /* Given the address of a pointer pointing to the textual name of a group
5788 relocation as may appear in assembler source, attempt to find its details
5789 in group_reloc_table. The pointer will be updated to the character after
5790 the trailing colon. On failure, FAIL will be returned; SUCCESS
5791 otherwise. On success, *entry will be updated to point at the relevant
5792 group_reloc_table entry. */
5795 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5798 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5800 int length
= strlen (group_reloc_table
[i
].name
);
5802 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5803 && (*str
)[length
] == ':')
5805 *out
= &group_reloc_table
[i
];
5806 *str
+= (length
+ 1);
5814 /* Parse a <shifter_operand> for an ARM data processing instruction
5815 (as for parse_shifter_operand) where group relocations are allowed:
5818 #<immediate>, <rotate>
5819 #:<group_reloc>:<expression>
5823 where <group_reloc> is one of the strings defined in group_reloc_table.
5824 The hashes are optional.
5826 Everything else is as for parse_shifter_operand. */
5828 static parse_operand_result
5829 parse_shifter_operand_group_reloc (char **str
, int i
)
5831 /* Determine if we have the sequence of characters #: or just :
5832 coming next. If we do, then we check for a group relocation.
5833 If we don't, punt the whole lot to parse_shifter_operand. */
5835 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5836 || (*str
)[0] == ':')
5838 struct group_reloc_table_entry
*entry
;
5840 if ((*str
)[0] == '#')
5845 /* Try to parse a group relocation. Anything else is an error. */
5846 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5848 inst
.error
= _("unknown group relocation");
5849 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5852 /* We now have the group relocation table entry corresponding to
5853 the name in the assembler source. Next, we parse the expression. */
5854 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5855 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5857 /* Record the relocation type (always the ALU variant here). */
5858 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5859 gas_assert (inst
.relocs
[0].type
!= 0);
5861 return PARSE_OPERAND_SUCCESS
;
5864 return parse_shifter_operand (str
, i
) == SUCCESS
5865 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5867 /* Never reached. */
5870 /* Parse a Neon alignment expression. Information is written to
5871 inst.operands[i]. We assume the initial ':' has been skipped.
5873 align .imm = align << 8, .immisalign=1, .preind=0 */
5874 static parse_operand_result
5875 parse_neon_alignment (char **str
, int i
)
5880 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5882 if (exp
.X_op
!= O_constant
)
5884 inst
.error
= _("alignment must be constant");
5885 return PARSE_OPERAND_FAIL
;
5888 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5889 inst
.operands
[i
].immisalign
= 1;
5890 /* Alignments are not pre-indexes. */
5891 inst
.operands
[i
].preind
= 0;
5894 return PARSE_OPERAND_SUCCESS
;
5897 /* Parse all forms of an ARM address expression. Information is written
5898 to inst.operands[i] and/or inst.relocs[0].
5900 Preindexed addressing (.preind=1):
5902 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5903 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5904 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5905 .shift_kind=shift .relocs[0].exp=shift_imm
5907 These three may have a trailing ! which causes .writeback to be set also.
5909 Postindexed addressing (.postind=1, .writeback=1):
5911 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5912 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5913 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5914 .shift_kind=shift .relocs[0].exp=shift_imm
5916 Unindexed addressing (.preind=0, .postind=0):
5918 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5922 [Rn]{!} shorthand for [Rn,#0]{!}
5923 =immediate .isreg=0 .relocs[0].exp=immediate
5924 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5926 It is the caller's responsibility to check for addressing modes not
5927 supported by the instruction, and to set inst.relocs[0].type. */
5929 static parse_operand_result
5930 parse_address_main (char **str
, int i
, int group_relocations
,
5931 group_reloc_type group_type
)
5936 if (skip_past_char (&p
, '[') == FAIL
)
5938 if (skip_past_char (&p
, '=') == FAIL
)
5940 /* Bare address - translate to PC-relative offset. */
5941 inst
.relocs
[0].pc_rel
= 1;
5942 inst
.operands
[i
].reg
= REG_PC
;
5943 inst
.operands
[i
].isreg
= 1;
5944 inst
.operands
[i
].preind
= 1;
5946 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5947 return PARSE_OPERAND_FAIL
;
5949 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5950 /*allow_symbol_p=*/TRUE
))
5951 return PARSE_OPERAND_FAIL
;
5954 return PARSE_OPERAND_SUCCESS
;
5957 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5958 skip_whitespace (p
);
5960 if (group_type
== GROUP_MVE
)
5962 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5963 struct neon_type_el et
;
5964 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5966 inst
.operands
[i
].isquad
= 1;
5968 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5970 inst
.error
= BAD_ADDR_MODE
;
5971 return PARSE_OPERAND_FAIL
;
5974 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5976 if (group_type
== GROUP_MVE
)
5977 inst
.error
= BAD_ADDR_MODE
;
5979 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5980 return PARSE_OPERAND_FAIL
;
5982 inst
.operands
[i
].reg
= reg
;
5983 inst
.operands
[i
].isreg
= 1;
5985 if (skip_past_comma (&p
) == SUCCESS
)
5987 inst
.operands
[i
].preind
= 1;
5990 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5992 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5993 struct neon_type_el et
;
5994 if (group_type
== GROUP_MVE
5995 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5997 inst
.operands
[i
].immisreg
= 2;
5998 inst
.operands
[i
].imm
= reg
;
6000 if (skip_past_comma (&p
) == SUCCESS
)
6002 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
6004 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
6005 inst
.relocs
[0].exp
.X_add_number
= 0;
6008 return PARSE_OPERAND_FAIL
;
6011 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6013 inst
.operands
[i
].imm
= reg
;
6014 inst
.operands
[i
].immisreg
= 1;
6016 if (skip_past_comma (&p
) == SUCCESS
)
6017 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6018 return PARSE_OPERAND_FAIL
;
6020 else if (skip_past_char (&p
, ':') == SUCCESS
)
6022 /* FIXME: '@' should be used here, but it's filtered out by generic
6023 code before we get to see it here. This may be subject to
6025 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6027 if (result
!= PARSE_OPERAND_SUCCESS
)
6032 if (inst
.operands
[i
].negative
)
6034 inst
.operands
[i
].negative
= 0;
6038 if (group_relocations
6039 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
6041 struct group_reloc_table_entry
*entry
;
6043 /* Skip over the #: or : sequence. */
6049 /* Try to parse a group relocation. Anything else is an
6051 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
6053 inst
.error
= _("unknown group relocation");
6054 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6057 /* We now have the group relocation table entry corresponding to
6058 the name in the assembler source. Next, we parse the
6060 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6061 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6063 /* Record the relocation type. */
6068 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6073 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6078 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6085 if (inst
.relocs
[0].type
== 0)
6087 inst
.error
= _("this group relocation is not allowed on this instruction");
6088 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6095 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6096 return PARSE_OPERAND_FAIL
;
6097 /* If the offset is 0, find out if it's a +0 or -0. */
6098 if (inst
.relocs
[0].exp
.X_op
== O_constant
6099 && inst
.relocs
[0].exp
.X_add_number
== 0)
6101 skip_whitespace (q
);
6105 skip_whitespace (q
);
6108 inst
.operands
[i
].negative
= 1;
6113 else if (skip_past_char (&p
, ':') == SUCCESS
)
6115 /* FIXME: '@' should be used here, but it's filtered out by generic code
6116 before we get to see it here. This may be subject to change. */
6117 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6119 if (result
!= PARSE_OPERAND_SUCCESS
)
6123 if (skip_past_char (&p
, ']') == FAIL
)
6125 inst
.error
= _("']' expected");
6126 return PARSE_OPERAND_FAIL
;
6129 if (skip_past_char (&p
, '!') == SUCCESS
)
6130 inst
.operands
[i
].writeback
= 1;
6132 else if (skip_past_comma (&p
) == SUCCESS
)
6134 if (skip_past_char (&p
, '{') == SUCCESS
)
6136 /* [Rn], {expr} - unindexed, with option */
6137 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6138 0, 255, TRUE
) == FAIL
)
6139 return PARSE_OPERAND_FAIL
;
6141 if (skip_past_char (&p
, '}') == FAIL
)
6143 inst
.error
= _("'}' expected at end of 'option' field");
6144 return PARSE_OPERAND_FAIL
;
6146 if (inst
.operands
[i
].preind
)
6148 inst
.error
= _("cannot combine index with option");
6149 return PARSE_OPERAND_FAIL
;
6152 return PARSE_OPERAND_SUCCESS
;
6156 inst
.operands
[i
].postind
= 1;
6157 inst
.operands
[i
].writeback
= 1;
6159 if (inst
.operands
[i
].preind
)
6161 inst
.error
= _("cannot combine pre- and post-indexing");
6162 return PARSE_OPERAND_FAIL
;
6166 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6168 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6169 struct neon_type_el et
;
6170 if (group_type
== GROUP_MVE
6171 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6173 inst
.operands
[i
].immisreg
= 2;
6174 inst
.operands
[i
].imm
= reg
;
6176 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6178 /* We might be using the immediate for alignment already. If we
6179 are, OR the register number into the low-order bits. */
6180 if (inst
.operands
[i
].immisalign
)
6181 inst
.operands
[i
].imm
|= reg
;
6183 inst
.operands
[i
].imm
= reg
;
6184 inst
.operands
[i
].immisreg
= 1;
6186 if (skip_past_comma (&p
) == SUCCESS
)
6187 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6188 return PARSE_OPERAND_FAIL
;
6194 if (inst
.operands
[i
].negative
)
6196 inst
.operands
[i
].negative
= 0;
6199 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6200 return PARSE_OPERAND_FAIL
;
6201 /* If the offset is 0, find out if it's a +0 or -0. */
6202 if (inst
.relocs
[0].exp
.X_op
== O_constant
6203 && inst
.relocs
[0].exp
.X_add_number
== 0)
6205 skip_whitespace (q
);
6209 skip_whitespace (q
);
6212 inst
.operands
[i
].negative
= 1;
6218 /* If at this point neither .preind nor .postind is set, we have a
6219 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6220 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6222 inst
.operands
[i
].preind
= 1;
6223 inst
.relocs
[0].exp
.X_op
= O_constant
;
6224 inst
.relocs
[0].exp
.X_add_number
= 0;
6227 return PARSE_OPERAND_SUCCESS
;
6231 parse_address (char **str
, int i
)
6233 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6237 static parse_operand_result
6238 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6240 return parse_address_main (str
, i
, 1, type
);
6243 /* Parse an operand for a MOVW or MOVT instruction. */
6245 parse_half (char **str
)
6250 skip_past_char (&p
, '#');
6251 if (strncasecmp (p
, ":lower16:", 9) == 0)
6252 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6253 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6254 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6256 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6259 skip_whitespace (p
);
6262 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6265 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6267 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6269 inst
.error
= _("constant expression expected");
6272 if (inst
.relocs
[0].exp
.X_add_number
< 0
6273 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6275 inst
.error
= _("immediate value out of range");
6283 /* Miscellaneous. */
6285 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6286 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6288 parse_psr (char **str
, bfd_boolean lhs
)
6291 unsigned long psr_field
;
6292 const struct asm_psr
*psr
;
6294 bfd_boolean is_apsr
= FALSE
;
6295 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6297 /* PR gas/12698: If the user has specified -march=all then m_profile will
6298 be TRUE, but we want to ignore it in this case as we are building for any
6299 CPU type, including non-m variants. */
6300 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6303 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6304 feature for ease of use and backwards compatibility. */
6306 if (strncasecmp (p
, "SPSR", 4) == 0)
6309 goto unsupported_psr
;
6311 psr_field
= SPSR_BIT
;
6313 else if (strncasecmp (p
, "CPSR", 4) == 0)
6316 goto unsupported_psr
;
6320 else if (strncasecmp (p
, "APSR", 4) == 0)
6322 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6323 and ARMv7-R architecture CPUs. */
6332 while (ISALNUM (*p
) || *p
== '_');
6334 if (strncasecmp (start
, "iapsr", 5) == 0
6335 || strncasecmp (start
, "eapsr", 5) == 0
6336 || strncasecmp (start
, "xpsr", 4) == 0
6337 || strncasecmp (start
, "psr", 3) == 0)
6338 p
= start
+ strcspn (start
, "rR") + 1;
6340 psr
= (const struct asm_psr
*) str_hash_find_n (arm_v7m_psr_hsh
, start
,
6346 /* If APSR is being written, a bitfield may be specified. Note that
6347 APSR itself is handled above. */
6348 if (psr
->field
<= 3)
6350 psr_field
= psr
->field
;
6356 /* M-profile MSR instructions have the mask field set to "10", except
6357 *PSR variants which modify APSR, which may use a different mask (and
6358 have been handled already). Do that by setting the PSR_f field
6360 return psr
->field
| (lhs
? PSR_f
: 0);
6363 goto unsupported_psr
;
6369 /* A suffix follows. */
6375 while (ISALNUM (*p
) || *p
== '_');
6379 /* APSR uses a notation for bits, rather than fields. */
6380 unsigned int nzcvq_bits
= 0;
6381 unsigned int g_bit
= 0;
6384 for (bit
= start
; bit
!= p
; bit
++)
6386 switch (TOLOWER (*bit
))
6389 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6393 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6397 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6401 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6405 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6409 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6413 inst
.error
= _("unexpected bit specified after APSR");
6418 if (nzcvq_bits
== 0x1f)
6423 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6425 inst
.error
= _("selected processor does not "
6426 "support DSP extension");
6433 if ((nzcvq_bits
& 0x20) != 0
6434 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6435 || (g_bit
& 0x2) != 0)
6437 inst
.error
= _("bad bitmask specified after APSR");
6443 psr
= (const struct asm_psr
*) str_hash_find_n (arm_psr_hsh
, start
,
6448 psr_field
|= psr
->field
;
6454 goto error
; /* Garbage after "[CS]PSR". */
6456 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6457 is deprecated, but allow it anyway. */
6461 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6464 else if (!m_profile
)
6465 /* These bits are never right for M-profile devices: don't set them
6466 (only code paths which read/write APSR reach here). */
6467 psr_field
|= (PSR_c
| PSR_f
);
6473 inst
.error
= _("selected processor does not support requested special "
6474 "purpose register");
6478 inst
.error
= _("flag for {c}psr instruction expected");
6483 parse_sys_vldr_vstr (char **str
)
6492 {"FPSCR", 0x1, 0x0},
6493 {"FPSCR_nzcvqc", 0x2, 0x0},
6496 {"FPCXTNS", 0x6, 0x1},
6497 {"FPCXTS", 0x7, 0x1}
6499 char *op_end
= strchr (*str
, ',');
6500 size_t op_strlen
= op_end
- *str
;
6502 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6504 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6506 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6515 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6516 value suitable for splatting into the AIF field of the instruction. */
6519 parse_cps_flags (char **str
)
6528 case '\0': case ',':
6531 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6532 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6533 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6536 inst
.error
= _("unrecognized CPS flag");
6541 if (saw_a_flag
== 0)
6543 inst
.error
= _("missing CPS flags");
6551 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6552 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6555 parse_endian_specifier (char **str
)
6560 if (strncasecmp (s
, "BE", 2))
6562 else if (strncasecmp (s
, "LE", 2))
6566 inst
.error
= _("valid endian specifiers are be or le");
6570 if (ISALNUM (s
[2]) || s
[2] == '_')
6572 inst
.error
= _("valid endian specifiers are be or le");
6577 return little_endian
;
6580 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6581 value suitable for poking into the rotate field of an sxt or sxta
6582 instruction, or FAIL on error. */
6585 parse_ror (char **str
)
6590 if (strncasecmp (s
, "ROR", 3) == 0)
6594 inst
.error
= _("missing rotation field after comma");
6598 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6603 case 0: *str
= s
; return 0x0;
6604 case 8: *str
= s
; return 0x1;
6605 case 16: *str
= s
; return 0x2;
6606 case 24: *str
= s
; return 0x3;
6609 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6614 /* Parse a conditional code (from conds[] below). The value returned is in the
6615 range 0 .. 14, or FAIL. */
6617 parse_cond (char **str
)
6620 const struct asm_cond
*c
;
6622 /* Condition codes are always 2 characters, so matching up to
6623 3 characters is sufficient. */
6628 while (ISALPHA (*q
) && n
< 3)
6630 cond
[n
] = TOLOWER (*q
);
6635 c
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, cond
, n
);
6638 inst
.error
= _("condition required");
6646 /* Parse an option for a barrier instruction. Returns the encoding for the
6649 parse_barrier (char **str
)
6652 const struct asm_barrier_opt
*o
;
6655 while (ISALPHA (*q
))
6658 o
= (const struct asm_barrier_opt
*) str_hash_find_n (arm_barrier_opt_hsh
, p
,
6663 if (!mark_feature_used (&o
->arch
))
6670 /* Parse the operands of a table branch instruction. Similar to a memory
6673 parse_tb (char **str
)
6678 if (skip_past_char (&p
, '[') == FAIL
)
6680 inst
.error
= _("'[' expected");
6684 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6686 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6689 inst
.operands
[0].reg
= reg
;
6691 if (skip_past_comma (&p
) == FAIL
)
6693 inst
.error
= _("',' expected");
6697 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6699 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6702 inst
.operands
[0].imm
= reg
;
6704 if (skip_past_comma (&p
) == SUCCESS
)
6706 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6708 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6710 inst
.error
= _("invalid shift");
6713 inst
.operands
[0].shifted
= 1;
6716 if (skip_past_char (&p
, ']') == FAIL
)
6718 inst
.error
= _("']' expected");
6725 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6726 information on the types the operands can take and how they are encoded.
6727 Up to four operands may be read; this function handles setting the
6728 ".present" field for each read operand itself.
6729 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6730 else returns FAIL. */
6733 parse_neon_mov (char **str
, int *which_operand
)
6735 int i
= *which_operand
, val
;
6736 enum arm_reg_type rtype
;
6738 struct neon_type_el optype
;
6740 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6742 /* Cases 17 or 19. */
6743 inst
.operands
[i
].reg
= val
;
6744 inst
.operands
[i
].isvec
= 1;
6745 inst
.operands
[i
].isscalar
= 2;
6746 inst
.operands
[i
].vectype
= optype
;
6747 inst
.operands
[i
++].present
= 1;
6749 if (skip_past_comma (&ptr
) == FAIL
)
6752 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6754 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6755 inst
.operands
[i
].reg
= val
;
6756 inst
.operands
[i
].isreg
= 1;
6757 inst
.operands
[i
].present
= 1;
6759 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6761 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6762 inst
.operands
[i
].reg
= val
;
6763 inst
.operands
[i
].isvec
= 1;
6764 inst
.operands
[i
].isscalar
= 2;
6765 inst
.operands
[i
].vectype
= optype
;
6766 inst
.operands
[i
++].present
= 1;
6768 if (skip_past_comma (&ptr
) == FAIL
)
6771 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6774 inst
.operands
[i
].reg
= val
;
6775 inst
.operands
[i
].isreg
= 1;
6776 inst
.operands
[i
++].present
= 1;
6778 if (skip_past_comma (&ptr
) == FAIL
)
6781 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6784 inst
.operands
[i
].reg
= val
;
6785 inst
.operands
[i
].isreg
= 1;
6786 inst
.operands
[i
].present
= 1;
6790 first_error (_("expected ARM or MVE vector register"));
6794 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6796 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6797 inst
.operands
[i
].reg
= val
;
6798 inst
.operands
[i
].isscalar
= 1;
6799 inst
.operands
[i
].vectype
= optype
;
6800 inst
.operands
[i
++].present
= 1;
6802 if (skip_past_comma (&ptr
) == FAIL
)
6805 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6808 inst
.operands
[i
].reg
= val
;
6809 inst
.operands
[i
].isreg
= 1;
6810 inst
.operands
[i
].present
= 1;
6812 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6814 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6817 /* Cases 0, 1, 2, 3, 5 (D only). */
6818 if (skip_past_comma (&ptr
) == FAIL
)
6821 inst
.operands
[i
].reg
= val
;
6822 inst
.operands
[i
].isreg
= 1;
6823 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6824 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6825 inst
.operands
[i
].isvec
= 1;
6826 inst
.operands
[i
].vectype
= optype
;
6827 inst
.operands
[i
++].present
= 1;
6829 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6831 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6832 Case 13: VMOV <Sd>, <Rm> */
6833 inst
.operands
[i
].reg
= val
;
6834 inst
.operands
[i
].isreg
= 1;
6835 inst
.operands
[i
].present
= 1;
6837 if (rtype
== REG_TYPE_NQ
)
6839 first_error (_("can't use Neon quad register here"));
6842 else if (rtype
!= REG_TYPE_VFS
)
6845 if (skip_past_comma (&ptr
) == FAIL
)
6847 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6849 inst
.operands
[i
].reg
= val
;
6850 inst
.operands
[i
].isreg
= 1;
6851 inst
.operands
[i
].present
= 1;
6854 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6856 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6859 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6860 Case 1: VMOV<c><q> <Dd>, <Dm>
6861 Case 8: VMOV.F32 <Sd>, <Sm>
6862 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6864 inst
.operands
[i
].reg
= val
;
6865 inst
.operands
[i
].isreg
= 1;
6866 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6867 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6868 inst
.operands
[i
].isvec
= 1;
6869 inst
.operands
[i
].vectype
= optype
;
6870 inst
.operands
[i
].present
= 1;
6872 if (skip_past_comma (&ptr
) == SUCCESS
)
6877 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6880 inst
.operands
[i
].reg
= val
;
6881 inst
.operands
[i
].isreg
= 1;
6882 inst
.operands
[i
++].present
= 1;
6884 if (skip_past_comma (&ptr
) == FAIL
)
6887 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6890 inst
.operands
[i
].reg
= val
;
6891 inst
.operands
[i
].isreg
= 1;
6892 inst
.operands
[i
].present
= 1;
6895 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6896 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6897 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6898 Case 10: VMOV.F32 <Sd>, #<imm>
6899 Case 11: VMOV.F64 <Dd>, #<imm> */
6900 inst
.operands
[i
].immisfloat
= 1;
6901 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6903 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6904 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6908 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6912 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6914 /* Cases 6, 7, 16, 18. */
6915 inst
.operands
[i
].reg
= val
;
6916 inst
.operands
[i
].isreg
= 1;
6917 inst
.operands
[i
++].present
= 1;
6919 if (skip_past_comma (&ptr
) == FAIL
)
6922 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6924 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6925 inst
.operands
[i
].reg
= val
;
6926 inst
.operands
[i
].isscalar
= 2;
6927 inst
.operands
[i
].present
= 1;
6928 inst
.operands
[i
].vectype
= optype
;
6930 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6932 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6933 inst
.operands
[i
].reg
= val
;
6934 inst
.operands
[i
].isscalar
= 1;
6935 inst
.operands
[i
].present
= 1;
6936 inst
.operands
[i
].vectype
= optype
;
6938 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6940 inst
.operands
[i
].reg
= val
;
6941 inst
.operands
[i
].isreg
= 1;
6942 inst
.operands
[i
++].present
= 1;
6944 if (skip_past_comma (&ptr
) == FAIL
)
6947 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6950 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6952 inst
.operands
[i
].reg
= val
;
6953 inst
.operands
[i
].isreg
= 1;
6954 inst
.operands
[i
].isvec
= 1;
6955 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6956 inst
.operands
[i
].vectype
= optype
;
6957 inst
.operands
[i
].present
= 1;
6959 if (rtype
== REG_TYPE_VFS
)
6963 if (skip_past_comma (&ptr
) == FAIL
)
6965 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6968 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6971 inst
.operands
[i
].reg
= val
;
6972 inst
.operands
[i
].isreg
= 1;
6973 inst
.operands
[i
].isvec
= 1;
6974 inst
.operands
[i
].issingle
= 1;
6975 inst
.operands
[i
].vectype
= optype
;
6976 inst
.operands
[i
].present
= 1;
6981 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6984 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6985 inst
.operands
[i
].reg
= val
;
6986 inst
.operands
[i
].isvec
= 1;
6987 inst
.operands
[i
].isscalar
= 2;
6988 inst
.operands
[i
].vectype
= optype
;
6989 inst
.operands
[i
++].present
= 1;
6991 if (skip_past_comma (&ptr
) == FAIL
)
6994 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6997 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
7000 inst
.operands
[i
].reg
= val
;
7001 inst
.operands
[i
].isvec
= 1;
7002 inst
.operands
[i
].isscalar
= 2;
7003 inst
.operands
[i
].vectype
= optype
;
7004 inst
.operands
[i
].present
= 1;
7008 first_error (_("VFP single, double or MVE vector register"
7014 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
7018 inst
.operands
[i
].reg
= val
;
7019 inst
.operands
[i
].isreg
= 1;
7020 inst
.operands
[i
].isvec
= 1;
7021 inst
.operands
[i
].issingle
= 1;
7022 inst
.operands
[i
].vectype
= optype
;
7023 inst
.operands
[i
].present
= 1;
7028 first_error (_("parse error"));
7032 /* Successfully parsed the operands. Update args. */
7038 first_error (_("expected comma"));
7042 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
7046 /* Use this macro when the operand constraints are different
7047 for ARM and THUMB (e.g. ldrd). */
7048 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7049 ((arm_operand) | ((thumb_operand) << 16))
7051 /* Matcher codes for parse_operands. */
7052 enum operand_parse_code
7054 OP_stop
, /* end of line */
7056 OP_RR
, /* ARM register */
7057 OP_RRnpc
, /* ARM register, not r15 */
7058 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7059 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
7060 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
7061 optional trailing ! */
7062 OP_RRw
, /* ARM register, not r15, optional trailing ! */
7063 OP_RCP
, /* Coprocessor number */
7064 OP_RCN
, /* Coprocessor register */
7065 OP_RF
, /* FPA register */
7066 OP_RVS
, /* VFP single precision register */
7067 OP_RVD
, /* VFP double precision register (0..15) */
7068 OP_RND
, /* Neon double precision register (0..31) */
7069 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
7070 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7072 OP_RNSDMQR
, /* Neon single or double precision, MVE vector or ARM register.
7074 OP_RNQ
, /* Neon quad precision register */
7075 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7076 OP_RVSD
, /* VFP single or double precision register */
7077 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7078 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7079 OP_RNSD
, /* Neon single or double precision register */
7080 OP_RNDQ
, /* Neon double or quad precision register */
7081 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7082 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7083 OP_RNSDQ
, /* Neon single, double or quad precision register */
7084 OP_RNSC
, /* Neon scalar D[X] */
7085 OP_RVC
, /* VFP control register */
7086 OP_RMF
, /* Maverick F register */
7087 OP_RMD
, /* Maverick D register */
7088 OP_RMFX
, /* Maverick FX register */
7089 OP_RMDX
, /* Maverick DX register */
7090 OP_RMAX
, /* Maverick AX register */
7091 OP_RMDS
, /* Maverick DSPSC register */
7092 OP_RIWR
, /* iWMMXt wR register */
7093 OP_RIWC
, /* iWMMXt wC register */
7094 OP_RIWG
, /* iWMMXt wCG register */
7095 OP_RXA
, /* XScale accumulator register */
7097 OP_RNSDMQ
, /* Neon single, double or MVE vector register */
7098 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7100 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7102 OP_RMQ
, /* MVE vector register. */
7103 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7104 OP_RMQRR
, /* MVE vector or ARM register. */
7106 /* New operands for Armv8.1-M Mainline. */
7107 OP_LR
, /* ARM LR register */
7108 OP_RRe
, /* ARM register, only even numbered. */
7109 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7110 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7111 OP_RR_ZR
, /* ARM register or ZR but no PC */
7113 OP_REGLST
, /* ARM register list */
7114 OP_CLRMLST
, /* CLRM register list */
7115 OP_VRSLST
, /* VFP single-precision register list */
7116 OP_VRDLST
, /* VFP double-precision register list */
7117 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7118 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7119 OP_NSTRLST
, /* Neon element/structure list */
7120 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7121 OP_MSTRLST2
, /* MVE vector list with two elements. */
7122 OP_MSTRLST4
, /* MVE vector list with four elements. */
7124 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7125 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7126 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7127 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7129 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7130 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7131 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7132 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7134 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7135 scalar, or ARM register. */
7136 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7137 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7138 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7140 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7141 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7142 OP_VMOV
, /* Neon VMOV operands. */
7143 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7144 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7146 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7147 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7149 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7150 OP_VLDR
, /* VLDR operand. */
7152 OP_I0
, /* immediate zero */
7153 OP_I7
, /* immediate value 0 .. 7 */
7154 OP_I15
, /* 0 .. 15 */
7155 OP_I16
, /* 1 .. 16 */
7156 OP_I16z
, /* 0 .. 16 */
7157 OP_I31
, /* 0 .. 31 */
7158 OP_I31w
, /* 0 .. 31, optional trailing ! */
7159 OP_I32
, /* 1 .. 32 */
7160 OP_I32z
, /* 0 .. 32 */
7161 OP_I48_I64
, /* 48 or 64 */
7162 OP_I63
, /* 0 .. 63 */
7163 OP_I63s
, /* -64 .. 63 */
7164 OP_I64
, /* 1 .. 64 */
7165 OP_I64z
, /* 0 .. 64 */
7166 OP_I127
, /* 0 .. 127 */
7167 OP_I255
, /* 0 .. 255 */
7168 OP_I511
, /* 0 .. 511 */
7169 OP_I4095
, /* 0 .. 4095 */
7170 OP_I8191
, /* 0 .. 8191 */
7171 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7172 OP_I7b
, /* 0 .. 7 */
7173 OP_I15b
, /* 0 .. 15 */
7174 OP_I31b
, /* 0 .. 31 */
7176 OP_SH
, /* shifter operand */
7177 OP_SHG
, /* shifter operand with possible group relocation */
7178 OP_ADDR
, /* Memory address expression (any mode) */
7179 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7180 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7181 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7182 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7183 OP_EXP
, /* arbitrary expression */
7184 OP_EXPi
, /* same, with optional immediate prefix */
7185 OP_EXPr
, /* same, with optional relocation suffix */
7186 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7187 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7188 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7189 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7191 OP_CPSF
, /* CPS flags */
7192 OP_ENDI
, /* Endianness specifier */
7193 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7194 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7195 OP_COND
, /* conditional code */
7196 OP_TB
, /* Table branch. */
7198 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7200 OP_RRnpc_I0
, /* ARM register or literal 0 */
7201 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7202 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7203 OP_RF_IF
, /* FPA register or immediate */
7204 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7205 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7207 /* Optional operands. */
7208 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7209 OP_oI31b
, /* 0 .. 31 */
7210 OP_oI32b
, /* 1 .. 32 */
7211 OP_oI32z
, /* 0 .. 32 */
7212 OP_oIffffb
, /* 0 .. 65535 */
7213 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7215 OP_oRR
, /* ARM register */
7216 OP_oLR
, /* ARM LR register */
7217 OP_oRRnpc
, /* ARM register, not the PC */
7218 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7219 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7220 OP_oRND
, /* Optional Neon double precision register */
7221 OP_oRNQ
, /* Optional Neon quad precision register */
7222 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7223 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7224 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7225 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7227 OP_oRNSDMQ
, /* Optional single, double register or MVE vector
7229 OP_oSHll
, /* LSL immediate */
7230 OP_oSHar
, /* ASR immediate */
7231 OP_oSHllar
, /* LSL or ASR immediate */
7232 OP_oROR
, /* ROR 0/8/16/24 */
7233 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7235 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7237 /* Some pre-defined mixed (ARM/THUMB) operands. */
7238 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7239 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7240 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7242 OP_FIRST_OPTIONAL
= OP_oI7b
7245 /* Generic instruction operand parser. This does no encoding and no
7246 semantic validation; it merely squirrels values away in the inst
7247 structure. Returns SUCCESS or FAIL depending on whether the
7248 specified grammar matched. */
7250 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7252 unsigned const int *upat
= pattern
;
7253 char *backtrack_pos
= 0;
7254 const char *backtrack_error
= 0;
7255 int i
, val
= 0, backtrack_index
= 0;
7256 enum arm_reg_type rtype
;
7257 parse_operand_result result
;
7258 unsigned int op_parse_code
;
7259 bfd_boolean partial_match
;
7261 #define po_char_or_fail(chr) \
7264 if (skip_past_char (&str, chr) == FAIL) \
7269 #define po_reg_or_fail(regtype) \
7272 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7273 & inst.operands[i].vectype); \
7276 first_error (_(reg_expected_msgs[regtype])); \
7279 inst.operands[i].reg = val; \
7280 inst.operands[i].isreg = 1; \
7281 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7282 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7283 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7284 || rtype == REG_TYPE_VFD \
7285 || rtype == REG_TYPE_NQ); \
7286 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7290 #define po_reg_or_goto(regtype, label) \
7293 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7294 & inst.operands[i].vectype); \
7298 inst.operands[i].reg = val; \
7299 inst.operands[i].isreg = 1; \
7300 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7301 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7302 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7303 || rtype == REG_TYPE_VFD \
7304 || rtype == REG_TYPE_NQ); \
7305 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7309 #define po_imm_or_fail(min, max, popt) \
7312 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7314 inst.operands[i].imm = val; \
7318 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7322 my_get_expression (&exp, &str, popt); \
7323 if (exp.X_op != O_constant) \
7325 inst.error = _("constant expression required"); \
7328 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7330 inst.error = _("immediate value 48 or 64 expected"); \
7333 inst.operands[i].imm = exp.X_add_number; \
7337 #define po_scalar_or_goto(elsz, label, reg_type) \
7340 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7344 inst.operands[i].reg = val; \
7345 inst.operands[i].isscalar = 1; \
7349 #define po_misc_or_fail(expr) \
7357 #define po_misc_or_fail_no_backtrack(expr) \
7361 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7362 backtrack_pos = 0; \
7363 if (result != PARSE_OPERAND_SUCCESS) \
7368 #define po_barrier_or_imm(str) \
7371 val = parse_barrier (&str); \
7372 if (val == FAIL && ! ISALPHA (*str)) \
7375 /* ISB can only take SY as an option. */ \
7376 || ((inst.instruction & 0xf0) == 0x60 \
7379 inst.error = _("invalid barrier type"); \
7380 backtrack_pos = 0; \
7386 skip_whitespace (str
);
7388 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7390 op_parse_code
= upat
[i
];
7391 if (op_parse_code
>= 1<<16)
7392 op_parse_code
= thumb
? (op_parse_code
>> 16)
7393 : (op_parse_code
& ((1<<16)-1));
7395 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7397 /* Remember where we are in case we need to backtrack. */
7398 backtrack_pos
= str
;
7399 backtrack_error
= inst
.error
;
7400 backtrack_index
= i
;
7403 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7404 po_char_or_fail (',');
7406 switch (op_parse_code
)
7418 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7419 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7420 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7421 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7422 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7423 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7426 po_reg_or_goto (REG_TYPE_VFS
, try_rndmqr
);
7430 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7434 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7437 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7439 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7441 /* Also accept generic coprocessor regs for unknown registers. */
7443 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7445 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7446 existing register with a value of 0, this seems like the
7447 best way to parse P0. */
7449 if (strncasecmp (str
, "P0", 2) == 0)
7452 inst
.operands
[i
].isreg
= 1;
7453 inst
.operands
[i
].reg
= 13;
7458 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7459 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7460 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7461 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7462 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7463 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7464 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7465 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7466 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7467 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7470 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7473 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7474 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7476 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7481 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7485 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7487 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7490 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7492 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7496 po_reg_or_goto (REG_TYPE_NSD
, try_mq2
);
7499 po_reg_or_fail (REG_TYPE_MQ
);
7502 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7504 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7509 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7512 po_reg_or_fail (REG_TYPE_NSDQ
);
7516 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7520 po_reg_or_fail (REG_TYPE_MQ
);
7522 /* Neon scalar. Using an element size of 8 means that some invalid
7523 scalars are accepted here, so deal with those in later code. */
7524 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7528 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7531 po_imm_or_fail (0, 0, TRUE
);
7536 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7540 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7545 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7548 if (parse_ifimm_zero (&str
))
7549 inst
.operands
[i
].imm
= 0;
7553 = _("only floating point zero is allowed as immediate value");
7561 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7564 po_reg_or_fail (REG_TYPE_RN
);
7568 case OP_RNSDQ_RNSC_MQ_RR
:
7569 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7572 case OP_RNSDQ_RNSC_MQ
:
7573 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7578 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7582 po_reg_or_fail (REG_TYPE_NSDQ
);
7589 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7592 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7595 po_reg_or_fail (REG_TYPE_NSD
);
7599 case OP_RNDQMQ_RNSC_RR
:
7600 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7603 case OP_RNDQ_RNSC_RR
:
7604 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7606 case OP_RNDQMQ_RNSC
:
7607 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7612 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7615 po_reg_or_fail (REG_TYPE_NDQ
);
7621 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7624 po_reg_or_fail (REG_TYPE_VFD
);
7629 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7630 not careful then bad things might happen. */
7631 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7634 case OP_RNDQMQ_Ibig
:
7635 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7640 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7643 /* There's a possibility of getting a 64-bit immediate here, so
7644 we need special handling. */
7645 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7648 inst
.error
= _("immediate value is out of range");
7654 case OP_RNDQMQ_I63b_RR
:
7655 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7658 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7663 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7666 po_imm_or_fail (0, 63, TRUE
);
7671 po_char_or_fail ('[');
7672 po_reg_or_fail (REG_TYPE_RN
);
7673 po_char_or_fail (']');
7679 po_reg_or_fail (REG_TYPE_RN
);
7680 if (skip_past_char (&str
, '!') == SUCCESS
)
7681 inst
.operands
[i
].writeback
= 1;
7685 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7686 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7687 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7688 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7689 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7690 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7691 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7692 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7693 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7694 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7695 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7696 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7697 case OP_I127
: po_imm_or_fail ( 0, 127, FALSE
); break;
7698 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7699 case OP_I511
: po_imm_or_fail ( 0, 511, FALSE
); break;
7700 case OP_I4095
: po_imm_or_fail ( 0, 4095, FALSE
); break;
7701 case OP_I8191
: po_imm_or_fail ( 0, 8191, FALSE
); break;
7702 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7704 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7705 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7707 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7708 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7709 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7710 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7712 /* Immediate variants */
7714 po_char_or_fail ('{');
7715 po_imm_or_fail (0, 255, TRUE
);
7716 po_char_or_fail ('}');
7720 /* The expression parser chokes on a trailing !, so we have
7721 to find it first and zap it. */
7724 while (*s
&& *s
!= ',')
7729 inst
.operands
[i
].writeback
= 1;
7731 po_imm_or_fail (0, 31, TRUE
);
7739 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7744 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7749 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7751 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7753 val
= parse_reloc (&str
);
7756 inst
.error
= _("unrecognized relocation suffix");
7759 else if (val
!= BFD_RELOC_UNUSED
)
7761 inst
.operands
[i
].imm
= val
;
7762 inst
.operands
[i
].hasreloc
= 1;
7768 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7770 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7772 inst
.operands
[i
].hasreloc
= 1;
7774 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7776 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7777 inst
.operands
[i
].hasreloc
= 0;
7781 /* Operand for MOVW or MOVT. */
7783 po_misc_or_fail (parse_half (&str
));
7786 /* Register or expression. */
7787 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7788 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7790 /* Register or immediate. */
7791 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7792 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7794 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7795 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7797 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7799 if (!is_immediate_prefix (*str
))
7802 val
= parse_fpa_immediate (&str
);
7805 /* FPA immediates are encoded as registers 8-15.
7806 parse_fpa_immediate has already applied the offset. */
7807 inst
.operands
[i
].reg
= val
;
7808 inst
.operands
[i
].isreg
= 1;
7811 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7812 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7814 /* Two kinds of register. */
7817 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7819 || (rege
->type
!= REG_TYPE_MMXWR
7820 && rege
->type
!= REG_TYPE_MMXWC
7821 && rege
->type
!= REG_TYPE_MMXWCG
))
7823 inst
.error
= _("iWMMXt data or control register expected");
7826 inst
.operands
[i
].reg
= rege
->number
;
7827 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7833 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7835 || (rege
->type
!= REG_TYPE_MMXWC
7836 && rege
->type
!= REG_TYPE_MMXWCG
))
7838 inst
.error
= _("iWMMXt control register expected");
7841 inst
.operands
[i
].reg
= rege
->number
;
7842 inst
.operands
[i
].isreg
= 1;
7847 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7848 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7849 case OP_oROR
: val
= parse_ror (&str
); break;
7851 case OP_COND
: val
= parse_cond (&str
); break;
7852 case OP_oBARRIER_I15
:
7853 po_barrier_or_imm (str
); break;
7855 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7861 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7862 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7864 inst
.error
= _("Banked registers are not available with this "
7870 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7874 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7877 val
= parse_sys_vldr_vstr (&str
);
7881 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7884 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7886 if (strncasecmp (str
, "APSR_", 5) == 0)
7893 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7894 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7895 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7896 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7897 default: found
= 16;
7901 inst
.operands
[i
].isvec
= 1;
7902 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7903 inst
.operands
[i
].reg
= REG_PC
;
7910 po_misc_or_fail (parse_tb (&str
));
7913 /* Register lists. */
7915 val
= parse_reg_list (&str
, REGLIST_RN
);
7918 inst
.operands
[i
].writeback
= 1;
7924 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7928 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7933 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7938 /* Allow Q registers too. */
7939 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7940 REGLIST_NEON_D
, &partial_match
);
7944 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7945 REGLIST_VFP_S
, &partial_match
);
7946 inst
.operands
[i
].issingle
= 1;
7951 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7952 REGLIST_VFP_D_VPR
, &partial_match
);
7953 if (val
== FAIL
&& !partial_match
)
7956 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7957 REGLIST_VFP_S_VPR
, &partial_match
);
7958 inst
.operands
[i
].issingle
= 1;
7963 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7964 REGLIST_NEON_D
, &partial_match
);
7969 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7970 1, &inst
.operands
[i
].vectype
);
7971 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7975 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7976 0, &inst
.operands
[i
].vectype
);
7979 /* Addressing modes */
7981 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7985 po_misc_or_fail (parse_address (&str
, i
));
7989 po_misc_or_fail_no_backtrack (
7990 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7994 po_misc_or_fail_no_backtrack (
7995 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7999 po_misc_or_fail_no_backtrack (
8000 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
8004 po_misc_or_fail (parse_shifter_operand (&str
, i
));
8008 po_misc_or_fail_no_backtrack (
8009 parse_shifter_operand_group_reloc (&str
, i
));
8013 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
8017 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
8021 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
8026 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
8031 po_reg_or_goto (REG_TYPE_RN
, ZR
);
8034 po_reg_or_fail (REG_TYPE_ZR
);
8038 as_fatal (_("unhandled operand code %d"), op_parse_code
);
8041 /* Various value-based sanity checks and shared operations. We
8042 do not signal immediate failures for the register constraints;
8043 this allows a syntax error to take precedence. */
8044 switch (op_parse_code
)
8052 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
8053 inst
.error
= BAD_PC
;
8058 case OP_RRnpcsp_I32
:
8059 if (inst
.operands
[i
].isreg
)
8061 if (inst
.operands
[i
].reg
== REG_PC
)
8062 inst
.error
= BAD_PC
;
8063 else if (inst
.operands
[i
].reg
== REG_SP
8064 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8065 relaxed since ARMv8-A. */
8066 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8069 inst
.error
= BAD_SP
;
8075 if (inst
.operands
[i
].isreg
8076 && inst
.operands
[i
].reg
== REG_PC
8077 && (inst
.operands
[i
].writeback
|| thumb
))
8078 inst
.error
= BAD_PC
;
8083 if (inst
.operands
[i
].isreg
)
8093 case OP_oBARRIER_I15
:
8106 inst
.operands
[i
].imm
= val
;
8111 if (inst
.operands
[i
].reg
!= REG_LR
)
8112 inst
.error
= _("operand must be LR register");
8118 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8119 inst
.error
= BAD_PC
;
8123 if (inst
.operands
[i
].isreg
8124 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8125 inst
.error
= BAD_ODD
;
8129 if (inst
.operands
[i
].isreg
)
8131 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8132 inst
.error
= BAD_EVEN
;
8133 else if (inst
.operands
[i
].reg
== REG_SP
)
8134 as_tsktsk (MVE_BAD_SP
);
8135 else if (inst
.operands
[i
].reg
== REG_PC
)
8136 inst
.error
= BAD_PC
;
8144 /* If we get here, this operand was successfully parsed. */
8145 inst
.operands
[i
].present
= 1;
8149 inst
.error
= BAD_ARGS
;
8154 /* The parse routine should already have set inst.error, but set a
8155 default here just in case. */
8157 inst
.error
= BAD_SYNTAX
;
8161 /* Do not backtrack over a trailing optional argument that
8162 absorbed some text. We will only fail again, with the
8163 'garbage following instruction' error message, which is
8164 probably less helpful than the current one. */
8165 if (backtrack_index
== i
&& backtrack_pos
!= str
8166 && upat
[i
+1] == OP_stop
)
8169 inst
.error
= BAD_SYNTAX
;
8173 /* Try again, skipping the optional argument at backtrack_pos. */
8174 str
= backtrack_pos
;
8175 inst
.error
= backtrack_error
;
8176 inst
.operands
[backtrack_index
].present
= 0;
8177 i
= backtrack_index
;
8181 /* Check that we have parsed all the arguments. */
8182 if (*str
!= '\0' && !inst
.error
)
8183 inst
.error
= _("garbage following instruction");
8185 return inst
.error
? FAIL
: SUCCESS
;
8188 #undef po_char_or_fail
8189 #undef po_reg_or_fail
8190 #undef po_reg_or_goto
8191 #undef po_imm_or_fail
8192 #undef po_scalar_or_fail
8193 #undef po_barrier_or_imm
8195 /* Shorthand macro for instruction encoding functions issuing errors. */
8196 #define constraint(expr, err) \
8207 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8208 instructions are unpredictable if these registers are used. This
8209 is the BadReg predicate in ARM's Thumb-2 documentation.
8211 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8212 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8213 #define reject_bad_reg(reg) \
8215 if (reg == REG_PC) \
8217 inst.error = BAD_PC; \
8220 else if (reg == REG_SP \
8221 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8223 inst.error = BAD_SP; \
8228 /* If REG is R13 (the stack pointer), warn that its use is
8230 #define warn_deprecated_sp(reg) \
8232 if (warn_on_deprecated && reg == REG_SP) \
8233 as_tsktsk (_("use of r13 is deprecated")); \
8236 /* Functions for operand encoding. ARM, then Thumb. */
8238 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8240 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8242 The only binary encoding difference is the Coprocessor number. Coprocessor
8243 9 is used for half-precision calculations or conversions. The format of the
8244 instruction is the same as the equivalent Coprocessor 10 instruction that
8245 exists for Single-Precision operation. */
8248 do_scalar_fp16_v82_encode (void)
8250 if (inst
.cond
< COND_ALWAYS
)
8251 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8252 " the behaviour is UNPREDICTABLE"));
8253 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8256 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8257 mark_feature_used (&arm_ext_fp16
);
8260 /* If VAL can be encoded in the immediate field of an ARM instruction,
8261 return the encoded form. Otherwise, return FAIL. */
8264 encode_arm_immediate (unsigned int val
)
8271 for (i
= 2; i
< 32; i
+= 2)
8272 if ((a
= rotate_left (val
, i
)) <= 0xff)
8273 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8278 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8279 return the encoded form. Otherwise, return FAIL. */
8281 encode_thumb32_immediate (unsigned int val
)
8288 for (i
= 1; i
<= 24; i
++)
8291 if ((val
& ~(0xff << i
)) == 0)
8292 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8296 if (val
== ((a
<< 16) | a
))
8298 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8302 if (val
== ((a
<< 16) | a
))
8303 return 0x200 | (a
>> 8);
8307 /* Encode a VFP SP or DP register number into inst.instruction. */
8310 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8312 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8315 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8318 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8321 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8326 first_error (_("D register out of range for selected VFP version"));
8334 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8338 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8342 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8346 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8350 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8354 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8362 /* Encode a <shift> in an ARM-format instruction. The immediate,
8363 if any, is handled by md_apply_fix. */
8365 encode_arm_shift (int i
)
8367 /* register-shifted register. */
8368 if (inst
.operands
[i
].immisreg
)
8371 for (op_index
= 0; op_index
<= i
; ++op_index
)
8373 /* Check the operand only when it's presented. In pre-UAL syntax,
8374 if the destination register is the same as the first operand, two
8375 register form of the instruction can be used. */
8376 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8377 && inst
.operands
[op_index
].reg
== REG_PC
)
8378 as_warn (UNPRED_REG ("r15"));
8381 if (inst
.operands
[i
].imm
== REG_PC
)
8382 as_warn (UNPRED_REG ("r15"));
8385 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8386 inst
.instruction
|= SHIFT_ROR
<< 5;
8389 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8390 if (inst
.operands
[i
].immisreg
)
8392 inst
.instruction
|= SHIFT_BY_REG
;
8393 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8396 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8401 encode_arm_shifter_operand (int i
)
8403 if (inst
.operands
[i
].isreg
)
8405 inst
.instruction
|= inst
.operands
[i
].reg
;
8406 encode_arm_shift (i
);
8410 inst
.instruction
|= INST_IMMEDIATE
;
8411 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8412 inst
.instruction
|= inst
.operands
[i
].imm
;
8416 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8418 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8421 Generate an error if the operand is not a register. */
8422 constraint (!inst
.operands
[i
].isreg
,
8423 _("Instruction does not support =N addresses"));
8425 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8427 if (inst
.operands
[i
].preind
)
8431 inst
.error
= _("instruction does not accept preindexed addressing");
8434 inst
.instruction
|= PRE_INDEX
;
8435 if (inst
.operands
[i
].writeback
)
8436 inst
.instruction
|= WRITE_BACK
;
8439 else if (inst
.operands
[i
].postind
)
8441 gas_assert (inst
.operands
[i
].writeback
);
8443 inst
.instruction
|= WRITE_BACK
;
8445 else /* unindexed - only for coprocessor */
8447 inst
.error
= _("instruction does not accept unindexed addressing");
8451 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8452 && (((inst
.instruction
& 0x000f0000) >> 16)
8453 == ((inst
.instruction
& 0x0000f000) >> 12)))
8454 as_warn ((inst
.instruction
& LOAD_BIT
)
8455 ? _("destination register same as write-back base")
8456 : _("source register same as write-back base"));
8459 /* inst.operands[i] was set up by parse_address. Encode it into an
8460 ARM-format mode 2 load or store instruction. If is_t is true,
8461 reject forms that cannot be used with a T instruction (i.e. not
8464 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8466 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8468 encode_arm_addr_mode_common (i
, is_t
);
8470 if (inst
.operands
[i
].immisreg
)
8472 constraint ((inst
.operands
[i
].imm
== REG_PC
8473 || (is_pc
&& inst
.operands
[i
].writeback
)),
8475 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8476 inst
.instruction
|= inst
.operands
[i
].imm
;
8477 if (!inst
.operands
[i
].negative
)
8478 inst
.instruction
|= INDEX_UP
;
8479 if (inst
.operands
[i
].shifted
)
8481 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8482 inst
.instruction
|= SHIFT_ROR
<< 5;
8485 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8486 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8490 else /* immediate offset in inst.relocs[0] */
8492 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8494 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8496 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8497 cannot use PC in addressing.
8498 PC cannot be used in writeback addressing, either. */
8499 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8502 /* Use of PC in str is deprecated for ARMv7. */
8503 if (warn_on_deprecated
8505 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8506 as_tsktsk (_("use of PC in this instruction is deprecated"));
8509 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8511 /* Prefer + for zero encoded value. */
8512 if (!inst
.operands
[i
].negative
)
8513 inst
.instruction
|= INDEX_UP
;
8514 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8519 /* inst.operands[i] was set up by parse_address. Encode it into an
8520 ARM-format mode 3 load or store instruction. Reject forms that
8521 cannot be used with such instructions. If is_t is true, reject
8522 forms that cannot be used with a T instruction (i.e. not
8525 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8527 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8529 inst
.error
= _("instruction does not accept scaled register index");
8533 encode_arm_addr_mode_common (i
, is_t
);
8535 if (inst
.operands
[i
].immisreg
)
8537 constraint ((inst
.operands
[i
].imm
== REG_PC
8538 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8540 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8542 inst
.instruction
|= inst
.operands
[i
].imm
;
8543 if (!inst
.operands
[i
].negative
)
8544 inst
.instruction
|= INDEX_UP
;
8546 else /* immediate offset in inst.relocs[0] */
8548 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8549 && inst
.operands
[i
].writeback
),
8551 inst
.instruction
|= HWOFFSET_IMM
;
8552 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8554 /* Prefer + for zero encoded value. */
8555 if (!inst
.operands
[i
].negative
)
8556 inst
.instruction
|= INDEX_UP
;
8558 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8563 /* Write immediate bits [7:0] to the following locations:
8565 |28/24|23 19|18 16|15 4|3 0|
8566 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8568 This function is used by VMOV/VMVN/VORR/VBIC. */
8571 neon_write_immbits (unsigned immbits
)
8573 inst
.instruction
|= immbits
& 0xf;
8574 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8575 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8578 /* Invert low-order SIZE bits of XHI:XLO. */
8581 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8583 unsigned immlo
= xlo
? *xlo
: 0;
8584 unsigned immhi
= xhi
? *xhi
: 0;
8589 immlo
= (~immlo
) & 0xff;
8593 immlo
= (~immlo
) & 0xffff;
8597 immhi
= (~immhi
) & 0xffffffff;
8601 immlo
= (~immlo
) & 0xffffffff;
8615 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8619 neon_bits_same_in_bytes (unsigned imm
)
8621 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8622 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8623 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8624 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8627 /* For immediate of above form, return 0bABCD. */
8630 neon_squash_bits (unsigned imm
)
8632 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8633 | ((imm
& 0x01000000) >> 21);
8636 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8639 neon_qfloat_bits (unsigned imm
)
8641 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8644 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8645 the instruction. *OP is passed as the initial value of the op field, and
8646 may be set to a different value depending on the constant (i.e.
8647 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8648 MVN). If the immediate looks like a repeated pattern then also
8649 try smaller element sizes. */
8652 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8653 unsigned *immbits
, int *op
, int size
,
8654 enum neon_el_type type
)
8656 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8658 if (type
== NT_float
&& !float_p
)
8661 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8663 if (size
!= 32 || *op
== 1)
8665 *immbits
= neon_qfloat_bits (immlo
);
8671 if (neon_bits_same_in_bytes (immhi
)
8672 && neon_bits_same_in_bytes (immlo
))
8676 *immbits
= (neon_squash_bits (immhi
) << 4)
8677 | neon_squash_bits (immlo
);
8688 if (immlo
== (immlo
& 0x000000ff))
8693 else if (immlo
== (immlo
& 0x0000ff00))
8695 *immbits
= immlo
>> 8;
8698 else if (immlo
== (immlo
& 0x00ff0000))
8700 *immbits
= immlo
>> 16;
8703 else if (immlo
== (immlo
& 0xff000000))
8705 *immbits
= immlo
>> 24;
8708 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8710 *immbits
= (immlo
>> 8) & 0xff;
8713 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8715 *immbits
= (immlo
>> 16) & 0xff;
8719 if ((immlo
& 0xffff) != (immlo
>> 16))
8726 if (immlo
== (immlo
& 0x000000ff))
8731 else if (immlo
== (immlo
& 0x0000ff00))
8733 *immbits
= immlo
>> 8;
8737 if ((immlo
& 0xff) != (immlo
>> 8))
8742 if (immlo
== (immlo
& 0x000000ff))
8744 /* Don't allow MVN with 8-bit immediate. */
8754 #if defined BFD_HOST_64_BIT
8755 /* Returns TRUE if double precision value V may be cast
8756 to single precision without loss of accuracy. */
8759 is_double_a_single (bfd_int64_t v
)
8761 int exp
= (int)((v
>> 52) & 0x7FF);
8762 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8764 return (exp
== 0 || exp
== 0x7FF
8765 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8766 && (mantissa
& 0x1FFFFFFFl
) == 0;
8769 /* Returns a double precision value casted to single precision
8770 (ignoring the least significant bits in exponent and mantissa). */
8773 double_to_single (bfd_int64_t v
)
8775 int sign
= (int) ((v
>> 63) & 1l);
8776 int exp
= (int) ((v
>> 52) & 0x7FF);
8777 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8783 exp
= exp
- 1023 + 127;
8792 /* No denormalized numbers. */
8798 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8800 #endif /* BFD_HOST_64_BIT */
8809 static void do_vfp_nsyn_opcode (const char *);
8811 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8812 Determine whether it can be performed with a move instruction; if
8813 it can, convert inst.instruction to that move instruction and
8814 return TRUE; if it can't, convert inst.instruction to a literal-pool
8815 load and return FALSE. If this is not a valid thing to do in the
8816 current context, set inst.error and return TRUE.
8818 inst.operands[i] describes the destination register. */
8821 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8824 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8825 bfd_boolean arm_p
= (t
== CONST_ARM
);
8828 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8832 if ((inst
.instruction
& tbit
) == 0)
8834 inst
.error
= _("invalid pseudo operation");
8838 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8839 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8840 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8842 inst
.error
= _("constant expression expected");
8846 if (inst
.relocs
[0].exp
.X_op
== O_constant
8847 || inst
.relocs
[0].exp
.X_op
== O_big
)
8849 #if defined BFD_HOST_64_BIT
8854 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8856 LITTLENUM_TYPE w
[X_PRECISION
];
8859 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8861 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8863 /* FIXME: Should we check words w[2..5] ? */
8868 #if defined BFD_HOST_64_BIT
8870 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8871 << LITTLENUM_NUMBER_OF_BITS
)
8872 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8873 << LITTLENUM_NUMBER_OF_BITS
)
8874 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8875 << LITTLENUM_NUMBER_OF_BITS
)
8876 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8878 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8879 | (l
[0] & LITTLENUM_MASK
);
8883 v
= inst
.relocs
[0].exp
.X_add_number
;
8885 if (!inst
.operands
[i
].issingle
)
8889 /* LDR should not use lead in a flag-setting instruction being
8890 chosen so we do not check whether movs can be used. */
8892 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8893 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8894 && inst
.operands
[i
].reg
!= 13
8895 && inst
.operands
[i
].reg
!= 15)
8897 /* Check if on thumb2 it can be done with a mov.w, mvn or
8898 movw instruction. */
8899 unsigned int newimm
;
8900 bfd_boolean isNegated
;
8902 newimm
= encode_thumb32_immediate (v
);
8903 if (newimm
!= (unsigned int) FAIL
)
8907 newimm
= encode_thumb32_immediate (~v
);
8908 if (newimm
!= (unsigned int) FAIL
)
8912 /* The number can be loaded with a mov.w or mvn
8914 if (newimm
!= (unsigned int) FAIL
8915 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8917 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8918 | (inst
.operands
[i
].reg
<< 8));
8919 /* Change to MOVN. */
8920 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8921 inst
.instruction
|= (newimm
& 0x800) << 15;
8922 inst
.instruction
|= (newimm
& 0x700) << 4;
8923 inst
.instruction
|= (newimm
& 0x0ff);
8926 /* The number can be loaded with a movw instruction. */
8927 else if ((v
& ~0xFFFF) == 0
8928 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8930 int imm
= v
& 0xFFFF;
8932 inst
.instruction
= 0xf2400000; /* MOVW. */
8933 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8934 inst
.instruction
|= (imm
& 0xf000) << 4;
8935 inst
.instruction
|= (imm
& 0x0800) << 15;
8936 inst
.instruction
|= (imm
& 0x0700) << 4;
8937 inst
.instruction
|= (imm
& 0x00ff);
8938 /* In case this replacement is being done on Armv8-M
8939 Baseline we need to make sure to disable the
8940 instruction size check, as otherwise GAS will reject
8941 the use of this T32 instruction. */
8949 int value
= encode_arm_immediate (v
);
8953 /* This can be done with a mov instruction. */
8954 inst
.instruction
&= LITERAL_MASK
;
8955 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8956 inst
.instruction
|= value
& 0xfff;
8960 value
= encode_arm_immediate (~ v
);
8963 /* This can be done with a mvn instruction. */
8964 inst
.instruction
&= LITERAL_MASK
;
8965 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8966 inst
.instruction
|= value
& 0xfff;
8970 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8973 unsigned immbits
= 0;
8974 unsigned immlo
= inst
.operands
[1].imm
;
8975 unsigned immhi
= inst
.operands
[1].regisimm
8976 ? inst
.operands
[1].reg
8977 : inst
.relocs
[0].exp
.X_unsigned
8979 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8980 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8981 &op
, 64, NT_invtype
);
8985 neon_invert_size (&immlo
, &immhi
, 64);
8987 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8988 &op
, 64, NT_invtype
);
8993 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8999 /* Fill other bits in vmov encoding for both thumb and arm. */
9001 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
9003 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
9004 neon_write_immbits (immbits
);
9012 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
9013 if (inst
.operands
[i
].issingle
9014 && is_quarter_float (inst
.operands
[1].imm
)
9015 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
9017 inst
.operands
[1].imm
=
9018 neon_qfloat_bits (v
);
9019 do_vfp_nsyn_opcode ("fconsts");
9023 /* If our host does not support a 64-bit type then we cannot perform
9024 the following optimization. This mean that there will be a
9025 discrepancy between the output produced by an assembler built for
9026 a 32-bit-only host and the output produced from a 64-bit host, but
9027 this cannot be helped. */
9028 #if defined BFD_HOST_64_BIT
9029 else if (!inst
.operands
[1].issingle
9030 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
9032 if (is_double_a_single (v
)
9033 && is_quarter_float (double_to_single (v
)))
9035 inst
.operands
[1].imm
=
9036 neon_qfloat_bits (double_to_single (v
));
9037 do_vfp_nsyn_opcode ("fconstd");
9045 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
9046 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
9049 inst
.operands
[1].reg
= REG_PC
;
9050 inst
.operands
[1].isreg
= 1;
9051 inst
.operands
[1].preind
= 1;
9052 inst
.relocs
[0].pc_rel
= 1;
9053 inst
.relocs
[0].type
= (thumb_p
9054 ? BFD_RELOC_ARM_THUMB_OFFSET
9056 ? BFD_RELOC_ARM_HWLITERAL
9057 : BFD_RELOC_ARM_LITERAL
));
9061 /* inst.operands[i] was set up by parse_address. Encode it into an
9062 ARM-format instruction. Reject all forms which cannot be encoded
9063 into a coprocessor load/store instruction. If wb_ok is false,
9064 reject use of writeback; if unind_ok is false, reject use of
9065 unindexed addressing. If reloc_override is not 0, use it instead
9066 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9067 (in which case it is preserved). */
9070 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
9072 if (!inst
.operands
[i
].isreg
)
9075 if (! inst
.operands
[0].isvec
)
9077 inst
.error
= _("invalid co-processor operand");
9080 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
9084 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9086 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
9088 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
9090 gas_assert (!inst
.operands
[i
].writeback
);
9093 inst
.error
= _("instruction does not support unindexed addressing");
9096 inst
.instruction
|= inst
.operands
[i
].imm
;
9097 inst
.instruction
|= INDEX_UP
;
9101 if (inst
.operands
[i
].preind
)
9102 inst
.instruction
|= PRE_INDEX
;
9104 if (inst
.operands
[i
].writeback
)
9106 if (inst
.operands
[i
].reg
== REG_PC
)
9108 inst
.error
= _("pc may not be used with write-back");
9113 inst
.error
= _("instruction does not support writeback");
9116 inst
.instruction
|= WRITE_BACK
;
9120 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9121 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9122 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9123 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9126 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9128 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9131 /* Prefer + for zero encoded value. */
9132 if (!inst
.operands
[i
].negative
)
9133 inst
.instruction
|= INDEX_UP
;
9138 /* Functions for instruction encoding, sorted by sub-architecture.
9139 First some generics; their names are taken from the conventional
9140 bit positions for register arguments in ARM format instructions. */
9150 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9156 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9162 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9163 inst
.instruction
|= inst
.operands
[1].reg
;
9169 inst
.instruction
|= inst
.operands
[0].reg
;
9170 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9176 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9177 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9183 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9184 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9190 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9191 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9195 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9197 if (ARM_CPU_IS_ANY (cpu_variant
))
9199 as_tsktsk ("%s", msg
);
9202 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9214 unsigned Rn
= inst
.operands
[2].reg
;
9215 /* Enforce restrictions on SWP instruction. */
9216 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9218 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9219 _("Rn must not overlap other operands"));
9221 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9223 if (!check_obsolete (&arm_ext_v8
,
9224 _("swp{b} use is obsoleted for ARMv8 and later"))
9225 && warn_on_deprecated
9226 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9227 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9230 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9231 inst
.instruction
|= inst
.operands
[1].reg
;
9232 inst
.instruction
|= Rn
<< 16;
9238 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9239 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9240 inst
.instruction
|= inst
.operands
[2].reg
;
9246 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9247 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9248 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9249 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9251 inst
.instruction
|= inst
.operands
[0].reg
;
9252 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9253 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9259 inst
.instruction
|= inst
.operands
[0].imm
;
9265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9266 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9269 /* ARM instructions, in alphabetical order by function name (except
9270 that wrapper functions appear immediately after the function they
9273 /* This is a pseudo-op of the form "adr rd, label" to be converted
9274 into a relative address of the form "add rd, pc, #label-.-8". */
9279 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9281 /* Frag hacking will turn this into a sub instruction if the offset turns
9282 out to be negative. */
9283 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9284 inst
.relocs
[0].pc_rel
= 1;
9285 inst
.relocs
[0].exp
.X_add_number
-= 8;
9287 if (support_interwork
9288 && inst
.relocs
[0].exp
.X_op
== O_symbol
9289 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9290 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9291 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9292 inst
.relocs
[0].exp
.X_add_number
|= 1;
9295 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9296 into a relative address of the form:
9297 add rd, pc, #low(label-.-8)"
9298 add rd, rd, #high(label-.-8)" */
9303 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9305 /* Frag hacking will turn this into a sub instruction if the offset turns
9306 out to be negative. */
9307 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9308 inst
.relocs
[0].pc_rel
= 1;
9309 inst
.size
= INSN_SIZE
* 2;
9310 inst
.relocs
[0].exp
.X_add_number
-= 8;
9312 if (support_interwork
9313 && inst
.relocs
[0].exp
.X_op
== O_symbol
9314 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9315 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9316 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9317 inst
.relocs
[0].exp
.X_add_number
|= 1;
9323 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9324 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9326 if (!inst
.operands
[1].present
)
9327 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9328 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9329 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9330 encode_arm_shifter_operand (2);
9336 if (inst
.operands
[0].present
)
9337 inst
.instruction
|= inst
.operands
[0].imm
;
9339 inst
.instruction
|= 0xf;
9345 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9346 constraint (msb
> 32, _("bit-field extends past end of register"));
9347 /* The instruction encoding stores the LSB and MSB,
9348 not the LSB and width. */
9349 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9350 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9351 inst
.instruction
|= (msb
- 1) << 16;
9359 /* #0 in second position is alternative syntax for bfc, which is
9360 the same instruction but with REG_PC in the Rm field. */
9361 if (!inst
.operands
[1].isreg
)
9362 inst
.operands
[1].reg
= REG_PC
;
9364 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9365 constraint (msb
> 32, _("bit-field extends past end of register"));
9366 /* The instruction encoding stores the LSB and MSB,
9367 not the LSB and width. */
9368 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9369 inst
.instruction
|= inst
.operands
[1].reg
;
9370 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9371 inst
.instruction
|= (msb
- 1) << 16;
9377 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9378 _("bit-field extends past end of register"));
9379 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9380 inst
.instruction
|= inst
.operands
[1].reg
;
9381 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9382 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9385 /* ARM V5 breakpoint instruction (argument parse)
9386 BKPT <16 bit unsigned immediate>
9387 Instruction is not conditional.
9388 The bit pattern given in insns[] has the COND_ALWAYS condition,
9389 and it is an error if the caller tried to override that. */
9394 /* Top 12 of 16 bits to bits 19:8. */
9395 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9397 /* Bottom 4 of 16 bits to bits 3:0. */
9398 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9402 encode_branch (int default_reloc
)
9404 if (inst
.operands
[0].hasreloc
)
9406 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9407 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9408 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9409 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9410 ? BFD_RELOC_ARM_PLT32
9411 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9414 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9415 inst
.relocs
[0].pc_rel
= 1;
9422 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9423 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9426 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9433 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9435 if (inst
.cond
== COND_ALWAYS
)
9436 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9438 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9442 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9445 /* ARM V5 branch-link-exchange instruction (argument parse)
9446 BLX <target_addr> ie BLX(1)
9447 BLX{<condition>} <Rm> ie BLX(2)
9448 Unfortunately, there are two different opcodes for this mnemonic.
9449 So, the insns[].value is not used, and the code here zaps values
9450 into inst.instruction.
9451 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9456 if (inst
.operands
[0].isreg
)
9458 /* Arg is a register; the opcode provided by insns[] is correct.
9459 It is not illegal to do "blx pc", just useless. */
9460 if (inst
.operands
[0].reg
== REG_PC
)
9461 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9463 inst
.instruction
|= inst
.operands
[0].reg
;
9467 /* Arg is an address; this instruction cannot be executed
9468 conditionally, and the opcode must be adjusted.
9469 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9470 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9471 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9472 inst
.instruction
= 0xfa000000;
9473 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9480 bfd_boolean want_reloc
;
9482 if (inst
.operands
[0].reg
== REG_PC
)
9483 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9485 inst
.instruction
|= inst
.operands
[0].reg
;
9486 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9487 it is for ARMv4t or earlier. */
9488 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9489 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9490 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9494 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9499 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9503 /* ARM v5TEJ. Jump to Jazelle code. */
9508 if (inst
.operands
[0].reg
== REG_PC
)
9509 as_tsktsk (_("use of r15 in bxj is not really useful"));
9511 inst
.instruction
|= inst
.operands
[0].reg
;
9514 /* Co-processor data operation:
9515 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9516 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9520 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9521 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9522 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9523 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9524 inst
.instruction
|= inst
.operands
[4].reg
;
9525 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9531 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9532 encode_arm_shifter_operand (1);
9535 /* Transfer between coprocessor and ARM registers.
9536 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9541 No special properties. */
9543 struct deprecated_coproc_regs_s
9550 arm_feature_set deprecated
;
9551 arm_feature_set obsoleted
;
9552 const char *dep_msg
;
9553 const char *obs_msg
;
9556 #define DEPR_ACCESS_V8 \
9557 N_("This coprocessor register access is deprecated in ARMv8")
9559 /* Table of all deprecated coprocessor registers. */
9560 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9562 {15, 0, 7, 10, 5, /* CP15DMB. */
9563 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9564 DEPR_ACCESS_V8
, NULL
},
9565 {15, 0, 7, 10, 4, /* CP15DSB. */
9566 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9567 DEPR_ACCESS_V8
, NULL
},
9568 {15, 0, 7, 5, 4, /* CP15ISB. */
9569 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9570 DEPR_ACCESS_V8
, NULL
},
9571 {14, 6, 1, 0, 0, /* TEEHBR. */
9572 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9573 DEPR_ACCESS_V8
, NULL
},
9574 {14, 6, 0, 0, 0, /* TEECR. */
9575 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9576 DEPR_ACCESS_V8
, NULL
},
9579 #undef DEPR_ACCESS_V8
9581 static const size_t deprecated_coproc_reg_count
=
9582 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9590 Rd
= inst
.operands
[2].reg
;
9593 if (inst
.instruction
== 0xee000010
9594 || inst
.instruction
== 0xfe000010)
9596 reject_bad_reg (Rd
);
9597 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9599 constraint (Rd
== REG_SP
, BAD_SP
);
9604 if (inst
.instruction
== 0xe000010)
9605 constraint (Rd
== REG_PC
, BAD_PC
);
9608 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9610 const struct deprecated_coproc_regs_s
*r
=
9611 deprecated_coproc_regs
+ i
;
9613 if (inst
.operands
[0].reg
== r
->cp
9614 && inst
.operands
[1].imm
== r
->opc1
9615 && inst
.operands
[3].reg
== r
->crn
9616 && inst
.operands
[4].reg
== r
->crm
9617 && inst
.operands
[5].imm
== r
->opc2
)
9619 if (! ARM_CPU_IS_ANY (cpu_variant
)
9620 && warn_on_deprecated
9621 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9622 as_tsktsk ("%s", r
->dep_msg
);
9626 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9627 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9628 inst
.instruction
|= Rd
<< 12;
9629 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9630 inst
.instruction
|= inst
.operands
[4].reg
;
9631 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9634 /* Transfer between coprocessor register and pair of ARM registers.
9635 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9640 Two XScale instructions are special cases of these:
9642 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9643 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9645 Result unpredictable if Rd or Rn is R15. */
9652 Rd
= inst
.operands
[2].reg
;
9653 Rn
= inst
.operands
[3].reg
;
9657 reject_bad_reg (Rd
);
9658 reject_bad_reg (Rn
);
9662 constraint (Rd
== REG_PC
, BAD_PC
);
9663 constraint (Rn
== REG_PC
, BAD_PC
);
9666 /* Only check the MRRC{2} variants. */
9667 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9669 /* If Rd == Rn, error that the operation is
9670 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9671 constraint (Rd
== Rn
, BAD_OVERLAP
);
9674 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9675 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9676 inst
.instruction
|= Rd
<< 12;
9677 inst
.instruction
|= Rn
<< 16;
9678 inst
.instruction
|= inst
.operands
[4].reg
;
9684 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9685 if (inst
.operands
[1].present
)
9687 inst
.instruction
|= CPSI_MMOD
;
9688 inst
.instruction
|= inst
.operands
[1].imm
;
9695 inst
.instruction
|= inst
.operands
[0].imm
;
9701 unsigned Rd
, Rn
, Rm
;
9703 Rd
= inst
.operands
[0].reg
;
9704 Rn
= (inst
.operands
[1].present
9705 ? inst
.operands
[1].reg
: Rd
);
9706 Rm
= inst
.operands
[2].reg
;
9708 constraint ((Rd
== REG_PC
), BAD_PC
);
9709 constraint ((Rn
== REG_PC
), BAD_PC
);
9710 constraint ((Rm
== REG_PC
), BAD_PC
);
9712 inst
.instruction
|= Rd
<< 16;
9713 inst
.instruction
|= Rn
<< 0;
9714 inst
.instruction
|= Rm
<< 8;
9720 /* There is no IT instruction in ARM mode. We
9721 process it to do the validation as if in
9722 thumb mode, just in case the code gets
9723 assembled for thumb using the unified syntax. */
9728 set_pred_insn_type (IT_INSN
);
9729 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9730 now_pred
.cc
= inst
.operands
[0].imm
;
9734 /* If there is only one register in the register list,
9735 then return its register number. Otherwise return -1. */
9737 only_one_reg_in_list (int range
)
9739 int i
= ffs (range
) - 1;
9740 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9744 encode_ldmstm(int from_push_pop_mnem
)
9746 int base_reg
= inst
.operands
[0].reg
;
9747 int range
= inst
.operands
[1].imm
;
9750 inst
.instruction
|= base_reg
<< 16;
9751 inst
.instruction
|= range
;
9753 if (inst
.operands
[1].writeback
)
9754 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9756 if (inst
.operands
[0].writeback
)
9758 inst
.instruction
|= WRITE_BACK
;
9759 /* Check for unpredictable uses of writeback. */
9760 if (inst
.instruction
& LOAD_BIT
)
9762 /* Not allowed in LDM type 2. */
9763 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9764 && ((range
& (1 << REG_PC
)) == 0))
9765 as_warn (_("writeback of base register is UNPREDICTABLE"));
9766 /* Only allowed if base reg not in list for other types. */
9767 else if (range
& (1 << base_reg
))
9768 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9772 /* Not allowed for type 2. */
9773 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9774 as_warn (_("writeback of base register is UNPREDICTABLE"));
9775 /* Only allowed if base reg not in list, or first in list. */
9776 else if ((range
& (1 << base_reg
))
9777 && (range
& ((1 << base_reg
) - 1)))
9778 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9782 /* If PUSH/POP has only one register, then use the A2 encoding. */
9783 one_reg
= only_one_reg_in_list (range
);
9784 if (from_push_pop_mnem
&& one_reg
>= 0)
9786 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9788 if (is_push
&& one_reg
== 13 /* SP */)
9789 /* PR 22483: The A2 encoding cannot be used when
9790 pushing the stack pointer as this is UNPREDICTABLE. */
9793 inst
.instruction
&= A_COND_MASK
;
9794 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9795 inst
.instruction
|= one_reg
<< 12;
9802 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9805 /* ARMv5TE load-consecutive (argument parse)
9814 constraint (inst
.operands
[0].reg
% 2 != 0,
9815 _("first transfer register must be even"));
9816 constraint (inst
.operands
[1].present
9817 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9818 _("can only transfer two consecutive registers"));
9819 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9820 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9822 if (!inst
.operands
[1].present
)
9823 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9825 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9826 register and the first register written; we have to diagnose
9827 overlap between the base and the second register written here. */
9829 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9830 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9831 as_warn (_("base register written back, and overlaps "
9832 "second transfer register"));
9834 if (!(inst
.instruction
& V4_STR_BIT
))
9836 /* For an index-register load, the index register must not overlap the
9837 destination (even if not write-back). */
9838 if (inst
.operands
[2].immisreg
9839 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9840 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9841 as_warn (_("index register overlaps transfer register"));
9843 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9844 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9850 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9851 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9852 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9853 || inst
.operands
[1].negative
9854 /* This can arise if the programmer has written
9856 or if they have mistakenly used a register name as the last
9859 It is very difficult to distinguish between these two cases
9860 because "rX" might actually be a label. ie the register
9861 name has been occluded by a symbol of the same name. So we
9862 just generate a general 'bad addressing mode' type error
9863 message and leave it up to the programmer to discover the
9864 true cause and fix their mistake. */
9865 || (inst
.operands
[1].reg
== REG_PC
),
9868 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9869 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9870 _("offset must be zero in ARM encoding"));
9872 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9874 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9875 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9876 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9882 constraint (inst
.operands
[0].reg
% 2 != 0,
9883 _("even register required"));
9884 constraint (inst
.operands
[1].present
9885 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9886 _("can only load two consecutive registers"));
9887 /* If op 1 were present and equal to PC, this function wouldn't
9888 have been called in the first place. */
9889 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9892 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9895 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9896 which is not a multiple of four is UNPREDICTABLE. */
9898 check_ldr_r15_aligned (void)
9900 constraint (!(inst
.operands
[1].immisreg
)
9901 && (inst
.operands
[0].reg
== REG_PC
9902 && inst
.operands
[1].reg
== REG_PC
9903 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9904 _("ldr to register 15 must be 4-byte aligned"));
9910 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9911 if (!inst
.operands
[1].isreg
)
9912 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9914 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9915 check_ldr_r15_aligned ();
9921 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9923 if (inst
.operands
[1].preind
)
9925 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9926 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9927 _("this instruction requires a post-indexed address"));
9929 inst
.operands
[1].preind
= 0;
9930 inst
.operands
[1].postind
= 1;
9931 inst
.operands
[1].writeback
= 1;
9933 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9934 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9937 /* Halfword and signed-byte load/store operations. */
9942 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9943 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9944 if (!inst
.operands
[1].isreg
)
9945 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9947 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9953 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9955 if (inst
.operands
[1].preind
)
9957 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9958 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9959 _("this instruction requires a post-indexed address"));
9961 inst
.operands
[1].preind
= 0;
9962 inst
.operands
[1].postind
= 1;
9963 inst
.operands
[1].writeback
= 1;
9965 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9966 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9969 /* Co-processor register load/store.
9970 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9974 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9975 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9976 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9982 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9983 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9984 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9985 && !(inst
.instruction
& 0x00400000))
9986 as_tsktsk (_("Rd and Rm should be different in mla"));
9988 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9989 inst
.instruction
|= inst
.operands
[1].reg
;
9990 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9991 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9997 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9998 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10000 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10001 encode_arm_shifter_operand (1);
10004 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
10011 top
= (inst
.instruction
& 0x00400000) != 0;
10012 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
10013 _(":lower16: not allowed in this instruction"));
10014 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
10015 _(":upper16: not allowed in this instruction"));
10016 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10017 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
10019 imm
= inst
.relocs
[0].exp
.X_add_number
;
10020 /* The value is in two pieces: 0:11, 16:19. */
10021 inst
.instruction
|= (imm
& 0x00000fff);
10022 inst
.instruction
|= (imm
& 0x0000f000) << 4;
10027 do_vfp_nsyn_mrs (void)
10029 if (inst
.operands
[0].isvec
)
10031 if (inst
.operands
[1].reg
!= 1)
10032 first_error (_("operand 1 must be FPSCR"));
10033 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
10034 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
10035 do_vfp_nsyn_opcode ("fmstat");
10037 else if (inst
.operands
[1].isvec
)
10038 do_vfp_nsyn_opcode ("fmrx");
10046 do_vfp_nsyn_msr (void)
10048 if (inst
.operands
[0].isvec
)
10049 do_vfp_nsyn_opcode ("fmxr");
10059 unsigned Rt
= inst
.operands
[0].reg
;
10061 if (thumb_mode
&& Rt
== REG_SP
)
10063 inst
.error
= BAD_SP
;
10067 switch (inst
.operands
[1].reg
)
10069 /* MVFR2 is only valid for Armv8-A. */
10071 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10075 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10076 case 1: /* fpscr. */
10077 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10078 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10082 case 14: /* fpcxt_ns. */
10083 case 15: /* fpcxt_s. */
10084 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10085 _("selected processor does not support instruction"));
10088 case 2: /* fpscr_nzcvqc. */
10089 case 12: /* vpr. */
10091 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10092 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10093 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10094 _("selected processor does not support instruction"));
10095 if (inst
.operands
[0].reg
!= 2
10096 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10097 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10104 /* APSR_ sets isvec. All other refs to PC are illegal. */
10105 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10107 inst
.error
= BAD_PC
;
10111 /* If we get through parsing the register name, we just insert the number
10112 generated into the instruction without further validation. */
10113 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10114 inst
.instruction
|= (Rt
<< 12);
10120 unsigned Rt
= inst
.operands
[1].reg
;
10123 reject_bad_reg (Rt
);
10124 else if (Rt
== REG_PC
)
10126 inst
.error
= BAD_PC
;
10130 switch (inst
.operands
[0].reg
)
10132 /* MVFR2 is only valid for Armv8-A. */
10134 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10138 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10139 case 1: /* fpcr. */
10140 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10141 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10145 case 14: /* fpcxt_ns. */
10146 case 15: /* fpcxt_s. */
10147 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10148 _("selected processor does not support instruction"));
10151 case 2: /* fpscr_nzcvqc. */
10152 case 12: /* vpr. */
10154 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10155 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10156 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10157 _("selected processor does not support instruction"));
10158 if (inst
.operands
[0].reg
!= 2
10159 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10160 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10167 /* If we get through parsing the register name, we just insert the number
10168 generated into the instruction without further validation. */
10169 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10170 inst
.instruction
|= (Rt
<< 12);
10178 if (do_vfp_nsyn_mrs () == SUCCESS
)
10181 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10182 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10184 if (inst
.operands
[1].isreg
)
10186 br
= inst
.operands
[1].reg
;
10187 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10188 as_bad (_("bad register for mrs"));
10192 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10193 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10195 _("'APSR', 'CPSR' or 'SPSR' expected"));
10196 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10199 inst
.instruction
|= br
;
10202 /* Two possible forms:
10203 "{C|S}PSR_<field>, Rm",
10204 "{C|S}PSR_f, #expression". */
10209 if (do_vfp_nsyn_msr () == SUCCESS
)
10212 inst
.instruction
|= inst
.operands
[0].imm
;
10213 if (inst
.operands
[1].isreg
)
10214 inst
.instruction
|= inst
.operands
[1].reg
;
10217 inst
.instruction
|= INST_IMMEDIATE
;
10218 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10219 inst
.relocs
[0].pc_rel
= 0;
10226 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10228 if (!inst
.operands
[2].present
)
10229 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10230 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10231 inst
.instruction
|= inst
.operands
[1].reg
;
10232 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10234 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10235 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10236 as_tsktsk (_("Rd and Rm should be different in mul"));
10239 /* Long Multiply Parser
10240 UMULL RdLo, RdHi, Rm, Rs
10241 SMULL RdLo, RdHi, Rm, Rs
10242 UMLAL RdLo, RdHi, Rm, Rs
10243 SMLAL RdLo, RdHi, Rm, Rs. */
10248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10249 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10250 inst
.instruction
|= inst
.operands
[2].reg
;
10251 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10253 /* rdhi and rdlo must be different. */
10254 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10255 as_tsktsk (_("rdhi and rdlo must be different"));
10257 /* rdhi, rdlo and rm must all be different before armv6. */
10258 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10259 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10260 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10261 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10267 if (inst
.operands
[0].present
10268 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10270 /* Architectural NOP hints are CPSR sets with no bits selected. */
10271 inst
.instruction
&= 0xf0000000;
10272 inst
.instruction
|= 0x0320f000;
10273 if (inst
.operands
[0].present
)
10274 inst
.instruction
|= inst
.operands
[0].imm
;
10278 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10279 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10280 Condition defaults to COND_ALWAYS.
10281 Error if Rd, Rn or Rm are R15. */
10286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10287 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10288 inst
.instruction
|= inst
.operands
[2].reg
;
10289 if (inst
.operands
[3].present
)
10290 encode_arm_shift (3);
10293 /* ARM V6 PKHTB (Argument Parse). */
10298 if (!inst
.operands
[3].present
)
10300 /* If the shift specifier is omitted, turn the instruction
10301 into pkhbt rd, rm, rn. */
10302 inst
.instruction
&= 0xfff00010;
10303 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10304 inst
.instruction
|= inst
.operands
[1].reg
;
10305 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10309 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10310 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10311 inst
.instruction
|= inst
.operands
[2].reg
;
10312 encode_arm_shift (3);
10316 /* ARMv5TE: Preload-Cache
10317 MP Extensions: Preload for write
10321 Syntactically, like LDR with B=1, W=0, L=1. */
10326 constraint (!inst
.operands
[0].isreg
,
10327 _("'[' expected after PLD mnemonic"));
10328 constraint (inst
.operands
[0].postind
,
10329 _("post-indexed expression used in preload instruction"));
10330 constraint (inst
.operands
[0].writeback
,
10331 _("writeback used in preload instruction"));
10332 constraint (!inst
.operands
[0].preind
,
10333 _("unindexed addressing used in preload instruction"));
10334 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10337 /* ARMv7: PLI <addr_mode> */
10341 constraint (!inst
.operands
[0].isreg
,
10342 _("'[' expected after PLI mnemonic"));
10343 constraint (inst
.operands
[0].postind
,
10344 _("post-indexed expression used in preload instruction"));
10345 constraint (inst
.operands
[0].writeback
,
10346 _("writeback used in preload instruction"));
10347 constraint (!inst
.operands
[0].preind
,
10348 _("unindexed addressing used in preload instruction"));
10349 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10350 inst
.instruction
&= ~PRE_INDEX
;
10356 constraint (inst
.operands
[0].writeback
,
10357 _("push/pop do not support {reglist}^"));
10358 inst
.operands
[1] = inst
.operands
[0];
10359 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10360 inst
.operands
[0].isreg
= 1;
10361 inst
.operands
[0].writeback
= 1;
10362 inst
.operands
[0].reg
= REG_SP
;
10363 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10366 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10367 word at the specified address and the following word
10369 Unconditionally executed.
10370 Error if Rn is R15. */
10375 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10376 if (inst
.operands
[0].writeback
)
10377 inst
.instruction
|= WRITE_BACK
;
10380 /* ARM V6 ssat (argument parse). */
10385 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10386 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10387 inst
.instruction
|= inst
.operands
[2].reg
;
10389 if (inst
.operands
[3].present
)
10390 encode_arm_shift (3);
10393 /* ARM V6 usat (argument parse). */
10398 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10399 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10400 inst
.instruction
|= inst
.operands
[2].reg
;
10402 if (inst
.operands
[3].present
)
10403 encode_arm_shift (3);
10406 /* ARM V6 ssat16 (argument parse). */
10411 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10412 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10413 inst
.instruction
|= inst
.operands
[2].reg
;
10419 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10420 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10421 inst
.instruction
|= inst
.operands
[2].reg
;
10424 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10425 preserving the other bits.
10427 setend <endian_specifier>, where <endian_specifier> is either
10433 if (warn_on_deprecated
10434 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10435 as_tsktsk (_("setend use is deprecated for ARMv8"));
10437 if (inst
.operands
[0].imm
)
10438 inst
.instruction
|= 0x200;
10444 unsigned int Rm
= (inst
.operands
[1].present
10445 ? inst
.operands
[1].reg
10446 : inst
.operands
[0].reg
);
10448 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10449 inst
.instruction
|= Rm
;
10450 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10452 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10453 inst
.instruction
|= SHIFT_BY_REG
;
10454 /* PR 12854: Error on extraneous shifts. */
10455 constraint (inst
.operands
[2].shifted
,
10456 _("extraneous shift as part of operand to shift insn"));
10459 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10465 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10466 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10468 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10469 inst
.relocs
[0].pc_rel
= 0;
10475 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10476 inst
.relocs
[0].pc_rel
= 0;
10482 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10483 inst
.relocs
[0].pc_rel
= 0;
10489 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10490 _("selected processor does not support SETPAN instruction"));
10492 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10498 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10499 _("selected processor does not support SETPAN instruction"));
10501 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10504 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10505 SMLAxy{cond} Rd,Rm,Rs,Rn
10506 SMLAWy{cond} Rd,Rm,Rs,Rn
10507 Error if any register is R15. */
10512 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10513 inst
.instruction
|= inst
.operands
[1].reg
;
10514 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10515 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10518 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10519 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10520 Error if any register is R15.
10521 Warning if Rdlo == Rdhi. */
10526 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10527 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10528 inst
.instruction
|= inst
.operands
[2].reg
;
10529 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10531 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10532 as_tsktsk (_("rdhi and rdlo must be different"));
10535 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10536 SMULxy{cond} Rd,Rm,Rs
10537 Error if any register is R15. */
10542 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10543 inst
.instruction
|= inst
.operands
[1].reg
;
10544 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10547 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10548 the same for both ARM and Thumb-2. */
10555 if (inst
.operands
[0].present
)
10557 reg
= inst
.operands
[0].reg
;
10558 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10563 inst
.instruction
|= reg
<< 16;
10564 inst
.instruction
|= inst
.operands
[1].imm
;
10565 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10566 inst
.instruction
|= WRITE_BACK
;
10569 /* ARM V6 strex (argument parse). */
10574 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10575 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10576 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10577 || inst
.operands
[2].negative
10578 /* See comment in do_ldrex(). */
10579 || (inst
.operands
[2].reg
== REG_PC
),
10582 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10583 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10585 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10586 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10587 _("offset must be zero in ARM encoding"));
10589 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10590 inst
.instruction
|= inst
.operands
[1].reg
;
10591 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10592 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10596 do_t_strexbh (void)
10598 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10599 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10600 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10601 || inst
.operands
[2].negative
,
10604 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10605 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10613 constraint (inst
.operands
[1].reg
% 2 != 0,
10614 _("even register required"));
10615 constraint (inst
.operands
[2].present
10616 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10617 _("can only store two consecutive registers"));
10618 /* If op 2 were present and equal to PC, this function wouldn't
10619 have been called in the first place. */
10620 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10622 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10623 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10624 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10627 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10628 inst
.instruction
|= inst
.operands
[1].reg
;
10629 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10636 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10637 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10645 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10646 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10651 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10652 extends it to 32-bits, and adds the result to a value in another
10653 register. You can specify a rotation by 0, 8, 16, or 24 bits
10654 before extracting the 16-bit value.
10655 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10656 Condition defaults to COND_ALWAYS.
10657 Error if any register uses R15. */
10662 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10663 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10664 inst
.instruction
|= inst
.operands
[2].reg
;
10665 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10670 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10671 Condition defaults to COND_ALWAYS.
10672 Error if any register uses R15. */
10677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10678 inst
.instruction
|= inst
.operands
[1].reg
;
10679 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10682 /* VFP instructions. In a logical order: SP variant first, monad
10683 before dyad, arithmetic then move then load/store. */
10686 do_vfp_sp_monadic (void)
10688 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10689 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10692 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10693 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10697 do_vfp_sp_dyadic (void)
10699 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10700 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10701 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10705 do_vfp_sp_compare_z (void)
10707 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10711 do_vfp_dp_sp_cvt (void)
10713 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10714 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10718 do_vfp_sp_dp_cvt (void)
10720 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10721 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10725 do_vfp_reg_from_sp (void)
10727 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10728 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10731 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10732 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10736 do_vfp_reg2_from_sp2 (void)
10738 constraint (inst
.operands
[2].imm
!= 2,
10739 _("only two consecutive VFP SP registers allowed here"));
10740 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10741 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10742 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10746 do_vfp_sp_from_reg (void)
10748 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10749 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10752 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10753 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10757 do_vfp_sp2_from_reg2 (void)
10759 constraint (inst
.operands
[0].imm
!= 2,
10760 _("only two consecutive VFP SP registers allowed here"));
10761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10762 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10763 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10767 do_vfp_sp_ldst (void)
10769 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10770 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10774 do_vfp_dp_ldst (void)
10776 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10777 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10782 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10784 if (inst
.operands
[0].writeback
)
10785 inst
.instruction
|= WRITE_BACK
;
10787 constraint (ldstm_type
!= VFP_LDSTMIA
,
10788 _("this addressing mode requires base-register writeback"));
10789 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10790 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10791 inst
.instruction
|= inst
.operands
[1].imm
;
10795 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10799 if (inst
.operands
[0].writeback
)
10800 inst
.instruction
|= WRITE_BACK
;
10802 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10803 _("this addressing mode requires base-register writeback"));
10805 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10806 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10808 count
= inst
.operands
[1].imm
<< 1;
10809 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10812 inst
.instruction
|= count
;
10816 do_vfp_sp_ldstmia (void)
10818 vfp_sp_ldstm (VFP_LDSTMIA
);
10822 do_vfp_sp_ldstmdb (void)
10824 vfp_sp_ldstm (VFP_LDSTMDB
);
10828 do_vfp_dp_ldstmia (void)
10830 vfp_dp_ldstm (VFP_LDSTMIA
);
10834 do_vfp_dp_ldstmdb (void)
10836 vfp_dp_ldstm (VFP_LDSTMDB
);
10840 do_vfp_xp_ldstmia (void)
10842 vfp_dp_ldstm (VFP_LDSTMIAX
);
10846 do_vfp_xp_ldstmdb (void)
10848 vfp_dp_ldstm (VFP_LDSTMDBX
);
10852 do_vfp_dp_rd_rm (void)
10854 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10855 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10858 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10859 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10863 do_vfp_dp_rn_rd (void)
10865 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10866 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10870 do_vfp_dp_rd_rn (void)
10872 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10873 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10877 do_vfp_dp_rd_rn_rm (void)
10879 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10880 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10883 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10884 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10885 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10889 do_vfp_dp_rd (void)
10891 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10895 do_vfp_dp_rm_rd_rn (void)
10897 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10898 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10901 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10902 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10903 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10906 /* VFPv3 instructions. */
10908 do_vfp_sp_const (void)
10910 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10911 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10912 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10916 do_vfp_dp_const (void)
10918 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10919 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10920 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10924 vfp_conv (int srcsize
)
10926 int immbits
= srcsize
- inst
.operands
[1].imm
;
10928 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10930 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10931 i.e. immbits must be in range 0 - 16. */
10932 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10935 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10937 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10938 i.e. immbits must be in range 0 - 31. */
10939 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10943 inst
.instruction
|= (immbits
& 1) << 5;
10944 inst
.instruction
|= (immbits
>> 1);
10948 do_vfp_sp_conv_16 (void)
10950 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10955 do_vfp_dp_conv_16 (void)
10957 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10962 do_vfp_sp_conv_32 (void)
10964 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10969 do_vfp_dp_conv_32 (void)
10971 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10975 /* FPA instructions. Also in a logical order. */
10980 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10981 inst
.instruction
|= inst
.operands
[1].reg
;
10985 do_fpa_ldmstm (void)
10987 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10988 switch (inst
.operands
[1].imm
)
10990 case 1: inst
.instruction
|= CP_T_X
; break;
10991 case 2: inst
.instruction
|= CP_T_Y
; break;
10992 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10997 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10999 /* The instruction specified "ea" or "fd", so we can only accept
11000 [Rn]{!}. The instruction does not really support stacking or
11001 unstacking, so we have to emulate these by setting appropriate
11002 bits and offsets. */
11003 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
11004 || inst
.relocs
[0].exp
.X_add_number
!= 0,
11005 _("this instruction does not support indexing"));
11007 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
11008 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
11010 if (!(inst
.instruction
& INDEX_UP
))
11011 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
11013 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
11015 inst
.operands
[2].preind
= 0;
11016 inst
.operands
[2].postind
= 1;
11020 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
11023 /* iWMMXt instructions: strictly in alphabetical order. */
11026 do_iwmmxt_tandorc (void)
11028 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
11032 do_iwmmxt_textrc (void)
11034 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11035 inst
.instruction
|= inst
.operands
[1].imm
;
11039 do_iwmmxt_textrm (void)
11041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11042 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11043 inst
.instruction
|= inst
.operands
[2].imm
;
11047 do_iwmmxt_tinsr (void)
11049 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11050 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11051 inst
.instruction
|= inst
.operands
[2].imm
;
11055 do_iwmmxt_tmia (void)
11057 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11058 inst
.instruction
|= inst
.operands
[1].reg
;
11059 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11063 do_iwmmxt_waligni (void)
11065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11066 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11067 inst
.instruction
|= inst
.operands
[2].reg
;
11068 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
11072 do_iwmmxt_wmerge (void)
11074 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11075 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11076 inst
.instruction
|= inst
.operands
[2].reg
;
11077 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
11081 do_iwmmxt_wmov (void)
11083 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11085 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11086 inst
.instruction
|= inst
.operands
[1].reg
;
11090 do_iwmmxt_wldstbh (void)
11093 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11095 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11097 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11098 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
11102 do_iwmmxt_wldstw (void)
11104 /* RIWR_RIWC clears .isreg for a control register. */
11105 if (!inst
.operands
[0].isreg
)
11107 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11108 inst
.instruction
|= 0xf0000000;
11111 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11112 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
11116 do_iwmmxt_wldstd (void)
11118 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11119 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11120 && inst
.operands
[1].immisreg
)
11122 inst
.instruction
&= ~0x1a000ff;
11123 inst
.instruction
|= (0xfU
<< 28);
11124 if (inst
.operands
[1].preind
)
11125 inst
.instruction
|= PRE_INDEX
;
11126 if (!inst
.operands
[1].negative
)
11127 inst
.instruction
|= INDEX_UP
;
11128 if (inst
.operands
[1].writeback
)
11129 inst
.instruction
|= WRITE_BACK
;
11130 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11131 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11132 inst
.instruction
|= inst
.operands
[1].imm
;
11135 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11139 do_iwmmxt_wshufh (void)
11141 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11142 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11143 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11144 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11148 do_iwmmxt_wzero (void)
11150 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11151 inst
.instruction
|= inst
.operands
[0].reg
;
11152 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11153 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11157 do_iwmmxt_wrwrwr_or_imm5 (void)
11159 if (inst
.operands
[2].isreg
)
11162 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11163 _("immediate operand requires iWMMXt2"));
11165 if (inst
.operands
[2].imm
== 0)
11167 switch ((inst
.instruction
>> 20) & 0xf)
11173 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11174 inst
.operands
[2].imm
= 16;
11175 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11181 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11182 inst
.operands
[2].imm
= 32;
11183 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11190 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11192 wrn
= (inst
.instruction
>> 16) & 0xf;
11193 inst
.instruction
&= 0xff0fff0f;
11194 inst
.instruction
|= wrn
;
11195 /* Bail out here; the instruction is now assembled. */
11200 /* Map 32 -> 0, etc. */
11201 inst
.operands
[2].imm
&= 0x1f;
11202 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11206 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11207 operations first, then control, shift, and load/store. */
11209 /* Insns like "foo X,Y,Z". */
11212 do_mav_triple (void)
11214 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11215 inst
.instruction
|= inst
.operands
[1].reg
;
11216 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11219 /* Insns like "foo W,X,Y,Z".
11220 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11225 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11226 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11227 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11228 inst
.instruction
|= inst
.operands
[3].reg
;
11231 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11233 do_mav_dspsc (void)
11235 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11238 /* Maverick shift immediate instructions.
11239 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11240 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11243 do_mav_shift (void)
11245 int imm
= inst
.operands
[2].imm
;
11247 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11248 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11250 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11251 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11252 Bit 4 should be 0. */
11253 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11255 inst
.instruction
|= imm
;
11258 /* XScale instructions. Also sorted arithmetic before move. */
11260 /* Xscale multiply-accumulate (argument parse)
11263 MIAxycc acc0,Rm,Rs. */
11268 inst
.instruction
|= inst
.operands
[1].reg
;
11269 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11272 /* Xscale move-accumulator-register (argument parse)
11274 MARcc acc0,RdLo,RdHi. */
11279 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11280 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11283 /* Xscale move-register-accumulator (argument parse)
11285 MRAcc RdLo,RdHi,acc0. */
11290 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11291 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11292 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11295 /* Encoding functions relevant only to Thumb. */
11297 /* inst.operands[i] is a shifted-register operand; encode
11298 it into inst.instruction in the format used by Thumb32. */
11301 encode_thumb32_shifted_operand (int i
)
11303 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11304 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11306 constraint (inst
.operands
[i
].immisreg
,
11307 _("shift by register not allowed in thumb mode"));
11308 inst
.instruction
|= inst
.operands
[i
].reg
;
11309 if (shift
== SHIFT_RRX
)
11310 inst
.instruction
|= SHIFT_ROR
<< 4;
11313 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11314 _("expression too complex"));
11316 constraint (value
> 32
11317 || (value
== 32 && (shift
== SHIFT_LSL
11318 || shift
== SHIFT_ROR
)),
11319 _("shift expression is too large"));
11323 else if (value
== 32)
11326 inst
.instruction
|= shift
<< 4;
11327 inst
.instruction
|= (value
& 0x1c) << 10;
11328 inst
.instruction
|= (value
& 0x03) << 6;
11333 /* inst.operands[i] was set up by parse_address. Encode it into a
11334 Thumb32 format load or store instruction. Reject forms that cannot
11335 be used with such instructions. If is_t is true, reject forms that
11336 cannot be used with a T instruction; if is_d is true, reject forms
11337 that cannot be used with a D instruction. If it is a store insn,
11338 reject PC in Rn. */
11341 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11343 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11345 constraint (!inst
.operands
[i
].isreg
,
11346 _("Instruction does not support =N addresses"));
11348 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11349 if (inst
.operands
[i
].immisreg
)
11351 constraint (is_pc
, BAD_PC_ADDRESSING
);
11352 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11353 constraint (inst
.operands
[i
].negative
,
11354 _("Thumb does not support negative register indexing"));
11355 constraint (inst
.operands
[i
].postind
,
11356 _("Thumb does not support register post-indexing"));
11357 constraint (inst
.operands
[i
].writeback
,
11358 _("Thumb does not support register indexing with writeback"));
11359 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11360 _("Thumb supports only LSL in shifted register indexing"));
11362 inst
.instruction
|= inst
.operands
[i
].imm
;
11363 if (inst
.operands
[i
].shifted
)
11365 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11366 _("expression too complex"));
11367 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11368 || inst
.relocs
[0].exp
.X_add_number
> 3,
11369 _("shift out of range"));
11370 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11372 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11374 else if (inst
.operands
[i
].preind
)
11376 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11377 constraint (is_t
&& inst
.operands
[i
].writeback
,
11378 _("cannot use writeback with this instruction"));
11379 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11380 BAD_PC_ADDRESSING
);
11384 inst
.instruction
|= 0x01000000;
11385 if (inst
.operands
[i
].writeback
)
11386 inst
.instruction
|= 0x00200000;
11390 inst
.instruction
|= 0x00000c00;
11391 if (inst
.operands
[i
].writeback
)
11392 inst
.instruction
|= 0x00000100;
11394 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11396 else if (inst
.operands
[i
].postind
)
11398 gas_assert (inst
.operands
[i
].writeback
);
11399 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11400 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11403 inst
.instruction
|= 0x00200000;
11405 inst
.instruction
|= 0x00000900;
11406 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11408 else /* unindexed - only for coprocessor */
11409 inst
.error
= _("instruction does not accept unindexed addressing");
11412 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11413 encodings (the latter only in post-V6T2 cores). The index is the
11414 value used in the insns table below. When there is more than one
11415 possible 16-bit encoding for the instruction, this table always
11417 Also contains several pseudo-instructions used during relaxation. */
11418 #define T16_32_TAB \
11419 X(_adc, 4140, eb400000), \
11420 X(_adcs, 4140, eb500000), \
11421 X(_add, 1c00, eb000000), \
11422 X(_adds, 1c00, eb100000), \
11423 X(_addi, 0000, f1000000), \
11424 X(_addis, 0000, f1100000), \
11425 X(_add_pc,000f, f20f0000), \
11426 X(_add_sp,000d, f10d0000), \
11427 X(_adr, 000f, f20f0000), \
11428 X(_and, 4000, ea000000), \
11429 X(_ands, 4000, ea100000), \
11430 X(_asr, 1000, fa40f000), \
11431 X(_asrs, 1000, fa50f000), \
11432 X(_b, e000, f000b000), \
11433 X(_bcond, d000, f0008000), \
11434 X(_bf, 0000, f040e001), \
11435 X(_bfcsel,0000, f000e001), \
11436 X(_bfx, 0000, f060e001), \
11437 X(_bfl, 0000, f000c001), \
11438 X(_bflx, 0000, f070e001), \
11439 X(_bic, 4380, ea200000), \
11440 X(_bics, 4380, ea300000), \
11441 X(_cinc, 0000, ea509000), \
11442 X(_cinv, 0000, ea50a000), \
11443 X(_cmn, 42c0, eb100f00), \
11444 X(_cmp, 2800, ebb00f00), \
11445 X(_cneg, 0000, ea50b000), \
11446 X(_cpsie, b660, f3af8400), \
11447 X(_cpsid, b670, f3af8600), \
11448 X(_cpy, 4600, ea4f0000), \
11449 X(_csel, 0000, ea508000), \
11450 X(_cset, 0000, ea5f900f), \
11451 X(_csetm, 0000, ea5fa00f), \
11452 X(_csinc, 0000, ea509000), \
11453 X(_csinv, 0000, ea50a000), \
11454 X(_csneg, 0000, ea50b000), \
11455 X(_dec_sp,80dd, f1ad0d00), \
11456 X(_dls, 0000, f040e001), \
11457 X(_dlstp, 0000, f000e001), \
11458 X(_eor, 4040, ea800000), \
11459 X(_eors, 4040, ea900000), \
11460 X(_inc_sp,00dd, f10d0d00), \
11461 X(_lctp, 0000, f00fe001), \
11462 X(_ldmia, c800, e8900000), \
11463 X(_ldr, 6800, f8500000), \
11464 X(_ldrb, 7800, f8100000), \
11465 X(_ldrh, 8800, f8300000), \
11466 X(_ldrsb, 5600, f9100000), \
11467 X(_ldrsh, 5e00, f9300000), \
11468 X(_ldr_pc,4800, f85f0000), \
11469 X(_ldr_pc2,4800, f85f0000), \
11470 X(_ldr_sp,9800, f85d0000), \
11471 X(_le, 0000, f00fc001), \
11472 X(_letp, 0000, f01fc001), \
11473 X(_lsl, 0000, fa00f000), \
11474 X(_lsls, 0000, fa10f000), \
11475 X(_lsr, 0800, fa20f000), \
11476 X(_lsrs, 0800, fa30f000), \
11477 X(_mov, 2000, ea4f0000), \
11478 X(_movs, 2000, ea5f0000), \
11479 X(_mul, 4340, fb00f000), \
11480 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11481 X(_mvn, 43c0, ea6f0000), \
11482 X(_mvns, 43c0, ea7f0000), \
11483 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11484 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11485 X(_orr, 4300, ea400000), \
11486 X(_orrs, 4300, ea500000), \
11487 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11488 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11489 X(_rev, ba00, fa90f080), \
11490 X(_rev16, ba40, fa90f090), \
11491 X(_revsh, bac0, fa90f0b0), \
11492 X(_ror, 41c0, fa60f000), \
11493 X(_rors, 41c0, fa70f000), \
11494 X(_sbc, 4180, eb600000), \
11495 X(_sbcs, 4180, eb700000), \
11496 X(_stmia, c000, e8800000), \
11497 X(_str, 6000, f8400000), \
11498 X(_strb, 7000, f8000000), \
11499 X(_strh, 8000, f8200000), \
11500 X(_str_sp,9000, f84d0000), \
11501 X(_sub, 1e00, eba00000), \
11502 X(_subs, 1e00, ebb00000), \
11503 X(_subi, 8000, f1a00000), \
11504 X(_subis, 8000, f1b00000), \
11505 X(_sxtb, b240, fa4ff080), \
11506 X(_sxth, b200, fa0ff080), \
11507 X(_tst, 4200, ea100f00), \
11508 X(_uxtb, b2c0, fa5ff080), \
11509 X(_uxth, b280, fa1ff080), \
11510 X(_nop, bf00, f3af8000), \
11511 X(_yield, bf10, f3af8001), \
11512 X(_wfe, bf20, f3af8002), \
11513 X(_wfi, bf30, f3af8003), \
11514 X(_wls, 0000, f040c001), \
11515 X(_wlstp, 0000, f000c001), \
11516 X(_sev, bf40, f3af8004), \
11517 X(_sevl, bf50, f3af8005), \
11518 X(_udf, de00, f7f0a000)
11520 /* To catch errors in encoding functions, the codes are all offset by
11521 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11522 as 16-bit instructions. */
11523 #define X(a,b,c) T_MNEM##a
11524 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11527 #define X(a,b,c) 0x##b
11528 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11529 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11532 #define X(a,b,c) 0x##c
11533 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11534 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11535 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11539 /* Thumb instruction encoders, in alphabetical order. */
11541 /* ADDW or SUBW. */
11544 do_t_add_sub_w (void)
11548 Rd
= inst
.operands
[0].reg
;
11549 Rn
= inst
.operands
[1].reg
;
11551 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11552 is the SP-{plus,minus}-immediate form of the instruction. */
11554 constraint (Rd
== REG_PC
, BAD_PC
);
11556 reject_bad_reg (Rd
);
11558 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11559 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11562 /* Parse an add or subtract instruction. We get here with inst.instruction
11563 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11566 do_t_add_sub (void)
11570 Rd
= inst
.operands
[0].reg
;
11571 Rs
= (inst
.operands
[1].present
11572 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11573 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11576 set_pred_insn_type_last ();
11578 if (unified_syntax
)
11581 bfd_boolean narrow
;
11584 flags
= (inst
.instruction
== T_MNEM_adds
11585 || inst
.instruction
== T_MNEM_subs
);
11587 narrow
= !in_pred_block ();
11589 narrow
= in_pred_block ();
11590 if (!inst
.operands
[2].isreg
)
11594 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11595 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11597 add
= (inst
.instruction
== T_MNEM_add
11598 || inst
.instruction
== T_MNEM_adds
);
11600 if (inst
.size_req
!= 4)
11602 /* Attempt to use a narrow opcode, with relaxation if
11604 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11605 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11606 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11607 opcode
= T_MNEM_add_sp
;
11608 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11609 opcode
= T_MNEM_add_pc
;
11610 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11613 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11615 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11619 inst
.instruction
= THUMB_OP16(opcode
);
11620 inst
.instruction
|= (Rd
<< 4) | Rs
;
11621 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11622 || (inst
.relocs
[0].type
11623 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11625 if (inst
.size_req
== 2)
11626 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11628 inst
.relax
= opcode
;
11632 constraint (inst
.size_req
== 2, BAD_HIREG
);
11634 if (inst
.size_req
== 4
11635 || (inst
.size_req
!= 2 && !opcode
))
11637 constraint ((inst
.relocs
[0].type
11638 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11639 && (inst
.relocs
[0].type
11640 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11641 THUMB1_RELOC_ONLY
);
11644 constraint (add
, BAD_PC
);
11645 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11646 _("only SUBS PC, LR, #const allowed"));
11647 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11648 _("expression too complex"));
11649 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11650 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11651 _("immediate value out of range"));
11652 inst
.instruction
= T2_SUBS_PC_LR
11653 | inst
.relocs
[0].exp
.X_add_number
;
11654 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11657 else if (Rs
== REG_PC
)
11659 /* Always use addw/subw. */
11660 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11661 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11665 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11666 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11669 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11671 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11673 inst
.instruction
|= Rd
<< 8;
11674 inst
.instruction
|= Rs
<< 16;
11679 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11680 unsigned int shift
= inst
.operands
[2].shift_kind
;
11682 Rn
= inst
.operands
[2].reg
;
11683 /* See if we can do this with a 16-bit instruction. */
11684 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11686 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11691 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11692 || inst
.instruction
== T_MNEM_add
)
11694 : T_OPCODE_SUB_R3
);
11695 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11699 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11701 /* Thumb-1 cores (except v6-M) require at least one high
11702 register in a narrow non flag setting add. */
11703 if (Rd
> 7 || Rn
> 7
11704 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11705 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11712 inst
.instruction
= T_OPCODE_ADD_HI
;
11713 inst
.instruction
|= (Rd
& 8) << 4;
11714 inst
.instruction
|= (Rd
& 7);
11715 inst
.instruction
|= Rn
<< 3;
11721 constraint (Rd
== REG_PC
, BAD_PC
);
11722 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11723 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11724 constraint (Rs
== REG_PC
, BAD_PC
);
11725 reject_bad_reg (Rn
);
11727 /* If we get here, it can't be done in 16 bits. */
11728 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11729 _("shift must be constant"));
11730 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11731 inst
.instruction
|= Rd
<< 8;
11732 inst
.instruction
|= Rs
<< 16;
11733 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11734 _("shift value over 3 not allowed in thumb mode"));
11735 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11736 _("only LSL shift allowed in thumb mode"));
11737 encode_thumb32_shifted_operand (2);
11742 constraint (inst
.instruction
== T_MNEM_adds
11743 || inst
.instruction
== T_MNEM_subs
,
11746 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11748 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11749 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11752 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11753 ? 0x0000 : 0x8000);
11754 inst
.instruction
|= (Rd
<< 4) | Rs
;
11755 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11759 Rn
= inst
.operands
[2].reg
;
11760 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11762 /* We now have Rd, Rs, and Rn set to registers. */
11763 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11765 /* Can't do this for SUB. */
11766 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11767 inst
.instruction
= T_OPCODE_ADD_HI
;
11768 inst
.instruction
|= (Rd
& 8) << 4;
11769 inst
.instruction
|= (Rd
& 7);
11771 inst
.instruction
|= Rn
<< 3;
11773 inst
.instruction
|= Rs
<< 3;
11775 constraint (1, _("dest must overlap one source register"));
11779 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11780 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11781 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11791 Rd
= inst
.operands
[0].reg
;
11792 reject_bad_reg (Rd
);
11794 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11796 /* Defer to section relaxation. */
11797 inst
.relax
= inst
.instruction
;
11798 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11799 inst
.instruction
|= Rd
<< 4;
11801 else if (unified_syntax
&& inst
.size_req
!= 2)
11803 /* Generate a 32-bit opcode. */
11804 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11805 inst
.instruction
|= Rd
<< 8;
11806 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11807 inst
.relocs
[0].pc_rel
= 1;
11811 /* Generate a 16-bit opcode. */
11812 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11813 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11814 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11815 inst
.relocs
[0].pc_rel
= 1;
11816 inst
.instruction
|= Rd
<< 4;
11819 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11820 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11821 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11822 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11823 inst
.relocs
[0].exp
.X_add_number
+= 1;
11826 /* Arithmetic instructions for which there is just one 16-bit
11827 instruction encoding, and it allows only two low registers.
11828 For maximal compatibility with ARM syntax, we allow three register
11829 operands even when Thumb-32 instructions are not available, as long
11830 as the first two are identical. For instance, both "sbc r0,r1" and
11831 "sbc r0,r0,r1" are allowed. */
11837 Rd
= inst
.operands
[0].reg
;
11838 Rs
= (inst
.operands
[1].present
11839 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11840 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11841 Rn
= inst
.operands
[2].reg
;
11843 reject_bad_reg (Rd
);
11844 reject_bad_reg (Rs
);
11845 if (inst
.operands
[2].isreg
)
11846 reject_bad_reg (Rn
);
11848 if (unified_syntax
)
11850 if (!inst
.operands
[2].isreg
)
11852 /* For an immediate, we always generate a 32-bit opcode;
11853 section relaxation will shrink it later if possible. */
11854 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11855 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11856 inst
.instruction
|= Rd
<< 8;
11857 inst
.instruction
|= Rs
<< 16;
11858 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11862 bfd_boolean narrow
;
11864 /* See if we can do this with a 16-bit instruction. */
11865 if (THUMB_SETS_FLAGS (inst
.instruction
))
11866 narrow
= !in_pred_block ();
11868 narrow
= in_pred_block ();
11870 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11872 if (inst
.operands
[2].shifted
)
11874 if (inst
.size_req
== 4)
11880 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11881 inst
.instruction
|= Rd
;
11882 inst
.instruction
|= Rn
<< 3;
11886 /* If we get here, it can't be done in 16 bits. */
11887 constraint (inst
.operands
[2].shifted
11888 && inst
.operands
[2].immisreg
,
11889 _("shift must be constant"));
11890 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11891 inst
.instruction
|= Rd
<< 8;
11892 inst
.instruction
|= Rs
<< 16;
11893 encode_thumb32_shifted_operand (2);
11898 /* On its face this is a lie - the instruction does set the
11899 flags. However, the only supported mnemonic in this mode
11900 says it doesn't. */
11901 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11903 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11904 _("unshifted register required"));
11905 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11906 constraint (Rd
!= Rs
,
11907 _("dest and source1 must be the same register"));
11909 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11910 inst
.instruction
|= Rd
;
11911 inst
.instruction
|= Rn
<< 3;
11915 /* Similarly, but for instructions where the arithmetic operation is
11916 commutative, so we can allow either of them to be different from
11917 the destination operand in a 16-bit instruction. For instance, all
11918 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11925 Rd
= inst
.operands
[0].reg
;
11926 Rs
= (inst
.operands
[1].present
11927 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11928 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11929 Rn
= inst
.operands
[2].reg
;
11931 reject_bad_reg (Rd
);
11932 reject_bad_reg (Rs
);
11933 if (inst
.operands
[2].isreg
)
11934 reject_bad_reg (Rn
);
11936 if (unified_syntax
)
11938 if (!inst
.operands
[2].isreg
)
11940 /* For an immediate, we always generate a 32-bit opcode;
11941 section relaxation will shrink it later if possible. */
11942 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11943 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11944 inst
.instruction
|= Rd
<< 8;
11945 inst
.instruction
|= Rs
<< 16;
11946 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11950 bfd_boolean narrow
;
11952 /* See if we can do this with a 16-bit instruction. */
11953 if (THUMB_SETS_FLAGS (inst
.instruction
))
11954 narrow
= !in_pred_block ();
11956 narrow
= in_pred_block ();
11958 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11960 if (inst
.operands
[2].shifted
)
11962 if (inst
.size_req
== 4)
11969 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11970 inst
.instruction
|= Rd
;
11971 inst
.instruction
|= Rn
<< 3;
11976 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11977 inst
.instruction
|= Rd
;
11978 inst
.instruction
|= Rs
<< 3;
11983 /* If we get here, it can't be done in 16 bits. */
11984 constraint (inst
.operands
[2].shifted
11985 && inst
.operands
[2].immisreg
,
11986 _("shift must be constant"));
11987 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11988 inst
.instruction
|= Rd
<< 8;
11989 inst
.instruction
|= Rs
<< 16;
11990 encode_thumb32_shifted_operand (2);
11995 /* On its face this is a lie - the instruction does set the
11996 flags. However, the only supported mnemonic in this mode
11997 says it doesn't. */
11998 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12000 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
12001 _("unshifted register required"));
12002 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
12004 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12005 inst
.instruction
|= Rd
;
12008 inst
.instruction
|= Rn
<< 3;
12010 inst
.instruction
|= Rs
<< 3;
12012 constraint (1, _("dest must overlap one source register"));
12020 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
12021 constraint (msb
> 32, _("bit-field extends past end of register"));
12022 /* The instruction encoding stores the LSB and MSB,
12023 not the LSB and width. */
12024 Rd
= inst
.operands
[0].reg
;
12025 reject_bad_reg (Rd
);
12026 inst
.instruction
|= Rd
<< 8;
12027 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
12028 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
12029 inst
.instruction
|= msb
- 1;
12038 Rd
= inst
.operands
[0].reg
;
12039 reject_bad_reg (Rd
);
12041 /* #0 in second position is alternative syntax for bfc, which is
12042 the same instruction but with REG_PC in the Rm field. */
12043 if (!inst
.operands
[1].isreg
)
12047 Rn
= inst
.operands
[1].reg
;
12048 reject_bad_reg (Rn
);
12051 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
12052 constraint (msb
> 32, _("bit-field extends past end of register"));
12053 /* The instruction encoding stores the LSB and MSB,
12054 not the LSB and width. */
12055 inst
.instruction
|= Rd
<< 8;
12056 inst
.instruction
|= Rn
<< 16;
12057 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12058 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12059 inst
.instruction
|= msb
- 1;
12067 Rd
= inst
.operands
[0].reg
;
12068 Rn
= inst
.operands
[1].reg
;
12070 reject_bad_reg (Rd
);
12071 reject_bad_reg (Rn
);
12073 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
12074 _("bit-field extends past end of register"));
12075 inst
.instruction
|= Rd
<< 8;
12076 inst
.instruction
|= Rn
<< 16;
12077 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12078 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12079 inst
.instruction
|= inst
.operands
[3].imm
- 1;
12082 /* ARM V5 Thumb BLX (argument parse)
12083 BLX <target_addr> which is BLX(1)
12084 BLX <Rm> which is BLX(2)
12085 Unfortunately, there are two different opcodes for this mnemonic.
12086 So, the insns[].value is not used, and the code here zaps values
12087 into inst.instruction.
12089 ??? How to take advantage of the additional two bits of displacement
12090 available in Thumb32 mode? Need new relocation? */
12095 set_pred_insn_type_last ();
12097 if (inst
.operands
[0].isreg
)
12099 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12100 /* We have a register, so this is BLX(2). */
12101 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12105 /* No register. This must be BLX(1). */
12106 inst
.instruction
= 0xf000e800;
12107 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12116 bfd_reloc_code_real_type reloc
;
12119 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12121 if (in_pred_block ())
12123 /* Conditional branches inside IT blocks are encoded as unconditional
12125 cond
= COND_ALWAYS
;
12130 if (cond
!= COND_ALWAYS
)
12131 opcode
= T_MNEM_bcond
;
12133 opcode
= inst
.instruction
;
12136 && (inst
.size_req
== 4
12137 || (inst
.size_req
!= 2
12138 && (inst
.operands
[0].hasreloc
12139 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12141 inst
.instruction
= THUMB_OP32(opcode
);
12142 if (cond
== COND_ALWAYS
)
12143 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12146 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12147 _("selected architecture does not support "
12148 "wide conditional branch instruction"));
12150 gas_assert (cond
!= 0xF);
12151 inst
.instruction
|= cond
<< 22;
12152 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12157 inst
.instruction
= THUMB_OP16(opcode
);
12158 if (cond
== COND_ALWAYS
)
12159 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12162 inst
.instruction
|= cond
<< 8;
12163 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12165 /* Allow section relaxation. */
12166 if (unified_syntax
&& inst
.size_req
!= 2)
12167 inst
.relax
= opcode
;
12169 inst
.relocs
[0].type
= reloc
;
12170 inst
.relocs
[0].pc_rel
= 1;
12173 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12174 between the two is the maximum immediate allowed - which is passed in
12177 do_t_bkpt_hlt1 (int range
)
12179 constraint (inst
.cond
!= COND_ALWAYS
,
12180 _("instruction is always unconditional"));
12181 if (inst
.operands
[0].present
)
12183 constraint (inst
.operands
[0].imm
> range
,
12184 _("immediate value out of range"));
12185 inst
.instruction
|= inst
.operands
[0].imm
;
12188 set_pred_insn_type (NEUTRAL_IT_INSN
);
12194 do_t_bkpt_hlt1 (63);
12200 do_t_bkpt_hlt1 (255);
12204 do_t_branch23 (void)
12206 set_pred_insn_type_last ();
12207 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12209 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12210 this file. We used to simply ignore the PLT reloc type here --
12211 the branch encoding is now needed to deal with TLSCALL relocs.
12212 So if we see a PLT reloc now, put it back to how it used to be to
12213 keep the preexisting behaviour. */
12214 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12215 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12217 #if defined(OBJ_COFF)
12218 /* If the destination of the branch is a defined symbol which does not have
12219 the THUMB_FUNC attribute, then we must be calling a function which has
12220 the (interfacearm) attribute. We look for the Thumb entry point to that
12221 function and change the branch to refer to that function instead. */
12222 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12223 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12224 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12225 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12226 inst
.relocs
[0].exp
.X_add_symbol
12227 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12234 set_pred_insn_type_last ();
12235 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12236 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12237 should cause the alignment to be checked once it is known. This is
12238 because BX PC only works if the instruction is word aligned. */
12246 set_pred_insn_type_last ();
12247 Rm
= inst
.operands
[0].reg
;
12248 reject_bad_reg (Rm
);
12249 inst
.instruction
|= Rm
<< 16;
12258 Rd
= inst
.operands
[0].reg
;
12259 Rm
= inst
.operands
[1].reg
;
12261 reject_bad_reg (Rd
);
12262 reject_bad_reg (Rm
);
12264 inst
.instruction
|= Rd
<< 8;
12265 inst
.instruction
|= Rm
<< 16;
12266 inst
.instruction
|= Rm
;
12269 /* For the Armv8.1-M conditional instructions. */
12273 unsigned Rd
, Rn
, Rm
;
12276 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12278 Rd
= inst
.operands
[0].reg
;
12279 switch (inst
.instruction
)
12285 Rn
= inst
.operands
[1].reg
;
12286 Rm
= inst
.operands
[2].reg
;
12287 cond
= inst
.operands
[3].imm
;
12288 constraint (Rn
== REG_SP
, BAD_SP
);
12289 constraint (Rm
== REG_SP
, BAD_SP
);
12295 Rn
= inst
.operands
[1].reg
;
12296 cond
= inst
.operands
[2].imm
;
12297 /* Invert the last bit to invert the cond. */
12298 cond
= TOGGLE_BIT (cond
, 0);
12299 constraint (Rn
== REG_SP
, BAD_SP
);
12305 cond
= inst
.operands
[1].imm
;
12306 /* Invert the last bit to invert the cond. */
12307 cond
= TOGGLE_BIT (cond
, 0);
12315 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12316 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12317 inst
.instruction
|= Rd
<< 8;
12318 inst
.instruction
|= Rn
<< 16;
12319 inst
.instruction
|= Rm
;
12320 inst
.instruction
|= cond
<< 4;
12326 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12332 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12333 inst
.instruction
|= inst
.operands
[0].imm
;
12339 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12341 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12342 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12344 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12345 inst
.instruction
= 0xf3af8000;
12346 inst
.instruction
|= imod
<< 9;
12347 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12348 if (inst
.operands
[1].present
)
12349 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12353 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12354 && (inst
.operands
[0].imm
& 4),
12355 _("selected processor does not support 'A' form "
12356 "of this instruction"));
12357 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12358 _("Thumb does not support the 2-argument "
12359 "form of this instruction"));
12360 inst
.instruction
|= inst
.operands
[0].imm
;
12364 /* THUMB CPY instruction (argument parse). */
12369 if (inst
.size_req
== 4)
12371 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12372 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12373 inst
.instruction
|= inst
.operands
[1].reg
;
12377 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12378 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12379 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12386 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12387 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12388 inst
.instruction
|= inst
.operands
[0].reg
;
12389 inst
.relocs
[0].pc_rel
= 1;
12390 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12396 inst
.instruction
|= inst
.operands
[0].imm
;
12402 unsigned Rd
, Rn
, Rm
;
12404 Rd
= inst
.operands
[0].reg
;
12405 Rn
= (inst
.operands
[1].present
12406 ? inst
.operands
[1].reg
: Rd
);
12407 Rm
= inst
.operands
[2].reg
;
12409 reject_bad_reg (Rd
);
12410 reject_bad_reg (Rn
);
12411 reject_bad_reg (Rm
);
12413 inst
.instruction
|= Rd
<< 8;
12414 inst
.instruction
|= Rn
<< 16;
12415 inst
.instruction
|= Rm
;
12421 if (unified_syntax
&& inst
.size_req
== 4)
12422 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12424 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12430 unsigned int cond
= inst
.operands
[0].imm
;
12432 set_pred_insn_type (IT_INSN
);
12433 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12434 now_pred
.cc
= cond
;
12435 now_pred
.warn_deprecated
= FALSE
;
12436 now_pred
.type
= SCALAR_PRED
;
12438 /* If the condition is a negative condition, invert the mask. */
12439 if ((cond
& 0x1) == 0x0)
12441 unsigned int mask
= inst
.instruction
& 0x000f;
12443 if ((mask
& 0x7) == 0)
12445 /* No conversion needed. */
12446 now_pred
.block_length
= 1;
12448 else if ((mask
& 0x3) == 0)
12451 now_pred
.block_length
= 2;
12453 else if ((mask
& 0x1) == 0)
12456 now_pred
.block_length
= 3;
12461 now_pred
.block_length
= 4;
12464 inst
.instruction
&= 0xfff0;
12465 inst
.instruction
|= mask
;
12468 inst
.instruction
|= cond
<< 4;
12471 /* Helper function used for both push/pop and ldm/stm. */
12473 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12474 bfd_boolean writeback
)
12476 bfd_boolean load
, store
;
12478 gas_assert (base
!= -1 || !do_io
);
12479 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12480 store
= do_io
&& !load
;
12482 if (mask
& (1 << 13))
12483 inst
.error
= _("SP not allowed in register list");
12485 if (do_io
&& (mask
& (1 << base
)) != 0
12487 inst
.error
= _("having the base register in the register list when "
12488 "using write back is UNPREDICTABLE");
12492 if (mask
& (1 << 15))
12494 if (mask
& (1 << 14))
12495 inst
.error
= _("LR and PC should not both be in register list");
12497 set_pred_insn_type_last ();
12502 if (mask
& (1 << 15))
12503 inst
.error
= _("PC not allowed in register list");
12506 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12508 /* Single register transfers implemented as str/ldr. */
12511 if (inst
.instruction
& (1 << 23))
12512 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12514 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12518 if (inst
.instruction
& (1 << 23))
12519 inst
.instruction
= 0x00800000; /* ia -> [base] */
12521 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12524 inst
.instruction
|= 0xf8400000;
12526 inst
.instruction
|= 0x00100000;
12528 mask
= ffs (mask
) - 1;
12531 else if (writeback
)
12532 inst
.instruction
|= WRITE_BACK
;
12534 inst
.instruction
|= mask
;
12536 inst
.instruction
|= base
<< 16;
12542 /* This really doesn't seem worth it. */
12543 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12544 _("expression too complex"));
12545 constraint (inst
.operands
[1].writeback
,
12546 _("Thumb load/store multiple does not support {reglist}^"));
12548 if (unified_syntax
)
12550 bfd_boolean narrow
;
12554 /* See if we can use a 16-bit instruction. */
12555 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12556 && inst
.size_req
!= 4
12557 && !(inst
.operands
[1].imm
& ~0xff))
12559 mask
= 1 << inst
.operands
[0].reg
;
12561 if (inst
.operands
[0].reg
<= 7)
12563 if (inst
.instruction
== T_MNEM_stmia
12564 ? inst
.operands
[0].writeback
12565 : (inst
.operands
[0].writeback
12566 == !(inst
.operands
[1].imm
& mask
)))
12568 if (inst
.instruction
== T_MNEM_stmia
12569 && (inst
.operands
[1].imm
& mask
)
12570 && (inst
.operands
[1].imm
& (mask
- 1)))
12571 as_warn (_("value stored for r%d is UNKNOWN"),
12572 inst
.operands
[0].reg
);
12574 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12575 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12576 inst
.instruction
|= inst
.operands
[1].imm
;
12579 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12581 /* This means 1 register in reg list one of 3 situations:
12582 1. Instruction is stmia, but without writeback.
12583 2. lmdia without writeback, but with Rn not in
12585 3. ldmia with writeback, but with Rn in reglist.
12586 Case 3 is UNPREDICTABLE behaviour, so we handle
12587 case 1 and 2 which can be converted into a 16-bit
12588 str or ldr. The SP cases are handled below. */
12589 unsigned long opcode
;
12590 /* First, record an error for Case 3. */
12591 if (inst
.operands
[1].imm
& mask
12592 && inst
.operands
[0].writeback
)
12594 _("having the base register in the register list when "
12595 "using write back is UNPREDICTABLE");
12597 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12599 inst
.instruction
= THUMB_OP16 (opcode
);
12600 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12601 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12605 else if (inst
.operands
[0] .reg
== REG_SP
)
12607 if (inst
.operands
[0].writeback
)
12610 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12611 ? T_MNEM_push
: T_MNEM_pop
);
12612 inst
.instruction
|= inst
.operands
[1].imm
;
12615 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12618 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12619 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12620 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12628 if (inst
.instruction
< 0xffff)
12629 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12631 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12632 inst
.operands
[1].imm
,
12633 inst
.operands
[0].writeback
);
12638 constraint (inst
.operands
[0].reg
> 7
12639 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12640 constraint (inst
.instruction
!= T_MNEM_ldmia
12641 && inst
.instruction
!= T_MNEM_stmia
,
12642 _("Thumb-2 instruction only valid in unified syntax"));
12643 if (inst
.instruction
== T_MNEM_stmia
)
12645 if (!inst
.operands
[0].writeback
)
12646 as_warn (_("this instruction will write back the base register"));
12647 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12648 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12649 as_warn (_("value stored for r%d is UNKNOWN"),
12650 inst
.operands
[0].reg
);
12654 if (!inst
.operands
[0].writeback
12655 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12656 as_warn (_("this instruction will write back the base register"));
12657 else if (inst
.operands
[0].writeback
12658 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12659 as_warn (_("this instruction will not write back the base register"));
12662 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12663 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12664 inst
.instruction
|= inst
.operands
[1].imm
;
12671 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12672 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12673 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12674 || inst
.operands
[1].negative
,
12677 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12679 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12680 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12681 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12687 if (!inst
.operands
[1].present
)
12689 constraint (inst
.operands
[0].reg
== REG_LR
,
12690 _("r14 not allowed as first register "
12691 "when second register is omitted"));
12692 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12694 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12697 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12698 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12699 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12705 unsigned long opcode
;
12708 if (inst
.operands
[0].isreg
12709 && !inst
.operands
[0].preind
12710 && inst
.operands
[0].reg
== REG_PC
)
12711 set_pred_insn_type_last ();
12713 opcode
= inst
.instruction
;
12714 if (unified_syntax
)
12716 if (!inst
.operands
[1].isreg
)
12718 if (opcode
<= 0xffff)
12719 inst
.instruction
= THUMB_OP32 (opcode
);
12720 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12723 if (inst
.operands
[1].isreg
12724 && !inst
.operands
[1].writeback
12725 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12726 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12727 && opcode
<= 0xffff
12728 && inst
.size_req
!= 4)
12730 /* Insn may have a 16-bit form. */
12731 Rn
= inst
.operands
[1].reg
;
12732 if (inst
.operands
[1].immisreg
)
12734 inst
.instruction
= THUMB_OP16 (opcode
);
12736 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12738 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12739 reject_bad_reg (inst
.operands
[1].imm
);
12741 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12742 && opcode
!= T_MNEM_ldrsb
)
12743 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12744 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12751 if (inst
.relocs
[0].pc_rel
)
12752 opcode
= T_MNEM_ldr_pc2
;
12754 opcode
= T_MNEM_ldr_pc
;
12758 if (opcode
== T_MNEM_ldr
)
12759 opcode
= T_MNEM_ldr_sp
;
12761 opcode
= T_MNEM_str_sp
;
12763 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12767 inst
.instruction
= inst
.operands
[0].reg
;
12768 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12770 inst
.instruction
|= THUMB_OP16 (opcode
);
12771 if (inst
.size_req
== 2)
12772 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12774 inst
.relax
= opcode
;
12778 /* Definitely a 32-bit variant. */
12780 /* Warning for Erratum 752419. */
12781 if (opcode
== T_MNEM_ldr
12782 && inst
.operands
[0].reg
== REG_SP
12783 && inst
.operands
[1].writeback
== 1
12784 && !inst
.operands
[1].immisreg
)
12786 if (no_cpu_selected ()
12787 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12788 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12789 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12790 as_warn (_("This instruction may be unpredictable "
12791 "if executed on M-profile cores "
12792 "with interrupts enabled."));
12795 /* Do some validations regarding addressing modes. */
12796 if (inst
.operands
[1].immisreg
)
12797 reject_bad_reg (inst
.operands
[1].imm
);
12799 constraint (inst
.operands
[1].writeback
== 1
12800 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12803 inst
.instruction
= THUMB_OP32 (opcode
);
12804 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12805 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12806 check_ldr_r15_aligned ();
12810 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12812 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12814 /* Only [Rn,Rm] is acceptable. */
12815 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12816 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12817 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12818 || inst
.operands
[1].negative
,
12819 _("Thumb does not support this addressing mode"));
12820 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12824 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12825 if (!inst
.operands
[1].isreg
)
12826 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12829 constraint (!inst
.operands
[1].preind
12830 || inst
.operands
[1].shifted
12831 || inst
.operands
[1].writeback
,
12832 _("Thumb does not support this addressing mode"));
12833 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12835 constraint (inst
.instruction
& 0x0600,
12836 _("byte or halfword not valid for base register"));
12837 constraint (inst
.operands
[1].reg
== REG_PC
12838 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12839 _("r15 based store not allowed"));
12840 constraint (inst
.operands
[1].immisreg
,
12841 _("invalid base register for register offset"));
12843 if (inst
.operands
[1].reg
== REG_PC
)
12844 inst
.instruction
= T_OPCODE_LDR_PC
;
12845 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12846 inst
.instruction
= T_OPCODE_LDR_SP
;
12848 inst
.instruction
= T_OPCODE_STR_SP
;
12850 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12851 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12855 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12856 if (!inst
.operands
[1].immisreg
)
12858 /* Immediate offset. */
12859 inst
.instruction
|= inst
.operands
[0].reg
;
12860 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12861 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12865 /* Register offset. */
12866 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12867 constraint (inst
.operands
[1].negative
,
12868 _("Thumb does not support this addressing mode"));
12871 switch (inst
.instruction
)
12873 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12874 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12875 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12876 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12877 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12878 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12879 case 0x5600 /* ldrsb */:
12880 case 0x5e00 /* ldrsh */: break;
12884 inst
.instruction
|= inst
.operands
[0].reg
;
12885 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12886 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12892 if (!inst
.operands
[1].present
)
12894 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12895 constraint (inst
.operands
[0].reg
== REG_LR
,
12896 _("r14 not allowed here"));
12897 constraint (inst
.operands
[0].reg
== REG_R12
,
12898 _("r12 not allowed here"));
12901 if (inst
.operands
[2].writeback
12902 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12903 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12904 as_warn (_("base register written back, and overlaps "
12905 "one of transfer registers"));
12907 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12908 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12909 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12916 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12922 unsigned Rd
, Rn
, Rm
, Ra
;
12924 Rd
= inst
.operands
[0].reg
;
12925 Rn
= inst
.operands
[1].reg
;
12926 Rm
= inst
.operands
[2].reg
;
12927 Ra
= inst
.operands
[3].reg
;
12929 reject_bad_reg (Rd
);
12930 reject_bad_reg (Rn
);
12931 reject_bad_reg (Rm
);
12932 reject_bad_reg (Ra
);
12934 inst
.instruction
|= Rd
<< 8;
12935 inst
.instruction
|= Rn
<< 16;
12936 inst
.instruction
|= Rm
;
12937 inst
.instruction
|= Ra
<< 12;
12943 unsigned RdLo
, RdHi
, Rn
, Rm
;
12945 RdLo
= inst
.operands
[0].reg
;
12946 RdHi
= inst
.operands
[1].reg
;
12947 Rn
= inst
.operands
[2].reg
;
12948 Rm
= inst
.operands
[3].reg
;
12950 reject_bad_reg (RdLo
);
12951 reject_bad_reg (RdHi
);
12952 reject_bad_reg (Rn
);
12953 reject_bad_reg (Rm
);
12955 inst
.instruction
|= RdLo
<< 12;
12956 inst
.instruction
|= RdHi
<< 8;
12957 inst
.instruction
|= Rn
<< 16;
12958 inst
.instruction
|= Rm
;
12962 do_t_mov_cmp (void)
12966 Rn
= inst
.operands
[0].reg
;
12967 Rm
= inst
.operands
[1].reg
;
12970 set_pred_insn_type_last ();
12972 if (unified_syntax
)
12974 int r0off
= (inst
.instruction
== T_MNEM_mov
12975 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12976 unsigned long opcode
;
12977 bfd_boolean narrow
;
12978 bfd_boolean low_regs
;
12980 low_regs
= (Rn
<= 7 && Rm
<= 7);
12981 opcode
= inst
.instruction
;
12982 if (in_pred_block ())
12983 narrow
= opcode
!= T_MNEM_movs
;
12985 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12986 if (inst
.size_req
== 4
12987 || inst
.operands
[1].shifted
)
12990 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12991 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12992 && !inst
.operands
[1].shifted
12996 inst
.instruction
= T2_SUBS_PC_LR
;
13000 if (opcode
== T_MNEM_cmp
)
13002 constraint (Rn
== REG_PC
, BAD_PC
);
13005 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
13007 warn_deprecated_sp (Rm
);
13008 /* R15 was documented as a valid choice for Rm in ARMv6,
13009 but as UNPREDICTABLE in ARMv7. ARM's proprietary
13010 tools reject R15, so we do too. */
13011 constraint (Rm
== REG_PC
, BAD_PC
);
13014 reject_bad_reg (Rm
);
13016 else if (opcode
== T_MNEM_mov
13017 || opcode
== T_MNEM_movs
)
13019 if (inst
.operands
[1].isreg
)
13021 if (opcode
== T_MNEM_movs
)
13023 reject_bad_reg (Rn
);
13024 reject_bad_reg (Rm
);
13028 /* This is mov.n. */
13029 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
13030 && (Rm
== REG_SP
|| Rm
== REG_PC
))
13032 as_tsktsk (_("Use of r%u as a source register is "
13033 "deprecated when r%u is the destination "
13034 "register."), Rm
, Rn
);
13039 /* This is mov.w. */
13040 constraint (Rn
== REG_PC
, BAD_PC
);
13041 constraint (Rm
== REG_PC
, BAD_PC
);
13042 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13043 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
13047 reject_bad_reg (Rn
);
13050 if (!inst
.operands
[1].isreg
)
13052 /* Immediate operand. */
13053 if (!in_pred_block () && opcode
== T_MNEM_mov
)
13055 if (low_regs
&& narrow
)
13057 inst
.instruction
= THUMB_OP16 (opcode
);
13058 inst
.instruction
|= Rn
<< 8;
13059 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13060 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
13062 if (inst
.size_req
== 2)
13063 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13065 inst
.relax
= opcode
;
13070 constraint ((inst
.relocs
[0].type
13071 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
13072 && (inst
.relocs
[0].type
13073 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
13074 THUMB1_RELOC_ONLY
);
13076 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13077 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13078 inst
.instruction
|= Rn
<< r0off
;
13079 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13082 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
13083 && (inst
.instruction
== T_MNEM_mov
13084 || inst
.instruction
== T_MNEM_movs
))
13086 /* Register shifts are encoded as separate shift instructions. */
13087 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
13089 if (in_pred_block ())
13094 if (inst
.size_req
== 4)
13097 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13103 switch (inst
.operands
[1].shift_kind
)
13106 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13109 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13112 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13115 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13121 inst
.instruction
= opcode
;
13124 inst
.instruction
|= Rn
;
13125 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13130 inst
.instruction
|= CONDS_BIT
;
13132 inst
.instruction
|= Rn
<< 8;
13133 inst
.instruction
|= Rm
<< 16;
13134 inst
.instruction
|= inst
.operands
[1].imm
;
13139 /* Some mov with immediate shift have narrow variants.
13140 Register shifts are handled above. */
13141 if (low_regs
&& inst
.operands
[1].shifted
13142 && (inst
.instruction
== T_MNEM_mov
13143 || inst
.instruction
== T_MNEM_movs
))
13145 if (in_pred_block ())
13146 narrow
= (inst
.instruction
== T_MNEM_mov
);
13148 narrow
= (inst
.instruction
== T_MNEM_movs
);
13153 switch (inst
.operands
[1].shift_kind
)
13155 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13156 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13157 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13158 default: narrow
= FALSE
; break;
13164 inst
.instruction
|= Rn
;
13165 inst
.instruction
|= Rm
<< 3;
13166 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13170 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13171 inst
.instruction
|= Rn
<< r0off
;
13172 encode_thumb32_shifted_operand (1);
13176 switch (inst
.instruction
)
13179 /* In v4t or v5t a move of two lowregs produces unpredictable
13180 results. Don't allow this. */
13183 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13184 "MOV Rd, Rs with two low registers is not "
13185 "permitted on this architecture");
13186 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13190 inst
.instruction
= T_OPCODE_MOV_HR
;
13191 inst
.instruction
|= (Rn
& 0x8) << 4;
13192 inst
.instruction
|= (Rn
& 0x7);
13193 inst
.instruction
|= Rm
<< 3;
13197 /* We know we have low registers at this point.
13198 Generate LSLS Rd, Rs, #0. */
13199 inst
.instruction
= T_OPCODE_LSL_I
;
13200 inst
.instruction
|= Rn
;
13201 inst
.instruction
|= Rm
<< 3;
13207 inst
.instruction
= T_OPCODE_CMP_LR
;
13208 inst
.instruction
|= Rn
;
13209 inst
.instruction
|= Rm
<< 3;
13213 inst
.instruction
= T_OPCODE_CMP_HR
;
13214 inst
.instruction
|= (Rn
& 0x8) << 4;
13215 inst
.instruction
|= (Rn
& 0x7);
13216 inst
.instruction
|= Rm
<< 3;
13223 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13225 /* PR 10443: Do not silently ignore shifted operands. */
13226 constraint (inst
.operands
[1].shifted
,
13227 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13229 if (inst
.operands
[1].isreg
)
13231 if (Rn
< 8 && Rm
< 8)
13233 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13234 since a MOV instruction produces unpredictable results. */
13235 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13236 inst
.instruction
= T_OPCODE_ADD_I3
;
13238 inst
.instruction
= T_OPCODE_CMP_LR
;
13240 inst
.instruction
|= Rn
;
13241 inst
.instruction
|= Rm
<< 3;
13245 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13246 inst
.instruction
= T_OPCODE_MOV_HR
;
13248 inst
.instruction
= T_OPCODE_CMP_HR
;
13254 constraint (Rn
> 7,
13255 _("only lo regs allowed with immediate"));
13256 inst
.instruction
|= Rn
<< 8;
13257 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13268 top
= (inst
.instruction
& 0x00800000) != 0;
13269 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13271 constraint (top
, _(":lower16: not allowed in this instruction"));
13272 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13274 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13276 constraint (!top
, _(":upper16: not allowed in this instruction"));
13277 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13280 Rd
= inst
.operands
[0].reg
;
13281 reject_bad_reg (Rd
);
13283 inst
.instruction
|= Rd
<< 8;
13284 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13286 imm
= inst
.relocs
[0].exp
.X_add_number
;
13287 inst
.instruction
|= (imm
& 0xf000) << 4;
13288 inst
.instruction
|= (imm
& 0x0800) << 15;
13289 inst
.instruction
|= (imm
& 0x0700) << 4;
13290 inst
.instruction
|= (imm
& 0x00ff);
13295 do_t_mvn_tst (void)
13299 Rn
= inst
.operands
[0].reg
;
13300 Rm
= inst
.operands
[1].reg
;
13302 if (inst
.instruction
== T_MNEM_cmp
13303 || inst
.instruction
== T_MNEM_cmn
)
13304 constraint (Rn
== REG_PC
, BAD_PC
);
13306 reject_bad_reg (Rn
);
13307 reject_bad_reg (Rm
);
13309 if (unified_syntax
)
13311 int r0off
= (inst
.instruction
== T_MNEM_mvn
13312 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13313 bfd_boolean narrow
;
13315 if (inst
.size_req
== 4
13316 || inst
.instruction
> 0xffff
13317 || inst
.operands
[1].shifted
13318 || Rn
> 7 || Rm
> 7)
13320 else if (inst
.instruction
== T_MNEM_cmn
13321 || inst
.instruction
== T_MNEM_tst
)
13323 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13324 narrow
= !in_pred_block ();
13326 narrow
= in_pred_block ();
13328 if (!inst
.operands
[1].isreg
)
13330 /* For an immediate, we always generate a 32-bit opcode;
13331 section relaxation will shrink it later if possible. */
13332 if (inst
.instruction
< 0xffff)
13333 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13334 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13335 inst
.instruction
|= Rn
<< r0off
;
13336 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13340 /* See if we can do this with a 16-bit instruction. */
13343 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13344 inst
.instruction
|= Rn
;
13345 inst
.instruction
|= Rm
<< 3;
13349 constraint (inst
.operands
[1].shifted
13350 && inst
.operands
[1].immisreg
,
13351 _("shift must be constant"));
13352 if (inst
.instruction
< 0xffff)
13353 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13354 inst
.instruction
|= Rn
<< r0off
;
13355 encode_thumb32_shifted_operand (1);
13361 constraint (inst
.instruction
> 0xffff
13362 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13363 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13364 _("unshifted register required"));
13365 constraint (Rn
> 7 || Rm
> 7,
13368 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13369 inst
.instruction
|= Rn
;
13370 inst
.instruction
|= Rm
<< 3;
13379 if (do_vfp_nsyn_mrs () == SUCCESS
)
13382 Rd
= inst
.operands
[0].reg
;
13383 reject_bad_reg (Rd
);
13384 inst
.instruction
|= Rd
<< 8;
13386 if (inst
.operands
[1].isreg
)
13388 unsigned br
= inst
.operands
[1].reg
;
13389 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13390 as_bad (_("bad register for mrs"));
13392 inst
.instruction
|= br
& (0xf << 16);
13393 inst
.instruction
|= (br
& 0x300) >> 4;
13394 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13398 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13400 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13402 /* PR gas/12698: The constraint is only applied for m_profile.
13403 If the user has specified -march=all, we want to ignore it as
13404 we are building for any CPU type, including non-m variants. */
13405 bfd_boolean m_profile
=
13406 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13407 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13408 "not support requested special purpose register"));
13411 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13413 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13414 _("'APSR', 'CPSR' or 'SPSR' expected"));
13416 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13417 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13418 inst
.instruction
|= 0xf0000;
13428 if (do_vfp_nsyn_msr () == SUCCESS
)
13431 constraint (!inst
.operands
[1].isreg
,
13432 _("Thumb encoding does not support an immediate here"));
13434 if (inst
.operands
[0].isreg
)
13435 flags
= (int)(inst
.operands
[0].reg
);
13437 flags
= inst
.operands
[0].imm
;
13439 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13441 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13443 /* PR gas/12698: The constraint is only applied for m_profile.
13444 If the user has specified -march=all, we want to ignore it as
13445 we are building for any CPU type, including non-m variants. */
13446 bfd_boolean m_profile
=
13447 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13448 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13449 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13450 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13451 && bits
!= PSR_f
)) && m_profile
,
13452 _("selected processor does not support requested special "
13453 "purpose register"));
13456 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13457 "requested special purpose register"));
13459 Rn
= inst
.operands
[1].reg
;
13460 reject_bad_reg (Rn
);
13462 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13463 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13464 inst
.instruction
|= (flags
& 0x300) >> 4;
13465 inst
.instruction
|= (flags
& 0xff);
13466 inst
.instruction
|= Rn
<< 16;
13472 bfd_boolean narrow
;
13473 unsigned Rd
, Rn
, Rm
;
13475 if (!inst
.operands
[2].present
)
13476 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13478 Rd
= inst
.operands
[0].reg
;
13479 Rn
= inst
.operands
[1].reg
;
13480 Rm
= inst
.operands
[2].reg
;
13482 if (unified_syntax
)
13484 if (inst
.size_req
== 4
13490 else if (inst
.instruction
== T_MNEM_muls
)
13491 narrow
= !in_pred_block ();
13493 narrow
= in_pred_block ();
13497 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13498 constraint (Rn
> 7 || Rm
> 7,
13505 /* 16-bit MULS/Conditional MUL. */
13506 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13507 inst
.instruction
|= Rd
;
13510 inst
.instruction
|= Rm
<< 3;
13512 inst
.instruction
|= Rn
<< 3;
13514 constraint (1, _("dest must overlap one source register"));
13518 constraint (inst
.instruction
!= T_MNEM_mul
,
13519 _("Thumb-2 MUL must not set flags"));
13521 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13522 inst
.instruction
|= Rd
<< 8;
13523 inst
.instruction
|= Rn
<< 16;
13524 inst
.instruction
|= Rm
<< 0;
13526 reject_bad_reg (Rd
);
13527 reject_bad_reg (Rn
);
13528 reject_bad_reg (Rm
);
13535 unsigned RdLo
, RdHi
, Rn
, Rm
;
13537 RdLo
= inst
.operands
[0].reg
;
13538 RdHi
= inst
.operands
[1].reg
;
13539 Rn
= inst
.operands
[2].reg
;
13540 Rm
= inst
.operands
[3].reg
;
13542 reject_bad_reg (RdLo
);
13543 reject_bad_reg (RdHi
);
13544 reject_bad_reg (Rn
);
13545 reject_bad_reg (Rm
);
13547 inst
.instruction
|= RdLo
<< 12;
13548 inst
.instruction
|= RdHi
<< 8;
13549 inst
.instruction
|= Rn
<< 16;
13550 inst
.instruction
|= Rm
;
13553 as_tsktsk (_("rdhi and rdlo must be different"));
13559 set_pred_insn_type (NEUTRAL_IT_INSN
);
13561 if (unified_syntax
)
13563 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13565 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13566 inst
.instruction
|= inst
.operands
[0].imm
;
13570 /* PR9722: Check for Thumb2 availability before
13571 generating a thumb2 nop instruction. */
13572 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13574 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13575 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13578 inst
.instruction
= 0x46c0;
13583 constraint (inst
.operands
[0].present
,
13584 _("Thumb does not support NOP with hints"));
13585 inst
.instruction
= 0x46c0;
13592 if (unified_syntax
)
13594 bfd_boolean narrow
;
13596 if (THUMB_SETS_FLAGS (inst
.instruction
))
13597 narrow
= !in_pred_block ();
13599 narrow
= in_pred_block ();
13600 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13602 if (inst
.size_req
== 4)
13607 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13608 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13609 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13613 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13614 inst
.instruction
|= inst
.operands
[0].reg
;
13615 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13620 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13622 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13624 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13625 inst
.instruction
|= inst
.operands
[0].reg
;
13626 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13635 Rd
= inst
.operands
[0].reg
;
13636 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13638 reject_bad_reg (Rd
);
13639 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13640 reject_bad_reg (Rn
);
13642 inst
.instruction
|= Rd
<< 8;
13643 inst
.instruction
|= Rn
<< 16;
13645 if (!inst
.operands
[2].isreg
)
13647 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13648 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13654 Rm
= inst
.operands
[2].reg
;
13655 reject_bad_reg (Rm
);
13657 constraint (inst
.operands
[2].shifted
13658 && inst
.operands
[2].immisreg
,
13659 _("shift must be constant"));
13660 encode_thumb32_shifted_operand (2);
13667 unsigned Rd
, Rn
, Rm
;
13669 Rd
= inst
.operands
[0].reg
;
13670 Rn
= inst
.operands
[1].reg
;
13671 Rm
= inst
.operands
[2].reg
;
13673 reject_bad_reg (Rd
);
13674 reject_bad_reg (Rn
);
13675 reject_bad_reg (Rm
);
13677 inst
.instruction
|= Rd
<< 8;
13678 inst
.instruction
|= Rn
<< 16;
13679 inst
.instruction
|= Rm
;
13680 if (inst
.operands
[3].present
)
13682 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13683 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13684 _("expression too complex"));
13685 inst
.instruction
|= (val
& 0x1c) << 10;
13686 inst
.instruction
|= (val
& 0x03) << 6;
13693 if (!inst
.operands
[3].present
)
13697 inst
.instruction
&= ~0x00000020;
13699 /* PR 10168. Swap the Rm and Rn registers. */
13700 Rtmp
= inst
.operands
[1].reg
;
13701 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13702 inst
.operands
[2].reg
= Rtmp
;
13710 if (inst
.operands
[0].immisreg
)
13711 reject_bad_reg (inst
.operands
[0].imm
);
13713 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13717 do_t_push_pop (void)
13721 constraint (inst
.operands
[0].writeback
,
13722 _("push/pop do not support {reglist}^"));
13723 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13724 _("expression too complex"));
13726 mask
= inst
.operands
[0].imm
;
13727 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13728 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13729 else if (inst
.size_req
!= 4
13730 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13731 ? REG_LR
: REG_PC
)))
13733 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13734 inst
.instruction
|= THUMB_PP_PC_LR
;
13735 inst
.instruction
|= mask
& 0xff;
13737 else if (unified_syntax
)
13739 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13740 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13744 inst
.error
= _("invalid register list to push/pop instruction");
13752 if (unified_syntax
)
13753 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13756 inst
.error
= _("invalid register list to push/pop instruction");
13762 do_t_vscclrm (void)
13764 if (inst
.operands
[0].issingle
)
13766 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13767 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13768 inst
.instruction
|= inst
.operands
[0].imm
;
13772 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13773 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13774 inst
.instruction
|= 1 << 8;
13775 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13784 Rd
= inst
.operands
[0].reg
;
13785 Rm
= inst
.operands
[1].reg
;
13787 reject_bad_reg (Rd
);
13788 reject_bad_reg (Rm
);
13790 inst
.instruction
|= Rd
<< 8;
13791 inst
.instruction
|= Rm
<< 16;
13792 inst
.instruction
|= Rm
;
13800 Rd
= inst
.operands
[0].reg
;
13801 Rm
= inst
.operands
[1].reg
;
13803 reject_bad_reg (Rd
);
13804 reject_bad_reg (Rm
);
13806 if (Rd
<= 7 && Rm
<= 7
13807 && inst
.size_req
!= 4)
13809 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13810 inst
.instruction
|= Rd
;
13811 inst
.instruction
|= Rm
<< 3;
13813 else if (unified_syntax
)
13815 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13816 inst
.instruction
|= Rd
<< 8;
13817 inst
.instruction
|= Rm
<< 16;
13818 inst
.instruction
|= Rm
;
13821 inst
.error
= BAD_HIREG
;
13829 Rd
= inst
.operands
[0].reg
;
13830 Rm
= inst
.operands
[1].reg
;
13832 reject_bad_reg (Rd
);
13833 reject_bad_reg (Rm
);
13835 inst
.instruction
|= Rd
<< 8;
13836 inst
.instruction
|= Rm
;
13844 Rd
= inst
.operands
[0].reg
;
13845 Rs
= (inst
.operands
[1].present
13846 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13847 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13849 reject_bad_reg (Rd
);
13850 reject_bad_reg (Rs
);
13851 if (inst
.operands
[2].isreg
)
13852 reject_bad_reg (inst
.operands
[2].reg
);
13854 inst
.instruction
|= Rd
<< 8;
13855 inst
.instruction
|= Rs
<< 16;
13856 if (!inst
.operands
[2].isreg
)
13858 bfd_boolean narrow
;
13860 if ((inst
.instruction
& 0x00100000) != 0)
13861 narrow
= !in_pred_block ();
13863 narrow
= in_pred_block ();
13865 if (Rd
> 7 || Rs
> 7)
13868 if (inst
.size_req
== 4 || !unified_syntax
)
13871 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13872 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13875 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13876 relaxation, but it doesn't seem worth the hassle. */
13879 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13880 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13881 inst
.instruction
|= Rs
<< 3;
13882 inst
.instruction
|= Rd
;
13886 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13887 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13891 encode_thumb32_shifted_operand (2);
13897 if (warn_on_deprecated
13898 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13899 as_tsktsk (_("setend use is deprecated for ARMv8"));
13901 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13902 if (inst
.operands
[0].imm
)
13903 inst
.instruction
|= 0x8;
13909 if (!inst
.operands
[1].present
)
13910 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13912 if (unified_syntax
)
13914 bfd_boolean narrow
;
13917 switch (inst
.instruction
)
13920 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13922 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13924 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13926 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13930 if (THUMB_SETS_FLAGS (inst
.instruction
))
13931 narrow
= !in_pred_block ();
13933 narrow
= in_pred_block ();
13934 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13936 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13938 if (inst
.operands
[2].isreg
13939 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13940 || inst
.operands
[2].reg
> 7))
13942 if (inst
.size_req
== 4)
13945 reject_bad_reg (inst
.operands
[0].reg
);
13946 reject_bad_reg (inst
.operands
[1].reg
);
13950 if (inst
.operands
[2].isreg
)
13952 reject_bad_reg (inst
.operands
[2].reg
);
13953 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13954 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13955 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13956 inst
.instruction
|= inst
.operands
[2].reg
;
13958 /* PR 12854: Error on extraneous shifts. */
13959 constraint (inst
.operands
[2].shifted
,
13960 _("extraneous shift as part of operand to shift insn"));
13964 inst
.operands
[1].shifted
= 1;
13965 inst
.operands
[1].shift_kind
= shift_kind
;
13966 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13967 ? T_MNEM_movs
: T_MNEM_mov
);
13968 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13969 encode_thumb32_shifted_operand (1);
13970 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13971 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13976 if (inst
.operands
[2].isreg
)
13978 switch (shift_kind
)
13980 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13981 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13982 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13983 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13987 inst
.instruction
|= inst
.operands
[0].reg
;
13988 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13990 /* PR 12854: Error on extraneous shifts. */
13991 constraint (inst
.operands
[2].shifted
,
13992 _("extraneous shift as part of operand to shift insn"));
13996 switch (shift_kind
)
13998 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13999 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14000 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14003 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14004 inst
.instruction
|= inst
.operands
[0].reg
;
14005 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14011 constraint (inst
.operands
[0].reg
> 7
14012 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
14013 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
14015 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
14017 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
14018 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14019 _("source1 and dest must be same register"));
14021 switch (inst
.instruction
)
14023 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
14024 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
14025 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
14026 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
14030 inst
.instruction
|= inst
.operands
[0].reg
;
14031 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
14033 /* PR 12854: Error on extraneous shifts. */
14034 constraint (inst
.operands
[2].shifted
,
14035 _("extraneous shift as part of operand to shift insn"));
14039 switch (inst
.instruction
)
14041 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14042 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14043 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14044 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
14047 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14048 inst
.instruction
|= inst
.operands
[0].reg
;
14049 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14057 unsigned Rd
, Rn
, Rm
;
14059 Rd
= inst
.operands
[0].reg
;
14060 Rn
= inst
.operands
[1].reg
;
14061 Rm
= inst
.operands
[2].reg
;
14063 reject_bad_reg (Rd
);
14064 reject_bad_reg (Rn
);
14065 reject_bad_reg (Rm
);
14067 inst
.instruction
|= Rd
<< 8;
14068 inst
.instruction
|= Rn
<< 16;
14069 inst
.instruction
|= Rm
;
14075 unsigned Rd
, Rn
, Rm
;
14077 Rd
= inst
.operands
[0].reg
;
14078 Rm
= inst
.operands
[1].reg
;
14079 Rn
= inst
.operands
[2].reg
;
14081 reject_bad_reg (Rd
);
14082 reject_bad_reg (Rn
);
14083 reject_bad_reg (Rm
);
14085 inst
.instruction
|= Rd
<< 8;
14086 inst
.instruction
|= Rn
<< 16;
14087 inst
.instruction
|= Rm
;
14093 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14094 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14095 _("SMC is not permitted on this architecture"));
14096 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14097 _("expression too complex"));
14098 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14100 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14101 inst
.instruction
|= (value
& 0x000f) << 16;
14103 /* PR gas/15623: SMC instructions must be last in an IT block. */
14104 set_pred_insn_type_last ();
14110 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14112 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14113 inst
.instruction
|= (value
& 0x0fff);
14114 inst
.instruction
|= (value
& 0xf000) << 4;
14118 do_t_ssat_usat (int bias
)
14122 Rd
= inst
.operands
[0].reg
;
14123 Rn
= inst
.operands
[2].reg
;
14125 reject_bad_reg (Rd
);
14126 reject_bad_reg (Rn
);
14128 inst
.instruction
|= Rd
<< 8;
14129 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14130 inst
.instruction
|= Rn
<< 16;
14132 if (inst
.operands
[3].present
)
14134 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14136 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14138 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14139 _("expression too complex"));
14141 if (shift_amount
!= 0)
14143 constraint (shift_amount
> 31,
14144 _("shift expression is too large"));
14146 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14147 inst
.instruction
|= 0x00200000; /* sh bit. */
14149 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14150 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14158 do_t_ssat_usat (1);
14166 Rd
= inst
.operands
[0].reg
;
14167 Rn
= inst
.operands
[2].reg
;
14169 reject_bad_reg (Rd
);
14170 reject_bad_reg (Rn
);
14172 inst
.instruction
|= Rd
<< 8;
14173 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14174 inst
.instruction
|= Rn
<< 16;
14180 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14181 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14182 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14183 || inst
.operands
[2].negative
,
14186 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14188 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14189 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14190 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14191 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14197 if (!inst
.operands
[2].present
)
14198 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14200 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14201 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14202 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14205 inst
.instruction
|= inst
.operands
[0].reg
;
14206 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14207 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14208 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14214 unsigned Rd
, Rn
, Rm
;
14216 Rd
= inst
.operands
[0].reg
;
14217 Rn
= inst
.operands
[1].reg
;
14218 Rm
= inst
.operands
[2].reg
;
14220 reject_bad_reg (Rd
);
14221 reject_bad_reg (Rn
);
14222 reject_bad_reg (Rm
);
14224 inst
.instruction
|= Rd
<< 8;
14225 inst
.instruction
|= Rn
<< 16;
14226 inst
.instruction
|= Rm
;
14227 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14235 Rd
= inst
.operands
[0].reg
;
14236 Rm
= inst
.operands
[1].reg
;
14238 reject_bad_reg (Rd
);
14239 reject_bad_reg (Rm
);
14241 if (inst
.instruction
<= 0xffff
14242 && inst
.size_req
!= 4
14243 && Rd
<= 7 && Rm
<= 7
14244 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14246 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14247 inst
.instruction
|= Rd
;
14248 inst
.instruction
|= Rm
<< 3;
14250 else if (unified_syntax
)
14252 if (inst
.instruction
<= 0xffff)
14253 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14254 inst
.instruction
|= Rd
<< 8;
14255 inst
.instruction
|= Rm
;
14256 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14260 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14261 _("Thumb encoding does not support rotation"));
14262 constraint (1, BAD_HIREG
);
14269 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14278 half
= (inst
.instruction
& 0x10) != 0;
14279 set_pred_insn_type_last ();
14280 constraint (inst
.operands
[0].immisreg
,
14281 _("instruction requires register index"));
14283 Rn
= inst
.operands
[0].reg
;
14284 Rm
= inst
.operands
[0].imm
;
14286 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14287 constraint (Rn
== REG_SP
, BAD_SP
);
14288 reject_bad_reg (Rm
);
14290 constraint (!half
&& inst
.operands
[0].shifted
,
14291 _("instruction does not allow shifted index"));
14292 inst
.instruction
|= (Rn
<< 16) | Rm
;
14298 if (!inst
.operands
[0].present
)
14299 inst
.operands
[0].imm
= 0;
14301 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14303 constraint (inst
.size_req
== 2,
14304 _("immediate value out of range"));
14305 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14306 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14307 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14311 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14312 inst
.instruction
|= inst
.operands
[0].imm
;
14315 set_pred_insn_type (NEUTRAL_IT_INSN
);
14322 do_t_ssat_usat (0);
14330 Rd
= inst
.operands
[0].reg
;
14331 Rn
= inst
.operands
[2].reg
;
14333 reject_bad_reg (Rd
);
14334 reject_bad_reg (Rn
);
14336 inst
.instruction
|= Rd
<< 8;
14337 inst
.instruction
|= inst
.operands
[1].imm
;
14338 inst
.instruction
|= Rn
<< 16;
14341 /* Checking the range of the branch offset (VAL) with NBITS bits
14342 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14344 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14346 gas_assert (nbits
> 0 && nbits
<= 32);
14349 int cmp
= (1 << (nbits
- 1));
14350 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14355 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14361 /* For branches in Armv8.1-M Mainline. */
14363 do_t_branch_future (void)
14365 unsigned long insn
= inst
.instruction
;
14367 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14368 if (inst
.operands
[0].hasreloc
== 0)
14370 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14371 as_bad (BAD_BRANCH_OFF
);
14373 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14377 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14378 inst
.relocs
[0].pc_rel
= 1;
14384 if (inst
.operands
[1].hasreloc
== 0)
14386 int val
= inst
.operands
[1].imm
;
14387 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14388 as_bad (BAD_BRANCH_OFF
);
14390 int immA
= (val
& 0x0001f000) >> 12;
14391 int immB
= (val
& 0x00000ffc) >> 2;
14392 int immC
= (val
& 0x00000002) >> 1;
14393 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14397 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14398 inst
.relocs
[1].pc_rel
= 1;
14403 if (inst
.operands
[1].hasreloc
== 0)
14405 int val
= inst
.operands
[1].imm
;
14406 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14407 as_bad (BAD_BRANCH_OFF
);
14409 int immA
= (val
& 0x0007f000) >> 12;
14410 int immB
= (val
& 0x00000ffc) >> 2;
14411 int immC
= (val
& 0x00000002) >> 1;
14412 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14416 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14417 inst
.relocs
[1].pc_rel
= 1;
14421 case T_MNEM_bfcsel
:
14423 if (inst
.operands
[1].hasreloc
== 0)
14425 int val
= inst
.operands
[1].imm
;
14426 int immA
= (val
& 0x00001000) >> 12;
14427 int immB
= (val
& 0x00000ffc) >> 2;
14428 int immC
= (val
& 0x00000002) >> 1;
14429 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14433 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14434 inst
.relocs
[1].pc_rel
= 1;
14438 if (inst
.operands
[2].hasreloc
== 0)
14440 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14441 int val2
= inst
.operands
[2].imm
;
14442 int val0
= inst
.operands
[0].imm
& 0x1f;
14443 int diff
= val2
- val0
;
14445 inst
.instruction
|= 1 << 17; /* T bit. */
14446 else if (diff
!= 2)
14447 as_bad (_("out of range label-relative fixup value"));
14451 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14452 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14453 inst
.relocs
[2].pc_rel
= 1;
14457 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14458 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14463 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14470 /* Helper function for do_t_loloop to handle relocations. */
14472 v8_1_loop_reloc (int is_le
)
14474 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14476 int value
= inst
.relocs
[0].exp
.X_add_number
;
14477 value
= (is_le
) ? -value
: value
;
14479 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14480 as_bad (BAD_BRANCH_OFF
);
14484 immh
= (value
& 0x00000ffc) >> 2;
14485 imml
= (value
& 0x00000002) >> 1;
14487 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14491 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14492 inst
.relocs
[0].pc_rel
= 1;
14496 /* For shifts with four operands in MVE. */
14498 do_mve_scalar_shift1 (void)
14500 unsigned int value
= inst
.operands
[2].imm
;
14502 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14503 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14505 /* Setting the bit for saturation. */
14506 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14508 /* Assuming Rm is already checked not to be 11x1. */
14509 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14510 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14511 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14514 /* For shifts in MVE. */
14516 do_mve_scalar_shift (void)
14518 if (!inst
.operands
[2].present
)
14520 inst
.operands
[2] = inst
.operands
[1];
14521 inst
.operands
[1].reg
= 0xf;
14524 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14525 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14527 if (inst
.operands
[2].isreg
)
14529 /* Assuming Rm is already checked not to be 11x1. */
14530 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14531 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14532 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14536 /* Assuming imm is already checked as [1,32]. */
14537 unsigned int value
= inst
.operands
[2].imm
;
14538 inst
.instruction
|= (value
& 0x1c) << 10;
14539 inst
.instruction
|= (value
& 0x03) << 6;
14540 /* Change last 4 bits from 0xd to 0xf. */
14541 inst
.instruction
|= 0x2;
14545 /* MVE instruction encoder helpers. */
14546 #define M_MNEM_vabav 0xee800f01
14547 #define M_MNEM_vmladav 0xeef00e00
14548 #define M_MNEM_vmladava 0xeef00e20
14549 #define M_MNEM_vmladavx 0xeef01e00
14550 #define M_MNEM_vmladavax 0xeef01e20
14551 #define M_MNEM_vmlsdav 0xeef00e01
14552 #define M_MNEM_vmlsdava 0xeef00e21
14553 #define M_MNEM_vmlsdavx 0xeef01e01
14554 #define M_MNEM_vmlsdavax 0xeef01e21
14555 #define M_MNEM_vmullt 0xee011e00
14556 #define M_MNEM_vmullb 0xee010e00
14557 #define M_MNEM_vctp 0xf000e801
14558 #define M_MNEM_vst20 0xfc801e00
14559 #define M_MNEM_vst21 0xfc801e20
14560 #define M_MNEM_vst40 0xfc801e01
14561 #define M_MNEM_vst41 0xfc801e21
14562 #define M_MNEM_vst42 0xfc801e41
14563 #define M_MNEM_vst43 0xfc801e61
14564 #define M_MNEM_vld20 0xfc901e00
14565 #define M_MNEM_vld21 0xfc901e20
14566 #define M_MNEM_vld40 0xfc901e01
14567 #define M_MNEM_vld41 0xfc901e21
14568 #define M_MNEM_vld42 0xfc901e41
14569 #define M_MNEM_vld43 0xfc901e61
14570 #define M_MNEM_vstrb 0xec000e00
14571 #define M_MNEM_vstrh 0xec000e10
14572 #define M_MNEM_vstrw 0xec000e40
14573 #define M_MNEM_vstrd 0xec000e50
14574 #define M_MNEM_vldrb 0xec100e00
14575 #define M_MNEM_vldrh 0xec100e10
14576 #define M_MNEM_vldrw 0xec100e40
14577 #define M_MNEM_vldrd 0xec100e50
14578 #define M_MNEM_vmovlt 0xeea01f40
14579 #define M_MNEM_vmovlb 0xeea00f40
14580 #define M_MNEM_vmovnt 0xfe311e81
14581 #define M_MNEM_vmovnb 0xfe310e81
14582 #define M_MNEM_vadc 0xee300f00
14583 #define M_MNEM_vadci 0xee301f00
14584 #define M_MNEM_vbrsr 0xfe011e60
14585 #define M_MNEM_vaddlv 0xee890f00
14586 #define M_MNEM_vaddlva 0xee890f20
14587 #define M_MNEM_vaddv 0xeef10f00
14588 #define M_MNEM_vaddva 0xeef10f20
14589 #define M_MNEM_vddup 0xee011f6e
14590 #define M_MNEM_vdwdup 0xee011f60
14591 #define M_MNEM_vidup 0xee010f6e
14592 #define M_MNEM_viwdup 0xee010f60
14593 #define M_MNEM_vmaxv 0xeee20f00
14594 #define M_MNEM_vmaxav 0xeee00f00
14595 #define M_MNEM_vminv 0xeee20f80
14596 #define M_MNEM_vminav 0xeee00f80
14597 #define M_MNEM_vmlaldav 0xee800e00
14598 #define M_MNEM_vmlaldava 0xee800e20
14599 #define M_MNEM_vmlaldavx 0xee801e00
14600 #define M_MNEM_vmlaldavax 0xee801e20
14601 #define M_MNEM_vmlsldav 0xee800e01
14602 #define M_MNEM_vmlsldava 0xee800e21
14603 #define M_MNEM_vmlsldavx 0xee801e01
14604 #define M_MNEM_vmlsldavax 0xee801e21
14605 #define M_MNEM_vrmlaldavhx 0xee801f00
14606 #define M_MNEM_vrmlaldavhax 0xee801f20
14607 #define M_MNEM_vrmlsldavh 0xfe800e01
14608 #define M_MNEM_vrmlsldavha 0xfe800e21
14609 #define M_MNEM_vrmlsldavhx 0xfe801e01
14610 #define M_MNEM_vrmlsldavhax 0xfe801e21
14611 #define M_MNEM_vqmovnt 0xee331e01
14612 #define M_MNEM_vqmovnb 0xee330e01
14613 #define M_MNEM_vqmovunt 0xee311e81
14614 #define M_MNEM_vqmovunb 0xee310e81
14615 #define M_MNEM_vshrnt 0xee801fc1
14616 #define M_MNEM_vshrnb 0xee800fc1
14617 #define M_MNEM_vrshrnt 0xfe801fc1
14618 #define M_MNEM_vqshrnt 0xee801f40
14619 #define M_MNEM_vqshrnb 0xee800f40
14620 #define M_MNEM_vqshrunt 0xee801fc0
14621 #define M_MNEM_vqshrunb 0xee800fc0
14622 #define M_MNEM_vrshrnb 0xfe800fc1
14623 #define M_MNEM_vqrshrnt 0xee801f41
14624 #define M_MNEM_vqrshrnb 0xee800f41
14625 #define M_MNEM_vqrshrunt 0xfe801fc0
14626 #define M_MNEM_vqrshrunb 0xfe800fc0
14628 /* Bfloat16 instruction encoder helpers. */
14629 #define B_MNEM_vfmat 0xfc300850
14630 #define B_MNEM_vfmab 0xfc300810
14632 /* Neon instruction encoder helpers. */
14634 /* Encodings for the different types for various Neon opcodes. */
14636 /* An "invalid" code for the following tables. */
14639 struct neon_tab_entry
14642 unsigned float_or_poly
;
14643 unsigned scalar_or_imm
;
14646 /* Map overloaded Neon opcodes to their respective encodings. */
14647 #define NEON_ENC_TAB \
14648 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14649 X(vabdl, 0x0800700, N_INV, N_INV), \
14650 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14651 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14652 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14653 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14654 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14655 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14656 X(vaddl, 0x0800000, N_INV, N_INV), \
14657 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14658 X(vsubl, 0x0800200, N_INV, N_INV), \
14659 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14660 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14661 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14662 /* Register variants of the following two instructions are encoded as
14663 vcge / vcgt with the operands reversed. */ \
14664 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14665 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14666 X(vfma, N_INV, 0x0000c10, N_INV), \
14667 X(vfms, N_INV, 0x0200c10, N_INV), \
14668 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14669 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14670 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14671 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14672 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14673 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14674 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14675 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14676 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14677 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14678 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14679 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14680 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14681 X(vshl, 0x0000400, N_INV, 0x0800510), \
14682 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14683 X(vand, 0x0000110, N_INV, 0x0800030), \
14684 X(vbic, 0x0100110, N_INV, 0x0800030), \
14685 X(veor, 0x1000110, N_INV, N_INV), \
14686 X(vorn, 0x0300110, N_INV, 0x0800010), \
14687 X(vorr, 0x0200110, N_INV, 0x0800010), \
14688 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14689 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14690 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14691 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14692 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14693 X(vst1, 0x0000000, 0x0800000, N_INV), \
14694 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14695 X(vst2, 0x0000100, 0x0800100, N_INV), \
14696 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14697 X(vst3, 0x0000200, 0x0800200, N_INV), \
14698 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14699 X(vst4, 0x0000300, 0x0800300, N_INV), \
14700 X(vmovn, 0x1b20200, N_INV, N_INV), \
14701 X(vtrn, 0x1b20080, N_INV, N_INV), \
14702 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14703 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14704 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14705 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14706 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14707 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14708 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14709 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14710 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14711 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14712 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14713 X(vseleq, 0xe000a00, N_INV, N_INV), \
14714 X(vselvs, 0xe100a00, N_INV, N_INV), \
14715 X(vselge, 0xe200a00, N_INV, N_INV), \
14716 X(vselgt, 0xe300a00, N_INV, N_INV), \
14717 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14718 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14719 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14720 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14721 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14722 X(aes, 0x3b00300, N_INV, N_INV), \
14723 X(sha3op, 0x2000c00, N_INV, N_INV), \
14724 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14725 X(sha2op, 0x3ba0380, N_INV, N_INV)
14729 #define X(OPC,I,F,S) N_MNEM_##OPC
14734 static const struct neon_tab_entry neon_enc_tab
[] =
14736 #define X(OPC,I,F,S) { (I), (F), (S) }
14741 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14742 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14743 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14744 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14745 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14746 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14747 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14748 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14749 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14750 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14751 #define NEON_ENC_SINGLE_(X) \
14752 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14753 #define NEON_ENC_DOUBLE_(X) \
14754 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14755 #define NEON_ENC_FPV8_(X) \
14756 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14758 #define NEON_ENCODE(type, inst) \
14761 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14762 inst.is_neon = 1; \
14766 #define check_neon_suffixes \
14769 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14771 as_bad (_("invalid neon suffix for non neon instruction")); \
14777 /* Define shapes for instruction operands. The following mnemonic characters
14778 are used in this table:
14780 F - VFP S<n> register
14781 D - Neon D<n> register
14782 Q - Neon Q<n> register
14786 L - D<n> register list
14788 This table is used to generate various data:
14789 - enumerations of the form NS_DDR to be used as arguments to
14791 - a table classifying shapes into single, double, quad, mixed.
14792 - a table used to drive neon_select_shape. */
14794 #define NEON_SHAPE_DEF \
14795 X(4, (R, R, Q, Q), QUAD), \
14796 X(4, (Q, R, R, I), QUAD), \
14797 X(4, (R, R, S, S), QUAD), \
14798 X(4, (S, S, R, R), QUAD), \
14799 X(3, (Q, R, I), QUAD), \
14800 X(3, (I, Q, Q), QUAD), \
14801 X(3, (I, Q, R), QUAD), \
14802 X(3, (R, Q, Q), QUAD), \
14803 X(3, (D, D, D), DOUBLE), \
14804 X(3, (Q, Q, Q), QUAD), \
14805 X(3, (D, D, I), DOUBLE), \
14806 X(3, (Q, Q, I), QUAD), \
14807 X(3, (D, D, S), DOUBLE), \
14808 X(3, (Q, Q, S), QUAD), \
14809 X(3, (Q, Q, R), QUAD), \
14810 X(3, (R, R, Q), QUAD), \
14811 X(2, (R, Q), QUAD), \
14812 X(2, (D, D), DOUBLE), \
14813 X(2, (Q, Q), QUAD), \
14814 X(2, (D, S), DOUBLE), \
14815 X(2, (Q, S), QUAD), \
14816 X(2, (D, R), DOUBLE), \
14817 X(2, (Q, R), QUAD), \
14818 X(2, (D, I), DOUBLE), \
14819 X(2, (Q, I), QUAD), \
14820 X(3, (P, F, I), SINGLE), \
14821 X(3, (P, D, I), DOUBLE), \
14822 X(3, (P, Q, I), QUAD), \
14823 X(4, (P, F, F, I), SINGLE), \
14824 X(4, (P, D, D, I), DOUBLE), \
14825 X(4, (P, Q, Q, I), QUAD), \
14826 X(5, (P, F, F, F, I), SINGLE), \
14827 X(5, (P, D, D, D, I), DOUBLE), \
14828 X(5, (P, Q, Q, Q, I), QUAD), \
14829 X(3, (D, L, D), DOUBLE), \
14830 X(2, (D, Q), MIXED), \
14831 X(2, (Q, D), MIXED), \
14832 X(3, (D, Q, I), MIXED), \
14833 X(3, (Q, D, I), MIXED), \
14834 X(3, (Q, D, D), MIXED), \
14835 X(3, (D, Q, Q), MIXED), \
14836 X(3, (Q, Q, D), MIXED), \
14837 X(3, (Q, D, S), MIXED), \
14838 X(3, (D, Q, S), MIXED), \
14839 X(4, (D, D, D, I), DOUBLE), \
14840 X(4, (Q, Q, Q, I), QUAD), \
14841 X(4, (D, D, S, I), DOUBLE), \
14842 X(4, (Q, Q, S, I), QUAD), \
14843 X(2, (F, F), SINGLE), \
14844 X(3, (F, F, F), SINGLE), \
14845 X(2, (F, I), SINGLE), \
14846 X(2, (F, D), MIXED), \
14847 X(2, (D, F), MIXED), \
14848 X(3, (F, F, I), MIXED), \
14849 X(4, (R, R, F, F), SINGLE), \
14850 X(4, (F, F, R, R), SINGLE), \
14851 X(3, (D, R, R), DOUBLE), \
14852 X(3, (R, R, D), DOUBLE), \
14853 X(2, (S, R), SINGLE), \
14854 X(2, (R, S), SINGLE), \
14855 X(2, (F, R), SINGLE), \
14856 X(2, (R, F), SINGLE), \
14857 /* Used for MVE tail predicated loop instructions. */\
14858 X(2, (R, R), QUAD), \
14859 /* Half float shape supported so far. */\
14860 X (2, (H, D), MIXED), \
14861 X (2, (D, H), MIXED), \
14862 X (2, (H, F), MIXED), \
14863 X (2, (F, H), MIXED), \
14864 X (2, (H, H), HALF), \
14865 X (2, (H, R), HALF), \
14866 X (2, (R, H), HALF), \
14867 X (2, (H, I), HALF), \
14868 X (3, (H, H, H), HALF), \
14869 X (3, (H, F, I), MIXED), \
14870 X (3, (F, H, I), MIXED), \
14871 X (3, (D, H, H), MIXED), \
14872 X (3, (D, H, S), MIXED)
14874 #define S2(A,B) NS_##A##B
14875 #define S3(A,B,C) NS_##A##B##C
14876 #define S4(A,B,C,D) NS_##A##B##C##D
14877 #define S5(A,B,C,D,E) NS_##A##B##C##D##E
14879 #define X(N, L, C) S##N L
14893 enum neon_shape_class
14902 #define X(N, L, C) SC_##C
14904 static enum neon_shape_class neon_shape_class
[] =
14924 /* Register widths of above. */
14925 static unsigned neon_shape_el_size
[] =
14938 struct neon_shape_info
14941 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14944 #define S2(A,B) { SE_##A, SE_##B }
14945 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14946 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14947 #define S5(A,B,C,D,E) { SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
14949 #define X(N, L, C) { N, S##N L }
14951 static struct neon_shape_info neon_shape_tab
[] =
14962 /* Bit masks used in type checking given instructions.
14963 'N_EQK' means the type must be the same as (or based on in some way) the key
14964 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14965 set, various other bits can be set as well in order to modify the meaning of
14966 the type constraint. */
14968 enum neon_type_mask
14992 N_BF16
= 0x0400000,
14993 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14994 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14995 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14996 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14997 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14998 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14999 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
15000 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
15001 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
15002 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
15003 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
15005 N_MAX_NONSPECIAL
= N_P64
15008 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
15010 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
15011 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15012 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
15013 #define N_S_32 (N_S8 | N_S16 | N_S32)
15014 #define N_F_16_32 (N_F16 | N_F32)
15015 #define N_SUF_32 (N_SU_32 | N_F_16_32)
15016 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
15017 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
15018 #define N_F_ALL (N_F16 | N_F32 | N_F64)
15019 #define N_I_MVE (N_I8 | N_I16 | N_I32)
15020 #define N_F_MVE (N_F16 | N_F32)
15021 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15023 /* Pass this as the first type argument to neon_check_type to ignore types
15025 #define N_IGNORE_TYPE (N_KEY | N_EQK)
15027 /* Select a "shape" for the current instruction (describing register types or
15028 sizes) from a list of alternatives. Return NS_NULL if the current instruction
15029 doesn't fit. For non-polymorphic shapes, checking is usually done as a
15030 function of operand parsing, so this function doesn't need to be called.
15031 Shapes should be listed in order of decreasing length. */
15033 static enum neon_shape
15034 neon_select_shape (enum neon_shape shape
, ...)
15037 enum neon_shape first_shape
= shape
;
15039 /* Fix missing optional operands. FIXME: we don't know at this point how
15040 many arguments we should have, so this makes the assumption that we have
15041 > 1. This is true of all current Neon opcodes, I think, but may not be
15042 true in the future. */
15043 if (!inst
.operands
[1].present
)
15044 inst
.operands
[1] = inst
.operands
[0];
15046 va_start (ap
, shape
);
15048 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
15053 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
15055 if (!inst
.operands
[j
].present
)
15061 switch (neon_shape_tab
[shape
].el
[j
])
15063 /* If a .f16, .16, .u16, .s16 type specifier is given over
15064 a VFP single precision register operand, it's essentially
15065 means only half of the register is used.
15067 If the type specifier is given after the mnemonics, the
15068 information is stored in inst.vectype. If the type specifier
15069 is given after register operand, the information is stored
15070 in inst.operands[].vectype.
15072 When there is only one type specifier, and all the register
15073 operands are the same type of hardware register, the type
15074 specifier applies to all register operands.
15076 If no type specifier is given, the shape is inferred from
15077 operand information.
15080 vadd.f16 s0, s1, s2: NS_HHH
15081 vabs.f16 s0, s1: NS_HH
15082 vmov.f16 s0, r1: NS_HR
15083 vmov.f16 r0, s1: NS_RH
15084 vcvt.f16 r0, s1: NS_RH
15085 vcvt.f16.s32 s2, s2, #29: NS_HFI
15086 vcvt.f16.s32 s2, s2: NS_HF
15089 if (!(inst
.operands
[j
].isreg
15090 && inst
.operands
[j
].isvec
15091 && inst
.operands
[j
].issingle
15092 && !inst
.operands
[j
].isquad
15093 && ((inst
.vectype
.elems
== 1
15094 && inst
.vectype
.el
[0].size
== 16)
15095 || (inst
.vectype
.elems
> 1
15096 && inst
.vectype
.el
[j
].size
== 16)
15097 || (inst
.vectype
.elems
== 0
15098 && inst
.operands
[j
].vectype
.type
!= NT_invtype
15099 && inst
.operands
[j
].vectype
.size
== 16))))
15104 if (!(inst
.operands
[j
].isreg
15105 && inst
.operands
[j
].isvec
15106 && inst
.operands
[j
].issingle
15107 && !inst
.operands
[j
].isquad
15108 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15109 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15110 || (inst
.vectype
.elems
== 0
15111 && (inst
.operands
[j
].vectype
.size
== 32
15112 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15117 if (!(inst
.operands
[j
].isreg
15118 && inst
.operands
[j
].isvec
15119 && !inst
.operands
[j
].isquad
15120 && !inst
.operands
[j
].issingle
))
15125 if (!(inst
.operands
[j
].isreg
15126 && !inst
.operands
[j
].isvec
))
15131 if (!(inst
.operands
[j
].isreg
15132 && inst
.operands
[j
].isvec
15133 && inst
.operands
[j
].isquad
15134 && !inst
.operands
[j
].issingle
))
15139 if (!(!inst
.operands
[j
].isreg
15140 && !inst
.operands
[j
].isscalar
))
15145 if (!(!inst
.operands
[j
].isreg
15146 && inst
.operands
[j
].isscalar
))
15157 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15158 /* We've matched all the entries in the shape table, and we don't
15159 have any left over operands which have not been matched. */
15165 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15166 first_error (_("invalid instruction shape"));
15171 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15172 means the Q bit should be set). */
15175 neon_quad (enum neon_shape shape
)
15177 return neon_shape_class
[shape
] == SC_QUAD
;
15181 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15184 /* Allow modification to be made to types which are constrained to be
15185 based on the key element, based on bits set alongside N_EQK. */
15186 if ((typebits
& N_EQK
) != 0)
15188 if ((typebits
& N_HLF
) != 0)
15190 else if ((typebits
& N_DBL
) != 0)
15192 if ((typebits
& N_SGN
) != 0)
15193 *g_type
= NT_signed
;
15194 else if ((typebits
& N_UNS
) != 0)
15195 *g_type
= NT_unsigned
;
15196 else if ((typebits
& N_INT
) != 0)
15197 *g_type
= NT_integer
;
15198 else if ((typebits
& N_FLT
) != 0)
15199 *g_type
= NT_float
;
15200 else if ((typebits
& N_SIZ
) != 0)
15201 *g_type
= NT_untyped
;
15205 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15206 operand type, i.e. the single type specified in a Neon instruction when it
15207 is the only one given. */
15209 static struct neon_type_el
15210 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15212 struct neon_type_el dest
= *key
;
15214 gas_assert ((thisarg
& N_EQK
) != 0);
15216 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15221 /* Convert Neon type and size into compact bitmask representation. */
15223 static enum neon_type_mask
15224 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15231 case 8: return N_8
;
15232 case 16: return N_16
;
15233 case 32: return N_32
;
15234 case 64: return N_64
;
15242 case 8: return N_I8
;
15243 case 16: return N_I16
;
15244 case 32: return N_I32
;
15245 case 64: return N_I64
;
15253 case 16: return N_F16
;
15254 case 32: return N_F32
;
15255 case 64: return N_F64
;
15263 case 8: return N_P8
;
15264 case 16: return N_P16
;
15265 case 64: return N_P64
;
15273 case 8: return N_S8
;
15274 case 16: return N_S16
;
15275 case 32: return N_S32
;
15276 case 64: return N_S64
;
15284 case 8: return N_U8
;
15285 case 16: return N_U16
;
15286 case 32: return N_U32
;
15287 case 64: return N_U64
;
15293 if (size
== 16) return N_BF16
;
15302 /* Convert compact Neon bitmask type representation to a type and size. Only
15303 handles the case where a single bit is set in the mask. */
15306 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15307 enum neon_type_mask mask
)
15309 if ((mask
& N_EQK
) != 0)
15312 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15314 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15317 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15319 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15324 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15326 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15327 *type
= NT_unsigned
;
15328 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15329 *type
= NT_integer
;
15330 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15331 *type
= NT_untyped
;
15332 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15334 else if ((mask
& (N_F_ALL
)) != 0)
15336 else if ((mask
& (N_BF16
)) != 0)
15344 /* Modify a bitmask of allowed types. This is only needed for type
15348 modify_types_allowed (unsigned allowed
, unsigned mods
)
15351 enum neon_el_type type
;
15357 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15359 if (el_type_of_type_chk (&type
, &size
,
15360 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15362 neon_modify_type_size (mods
, &type
, &size
);
15363 destmask
|= type_chk_of_el_type (type
, size
);
15370 /* Check type and return type classification.
15371 The manual states (paraphrase): If one datatype is given, it indicates the
15373 - the second operand, if there is one
15374 - the operand, if there is no second operand
15375 - the result, if there are no operands.
15376 This isn't quite good enough though, so we use a concept of a "key" datatype
15377 which is set on a per-instruction basis, which is the one which matters when
15378 only one data type is written.
15379 Note: this function has side-effects (e.g. filling in missing operands). All
15380 Neon instructions should call it before performing bit encoding. */
15382 static struct neon_type_el
15383 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15386 unsigned i
, pass
, key_el
= 0;
15387 unsigned types
[NEON_MAX_TYPE_ELS
];
15388 enum neon_el_type k_type
= NT_invtype
;
15389 unsigned k_size
= -1u;
15390 struct neon_type_el badtype
= {NT_invtype
, -1};
15391 unsigned key_allowed
= 0;
15393 /* Optional registers in Neon instructions are always (not) in operand 1.
15394 Fill in the missing operand here, if it was omitted. */
15395 if (els
> 1 && !inst
.operands
[1].present
)
15396 inst
.operands
[1] = inst
.operands
[0];
15398 /* Suck up all the varargs. */
15400 for (i
= 0; i
< els
; i
++)
15402 unsigned thisarg
= va_arg (ap
, unsigned);
15403 if (thisarg
== N_IGNORE_TYPE
)
15408 types
[i
] = thisarg
;
15409 if ((thisarg
& N_KEY
) != 0)
15414 if (inst
.vectype
.elems
> 0)
15415 for (i
= 0; i
< els
; i
++)
15416 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15418 first_error (_("types specified in both the mnemonic and operands"));
15422 /* Duplicate inst.vectype elements here as necessary.
15423 FIXME: No idea if this is exactly the same as the ARM assembler,
15424 particularly when an insn takes one register and one non-register
15426 if (inst
.vectype
.elems
== 1 && els
> 1)
15429 inst
.vectype
.elems
= els
;
15430 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15431 for (j
= 0; j
< els
; j
++)
15433 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15436 else if (inst
.vectype
.elems
== 0 && els
> 0)
15439 /* No types were given after the mnemonic, so look for types specified
15440 after each operand. We allow some flexibility here; as long as the
15441 "key" operand has a type, we can infer the others. */
15442 for (j
= 0; j
< els
; j
++)
15443 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15444 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15446 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15448 for (j
= 0; j
< els
; j
++)
15449 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15450 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15455 first_error (_("operand types can't be inferred"));
15459 else if (inst
.vectype
.elems
!= els
)
15461 first_error (_("type specifier has the wrong number of parts"));
15465 for (pass
= 0; pass
< 2; pass
++)
15467 for (i
= 0; i
< els
; i
++)
15469 unsigned thisarg
= types
[i
];
15470 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15471 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15472 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15473 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15475 /* Decay more-specific signed & unsigned types to sign-insensitive
15476 integer types if sign-specific variants are unavailable. */
15477 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15478 && (types_allowed
& N_SU_ALL
) == 0)
15479 g_type
= NT_integer
;
15481 /* If only untyped args are allowed, decay any more specific types to
15482 them. Some instructions only care about signs for some element
15483 sizes, so handle that properly. */
15484 if (((types_allowed
& N_UNT
) == 0)
15485 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15486 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15487 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15488 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15489 g_type
= NT_untyped
;
15493 if ((thisarg
& N_KEY
) != 0)
15497 key_allowed
= thisarg
& ~N_KEY
;
15499 /* Check architecture constraint on FP16 extension. */
15501 && k_type
== NT_float
15502 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15504 inst
.error
= _(BAD_FP16
);
15511 if ((thisarg
& N_VFP
) != 0)
15513 enum neon_shape_el regshape
;
15514 unsigned regwidth
, match
;
15516 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15519 first_error (_("invalid instruction shape"));
15522 regshape
= neon_shape_tab
[ns
].el
[i
];
15523 regwidth
= neon_shape_el_size
[regshape
];
15525 /* In VFP mode, operands must match register widths. If we
15526 have a key operand, use its width, else use the width of
15527 the current operand. */
15533 /* FP16 will use a single precision register. */
15534 if (regwidth
== 32 && match
== 16)
15536 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15540 inst
.error
= _(BAD_FP16
);
15545 if (regwidth
!= match
)
15547 first_error (_("operand size must match register width"));
15552 if ((thisarg
& N_EQK
) == 0)
15554 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15556 if ((given_type
& types_allowed
) == 0)
15558 first_error (BAD_SIMD_TYPE
);
15564 enum neon_el_type mod_k_type
= k_type
;
15565 unsigned mod_k_size
= k_size
;
15566 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15567 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15569 first_error (_("inconsistent types in Neon instruction"));
15577 return inst
.vectype
.el
[key_el
];
15580 /* Neon-style VFP instruction forwarding. */
15582 /* Thumb VFP instructions have 0xE in the condition field. */
15585 do_vfp_cond_or_thumb (void)
15590 inst
.instruction
|= 0xe0000000;
15592 inst
.instruction
|= inst
.cond
<< 28;
15595 /* Look up and encode a simple mnemonic, for use as a helper function for the
15596 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15597 etc. It is assumed that operand parsing has already been done, and that the
15598 operands are in the form expected by the given opcode (this isn't necessarily
15599 the same as the form in which they were parsed, hence some massaging must
15600 take place before this function is called).
15601 Checks current arch version against that in the looked-up opcode. */
15604 do_vfp_nsyn_opcode (const char *opname
)
15606 const struct asm_opcode
*opcode
;
15608 opcode
= (const struct asm_opcode
*) str_hash_find (arm_ops_hsh
, opname
);
15613 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15614 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15621 inst
.instruction
= opcode
->tvalue
;
15622 opcode
->tencode ();
15626 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15627 opcode
->aencode ();
15632 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15634 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15636 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15639 do_vfp_nsyn_opcode ("fadds");
15641 do_vfp_nsyn_opcode ("fsubs");
15643 /* ARMv8.2 fp16 instruction. */
15645 do_scalar_fp16_v82_encode ();
15650 do_vfp_nsyn_opcode ("faddd");
15652 do_vfp_nsyn_opcode ("fsubd");
15656 /* Check operand types to see if this is a VFP instruction, and if so call
15660 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15662 enum neon_shape rs
;
15663 struct neon_type_el et
;
15668 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15669 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15673 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15674 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15675 N_F_ALL
| N_KEY
| N_VFP
);
15682 if (et
.type
!= NT_invtype
)
15693 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15695 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15697 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15700 do_vfp_nsyn_opcode ("fmacs");
15702 do_vfp_nsyn_opcode ("fnmacs");
15704 /* ARMv8.2 fp16 instruction. */
15706 do_scalar_fp16_v82_encode ();
15711 do_vfp_nsyn_opcode ("fmacd");
15713 do_vfp_nsyn_opcode ("fnmacd");
15718 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15720 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15722 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15725 do_vfp_nsyn_opcode ("ffmas");
15727 do_vfp_nsyn_opcode ("ffnmas");
15729 /* ARMv8.2 fp16 instruction. */
15731 do_scalar_fp16_v82_encode ();
15736 do_vfp_nsyn_opcode ("ffmad");
15738 do_vfp_nsyn_opcode ("ffnmad");
15743 do_vfp_nsyn_mul (enum neon_shape rs
)
15745 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15747 do_vfp_nsyn_opcode ("fmuls");
15749 /* ARMv8.2 fp16 instruction. */
15751 do_scalar_fp16_v82_encode ();
15754 do_vfp_nsyn_opcode ("fmuld");
15758 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15760 int is_neg
= (inst
.instruction
& 0x80) != 0;
15761 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15763 if (rs
== NS_FF
|| rs
== NS_HH
)
15766 do_vfp_nsyn_opcode ("fnegs");
15768 do_vfp_nsyn_opcode ("fabss");
15770 /* ARMv8.2 fp16 instruction. */
15772 do_scalar_fp16_v82_encode ();
15777 do_vfp_nsyn_opcode ("fnegd");
15779 do_vfp_nsyn_opcode ("fabsd");
15783 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15784 insns belong to Neon, and are handled elsewhere. */
15787 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15789 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15793 do_vfp_nsyn_opcode ("fldmdbs");
15795 do_vfp_nsyn_opcode ("fldmias");
15800 do_vfp_nsyn_opcode ("fstmdbs");
15802 do_vfp_nsyn_opcode ("fstmias");
15807 do_vfp_nsyn_sqrt (void)
15809 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15810 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15812 if (rs
== NS_FF
|| rs
== NS_HH
)
15814 do_vfp_nsyn_opcode ("fsqrts");
15816 /* ARMv8.2 fp16 instruction. */
15818 do_scalar_fp16_v82_encode ();
15821 do_vfp_nsyn_opcode ("fsqrtd");
15825 do_vfp_nsyn_div (void)
15827 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15828 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15829 N_F_ALL
| N_KEY
| N_VFP
);
15831 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15833 do_vfp_nsyn_opcode ("fdivs");
15835 /* ARMv8.2 fp16 instruction. */
15837 do_scalar_fp16_v82_encode ();
15840 do_vfp_nsyn_opcode ("fdivd");
15844 do_vfp_nsyn_nmul (void)
15846 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15847 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15848 N_F_ALL
| N_KEY
| N_VFP
);
15850 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15852 NEON_ENCODE (SINGLE
, inst
);
15853 do_vfp_sp_dyadic ();
15855 /* ARMv8.2 fp16 instruction. */
15857 do_scalar_fp16_v82_encode ();
15861 NEON_ENCODE (DOUBLE
, inst
);
15862 do_vfp_dp_rd_rn_rm ();
15864 do_vfp_cond_or_thumb ();
15868 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15872 neon_logbits (unsigned x
)
15874 return ffs (x
) - 4;
15877 #define LOW4(R) ((R) & 0xf)
15878 #define HI1(R) (((R) >> 4) & 1)
15879 #define LOW1(R) ((R) & 0x1)
15880 #define HI4(R) (((R) >> 1) & 0xf)
15883 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15888 first_error (BAD_EL_TYPE
);
15891 switch (inst
.operands
[0].imm
)
15894 first_error (_("invalid condition"));
15916 /* only accept eq and ne. */
15917 if (inst
.operands
[0].imm
> 1)
15919 first_error (_("invalid condition"));
15922 return inst
.operands
[0].imm
;
15924 if (inst
.operands
[0].imm
== 0x2)
15926 else if (inst
.operands
[0].imm
== 0x8)
15930 first_error (_("invalid condition"));
15934 switch (inst
.operands
[0].imm
)
15937 first_error (_("invalid condition"));
15953 /* Should be unreachable. */
15957 /* For VCTP (create vector tail predicate) in MVE. */
15962 unsigned size
= 0x0;
15964 if (inst
.cond
> COND_ALWAYS
)
15965 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15967 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15969 /* This is a typical MVE instruction which has no type but have size 8, 16,
15970 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15971 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15972 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15973 dt
= inst
.vectype
.el
[0].size
;
15975 /* Setting this does not indicate an actual NEON instruction, but only
15976 indicates that the mnemonic accepts neon-style type suffixes. */
15990 first_error (_("Type is not allowed for this instruction"));
15992 inst
.instruction
|= size
<< 20;
15993 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15999 /* We are dealing with a vector predicated block. */
16000 if (inst
.operands
[0].present
)
16002 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16003 struct neon_type_el et
16004 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16007 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16009 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16011 if (et
.type
== NT_invtype
)
16014 if (et
.type
== NT_float
)
16016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16018 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
16019 inst
.instruction
|= (et
.size
== 16) << 28;
16020 inst
.instruction
|= 0x3 << 20;
16024 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
16026 inst
.instruction
|= 1 << 28;
16027 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16030 if (inst
.operands
[2].isquad
)
16032 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16033 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16034 inst
.instruction
|= (fcond
& 0x2) >> 1;
16038 if (inst
.operands
[2].reg
== REG_SP
)
16039 as_tsktsk (MVE_BAD_SP
);
16040 inst
.instruction
|= 1 << 6;
16041 inst
.instruction
|= (fcond
& 0x2) << 4;
16042 inst
.instruction
|= inst
.operands
[2].reg
;
16044 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16045 inst
.instruction
|= (fcond
& 0x4) << 10;
16046 inst
.instruction
|= (fcond
& 0x1) << 7;
16049 set_pred_insn_type (VPT_INSN
);
16051 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
16052 | ((inst
.instruction
& 0xe000) >> 13);
16053 now_pred
.warn_deprecated
= FALSE
;
16054 now_pred
.type
= VECTOR_PRED
;
16061 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
16062 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
16063 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
16064 if (!inst
.operands
[2].present
)
16065 first_error (_("MVE vector or ARM register expected"));
16066 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16068 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16069 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
16070 && inst
.operands
[1].isquad
)
16072 inst
.instruction
= N_MNEM_vcmp
;
16076 if (inst
.cond
> COND_ALWAYS
)
16077 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16079 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16081 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16082 struct neon_type_el et
16083 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16086 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
16087 && !inst
.operands
[2].iszr
, BAD_PC
);
16089 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16091 inst
.instruction
= 0xee010f00;
16092 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16093 inst
.instruction
|= (fcond
& 0x4) << 10;
16094 inst
.instruction
|= (fcond
& 0x1) << 7;
16095 if (et
.type
== NT_float
)
16097 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16099 inst
.instruction
|= (et
.size
== 16) << 28;
16100 inst
.instruction
|= 0x3 << 20;
16104 inst
.instruction
|= 1 << 28;
16105 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16107 if (inst
.operands
[2].isquad
)
16109 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16110 inst
.instruction
|= (fcond
& 0x2) >> 1;
16111 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16115 if (inst
.operands
[2].reg
== REG_SP
)
16116 as_tsktsk (MVE_BAD_SP
);
16117 inst
.instruction
|= 1 << 6;
16118 inst
.instruction
|= (fcond
& 0x2) << 4;
16119 inst
.instruction
|= inst
.operands
[2].reg
;
16127 do_mve_vmaxa_vmina (void)
16129 if (inst
.cond
> COND_ALWAYS
)
16130 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16132 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16134 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16135 struct neon_type_el et
16136 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16138 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16139 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16140 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16141 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16142 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16147 do_mve_vfmas (void)
16149 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16150 struct neon_type_el et
16151 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16153 if (inst
.cond
> COND_ALWAYS
)
16154 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16156 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16158 if (inst
.operands
[2].reg
== REG_SP
)
16159 as_tsktsk (MVE_BAD_SP
);
16160 else if (inst
.operands
[2].reg
== REG_PC
)
16161 as_tsktsk (MVE_BAD_PC
);
16163 inst
.instruction
|= (et
.size
== 16) << 28;
16164 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16165 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16166 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16167 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16168 inst
.instruction
|= inst
.operands
[2].reg
;
16173 do_mve_viddup (void)
16175 if (inst
.cond
> COND_ALWAYS
)
16176 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16178 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16180 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16181 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16182 _("immediate must be either 1, 2, 4 or 8"));
16184 enum neon_shape rs
;
16185 struct neon_type_el et
;
16187 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16189 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16190 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16195 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16196 if (inst
.operands
[2].reg
== REG_SP
)
16197 as_tsktsk (MVE_BAD_SP
);
16198 else if (inst
.operands
[2].reg
== REG_PC
)
16199 first_error (BAD_PC
);
16201 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16202 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16203 Rm
= inst
.operands
[2].reg
>> 1;
16205 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16206 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16207 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16208 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16209 inst
.instruction
|= (imm
> 2) << 7;
16210 inst
.instruction
|= Rm
<< 1;
16211 inst
.instruction
|= (imm
== 2 || imm
== 8);
16216 do_mve_vmlas (void)
16218 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16219 struct neon_type_el et
16220 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16222 if (inst
.operands
[2].reg
== REG_PC
)
16223 as_tsktsk (MVE_BAD_PC
);
16224 else if (inst
.operands
[2].reg
== REG_SP
)
16225 as_tsktsk (MVE_BAD_SP
);
16227 if (inst
.cond
> COND_ALWAYS
)
16228 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16230 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16232 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16233 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16234 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16235 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16236 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16237 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16238 inst
.instruction
|= inst
.operands
[2].reg
;
16243 do_mve_vshll (void)
16245 struct neon_type_el et
16246 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16248 if (inst
.cond
> COND_ALWAYS
)
16249 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16251 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16253 int imm
= inst
.operands
[2].imm
;
16254 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16255 _("immediate value out of range"));
16257 if ((unsigned)imm
== et
.size
)
16259 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16260 inst
.instruction
|= 0x110001;
16264 inst
.instruction
|= (et
.size
+ imm
) << 16;
16265 inst
.instruction
|= 0x800140;
16268 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16269 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16270 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16271 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16272 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16277 do_mve_vshlc (void)
16279 if (inst
.cond
> COND_ALWAYS
)
16280 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16282 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16284 if (inst
.operands
[1].reg
== REG_PC
)
16285 as_tsktsk (MVE_BAD_PC
);
16286 else if (inst
.operands
[1].reg
== REG_SP
)
16287 as_tsktsk (MVE_BAD_SP
);
16289 int imm
= inst
.operands
[2].imm
;
16290 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16292 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16293 inst
.instruction
|= (imm
& 0x1f) << 16;
16294 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16295 inst
.instruction
|= inst
.operands
[1].reg
;
16300 do_mve_vshrn (void)
16303 switch (inst
.instruction
)
16305 case M_MNEM_vshrnt
:
16306 case M_MNEM_vshrnb
:
16307 case M_MNEM_vrshrnt
:
16308 case M_MNEM_vrshrnb
:
16309 types
= N_I16
| N_I32
;
16311 case M_MNEM_vqshrnt
:
16312 case M_MNEM_vqshrnb
:
16313 case M_MNEM_vqrshrnt
:
16314 case M_MNEM_vqrshrnb
:
16315 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16317 case M_MNEM_vqshrunt
:
16318 case M_MNEM_vqshrunb
:
16319 case M_MNEM_vqrshrunt
:
16320 case M_MNEM_vqrshrunb
:
16321 types
= N_S16
| N_S32
;
16327 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16329 if (inst
.cond
> COND_ALWAYS
)
16330 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16332 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16334 unsigned Qd
= inst
.operands
[0].reg
;
16335 unsigned Qm
= inst
.operands
[1].reg
;
16336 unsigned imm
= inst
.operands
[2].imm
;
16337 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16339 ? _("immediate operand expected in the range [1,8]")
16340 : _("immediate operand expected in the range [1,16]"));
16342 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16343 inst
.instruction
|= HI1 (Qd
) << 22;
16344 inst
.instruction
|= (et
.size
- imm
) << 16;
16345 inst
.instruction
|= LOW4 (Qd
) << 12;
16346 inst
.instruction
|= HI1 (Qm
) << 5;
16347 inst
.instruction
|= LOW4 (Qm
);
16352 do_mve_vqmovn (void)
16354 struct neon_type_el et
;
16355 if (inst
.instruction
== M_MNEM_vqmovnt
16356 || inst
.instruction
== M_MNEM_vqmovnb
)
16357 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16358 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16360 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16362 if (inst
.cond
> COND_ALWAYS
)
16363 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16365 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16367 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16368 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16369 inst
.instruction
|= (et
.size
== 32) << 18;
16370 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16371 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16372 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16377 do_mve_vpsel (void)
16379 neon_select_shape (NS_QQQ
, NS_NULL
);
16381 if (inst
.cond
> COND_ALWAYS
)
16382 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16384 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16386 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16387 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16388 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16389 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16390 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16391 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16396 do_mve_vpnot (void)
16398 if (inst
.cond
> COND_ALWAYS
)
16399 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16401 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16405 do_mve_vmaxnma_vminnma (void)
16407 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16408 struct neon_type_el et
16409 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16411 if (inst
.cond
> COND_ALWAYS
)
16412 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16414 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16416 inst
.instruction
|= (et
.size
== 16) << 28;
16417 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16418 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16419 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16420 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16425 do_mve_vcmul (void)
16427 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16428 struct neon_type_el et
16429 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16431 if (inst
.cond
> COND_ALWAYS
)
16432 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16434 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16436 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16437 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16438 _("immediate out of range"));
16440 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16441 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16442 as_tsktsk (BAD_MVE_SRCDEST
);
16444 inst
.instruction
|= (et
.size
== 32) << 28;
16445 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16446 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16447 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16448 inst
.instruction
|= (rot
> 90) << 12;
16449 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16450 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16451 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16452 inst
.instruction
|= (rot
== 90 || rot
== 270);
16456 /* To handle the Low Overhead Loop instructions
16457 in Armv8.1-M Mainline and MVE. */
16461 unsigned long insn
= inst
.instruction
;
16463 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16465 if (insn
== T_MNEM_lctp
)
16468 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16470 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16472 struct neon_type_el et
16473 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16474 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16481 constraint (!inst
.operands
[0].present
,
16483 /* fall through. */
16486 if (!inst
.operands
[0].present
)
16487 inst
.instruction
|= 1 << 21;
16489 v8_1_loop_reloc (TRUE
);
16494 v8_1_loop_reloc (FALSE
);
16495 /* fall through. */
16498 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16500 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16501 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16502 else if (inst
.operands
[1].reg
== REG_PC
)
16503 as_tsktsk (MVE_BAD_PC
);
16504 if (inst
.operands
[1].reg
== REG_SP
)
16505 as_tsktsk (MVE_BAD_SP
);
16507 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16517 do_vfp_nsyn_cmp (void)
16519 enum neon_shape rs
;
16520 if (!inst
.operands
[0].isreg
)
16527 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16528 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16532 if (inst
.operands
[1].isreg
)
16534 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16535 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16537 if (rs
== NS_FF
|| rs
== NS_HH
)
16539 NEON_ENCODE (SINGLE
, inst
);
16540 do_vfp_sp_monadic ();
16544 NEON_ENCODE (DOUBLE
, inst
);
16545 do_vfp_dp_rd_rm ();
16550 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16551 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16553 switch (inst
.instruction
& 0x0fffffff)
16556 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16559 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16565 if (rs
== NS_FI
|| rs
== NS_HI
)
16567 NEON_ENCODE (SINGLE
, inst
);
16568 do_vfp_sp_compare_z ();
16572 NEON_ENCODE (DOUBLE
, inst
);
16576 do_vfp_cond_or_thumb ();
16578 /* ARMv8.2 fp16 instruction. */
16579 if (rs
== NS_HI
|| rs
== NS_HH
)
16580 do_scalar_fp16_v82_encode ();
16584 nsyn_insert_sp (void)
16586 inst
.operands
[1] = inst
.operands
[0];
16587 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16588 inst
.operands
[0].reg
= REG_SP
;
16589 inst
.operands
[0].isreg
= 1;
16590 inst
.operands
[0].writeback
= 1;
16591 inst
.operands
[0].present
= 1;
16594 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16595 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16598 neon_dp_fixup (struct arm_it
* insn
)
16600 unsigned int i
= insn
->instruction
;
16605 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16616 insn
->instruction
= i
;
16620 mve_encode_qqr (int size
, int U
, int fp
)
16622 if (inst
.operands
[2].reg
== REG_SP
)
16623 as_tsktsk (MVE_BAD_SP
);
16624 else if (inst
.operands
[2].reg
== REG_PC
)
16625 as_tsktsk (MVE_BAD_PC
);
16630 if (((unsigned)inst
.instruction
) == 0xd00)
16631 inst
.instruction
= 0xee300f40;
16633 else if (((unsigned)inst
.instruction
) == 0x200d00)
16634 inst
.instruction
= 0xee301f40;
16636 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16637 inst
.instruction
= 0xee310e60;
16639 /* Setting size which is 1 for F16 and 0 for F32. */
16640 inst
.instruction
|= (size
== 16) << 28;
16645 if (((unsigned)inst
.instruction
) == 0x800)
16646 inst
.instruction
= 0xee010f40;
16648 else if (((unsigned)inst
.instruction
) == 0x1000800)
16649 inst
.instruction
= 0xee011f40;
16651 else if (((unsigned)inst
.instruction
) == 0)
16652 inst
.instruction
= 0xee000f40;
16654 else if (((unsigned)inst
.instruction
) == 0x200)
16655 inst
.instruction
= 0xee001f40;
16657 else if (((unsigned)inst
.instruction
) == 0x900)
16658 inst
.instruction
= 0xee010e40;
16660 else if (((unsigned)inst
.instruction
) == 0x910)
16661 inst
.instruction
= 0xee011e60;
16663 else if (((unsigned)inst
.instruction
) == 0x10)
16664 inst
.instruction
= 0xee000f60;
16666 else if (((unsigned)inst
.instruction
) == 0x210)
16667 inst
.instruction
= 0xee001f60;
16669 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16670 inst
.instruction
= 0xee000e40;
16672 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16673 inst
.instruction
= 0xee010e60;
16675 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16676 inst
.instruction
= 0xfe010e60;
16679 inst
.instruction
|= U
<< 28;
16681 /* Setting bits for size. */
16682 inst
.instruction
|= neon_logbits (size
) << 20;
16684 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16685 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16686 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16687 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16688 inst
.instruction
|= inst
.operands
[2].reg
;
16693 mve_encode_rqq (unsigned bit28
, unsigned size
)
16695 inst
.instruction
|= bit28
<< 28;
16696 inst
.instruction
|= neon_logbits (size
) << 20;
16697 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16698 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16699 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16700 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16701 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16706 mve_encode_qqq (int ubit
, int size
)
16709 inst
.instruction
|= (ubit
!= 0) << 28;
16710 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16711 inst
.instruction
|= neon_logbits (size
) << 20;
16712 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16713 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16714 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16715 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16716 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16722 mve_encode_rq (unsigned bit28
, unsigned size
)
16724 inst
.instruction
|= bit28
<< 28;
16725 inst
.instruction
|= neon_logbits (size
) << 18;
16726 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16727 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16732 mve_encode_rrqq (unsigned U
, unsigned size
)
16734 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16736 inst
.instruction
|= U
<< 28;
16737 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16738 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16739 inst
.instruction
|= (size
== 32) << 16;
16740 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16741 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16742 inst
.instruction
|= inst
.operands
[3].reg
;
16746 /* Helper function for neon_three_same handling the operands. */
16748 neon_three_args (int isquad
)
16750 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16751 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16752 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16753 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16754 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16755 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16756 inst
.instruction
|= (isquad
!= 0) << 6;
16760 /* Encode insns with bit pattern:
16762 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16763 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16765 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16766 different meaning for some instruction. */
16769 neon_three_same (int isquad
, int ubit
, int size
)
16771 neon_three_args (isquad
);
16772 inst
.instruction
|= (ubit
!= 0) << 24;
16774 inst
.instruction
|= neon_logbits (size
) << 20;
16776 neon_dp_fixup (&inst
);
16779 /* Encode instructions of the form:
16781 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16782 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16784 Don't write size if SIZE == -1. */
16787 neon_two_same (int qbit
, int ubit
, int size
)
16789 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16790 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16791 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16792 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16793 inst
.instruction
|= (qbit
!= 0) << 6;
16794 inst
.instruction
|= (ubit
!= 0) << 24;
16797 inst
.instruction
|= neon_logbits (size
) << 18;
16799 neon_dp_fixup (&inst
);
16802 enum vfp_or_neon_is_neon_bits
16805 NEON_CHECK_ARCH
= 2,
16806 NEON_CHECK_ARCH8
= 4
16809 /* Call this function if an instruction which may have belonged to the VFP or
16810 Neon instruction sets, but turned out to be a Neon instruction (due to the
16811 operand types involved, etc.). We have to check and/or fix-up a couple of
16814 - Make sure the user hasn't attempted to make a Neon instruction
16816 - Alter the value in the condition code field if necessary.
16817 - Make sure that the arch supports Neon instructions.
16819 Which of these operations take place depends on bits from enum
16820 vfp_or_neon_is_neon_bits.
16822 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16823 current instruction's condition is COND_ALWAYS, the condition field is
16824 changed to inst.uncond_value. This is necessary because instructions shared
16825 between VFP and Neon may be conditional for the VFP variants only, and the
16826 unconditional Neon version must have, e.g., 0xF in the condition field. */
16829 vfp_or_neon_is_neon (unsigned check
)
16831 /* Conditions are always legal in Thumb mode (IT blocks). */
16832 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16834 if (inst
.cond
!= COND_ALWAYS
)
16836 first_error (_(BAD_COND
));
16839 if (inst
.uncond_value
!= -1)
16840 inst
.instruction
|= inst
.uncond_value
<< 28;
16844 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16845 || ((check
& NEON_CHECK_ARCH8
)
16846 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16848 first_error (_(BAD_FPU
));
16856 /* Return TRUE if the SIMD instruction is available for the current
16857 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16858 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16859 vfp_or_neon_is_neon for the NEON specific checks. */
16862 check_simd_pred_availability (int fp
, unsigned check
)
16864 if (inst
.cond
> COND_ALWAYS
)
16866 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16868 inst
.error
= BAD_FPU
;
16871 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16873 else if (inst
.cond
< COND_ALWAYS
)
16875 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16876 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16877 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16882 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16883 && vfp_or_neon_is_neon (check
) == FAIL
)
16886 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16887 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16892 /* Neon instruction encoders, in approximate order of appearance. */
16895 do_neon_dyadic_i_su (void)
16897 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16900 enum neon_shape rs
;
16901 struct neon_type_el et
;
16902 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16903 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16905 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16907 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16911 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16913 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16917 do_neon_dyadic_i64_su (void)
16919 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16921 enum neon_shape rs
;
16922 struct neon_type_el et
;
16923 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16925 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16926 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16930 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16931 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16934 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16936 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16940 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16943 unsigned size
= et
.size
>> 3;
16944 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16945 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16946 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16947 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16948 inst
.instruction
|= (isquad
!= 0) << 6;
16949 inst
.instruction
|= immbits
<< 16;
16950 inst
.instruction
|= (size
>> 3) << 7;
16951 inst
.instruction
|= (size
& 0x7) << 19;
16953 inst
.instruction
|= (uval
!= 0) << 24;
16955 neon_dp_fixup (&inst
);
16961 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16964 if (!inst
.operands
[2].isreg
)
16966 enum neon_shape rs
;
16967 struct neon_type_el et
;
16968 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16970 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16971 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16975 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16976 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16978 int imm
= inst
.operands
[2].imm
;
16980 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16981 _("immediate out of range for shift"));
16982 NEON_ENCODE (IMMED
, inst
);
16983 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16987 enum neon_shape rs
;
16988 struct neon_type_el et
;
16989 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16991 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16992 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16996 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16997 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17003 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17004 _("invalid instruction shape"));
17005 if (inst
.operands
[2].reg
== REG_SP
)
17006 as_tsktsk (MVE_BAD_SP
);
17007 else if (inst
.operands
[2].reg
== REG_PC
)
17008 as_tsktsk (MVE_BAD_PC
);
17010 inst
.instruction
= 0xee311e60;
17011 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17012 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17013 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17014 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17015 inst
.instruction
|= inst
.operands
[2].reg
;
17022 /* VSHL/VQSHL 3-register variants have syntax such as:
17024 whereas other 3-register operations encoded by neon_three_same have
17027 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17028 operands[2].reg here. */
17029 tmp
= inst
.operands
[2].reg
;
17030 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17031 inst
.operands
[1].reg
= tmp
;
17032 NEON_ENCODE (INTEGER
, inst
);
17033 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17039 do_neon_qshl (void)
17041 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17044 if (!inst
.operands
[2].isreg
)
17046 enum neon_shape rs
;
17047 struct neon_type_el et
;
17048 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17050 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17051 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
17055 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17056 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17058 int imm
= inst
.operands
[2].imm
;
17060 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17061 _("immediate out of range for shift"));
17062 NEON_ENCODE (IMMED
, inst
);
17063 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
17067 enum neon_shape rs
;
17068 struct neon_type_el et
;
17070 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17072 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17073 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17077 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17078 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17083 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17084 _("invalid instruction shape"));
17085 if (inst
.operands
[2].reg
== REG_SP
)
17086 as_tsktsk (MVE_BAD_SP
);
17087 else if (inst
.operands
[2].reg
== REG_PC
)
17088 as_tsktsk (MVE_BAD_PC
);
17090 inst
.instruction
= 0xee311ee0;
17091 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17092 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17093 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17094 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17095 inst
.instruction
|= inst
.operands
[2].reg
;
17102 /* See note in do_neon_shl. */
17103 tmp
= inst
.operands
[2].reg
;
17104 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17105 inst
.operands
[1].reg
= tmp
;
17106 NEON_ENCODE (INTEGER
, inst
);
17107 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17113 do_neon_rshl (void)
17115 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17118 enum neon_shape rs
;
17119 struct neon_type_el et
;
17120 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17122 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17123 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17127 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17128 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17135 if (inst
.operands
[2].reg
== REG_PC
)
17136 as_tsktsk (MVE_BAD_PC
);
17137 else if (inst
.operands
[2].reg
== REG_SP
)
17138 as_tsktsk (MVE_BAD_SP
);
17140 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17141 _("invalid instruction shape"));
17143 if (inst
.instruction
== 0x0000510)
17144 /* We are dealing with vqrshl. */
17145 inst
.instruction
= 0xee331ee0;
17147 /* We are dealing with vrshl. */
17148 inst
.instruction
= 0xee331e60;
17150 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17151 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17152 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17153 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17154 inst
.instruction
|= inst
.operands
[2].reg
;
17159 tmp
= inst
.operands
[2].reg
;
17160 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17161 inst
.operands
[1].reg
= tmp
;
17162 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17167 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17169 /* Handle .I8 pseudo-instructions. */
17172 /* Unfortunately, this will make everything apart from zero out-of-range.
17173 FIXME is this the intended semantics? There doesn't seem much point in
17174 accepting .I8 if so. */
17175 immediate
|= immediate
<< 8;
17181 if (immediate
== (immediate
& 0x000000ff))
17183 *immbits
= immediate
;
17186 else if (immediate
== (immediate
& 0x0000ff00))
17188 *immbits
= immediate
>> 8;
17191 else if (immediate
== (immediate
& 0x00ff0000))
17193 *immbits
= immediate
>> 16;
17196 else if (immediate
== (immediate
& 0xff000000))
17198 *immbits
= immediate
>> 24;
17201 if ((immediate
& 0xffff) != (immediate
>> 16))
17202 goto bad_immediate
;
17203 immediate
&= 0xffff;
17206 if (immediate
== (immediate
& 0x000000ff))
17208 *immbits
= immediate
;
17211 else if (immediate
== (immediate
& 0x0000ff00))
17213 *immbits
= immediate
>> 8;
17218 first_error (_("immediate value out of range"));
17223 do_neon_logic (void)
17225 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17227 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17229 && !check_simd_pred_availability (FALSE
,
17230 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17232 else if (rs
!= NS_QQQ
17233 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17234 first_error (BAD_FPU
);
17236 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17237 /* U bit and size field were set as part of the bitmask. */
17238 NEON_ENCODE (INTEGER
, inst
);
17239 neon_three_same (neon_quad (rs
), 0, -1);
17243 const int three_ops_form
= (inst
.operands
[2].present
17244 && !inst
.operands
[2].isreg
);
17245 const int immoperand
= (three_ops_form
? 2 : 1);
17246 enum neon_shape rs
= (three_ops_form
17247 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17248 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17249 /* Because neon_select_shape makes the second operand a copy of the first
17250 if the second operand is not present. */
17252 && !check_simd_pred_availability (FALSE
,
17253 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17255 else if (rs
!= NS_QQI
17256 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17257 first_error (BAD_FPU
);
17259 struct neon_type_el et
;
17260 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17261 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17263 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17266 if (et
.type
== NT_invtype
)
17268 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17273 if (three_ops_form
)
17274 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17275 _("first and second operands shall be the same register"));
17277 NEON_ENCODE (IMMED
, inst
);
17279 immbits
= inst
.operands
[immoperand
].imm
;
17282 /* .i64 is a pseudo-op, so the immediate must be a repeating
17284 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17285 inst
.operands
[immoperand
].reg
: 0))
17287 /* Set immbits to an invalid constant. */
17288 immbits
= 0xdeadbeef;
17295 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17299 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17303 /* Pseudo-instruction for VBIC. */
17304 neon_invert_size (&immbits
, 0, et
.size
);
17305 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17309 /* Pseudo-instruction for VORR. */
17310 neon_invert_size (&immbits
, 0, et
.size
);
17311 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17321 inst
.instruction
|= neon_quad (rs
) << 6;
17322 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17323 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17324 inst
.instruction
|= cmode
<< 8;
17325 neon_write_immbits (immbits
);
17327 neon_dp_fixup (&inst
);
17332 do_neon_bitfield (void)
17334 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17335 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17336 neon_three_same (neon_quad (rs
), 0, -1);
17340 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17343 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17344 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17346 if (et
.type
== NT_float
)
17348 NEON_ENCODE (FLOAT
, inst
);
17350 mve_encode_qqr (et
.size
, 0, 1);
17352 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17356 NEON_ENCODE (INTEGER
, inst
);
17358 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17360 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17366 do_neon_dyadic_if_su_d (void)
17368 /* This version only allow D registers, but that constraint is enforced during
17369 operand parsing so we don't need to do anything extra here. */
17370 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17374 do_neon_dyadic_if_i_d (void)
17376 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17377 affected if we specify unsigned args. */
17378 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17382 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17384 constraint (size
< 32, BAD_ADDR_MODE
);
17385 constraint (size
!= elsize
, BAD_EL_TYPE
);
17386 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17387 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17388 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17389 _("destination register and offset register may not be the"
17392 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17399 constraint ((imm
% (size
/ 8) != 0)
17400 || imm
> (0x7f << neon_logbits (size
)),
17401 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17402 " range of +/-[0,508]")
17403 : _("immediate must be a multiple of 8 in the"
17404 " range of +/-[0,1016]"));
17405 inst
.instruction
|= 0x11 << 24;
17406 inst
.instruction
|= add
<< 23;
17407 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17408 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17409 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17410 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17411 inst
.instruction
|= 1 << 12;
17412 inst
.instruction
|= (size
== 64) << 8;
17413 inst
.instruction
&= 0xffffff00;
17414 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17415 inst
.instruction
|= imm
>> neon_logbits (size
);
17419 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17421 unsigned os
= inst
.operands
[1].imm
>> 5;
17422 unsigned type
= inst
.vectype
.el
[0].type
;
17423 constraint (os
!= 0 && size
== 8,
17424 _("can not shift offsets when accessing less than half-word"));
17425 constraint (os
&& os
!= neon_logbits (size
),
17426 _("shift immediate must be 1, 2 or 3 for half-word, word"
17427 " or double-word accesses respectively"));
17428 if (inst
.operands
[1].reg
== REG_PC
)
17429 as_tsktsk (MVE_BAD_PC
);
17434 constraint (elsize
>= 64, BAD_EL_TYPE
);
17437 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17441 constraint (elsize
!= size
, BAD_EL_TYPE
);
17446 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17450 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17451 _("destination register and offset register may not be"
17453 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17454 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17456 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17460 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17463 inst
.instruction
|= 1 << 23;
17464 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17465 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17466 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17467 inst
.instruction
|= neon_logbits (elsize
) << 7;
17468 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17469 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17470 inst
.instruction
|= !!os
;
17474 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17476 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17478 constraint (size
>= 64, BAD_ADDR_MODE
);
17482 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17485 constraint (elsize
!= size
, BAD_EL_TYPE
);
17492 constraint (elsize
!= size
&& type
!= NT_unsigned
17493 && type
!= NT_signed
, BAD_EL_TYPE
);
17497 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17500 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17508 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17513 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17516 constraint (1, _("immediate must be a multiple of 2 in the"
17517 " range of +/-[0,254]"));
17520 constraint (1, _("immediate must be a multiple of 4 in the"
17521 " range of +/-[0,508]"));
17526 if (size
!= elsize
)
17528 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17529 constraint (inst
.operands
[0].reg
> 14,
17530 _("MVE vector register in the range [Q0..Q7] expected"));
17531 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17532 inst
.instruction
|= (size
== 16) << 19;
17533 inst
.instruction
|= neon_logbits (elsize
) << 7;
17537 if (inst
.operands
[1].reg
== REG_PC
)
17538 as_tsktsk (MVE_BAD_PC
);
17539 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17540 as_tsktsk (MVE_BAD_SP
);
17541 inst
.instruction
|= 1 << 12;
17542 inst
.instruction
|= neon_logbits (size
) << 7;
17544 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17545 inst
.instruction
|= add
<< 23;
17546 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17547 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17548 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17549 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17550 inst
.instruction
&= 0xffffff80;
17551 inst
.instruction
|= imm
>> neon_logbits (size
);
17556 do_mve_vstr_vldr (void)
17561 if (inst
.cond
> COND_ALWAYS
)
17562 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17564 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17566 switch (inst
.instruction
)
17573 /* fall through. */
17579 /* fall through. */
17585 /* fall through. */
17591 /* fall through. */
17596 unsigned elsize
= inst
.vectype
.el
[0].size
;
17598 if (inst
.operands
[1].isquad
)
17600 /* We are dealing with [Q, imm]{!} cases. */
17601 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17605 if (inst
.operands
[1].immisreg
== 2)
17607 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17608 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17610 else if (!inst
.operands
[1].immisreg
)
17612 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17613 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17616 constraint (1, BAD_ADDR_MODE
);
17623 do_mve_vst_vld (void)
17625 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17628 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17629 || inst
.relocs
[0].exp
.X_add_number
!= 0
17630 || inst
.operands
[1].immisreg
!= 0,
17632 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17633 if (inst
.operands
[1].reg
== REG_PC
)
17634 as_tsktsk (MVE_BAD_PC
);
17635 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17636 as_tsktsk (MVE_BAD_SP
);
17639 /* These instructions are one of the "exceptions" mentioned in
17640 handle_pred_state. They are MVE instructions that are not VPT compatible
17641 and do not accept a VPT code, thus appending such a code is a syntax
17643 if (inst
.cond
> COND_ALWAYS
)
17644 first_error (BAD_SYNTAX
);
17645 /* If we append a scalar condition code we can set this to
17646 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17647 else if (inst
.cond
< COND_ALWAYS
)
17648 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17650 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17652 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17653 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17654 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17655 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17656 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17661 do_mve_vaddlv (void)
17663 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17664 struct neon_type_el et
17665 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17667 if (et
.type
== NT_invtype
)
17668 first_error (BAD_EL_TYPE
);
17670 if (inst
.cond
> COND_ALWAYS
)
17671 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17673 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17675 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17677 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17678 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17679 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17680 inst
.instruction
|= inst
.operands
[2].reg
;
17685 do_neon_dyadic_if_su (void)
17687 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17688 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17691 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17692 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17693 && et
.type
== NT_float
17694 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17696 if (!check_simd_pred_availability (et
.type
== NT_float
,
17697 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17700 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17704 do_neon_addsub_if_i (void)
17706 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17707 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17710 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17711 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17712 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17714 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17715 /* If we are parsing Q registers and the element types match MVE, which NEON
17716 also supports, then we must check whether this is an instruction that can
17717 be used by both MVE/NEON. This distinction can be made based on whether
17718 they are predicated or not. */
17719 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17721 if (!check_simd_pred_availability (et
.type
== NT_float
,
17722 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17727 /* If they are either in a D register or are using an unsupported. */
17729 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17733 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17734 affected if we specify unsigned args. */
17735 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17738 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17740 V<op> A,B (A is operand 0, B is operand 2)
17745 so handle that case specially. */
17748 neon_exchange_operands (void)
17750 if (inst
.operands
[1].present
)
17752 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17754 /* Swap operands[1] and operands[2]. */
17755 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17756 inst
.operands
[1] = inst
.operands
[2];
17757 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17762 inst
.operands
[1] = inst
.operands
[2];
17763 inst
.operands
[2] = inst
.operands
[0];
17768 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17770 if (inst
.operands
[2].isreg
)
17773 neon_exchange_operands ();
17774 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17778 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17779 struct neon_type_el et
= neon_check_type (2, rs
,
17780 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17782 NEON_ENCODE (IMMED
, inst
);
17783 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17784 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17785 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17786 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17787 inst
.instruction
|= neon_quad (rs
) << 6;
17788 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17789 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17791 neon_dp_fixup (&inst
);
17798 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17802 do_neon_cmp_inv (void)
17804 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17810 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17813 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17814 scalars, which are encoded in 5 bits, M : Rm.
17815 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17816 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17819 Dot Product instructions are similar to multiply instructions except elsize
17820 should always be 32.
17822 This function translates SCALAR, which is GAS's internal encoding of indexed
17823 scalar register, to raw encoding. There is also register and index range
17824 check based on ELSIZE. */
17827 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17829 unsigned regno
= NEON_SCALAR_REG (scalar
);
17830 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17835 if (regno
> 7 || elno
> 3)
17837 return regno
| (elno
<< 3);
17840 if (regno
> 15 || elno
> 1)
17842 return regno
| (elno
<< 4);
17846 first_error (_("scalar out of range for multiply instruction"));
17852 /* Encode multiply / multiply-accumulate scalar instructions. */
17855 neon_mul_mac (struct neon_type_el et
, int ubit
)
17859 /* Give a more helpful error message if we have an invalid type. */
17860 if (et
.type
== NT_invtype
)
17863 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17864 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17865 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17866 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17867 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17868 inst
.instruction
|= LOW4 (scalar
);
17869 inst
.instruction
|= HI1 (scalar
) << 5;
17870 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17871 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17872 inst
.instruction
|= (ubit
!= 0) << 24;
17874 neon_dp_fixup (&inst
);
17878 do_neon_mac_maybe_scalar (void)
17880 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17883 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17886 if (inst
.operands
[2].isscalar
)
17888 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17889 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17890 struct neon_type_el et
= neon_check_type (3, rs
,
17891 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17892 NEON_ENCODE (SCALAR
, inst
);
17893 neon_mul_mac (et
, neon_quad (rs
));
17895 else if (!inst
.operands
[2].isvec
)
17897 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17899 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17900 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17902 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17906 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17907 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17908 affected if we specify unsigned args. */
17909 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17914 do_bfloat_vfma (void)
17916 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17917 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17918 enum neon_shape rs
;
17921 if (inst
.instruction
!= B_MNEM_vfmab
)
17924 inst
.instruction
= B_MNEM_vfmat
;
17927 if (inst
.operands
[2].isscalar
)
17929 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17930 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17932 inst
.instruction
|= (1 << 25);
17933 int index
= inst
.operands
[2].reg
& 0xf;
17934 constraint (!(index
< 4), _("index must be in the range 0 to 3"));
17935 inst
.operands
[2].reg
>>= 4;
17936 constraint (!(inst
.operands
[2].reg
< 8),
17937 _("indexed register must be less than 8"));
17938 neon_three_args (t_bit
);
17939 inst
.instruction
|= ((index
& 1) << 3);
17940 inst
.instruction
|= ((index
& 2) << 4);
17944 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17945 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17946 neon_three_args (t_bit
);
17952 do_neon_fmac (void)
17954 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17955 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17958 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17961 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17963 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17964 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17970 if (inst
.operands
[2].reg
== REG_SP
)
17971 as_tsktsk (MVE_BAD_SP
);
17972 else if (inst
.operands
[2].reg
== REG_PC
)
17973 as_tsktsk (MVE_BAD_PC
);
17975 inst
.instruction
= 0xee310e40;
17976 inst
.instruction
|= (et
.size
== 16) << 28;
17977 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17978 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17979 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17980 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17981 inst
.instruction
|= inst
.operands
[2].reg
;
17988 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17991 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17997 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
17998 inst
.cond
== COND_ALWAYS
)
18000 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18001 inst
.instruction
= N_MNEM_vfma
;
18002 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18004 return do_neon_fmac();
18015 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18016 struct neon_type_el et
= neon_check_type (3, rs
,
18017 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18018 neon_three_same (neon_quad (rs
), 0, et
.size
);
18021 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
18022 same types as the MAC equivalents. The polynomial type for this instruction
18023 is encoded the same as the integer type. */
18028 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
18031 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18034 if (inst
.operands
[2].isscalar
)
18036 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18037 do_neon_mac_maybe_scalar ();
18041 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18043 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18044 struct neon_type_el et
18045 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
18046 if (et
.type
== NT_float
)
18047 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
18050 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
18054 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
18055 neon_dyadic_misc (NT_poly
,
18056 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
18062 do_neon_qdmulh (void)
18064 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18067 if (inst
.operands
[2].isscalar
)
18069 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18070 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18071 struct neon_type_el et
= neon_check_type (3, rs
,
18072 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18073 NEON_ENCODE (SCALAR
, inst
);
18074 neon_mul_mac (et
, neon_quad (rs
));
18078 enum neon_shape rs
;
18079 struct neon_type_el et
;
18080 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18082 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18083 et
= neon_check_type (3, rs
,
18084 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18088 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18089 et
= neon_check_type (3, rs
,
18090 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18093 NEON_ENCODE (INTEGER
, inst
);
18095 mve_encode_qqr (et
.size
, 0, 0);
18097 /* The U bit (rounding) comes from bit mask. */
18098 neon_three_same (neon_quad (rs
), 0, et
.size
);
18103 do_mve_vaddv (void)
18105 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18106 struct neon_type_el et
18107 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18109 if (et
.type
== NT_invtype
)
18110 first_error (BAD_EL_TYPE
);
18112 if (inst
.cond
> COND_ALWAYS
)
18113 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18115 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18117 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18119 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18123 do_mve_vhcadd (void)
18125 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18126 struct neon_type_el et
18127 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18129 if (inst
.cond
> COND_ALWAYS
)
18130 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18132 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18134 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18135 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18137 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18138 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18139 "operand makes instruction UNPREDICTABLE"));
18141 mve_encode_qqq (0, et
.size
);
18142 inst
.instruction
|= (rot
== 270) << 12;
18147 do_mve_vqdmull (void)
18149 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18150 struct neon_type_el et
18151 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18154 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18155 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18156 as_tsktsk (BAD_MVE_SRCDEST
);
18158 if (inst
.cond
> COND_ALWAYS
)
18159 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18161 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18165 mve_encode_qqq (et
.size
== 32, 64);
18166 inst
.instruction
|= 1;
18170 mve_encode_qqr (64, et
.size
== 32, 0);
18171 inst
.instruction
|= 0x3 << 5;
18178 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18179 struct neon_type_el et
18180 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18182 if (et
.type
== NT_invtype
)
18183 first_error (BAD_EL_TYPE
);
18185 if (inst
.cond
> COND_ALWAYS
)
18186 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18188 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18190 mve_encode_qqq (0, 64);
18194 do_mve_vbrsr (void)
18196 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18197 struct neon_type_el et
18198 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18200 if (inst
.cond
> COND_ALWAYS
)
18201 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18203 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18205 mve_encode_qqr (et
.size
, 0, 0);
18211 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18213 if (inst
.cond
> COND_ALWAYS
)
18214 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18216 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18218 mve_encode_qqq (1, 64);
18222 do_mve_vmulh (void)
18224 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18225 struct neon_type_el et
18226 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18228 if (inst
.cond
> COND_ALWAYS
)
18229 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18231 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18233 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18237 do_mve_vqdmlah (void)
18239 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18240 struct neon_type_el et
18241 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18243 if (inst
.cond
> COND_ALWAYS
)
18244 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18246 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18248 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18252 do_mve_vqdmladh (void)
18254 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18255 struct neon_type_el et
18256 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18258 if (inst
.cond
> COND_ALWAYS
)
18259 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18261 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18263 mve_encode_qqq (0, et
.size
);
18268 do_mve_vmull (void)
18271 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18272 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18273 if (inst
.cond
== COND_ALWAYS
18274 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18279 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18286 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18287 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18288 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18290 /* We are dealing with MVE's vmullt. */
18292 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18293 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18294 as_tsktsk (BAD_MVE_SRCDEST
);
18296 if (inst
.cond
> COND_ALWAYS
)
18297 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18299 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18301 if (et
.type
== NT_poly
)
18302 mve_encode_qqq (neon_logbits (et
.size
), 64);
18304 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18309 inst
.instruction
= N_MNEM_vmul
;
18312 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18317 do_mve_vabav (void)
18319 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18324 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18327 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18328 | N_S16
| N_S32
| N_U8
| N_U16
18331 if (inst
.cond
> COND_ALWAYS
)
18332 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18334 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18336 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18340 do_mve_vmladav (void)
18342 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18343 struct neon_type_el et
= neon_check_type (3, rs
,
18344 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18346 if (et
.type
== NT_unsigned
18347 && (inst
.instruction
== M_MNEM_vmladavx
18348 || inst
.instruction
== M_MNEM_vmladavax
18349 || inst
.instruction
== M_MNEM_vmlsdav
18350 || inst
.instruction
== M_MNEM_vmlsdava
18351 || inst
.instruction
== M_MNEM_vmlsdavx
18352 || inst
.instruction
== M_MNEM_vmlsdavax
))
18353 first_error (BAD_SIMD_TYPE
);
18355 constraint (inst
.operands
[2].reg
> 14,
18356 _("MVE vector register in the range [Q0..Q7] expected"));
18358 if (inst
.cond
> COND_ALWAYS
)
18359 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18361 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18363 if (inst
.instruction
== M_MNEM_vmlsdav
18364 || inst
.instruction
== M_MNEM_vmlsdava
18365 || inst
.instruction
== M_MNEM_vmlsdavx
18366 || inst
.instruction
== M_MNEM_vmlsdavax
)
18367 inst
.instruction
|= (et
.size
== 8) << 28;
18369 inst
.instruction
|= (et
.size
== 8) << 8;
18371 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18372 inst
.instruction
|= (et
.size
== 32) << 16;
18376 do_mve_vmlaldav (void)
18378 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18379 struct neon_type_el et
18380 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18381 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18383 if (et
.type
== NT_unsigned
18384 && (inst
.instruction
== M_MNEM_vmlsldav
18385 || inst
.instruction
== M_MNEM_vmlsldava
18386 || inst
.instruction
== M_MNEM_vmlsldavx
18387 || inst
.instruction
== M_MNEM_vmlsldavax
))
18388 first_error (BAD_SIMD_TYPE
);
18390 if (inst
.cond
> COND_ALWAYS
)
18391 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18393 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18395 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18399 do_mve_vrmlaldavh (void)
18401 struct neon_type_el et
;
18402 if (inst
.instruction
== M_MNEM_vrmlsldavh
18403 || inst
.instruction
== M_MNEM_vrmlsldavha
18404 || inst
.instruction
== M_MNEM_vrmlsldavhx
18405 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18407 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18408 if (inst
.operands
[1].reg
== REG_SP
)
18409 as_tsktsk (MVE_BAD_SP
);
18413 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18414 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18415 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18417 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18418 N_U32
| N_S32
| N_KEY
);
18419 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18420 with vmax/min instructions, making the use of SP in assembly really
18421 nonsensical, so instead of issuing a warning like we do for other uses
18422 of SP for the odd register operand we error out. */
18423 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18426 /* Make sure we still check the second operand is an odd one and that PC is
18427 disallowed. This because we are parsing for any GPR operand, to be able
18428 to distinguish between giving a warning or an error for SP as described
18430 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18431 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18433 if (inst
.cond
> COND_ALWAYS
)
18434 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18436 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18438 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18443 do_mve_vmaxnmv (void)
18445 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18446 struct neon_type_el et
18447 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18449 if (inst
.cond
> COND_ALWAYS
)
18450 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18452 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18454 if (inst
.operands
[0].reg
== REG_SP
)
18455 as_tsktsk (MVE_BAD_SP
);
18456 else if (inst
.operands
[0].reg
== REG_PC
)
18457 as_tsktsk (MVE_BAD_PC
);
18459 mve_encode_rq (et
.size
== 16, 64);
18463 do_mve_vmaxv (void)
18465 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18466 struct neon_type_el et
;
18468 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18469 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18471 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18473 if (inst
.cond
> COND_ALWAYS
)
18474 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18476 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18478 if (inst
.operands
[0].reg
== REG_SP
)
18479 as_tsktsk (MVE_BAD_SP
);
18480 else if (inst
.operands
[0].reg
== REG_PC
)
18481 as_tsktsk (MVE_BAD_PC
);
18483 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18488 do_neon_qrdmlah (void)
18490 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18492 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18494 /* Check we're on the correct architecture. */
18495 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18497 = _("instruction form not available on this architecture.");
18498 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18500 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18501 record_feature_use (&fpu_neon_ext_v8_1
);
18503 if (inst
.operands
[2].isscalar
)
18505 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18506 struct neon_type_el et
= neon_check_type (3, rs
,
18507 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18508 NEON_ENCODE (SCALAR
, inst
);
18509 neon_mul_mac (et
, neon_quad (rs
));
18513 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18514 struct neon_type_el et
= neon_check_type (3, rs
,
18515 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18516 NEON_ENCODE (INTEGER
, inst
);
18517 /* The U bit (rounding) comes from bit mask. */
18518 neon_three_same (neon_quad (rs
), 0, et
.size
);
18523 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18524 struct neon_type_el et
18525 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18527 NEON_ENCODE (INTEGER
, inst
);
18528 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18533 do_neon_fcmp_absolute (void)
18535 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18536 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18537 N_F_16_32
| N_KEY
);
18538 /* Size field comes from bit mask. */
18539 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18543 do_neon_fcmp_absolute_inv (void)
18545 neon_exchange_operands ();
18546 do_neon_fcmp_absolute ();
18550 do_neon_step (void)
18552 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18553 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18554 N_F_16_32
| N_KEY
);
18555 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18559 do_neon_abs_neg (void)
18561 enum neon_shape rs
;
18562 struct neon_type_el et
;
18564 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18567 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18568 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18570 if (!check_simd_pred_availability (et
.type
== NT_float
,
18571 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18574 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18575 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18576 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18577 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18578 inst
.instruction
|= neon_quad (rs
) << 6;
18579 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18580 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18582 neon_dp_fixup (&inst
);
18588 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18591 enum neon_shape rs
;
18592 struct neon_type_el et
;
18593 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18595 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18596 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18600 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18601 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18605 int imm
= inst
.operands
[2].imm
;
18606 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18607 _("immediate out of range for insert"));
18608 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18614 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18617 enum neon_shape rs
;
18618 struct neon_type_el et
;
18619 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18621 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18622 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18626 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18627 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18630 int imm
= inst
.operands
[2].imm
;
18631 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18632 _("immediate out of range for insert"));
18633 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18637 do_neon_qshlu_imm (void)
18639 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18642 enum neon_shape rs
;
18643 struct neon_type_el et
;
18644 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18646 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18647 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18651 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18652 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18653 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18656 int imm
= inst
.operands
[2].imm
;
18657 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18658 _("immediate out of range for shift"));
18659 /* Only encodes the 'U present' variant of the instruction.
18660 In this case, signed types have OP (bit 8) set to 0.
18661 Unsigned types have OP set to 1. */
18662 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18663 /* The rest of the bits are the same as other immediate shifts. */
18664 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18668 do_neon_qmovn (void)
18670 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18671 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18672 /* Saturating move where operands can be signed or unsigned, and the
18673 destination has the same signedness. */
18674 NEON_ENCODE (INTEGER
, inst
);
18675 if (et
.type
== NT_unsigned
)
18676 inst
.instruction
|= 0xc0;
18678 inst
.instruction
|= 0x80;
18679 neon_two_same (0, 1, et
.size
/ 2);
18683 do_neon_qmovun (void)
18685 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18686 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18687 /* Saturating move with unsigned results. Operands must be signed. */
18688 NEON_ENCODE (INTEGER
, inst
);
18689 neon_two_same (0, 1, et
.size
/ 2);
18693 do_neon_rshift_sat_narrow (void)
18695 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18696 or unsigned. If operands are unsigned, results must also be unsigned. */
18697 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18698 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18699 int imm
= inst
.operands
[2].imm
;
18700 /* This gets the bounds check, size encoding and immediate bits calculation
18704 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18705 VQMOVN.I<size> <Dd>, <Qm>. */
18708 inst
.operands
[2].present
= 0;
18709 inst
.instruction
= N_MNEM_vqmovn
;
18714 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18715 _("immediate out of range"));
18716 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18720 do_neon_rshift_sat_narrow_u (void)
18722 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18723 or unsigned. If operands are unsigned, results must also be unsigned. */
18724 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18725 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18726 int imm
= inst
.operands
[2].imm
;
18727 /* This gets the bounds check, size encoding and immediate bits calculation
18731 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18732 VQMOVUN.I<size> <Dd>, <Qm>. */
18735 inst
.operands
[2].present
= 0;
18736 inst
.instruction
= N_MNEM_vqmovun
;
18741 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18742 _("immediate out of range"));
18743 /* FIXME: The manual is kind of unclear about what value U should have in
18744 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18746 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18750 do_neon_movn (void)
18752 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18753 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18754 NEON_ENCODE (INTEGER
, inst
);
18755 neon_two_same (0, 1, et
.size
/ 2);
18759 do_neon_rshift_narrow (void)
18761 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18762 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18763 int imm
= inst
.operands
[2].imm
;
18764 /* This gets the bounds check, size encoding and immediate bits calculation
18768 /* If immediate is zero then we are a pseudo-instruction for
18769 VMOVN.I<size> <Dd>, <Qm> */
18772 inst
.operands
[2].present
= 0;
18773 inst
.instruction
= N_MNEM_vmovn
;
18778 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18779 _("immediate out of range for narrowing operation"));
18780 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18784 do_neon_shll (void)
18786 /* FIXME: Type checking when lengthening. */
18787 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18788 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18789 unsigned imm
= inst
.operands
[2].imm
;
18791 if (imm
== et
.size
)
18793 /* Maximum shift variant. */
18794 NEON_ENCODE (INTEGER
, inst
);
18795 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18796 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18797 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18798 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18799 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18801 neon_dp_fixup (&inst
);
18805 /* A more-specific type check for non-max versions. */
18806 et
= neon_check_type (2, NS_QDI
,
18807 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18808 NEON_ENCODE (IMMED
, inst
);
18809 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18813 /* Check the various types for the VCVT instruction, and return which version
18814 the current instruction is. */
18816 #define CVT_FLAVOUR_VAR \
18817 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18818 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18819 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18820 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18821 /* Half-precision conversions. */ \
18822 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18823 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18824 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18825 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18826 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18827 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18828 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18829 Compared with single/double precision variants, only the co-processor \
18830 field is different, so the encoding flow is reused here. */ \
18831 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18832 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18833 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18834 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18835 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18836 /* VFP instructions. */ \
18837 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18838 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18839 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18840 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18841 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18842 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18843 /* VFP instructions with bitshift. */ \
18844 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18845 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18846 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18847 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18848 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18849 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18850 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18851 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18853 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18854 neon_cvt_flavour_##C,
18856 /* The different types of conversions we can do. */
18857 enum neon_cvt_flavour
18860 neon_cvt_flavour_invalid
,
18861 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18866 static enum neon_cvt_flavour
18867 get_neon_cvt_flavour (enum neon_shape rs
)
18869 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18870 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18871 if (et.type != NT_invtype) \
18873 inst.error = NULL; \
18874 return (neon_cvt_flavour_##C); \
18877 struct neon_type_el et
;
18878 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18879 || rs
== NS_FF
) ? N_VFP
: 0;
18880 /* The instruction versions which take an immediate take one register
18881 argument, which is extended to the width of the full register. Thus the
18882 "source" and "destination" registers must have the same width. Hack that
18883 here by making the size equal to the key (wider, in this case) operand. */
18884 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18888 return neon_cvt_flavour_invalid
;
18903 /* Neon-syntax VFP conversions. */
18906 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18908 const char *opname
= 0;
18910 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18911 || rs
== NS_FHI
|| rs
== NS_HFI
)
18913 /* Conversions with immediate bitshift. */
18914 const char *enc
[] =
18916 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18922 if (flavour
< (int) ARRAY_SIZE (enc
))
18924 opname
= enc
[flavour
];
18925 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18926 _("operands 0 and 1 must be the same register"));
18927 inst
.operands
[1] = inst
.operands
[2];
18928 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18933 /* Conversions without bitshift. */
18934 const char *enc
[] =
18936 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18942 if (flavour
< (int) ARRAY_SIZE (enc
))
18943 opname
= enc
[flavour
];
18947 do_vfp_nsyn_opcode (opname
);
18949 /* ARMv8.2 fp16 VCVT instruction. */
18950 if (flavour
== neon_cvt_flavour_s32_f16
18951 || flavour
== neon_cvt_flavour_u32_f16
18952 || flavour
== neon_cvt_flavour_f16_u32
18953 || flavour
== neon_cvt_flavour_f16_s32
)
18954 do_scalar_fp16_v82_encode ();
18958 do_vfp_nsyn_cvtz (void)
18960 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18961 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18962 const char *enc
[] =
18964 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18970 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18971 do_vfp_nsyn_opcode (enc
[flavour
]);
18975 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18976 enum neon_cvt_mode mode
)
18981 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18982 D register operands. */
18983 if (flavour
== neon_cvt_flavour_s32_f64
18984 || flavour
== neon_cvt_flavour_u32_f64
)
18985 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18988 if (flavour
== neon_cvt_flavour_s32_f16
18989 || flavour
== neon_cvt_flavour_u32_f16
)
18990 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18993 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18997 case neon_cvt_flavour_s32_f64
:
19001 case neon_cvt_flavour_s32_f32
:
19005 case neon_cvt_flavour_s32_f16
:
19009 case neon_cvt_flavour_u32_f64
:
19013 case neon_cvt_flavour_u32_f32
:
19017 case neon_cvt_flavour_u32_f16
:
19022 first_error (_("invalid instruction shape"));
19028 case neon_cvt_mode_a
: rm
= 0; break;
19029 case neon_cvt_mode_n
: rm
= 1; break;
19030 case neon_cvt_mode_p
: rm
= 2; break;
19031 case neon_cvt_mode_m
: rm
= 3; break;
19032 default: first_error (_("invalid rounding mode")); return;
19035 NEON_ENCODE (FPV8
, inst
);
19036 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
19037 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
19038 inst
.instruction
|= sz
<< 8;
19040 /* ARMv8.2 fp16 VCVT instruction. */
19041 if (flavour
== neon_cvt_flavour_s32_f16
19042 ||flavour
== neon_cvt_flavour_u32_f16
)
19043 do_scalar_fp16_v82_encode ();
19044 inst
.instruction
|= op
<< 7;
19045 inst
.instruction
|= rm
<< 16;
19046 inst
.instruction
|= 0xf0000000;
19047 inst
.is_neon
= TRUE
;
19051 do_neon_cvt_1 (enum neon_cvt_mode mode
)
19053 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
19054 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
19055 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
19057 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19059 if (flavour
== neon_cvt_flavour_invalid
)
19062 /* PR11109: Handle round-to-zero for VCVT conversions. */
19063 if (mode
== neon_cvt_mode_z
19064 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
19065 && (flavour
== neon_cvt_flavour_s16_f16
19066 || flavour
== neon_cvt_flavour_u16_f16
19067 || flavour
== neon_cvt_flavour_s32_f32
19068 || flavour
== neon_cvt_flavour_u32_f32
19069 || flavour
== neon_cvt_flavour_s32_f64
19070 || flavour
== neon_cvt_flavour_u32_f64
)
19071 && (rs
== NS_FD
|| rs
== NS_FF
))
19073 do_vfp_nsyn_cvtz ();
19077 /* ARMv8.2 fp16 VCVT conversions. */
19078 if (mode
== neon_cvt_mode_z
19079 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19080 && (flavour
== neon_cvt_flavour_s32_f16
19081 || flavour
== neon_cvt_flavour_u32_f16
)
19084 do_vfp_nsyn_cvtz ();
19085 do_scalar_fp16_v82_encode ();
19089 if ((rs
== NS_FD
|| rs
== NS_QQI
) && mode
== neon_cvt_mode_n
19090 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19092 /* We are dealing with vcvt with the 'ne' condition. */
19094 inst
.instruction
= N_MNEM_vcvt
;
19095 do_neon_cvt_1 (neon_cvt_mode_z
);
19099 /* VFP rather than Neon conversions. */
19100 if (flavour
>= neon_cvt_flavour_first_fp
)
19102 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19103 do_vfp_nsyn_cvt (rs
, flavour
);
19105 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19113 if (mode
== neon_cvt_mode_z
19114 && (flavour
== neon_cvt_flavour_f16_s16
19115 || flavour
== neon_cvt_flavour_f16_u16
19116 || flavour
== neon_cvt_flavour_s16_f16
19117 || flavour
== neon_cvt_flavour_u16_f16
19118 || flavour
== neon_cvt_flavour_f32_u32
19119 || flavour
== neon_cvt_flavour_f32_s32
19120 || flavour
== neon_cvt_flavour_s32_f32
19121 || flavour
== neon_cvt_flavour_u32_f32
))
19123 if (!check_simd_pred_availability (TRUE
,
19124 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19127 /* fall through. */
19131 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19132 0x0000100, 0x1000100, 0x0, 0x1000000};
19134 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19135 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19138 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19140 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19141 _("immediate value out of range"));
19144 case neon_cvt_flavour_f16_s16
:
19145 case neon_cvt_flavour_f16_u16
:
19146 case neon_cvt_flavour_s16_f16
:
19147 case neon_cvt_flavour_u16_f16
:
19148 constraint (inst
.operands
[2].imm
> 16,
19149 _("immediate value out of range"));
19151 case neon_cvt_flavour_f32_u32
:
19152 case neon_cvt_flavour_f32_s32
:
19153 case neon_cvt_flavour_s32_f32
:
19154 case neon_cvt_flavour_u32_f32
:
19155 constraint (inst
.operands
[2].imm
> 32,
19156 _("immediate value out of range"));
19159 inst
.error
= BAD_FPU
;
19164 /* Fixed-point conversion with #0 immediate is encoded as an
19165 integer conversion. */
19166 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19168 NEON_ENCODE (IMMED
, inst
);
19169 if (flavour
!= neon_cvt_flavour_invalid
)
19170 inst
.instruction
|= enctab
[flavour
];
19171 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19172 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19173 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19174 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19175 inst
.instruction
|= neon_quad (rs
) << 6;
19176 inst
.instruction
|= 1 << 21;
19177 if (flavour
< neon_cvt_flavour_s16_f16
)
19179 inst
.instruction
|= 1 << 21;
19180 immbits
= 32 - inst
.operands
[2].imm
;
19181 inst
.instruction
|= immbits
<< 16;
19185 inst
.instruction
|= 3 << 20;
19186 immbits
= 16 - inst
.operands
[2].imm
;
19187 inst
.instruction
|= immbits
<< 16;
19188 inst
.instruction
&= ~(1 << 9);
19191 neon_dp_fixup (&inst
);
19196 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19197 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19198 && (flavour
== neon_cvt_flavour_s16_f16
19199 || flavour
== neon_cvt_flavour_u16_f16
19200 || flavour
== neon_cvt_flavour_s32_f32
19201 || flavour
== neon_cvt_flavour_u32_f32
))
19203 if (!check_simd_pred_availability (TRUE
,
19204 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19207 else if (mode
== neon_cvt_mode_z
19208 && (flavour
== neon_cvt_flavour_f16_s16
19209 || flavour
== neon_cvt_flavour_f16_u16
19210 || flavour
== neon_cvt_flavour_s16_f16
19211 || flavour
== neon_cvt_flavour_u16_f16
19212 || flavour
== neon_cvt_flavour_f32_u32
19213 || flavour
== neon_cvt_flavour_f32_s32
19214 || flavour
== neon_cvt_flavour_s32_f32
19215 || flavour
== neon_cvt_flavour_u32_f32
))
19217 if (!check_simd_pred_availability (TRUE
,
19218 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19221 /* fall through. */
19223 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19226 NEON_ENCODE (FLOAT
, inst
);
19227 if (!check_simd_pred_availability (TRUE
,
19228 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19231 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19232 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19233 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19234 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19235 inst
.instruction
|= neon_quad (rs
) << 6;
19236 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19237 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19238 inst
.instruction
|= mode
<< 8;
19239 if (flavour
== neon_cvt_flavour_u16_f16
19240 || flavour
== neon_cvt_flavour_s16_f16
)
19241 /* Mask off the original size bits and reencode them. */
19242 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19245 inst
.instruction
|= 0xfc000000;
19247 inst
.instruction
|= 0xf0000000;
19253 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19254 0x100, 0x180, 0x0, 0x080};
19256 NEON_ENCODE (INTEGER
, inst
);
19258 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19260 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19264 if (flavour
!= neon_cvt_flavour_invalid
)
19265 inst
.instruction
|= enctab
[flavour
];
19267 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19268 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19269 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19270 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19271 inst
.instruction
|= neon_quad (rs
) << 6;
19272 if (flavour
>= neon_cvt_flavour_s16_f16
19273 && flavour
<= neon_cvt_flavour_f16_u16
)
19274 /* Half precision. */
19275 inst
.instruction
|= 1 << 18;
19277 inst
.instruction
|= 2 << 18;
19279 neon_dp_fixup (&inst
);
19284 /* Half-precision conversions for Advanced SIMD -- neon. */
19287 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19291 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19293 as_bad (_("operand size must match register width"));
19298 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19300 as_bad (_("operand size must match register width"));
19306 if (flavour
== neon_cvt_flavour_bf16_f32
)
19308 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19310 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19311 /* VCVT.bf16.f32. */
19312 inst
.instruction
= 0x11b60640;
19315 /* VCVT.f16.f32. */
19316 inst
.instruction
= 0x3b60600;
19319 /* VCVT.f32.f16. */
19320 inst
.instruction
= 0x3b60700;
19322 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19323 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19324 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19325 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19326 neon_dp_fixup (&inst
);
19330 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19331 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19332 do_vfp_nsyn_cvt (rs
, flavour
);
19334 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19339 do_neon_cvtr (void)
19341 do_neon_cvt_1 (neon_cvt_mode_x
);
19347 do_neon_cvt_1 (neon_cvt_mode_z
);
19351 do_neon_cvta (void)
19353 do_neon_cvt_1 (neon_cvt_mode_a
);
19357 do_neon_cvtn (void)
19359 do_neon_cvt_1 (neon_cvt_mode_n
);
19363 do_neon_cvtp (void)
19365 do_neon_cvt_1 (neon_cvt_mode_p
);
19369 do_neon_cvtm (void)
19371 do_neon_cvt_1 (neon_cvt_mode_m
);
19375 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19378 mark_feature_used (&fpu_vfp_ext_armv8
);
19380 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19381 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19382 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19383 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19384 inst
.instruction
|= to
? 0x10000 : 0;
19385 inst
.instruction
|= t
? 0x80 : 0;
19386 inst
.instruction
|= is_double
? 0x100 : 0;
19387 do_vfp_cond_or_thumb ();
19391 do_neon_cvttb_1 (bfd_boolean t
)
19393 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19394 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19398 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19400 int single_to_half
= 0;
19401 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19404 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19406 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19407 && (flavour
== neon_cvt_flavour_u16_f16
19408 || flavour
== neon_cvt_flavour_s16_f16
19409 || flavour
== neon_cvt_flavour_f16_s16
19410 || flavour
== neon_cvt_flavour_f16_u16
19411 || flavour
== neon_cvt_flavour_u32_f32
19412 || flavour
== neon_cvt_flavour_s32_f32
19413 || flavour
== neon_cvt_flavour_f32_s32
19414 || flavour
== neon_cvt_flavour_f32_u32
))
19417 inst
.instruction
= N_MNEM_vcvt
;
19418 set_pred_insn_type (INSIDE_VPT_INSN
);
19419 do_neon_cvt_1 (neon_cvt_mode_z
);
19422 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19423 single_to_half
= 1;
19424 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19426 first_error (BAD_FPU
);
19430 inst
.instruction
= 0xee3f0e01;
19431 inst
.instruction
|= single_to_half
<< 28;
19432 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19433 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19434 inst
.instruction
|= t
<< 12;
19435 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19436 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19439 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19442 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19444 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19447 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19449 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19451 /* The VCVTB and VCVTT instructions with D-register operands
19452 don't work for SP only targets. */
19453 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19457 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19459 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19461 /* The VCVTB and VCVTT instructions with D-register operands
19462 don't work for SP only targets. */
19463 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19467 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19469 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19471 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19473 inst
.instruction
|= (1 << 8);
19474 inst
.instruction
&= ~(1 << 9);
19475 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19482 do_neon_cvtb (void)
19484 do_neon_cvttb_1 (FALSE
);
19489 do_neon_cvtt (void)
19491 do_neon_cvttb_1 (TRUE
);
19495 neon_move_immediate (void)
19497 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19498 struct neon_type_el et
= neon_check_type (2, rs
,
19499 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19500 unsigned immlo
, immhi
= 0, immbits
;
19501 int op
, cmode
, float_p
;
19503 constraint (et
.type
== NT_invtype
,
19504 _("operand size must be specified for immediate VMOV"));
19506 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19507 op
= (inst
.instruction
& (1 << 5)) != 0;
19509 immlo
= inst
.operands
[1].imm
;
19510 if (inst
.operands
[1].regisimm
)
19511 immhi
= inst
.operands
[1].reg
;
19513 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19514 _("immediate has bits set outside the operand size"));
19516 float_p
= inst
.operands
[1].immisfloat
;
19518 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19519 et
.size
, et
.type
)) == FAIL
)
19521 /* Invert relevant bits only. */
19522 neon_invert_size (&immlo
, &immhi
, et
.size
);
19523 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19524 with one or the other; those cases are caught by
19525 neon_cmode_for_move_imm. */
19527 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19528 &op
, et
.size
, et
.type
)) == FAIL
)
19530 first_error (_("immediate out of range"));
19535 inst
.instruction
&= ~(1 << 5);
19536 inst
.instruction
|= op
<< 5;
19538 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19539 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19540 inst
.instruction
|= neon_quad (rs
) << 6;
19541 inst
.instruction
|= cmode
<< 8;
19543 neon_write_immbits (immbits
);
19549 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19552 if (inst
.operands
[1].isreg
)
19554 enum neon_shape rs
;
19555 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19556 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19558 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19560 NEON_ENCODE (INTEGER
, inst
);
19561 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19562 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19563 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19564 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19565 inst
.instruction
|= neon_quad (rs
) << 6;
19569 NEON_ENCODE (IMMED
, inst
);
19570 neon_move_immediate ();
19573 neon_dp_fixup (&inst
);
19575 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19577 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19581 /* Encode instructions of form:
19583 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19584 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19587 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19589 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19590 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19591 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19592 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19593 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19594 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19595 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19596 inst
.instruction
|= neon_logbits (size
) << 20;
19598 neon_dp_fixup (&inst
);
19602 do_neon_dyadic_long (void)
19604 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
19607 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19610 NEON_ENCODE (INTEGER
, inst
);
19611 /* FIXME: Type checking for lengthening op. */
19612 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19613 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19614 neon_mixed_length (et
, et
.size
);
19616 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19617 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19619 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19620 in an IT block with le/lt conditions. */
19622 if (inst
.cond
== 0xf)
19624 else if (inst
.cond
== 0x10)
19627 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19629 if (inst
.instruction
== N_MNEM_vaddl
)
19631 inst
.instruction
= N_MNEM_vadd
;
19632 do_neon_addsub_if_i ();
19634 else if (inst
.instruction
== N_MNEM_vsubl
)
19636 inst
.instruction
= N_MNEM_vsub
;
19637 do_neon_addsub_if_i ();
19639 else if (inst
.instruction
== N_MNEM_vabdl
)
19641 inst
.instruction
= N_MNEM_vabd
;
19642 do_neon_dyadic_if_su ();
19646 first_error (BAD_FPU
);
19650 do_neon_abal (void)
19652 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19653 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19654 neon_mixed_length (et
, et
.size
);
19658 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19660 if (inst
.operands
[2].isscalar
)
19662 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19663 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19664 NEON_ENCODE (SCALAR
, inst
);
19665 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19669 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19670 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19671 NEON_ENCODE (INTEGER
, inst
);
19672 neon_mixed_length (et
, et
.size
);
19677 do_neon_mac_maybe_scalar_long (void)
19679 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19682 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19683 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19686 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19688 unsigned regno
= NEON_SCALAR_REG (scalar
);
19689 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19693 if (regno
> 7 || elno
> 3)
19696 return ((regno
& 0x7)
19697 | ((elno
& 0x1) << 3)
19698 | (((elno
>> 1) & 0x1) << 5));
19702 if (regno
> 15 || elno
> 1)
19705 return (((regno
& 0x1) << 5)
19706 | ((regno
>> 1) & 0x7)
19707 | ((elno
& 0x1) << 3));
19711 first_error (_("scalar out of range for multiply instruction"));
19716 do_neon_fmac_maybe_scalar_long (int subtype
)
19718 enum neon_shape rs
;
19720 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19721 field (bits[21:20]) has different meaning. For scalar index variant, it's
19722 used to differentiate add and subtract, otherwise it's with fixed value
19726 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19727 be a scalar index register. */
19728 if (inst
.operands
[2].isscalar
)
19730 high8
= 0xfe000000;
19733 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19737 high8
= 0xfc000000;
19740 inst
.instruction
|= (0x1 << 23);
19741 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19745 if (inst
.cond
!= COND_ALWAYS
)
19746 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19747 "behaviour is UNPREDICTABLE"));
19749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19752 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19755 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19756 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19757 so we simply pass -1 as size. */
19758 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19759 neon_three_same (quad_p
, 0, size
);
19761 /* Undo neon_dp_fixup. Redo the high eight bits. */
19762 inst
.instruction
&= 0x00ffffff;
19763 inst
.instruction
|= high8
;
19765 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19766 whether the instruction is in Q form and whether Vm is a scalar indexed
19768 if (inst
.operands
[2].isscalar
)
19771 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19772 inst
.instruction
&= 0xffffffd0;
19773 inst
.instruction
|= rm
;
19777 /* Redo Rn as well. */
19778 inst
.instruction
&= 0xfff0ff7f;
19779 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19780 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19785 /* Redo Rn and Rm. */
19786 inst
.instruction
&= 0xfff0ff50;
19787 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19788 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19789 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19790 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19795 do_neon_vfmal (void)
19797 return do_neon_fmac_maybe_scalar_long (0);
19801 do_neon_vfmsl (void)
19803 return do_neon_fmac_maybe_scalar_long (1);
19807 do_neon_dyadic_wide (void)
19809 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19810 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19811 neon_mixed_length (et
, et
.size
);
19815 do_neon_dyadic_narrow (void)
19817 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19818 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19819 /* Operand sign is unimportant, and the U bit is part of the opcode,
19820 so force the operand type to integer. */
19821 et
.type
= NT_integer
;
19822 neon_mixed_length (et
, et
.size
/ 2);
19826 do_neon_mul_sat_scalar_long (void)
19828 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19832 do_neon_vmull (void)
19834 if (inst
.operands
[2].isscalar
)
19835 do_neon_mac_maybe_scalar_long ();
19838 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19839 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19841 if (et
.type
== NT_poly
)
19842 NEON_ENCODE (POLY
, inst
);
19844 NEON_ENCODE (INTEGER
, inst
);
19846 /* For polynomial encoding the U bit must be zero, and the size must
19847 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19848 obviously, as 0b10). */
19851 /* Check we're on the correct architecture. */
19852 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19854 _("Instruction form not available on this architecture.");
19859 neon_mixed_length (et
, et
.size
);
19866 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19867 struct neon_type_el et
= neon_check_type (3, rs
,
19868 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19869 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19871 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19872 _("shift out of range"));
19873 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19874 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19875 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19876 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19877 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19878 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19879 inst
.instruction
|= neon_quad (rs
) << 6;
19880 inst
.instruction
|= imm
<< 8;
19882 neon_dp_fixup (&inst
);
19888 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19891 enum neon_shape rs
;
19892 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19893 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19895 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19897 struct neon_type_el et
= neon_check_type (2, rs
,
19898 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19900 unsigned op
= (inst
.instruction
>> 7) & 3;
19901 /* N (width of reversed regions) is encoded as part of the bitmask. We
19902 extract it here to check the elements to be reversed are smaller.
19903 Otherwise we'd get a reserved instruction. */
19904 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19906 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19907 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19908 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19909 " operands makes instruction UNPREDICTABLE"));
19911 gas_assert (elsize
!= 0);
19912 constraint (et
.size
>= elsize
,
19913 _("elements must be smaller than reversal region"));
19914 neon_two_same (neon_quad (rs
), 1, et
.size
);
19920 if (inst
.operands
[1].isscalar
)
19922 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19924 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19925 struct neon_type_el et
= neon_check_type (2, rs
,
19926 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19927 unsigned sizebits
= et
.size
>> 3;
19928 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19929 int logsize
= neon_logbits (et
.size
);
19930 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19932 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19935 NEON_ENCODE (SCALAR
, inst
);
19936 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19937 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19938 inst
.instruction
|= LOW4 (dm
);
19939 inst
.instruction
|= HI1 (dm
) << 5;
19940 inst
.instruction
|= neon_quad (rs
) << 6;
19941 inst
.instruction
|= x
<< 17;
19942 inst
.instruction
|= sizebits
<< 16;
19944 neon_dp_fixup (&inst
);
19948 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19949 struct neon_type_el et
= neon_check_type (2, rs
,
19950 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19953 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19957 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19960 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19962 if (inst
.operands
[1].reg
== REG_SP
)
19963 as_tsktsk (MVE_BAD_SP
);
19964 else if (inst
.operands
[1].reg
== REG_PC
)
19965 as_tsktsk (MVE_BAD_PC
);
19968 /* Duplicate ARM register to lanes of vector. */
19969 NEON_ENCODE (ARMREG
, inst
);
19972 case 8: inst
.instruction
|= 0x400000; break;
19973 case 16: inst
.instruction
|= 0x000020; break;
19974 case 32: inst
.instruction
|= 0x000000; break;
19977 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19978 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19979 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19980 inst
.instruction
|= neon_quad (rs
) << 21;
19981 /* The encoding for this instruction is identical for the ARM and Thumb
19982 variants, except for the condition field. */
19983 do_vfp_cond_or_thumb ();
19988 do_mve_mov (int toQ
)
19990 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19992 if (inst
.cond
> COND_ALWAYS
)
19993 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19995 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
20004 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
20005 _("Index one must be [2,3] and index two must be two less than"
20007 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
20008 _("General purpose registers may not be the same"));
20009 constraint (inst
.operands
[Rt
].reg
== REG_SP
20010 || inst
.operands
[Rt2
].reg
== REG_SP
,
20012 constraint (inst
.operands
[Rt
].reg
== REG_PC
20013 || inst
.operands
[Rt2
].reg
== REG_PC
,
20016 inst
.instruction
= 0xec000f00;
20017 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
20018 inst
.instruction
|= !!toQ
<< 20;
20019 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
20020 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
20021 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
20022 inst
.instruction
|= inst
.operands
[Rt
].reg
;
20028 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20031 if (inst
.cond
> COND_ALWAYS
)
20032 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20034 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
20036 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
20039 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20040 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
20041 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20042 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20043 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20048 /* VMOV has particularly many variations. It can be one of:
20049 0. VMOV<c><q> <Qd>, <Qm>
20050 1. VMOV<c><q> <Dd>, <Dm>
20051 (Register operations, which are VORR with Rm = Rn.)
20052 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20053 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20055 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20056 (ARM register to scalar.)
20057 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20058 (Two ARM registers to vector.)
20059 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20060 (Scalar to ARM register.)
20061 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20062 (Vector to two ARM registers.)
20063 8. VMOV.F32 <Sd>, <Sm>
20064 9. VMOV.F64 <Dd>, <Dm>
20065 (VFP register moves.)
20066 10. VMOV.F32 <Sd>, #imm
20067 11. VMOV.F64 <Dd>, #imm
20068 (VFP float immediate load.)
20069 12. VMOV <Rd>, <Sm>
20070 (VFP single to ARM reg.)
20071 13. VMOV <Sd>, <Rm>
20072 (ARM reg to VFP single.)
20073 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20074 (Two ARM regs to two VFP singles.)
20075 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20076 (Two VFP singles to two ARM regs.)
20077 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20078 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20079 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20080 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20082 These cases can be disambiguated using neon_select_shape, except cases 1/9
20083 and 3/11 which depend on the operand type too.
20085 All the encoded bits are hardcoded by this function.
20087 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20088 Cases 5, 7 may be used with VFPv2 and above.
20090 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20091 can specify a type where it doesn't make sense to, and is ignored). */
20096 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20097 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20098 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20099 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20101 struct neon_type_el et
;
20102 const char *ldconst
= 0;
20106 case NS_DD
: /* case 1/9. */
20107 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20108 /* It is not an error here if no type is given. */
20111 /* In MVE we interpret the following instructions as same, so ignoring
20112 the following type (float) and size (64) checks.
20113 a: VMOV<c><q> <Dd>, <Dm>
20114 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20115 if ((et
.type
== NT_float
&& et
.size
== 64)
20116 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20118 do_vfp_nsyn_opcode ("fcpyd");
20121 /* fall through. */
20123 case NS_QQ
: /* case 0/1. */
20125 if (!check_simd_pred_availability (FALSE
,
20126 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20128 /* The architecture manual I have doesn't explicitly state which
20129 value the U bit should have for register->register moves, but
20130 the equivalent VORR instruction has U = 0, so do that. */
20131 inst
.instruction
= 0x0200110;
20132 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20133 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20134 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20135 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20136 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20137 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20138 inst
.instruction
|= neon_quad (rs
) << 6;
20140 neon_dp_fixup (&inst
);
20144 case NS_DI
: /* case 3/11. */
20145 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20147 if (et
.type
== NT_float
&& et
.size
== 64)
20149 /* case 11 (fconstd). */
20150 ldconst
= "fconstd";
20151 goto encode_fconstd
;
20153 /* fall through. */
20155 case NS_QI
: /* case 2/3. */
20156 if (!check_simd_pred_availability (FALSE
,
20157 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20159 inst
.instruction
= 0x0800010;
20160 neon_move_immediate ();
20161 neon_dp_fixup (&inst
);
20164 case NS_SR
: /* case 4. */
20166 unsigned bcdebits
= 0;
20168 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20169 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20171 /* .<size> is optional here, defaulting to .32. */
20172 if (inst
.vectype
.elems
== 0
20173 && inst
.operands
[0].vectype
.type
== NT_invtype
20174 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20176 inst
.vectype
.el
[0].type
= NT_untyped
;
20177 inst
.vectype
.el
[0].size
= 32;
20178 inst
.vectype
.elems
= 1;
20181 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20182 logsize
= neon_logbits (et
.size
);
20186 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20187 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20192 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20193 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20197 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20199 if (inst
.operands
[1].reg
== REG_SP
)
20200 as_tsktsk (MVE_BAD_SP
);
20201 else if (inst
.operands
[1].reg
== REG_PC
)
20202 as_tsktsk (MVE_BAD_PC
);
20204 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20206 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20207 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20212 case 8: bcdebits
= 0x8; break;
20213 case 16: bcdebits
= 0x1; break;
20214 case 32: bcdebits
= 0x0; break;
20218 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20220 inst
.instruction
= 0xe000b10;
20221 do_vfp_cond_or_thumb ();
20222 inst
.instruction
|= LOW4 (dn
) << 16;
20223 inst
.instruction
|= HI1 (dn
) << 7;
20224 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20225 inst
.instruction
|= (bcdebits
& 3) << 5;
20226 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20227 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20231 case NS_DRR
: /* case 5 (fmdrr). */
20232 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20233 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20236 inst
.instruction
= 0xc400b10;
20237 do_vfp_cond_or_thumb ();
20238 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20239 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20240 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20241 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20244 case NS_RS
: /* case 6. */
20247 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20248 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20249 unsigned abcdebits
= 0;
20251 /* .<dt> is optional here, defaulting to .32. */
20252 if (inst
.vectype
.elems
== 0
20253 && inst
.operands
[0].vectype
.type
== NT_invtype
20254 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20256 inst
.vectype
.el
[0].type
= NT_untyped
;
20257 inst
.vectype
.el
[0].size
= 32;
20258 inst
.vectype
.elems
= 1;
20261 et
= neon_check_type (2, NS_NULL
,
20262 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20263 logsize
= neon_logbits (et
.size
);
20267 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20268 && vfp_or_neon_is_neon (NEON_CHECK_CC
20269 | NEON_CHECK_ARCH
) == FAIL
)
20274 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20275 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20279 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20281 if (inst
.operands
[0].reg
== REG_SP
)
20282 as_tsktsk (MVE_BAD_SP
);
20283 else if (inst
.operands
[0].reg
== REG_PC
)
20284 as_tsktsk (MVE_BAD_PC
);
20287 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20289 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20290 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20294 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20295 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20296 case 32: abcdebits
= 0x00; break;
20300 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20301 inst
.instruction
= 0xe100b10;
20302 do_vfp_cond_or_thumb ();
20303 inst
.instruction
|= LOW4 (dn
) << 16;
20304 inst
.instruction
|= HI1 (dn
) << 7;
20305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20306 inst
.instruction
|= (abcdebits
& 3) << 5;
20307 inst
.instruction
|= (abcdebits
>> 2) << 21;
20308 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20312 case NS_RRD
: /* case 7 (fmrrd). */
20313 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20314 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20317 inst
.instruction
= 0xc500b10;
20318 do_vfp_cond_or_thumb ();
20319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20320 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20321 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20322 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20325 case NS_FF
: /* case 8 (fcpys). */
20326 do_vfp_nsyn_opcode ("fcpys");
20330 case NS_FI
: /* case 10 (fconsts). */
20331 ldconst
= "fconsts";
20333 if (!inst
.operands
[1].immisfloat
)
20336 /* Immediate has to fit in 8 bits so float is enough. */
20337 float imm
= (float) inst
.operands
[1].imm
;
20338 memcpy (&new_imm
, &imm
, sizeof (float));
20339 /* But the assembly may have been written to provide an integer
20340 bit pattern that equates to a float, so check that the
20341 conversion has worked. */
20342 if (is_quarter_float (new_imm
))
20344 if (is_quarter_float (inst
.operands
[1].imm
))
20345 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20347 inst
.operands
[1].imm
= new_imm
;
20348 inst
.operands
[1].immisfloat
= 1;
20352 if (is_quarter_float (inst
.operands
[1].imm
))
20354 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20355 do_vfp_nsyn_opcode (ldconst
);
20357 /* ARMv8.2 fp16 vmov.f16 instruction. */
20359 do_scalar_fp16_v82_encode ();
20362 first_error (_("immediate out of range"));
20366 case NS_RF
: /* case 12 (fmrs). */
20367 do_vfp_nsyn_opcode ("fmrs");
20368 /* ARMv8.2 fp16 vmov.f16 instruction. */
20370 do_scalar_fp16_v82_encode ();
20374 case NS_FR
: /* case 13 (fmsr). */
20375 do_vfp_nsyn_opcode ("fmsr");
20376 /* ARMv8.2 fp16 vmov.f16 instruction. */
20378 do_scalar_fp16_v82_encode ();
20388 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20389 (one of which is a list), but we have parsed four. Do some fiddling to
20390 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20392 case NS_RRFF
: /* case 14 (fmrrs). */
20393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20394 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20396 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20397 _("VFP registers must be adjacent"));
20398 inst
.operands
[2].imm
= 2;
20399 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20400 do_vfp_nsyn_opcode ("fmrrs");
20403 case NS_FFRR
: /* case 15 (fmsrr). */
20404 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20405 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20407 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20408 _("VFP registers must be adjacent"));
20409 inst
.operands
[1] = inst
.operands
[2];
20410 inst
.operands
[2] = inst
.operands
[3];
20411 inst
.operands
[0].imm
= 2;
20412 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20413 do_vfp_nsyn_opcode ("fmsrr");
20417 /* neon_select_shape has determined that the instruction
20418 shape is wrong and has already set the error message. */
20429 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20430 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20431 && !inst
.operands
[2].present
))
20433 inst
.instruction
= 0;
20436 set_pred_insn_type (INSIDE_IT_INSN
);
20441 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20444 if (inst
.cond
!= COND_ALWAYS
)
20445 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20447 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20448 | N_S16
| N_U16
| N_KEY
);
20450 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20451 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20452 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20453 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20454 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20455 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20460 do_neon_rshift_round_imm (void)
20462 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20465 enum neon_shape rs
;
20466 struct neon_type_el et
;
20468 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20470 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20471 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20475 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20476 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20478 int imm
= inst
.operands
[2].imm
;
20480 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20483 inst
.operands
[2].present
= 0;
20488 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20489 _("immediate out of range for shift"));
20490 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20495 do_neon_movhf (void)
20497 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20498 constraint (rs
!= NS_HH
, _("invalid suffix"));
20500 if (inst
.cond
!= COND_ALWAYS
)
20504 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20505 " the behaviour is UNPREDICTABLE"));
20509 inst
.error
= BAD_COND
;
20514 do_vfp_sp_monadic ();
20517 inst
.instruction
|= 0xf0000000;
20521 do_neon_movl (void)
20523 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20524 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20525 unsigned sizebits
= et
.size
>> 3;
20526 inst
.instruction
|= sizebits
<< 19;
20527 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20533 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20534 struct neon_type_el et
= neon_check_type (2, rs
,
20535 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20536 NEON_ENCODE (INTEGER
, inst
);
20537 neon_two_same (neon_quad (rs
), 1, et
.size
);
20541 do_neon_zip_uzp (void)
20543 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20544 struct neon_type_el et
= neon_check_type (2, rs
,
20545 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20546 if (rs
== NS_DD
&& et
.size
== 32)
20548 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20549 inst
.instruction
= N_MNEM_vtrn
;
20553 neon_two_same (neon_quad (rs
), 1, et
.size
);
20557 do_neon_sat_abs_neg (void)
20559 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20562 enum neon_shape rs
;
20563 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20564 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20566 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20567 struct neon_type_el et
= neon_check_type (2, rs
,
20568 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20569 neon_two_same (neon_quad (rs
), 1, et
.size
);
20573 do_neon_pair_long (void)
20575 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20576 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20577 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20578 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20579 neon_two_same (neon_quad (rs
), 1, et
.size
);
20583 do_neon_recip_est (void)
20585 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20586 struct neon_type_el et
= neon_check_type (2, rs
,
20587 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20588 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20589 neon_two_same (neon_quad (rs
), 1, et
.size
);
20595 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20598 enum neon_shape rs
;
20599 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20600 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20602 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20604 struct neon_type_el et
= neon_check_type (2, rs
,
20605 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20606 neon_two_same (neon_quad (rs
), 1, et
.size
);
20612 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20615 enum neon_shape rs
;
20616 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20617 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20619 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20621 struct neon_type_el et
= neon_check_type (2, rs
,
20622 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20623 neon_two_same (neon_quad (rs
), 1, et
.size
);
20629 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20630 struct neon_type_el et
= neon_check_type (2, rs
,
20631 N_EQK
| N_INT
, N_8
| N_KEY
);
20632 neon_two_same (neon_quad (rs
), 1, et
.size
);
20638 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20639 neon_two_same (neon_quad (rs
), 1, -1);
20643 do_neon_tbl_tbx (void)
20645 unsigned listlenbits
;
20646 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20648 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20650 first_error (_("bad list length for table lookup"));
20654 listlenbits
= inst
.operands
[1].imm
- 1;
20655 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20656 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20657 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20658 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20659 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20660 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20661 inst
.instruction
|= listlenbits
<< 8;
20663 neon_dp_fixup (&inst
);
20667 do_neon_ldm_stm (void)
20669 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
20670 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20672 /* P, U and L bits are part of bitmask. */
20673 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20674 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20676 if (inst
.operands
[1].issingle
)
20678 do_vfp_nsyn_ldm_stm (is_dbmode
);
20682 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20683 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20685 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20686 _("register list must contain at least 1 and at most 16 "
20689 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20690 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20691 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20692 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20694 inst
.instruction
|= offsetbits
;
20696 do_vfp_cond_or_thumb ();
20700 do_vfp_nsyn_pop (void)
20703 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20704 return do_vfp_nsyn_opcode ("vldm");
20707 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20710 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20711 _("register list must contain at least 1 and at most 16 "
20714 if (inst
.operands
[1].issingle
)
20715 do_vfp_nsyn_opcode ("fldmias");
20717 do_vfp_nsyn_opcode ("fldmiad");
20721 do_vfp_nsyn_push (void)
20724 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20725 return do_vfp_nsyn_opcode ("vstmdb");
20728 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20731 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20732 _("register list must contain at least 1 and at most 16 "
20735 if (inst
.operands
[1].issingle
)
20736 do_vfp_nsyn_opcode ("fstmdbs");
20738 do_vfp_nsyn_opcode ("fstmdbd");
20743 do_neon_ldr_str (void)
20745 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20747 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20748 And is UNPREDICTABLE in thumb mode. */
20750 && inst
.operands
[1].reg
== REG_PC
20751 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20754 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20755 else if (warn_on_deprecated
)
20756 as_tsktsk (_("Use of PC here is deprecated"));
20759 if (inst
.operands
[0].issingle
)
20762 do_vfp_nsyn_opcode ("flds");
20764 do_vfp_nsyn_opcode ("fsts");
20766 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20767 if (inst
.vectype
.el
[0].size
== 16)
20768 do_scalar_fp16_v82_encode ();
20773 do_vfp_nsyn_opcode ("fldd");
20775 do_vfp_nsyn_opcode ("fstd");
20780 do_t_vldr_vstr_sysreg (void)
20782 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20783 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20785 /* Use of PC is UNPREDICTABLE. */
20786 if (inst
.operands
[1].reg
== REG_PC
)
20787 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20789 if (inst
.operands
[1].immisreg
)
20790 inst
.error
= _("instruction does not accept register index");
20792 if (!inst
.operands
[1].isreg
)
20793 inst
.error
= _("instruction does not accept PC-relative addressing");
20795 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20796 inst
.error
= _("immediate value out of range");
20798 inst
.instruction
= 0xec000f80;
20800 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20801 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20802 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20803 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20807 do_vldr_vstr (void)
20809 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20811 /* VLDR/VSTR (System Register). */
20814 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20815 as_bad (_("Instruction not permitted on this architecture"));
20817 do_t_vldr_vstr_sysreg ();
20822 if (!mark_feature_used (&fpu_vfp_ext_v1xd
)
20823 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20824 as_bad (_("Instruction not permitted on this architecture"));
20825 do_neon_ldr_str ();
20829 /* "interleave" version also handles non-interleaving register VLD1/VST1
20833 do_neon_ld_st_interleave (void)
20835 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20836 N_8
| N_16
| N_32
| N_64
);
20837 unsigned alignbits
= 0;
20839 /* The bits in this table go:
20840 0: register stride of one (0) or two (1)
20841 1,2: register list length, minus one (1, 2, 3, 4).
20842 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20843 We use -1 for invalid entries. */
20844 const int typetable
[] =
20846 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20847 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20848 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20849 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20853 if (et
.type
== NT_invtype
)
20856 if (inst
.operands
[1].immisalign
)
20857 switch (inst
.operands
[1].imm
>> 8)
20859 case 64: alignbits
= 1; break;
20861 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20862 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20863 goto bad_alignment
;
20867 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20868 goto bad_alignment
;
20873 first_error (_("bad alignment"));
20877 inst
.instruction
|= alignbits
<< 4;
20878 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20880 /* Bits [4:6] of the immediate in a list specifier encode register stride
20881 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20882 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20883 up the right value for "type" in a table based on this value and the given
20884 list style, then stick it back. */
20885 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20886 | (((inst
.instruction
>> 8) & 3) << 3);
20888 typebits
= typetable
[idx
];
20890 constraint (typebits
== -1, _("bad list type for instruction"));
20891 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20894 inst
.instruction
&= ~0xf00;
20895 inst
.instruction
|= typebits
<< 8;
20898 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20899 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20900 otherwise. The variable arguments are a list of pairs of legal (size, align)
20901 values, terminated with -1. */
20904 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20907 int result
= FAIL
, thissize
, thisalign
;
20909 if (!inst
.operands
[1].immisalign
)
20915 va_start (ap
, do_alignment
);
20919 thissize
= va_arg (ap
, int);
20920 if (thissize
== -1)
20922 thisalign
= va_arg (ap
, int);
20924 if (size
== thissize
&& align
== thisalign
)
20927 while (result
!= SUCCESS
);
20931 if (result
== SUCCESS
)
20934 first_error (_("unsupported alignment for instruction"));
20940 do_neon_ld_st_lane (void)
20942 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20943 int align_good
, do_alignment
= 0;
20944 int logsize
= neon_logbits (et
.size
);
20945 int align
= inst
.operands
[1].imm
>> 8;
20946 int n
= (inst
.instruction
>> 8) & 3;
20947 int max_el
= 64 / et
.size
;
20949 if (et
.type
== NT_invtype
)
20952 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20953 _("bad list length"));
20954 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20955 _("scalar index out of range"));
20956 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20958 _("stride of 2 unavailable when element size is 8"));
20962 case 0: /* VLD1 / VST1. */
20963 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20965 if (align_good
== FAIL
)
20969 unsigned alignbits
= 0;
20972 case 16: alignbits
= 0x1; break;
20973 case 32: alignbits
= 0x3; break;
20976 inst
.instruction
|= alignbits
<< 4;
20980 case 1: /* VLD2 / VST2. */
20981 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20982 16, 32, 32, 64, -1);
20983 if (align_good
== FAIL
)
20986 inst
.instruction
|= 1 << 4;
20989 case 2: /* VLD3 / VST3. */
20990 constraint (inst
.operands
[1].immisalign
,
20991 _("can't use alignment with this instruction"));
20994 case 3: /* VLD4 / VST4. */
20995 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20996 16, 64, 32, 64, 32, 128, -1);
20997 if (align_good
== FAIL
)
21001 unsigned alignbits
= 0;
21004 case 8: alignbits
= 0x1; break;
21005 case 16: alignbits
= 0x1; break;
21006 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
21009 inst
.instruction
|= alignbits
<< 4;
21016 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
21017 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21018 inst
.instruction
|= 1 << (4 + logsize
);
21020 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
21021 inst
.instruction
|= logsize
<< 10;
21024 /* Encode single n-element structure to all lanes VLD<n> instructions. */
21027 do_neon_ld_dup (void)
21029 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
21030 int align_good
, do_alignment
= 0;
21032 if (et
.type
== NT_invtype
)
21035 switch ((inst
.instruction
>> 8) & 3)
21037 case 0: /* VLD1. */
21038 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
21039 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21040 &do_alignment
, 16, 16, 32, 32, -1);
21041 if (align_good
== FAIL
)
21043 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
21046 case 2: inst
.instruction
|= 1 << 5; break;
21047 default: first_error (_("bad list length")); return;
21049 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21052 case 1: /* VLD2. */
21053 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21054 &do_alignment
, 8, 16, 16, 32, 32, 64,
21056 if (align_good
== FAIL
)
21058 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
21059 _("bad list length"));
21060 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21061 inst
.instruction
|= 1 << 5;
21062 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21065 case 2: /* VLD3. */
21066 constraint (inst
.operands
[1].immisalign
,
21067 _("can't use alignment with this instruction"));
21068 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
21069 _("bad list length"));
21070 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21071 inst
.instruction
|= 1 << 5;
21072 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21075 case 3: /* VLD4. */
21077 int align
= inst
.operands
[1].imm
>> 8;
21078 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21079 16, 64, 32, 64, 32, 128, -1);
21080 if (align_good
== FAIL
)
21082 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
21083 _("bad list length"));
21084 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21085 inst
.instruction
|= 1 << 5;
21086 if (et
.size
== 32 && align
== 128)
21087 inst
.instruction
|= 0x3 << 6;
21089 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21096 inst
.instruction
|= do_alignment
<< 4;
21099 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21100 apart from bits [11:4]. */
21103 do_neon_ldx_stx (void)
21105 if (inst
.operands
[1].isreg
)
21106 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
21108 switch (NEON_LANE (inst
.operands
[0].imm
))
21110 case NEON_INTERLEAVE_LANES
:
21111 NEON_ENCODE (INTERLV
, inst
);
21112 do_neon_ld_st_interleave ();
21115 case NEON_ALL_LANES
:
21116 NEON_ENCODE (DUP
, inst
);
21117 if (inst
.instruction
== N_INV
)
21119 first_error ("only loads support such operands");
21126 NEON_ENCODE (LANE
, inst
);
21127 do_neon_ld_st_lane ();
21130 /* L bit comes from bit mask. */
21131 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21132 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21133 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21135 if (inst
.operands
[1].postind
)
21137 int postreg
= inst
.operands
[1].imm
& 0xf;
21138 constraint (!inst
.operands
[1].immisreg
,
21139 _("post-index must be a register"));
21140 constraint (postreg
== 0xd || postreg
== 0xf,
21141 _("bad register for post-index"));
21142 inst
.instruction
|= postreg
;
21146 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21147 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21148 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21151 if (inst
.operands
[1].writeback
)
21153 inst
.instruction
|= 0xd;
21156 inst
.instruction
|= 0xf;
21160 inst
.instruction
|= 0xf9000000;
21162 inst
.instruction
|= 0xf4000000;
21167 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21169 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21170 D register operands. */
21171 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21172 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21175 NEON_ENCODE (FPV8
, inst
);
21177 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21179 do_vfp_sp_dyadic ();
21181 /* ARMv8.2 fp16 instruction. */
21183 do_scalar_fp16_v82_encode ();
21186 do_vfp_dp_rd_rn_rm ();
21189 inst
.instruction
|= 0x100;
21191 inst
.instruction
|= 0xf0000000;
21197 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21199 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21200 first_error (_("invalid instruction shape"));
21206 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21207 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21209 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21212 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21215 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21219 do_vrint_1 (enum neon_cvt_mode mode
)
21221 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21222 struct neon_type_el et
;
21227 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21228 D register operands. */
21229 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21230 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21233 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21235 if (et
.type
!= NT_invtype
)
21237 /* VFP encodings. */
21238 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21239 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21240 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21242 NEON_ENCODE (FPV8
, inst
);
21243 if (rs
== NS_FF
|| rs
== NS_HH
)
21244 do_vfp_sp_monadic ();
21246 do_vfp_dp_rd_rm ();
21250 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21251 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21252 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21253 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21254 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21255 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21256 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21260 inst
.instruction
|= (rs
== NS_DD
) << 8;
21261 do_vfp_cond_or_thumb ();
21263 /* ARMv8.2 fp16 vrint instruction. */
21265 do_scalar_fp16_v82_encode ();
21269 /* Neon encodings (or something broken...). */
21271 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21273 if (et
.type
== NT_invtype
)
21276 if (!check_simd_pred_availability (TRUE
,
21277 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21280 NEON_ENCODE (FLOAT
, inst
);
21282 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21283 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21284 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21285 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21286 inst
.instruction
|= neon_quad (rs
) << 6;
21287 /* Mask off the original size bits and reencode them. */
21288 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21289 | neon_logbits (et
.size
) << 18);
21293 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21294 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21295 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21296 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21297 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21298 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21299 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21304 inst
.instruction
|= 0xfc000000;
21306 inst
.instruction
|= 0xf0000000;
21313 do_vrint_1 (neon_cvt_mode_x
);
21319 do_vrint_1 (neon_cvt_mode_z
);
21325 do_vrint_1 (neon_cvt_mode_r
);
21331 do_vrint_1 (neon_cvt_mode_a
);
21337 do_vrint_1 (neon_cvt_mode_n
);
21343 do_vrint_1 (neon_cvt_mode_p
);
21349 do_vrint_1 (neon_cvt_mode_m
);
21353 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21355 unsigned regno
= NEON_SCALAR_REG (opnd
);
21356 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21358 if (elsize
== 16 && elno
< 2 && regno
< 16)
21359 return regno
| (elno
<< 4);
21360 else if (elsize
== 32 && elno
== 0)
21363 first_error (_("scalar out of range"));
21370 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21371 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21372 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21373 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21374 _("expression too complex"));
21375 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21376 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21377 _("immediate out of range"));
21380 if (!check_simd_pred_availability (TRUE
,
21381 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21384 if (inst
.operands
[2].isscalar
)
21386 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21387 first_error (_("invalid instruction shape"));
21388 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21389 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21390 N_KEY
| N_F16
| N_F32
).size
;
21391 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21393 inst
.instruction
= 0xfe000800;
21394 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21395 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21396 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21397 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21398 inst
.instruction
|= LOW4 (m
);
21399 inst
.instruction
|= HI1 (m
) << 5;
21400 inst
.instruction
|= neon_quad (rs
) << 6;
21401 inst
.instruction
|= rot
<< 20;
21402 inst
.instruction
|= (size
== 32) << 23;
21406 enum neon_shape rs
;
21407 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21408 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21410 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21412 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21413 N_KEY
| N_F16
| N_F32
).size
;
21414 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21415 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21416 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21417 as_tsktsk (BAD_MVE_SRCDEST
);
21419 neon_three_same (neon_quad (rs
), 0, -1);
21420 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21421 inst
.instruction
|= 0xfc200800;
21422 inst
.instruction
|= rot
<< 23;
21423 inst
.instruction
|= (size
== 32) << 20;
21430 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21431 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21432 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21433 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21434 _("expression too complex"));
21436 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21437 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21438 enum neon_shape rs
;
21439 struct neon_type_el et
;
21440 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21442 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21443 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21447 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21448 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21450 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21451 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21452 "operand makes instruction UNPREDICTABLE"));
21455 if (et
.type
== NT_invtype
)
21458 if (!check_simd_pred_availability (et
.type
== NT_float
,
21459 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21462 if (et
.type
== NT_float
)
21464 neon_three_same (neon_quad (rs
), 0, -1);
21465 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21466 inst
.instruction
|= 0xfc800800;
21467 inst
.instruction
|= (rot
== 270) << 24;
21468 inst
.instruction
|= (et
.size
== 32) << 20;
21472 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21473 inst
.instruction
= 0xfe000f00;
21474 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21475 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21476 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21477 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21478 inst
.instruction
|= (rot
== 270) << 12;
21479 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21480 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21481 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21486 /* Dot Product instructions encoding support. */
21489 do_neon_dotproduct (int unsigned_p
)
21491 enum neon_shape rs
;
21492 unsigned scalar_oprd2
= 0;
21495 if (inst
.cond
!= COND_ALWAYS
)
21496 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21497 "is UNPREDICTABLE"));
21499 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21502 /* Dot Product instructions are in three-same D/Q register format or the third
21503 operand can be a scalar index register. */
21504 if (inst
.operands
[2].isscalar
)
21506 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21507 high8
= 0xfe000000;
21508 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21512 high8
= 0xfc000000;
21513 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21517 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21519 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21521 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21522 Product instruction, so we pass 0 as the "ubit" parameter. And the
21523 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21524 neon_three_same (neon_quad (rs
), 0, 32);
21526 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21527 different NEON three-same encoding. */
21528 inst
.instruction
&= 0x00ffffff;
21529 inst
.instruction
|= high8
;
21530 /* Encode 'U' bit which indicates signedness. */
21531 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21532 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21533 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21534 the instruction encoding. */
21535 if (inst
.operands
[2].isscalar
)
21537 inst
.instruction
&= 0xffffffd0;
21538 inst
.instruction
|= LOW4 (scalar_oprd2
);
21539 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21543 /* Dot Product instructions for signed integer. */
21546 do_neon_dotproduct_s (void)
21548 return do_neon_dotproduct (0);
21551 /* Dot Product instructions for unsigned integer. */
21554 do_neon_dotproduct_u (void)
21556 return do_neon_dotproduct (1);
21562 enum neon_shape rs
;
21563 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21564 if (inst
.operands
[2].isscalar
)
21566 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21567 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21569 inst
.instruction
|= (1 << 25);
21570 int index
= inst
.operands
[2].reg
& 0xf;
21571 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21572 inst
.operands
[2].reg
>>= 4;
21573 constraint (!(inst
.operands
[2].reg
< 16),
21574 _("indexed register must be less than 16"));
21575 neon_three_args (rs
== NS_QQS
);
21576 inst
.instruction
|= (index
<< 5);
21580 inst
.instruction
|= (1 << 21);
21581 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21582 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21583 neon_three_args (rs
== NS_QQQ
);
21590 enum neon_shape rs
;
21591 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21592 if (inst
.operands
[2].isscalar
)
21594 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21595 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21597 inst
.instruction
|= (1 << 25);
21598 int index
= inst
.operands
[2].reg
& 0xf;
21599 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21600 inst
.operands
[2].reg
>>= 4;
21601 constraint (!(inst
.operands
[2].reg
< 16),
21602 _("indexed register must be less than 16"));
21603 neon_three_args (rs
== NS_QQS
);
21604 inst
.instruction
|= (index
<< 5);
21611 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21612 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21614 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21616 neon_three_args (1);
21623 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21624 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21626 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21628 neon_three_args (1);
21633 check_cde_operand (size_t index
, int is_dual
)
21635 unsigned Rx
= inst
.operands
[index
].reg
;
21636 bfd_boolean isvec
= inst
.operands
[index
].isvec
;
21637 if (is_dual
== 0 && thumb_mode
)
21639 !((Rx
<= 14 && Rx
!= 13) || (Rx
== REG_PC
&& isvec
)),
21640 _("Register must be r0-r14 except r13, or APSR_nzcv."));
21642 constraint ( !((Rx
<= 10 && Rx
% 2 == 0 )),
21643 _("Register must be an even register between r0-r10."));
21647 cde_coproc_enabled (unsigned coproc
)
21651 case 0: return mark_feature_used (&arm_ext_cde0
);
21652 case 1: return mark_feature_used (&arm_ext_cde1
);
21653 case 2: return mark_feature_used (&arm_ext_cde2
);
21654 case 3: return mark_feature_used (&arm_ext_cde3
);
21655 case 4: return mark_feature_used (&arm_ext_cde4
);
21656 case 5: return mark_feature_used (&arm_ext_cde5
);
21657 case 6: return mark_feature_used (&arm_ext_cde6
);
21658 case 7: return mark_feature_used (&arm_ext_cde7
);
21659 default: return FALSE
;
21663 #define cde_coproc_pos 8
21665 cde_handle_coproc (void)
21667 unsigned coproc
= inst
.operands
[0].reg
;
21668 constraint (coproc
> 7, _("CDE Coprocessor must be in range 0-7"));
21669 constraint (!(cde_coproc_enabled (coproc
)), BAD_CDE_COPROC
);
21670 inst
.instruction
|= coproc
<< cde_coproc_pos
;
21672 #undef cde_coproc_pos
21675 cxn_handle_predication (bfd_boolean is_accum
)
21677 if (is_accum
&& conditional_insn ())
21678 set_pred_insn_type (INSIDE_IT_INSN
);
21679 else if (conditional_insn ())
21680 /* conditional_insn essentially checks for a suffix, not whether the
21681 instruction is inside an IT block or not.
21682 The non-accumulator versions should not have suffixes. */
21683 inst
.error
= BAD_SYNTAX
;
21685 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21689 do_custom_instruction_1 (int is_dual
, bfd_boolean is_accum
)
21692 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21696 Rd
= inst
.operands
[1].reg
;
21697 check_cde_operand (1, is_dual
);
21701 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21702 _("cx1d requires consecutive destination registers."));
21703 imm
= inst
.operands
[3].imm
;
21705 else if (is_dual
== 0)
21706 imm
= inst
.operands
[2].imm
;
21710 inst
.instruction
|= Rd
<< 12;
21711 inst
.instruction
|= (imm
& 0x1F80) << 9;
21712 inst
.instruction
|= (imm
& 0x0040) << 1;
21713 inst
.instruction
|= (imm
& 0x003f);
21715 cde_handle_coproc ();
21716 cxn_handle_predication (is_accum
);
21720 do_custom_instruction_2 (int is_dual
, bfd_boolean is_accum
)
21723 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21725 unsigned imm
, Rd
, Rn
;
21727 Rd
= inst
.operands
[1].reg
;
21731 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21732 _("cx2d requires consecutive destination registers."));
21733 imm
= inst
.operands
[4].imm
;
21734 Rn
= inst
.operands
[3].reg
;
21736 else if (is_dual
== 0)
21738 imm
= inst
.operands
[3].imm
;
21739 Rn
= inst
.operands
[2].reg
;
21744 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21745 check_cde_operand (1, is_dual
);
21747 inst
.instruction
|= Rd
<< 12;
21748 inst
.instruction
|= Rn
<< 16;
21750 inst
.instruction
|= (imm
& 0x0380) << 13;
21751 inst
.instruction
|= (imm
& 0x0040) << 1;
21752 inst
.instruction
|= (imm
& 0x003f);
21754 cde_handle_coproc ();
21755 cxn_handle_predication (is_accum
);
21759 do_custom_instruction_3 (int is_dual
, bfd_boolean is_accum
)
21762 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21764 unsigned imm
, Rd
, Rn
, Rm
;
21766 Rd
= inst
.operands
[1].reg
;
21770 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21771 _("cx3d requires consecutive destination registers."));
21772 imm
= inst
.operands
[5].imm
;
21773 Rn
= inst
.operands
[3].reg
;
21774 Rm
= inst
.operands
[4].reg
;
21776 else if (is_dual
== 0)
21778 imm
= inst
.operands
[4].imm
;
21779 Rn
= inst
.operands
[2].reg
;
21780 Rm
= inst
.operands
[3].reg
;
21785 check_cde_operand (1, is_dual
);
21786 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21787 check_cde_operand (3 + is_dual
, /* is_dual = */0);
21789 inst
.instruction
|= Rd
;
21790 inst
.instruction
|= Rn
<< 16;
21791 inst
.instruction
|= Rm
<< 12;
21793 inst
.instruction
|= (imm
& 0x0038) << 17;
21794 inst
.instruction
|= (imm
& 0x0004) << 5;
21795 inst
.instruction
|= (imm
& 0x0003) << 4;
21797 cde_handle_coproc ();
21798 cxn_handle_predication (is_accum
);
21804 return do_custom_instruction_1 (0, 0);
21810 return do_custom_instruction_1 (0, 1);
21816 return do_custom_instruction_1 (1, 0);
21822 return do_custom_instruction_1 (1, 1);
21828 return do_custom_instruction_2 (0, 0);
21834 return do_custom_instruction_2 (0, 1);
21840 return do_custom_instruction_2 (1, 0);
21846 return do_custom_instruction_2 (1, 1);
21852 return do_custom_instruction_3 (0, 0);
21858 return do_custom_instruction_3 (0, 1);
21864 return do_custom_instruction_3 (1, 0);
21870 return do_custom_instruction_3 (1, 1);
21874 vcx_assign_vec_d (unsigned regnum
)
21876 inst
.instruction
|= HI4 (regnum
) << 12;
21877 inst
.instruction
|= LOW1 (regnum
) << 22;
21881 vcx_assign_vec_m (unsigned regnum
)
21883 inst
.instruction
|= HI4 (regnum
);
21884 inst
.instruction
|= LOW1 (regnum
) << 5;
21888 vcx_assign_vec_n (unsigned regnum
)
21890 inst
.instruction
|= HI4 (regnum
) << 16;
21891 inst
.instruction
|= LOW1 (regnum
) << 7;
21894 enum vcx_reg_type
{
21900 static enum vcx_reg_type
21901 vcx_get_reg_type (enum neon_shape ns
)
21903 gas_assert (ns
== NS_PQI
21911 || ns
== NS_PFFFI
);
21912 if (ns
== NS_PQI
|| ns
== NS_PQQI
|| ns
== NS_PQQQI
)
21914 if (ns
== NS_PDI
|| ns
== NS_PDDI
|| ns
== NS_PDDDI
)
21919 #define vcx_size_pos 24
21920 #define vcx_vec_pos 6
21922 vcx_handle_shape (enum vcx_reg_type reg_type
)
21925 if (reg_type
== q_reg
)
21926 inst
.instruction
|= 1 << vcx_vec_pos
;
21927 else if (reg_type
== d_reg
)
21928 inst
.instruction
|= 1 << vcx_size_pos
;
21932 The documentation says that the Q registers are encoded as 2*N in the D:Vd
21933 bits (or equivalent for N and M registers).
21934 Similarly the D registers are encoded as N in D:Vd bits.
21935 While the S registers are encoded as N in the Vd:D bits.
21937 Taking into account the maximum values of these registers we can see a
21938 nicer pattern for calculation:
21939 Q -> 7, D -> 15, S -> 31
21941 If we say that everything is encoded in the Vd:D bits, then we can say
21942 that Q is encoded as 4*N, and D is encoded as 2*N.
21943 This way the bits will end up the same, and calculation is simpler.
21944 (calculation is now:
21945 1. Multiply by a number determined by the register letter.
21946 2. Encode resulting number in Vd:D bits.)
21948 This is made a little more complicated by automatic handling of 'Q'
21949 registers elsewhere, which means the register number is already 2*N where
21950 N is the number the user wrote after the register letter.
21955 #undef vcx_size_pos
21958 vcx_ensure_register_in_range (unsigned R
, enum vcx_reg_type reg_type
)
21960 if (reg_type
== q_reg
)
21962 gas_assert (R
% 2 == 0);
21963 constraint (R
>= 16, _("'q' register must be in range 0-7"));
21965 else if (reg_type
== d_reg
)
21966 constraint (R
>= 16, _("'d' register must be in range 0-15"));
21968 constraint (R
>= 32, _("'s' register must be in range 0-31"));
21971 static void (*vcx_assign_vec
[3]) (unsigned) = {
21978 vcx_handle_register_arguments (unsigned num_registers
,
21979 enum vcx_reg_type reg_type
)
21982 unsigned reg_mult
= vcx_handle_shape (reg_type
);
21983 for (i
= 0; i
< num_registers
; i
++)
21985 R
= inst
.operands
[i
+1].reg
;
21986 vcx_ensure_register_in_range (R
, reg_type
);
21987 if (num_registers
== 3 && i
> 0)
21990 vcx_assign_vec
[1] (R
* reg_mult
);
21992 vcx_assign_vec
[2] (R
* reg_mult
);
21995 vcx_assign_vec
[i
](R
* reg_mult
);
22000 vcx_handle_insn_block (enum vcx_reg_type reg_type
)
22002 if (reg_type
== q_reg
)
22003 if (inst
.cond
> COND_ALWAYS
)
22004 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
22006 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
22007 else if (inst
.cond
== COND_ALWAYS
)
22008 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22010 inst
.error
= BAD_NOT_IT
;
22014 vcx_handle_common_checks (unsigned num_args
, enum neon_shape rs
)
22016 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
22017 cde_handle_coproc ();
22018 enum vcx_reg_type reg_type
= vcx_get_reg_type (rs
);
22019 vcx_handle_register_arguments (num_args
, reg_type
);
22020 vcx_handle_insn_block (reg_type
);
22021 if (reg_type
== q_reg
)
22022 constraint (!mark_feature_used (&mve_ext
),
22023 _("vcx instructions with Q registers require MVE"));
22025 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp
, cpu_variant
)
22026 && mark_feature_used (&armv8m_fp
))
22027 && !mark_feature_used (&mve_ext
),
22028 _("vcx instructions with S or D registers require either MVE"
22029 " or Armv8-M floating point extension."));
22035 enum neon_shape rs
= neon_select_shape (NS_PQI
, NS_PDI
, NS_PFI
, NS_NULL
);
22036 vcx_handle_common_checks (1, rs
);
22038 unsigned imm
= inst
.operands
[2].imm
;
22039 inst
.instruction
|= (imm
& 0x03f);
22040 inst
.instruction
|= (imm
& 0x040) << 1;
22041 inst
.instruction
|= (imm
& 0x780) << 9;
22043 constraint (imm
>= 2048,
22044 _("vcx1 with S or D registers takes immediate within 0-2047"));
22045 inst
.instruction
|= (imm
& 0x800) << 13;
22051 enum neon_shape rs
= neon_select_shape (NS_PQQI
, NS_PDDI
, NS_PFFI
, NS_NULL
);
22052 vcx_handle_common_checks (2, rs
);
22054 unsigned imm
= inst
.operands
[3].imm
;
22055 inst
.instruction
|= (imm
& 0x01) << 4;
22056 inst
.instruction
|= (imm
& 0x02) << 6;
22057 inst
.instruction
|= (imm
& 0x3c) << 14;
22059 constraint (imm
>= 64,
22060 _("vcx2 with S or D registers takes immediate within 0-63"));
22061 inst
.instruction
|= (imm
& 0x40) << 18;
22067 enum neon_shape rs
= neon_select_shape (NS_PQQQI
, NS_PDDDI
, NS_PFFFI
, NS_NULL
);
22068 vcx_handle_common_checks (3, rs
);
22070 unsigned imm
= inst
.operands
[4].imm
;
22071 inst
.instruction
|= (imm
& 0x1) << 4;
22072 inst
.instruction
|= (imm
& 0x6) << 19;
22073 if (rs
!= NS_PQQQI
)
22074 constraint (imm
>= 8,
22075 _("vcx2 with S or D registers takes immediate within 0-7"));
22076 inst
.instruction
|= (imm
& 0x8) << 21;
22079 /* Crypto v1 instructions. */
22081 do_crypto_2op_1 (unsigned elttype
, int op
)
22083 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22085 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
22091 NEON_ENCODE (INTEGER
, inst
);
22092 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
22093 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
22094 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
22095 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
22097 inst
.instruction
|= op
<< 6;
22100 inst
.instruction
|= 0xfc000000;
22102 inst
.instruction
|= 0xf0000000;
22106 do_crypto_3op_1 (int u
, int op
)
22108 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22110 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
22111 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
22116 NEON_ENCODE (INTEGER
, inst
);
22117 neon_three_same (1, u
, 8 << op
);
22123 do_crypto_2op_1 (N_8
, 0);
22129 do_crypto_2op_1 (N_8
, 1);
22135 do_crypto_2op_1 (N_8
, 2);
22141 do_crypto_2op_1 (N_8
, 3);
22147 do_crypto_3op_1 (0, 0);
22153 do_crypto_3op_1 (0, 1);
22159 do_crypto_3op_1 (0, 2);
22165 do_crypto_3op_1 (0, 3);
22171 do_crypto_3op_1 (1, 0);
22177 do_crypto_3op_1 (1, 1);
22181 do_sha256su1 (void)
22183 do_crypto_3op_1 (1, 2);
22189 do_crypto_2op_1 (N_32
, -1);
22195 do_crypto_2op_1 (N_32
, 0);
22199 do_sha256su0 (void)
22201 do_crypto_2op_1 (N_32
, 1);
22205 do_crc32_1 (unsigned int poly
, unsigned int sz
)
22207 unsigned int Rd
= inst
.operands
[0].reg
;
22208 unsigned int Rn
= inst
.operands
[1].reg
;
22209 unsigned int Rm
= inst
.operands
[2].reg
;
22211 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22212 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
22213 inst
.instruction
|= LOW4 (Rn
) << 16;
22214 inst
.instruction
|= LOW4 (Rm
);
22215 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
22216 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
22218 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
22219 as_warn (UNPRED_REG ("r15"));
22261 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
22263 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
22264 do_vfp_sp_dp_cvt ();
22265 do_vfp_cond_or_thumb ();
22271 enum neon_shape rs
;
22272 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22273 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22274 if (inst
.operands
[2].isscalar
)
22276 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
22277 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22279 inst
.instruction
|= (1 << 25);
22280 int index
= inst
.operands
[2].reg
& 0xf;
22281 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
22282 inst
.operands
[2].reg
>>= 4;
22283 constraint (!(inst
.operands
[2].reg
< 16),
22284 _("indexed register must be less than 16"));
22285 neon_three_args (rs
== NS_QQS
);
22286 inst
.instruction
|= (index
<< 5);
22290 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
22291 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22292 neon_three_args (rs
== NS_QQQ
);
22299 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
22300 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22302 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22303 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22305 neon_three_args (1);
22309 /* Overall per-instruction processing. */
22311 /* We need to be able to fix up arbitrary expressions in some statements.
22312 This is so that we can handle symbols that are an arbitrary distance from
22313 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22314 which returns part of an address in a form which will be valid for
22315 a data instruction. We do this by pushing the expression into a symbol
22316 in the expr_section, and creating a fix for that. */
22319 fix_new_arm (fragS
* frag
,
22333 /* Create an absolute valued symbol, so we have something to
22334 refer to in the object file. Unfortunately for us, gas's
22335 generic expression parsing will already have folded out
22336 any use of .set foo/.type foo %function that may have
22337 been used to set type information of the target location,
22338 that's being specified symbolically. We have to presume
22339 the user knows what they are doing. */
22343 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
22345 symbol
= symbol_find_or_make (name
);
22346 S_SET_SEGMENT (symbol
, absolute_section
);
22347 symbol_set_frag (symbol
, &zero_address_frag
);
22348 S_SET_VALUE (symbol
, exp
->X_add_number
);
22349 exp
->X_op
= O_symbol
;
22350 exp
->X_add_symbol
= symbol
;
22351 exp
->X_add_number
= 0;
22357 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
22358 (enum bfd_reloc_code_real
) reloc
);
22362 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
22363 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
22367 /* Mark whether the fix is to a THUMB instruction, or an ARM
22369 new_fix
->tc_fix_data
= thumb_mode
;
22372 /* Create a frg for an instruction requiring relaxation. */
22374 output_relax_insn (void)
22380 /* The size of the instruction is unknown, so tie the debug info to the
22381 start of the instruction. */
22382 dwarf2_emit_insn (0);
22384 switch (inst
.relocs
[0].exp
.X_op
)
22387 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
22388 offset
= inst
.relocs
[0].exp
.X_add_number
;
22392 offset
= inst
.relocs
[0].exp
.X_add_number
;
22395 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
22399 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
22400 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
22401 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
22404 /* Write a 32-bit thumb instruction to buf. */
22406 put_thumb32_insn (char * buf
, unsigned long insn
)
22408 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
22409 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
22413 output_inst (const char * str
)
22419 as_bad ("%s -- `%s'", inst
.error
, str
);
22424 output_relax_insn ();
22427 if (inst
.size
== 0)
22430 to
= frag_more (inst
.size
);
22431 /* PR 9814: Record the thumb mode into the current frag so that we know
22432 what type of NOP padding to use, if necessary. We override any previous
22433 setting so that if the mode has changed then the NOPS that we use will
22434 match the encoding of the last instruction in the frag. */
22435 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22437 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
22439 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
22440 put_thumb32_insn (to
, inst
.instruction
);
22442 else if (inst
.size
> INSN_SIZE
)
22444 gas_assert (inst
.size
== (2 * INSN_SIZE
));
22445 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
22446 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
22449 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
22452 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22454 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
22455 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
22456 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
22457 inst
.relocs
[r
].type
);
22460 dwarf2_emit_insn (inst
.size
);
22464 output_it_inst (int cond
, int mask
, char * to
)
22466 unsigned long instruction
= 0xbf00;
22469 instruction
|= mask
;
22470 instruction
|= cond
<< 4;
22474 to
= frag_more (2);
22476 dwarf2_emit_insn (2);
22480 md_number_to_chars (to
, instruction
, 2);
22485 /* Tag values used in struct asm_opcode's tag field. */
22488 OT_unconditional
, /* Instruction cannot be conditionalized.
22489 The ARM condition field is still 0xE. */
22490 OT_unconditionalF
, /* Instruction cannot be conditionalized
22491 and carries 0xF in its ARM condition field. */
22492 OT_csuffix
, /* Instruction takes a conditional suffix. */
22493 OT_csuffixF
, /* Some forms of the instruction take a scalar
22494 conditional suffix, others place 0xF where the
22495 condition field would be, others take a vector
22496 conditional suffix. */
22497 OT_cinfix3
, /* Instruction takes a conditional infix,
22498 beginning at character index 3. (In
22499 unified mode, it becomes a suffix.) */
22500 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
22501 tsts, cmps, cmns, and teqs. */
22502 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
22503 character index 3, even in unified mode. Used for
22504 legacy instructions where suffix and infix forms
22505 may be ambiguous. */
22506 OT_csuf_or_in3
, /* Instruction takes either a conditional
22507 suffix or an infix at character index 3. */
22508 OT_odd_infix_unc
, /* This is the unconditional variant of an
22509 instruction that takes a conditional infix
22510 at an unusual position. In unified mode,
22511 this variant will accept a suffix. */
22512 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
22513 are the conditional variants of instructions that
22514 take conditional infixes in unusual positions.
22515 The infix appears at character index
22516 (tag - OT_odd_infix_0). These are not accepted
22517 in unified mode. */
22520 /* Subroutine of md_assemble, responsible for looking up the primary
22521 opcode from the mnemonic the user wrote. STR points to the
22522 beginning of the mnemonic.
22524 This is not simply a hash table lookup, because of conditional
22525 variants. Most instructions have conditional variants, which are
22526 expressed with a _conditional affix_ to the mnemonic. If we were
22527 to encode each conditional variant as a literal string in the opcode
22528 table, it would have approximately 20,000 entries.
22530 Most mnemonics take this affix as a suffix, and in unified syntax,
22531 'most' is upgraded to 'all'. However, in the divided syntax, some
22532 instructions take the affix as an infix, notably the s-variants of
22533 the arithmetic instructions. Of those instructions, all but six
22534 have the infix appear after the third character of the mnemonic.
22536 Accordingly, the algorithm for looking up primary opcodes given
22539 1. Look up the identifier in the opcode table.
22540 If we find a match, go to step U.
22542 2. Look up the last two characters of the identifier in the
22543 conditions table. If we find a match, look up the first N-2
22544 characters of the identifier in the opcode table. If we
22545 find a match, go to step CE.
22547 3. Look up the fourth and fifth characters of the identifier in
22548 the conditions table. If we find a match, extract those
22549 characters from the identifier, and look up the remaining
22550 characters in the opcode table. If we find a match, go
22555 U. Examine the tag field of the opcode structure, in case this is
22556 one of the six instructions with its conditional infix in an
22557 unusual place. If it is, the tag tells us where to find the
22558 infix; look it up in the conditions table and set inst.cond
22559 accordingly. Otherwise, this is an unconditional instruction.
22560 Again set inst.cond accordingly. Return the opcode structure.
22562 CE. Examine the tag field to make sure this is an instruction that
22563 should receive a conditional suffix. If it is not, fail.
22564 Otherwise, set inst.cond from the suffix we already looked up,
22565 and return the opcode structure.
22567 CM. Examine the tag field to make sure this is an instruction that
22568 should receive a conditional infix after the third character.
22569 If it is not, fail. Otherwise, undo the edits to the current
22570 line of input and proceed as for case CE. */
22572 static const struct asm_opcode
*
22573 opcode_lookup (char **str
)
22577 const struct asm_opcode
*opcode
;
22578 const struct asm_cond
*cond
;
22581 /* Scan up to the end of the mnemonic, which must end in white space,
22582 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22583 for (base
= end
= *str
; *end
!= '\0'; end
++)
22584 if (*end
== ' ' || *end
== '.')
22590 /* Handle a possible width suffix and/or Neon type suffix. */
22595 /* The .w and .n suffixes are only valid if the unified syntax is in
22597 if (unified_syntax
&& end
[1] == 'w')
22599 else if (unified_syntax
&& end
[1] == 'n')
22604 inst
.vectype
.elems
= 0;
22606 *str
= end
+ offset
;
22608 if (end
[offset
] == '.')
22610 /* See if we have a Neon type suffix (possible in either unified or
22611 non-unified ARM syntax mode). */
22612 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
22615 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
22621 /* Look for unaffixed or special-case affixed mnemonic. */
22622 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22627 if (opcode
->tag
< OT_odd_infix_0
)
22629 inst
.cond
= COND_ALWAYS
;
22633 if (warn_on_deprecated
&& unified_syntax
)
22634 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22635 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
22636 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22639 inst
.cond
= cond
->value
;
22642 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22644 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22646 if (end
- base
< 2)
22649 cond
= (const struct asm_cond
*) str_hash_find_n (arm_vcond_hsh
, affix
, 1);
22650 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22652 /* If this opcode can not be vector predicated then don't accept it with a
22653 vector predication code. */
22654 if (opcode
&& !opcode
->mayBeVecPred
)
22657 if (!opcode
|| !cond
)
22659 /* Cannot have a conditional suffix on a mnemonic of less than two
22661 if (end
- base
< 3)
22664 /* Look for suffixed mnemonic. */
22666 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22667 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22671 if (opcode
&& cond
)
22674 switch (opcode
->tag
)
22676 case OT_cinfix3_legacy
:
22677 /* Ignore conditional suffixes matched on infix only mnemonics. */
22681 case OT_cinfix3_deprecated
:
22682 case OT_odd_infix_unc
:
22683 if (!unified_syntax
)
22685 /* Fall through. */
22689 case OT_csuf_or_in3
:
22690 inst
.cond
= cond
->value
;
22693 case OT_unconditional
:
22694 case OT_unconditionalF
:
22696 inst
.cond
= cond
->value
;
22699 /* Delayed diagnostic. */
22700 inst
.error
= BAD_COND
;
22701 inst
.cond
= COND_ALWAYS
;
22710 /* Cannot have a usual-position infix on a mnemonic of less than
22711 six characters (five would be a suffix). */
22712 if (end
- base
< 6)
22715 /* Look for infixed mnemonic in the usual position. */
22717 cond
= (const struct asm_cond
*) str_hash_find_n (arm_cond_hsh
, affix
, 2);
22721 memcpy (save
, affix
, 2);
22722 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22723 opcode
= (const struct asm_opcode
*) str_hash_find_n (arm_ops_hsh
, base
,
22725 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22726 memcpy (affix
, save
, 2);
22729 && (opcode
->tag
== OT_cinfix3
22730 || opcode
->tag
== OT_cinfix3_deprecated
22731 || opcode
->tag
== OT_csuf_or_in3
22732 || opcode
->tag
== OT_cinfix3_legacy
))
22735 if (warn_on_deprecated
&& unified_syntax
22736 && (opcode
->tag
== OT_cinfix3
22737 || opcode
->tag
== OT_cinfix3_deprecated
))
22738 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22740 inst
.cond
= cond
->value
;
22747 /* This function generates an initial IT instruction, leaving its block
22748 virtually open for the new instructions. Eventually,
22749 the mask will be updated by now_pred_add_mask () each time
22750 a new instruction needs to be included in the IT block.
22751 Finally, the block is closed with close_automatic_it_block ().
22752 The block closure can be requested either from md_assemble (),
22753 a tencode (), or due to a label hook. */
22756 new_automatic_it_block (int cond
)
22758 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22759 now_pred
.mask
= 0x18;
22760 now_pred
.cc
= cond
;
22761 now_pred
.block_length
= 1;
22762 mapping_state (MAP_THUMB
);
22763 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22764 now_pred
.warn_deprecated
= FALSE
;
22765 now_pred
.insn_cond
= TRUE
;
22768 /* Close an automatic IT block.
22769 See comments in new_automatic_it_block (). */
22772 close_automatic_it_block (void)
22774 now_pred
.mask
= 0x10;
22775 now_pred
.block_length
= 0;
22778 /* Update the mask of the current automatically-generated IT
22779 instruction. See comments in new_automatic_it_block (). */
22782 now_pred_add_mask (int cond
)
22784 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22785 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22786 | ((bitvalue) << (nbit)))
22787 const int resulting_bit
= (cond
& 1);
22789 now_pred
.mask
&= 0xf;
22790 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22792 (5 - now_pred
.block_length
));
22793 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22795 ((5 - now_pred
.block_length
) - 1));
22796 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22799 #undef SET_BIT_VALUE
22802 /* The IT blocks handling machinery is accessed through the these functions:
22803 it_fsm_pre_encode () from md_assemble ()
22804 set_pred_insn_type () optional, from the tencode functions
22805 set_pred_insn_type_last () ditto
22806 in_pred_block () ditto
22807 it_fsm_post_encode () from md_assemble ()
22808 force_automatic_it_block_close () from label handling functions
22811 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22812 initializing the IT insn type with a generic initial value depending
22813 on the inst.condition.
22814 2) During the tencode function, two things may happen:
22815 a) The tencode function overrides the IT insn type by
22816 calling either set_pred_insn_type (type) or
22817 set_pred_insn_type_last ().
22818 b) The tencode function queries the IT block state by
22819 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22821 Both set_pred_insn_type and in_pred_block run the internal FSM state
22822 handling function (handle_pred_state), because: a) setting the IT insn
22823 type may incur in an invalid state (exiting the function),
22824 and b) querying the state requires the FSM to be updated.
22825 Specifically we want to avoid creating an IT block for conditional
22826 branches, so it_fsm_pre_encode is actually a guess and we can't
22827 determine whether an IT block is required until the tencode () routine
22828 has decided what type of instruction this actually it.
22829 Because of this, if set_pred_insn_type and in_pred_block have to be
22830 used, set_pred_insn_type has to be called first.
22832 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22833 that determines the insn IT type depending on the inst.cond code.
22834 When a tencode () routine encodes an instruction that can be
22835 either outside an IT block, or, in the case of being inside, has to be
22836 the last one, set_pred_insn_type_last () will determine the proper
22837 IT instruction type based on the inst.cond code. Otherwise,
22838 set_pred_insn_type can be called for overriding that logic or
22839 for covering other cases.
22841 Calling handle_pred_state () may not transition the IT block state to
22842 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22843 still queried. Instead, if the FSM determines that the state should
22844 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22845 after the tencode () function: that's what it_fsm_post_encode () does.
22847 Since in_pred_block () calls the state handling function to get an
22848 updated state, an error may occur (due to invalid insns combination).
22849 In that case, inst.error is set.
22850 Therefore, inst.error has to be checked after the execution of
22851 the tencode () routine.
22853 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22854 any pending state change (if any) that didn't take place in
22855 handle_pred_state () as explained above. */
22858 it_fsm_pre_encode (void)
22860 if (inst
.cond
!= COND_ALWAYS
)
22861 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22863 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22865 now_pred
.state_handled
= 0;
22868 /* IT state FSM handling function. */
22869 /* MVE instructions and non-MVE instructions are handled differently because of
22870 the introduction of VPT blocks.
22871 Specifications say that any non-MVE instruction inside a VPT block is
22872 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22873 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22874 few exceptions we have MVE_UNPREDICABLE_INSN.
22875 The error messages provided depending on the different combinations possible
22876 are described in the cases below:
22877 For 'most' MVE instructions:
22878 1) In an IT block, with an IT code: syntax error
22879 2) In an IT block, with a VPT code: error: must be in a VPT block
22880 3) In an IT block, with no code: warning: UNPREDICTABLE
22881 4) In a VPT block, with an IT code: syntax error
22882 5) In a VPT block, with a VPT code: OK!
22883 6) In a VPT block, with no code: error: missing code
22884 7) Outside a pred block, with an IT code: error: syntax error
22885 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22886 9) Outside a pred block, with no code: OK!
22887 For non-MVE instructions:
22888 10) In an IT block, with an IT code: OK!
22889 11) In an IT block, with a VPT code: syntax error
22890 12) In an IT block, with no code: error: missing code
22891 13) In a VPT block, with an IT code: error: should be in an IT block
22892 14) In a VPT block, with a VPT code: syntax error
22893 15) In a VPT block, with no code: UNPREDICTABLE
22894 16) Outside a pred block, with an IT code: error: should be in an IT block
22895 17) Outside a pred block, with a VPT code: syntax error
22896 18) Outside a pred block, with no code: OK!
22901 handle_pred_state (void)
22903 now_pred
.state_handled
= 1;
22904 now_pred
.insn_cond
= FALSE
;
22906 switch (now_pred
.state
)
22908 case OUTSIDE_PRED_BLOCK
:
22909 switch (inst
.pred_insn_type
)
22911 case MVE_UNPREDICABLE_INSN
:
22912 case MVE_OUTSIDE_PRED_INSN
:
22913 if (inst
.cond
< COND_ALWAYS
)
22915 /* Case 7: Outside a pred block, with an IT code: error: syntax
22917 inst
.error
= BAD_SYNTAX
;
22920 /* Case 9: Outside a pred block, with no code: OK! */
22922 case OUTSIDE_PRED_INSN
:
22923 if (inst
.cond
> COND_ALWAYS
)
22925 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22927 inst
.error
= BAD_SYNTAX
;
22930 /* Case 18: Outside a pred block, with no code: OK! */
22933 case INSIDE_VPT_INSN
:
22934 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22936 inst
.error
= BAD_OUT_VPT
;
22939 case INSIDE_IT_INSN
:
22940 case INSIDE_IT_LAST_INSN
:
22941 if (inst
.cond
< COND_ALWAYS
)
22943 /* Case 16: Outside a pred block, with an IT code: error: should
22944 be in an IT block. */
22945 if (thumb_mode
== 0)
22948 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22949 as_tsktsk (_("Warning: conditional outside an IT block"\
22954 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22955 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22957 /* Automatically generate the IT instruction. */
22958 new_automatic_it_block (inst
.cond
);
22959 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22960 close_automatic_it_block ();
22964 inst
.error
= BAD_OUT_IT
;
22970 else if (inst
.cond
> COND_ALWAYS
)
22972 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22974 inst
.error
= BAD_SYNTAX
;
22979 case IF_INSIDE_IT_LAST_INSN
:
22980 case NEUTRAL_IT_INSN
:
22984 if (inst
.cond
!= COND_ALWAYS
)
22985 first_error (BAD_SYNTAX
);
22986 now_pred
.state
= MANUAL_PRED_BLOCK
;
22987 now_pred
.block_length
= 0;
22988 now_pred
.type
= VECTOR_PRED
;
22992 now_pred
.state
= MANUAL_PRED_BLOCK
;
22993 now_pred
.block_length
= 0;
22994 now_pred
.type
= SCALAR_PRED
;
22999 case AUTOMATIC_PRED_BLOCK
:
23000 /* Three things may happen now:
23001 a) We should increment current it block size;
23002 b) We should close current it block (closing insn or 4 insns);
23003 c) We should close current it block and start a new one (due
23004 to incompatible conditions or
23005 4 insns-length block reached). */
23007 switch (inst
.pred_insn_type
)
23009 case INSIDE_VPT_INSN
:
23011 case MVE_UNPREDICABLE_INSN
:
23012 case MVE_OUTSIDE_PRED_INSN
:
23014 case OUTSIDE_PRED_INSN
:
23015 /* The closure of the block shall happen immediately,
23016 so any in_pred_block () call reports the block as closed. */
23017 force_automatic_it_block_close ();
23020 case INSIDE_IT_INSN
:
23021 case INSIDE_IT_LAST_INSN
:
23022 case IF_INSIDE_IT_LAST_INSN
:
23023 now_pred
.block_length
++;
23025 if (now_pred
.block_length
> 4
23026 || !now_pred_compatible (inst
.cond
))
23028 force_automatic_it_block_close ();
23029 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
23030 new_automatic_it_block (inst
.cond
);
23034 now_pred
.insn_cond
= TRUE
;
23035 now_pred_add_mask (inst
.cond
);
23038 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
23039 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
23040 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
23041 close_automatic_it_block ();
23045 case NEUTRAL_IT_INSN
:
23046 now_pred
.block_length
++;
23047 now_pred
.insn_cond
= TRUE
;
23049 if (now_pred
.block_length
> 4)
23050 force_automatic_it_block_close ();
23052 now_pred_add_mask (now_pred
.cc
& 1);
23056 close_automatic_it_block ();
23057 now_pred
.state
= MANUAL_PRED_BLOCK
;
23062 case MANUAL_PRED_BLOCK
:
23065 if (now_pred
.type
== SCALAR_PRED
)
23067 /* Check conditional suffixes. */
23068 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
23069 now_pred
.mask
<<= 1;
23070 now_pred
.mask
&= 0x1f;
23071 is_last
= (now_pred
.mask
== 0x10);
23075 now_pred
.cc
^= (now_pred
.mask
>> 4);
23076 cond
= now_pred
.cc
+ 0xf;
23077 now_pred
.mask
<<= 1;
23078 now_pred
.mask
&= 0x1f;
23079 is_last
= now_pred
.mask
== 0x10;
23081 now_pred
.insn_cond
= TRUE
;
23083 switch (inst
.pred_insn_type
)
23085 case OUTSIDE_PRED_INSN
:
23086 if (now_pred
.type
== SCALAR_PRED
)
23088 if (inst
.cond
== COND_ALWAYS
)
23090 /* Case 12: In an IT block, with no code: error: missing
23092 inst
.error
= BAD_NOT_IT
;
23095 else if (inst
.cond
> COND_ALWAYS
)
23097 /* Case 11: In an IT block, with a VPT code: syntax error.
23099 inst
.error
= BAD_SYNTAX
;
23102 else if (thumb_mode
)
23104 /* This is for some special cases where a non-MVE
23105 instruction is not allowed in an IT block, such as cbz,
23106 but are put into one with a condition code.
23107 You could argue this should be a syntax error, but we
23108 gave the 'not allowed in IT block' diagnostic in the
23109 past so we will keep doing so. */
23110 inst
.error
= BAD_NOT_IT
;
23117 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
23118 as_tsktsk (MVE_NOT_VPT
);
23121 case MVE_OUTSIDE_PRED_INSN
:
23122 if (now_pred
.type
== SCALAR_PRED
)
23124 if (inst
.cond
== COND_ALWAYS
)
23126 /* Case 3: In an IT block, with no code: warning:
23128 as_tsktsk (MVE_NOT_IT
);
23131 else if (inst
.cond
< COND_ALWAYS
)
23133 /* Case 1: In an IT block, with an IT code: syntax error.
23135 inst
.error
= BAD_SYNTAX
;
23143 if (inst
.cond
< COND_ALWAYS
)
23145 /* Case 4: In a VPT block, with an IT code: syntax error.
23147 inst
.error
= BAD_SYNTAX
;
23150 else if (inst
.cond
== COND_ALWAYS
)
23152 /* Case 6: In a VPT block, with no code: error: missing
23154 inst
.error
= BAD_NOT_VPT
;
23162 case MVE_UNPREDICABLE_INSN
:
23163 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
23165 case INSIDE_IT_INSN
:
23166 if (inst
.cond
> COND_ALWAYS
)
23168 /* Case 11: In an IT block, with a VPT code: syntax error. */
23169 /* Case 14: In a VPT block, with a VPT code: syntax error. */
23170 inst
.error
= BAD_SYNTAX
;
23173 else if (now_pred
.type
== SCALAR_PRED
)
23175 /* Case 10: In an IT block, with an IT code: OK! */
23176 if (cond
!= inst
.cond
)
23178 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
23185 /* Case 13: In a VPT block, with an IT code: error: should be
23187 inst
.error
= BAD_OUT_IT
;
23192 case INSIDE_VPT_INSN
:
23193 if (now_pred
.type
== SCALAR_PRED
)
23195 /* Case 2: In an IT block, with a VPT code: error: must be in a
23197 inst
.error
= BAD_OUT_VPT
;
23200 /* Case 5: In a VPT block, with a VPT code: OK! */
23201 else if (cond
!= inst
.cond
)
23203 inst
.error
= BAD_VPT_COND
;
23207 case INSIDE_IT_LAST_INSN
:
23208 case IF_INSIDE_IT_LAST_INSN
:
23209 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
23211 /* Case 4: In a VPT block, with an IT code: syntax error. */
23212 /* Case 11: In an IT block, with a VPT code: syntax error. */
23213 inst
.error
= BAD_SYNTAX
;
23216 else if (cond
!= inst
.cond
)
23218 inst
.error
= BAD_IT_COND
;
23223 inst
.error
= BAD_BRANCH
;
23228 case NEUTRAL_IT_INSN
:
23229 /* The BKPT instruction is unconditional even in a IT or VPT
23234 if (now_pred
.type
== SCALAR_PRED
)
23236 inst
.error
= BAD_IT_IT
;
23239 /* fall through. */
23241 if (inst
.cond
== COND_ALWAYS
)
23243 /* Executing a VPT/VPST instruction inside an IT block or a
23244 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23246 if (now_pred
.type
== SCALAR_PRED
)
23247 as_tsktsk (MVE_NOT_IT
);
23249 as_tsktsk (MVE_NOT_VPT
);
23254 /* VPT/VPST do not accept condition codes. */
23255 inst
.error
= BAD_SYNTAX
;
23266 struct depr_insn_mask
23268 unsigned long pattern
;
23269 unsigned long mask
;
23270 const char* description
;
23273 /* List of 16-bit instruction patterns deprecated in an IT block in
23275 static const struct depr_insn_mask depr_it_insns
[] = {
23276 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23277 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23278 { 0xa000, 0xb800, N_("ADR") },
23279 { 0x4800, 0xf800, N_("Literal loads") },
23280 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23281 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
23282 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23283 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
23284 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
23289 it_fsm_post_encode (void)
23293 if (!now_pred
.state_handled
)
23294 handle_pred_state ();
23296 if (now_pred
.insn_cond
23297 && warn_on_restrict_it
23298 && !now_pred
.warn_deprecated
23299 && warn_on_deprecated
23300 && (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
23301 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8r
))
23302 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
23304 if (inst
.instruction
>= 0x10000)
23306 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
23307 "performance deprecated in ARMv8-A and ARMv8-R"));
23308 now_pred
.warn_deprecated
= TRUE
;
23312 const struct depr_insn_mask
*p
= depr_it_insns
;
23314 while (p
->mask
!= 0)
23316 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
23318 as_tsktsk (_("IT blocks containing 16-bit Thumb "
23319 "instructions of the following class are "
23320 "performance deprecated in ARMv8-A and "
23321 "ARMv8-R: %s"), p
->description
);
23322 now_pred
.warn_deprecated
= TRUE
;
23330 if (now_pred
.block_length
> 1)
23332 as_tsktsk (_("IT blocks containing more than one conditional "
23333 "instruction are performance deprecated in ARMv8-A and "
23335 now_pred
.warn_deprecated
= TRUE
;
23339 is_last
= (now_pred
.mask
== 0x10);
23342 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23348 force_automatic_it_block_close (void)
23350 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
23352 close_automatic_it_block ();
23353 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23359 in_pred_block (void)
23361 if (!now_pred
.state_handled
)
23362 handle_pred_state ();
23364 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
23367 /* Whether OPCODE only has T32 encoding. Since this function is only used by
23368 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23369 here, hence the "known" in the function name. */
23372 known_t32_only_insn (const struct asm_opcode
*opcode
)
23374 /* Original Thumb-1 wide instruction. */
23375 if (opcode
->tencode
== do_t_blx
23376 || opcode
->tencode
== do_t_branch23
23377 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
23378 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
23381 /* Wide-only instruction added to ARMv8-M Baseline. */
23382 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
23383 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
23384 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
23385 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
23391 /* Whether wide instruction variant can be used if available for a valid OPCODE
23395 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
23397 if (known_t32_only_insn (opcode
))
23400 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
23401 of variant T3 of B.W is checked in do_t_branch. */
23402 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23403 && opcode
->tencode
== do_t_branch
)
23406 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
23407 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23408 && opcode
->tencode
== do_t_mov_cmp
23409 /* Make sure CMP instruction is not affected. */
23410 && opcode
->aencode
== do_mov
)
23413 /* Wide instruction variants of all instructions with narrow *and* wide
23414 variants become available with ARMv6t2. Other opcodes are either
23415 narrow-only or wide-only and are thus available if OPCODE is valid. */
23416 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
23419 /* OPCODE with narrow only instruction variant or wide variant not
23425 md_assemble (char *str
)
23428 const struct asm_opcode
* opcode
;
23430 /* Align the previous label if needed. */
23431 if (last_label_seen
!= NULL
)
23433 symbol_set_frag (last_label_seen
, frag_now
);
23434 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
23435 S_SET_SEGMENT (last_label_seen
, now_seg
);
23438 memset (&inst
, '\0', sizeof (inst
));
23440 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
23441 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
23443 opcode
= opcode_lookup (&p
);
23446 /* It wasn't an instruction, but it might be a register alias of
23447 the form alias .req reg, or a Neon .dn/.qn directive. */
23448 if (! create_register_alias (str
, p
)
23449 && ! create_neon_reg_alias (str
, p
))
23450 as_bad (_("bad instruction `%s'"), str
);
23455 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
23456 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
23458 /* The value which unconditional instructions should have in place of the
23459 condition field. */
23460 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
23464 arm_feature_set variant
;
23466 variant
= cpu_variant
;
23467 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
23468 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
23469 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
23470 /* Check that this instruction is supported for this CPU. */
23471 if (!opcode
->tvariant
23472 || (thumb_mode
== 1
23473 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
23475 if (opcode
->tencode
== do_t_swi
)
23476 as_bad (_("SVC is not permitted on this architecture"));
23478 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
23481 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
23482 && opcode
->tencode
!= do_t_branch
)
23484 as_bad (_("Thumb does not support conditional execution"));
23488 /* Two things are addressed here:
23489 1) Implicit require narrow instructions on Thumb-1.
23490 This avoids relaxation accidentally introducing Thumb-2
23492 2) Reject wide instructions in non Thumb-2 cores.
23494 Only instructions with narrow and wide variants need to be handled
23495 but selecting all non wide-only instructions is easier. */
23496 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
23497 && !t32_insn_ok (variant
, opcode
))
23499 if (inst
.size_req
== 0)
23501 else if (inst
.size_req
== 4)
23503 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
23504 as_bad (_("selected processor does not support 32bit wide "
23505 "variant of instruction `%s'"), str
);
23507 as_bad (_("selected processor does not support `%s' in "
23508 "Thumb-2 mode"), str
);
23513 inst
.instruction
= opcode
->tvalue
;
23515 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
23517 /* Prepare the pred_insn_type for those encodings that don't set
23519 it_fsm_pre_encode ();
23521 opcode
->tencode ();
23523 it_fsm_post_encode ();
23526 if (!(inst
.error
|| inst
.relax
))
23528 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
23529 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
23530 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
23532 as_bad (_("cannot honor width suffix -- `%s'"), str
);
23537 /* Something has gone badly wrong if we try to relax a fixed size
23539 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
23541 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23542 *opcode
->tvariant
);
23543 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23544 set those bits when Thumb-2 32-bit instructions are seen. The impact
23545 of relaxable instructions will be considered later after we finish all
23547 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
23548 variant
= arm_arch_none
;
23550 variant
= cpu_variant
;
23551 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
23552 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23555 check_neon_suffixes
;
23559 mapping_state (MAP_THUMB
);
23562 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23566 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23567 is_bx
= (opcode
->aencode
== do_bx
);
23569 /* Check that this instruction is supported for this CPU. */
23570 if (!(is_bx
&& fix_v4bx
)
23571 && !(opcode
->avariant
&&
23572 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
23574 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
23579 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
23583 inst
.instruction
= opcode
->avalue
;
23584 if (opcode
->tag
== OT_unconditionalF
)
23585 inst
.instruction
|= 0xFU
<< 28;
23587 inst
.instruction
|= inst
.cond
<< 28;
23588 inst
.size
= INSN_SIZE
;
23589 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
23591 it_fsm_pre_encode ();
23592 opcode
->aencode ();
23593 it_fsm_post_encode ();
23595 /* Arm mode bx is marked as both v4T and v5 because it's still required
23596 on a hypothetical non-thumb v5 core. */
23598 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
23600 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
23601 *opcode
->avariant
);
23603 check_neon_suffixes
;
23607 mapping_state (MAP_ARM
);
23612 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23620 check_pred_blocks_finished (void)
23625 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
23626 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
23627 == MANUAL_PRED_BLOCK
)
23629 if (now_pred
.type
== SCALAR_PRED
)
23630 as_warn (_("section '%s' finished with an open IT block."),
23633 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23637 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
23639 if (now_pred
.type
== SCALAR_PRED
)
23640 as_warn (_("file finished with an open IT block."));
23642 as_warn (_("file finished with an open VPT/VPST block."));
23647 /* Various frobbings of labels and their addresses. */
23650 arm_start_line_hook (void)
23652 last_label_seen
= NULL
;
23656 arm_frob_label (symbolS
* sym
)
23658 last_label_seen
= sym
;
23660 ARM_SET_THUMB (sym
, thumb_mode
);
23662 #if defined OBJ_COFF || defined OBJ_ELF
23663 ARM_SET_INTERWORK (sym
, support_interwork
);
23666 force_automatic_it_block_close ();
23668 /* Note - do not allow local symbols (.Lxxx) to be labelled
23669 as Thumb functions. This is because these labels, whilst
23670 they exist inside Thumb code, are not the entry points for
23671 possible ARM->Thumb calls. Also, these labels can be used
23672 as part of a computed goto or switch statement. eg gcc
23673 can generate code that looks like this:
23675 ldr r2, [pc, .Laaa]
23685 The first instruction loads the address of the jump table.
23686 The second instruction converts a table index into a byte offset.
23687 The third instruction gets the jump address out of the table.
23688 The fourth instruction performs the jump.
23690 If the address stored at .Laaa is that of a symbol which has the
23691 Thumb_Func bit set, then the linker will arrange for this address
23692 to have the bottom bit set, which in turn would mean that the
23693 address computation performed by the third instruction would end
23694 up with the bottom bit set. Since the ARM is capable of unaligned
23695 word loads, the instruction would then load the incorrect address
23696 out of the jump table, and chaos would ensue. */
23697 if (label_is_thumb_function_name
23698 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23699 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23701 /* When the address of a Thumb function is taken the bottom
23702 bit of that address should be set. This will allow
23703 interworking between Arm and Thumb functions to work
23706 THUMB_SET_FUNC (sym
, 1);
23708 label_is_thumb_function_name
= FALSE
;
23711 dwarf2_emit_label (sym
);
23715 arm_data_in_code (void)
23717 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
23719 *input_line_pointer
= '/';
23720 input_line_pointer
+= 5;
23721 *input_line_pointer
= 0;
23729 arm_canonicalize_symbol_name (char * name
)
23733 if (thumb_mode
&& (len
= strlen (name
)) > 5
23734 && streq (name
+ len
- 5, "/data"))
23735 *(name
+ len
- 5) = 0;
23740 /* Table of all register names defined by default. The user can
23741 define additional names with .req. Note that all register names
23742 should appear in both upper and lowercase variants. Some registers
23743 also have mixed-case names. */
23745 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23746 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23747 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23748 #define REGSET(p,t) \
23749 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23750 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23751 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23752 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23753 #define REGSETH(p,t) \
23754 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23755 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23756 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23757 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23758 #define REGSET2(p,t) \
23759 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23760 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23761 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23762 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23763 #define SPLRBANK(base,bank,t) \
23764 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23765 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23766 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23767 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23768 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23769 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23771 static const struct reg_entry reg_names
[] =
23773 /* ARM integer registers. */
23774 REGSET(r
, RN
), REGSET(R
, RN
),
23776 /* ATPCS synonyms. */
23777 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23778 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23779 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23781 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23782 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23783 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23785 /* Well-known aliases. */
23786 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23787 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23789 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23790 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23792 /* Defining the new Zero register from ARMv8.1-M. */
23796 /* Coprocessor numbers. */
23797 REGSET(p
, CP
), REGSET(P
, CP
),
23799 /* Coprocessor register numbers. The "cr" variants are for backward
23801 REGSET(c
, CN
), REGSET(C
, CN
),
23802 REGSET(cr
, CN
), REGSET(CR
, CN
),
23804 /* ARM banked registers. */
23805 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23806 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23807 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23808 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23809 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23810 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23811 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23813 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23814 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23815 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23816 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23817 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23818 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23819 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23820 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23822 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23823 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23824 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23825 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23826 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23827 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23828 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23829 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23830 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23832 /* FPA registers. */
23833 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23834 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23836 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23837 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23839 /* VFP SP registers. */
23840 REGSET(s
,VFS
), REGSET(S
,VFS
),
23841 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23843 /* VFP DP Registers. */
23844 REGSET(d
,VFD
), REGSET(D
,VFD
),
23845 /* Extra Neon DP registers. */
23846 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23848 /* Neon QP registers. */
23849 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23851 /* VFP control registers. */
23852 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23853 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23854 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23855 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23856 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23857 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23858 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23859 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23860 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23861 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23862 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23864 /* Maverick DSP coprocessor registers. */
23865 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23866 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23868 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23869 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23870 REGDEF(dspsc
,0,DSPSC
),
23872 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23873 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23874 REGDEF(DSPSC
,0,DSPSC
),
23876 /* iWMMXt data registers - p0, c0-15. */
23877 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23879 /* iWMMXt control registers - p1, c0-3. */
23880 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23881 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23882 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23883 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23885 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23886 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23887 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23888 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23889 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23891 /* XScale accumulator registers. */
23892 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23898 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23899 within psr_required_here. */
23900 static const struct asm_psr psrs
[] =
23902 /* Backward compatibility notation. Note that "all" is no longer
23903 truly all possible PSR bits. */
23904 {"all", PSR_c
| PSR_f
},
23908 /* Individual flags. */
23914 /* Combinations of flags. */
23915 {"fs", PSR_f
| PSR_s
},
23916 {"fx", PSR_f
| PSR_x
},
23917 {"fc", PSR_f
| PSR_c
},
23918 {"sf", PSR_s
| PSR_f
},
23919 {"sx", PSR_s
| PSR_x
},
23920 {"sc", PSR_s
| PSR_c
},
23921 {"xf", PSR_x
| PSR_f
},
23922 {"xs", PSR_x
| PSR_s
},
23923 {"xc", PSR_x
| PSR_c
},
23924 {"cf", PSR_c
| PSR_f
},
23925 {"cs", PSR_c
| PSR_s
},
23926 {"cx", PSR_c
| PSR_x
},
23927 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23928 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23929 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23930 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23931 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23932 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23933 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23934 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23935 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23936 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23937 {"scf", PSR_s
| PSR_c
| PSR_f
},
23938 {"scx", PSR_s
| PSR_c
| PSR_x
},
23939 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23940 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23941 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23942 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23943 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23944 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23945 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23946 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23947 {"csf", PSR_c
| PSR_s
| PSR_f
},
23948 {"csx", PSR_c
| PSR_s
| PSR_x
},
23949 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23950 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23951 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23952 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23953 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23954 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23955 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23956 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23957 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23958 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23959 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23960 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23961 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23962 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23963 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23964 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23965 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23966 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23967 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23968 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23969 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23970 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23971 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23972 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23973 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23974 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23977 /* Table of V7M psr names. */
23978 static const struct asm_psr v7m_psrs
[] =
23980 {"apsr", 0x0 }, {"APSR", 0x0 },
23981 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23982 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23983 {"psr", 0x3 }, {"PSR", 0x3 },
23984 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23985 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23986 {"epsr", 0x6 }, {"EPSR", 0x6 },
23987 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23988 {"msp", 0x8 }, {"MSP", 0x8 },
23989 {"psp", 0x9 }, {"PSP", 0x9 },
23990 {"msplim", 0xa }, {"MSPLIM", 0xa },
23991 {"psplim", 0xb }, {"PSPLIM", 0xb },
23992 {"primask", 0x10}, {"PRIMASK", 0x10},
23993 {"basepri", 0x11}, {"BASEPRI", 0x11},
23994 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23995 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23996 {"control", 0x14}, {"CONTROL", 0x14},
23997 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23998 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23999 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
24000 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
24001 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
24002 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
24003 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24004 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
24005 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
24008 /* Table of all shift-in-operand names. */
24009 static const struct asm_shift_name shift_names
[] =
24011 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
24012 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
24013 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
24014 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
24015 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
24016 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
24017 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
24020 /* Table of all explicit relocation names. */
24022 static struct reloc_entry reloc_names
[] =
24024 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
24025 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
24026 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
24027 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
24028 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
24029 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
24030 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
24031 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
24032 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
24033 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
24034 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
24035 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
24036 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
24037 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
24038 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
24039 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
24040 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
24041 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
24042 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
24043 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
24044 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24045 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24046 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
24047 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
24048 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
24049 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
24050 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
24054 /* Table of all conditional affixes. */
24055 static const struct asm_cond conds
[] =
24059 {"cs", 0x2}, {"hs", 0x2},
24060 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24073 static const struct asm_cond vconds
[] =
24079 #define UL_BARRIER(L,U,CODE,FEAT) \
24080 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24081 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
24083 static struct asm_barrier_opt barrier_opt_names
[] =
24085 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
24086 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
24087 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
24088 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
24089 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
24090 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
24091 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
24092 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
24093 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
24094 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
24095 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
24096 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
24097 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
24098 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
24099 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
24100 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
24105 /* Table of ARM-format instructions. */
24107 /* Macros for gluing together operand strings. N.B. In all cases
24108 other than OPS0, the trailing OP_stop comes from default
24109 zero-initialization of the unspecified elements of the array. */
24110 #define OPS0() { OP_stop, }
24111 #define OPS1(a) { OP_##a, }
24112 #define OPS2(a,b) { OP_##a,OP_##b, }
24113 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
24114 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
24115 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24116 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24118 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24119 This is useful when mixing operands for ARM and THUMB, i.e. using the
24120 MIX_ARM_THUMB_OPERANDS macro.
24121 In order to use these macros, prefix the number of operands with _
24123 #define OPS_1(a) { a, }
24124 #define OPS_2(a,b) { a,b, }
24125 #define OPS_3(a,b,c) { a,b,c, }
24126 #define OPS_4(a,b,c,d) { a,b,c,d, }
24127 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
24128 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24130 /* These macros abstract out the exact format of the mnemonic table and
24131 save some repeated characters. */
24133 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
24134 #define TxCE(mnem, op, top, nops, ops, ae, te) \
24135 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
24136 THUMB_VARIANT, do_##ae, do_##te, 0 }
24138 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24139 a T_MNEM_xyz enumerator. */
24140 #define TCE(mnem, aop, top, nops, ops, ae, te) \
24141 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
24142 #define tCE(mnem, aop, top, nops, ops, ae, te) \
24143 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24145 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24146 infix after the third character. */
24147 #define TxC3(mnem, op, top, nops, ops, ae, te) \
24148 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
24149 THUMB_VARIANT, do_##ae, do_##te, 0 }
24150 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
24151 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
24152 THUMB_VARIANT, do_##ae, do_##te, 0 }
24153 #define TC3(mnem, aop, top, nops, ops, ae, te) \
24154 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
24155 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
24156 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
24157 #define tC3(mnem, aop, top, nops, ops, ae, te) \
24158 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24159 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
24160 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24162 /* Mnemonic that cannot be conditionalized. The ARM condition-code
24163 field is still 0xE. Many of the Thumb variants can be executed
24164 conditionally, so this is checked separately. */
24165 #define TUE(mnem, op, top, nops, ops, ae, te) \
24166 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24167 THUMB_VARIANT, do_##ae, do_##te, 0 }
24169 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24170 Used by mnemonics that have very minimal differences in the encoding for
24171 ARM and Thumb variants and can be handled in a common function. */
24172 #define TUEc(mnem, op, top, nops, ops, en) \
24173 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24174 THUMB_VARIANT, do_##en, do_##en, 0 }
24176 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24177 condition code field. */
24178 #define TUF(mnem, op, top, nops, ops, ae, te) \
24179 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
24180 THUMB_VARIANT, do_##ae, do_##te, 0 }
24182 /* ARM-only variants of all the above. */
24183 #define CE(mnem, op, nops, ops, ae) \
24184 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24186 #define C3(mnem, op, nops, ops, ae) \
24187 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24189 /* Thumb-only variants of TCE and TUE. */
24190 #define ToC(mnem, top, nops, ops, te) \
24191 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24194 #define ToU(mnem, top, nops, ops, te) \
24195 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
24198 /* T_MNEM_xyz enumerator variants of ToC. */
24199 #define toC(mnem, top, nops, ops, te) \
24200 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
24203 /* T_MNEM_xyz enumerator variants of ToU. */
24204 #define toU(mnem, top, nops, ops, te) \
24205 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
24208 /* Legacy mnemonics that always have conditional infix after the third
24210 #define CL(mnem, op, nops, ops, ae) \
24211 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24212 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24214 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
24215 #define cCE(mnem, op, nops, ops, ae) \
24216 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24218 /* mov instructions that are shared between coprocessor and MVE. */
24219 #define mcCE(mnem, op, nops, ops, ae) \
24220 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24222 /* Legacy coprocessor instructions where conditional infix and conditional
24223 suffix are ambiguous. For consistency this includes all FPA instructions,
24224 not just the potentially ambiguous ones. */
24225 #define cCL(mnem, op, nops, ops, ae) \
24226 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24227 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24229 /* Coprocessor, takes either a suffix or a position-3 infix
24230 (for an FPA corner case). */
24231 #define C3E(mnem, op, nops, ops, ae) \
24232 { mnem, OPS##nops ops, OT_csuf_or_in3, \
24233 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24235 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
24236 { m1 #m2 m3, OPS##nops ops, \
24237 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
24238 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24240 #define CM(m1, m2, op, nops, ops, ae) \
24241 xCM_ (m1, , m2, op, nops, ops, ae), \
24242 xCM_ (m1, eq, m2, op, nops, ops, ae), \
24243 xCM_ (m1, ne, m2, op, nops, ops, ae), \
24244 xCM_ (m1, cs, m2, op, nops, ops, ae), \
24245 xCM_ (m1, hs, m2, op, nops, ops, ae), \
24246 xCM_ (m1, cc, m2, op, nops, ops, ae), \
24247 xCM_ (m1, ul, m2, op, nops, ops, ae), \
24248 xCM_ (m1, lo, m2, op, nops, ops, ae), \
24249 xCM_ (m1, mi, m2, op, nops, ops, ae), \
24250 xCM_ (m1, pl, m2, op, nops, ops, ae), \
24251 xCM_ (m1, vs, m2, op, nops, ops, ae), \
24252 xCM_ (m1, vc, m2, op, nops, ops, ae), \
24253 xCM_ (m1, hi, m2, op, nops, ops, ae), \
24254 xCM_ (m1, ls, m2, op, nops, ops, ae), \
24255 xCM_ (m1, ge, m2, op, nops, ops, ae), \
24256 xCM_ (m1, lt, m2, op, nops, ops, ae), \
24257 xCM_ (m1, gt, m2, op, nops, ops, ae), \
24258 xCM_ (m1, le, m2, op, nops, ops, ae), \
24259 xCM_ (m1, al, m2, op, nops, ops, ae)
24261 #define UE(mnem, op, nops, ops, ae) \
24262 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24264 #define UF(mnem, op, nops, ops, ae) \
24265 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24267 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
24268 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24269 use the same encoding function for each. */
24270 #define NUF(mnem, op, nops, ops, enc) \
24271 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24272 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24274 /* Neon data processing, version which indirects through neon_enc_tab for
24275 the various overloaded versions of opcodes. */
24276 #define nUF(mnem, op, nops, ops, enc) \
24277 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24278 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24280 /* Neon insn with conditional suffix for the ARM version, non-overloaded
24282 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24283 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
24284 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24286 #define NCE(mnem, op, nops, ops, enc) \
24287 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24289 #define NCEF(mnem, op, nops, ops, enc) \
24290 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24292 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
24293 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24294 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
24295 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24297 #define nCE(mnem, op, nops, ops, enc) \
24298 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24300 #define nCEF(mnem, op, nops, ops, enc) \
24301 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24304 #define mCEF(mnem, op, nops, ops, enc) \
24305 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
24306 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24309 /* nCEF but for MVE predicated instructions. */
24310 #define mnCEF(mnem, op, nops, ops, enc) \
24311 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24313 /* nCE but for MVE predicated instructions. */
24314 #define mnCE(mnem, op, nops, ops, enc) \
24315 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24317 /* NUF but for potentially MVE predicated instructions. */
24318 #define MNUF(mnem, op, nops, ops, enc) \
24319 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24320 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24322 /* nUF but for potentially MVE predicated instructions. */
24323 #define mnUF(mnem, op, nops, ops, enc) \
24324 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24325 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24327 /* ToC but for potentially MVE predicated instructions. */
24328 #define mToC(mnem, top, nops, ops, te) \
24329 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24332 /* NCE but for MVE predicated instructions. */
24333 #define MNCE(mnem, op, nops, ops, enc) \
24334 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24336 /* NCEF but for MVE predicated instructions. */
24337 #define MNCEF(mnem, op, nops, ops, enc) \
24338 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24341 static const struct asm_opcode insns
[] =
24343 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
24344 #define THUMB_VARIANT & arm_ext_v4t
24345 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24346 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24347 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24348 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24349 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24350 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24351 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24352 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24353 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24354 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24355 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24356 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24357 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24358 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24359 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24360 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24362 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24363 for setting PSR flag bits. They are obsolete in V6 and do not
24364 have Thumb equivalents. */
24365 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24366 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24367 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
24368 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24369 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24370 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
24371 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24372 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24373 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
24375 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
24376 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
24377 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24378 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24380 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
24381 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24382 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
24384 OP_ADDRGLDR
),ldst
, t_ldst
),
24385 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24387 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24388 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24389 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24390 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24391 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24392 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24394 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
24395 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
24398 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
24399 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
24400 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
24401 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
24403 /* Thumb-compatibility pseudo ops. */
24404 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24405 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24406 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24407 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24408 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24409 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24410 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24411 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24412 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
24413 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
24414 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
24415 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
24417 /* These may simplify to neg. */
24418 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24419 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24421 #undef THUMB_VARIANT
24422 #define THUMB_VARIANT & arm_ext_os
24424 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24425 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24427 #undef THUMB_VARIANT
24428 #define THUMB_VARIANT & arm_ext_v6
24430 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
24432 /* V1 instructions with no Thumb analogue prior to V6T2. */
24433 #undef THUMB_VARIANT
24434 #define THUMB_VARIANT & arm_ext_v6t2
24436 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24437 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24438 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
24440 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24441 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24442 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
24443 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24445 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24446 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24448 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24449 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24451 /* V1 instructions with no Thumb analogue at all. */
24452 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
24453 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
24455 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24456 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24457 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24458 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24459 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24460 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24461 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24462 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24465 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
24466 #undef THUMB_VARIANT
24467 #define THUMB_VARIANT & arm_ext_v4t
24469 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24470 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24472 #undef THUMB_VARIANT
24473 #define THUMB_VARIANT & arm_ext_v6t2
24475 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24476 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
24478 /* Generic coprocessor instructions. */
24479 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24480 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24481 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24482 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24483 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24484 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24485 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24488 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
24490 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24491 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24494 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
24495 #undef THUMB_VARIANT
24496 #define THUMB_VARIANT & arm_ext_msr
24498 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
24499 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
24502 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
24503 #undef THUMB_VARIANT
24504 #define THUMB_VARIANT & arm_ext_v6t2
24506 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24507 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24508 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24509 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24510 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24511 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24512 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24513 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24516 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
24517 #undef THUMB_VARIANT
24518 #define THUMB_VARIANT & arm_ext_v4t
24520 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24521 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24522 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24523 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24524 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24525 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24528 #define ARM_VARIANT & arm_ext_v4t_5
24530 /* ARM Architecture 4T. */
24531 /* Note: bx (and blx) are required on V5, even if the processor does
24532 not support Thumb. */
24533 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
24536 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24537 #undef THUMB_VARIANT
24538 #define THUMB_VARIANT & arm_ext_v5t
24540 /* Note: blx has 2 variants; the .value coded here is for
24541 BLX(2). Only this variant has conditional execution. */
24542 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
24543 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
24545 #undef THUMB_VARIANT
24546 #define THUMB_VARIANT & arm_ext_v6t2
24548 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
24549 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24550 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24551 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24552 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24553 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24554 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24555 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24558 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24559 #undef THUMB_VARIANT
24560 #define THUMB_VARIANT & arm_ext_v5exp
24562 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24563 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24564 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24565 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24567 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24568 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24570 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24571 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24572 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24573 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24575 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24576 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24577 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24578 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24580 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24581 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24583 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24584 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24585 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24586 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24589 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24590 #undef THUMB_VARIANT
24591 #define THUMB_VARIANT & arm_ext_v6t2
24593 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
24594 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
24596 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
24597 ADDRGLDRS
), ldrd
, t_ldstd
),
24599 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24600 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24603 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24605 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
24608 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24609 #undef THUMB_VARIANT
24610 #define THUMB_VARIANT & arm_ext_v6
24612 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24613 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24614 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24615 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24616 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24617 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24618 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24619 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24620 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24621 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
24623 #undef THUMB_VARIANT
24624 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24626 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
24627 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24629 #undef THUMB_VARIANT
24630 #define THUMB_VARIANT & arm_ext_v6t2
24632 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24633 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24635 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
24636 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
24638 /* ARM V6 not included in V7M. */
24639 #undef THUMB_VARIANT
24640 #define THUMB_VARIANT & arm_ext_v6_notm
24641 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24642 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24643 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24644 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24645 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24646 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24647 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24648 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24649 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24650 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24651 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24652 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24653 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24654 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24655 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24656 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24657 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24658 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24659 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24661 /* ARM V6 not included in V7M (eg. integer SIMD). */
24662 #undef THUMB_VARIANT
24663 #define THUMB_VARIANT & arm_ext_v6_dsp
24664 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24665 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24666 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24667 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24668 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24669 /* Old name for QASX. */
24670 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24671 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24672 /* Old name for QSAX. */
24673 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24674 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24675 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24676 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24677 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24678 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24679 /* Old name for SASX. */
24680 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24681 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24682 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24683 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24684 /* Old name for SHASX. */
24685 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24686 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24687 /* Old name for SHSAX. */
24688 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24689 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24690 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24691 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24692 /* Old name for SSAX. */
24693 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24694 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24695 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24696 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24697 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24698 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24699 /* Old name for UASX. */
24700 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24701 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24702 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24703 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24704 /* Old name for UHASX. */
24705 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24706 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24707 /* Old name for UHSAX. */
24708 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24709 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24710 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24711 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24712 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24713 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24714 /* Old name for UQASX. */
24715 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24716 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24717 /* Old name for UQSAX. */
24718 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24719 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24720 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24721 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24722 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24723 /* Old name for USAX. */
24724 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24725 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24726 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24727 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24728 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24729 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24730 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24731 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24732 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24733 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24734 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24735 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24736 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24737 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24738 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24739 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24740 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24741 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24742 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24743 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24744 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24745 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24746 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24747 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24748 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24749 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24750 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24751 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24752 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24753 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24754 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24755 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24756 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24757 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24760 #define ARM_VARIANT & arm_ext_v6k_v6t2
24761 #undef THUMB_VARIANT
24762 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24764 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24765 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24766 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24767 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24769 #undef THUMB_VARIANT
24770 #define THUMB_VARIANT & arm_ext_v6_notm
24771 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24773 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24774 RRnpcb
), strexd
, t_strexd
),
24776 #undef THUMB_VARIANT
24777 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24778 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24780 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24782 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24784 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24786 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24789 #define ARM_VARIANT & arm_ext_sec
24790 #undef THUMB_VARIANT
24791 #define THUMB_VARIANT & arm_ext_sec
24793 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24796 #define ARM_VARIANT & arm_ext_virt
24797 #undef THUMB_VARIANT
24798 #define THUMB_VARIANT & arm_ext_virt
24800 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24801 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24804 #define ARM_VARIANT & arm_ext_pan
24805 #undef THUMB_VARIANT
24806 #define THUMB_VARIANT & arm_ext_pan
24808 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24811 #define ARM_VARIANT & arm_ext_v6t2
24812 #undef THUMB_VARIANT
24813 #define THUMB_VARIANT & arm_ext_v6t2
24815 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24816 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24817 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24818 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24820 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24821 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24823 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24824 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24825 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24826 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24829 #define ARM_VARIANT & arm_ext_v3
24830 #undef THUMB_VARIANT
24831 #define THUMB_VARIANT & arm_ext_v6t2
24833 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24834 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24835 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24838 #define ARM_VARIANT & arm_ext_v6t2
24839 #undef THUMB_VARIANT
24840 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24841 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24842 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24844 /* Thumb-only instructions. */
24846 #define ARM_VARIANT NULL
24847 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24848 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24850 /* ARM does not really have an IT instruction, so always allow it.
24851 The opcode is copied from Thumb in order to allow warnings in
24852 -mimplicit-it=[never | arm] modes. */
24854 #define ARM_VARIANT & arm_ext_v1
24855 #undef THUMB_VARIANT
24856 #define THUMB_VARIANT & arm_ext_v6t2
24858 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24859 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24860 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24861 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24862 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24863 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24864 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24865 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24866 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24867 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24868 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24869 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24870 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24871 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24872 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24873 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24874 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24875 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24877 /* Thumb2 only instructions. */
24879 #define ARM_VARIANT NULL
24881 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24882 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24883 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24884 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24885 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24886 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24888 /* Hardware division instructions. */
24890 #define ARM_VARIANT & arm_ext_adiv
24891 #undef THUMB_VARIANT
24892 #define THUMB_VARIANT & arm_ext_div
24894 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24895 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24897 /* ARM V6M/V7 instructions. */
24899 #define ARM_VARIANT & arm_ext_barrier
24900 #undef THUMB_VARIANT
24901 #define THUMB_VARIANT & arm_ext_barrier
24903 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24904 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24905 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24907 /* ARM V7 instructions. */
24909 #define ARM_VARIANT & arm_ext_v7
24910 #undef THUMB_VARIANT
24911 #define THUMB_VARIANT & arm_ext_v7
24913 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24914 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24917 #define ARM_VARIANT & arm_ext_mp
24918 #undef THUMB_VARIANT
24919 #define THUMB_VARIANT & arm_ext_mp
24921 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24923 /* AArchv8 instructions. */
24925 #define ARM_VARIANT & arm_ext_v8
24927 /* Instructions shared between armv8-a and armv8-m. */
24928 #undef THUMB_VARIANT
24929 #define THUMB_VARIANT & arm_ext_atomics
24931 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24932 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24933 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24934 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24935 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24936 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24937 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24938 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24939 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24940 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24942 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24944 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24946 #undef THUMB_VARIANT
24947 #define THUMB_VARIANT & arm_ext_v8
24949 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24950 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24952 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24954 #undef THUMB_VARIANT
24955 #define THUMB_VARIANT & arm_ext_v8r
24957 #define ARM_VARIANT & arm_ext_v8r
24959 /* ARMv8-R instructions. */
24960 TUF("dfb", 57ff04c
, f3bf8f4c
, 0, (), noargs
, noargs
),
24962 /* Defined in V8 but is in undefined encoding space for earlier
24963 architectures. However earlier architectures are required to treat
24964 this instuction as a semihosting trap as well. Hence while not explicitly
24965 defined as such, it is in fact correct to define the instruction for all
24967 #undef THUMB_VARIANT
24968 #define THUMB_VARIANT & arm_ext_v1
24970 #define ARM_VARIANT & arm_ext_v1
24971 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24973 /* ARMv8 T32 only. */
24975 #define ARM_VARIANT NULL
24976 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24977 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24978 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24980 /* FP for ARMv8. */
24982 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24983 #undef THUMB_VARIANT
24984 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24986 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24987 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24988 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24989 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24990 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24991 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24992 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24993 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24994 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24995 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24996 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24998 /* Crypto v1 extensions. */
25000 #define ARM_VARIANT & fpu_crypto_ext_armv8
25001 #undef THUMB_VARIANT
25002 #define THUMB_VARIANT & fpu_crypto_ext_armv8
25004 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
25005 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
25006 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
25007 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
25008 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
25009 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
25010 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
25011 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
25012 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
25013 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
25014 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
25015 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
25016 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
25017 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
25020 #define ARM_VARIANT & arm_ext_crc
25021 #undef THUMB_VARIANT
25022 #define THUMB_VARIANT & arm_ext_crc
25023 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
25024 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
25025 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
25026 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
25027 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
25028 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
25030 /* ARMv8.2 RAS extension. */
25032 #define ARM_VARIANT & arm_ext_ras
25033 #undef THUMB_VARIANT
25034 #define THUMB_VARIANT & arm_ext_ras
25035 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
25038 #define ARM_VARIANT & arm_ext_v8_3
25039 #undef THUMB_VARIANT
25040 #define THUMB_VARIANT & arm_ext_v8_3
25041 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
25044 #define ARM_VARIANT & fpu_neon_ext_dotprod
25045 #undef THUMB_VARIANT
25046 #define THUMB_VARIANT & fpu_neon_ext_dotprod
25047 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
25048 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
25051 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
25052 #undef THUMB_VARIANT
25053 #define THUMB_VARIANT NULL
25055 cCE("wfs", e200110
, 1, (RR
), rd
),
25056 cCE("rfs", e300110
, 1, (RR
), rd
),
25057 cCE("wfc", e400110
, 1, (RR
), rd
),
25058 cCE("rfc", e500110
, 1, (RR
), rd
),
25060 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25061 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25062 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25063 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25065 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25066 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25067 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25068 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25070 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
25071 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
25072 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
25073 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
25074 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
25075 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
25076 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
25077 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
25078 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
25079 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
25080 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
25081 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
25083 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
25084 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
25085 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
25086 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
25087 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
25088 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
25089 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
25090 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
25091 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
25092 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
25093 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
25094 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
25096 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
25097 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
25098 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
25099 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
25100 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
25101 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
25102 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
25103 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
25104 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
25105 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
25106 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
25107 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
25109 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
25110 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
25111 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
25112 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
25113 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
25114 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
25115 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
25116 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
25117 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
25118 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
25119 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
25120 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
25122 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
25123 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
25124 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
25125 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
25126 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
25127 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
25128 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
25129 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
25130 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
25131 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
25132 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
25133 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
25135 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
25136 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
25137 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
25138 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
25139 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
25140 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
25141 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
25142 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
25143 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
25144 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
25145 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
25146 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
25148 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
25149 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
25150 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
25151 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
25152 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
25153 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
25154 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
25155 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
25156 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
25157 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
25158 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
25159 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
25161 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
25162 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
25163 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
25164 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
25165 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
25166 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
25167 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
25168 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
25169 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
25170 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
25171 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
25172 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
25174 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
25175 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
25176 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
25177 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
25178 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
25179 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
25180 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
25181 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
25182 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
25183 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
25184 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
25185 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
25187 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
25188 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
25189 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
25190 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
25191 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
25192 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
25193 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
25194 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
25195 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
25196 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
25197 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
25198 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
25200 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
25201 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
25202 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
25203 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
25204 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
25205 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
25206 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
25207 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
25208 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
25209 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
25210 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
25211 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
25213 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
25214 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
25215 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
25216 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
25217 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
25218 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
25219 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
25220 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
25221 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
25222 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
25223 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
25224 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
25226 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
25227 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
25228 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
25229 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
25230 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
25231 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
25232 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
25233 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
25234 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
25235 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
25236 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
25237 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
25239 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
25240 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
25241 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
25242 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
25243 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
25244 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
25245 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
25246 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
25247 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
25248 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
25249 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
25250 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
25252 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
25253 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
25254 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
25255 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
25256 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
25257 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
25258 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
25259 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
25260 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
25261 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
25262 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
25263 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
25265 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
25266 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
25267 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
25268 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
25269 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
25270 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
25271 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
25272 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
25273 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
25274 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
25275 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
25276 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
25278 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25279 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25280 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25281 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25282 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25283 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25284 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25285 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25286 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25287 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25288 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25289 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25291 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25292 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25293 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25294 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25295 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25296 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25297 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25298 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25299 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25300 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25301 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25302 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25304 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25305 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25306 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25307 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25308 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25309 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25310 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25311 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25312 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25313 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25314 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25315 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25317 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25318 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25319 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25320 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25321 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25322 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25323 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25324 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25325 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25326 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25327 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25328 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25330 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25331 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25332 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25333 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25334 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25335 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25336 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25337 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25338 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25339 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25340 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25341 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25343 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25344 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25345 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25346 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25347 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25348 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25349 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25350 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25351 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25352 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25353 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25354 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25356 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25357 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25358 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25359 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25360 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25361 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25362 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25363 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25364 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25365 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25366 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25367 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25369 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25370 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25371 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25372 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25373 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25374 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25375 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25376 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25377 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25378 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25379 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25380 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25382 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25383 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25384 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25385 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25386 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25387 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25388 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25389 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25390 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25391 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25392 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25393 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25395 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25396 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25397 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25398 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25399 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25400 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25401 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25402 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25403 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25404 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25405 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25406 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25408 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25409 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25410 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25411 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25412 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25413 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25414 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25415 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25416 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25417 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25418 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25419 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25421 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25422 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25423 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25424 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25425 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25426 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25427 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25428 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25429 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25430 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25431 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25432 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25434 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25435 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25436 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25437 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25438 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25439 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25440 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25441 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25442 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25443 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25444 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25445 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25447 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25448 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25449 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25450 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25452 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
25453 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
25454 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
25455 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
25456 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
25457 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
25458 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
25459 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
25460 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
25461 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
25462 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
25463 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
25465 /* The implementation of the FIX instruction is broken on some
25466 assemblers, in that it accepts a precision specifier as well as a
25467 rounding specifier, despite the fact that this is meaningless.
25468 To be more compatible, we accept it as well, though of course it
25469 does not set any bits. */
25470 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
25471 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
25472 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
25473 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
25474 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
25475 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
25476 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
25477 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
25478 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
25479 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
25480 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
25481 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
25482 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
25484 /* Instructions that were new with the real FPA, call them V2. */
25486 #define ARM_VARIANT & fpu_fpa_ext_v2
25488 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25489 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25490 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25491 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25492 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25493 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25496 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
25497 #undef THUMB_VARIANT
25498 #define THUMB_VARIANT & arm_ext_v6t2
25499 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
25500 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
25501 mcCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25502 mcCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25503 mcCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25504 mcCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25506 /* Memory operations. */
25507 mcCE(fldmias
, c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25508 mcCE(fldmdbs
, d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25509 mcCE(fstmias
, c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25510 mcCE(fstmdbs
, d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25511 #undef THUMB_VARIANT
25513 /* Moves and type conversions. */
25514 cCE("fmstat", ef1fa10
, 0, (), noargs
),
25515 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25516 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25517 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25518 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25519 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25520 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25521 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
25522 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
25524 /* Memory operations. */
25525 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25526 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25527 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25528 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25529 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25530 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25531 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25532 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25533 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25534 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25535 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25536 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25538 /* Monadic operations. */
25539 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25540 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25541 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25543 /* Dyadic operations. */
25544 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25545 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25546 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25547 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25548 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25549 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25550 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25551 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25552 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25555 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25556 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
25557 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25558 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
25560 /* Double precision load/store are still present on single precision
25561 implementations. */
25562 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25563 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25564 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25565 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25566 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25567 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25568 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25569 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25572 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25574 /* Moves and type conversions. */
25575 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25576 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25577 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25578 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25579 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25580 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25581 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25582 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25583 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25584 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25585 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25586 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25588 /* Monadic operations. */
25589 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25590 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25591 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25593 /* Dyadic operations. */
25594 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25595 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25596 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25597 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25598 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25599 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25600 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25601 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25602 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25605 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25606 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
25607 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25608 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
25610 /* Instructions which may belong to either the Neon or VFP instruction sets.
25611 Individual encoder functions perform additional architecture checks. */
25613 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25614 #undef THUMB_VARIANT
25615 #define THUMB_VARIANT & arm_ext_v6t2
25617 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25618 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25619 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25620 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25621 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25622 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25624 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
25625 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
25627 #undef THUMB_VARIANT
25628 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
25630 /* These mnemonics are unique to VFP. */
25631 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
25632 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
25633 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25634 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25635 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25636 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
25638 /* Mnemonics shared by Neon and VFP. */
25639 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
25641 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
25642 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
25643 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
25644 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
25647 /* NOTE: All VMOV encoding is special-cased! */
25648 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
25650 #undef THUMB_VARIANT
25651 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25652 by different feature bits. Since we are setting the Thumb guard, we can
25653 require Thumb-1 which makes it a nop guard and set the right feature bit in
25654 do_vldr_vstr (). */
25655 #define THUMB_VARIANT & arm_ext_v4t
25656 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25657 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25660 #define ARM_VARIANT & arm_ext_fp16
25661 #undef THUMB_VARIANT
25662 #define THUMB_VARIANT & arm_ext_fp16
25663 /* New instructions added from v8.2, allowing the extraction and insertion of
25664 the upper 16 bits of a 32-bit vector register. */
25665 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25666 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25668 /* New backported fma/fms instructions optional in v8.2. */
25669 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25670 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25672 #undef THUMB_VARIANT
25673 #define THUMB_VARIANT & fpu_neon_ext_v1
25675 #define ARM_VARIANT & fpu_neon_ext_v1
25677 /* Data processing with three registers of the same length. */
25678 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25679 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25680 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25681 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25682 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25683 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25684 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25685 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25686 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25687 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25688 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25689 /* If not immediate, fall back to neon_dyadic_i64_su.
25690 shl should accept I8 I16 I32 I64,
25691 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25692 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25693 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25694 /* Logic ops, types optional & ignored. */
25695 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25696 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25697 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25698 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25699 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25700 /* Bitfield ops, untyped. */
25701 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25702 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25703 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25704 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25705 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25706 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25707 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25708 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25709 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25710 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25711 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25712 back to neon_dyadic_if_su. */
25713 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25714 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25715 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25716 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25717 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25718 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25719 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25720 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25721 /* Comparison. Type I8 I16 I32 F32. */
25722 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25723 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25724 /* As above, D registers only. */
25725 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25726 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25727 /* Int and float variants, signedness unimportant. */
25728 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25729 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25730 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25731 /* Add/sub take types I8 I16 I32 I64 F32. */
25732 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25733 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25734 /* vtst takes sizes 8, 16, 32. */
25735 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25736 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25737 /* VMUL takes I8 I16 I32 F32 P8. */
25738 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25739 /* VQD{R}MULH takes S16 S32. */
25740 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25741 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25742 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25743 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25744 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25745 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25746 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25747 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25748 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25749 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25750 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25751 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25752 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25753 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25754 /* ARM v8.1 extension. */
25755 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25756 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25757 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25759 /* Two address, int/float. Types S8 S16 S32 F32. */
25760 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25761 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25763 /* Data processing with two registers and a shift amount. */
25764 /* Right shifts, and variants with rounding.
25765 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25766 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25767 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25768 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25769 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25770 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25771 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25772 /* Shift and insert. Sizes accepted 8 16 32 64. */
25773 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25774 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25775 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25776 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25777 /* Right shift immediate, saturating & narrowing, with rounding variants.
25778 Types accepted S16 S32 S64 U16 U32 U64. */
25779 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25780 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25781 /* As above, unsigned. Types accepted S16 S32 S64. */
25782 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25783 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25784 /* Right shift narrowing. Types accepted I16 I32 I64. */
25785 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25786 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25787 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25788 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25789 /* CVT with optional immediate for fixed-point variant. */
25790 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25792 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25794 /* Data processing, three registers of different lengths. */
25795 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25796 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25797 /* If not scalar, fall back to neon_dyadic_long.
25798 Vector types as above, scalar types S16 S32 U16 U32. */
25799 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25800 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25801 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25802 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25803 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25804 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25805 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25806 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25807 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25808 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25809 /* Saturating doubling multiplies. Types S16 S32. */
25810 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25811 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25812 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25813 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25814 S16 S32 U16 U32. */
25815 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25817 /* Extract. Size 8. */
25818 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25819 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25821 /* Two registers, miscellaneous. */
25822 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25823 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25824 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25825 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25826 /* Vector replicate. Sizes 8 16 32. */
25827 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25828 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25829 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25830 /* VMOVN. Types I16 I32 I64. */
25831 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25832 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25833 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25834 /* VQMOVUN. Types S16 S32 S64. */
25835 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25836 /* VZIP / VUZP. Sizes 8 16 32. */
25837 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25838 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25839 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25840 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25841 /* VQABS / VQNEG. Types S8 S16 S32. */
25842 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25843 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25844 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25845 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25846 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25847 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25848 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25849 /* Reciprocal estimates. Types U32 F16 F32. */
25850 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25851 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25852 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25853 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25854 /* VCLS. Types S8 S16 S32. */
25855 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25856 /* VCLZ. Types I8 I16 I32. */
25857 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25858 /* VCNT. Size 8. */
25859 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25860 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25861 /* Two address, untyped. */
25862 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25863 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25864 /* VTRN. Sizes 8 16 32. */
25865 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25866 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25868 /* Table lookup. Size 8. */
25869 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25870 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25872 #undef THUMB_VARIANT
25873 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25875 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25877 /* Neon element/structure load/store. */
25878 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25879 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25880 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25881 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25882 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25883 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25884 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25885 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25887 #undef THUMB_VARIANT
25888 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25890 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25891 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25892 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25893 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25894 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25895 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25896 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25897 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25898 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25899 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25901 #undef THUMB_VARIANT
25902 #define THUMB_VARIANT & fpu_vfp_ext_v3
25904 #define ARM_VARIANT & fpu_vfp_ext_v3
25906 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25907 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25908 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25909 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25910 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25911 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25912 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25913 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25914 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25917 #define ARM_VARIANT & fpu_vfp_ext_fma
25918 #undef THUMB_VARIANT
25919 #define THUMB_VARIANT & fpu_vfp_ext_fma
25920 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25921 VFP FMA variant; NEON and VFP FMA always includes the NEON
25922 FMA instructions. */
25923 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25924 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25925 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25927 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25928 the v form should always be used. */
25929 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25930 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25931 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25932 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25933 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25934 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25936 #undef THUMB_VARIANT
25938 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25940 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25941 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25942 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25943 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25944 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25945 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25946 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25947 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25950 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25952 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25953 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25954 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25955 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25956 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25957 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25958 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25959 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25960 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25961 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25962 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25963 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25964 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25965 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25966 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25967 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25968 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25969 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25970 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25971 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25972 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25973 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25974 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25975 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25976 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25977 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25978 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25979 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25980 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25981 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25982 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25983 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25984 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25985 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25986 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25987 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25988 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25989 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25990 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25991 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25992 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25993 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25994 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25995 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25996 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25997 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25998 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25999 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26000 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26001 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26002 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26003 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26004 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26005 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26006 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26007 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26008 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26009 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26010 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26011 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26012 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26013 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26014 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26015 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26016 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26017 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26018 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26019 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26020 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26021 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26022 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26023 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26024 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26025 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26026 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26027 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26028 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26029 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26030 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26031 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26032 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26033 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26034 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26035 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26036 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26037 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26038 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26039 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26040 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
26041 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26042 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26043 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26044 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26045 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26046 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26047 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26048 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26049 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26050 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26051 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26052 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26053 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26054 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26055 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26056 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26057 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26058 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26059 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26060 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26061 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26062 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
26063 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26064 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26065 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26066 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26067 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26068 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26069 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26070 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26071 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26072 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26073 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26074 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26075 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26076 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26077 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26078 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26079 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26080 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26081 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26082 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26083 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26084 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26085 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26086 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26087 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26088 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26089 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26090 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26091 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26092 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26093 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26094 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26095 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26096 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26097 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26098 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26099 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26100 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26101 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26102 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26103 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26104 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26105 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26106 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26107 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26108 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26109 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26110 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26111 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26112 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26113 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
26116 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
26118 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
26119 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
26120 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
26121 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26122 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26123 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26124 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26125 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26126 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26127 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26128 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26129 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26130 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26131 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26132 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26133 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26134 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26135 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26136 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26137 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26138 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
26139 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26140 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26141 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26142 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26143 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26144 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26145 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26146 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26147 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26148 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26149 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26150 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26151 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26152 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26153 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26154 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26155 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26156 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26157 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26158 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26159 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26160 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26161 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26162 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26163 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26164 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26165 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26166 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26167 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26168 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26169 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26170 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26171 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26172 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26173 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26174 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26177 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
26179 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26180 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26181 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26182 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26183 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26184 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26185 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26186 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26187 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
26188 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
26189 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
26190 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
26191 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
26192 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
26193 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
26194 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
26195 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
26196 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
26197 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
26198 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
26199 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
26200 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
26201 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
26202 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
26203 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
26204 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
26205 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
26206 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
26207 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
26208 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
26209 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
26210 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
26211 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
26212 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
26213 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
26214 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
26215 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
26216 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
26217 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
26218 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
26219 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
26220 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
26221 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
26222 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
26223 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
26224 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
26225 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
26226 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
26227 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
26228 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
26229 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
26230 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
26231 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
26232 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
26233 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26234 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26235 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26236 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26237 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26238 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26239 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
26240 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
26241 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
26242 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
26243 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26244 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26245 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26246 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26247 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26248 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26249 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26250 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26251 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26252 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26253 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26254 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26256 /* ARMv8.5-A instructions. */
26258 #define ARM_VARIANT & arm_ext_sb
26259 #undef THUMB_VARIANT
26260 #define THUMB_VARIANT & arm_ext_sb
26261 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
26264 #define ARM_VARIANT & arm_ext_predres
26265 #undef THUMB_VARIANT
26266 #define THUMB_VARIANT & arm_ext_predres
26267 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
26268 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
26269 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
26271 /* ARMv8-M instructions. */
26273 #define ARM_VARIANT NULL
26274 #undef THUMB_VARIANT
26275 #define THUMB_VARIANT & arm_ext_v8m
26276 ToU("sg", e97fe97f
, 0, (), noargs
),
26277 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
26278 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
26279 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
26280 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
26281 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
26282 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
26284 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
26285 instructions behave as nop if no VFP is present. */
26286 #undef THUMB_VARIANT
26287 #define THUMB_VARIANT & arm_ext_v8m_main
26288 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
26289 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
26291 /* Armv8.1-M Mainline instructions. */
26292 #undef THUMB_VARIANT
26293 #define THUMB_VARIANT & arm_ext_v8_1m_main
26294 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26295 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26296 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26297 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26298 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
26299 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
26300 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26301 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26302 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26304 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
26305 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
26306 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26307 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
26308 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26310 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
26311 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
26312 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
26314 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
26315 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
26317 #undef THUMB_VARIANT
26318 #define THUMB_VARIANT & mve_ext
26319 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26320 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26321 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26322 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26323 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26324 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26325 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26326 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26327 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26328 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26329 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26330 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26331 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26332 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26333 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26335 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26336 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26337 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26338 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26339 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26340 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26341 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26342 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26343 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26344 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26345 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26346 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26347 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26348 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26349 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26351 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
26352 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
26353 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
26354 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
26355 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
26356 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
26357 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
26358 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
26359 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
26360 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
26361 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
26362 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
26363 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
26364 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
26365 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
26367 /* MVE and MVE FP only. */
26368 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
26369 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
26370 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26371 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26372 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26373 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26374 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
26375 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
26376 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26377 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26378 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26379 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26380 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26381 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26382 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26383 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26384 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26385 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26387 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26388 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26389 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26390 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26391 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26392 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26393 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26394 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26395 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26396 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26397 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26398 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26399 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26400 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26401 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26402 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26403 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26404 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26405 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26406 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26408 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
26409 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
26410 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
26411 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26412 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26413 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
26414 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
26415 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26416 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26417 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26418 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26419 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26420 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26421 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
26422 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
26423 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
26424 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
26426 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26427 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26428 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26429 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26430 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26431 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26432 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26433 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26434 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26435 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26436 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26437 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26438 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26439 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26440 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26441 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26442 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26443 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26444 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26445 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26447 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
26448 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26449 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26450 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
26451 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
26453 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26454 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26455 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26456 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26457 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26458 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26459 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26460 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26461 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26462 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26463 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26464 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26465 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26466 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26467 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26468 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26469 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26471 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26472 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26473 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26474 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26475 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26476 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26477 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26478 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26479 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26480 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26481 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26482 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26484 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
26485 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26486 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26488 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
26489 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
26490 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
26491 toU("lctp", _lctp
, 0, (), t_loloop
),
26493 #undef THUMB_VARIANT
26494 #define THUMB_VARIANT & mve_fp_ext
26495 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
26496 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
26497 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26498 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26499 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26500 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26501 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26502 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26505 #define ARM_VARIANT & fpu_vfp_ext_v1
26506 #undef THUMB_VARIANT
26507 #define THUMB_VARIANT & arm_ext_v6t2
26508 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
26509 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
26511 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
26514 #define ARM_VARIANT & fpu_vfp_ext_v1xd
26516 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
26517 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
26518 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
26519 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
26521 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
26522 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26523 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26525 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26526 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26528 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
26529 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
26531 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26532 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26535 #define ARM_VARIANT & fpu_vfp_ext_v2
26537 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
26538 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
26539 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
26540 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
26543 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
26544 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
26545 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
26546 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
26547 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
26548 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26549 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26552 #define ARM_VARIANT & fpu_neon_ext_v1
26553 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26554 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
26555 mnUF(vaddl
, _vaddl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26556 mnUF(vsubl
, _vsubl
, 3, (RNSDQMQ
, oRNSDMQ
, RNSDMQR
), neon_dyadic_long
),
26557 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26558 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26559 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26560 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26561 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
26562 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
26563 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
26564 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
26565 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26566 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
26567 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26568 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26569 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26570 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26571 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26572 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
26573 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26574 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26575 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
26576 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26577 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26578 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26579 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26580 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26581 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26582 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
26583 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
26584 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26585 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26586 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26587 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
26588 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
26589 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
26592 #define ARM_VARIANT & arm_ext_v8_3
26593 #undef THUMB_VARIANT
26594 #define THUMB_VARIANT & arm_ext_v6t2_v8m
26595 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
26596 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
26599 #define ARM_VARIANT &arm_ext_bf16
26600 #undef THUMB_VARIANT
26601 #define THUMB_VARIANT &arm_ext_bf16
26602 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
26603 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
26604 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
26607 #define ARM_VARIANT &arm_ext_i8mm
26608 #undef THUMB_VARIANT
26609 #define THUMB_VARIANT &arm_ext_i8mm
26610 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26611 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
26612 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26613 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
26614 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
26617 #undef THUMB_VARIANT
26618 #define THUMB_VARIANT &arm_ext_cde
26619 ToC ("cx1", ee000000
, 3, (RCP
, APSR_RR
, I8191
), cx1
),
26620 ToC ("cx1a", fe000000
, 3, (RCP
, APSR_RR
, I8191
), cx1a
),
26621 ToC ("cx1d", ee000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1d
),
26622 ToC ("cx1da", fe000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1da
),
26624 ToC ("cx2", ee400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2
),
26625 ToC ("cx2a", fe400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2a
),
26626 ToC ("cx2d", ee400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2d
),
26627 ToC ("cx2da", fe400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2da
),
26629 ToC ("cx3", ee800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3
),
26630 ToC ("cx3a", fe800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3a
),
26631 ToC ("cx3d", ee800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3d
),
26632 ToC ("cx3da", fe800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3da
),
26634 mToC ("vcx1", ec200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26635 mToC ("vcx1a", fc200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26637 mToC ("vcx2", ec300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26638 mToC ("vcx2a", fc300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26640 mToC ("vcx3", ec800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26641 mToC ("vcx3a", fc800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26645 #undef THUMB_VARIANT
26677 /* MD interface: bits in the object file. */
26679 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26680 for use in the a.out file, and stores them in the array pointed to by buf.
26681 This knows about the endian-ness of the target machine and does
26682 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26683 2 (short) and 4 (long) Floating numbers are put out as a series of
26684 LITTLENUMS (shorts, here at least). */
26687 md_number_to_chars (char * buf
, valueT val
, int n
)
26689 if (target_big_endian
)
26690 number_to_chars_bigendian (buf
, val
, n
);
26692 number_to_chars_littleendian (buf
, val
, n
);
26696 md_chars_to_number (char * buf
, int n
)
26699 unsigned char * where
= (unsigned char *) buf
;
26701 if (target_big_endian
)
26706 result
|= (*where
++ & 255);
26714 result
|= (where
[n
] & 255);
26721 /* MD interface: Sections. */
26723 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26724 that an rs_machine_dependent frag may reach. */
26727 arm_frag_max_var (fragS
*fragp
)
26729 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26730 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26732 Note that we generate relaxable instructions even for cases that don't
26733 really need it, like an immediate that's a trivial constant. So we're
26734 overestimating the instruction size for some of those cases. Rather
26735 than putting more intelligence here, it would probably be better to
26736 avoid generating a relaxation frag in the first place when it can be
26737 determined up front that a short instruction will suffice. */
26739 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26743 /* Estimate the size of a frag before relaxing. Assume everything fits in
26747 md_estimate_size_before_relax (fragS
* fragp
,
26748 segT segtype ATTRIBUTE_UNUSED
)
26754 /* Convert a machine dependent frag. */
26757 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26759 unsigned long insn
;
26760 unsigned long old_op
;
26768 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26770 old_op
= bfd_get_16(abfd
, buf
);
26771 if (fragp
->fr_symbol
)
26773 exp
.X_op
= O_symbol
;
26774 exp
.X_add_symbol
= fragp
->fr_symbol
;
26778 exp
.X_op
= O_constant
;
26780 exp
.X_add_number
= fragp
->fr_offset
;
26781 opcode
= fragp
->fr_subtype
;
26784 case T_MNEM_ldr_pc
:
26785 case T_MNEM_ldr_pc2
:
26786 case T_MNEM_ldr_sp
:
26787 case T_MNEM_str_sp
:
26794 if (fragp
->fr_var
== 4)
26796 insn
= THUMB_OP32 (opcode
);
26797 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26799 insn
|= (old_op
& 0x700) << 4;
26803 insn
|= (old_op
& 7) << 12;
26804 insn
|= (old_op
& 0x38) << 13;
26806 insn
|= 0x00000c00;
26807 put_thumb32_insn (buf
, insn
);
26808 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26812 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26814 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26817 if (fragp
->fr_var
== 4)
26819 insn
= THUMB_OP32 (opcode
);
26820 insn
|= (old_op
& 0xf0) << 4;
26821 put_thumb32_insn (buf
, insn
);
26822 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26826 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26827 exp
.X_add_number
-= 4;
26835 if (fragp
->fr_var
== 4)
26837 int r0off
= (opcode
== T_MNEM_mov
26838 || opcode
== T_MNEM_movs
) ? 0 : 8;
26839 insn
= THUMB_OP32 (opcode
);
26840 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26841 insn
|= (old_op
& 0x700) << r0off
;
26842 put_thumb32_insn (buf
, insn
);
26843 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26847 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26852 if (fragp
->fr_var
== 4)
26854 insn
= THUMB_OP32(opcode
);
26855 put_thumb32_insn (buf
, insn
);
26856 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26859 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26863 if (fragp
->fr_var
== 4)
26865 insn
= THUMB_OP32(opcode
);
26866 insn
|= (old_op
& 0xf00) << 14;
26867 put_thumb32_insn (buf
, insn
);
26868 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26871 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26874 case T_MNEM_add_sp
:
26875 case T_MNEM_add_pc
:
26876 case T_MNEM_inc_sp
:
26877 case T_MNEM_dec_sp
:
26878 if (fragp
->fr_var
== 4)
26880 /* ??? Choose between add and addw. */
26881 insn
= THUMB_OP32 (opcode
);
26882 insn
|= (old_op
& 0xf0) << 4;
26883 put_thumb32_insn (buf
, insn
);
26884 if (opcode
== T_MNEM_add_pc
)
26885 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26887 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26890 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26898 if (fragp
->fr_var
== 4)
26900 insn
= THUMB_OP32 (opcode
);
26901 insn
|= (old_op
& 0xf0) << 4;
26902 insn
|= (old_op
& 0xf) << 16;
26903 put_thumb32_insn (buf
, insn
);
26904 if (insn
& (1 << 20))
26905 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26907 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26910 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26916 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26917 (enum bfd_reloc_code_real
) reloc_type
);
26918 fixp
->fx_file
= fragp
->fr_file
;
26919 fixp
->fx_line
= fragp
->fr_line
;
26920 fragp
->fr_fix
+= fragp
->fr_var
;
26922 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26923 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26924 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26925 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26928 /* Return the size of a relaxable immediate operand instruction.
26929 SHIFT and SIZE specify the form of the allowable immediate. */
26931 relax_immediate (fragS
*fragp
, int size
, int shift
)
26937 /* ??? Should be able to do better than this. */
26938 if (fragp
->fr_symbol
)
26941 low
= (1 << shift
) - 1;
26942 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26943 offset
= fragp
->fr_offset
;
26944 /* Force misaligned offsets to 32-bit variant. */
26947 if (offset
& ~mask
)
26952 /* Get the address of a symbol during relaxation. */
26954 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26960 sym
= fragp
->fr_symbol
;
26961 sym_frag
= symbol_get_frag (sym
);
26962 know (S_GET_SEGMENT (sym
) != absolute_section
26963 || sym_frag
== &zero_address_frag
);
26964 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26966 /* If frag has yet to be reached on this pass, assume it will
26967 move by STRETCH just as we did. If this is not so, it will
26968 be because some frag between grows, and that will force
26972 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26976 /* Adjust stretch for any alignment frag. Note that if have
26977 been expanding the earlier code, the symbol may be
26978 defined in what appears to be an earlier frag. FIXME:
26979 This doesn't handle the fr_subtype field, which specifies
26980 a maximum number of bytes to skip when doing an
26982 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26984 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26987 stretch
= - ((- stretch
)
26988 & ~ ((1 << (int) f
->fr_offset
) - 1));
26990 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
27002 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
27005 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
27010 /* Assume worst case for symbols not known to be in the same section. */
27011 if (fragp
->fr_symbol
== NULL
27012 || !S_IS_DEFINED (fragp
->fr_symbol
)
27013 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27014 || S_IS_WEAK (fragp
->fr_symbol
))
27017 val
= relaxed_symbol_addr (fragp
, stretch
);
27018 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
27019 addr
= (addr
+ 4) & ~3;
27020 /* Force misaligned targets to 32-bit variant. */
27024 if (val
< 0 || val
> 1020)
27029 /* Return the size of a relaxable add/sub immediate instruction. */
27031 relax_addsub (fragS
*fragp
, asection
*sec
)
27036 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
27037 op
= bfd_get_16(sec
->owner
, buf
);
27038 if ((op
& 0xf) == ((op
>> 4) & 0xf))
27039 return relax_immediate (fragp
, 8, 0);
27041 return relax_immediate (fragp
, 3, 0);
27044 /* Return TRUE iff the definition of symbol S could be pre-empted
27045 (overridden) at link or load time. */
27047 symbol_preemptible (symbolS
*s
)
27049 /* Weak symbols can always be pre-empted. */
27053 /* Non-global symbols cannot be pre-empted. */
27054 if (! S_IS_EXTERNAL (s
))
27058 /* In ELF, a global symbol can be marked protected, or private. In that
27059 case it can't be pre-empted (other definitions in the same link unit
27060 would violate the ODR). */
27061 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
27065 /* Other global symbols might be pre-empted. */
27069 /* Return the size of a relaxable branch instruction. BITS is the
27070 size of the offset field in the narrow instruction. */
27073 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
27079 /* Assume worst case for symbols not known to be in the same section. */
27080 if (!S_IS_DEFINED (fragp
->fr_symbol
)
27081 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27082 || S_IS_WEAK (fragp
->fr_symbol
))
27086 /* A branch to a function in ARM state will require interworking. */
27087 if (S_IS_DEFINED (fragp
->fr_symbol
)
27088 && ARM_IS_FUNC (fragp
->fr_symbol
))
27092 if (symbol_preemptible (fragp
->fr_symbol
))
27095 val
= relaxed_symbol_addr (fragp
, stretch
);
27096 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
27099 /* Offset is a signed value *2 */
27101 if (val
>= limit
|| val
< -limit
)
27107 /* Relax a machine dependent frag. This returns the amount by which
27108 the current size of the frag should change. */
27111 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
27116 oldsize
= fragp
->fr_var
;
27117 switch (fragp
->fr_subtype
)
27119 case T_MNEM_ldr_pc2
:
27120 newsize
= relax_adr (fragp
, sec
, stretch
);
27122 case T_MNEM_ldr_pc
:
27123 case T_MNEM_ldr_sp
:
27124 case T_MNEM_str_sp
:
27125 newsize
= relax_immediate (fragp
, 8, 2);
27129 newsize
= relax_immediate (fragp
, 5, 2);
27133 newsize
= relax_immediate (fragp
, 5, 1);
27137 newsize
= relax_immediate (fragp
, 5, 0);
27140 newsize
= relax_adr (fragp
, sec
, stretch
);
27146 newsize
= relax_immediate (fragp
, 8, 0);
27149 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
27152 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
27154 case T_MNEM_add_sp
:
27155 case T_MNEM_add_pc
:
27156 newsize
= relax_immediate (fragp
, 8, 2);
27158 case T_MNEM_inc_sp
:
27159 case T_MNEM_dec_sp
:
27160 newsize
= relax_immediate (fragp
, 7, 2);
27166 newsize
= relax_addsub (fragp
, sec
);
27172 fragp
->fr_var
= newsize
;
27173 /* Freeze wide instructions that are at or before the same location as
27174 in the previous pass. This avoids infinite loops.
27175 Don't freeze them unconditionally because targets may be artificially
27176 misaligned by the expansion of preceding frags. */
27177 if (stretch
<= 0 && newsize
> 2)
27179 md_convert_frag (sec
->owner
, sec
, fragp
);
27183 return newsize
- oldsize
;
27186 /* Round up a section size to the appropriate boundary. */
27189 md_section_align (segT segment ATTRIBUTE_UNUSED
,
27195 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
27196 of an rs_align_code fragment. */
27199 arm_handle_align (fragS
* fragP
)
27201 static unsigned char const arm_noop
[2][2][4] =
27204 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
27205 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
27208 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
27209 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
27212 static unsigned char const thumb_noop
[2][2][2] =
27215 {0xc0, 0x46}, /* LE */
27216 {0x46, 0xc0}, /* BE */
27219 {0x00, 0xbf}, /* LE */
27220 {0xbf, 0x00} /* BE */
27223 static unsigned char const wide_thumb_noop
[2][4] =
27224 { /* Wide Thumb-2 */
27225 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
27226 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
27229 unsigned bytes
, fix
, noop_size
;
27231 const unsigned char * noop
;
27232 const unsigned char *narrow_noop
= NULL
;
27237 if (fragP
->fr_type
!= rs_align_code
)
27240 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
27241 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
27244 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27245 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
27247 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
27249 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
27251 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27252 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
27254 narrow_noop
= thumb_noop
[1][target_big_endian
];
27255 noop
= wide_thumb_noop
[target_big_endian
];
27258 noop
= thumb_noop
[0][target_big_endian
];
27266 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27267 ? selected_cpu
: arm_arch_none
,
27269 [target_big_endian
];
27276 fragP
->fr_var
= noop_size
;
27278 if (bytes
& (noop_size
- 1))
27280 fix
= bytes
& (noop_size
- 1);
27282 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
27284 memset (p
, 0, fix
);
27291 if (bytes
& noop_size
)
27293 /* Insert a narrow noop. */
27294 memcpy (p
, narrow_noop
, noop_size
);
27296 bytes
-= noop_size
;
27300 /* Use wide noops for the remainder */
27304 while (bytes
>= noop_size
)
27306 memcpy (p
, noop
, noop_size
);
27308 bytes
-= noop_size
;
27312 fragP
->fr_fix
+= fix
;
27315 /* Called from md_do_align. Used to create an alignment
27316 frag in a code section. */
27319 arm_frag_align_code (int n
, int max
)
27323 /* We assume that there will never be a requirement
27324 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
27325 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27330 _("alignments greater than %d bytes not supported in .text sections."),
27331 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
27332 as_fatal ("%s", err_msg
);
27335 p
= frag_var (rs_align_code
,
27336 MAX_MEM_FOR_RS_ALIGN_CODE
,
27338 (relax_substateT
) max
,
27345 /* Perform target specific initialisation of a frag.
27346 Note - despite the name this initialisation is not done when the frag
27347 is created, but only when its type is assigned. A frag can be created
27348 and used a long time before its type is set, so beware of assuming that
27349 this initialisation is performed first. */
27353 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
27355 /* Record whether this frag is in an ARM or a THUMB area. */
27356 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27359 #else /* OBJ_ELF is defined. */
27361 arm_init_frag (fragS
* fragP
, int max_chars
)
27363 bfd_boolean frag_thumb_mode
;
27365 /* If the current ARM vs THUMB mode has not already
27366 been recorded into this frag then do so now. */
27367 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
27368 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27370 /* PR 21809: Do not set a mapping state for debug sections
27371 - it just confuses other tools. */
27372 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
27375 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
27377 /* Record a mapping symbol for alignment frags. We will delete this
27378 later if the alignment ends up empty. */
27379 switch (fragP
->fr_type
)
27382 case rs_align_test
:
27384 mapping_state_2 (MAP_DATA
, max_chars
);
27386 case rs_align_code
:
27387 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
27394 /* When we change sections we need to issue a new mapping symbol. */
27397 arm_elf_change_section (void)
27399 /* Link an unlinked unwind index table section to the .text section. */
27400 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
27401 && elf_linked_to_section (now_seg
) == NULL
)
27402 elf_linked_to_section (now_seg
) = text_section
;
27406 arm_elf_section_type (const char * str
, size_t len
)
27408 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
27409 return SHT_ARM_EXIDX
;
27414 /* Code to deal with unwinding tables. */
27416 static void add_unwind_adjustsp (offsetT
);
27418 /* Generate any deferred unwind frame offset. */
27421 flush_pending_unwind (void)
27425 offset
= unwind
.pending_offset
;
27426 unwind
.pending_offset
= 0;
27428 add_unwind_adjustsp (offset
);
27431 /* Add an opcode to this list for this function. Two-byte opcodes should
27432 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
27436 add_unwind_opcode (valueT op
, int length
)
27438 /* Add any deferred stack adjustment. */
27439 if (unwind
.pending_offset
)
27440 flush_pending_unwind ();
27442 unwind
.sp_restored
= 0;
27444 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
27446 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
27447 if (unwind
.opcodes
)
27448 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
27449 unwind
.opcode_alloc
);
27451 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
27456 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
27458 unwind
.opcode_count
++;
27462 /* Add unwind opcodes to adjust the stack pointer. */
27465 add_unwind_adjustsp (offsetT offset
)
27469 if (offset
> 0x200)
27471 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
27476 /* Long form: 0xb2, uleb128. */
27477 /* This might not fit in a word so add the individual bytes,
27478 remembering the list is built in reverse order. */
27479 o
= (valueT
) ((offset
- 0x204) >> 2);
27481 add_unwind_opcode (0, 1);
27483 /* Calculate the uleb128 encoding of the offset. */
27487 bytes
[n
] = o
& 0x7f;
27493 /* Add the insn. */
27495 add_unwind_opcode (bytes
[n
- 1], 1);
27496 add_unwind_opcode (0xb2, 1);
27498 else if (offset
> 0x100)
27500 /* Two short opcodes. */
27501 add_unwind_opcode (0x3f, 1);
27502 op
= (offset
- 0x104) >> 2;
27503 add_unwind_opcode (op
, 1);
27505 else if (offset
> 0)
27507 /* Short opcode. */
27508 op
= (offset
- 4) >> 2;
27509 add_unwind_opcode (op
, 1);
27511 else if (offset
< 0)
27514 while (offset
> 0x100)
27516 add_unwind_opcode (0x7f, 1);
27519 op
= ((offset
- 4) >> 2) | 0x40;
27520 add_unwind_opcode (op
, 1);
27524 /* Finish the list of unwind opcodes for this function. */
27527 finish_unwind_opcodes (void)
27531 if (unwind
.fp_used
)
27533 /* Adjust sp as necessary. */
27534 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
27535 flush_pending_unwind ();
27537 /* After restoring sp from the frame pointer. */
27538 op
= 0x90 | unwind
.fp_reg
;
27539 add_unwind_opcode (op
, 1);
27542 flush_pending_unwind ();
27546 /* Start an exception table entry. If idx is nonzero this is an index table
27550 start_unwind_section (const segT text_seg
, int idx
)
27552 const char * text_name
;
27553 const char * prefix
;
27554 const char * prefix_once
;
27555 struct elf_section_match match
;
27563 prefix
= ELF_STRING_ARM_unwind
;
27564 prefix_once
= ELF_STRING_ARM_unwind_once
;
27565 type
= SHT_ARM_EXIDX
;
27569 prefix
= ELF_STRING_ARM_unwind_info
;
27570 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
27571 type
= SHT_PROGBITS
;
27574 text_name
= segment_name (text_seg
);
27575 if (streq (text_name
, ".text"))
27578 if (strncmp (text_name
, ".gnu.linkonce.t.",
27579 strlen (".gnu.linkonce.t.")) == 0)
27581 prefix
= prefix_once
;
27582 text_name
+= strlen (".gnu.linkonce.t.");
27585 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
27589 memset (&match
, 0, sizeof (match
));
27591 /* Handle COMDAT group. */
27592 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
27594 match
.group_name
= elf_group_name (text_seg
);
27595 if (match
.group_name
== NULL
)
27597 as_bad (_("Group section `%s' has no group signature"),
27598 segment_name (text_seg
));
27599 ignore_rest_of_line ();
27602 flags
|= SHF_GROUP
;
27606 obj_elf_change_section (sec_name
, type
, flags
, 0, &match
,
27609 /* Set the section link for index tables. */
27611 elf_linked_to_section (now_seg
) = text_seg
;
27615 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27616 personality routine data. Returns zero, or the index table value for
27617 an inline entry. */
27620 create_unwind_entry (int have_data
)
27625 /* The current word of data. */
27627 /* The number of bytes left in this word. */
27630 finish_unwind_opcodes ();
27632 /* Remember the current text section. */
27633 unwind
.saved_seg
= now_seg
;
27634 unwind
.saved_subseg
= now_subseg
;
27636 start_unwind_section (now_seg
, 0);
27638 if (unwind
.personality_routine
== NULL
)
27640 if (unwind
.personality_index
== -2)
27643 as_bad (_("handlerdata in cantunwind frame"));
27644 return 1; /* EXIDX_CANTUNWIND. */
27647 /* Use a default personality routine if none is specified. */
27648 if (unwind
.personality_index
== -1)
27650 if (unwind
.opcode_count
> 3)
27651 unwind
.personality_index
= 1;
27653 unwind
.personality_index
= 0;
27656 /* Space for the personality routine entry. */
27657 if (unwind
.personality_index
== 0)
27659 if (unwind
.opcode_count
> 3)
27660 as_bad (_("too many unwind opcodes for personality routine 0"));
27664 /* All the data is inline in the index table. */
27667 while (unwind
.opcode_count
> 0)
27669 unwind
.opcode_count
--;
27670 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27674 /* Pad with "finish" opcodes. */
27676 data
= (data
<< 8) | 0xb0;
27683 /* We get two opcodes "free" in the first word. */
27684 size
= unwind
.opcode_count
- 2;
27688 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27689 if (unwind
.personality_index
!= -1)
27691 as_bad (_("attempt to recreate an unwind entry"));
27695 /* An extra byte is required for the opcode count. */
27696 size
= unwind
.opcode_count
+ 1;
27699 size
= (size
+ 3) >> 2;
27701 as_bad (_("too many unwind opcodes"));
27703 frag_align (2, 0, 0);
27704 record_alignment (now_seg
, 2);
27705 unwind
.table_entry
= expr_build_dot ();
27707 /* Allocate the table entry. */
27708 ptr
= frag_more ((size
<< 2) + 4);
27709 /* PR 13449: Zero the table entries in case some of them are not used. */
27710 memset (ptr
, 0, (size
<< 2) + 4);
27711 where
= frag_now_fix () - ((size
<< 2) + 4);
27713 switch (unwind
.personality_index
)
27716 /* ??? Should this be a PLT generating relocation? */
27717 /* Custom personality routine. */
27718 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27719 BFD_RELOC_ARM_PREL31
);
27724 /* Set the first byte to the number of additional words. */
27725 data
= size
> 0 ? size
- 1 : 0;
27729 /* ABI defined personality routines. */
27731 /* Three opcodes bytes are packed into the first word. */
27738 /* The size and first two opcode bytes go in the first word. */
27739 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27744 /* Should never happen. */
27748 /* Pack the opcodes into words (MSB first), reversing the list at the same
27750 while (unwind
.opcode_count
> 0)
27754 md_number_to_chars (ptr
, data
, 4);
27759 unwind
.opcode_count
--;
27761 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27764 /* Finish off the last word. */
27767 /* Pad with "finish" opcodes. */
27769 data
= (data
<< 8) | 0xb0;
27771 md_number_to_chars (ptr
, data
, 4);
27776 /* Add an empty descriptor if there is no user-specified data. */
27777 ptr
= frag_more (4);
27778 md_number_to_chars (ptr
, 0, 4);
27785 /* Initialize the DWARF-2 unwind information for this procedure. */
27788 tc_arm_frame_initial_instructions (void)
27790 cfi_add_CFA_def_cfa (REG_SP
, 0);
27792 #endif /* OBJ_ELF */
27794 /* Convert REGNAME to a DWARF-2 register number. */
27797 tc_arm_regname_to_dw2regnum (char *regname
)
27799 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27803 /* PR 16694: Allow VFP registers as well. */
27804 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27808 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27817 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27821 exp
.X_op
= O_secrel
;
27822 exp
.X_add_symbol
= symbol
;
27823 exp
.X_add_number
= 0;
27824 emit_expr (&exp
, size
);
27828 /* MD interface: Symbol and relocation handling. */
27830 /* Return the address within the segment that a PC-relative fixup is
27831 relative to. For ARM, PC-relative fixups applied to instructions
27832 are generally relative to the location of the fixup plus 8 bytes.
27833 Thumb branches are offset by 4, and Thumb loads relative to PC
27834 require special handling. */
27837 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27839 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27841 /* If this is pc-relative and we are going to emit a relocation
27842 then we just want to put out any pipeline compensation that the linker
27843 will need. Otherwise we want to use the calculated base.
27844 For WinCE we skip the bias for externals as well, since this
27845 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27847 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27848 || (arm_force_relocation (fixP
)
27850 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27856 switch (fixP
->fx_r_type
)
27858 /* PC relative addressing on the Thumb is slightly odd as the
27859 bottom two bits of the PC are forced to zero for the
27860 calculation. This happens *after* application of the
27861 pipeline offset. However, Thumb adrl already adjusts for
27862 this, so we need not do it again. */
27863 case BFD_RELOC_ARM_THUMB_ADD
:
27866 case BFD_RELOC_ARM_THUMB_OFFSET
:
27867 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27868 case BFD_RELOC_ARM_T32_ADD_PC12
:
27869 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27870 return (base
+ 4) & ~3;
27872 /* Thumb branches are simply offset by +4. */
27873 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27874 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27875 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27876 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27877 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27878 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27879 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27880 case BFD_RELOC_ARM_THUMB_BF17
:
27881 case BFD_RELOC_ARM_THUMB_BF19
:
27882 case BFD_RELOC_ARM_THUMB_BF13
:
27883 case BFD_RELOC_ARM_THUMB_LOOP12
:
27886 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27888 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27889 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27890 && ARM_IS_FUNC (fixP
->fx_addsy
)
27891 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27892 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27895 /* BLX is like branches above, but forces the low two bits of PC to
27897 case BFD_RELOC_THUMB_PCREL_BLX
:
27899 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27900 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27901 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27902 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27903 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27904 return (base
+ 4) & ~3;
27906 /* ARM mode branches are offset by +8. However, the Windows CE
27907 loader expects the relocation not to take this into account. */
27908 case BFD_RELOC_ARM_PCREL_BLX
:
27910 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27911 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27912 && ARM_IS_FUNC (fixP
->fx_addsy
)
27913 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27914 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27917 case BFD_RELOC_ARM_PCREL_CALL
:
27919 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27920 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27921 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27922 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27923 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27926 case BFD_RELOC_ARM_PCREL_BRANCH
:
27927 case BFD_RELOC_ARM_PCREL_JUMP
:
27928 case BFD_RELOC_ARM_PLT32
:
27930 /* When handling fixups immediately, because we have already
27931 discovered the value of a symbol, or the address of the frag involved
27932 we must account for the offset by +8, as the OS loader will never see the reloc.
27933 see fixup_segment() in write.c
27934 The S_IS_EXTERNAL test handles the case of global symbols.
27935 Those need the calculated base, not just the pipe compensation the linker will need. */
27937 && fixP
->fx_addsy
!= NULL
27938 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27939 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27947 /* ARM mode loads relative to PC are also offset by +8. Unlike
27948 branches, the Windows CE loader *does* expect the relocation
27949 to take this into account. */
27950 case BFD_RELOC_ARM_OFFSET_IMM
:
27951 case BFD_RELOC_ARM_OFFSET_IMM8
:
27952 case BFD_RELOC_ARM_HWLITERAL
:
27953 case BFD_RELOC_ARM_LITERAL
:
27954 case BFD_RELOC_ARM_CP_OFF_IMM
:
27958 /* Other PC-relative relocations are un-offset. */
27964 static bfd_boolean flag_warn_syms
= TRUE
;
27967 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27969 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27970 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27971 does mean that the resulting code might be very confusing to the reader.
27972 Also this warning can be triggered if the user omits an operand before
27973 an immediate address, eg:
27977 GAS treats this as an assignment of the value of the symbol foo to a
27978 symbol LDR, and so (without this code) it will not issue any kind of
27979 warning or error message.
27981 Note - ARM instructions are case-insensitive but the strings in the hash
27982 table are all stored in lower case, so we must first ensure that name is
27984 if (flag_warn_syms
&& arm_ops_hsh
)
27986 char * nbuf
= strdup (name
);
27989 for (p
= nbuf
; *p
; p
++)
27991 if (str_hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27993 static htab_t already_warned
= NULL
;
27995 if (already_warned
== NULL
)
27996 already_warned
= str_htab_create ();
27997 /* Only warn about the symbol once. To keep the code
27998 simple we let str_hash_insert do the lookup for us. */
27999 if (str_hash_find (already_warned
, nbuf
) == NULL
)
28001 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
28002 str_hash_insert (already_warned
, nbuf
, NULL
);
28012 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28013 Otherwise we have no need to default values of symbols. */
28016 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
28019 if (name
[0] == '_' && name
[1] == 'G'
28020 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
28024 if (symbol_find (name
))
28025 as_bad (_("GOT already in the symbol table"));
28027 GOT_symbol
= symbol_new (name
, undefined_section
,
28028 &zero_address_frag
, 0);
28038 /* Subroutine of md_apply_fix. Check to see if an immediate can be
28039 computed as two separate immediate values, added together. We
28040 already know that this value cannot be computed by just one ARM
28043 static unsigned int
28044 validate_immediate_twopart (unsigned int val
,
28045 unsigned int * highpart
)
28050 for (i
= 0; i
< 32; i
+= 2)
28051 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
28057 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
28059 else if (a
& 0xff0000)
28061 if (a
& 0xff000000)
28063 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
28067 gas_assert (a
& 0xff000000);
28068 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
28071 return (a
& 0xff) | (i
<< 7);
28078 validate_offset_imm (unsigned int val
, int hwse
)
28080 if ((hwse
&& val
> 255) || val
> 4095)
28085 /* Subroutine of md_apply_fix. Do those data_ops which can take a
28086 negative immediate constant by altering the instruction. A bit of
28091 by inverting the second operand, and
28094 by negating the second operand. */
28097 negate_data_op (unsigned long * instruction
,
28098 unsigned long value
)
28101 unsigned long negated
, inverted
;
28103 negated
= encode_arm_immediate (-value
);
28104 inverted
= encode_arm_immediate (~value
);
28106 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
28109 /* First negates. */
28110 case OPCODE_SUB
: /* ADD <-> SUB */
28111 new_inst
= OPCODE_ADD
;
28116 new_inst
= OPCODE_SUB
;
28120 case OPCODE_CMP
: /* CMP <-> CMN */
28121 new_inst
= OPCODE_CMN
;
28126 new_inst
= OPCODE_CMP
;
28130 /* Now Inverted ops. */
28131 case OPCODE_MOV
: /* MOV <-> MVN */
28132 new_inst
= OPCODE_MVN
;
28137 new_inst
= OPCODE_MOV
;
28141 case OPCODE_AND
: /* AND <-> BIC */
28142 new_inst
= OPCODE_BIC
;
28147 new_inst
= OPCODE_AND
;
28151 case OPCODE_ADC
: /* ADC <-> SBC */
28152 new_inst
= OPCODE_SBC
;
28157 new_inst
= OPCODE_ADC
;
28161 /* We cannot do anything. */
28166 if (value
== (unsigned) FAIL
)
28169 *instruction
&= OPCODE_MASK
;
28170 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
28174 /* Like negate_data_op, but for Thumb-2. */
28176 static unsigned int
28177 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
28181 unsigned int negated
, inverted
;
28183 negated
= encode_thumb32_immediate (-value
);
28184 inverted
= encode_thumb32_immediate (~value
);
28186 rd
= (*instruction
>> 8) & 0xf;
28187 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
28190 /* ADD <-> SUB. Includes CMP <-> CMN. */
28191 case T2_OPCODE_SUB
:
28192 new_inst
= T2_OPCODE_ADD
;
28196 case T2_OPCODE_ADD
:
28197 new_inst
= T2_OPCODE_SUB
;
28201 /* ORR <-> ORN. Includes MOV <-> MVN. */
28202 case T2_OPCODE_ORR
:
28203 new_inst
= T2_OPCODE_ORN
;
28207 case T2_OPCODE_ORN
:
28208 new_inst
= T2_OPCODE_ORR
;
28212 /* AND <-> BIC. TST has no inverted equivalent. */
28213 case T2_OPCODE_AND
:
28214 new_inst
= T2_OPCODE_BIC
;
28221 case T2_OPCODE_BIC
:
28222 new_inst
= T2_OPCODE_AND
;
28227 case T2_OPCODE_ADC
:
28228 new_inst
= T2_OPCODE_SBC
;
28232 case T2_OPCODE_SBC
:
28233 new_inst
= T2_OPCODE_ADC
;
28237 /* We cannot do anything. */
28242 if (value
== (unsigned int)FAIL
)
28245 *instruction
&= T2_OPCODE_MASK
;
28246 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
28250 /* Read a 32-bit thumb instruction from buf. */
28252 static unsigned long
28253 get_thumb32_insn (char * buf
)
28255 unsigned long insn
;
28256 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
28257 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28262 /* We usually want to set the low bit on the address of thumb function
28263 symbols. In particular .word foo - . should have the low bit set.
28264 Generic code tries to fold the difference of two symbols to
28265 a constant. Prevent this and force a relocation when the first symbols
28266 is a thumb function. */
28269 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
28271 if (op
== O_subtract
28272 && l
->X_op
== O_symbol
28273 && r
->X_op
== O_symbol
28274 && THUMB_IS_FUNC (l
->X_add_symbol
))
28276 l
->X_op
= O_subtract
;
28277 l
->X_op_symbol
= r
->X_add_symbol
;
28278 l
->X_add_number
-= r
->X_add_number
;
28282 /* Process as normal. */
28286 /* Encode Thumb2 unconditional branches and calls. The encoding
28287 for the 2 are identical for the immediate values. */
28290 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
28292 #define T2I1I2MASK ((1 << 13) | (1 << 11))
28295 addressT S
, I1
, I2
, lo
, hi
;
28297 S
= (value
>> 24) & 0x01;
28298 I1
= (value
>> 23) & 0x01;
28299 I2
= (value
>> 22) & 0x01;
28300 hi
= (value
>> 12) & 0x3ff;
28301 lo
= (value
>> 1) & 0x7ff;
28302 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28303 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28304 newval
|= (S
<< 10) | hi
;
28305 newval2
&= ~T2I1I2MASK
;
28306 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
28307 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28308 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28312 md_apply_fix (fixS
* fixP
,
28316 offsetT value
= * valP
;
28318 unsigned int newimm
;
28319 unsigned long temp
;
28321 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
28323 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
28325 /* Note whether this will delete the relocation. */
28327 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
28330 /* On a 64-bit host, silently truncate 'value' to 32 bits for
28331 consistency with the behaviour on 32-bit hosts. Remember value
28333 value
&= 0xffffffff;
28334 value
^= 0x80000000;
28335 value
-= 0x80000000;
28338 fixP
->fx_addnumber
= value
;
28340 /* Same treatment for fixP->fx_offset. */
28341 fixP
->fx_offset
&= 0xffffffff;
28342 fixP
->fx_offset
^= 0x80000000;
28343 fixP
->fx_offset
-= 0x80000000;
28345 switch (fixP
->fx_r_type
)
28347 case BFD_RELOC_NONE
:
28348 /* This will need to go in the object file. */
28352 case BFD_RELOC_ARM_IMMEDIATE
:
28353 /* We claim that this fixup has been processed here,
28354 even if in fact we generate an error because we do
28355 not have a reloc for it, so tc_gen_reloc will reject it. */
28358 if (fixP
->fx_addsy
)
28360 const char *msg
= 0;
28362 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28363 msg
= _("undefined symbol %s used as an immediate value");
28364 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28365 msg
= _("symbol %s is in a different section");
28366 else if (S_IS_WEAK (fixP
->fx_addsy
))
28367 msg
= _("symbol %s is weak and may be overridden later");
28371 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28372 msg
, S_GET_NAME (fixP
->fx_addsy
));
28377 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28379 /* If the offset is negative, we should use encoding A2 for ADR. */
28380 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
28381 newimm
= negate_data_op (&temp
, value
);
28384 newimm
= encode_arm_immediate (value
);
28386 /* If the instruction will fail, see if we can fix things up by
28387 changing the opcode. */
28388 if (newimm
== (unsigned int) FAIL
)
28389 newimm
= negate_data_op (&temp
, value
);
28390 /* MOV accepts both ARM modified immediate (A1 encoding) and
28391 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28392 When disassembling, MOV is preferred when there is no encoding
28394 if (newimm
== (unsigned int) FAIL
28395 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
28396 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
28397 && !((temp
>> SBIT_SHIFT
) & 0x1)
28398 && value
>= 0 && value
<= 0xffff)
28400 /* Clear bits[23:20] to change encoding from A1 to A2. */
28401 temp
&= 0xff0fffff;
28402 /* Encoding high 4bits imm. Code below will encode the remaining
28404 temp
|= (value
& 0x0000f000) << 4;
28405 newimm
= value
& 0x00000fff;
28409 if (newimm
== (unsigned int) FAIL
)
28411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28412 _("invalid constant (%lx) after fixup"),
28413 (unsigned long) value
);
28417 newimm
|= (temp
& 0xfffff000);
28418 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28421 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28423 unsigned int highpart
= 0;
28424 unsigned int newinsn
= 0xe1a00000; /* nop. */
28426 if (fixP
->fx_addsy
)
28428 const char *msg
= 0;
28430 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28431 msg
= _("undefined symbol %s used as an immediate value");
28432 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28433 msg
= _("symbol %s is in a different section");
28434 else if (S_IS_WEAK (fixP
->fx_addsy
))
28435 msg
= _("symbol %s is weak and may be overridden later");
28439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28440 msg
, S_GET_NAME (fixP
->fx_addsy
));
28445 newimm
= encode_arm_immediate (value
);
28446 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28448 /* If the instruction will fail, see if we can fix things up by
28449 changing the opcode. */
28450 if (newimm
== (unsigned int) FAIL
28451 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
28453 /* No ? OK - try using two ADD instructions to generate
28455 newimm
= validate_immediate_twopart (value
, & highpart
);
28457 /* Yes - then make sure that the second instruction is
28459 if (newimm
!= (unsigned int) FAIL
)
28461 /* Still No ? Try using a negated value. */
28462 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
28463 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
28464 /* Otherwise - give up. */
28467 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28468 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28473 /* Replace the first operand in the 2nd instruction (which
28474 is the PC) with the destination register. We have
28475 already added in the PC in the first instruction and we
28476 do not want to do it again. */
28477 newinsn
&= ~ 0xf0000;
28478 newinsn
|= ((newinsn
& 0x0f000) << 4);
28481 newimm
|= (temp
& 0xfffff000);
28482 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28484 highpart
|= (newinsn
& 0xfffff000);
28485 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
28489 case BFD_RELOC_ARM_OFFSET_IMM
:
28490 if (!fixP
->fx_done
&& seg
->use_rela_p
)
28492 /* Fall through. */
28494 case BFD_RELOC_ARM_LITERAL
:
28500 if (validate_offset_imm (value
, 0) == FAIL
)
28502 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
28503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28504 _("invalid literal constant: pool needs to be closer"));
28506 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28507 _("bad immediate value for offset (%ld)"),
28512 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28514 newval
&= 0xfffff000;
28517 newval
&= 0xff7ff000;
28518 newval
|= value
| (sign
? INDEX_UP
: 0);
28520 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28523 case BFD_RELOC_ARM_OFFSET_IMM8
:
28524 case BFD_RELOC_ARM_HWLITERAL
:
28530 if (validate_offset_imm (value
, 1) == FAIL
)
28532 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
28533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28534 _("invalid literal constant: pool needs to be closer"));
28536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28537 _("bad immediate value for 8-bit offset (%ld)"),
28542 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28544 newval
&= 0xfffff0f0;
28547 newval
&= 0xff7ff0f0;
28548 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
28550 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28553 case BFD_RELOC_ARM_T32_OFFSET_U8
:
28554 if (value
< 0 || value
> 1020 || value
% 4 != 0)
28555 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28556 _("bad immediate value for offset (%ld)"), (long) value
);
28559 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
28561 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
28564 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
28565 /* This is a complicated relocation used for all varieties of Thumb32
28566 load/store instruction with immediate offset:
28568 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28569 *4, optional writeback(W)
28570 (doubleword load/store)
28572 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28573 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28574 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28575 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28576 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28578 Uppercase letters indicate bits that are already encoded at
28579 this point. Lowercase letters are our problem. For the
28580 second block of instructions, the secondary opcode nybble
28581 (bits 8..11) is present, and bit 23 is zero, even if this is
28582 a PC-relative operation. */
28583 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28585 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
28587 if ((newval
& 0xf0000000) == 0xe0000000)
28589 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28591 newval
|= (1 << 23);
28594 if (value
% 4 != 0)
28596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28597 _("offset not a multiple of 4"));
28603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28604 _("offset out of range"));
28609 else if ((newval
& 0x000f0000) == 0x000f0000)
28611 /* PC-relative, 12-bit offset. */
28613 newval
|= (1 << 23);
28618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28619 _("offset out of range"));
28624 else if ((newval
& 0x00000100) == 0x00000100)
28626 /* Writeback: 8-bit, +/- offset. */
28628 newval
|= (1 << 9);
28633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28634 _("offset out of range"));
28639 else if ((newval
& 0x00000f00) == 0x00000e00)
28641 /* T-instruction: positive 8-bit offset. */
28642 if (value
< 0 || value
> 0xff)
28644 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28645 _("offset out of range"));
28653 /* Positive 12-bit or negative 8-bit offset. */
28657 newval
|= (1 << 23);
28667 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28668 _("offset out of range"));
28675 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
28676 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
28679 case BFD_RELOC_ARM_SHIFT_IMM
:
28680 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28681 if (((unsigned long) value
) > 32
28683 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
28685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28686 _("shift expression is too large"));
28691 /* Shifts of zero must be done as lsl. */
28693 else if (value
== 32)
28695 newval
&= 0xfffff07f;
28696 newval
|= (value
& 0x1f) << 7;
28697 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28700 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28701 case BFD_RELOC_ARM_T32_ADD_IMM
:
28702 case BFD_RELOC_ARM_T32_IMM12
:
28703 case BFD_RELOC_ARM_T32_ADD_PC12
:
28704 /* We claim that this fixup has been processed here,
28705 even if in fact we generate an error because we do
28706 not have a reloc for it, so tc_gen_reloc will reject it. */
28710 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28713 _("undefined symbol %s used as an immediate value"),
28714 S_GET_NAME (fixP
->fx_addsy
));
28718 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28720 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28723 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28724 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28725 Thumb2 modified immediate encoding (T2). */
28726 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28727 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28729 newimm
= encode_thumb32_immediate (value
);
28730 if (newimm
== (unsigned int) FAIL
)
28731 newimm
= thumb32_negate_data_op (&newval
, value
);
28733 if (newimm
== (unsigned int) FAIL
)
28735 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28737 /* Turn add/sum into addw/subw. */
28738 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28739 newval
= (newval
& 0xfeffffff) | 0x02000000;
28740 /* No flat 12-bit imm encoding for addsw/subsw. */
28741 if ((newval
& 0x00100000) == 0)
28743 /* 12 bit immediate for addw/subw. */
28747 newval
^= 0x00a00000;
28750 newimm
= (unsigned int) FAIL
;
28757 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28758 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28759 disassembling, MOV is preferred when there is no encoding
28761 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28762 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28763 but with the Rn field [19:16] set to 1111. */
28764 && (((newval
>> 16) & 0xf) == 0xf)
28765 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28766 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28767 && value
>= 0 && value
<= 0xffff)
28769 /* Toggle bit[25] to change encoding from T2 to T3. */
28771 /* Clear bits[19:16]. */
28772 newval
&= 0xfff0ffff;
28773 /* Encoding high 4bits imm. Code below will encode the
28774 remaining low 12bits. */
28775 newval
|= (value
& 0x0000f000) << 4;
28776 newimm
= value
& 0x00000fff;
28781 if (newimm
== (unsigned int)FAIL
)
28783 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28784 _("invalid constant (%lx) after fixup"),
28785 (unsigned long) value
);
28789 newval
|= (newimm
& 0x800) << 15;
28790 newval
|= (newimm
& 0x700) << 4;
28791 newval
|= (newimm
& 0x0ff);
28793 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28794 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28797 case BFD_RELOC_ARM_SMC
:
28798 if (((unsigned long) value
) > 0xf)
28799 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28800 _("invalid smc expression"));
28802 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28803 newval
|= (value
& 0xf);
28804 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28807 case BFD_RELOC_ARM_HVC
:
28808 if (((unsigned long) value
) > 0xffff)
28809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28810 _("invalid hvc expression"));
28811 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28812 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28813 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28816 case BFD_RELOC_ARM_SWI
:
28817 if (fixP
->tc_fix_data
!= 0)
28819 if (((unsigned long) value
) > 0xff)
28820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28821 _("invalid swi expression"));
28822 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28824 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28828 if (((unsigned long) value
) > 0x00ffffff)
28829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28830 _("invalid swi expression"));
28831 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28833 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28837 case BFD_RELOC_ARM_MULTI
:
28838 if (((unsigned long) value
) > 0xffff)
28839 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28840 _("invalid expression in load/store multiple"));
28841 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28842 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28846 case BFD_RELOC_ARM_PCREL_CALL
:
28848 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28850 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28851 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28852 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28853 /* Flip the bl to blx. This is a simple flip
28854 bit here because we generate PCREL_CALL for
28855 unconditional bls. */
28857 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28858 newval
= newval
| 0x10000000;
28859 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28865 goto arm_branch_common
;
28867 case BFD_RELOC_ARM_PCREL_JUMP
:
28868 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28870 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28871 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28872 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28874 /* This would map to a bl<cond>, b<cond>,
28875 b<always> to a Thumb function. We
28876 need to force a relocation for this particular
28878 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28881 /* Fall through. */
28883 case BFD_RELOC_ARM_PLT32
:
28885 case BFD_RELOC_ARM_PCREL_BRANCH
:
28887 goto arm_branch_common
;
28889 case BFD_RELOC_ARM_PCREL_BLX
:
28892 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28894 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28895 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28896 && ARM_IS_FUNC (fixP
->fx_addsy
))
28898 /* Flip the blx to a bl and warn. */
28899 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28900 newval
= 0xeb000000;
28901 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28902 _("blx to '%s' an ARM ISA state function changed to bl"),
28904 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28910 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28911 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28915 /* We are going to store value (shifted right by two) in the
28916 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28917 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28921 _("misaligned branch destination"));
28922 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
28923 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
28924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28926 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28928 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28929 newval
|= (value
>> 2) & 0x00ffffff;
28930 /* Set the H bit on BLX instructions. */
28934 newval
|= 0x01000000;
28936 newval
&= ~0x01000000;
28938 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28942 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28943 /* CBZ can only branch forward. */
28945 /* Attempts to use CBZ to branch to the next instruction
28946 (which, strictly speaking, are prohibited) will be turned into
28949 FIXME: It may be better to remove the instruction completely and
28950 perform relaxation. */
28953 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28954 newval
= 0xbf00; /* NOP encoding T1 */
28955 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28962 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28964 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28965 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28966 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28971 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28972 if (out_of_range_p (value
, 8))
28973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28975 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28977 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28978 newval
|= (value
& 0x1ff) >> 1;
28979 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28983 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28984 if (out_of_range_p (value
, 11))
28985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28987 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28989 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28990 newval
|= (value
& 0xfff) >> 1;
28991 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28995 /* This relocation is misnamed, it should be BRANCH21. */
28996 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28998 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28999 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29000 && ARM_IS_FUNC (fixP
->fx_addsy
)
29001 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29003 /* Force a relocation for a branch 20 bits wide. */
29006 if (out_of_range_p (value
, 20))
29007 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29008 _("conditional branch out of range"));
29010 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29013 addressT S
, J1
, J2
, lo
, hi
;
29015 S
= (value
& 0x00100000) >> 20;
29016 J2
= (value
& 0x00080000) >> 19;
29017 J1
= (value
& 0x00040000) >> 18;
29018 hi
= (value
& 0x0003f000) >> 12;
29019 lo
= (value
& 0x00000ffe) >> 1;
29021 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29022 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29023 newval
|= (S
<< 10) | hi
;
29024 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
29025 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29026 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29030 case BFD_RELOC_THUMB_PCREL_BLX
:
29031 /* If there is a blx from a thumb state function to
29032 another thumb function flip this to a bl and warn
29036 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29037 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29038 && THUMB_IS_FUNC (fixP
->fx_addsy
))
29040 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
29041 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29042 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29044 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29045 newval
= newval
| 0x1000;
29046 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29047 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29052 goto thumb_bl_common
;
29054 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29055 /* A bl from Thumb state ISA to an internal ARM state function
29056 is converted to a blx. */
29058 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29059 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29060 && ARM_IS_FUNC (fixP
->fx_addsy
)
29061 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29063 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29064 newval
= newval
& ~0x1000;
29065 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29066 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
29072 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29073 /* For a BLX instruction, make sure that the relocation is rounded up
29074 to a word boundary. This follows the semantics of the instruction
29075 which specifies that bit 1 of the target address will come from bit
29076 1 of the base address. */
29077 value
= (value
+ 3) & ~ 3;
29080 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
29081 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29082 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29085 if (out_of_range_p (value
, 22))
29087 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
29088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29089 else if (out_of_range_p (value
, 24))
29090 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29091 _("Thumb2 branch out of range"));
29094 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29095 encode_thumb2_b_bl_offset (buf
, value
);
29099 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29100 if (out_of_range_p (value
, 24))
29101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29103 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29104 encode_thumb2_b_bl_offset (buf
, value
);
29109 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29114 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29115 md_number_to_chars (buf
, value
, 2);
29119 case BFD_RELOC_ARM_TLS_CALL
:
29120 case BFD_RELOC_ARM_THM_TLS_CALL
:
29121 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29122 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29123 case BFD_RELOC_ARM_TLS_GOTDESC
:
29124 case BFD_RELOC_ARM_TLS_GD32
:
29125 case BFD_RELOC_ARM_TLS_LE32
:
29126 case BFD_RELOC_ARM_TLS_IE32
:
29127 case BFD_RELOC_ARM_TLS_LDM32
:
29128 case BFD_RELOC_ARM_TLS_LDO32
:
29129 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29132 /* Same handling as above, but with the arm_fdpic guard. */
29133 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29134 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29135 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29138 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29143 _("Relocation supported only in FDPIC mode"));
29147 case BFD_RELOC_ARM_GOT32
:
29148 case BFD_RELOC_ARM_GOTOFF
:
29151 case BFD_RELOC_ARM_GOT_PREL
:
29152 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29153 md_number_to_chars (buf
, value
, 4);
29156 case BFD_RELOC_ARM_TARGET2
:
29157 /* TARGET2 is not partial-inplace, so we need to write the
29158 addend here for REL targets, because it won't be written out
29159 during reloc processing later. */
29160 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29161 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
29164 /* Relocations for FDPIC. */
29165 case BFD_RELOC_ARM_GOTFUNCDESC
:
29166 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29167 case BFD_RELOC_ARM_FUNCDESC
:
29170 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29171 md_number_to_chars (buf
, 0, 4);
29175 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29176 _("Relocation supported only in FDPIC mode"));
29181 case BFD_RELOC_RVA
:
29183 case BFD_RELOC_ARM_TARGET1
:
29184 case BFD_RELOC_ARM_ROSEGREL32
:
29185 case BFD_RELOC_ARM_SBREL32
:
29186 case BFD_RELOC_32_PCREL
:
29188 case BFD_RELOC_32_SECREL
:
29190 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29192 /* For WinCE we only do this for pcrel fixups. */
29193 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
29195 md_number_to_chars (buf
, value
, 4);
29199 case BFD_RELOC_ARM_PREL31
:
29200 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29202 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
29203 if ((value
^ (value
>> 1)) & 0x40000000)
29205 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29206 _("rel31 relocation overflow"));
29208 newval
|= value
& 0x7fffffff;
29209 md_number_to_chars (buf
, newval
, 4);
29214 case BFD_RELOC_ARM_CP_OFF_IMM
:
29215 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
29216 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
29217 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
29218 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29220 newval
= get_thumb32_insn (buf
);
29221 if ((newval
& 0x0f200f00) == 0x0d000900)
29223 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
29224 has permitted values that are multiples of 2, in the range 0
29226 if (value
< -510 || value
> 510 || (value
& 1))
29227 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29228 _("co-processor offset out of range"));
29230 else if ((newval
& 0xfe001f80) == 0xec000f80)
29232 if (value
< -511 || value
> 512 || (value
& 3))
29233 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29234 _("co-processor offset out of range"));
29236 else if (value
< -1023 || value
> 1023 || (value
& 3))
29237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29238 _("co-processor offset out of range"));
29243 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29244 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29245 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29247 newval
= get_thumb32_insn (buf
);
29250 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29251 newval
&= 0xffffff80;
29253 newval
&= 0xffffff00;
29257 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29258 newval
&= 0xff7fff80;
29260 newval
&= 0xff7fff00;
29261 if ((newval
& 0x0f200f00) == 0x0d000900)
29263 /* This is a fp16 vstr/vldr.
29265 It requires the immediate offset in the instruction is shifted
29266 left by 1 to be a half-word offset.
29268 Here, left shift by 1 first, and later right shift by 2
29269 should get the right offset. */
29272 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
29274 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29275 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29276 md_number_to_chars (buf
, newval
, INSN_SIZE
);
29278 put_thumb32_insn (buf
, newval
);
29281 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
29282 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
29283 if (value
< -255 || value
> 255)
29284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29285 _("co-processor offset out of range"));
29287 goto cp_off_common
;
29289 case BFD_RELOC_ARM_THUMB_OFFSET
:
29290 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29291 /* Exactly what ranges, and where the offset is inserted depends
29292 on the type of instruction, we can establish this from the
29294 switch (newval
>> 12)
29296 case 4: /* PC load. */
29297 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29298 forced to zero for these loads; md_pcrel_from has already
29299 compensated for this. */
29301 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29302 _("invalid offset, target not word aligned (0x%08lX)"),
29303 (((unsigned long) fixP
->fx_frag
->fr_address
29304 + (unsigned long) fixP
->fx_where
) & ~3)
29305 + (unsigned long) value
);
29306 else if (get_recorded_alignment (seg
) < 2)
29307 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29308 _("section does not have enough alignment to ensure safe PC-relative loads"));
29310 if (value
& ~0x3fc)
29311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29312 _("invalid offset, value too big (0x%08lX)"),
29315 newval
|= value
>> 2;
29318 case 9: /* SP load/store. */
29319 if (value
& ~0x3fc)
29320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29321 _("invalid offset, value too big (0x%08lX)"),
29323 newval
|= value
>> 2;
29326 case 6: /* Word load/store. */
29328 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29329 _("invalid offset, value too big (0x%08lX)"),
29331 newval
|= value
<< 4; /* 6 - 2. */
29334 case 7: /* Byte load/store. */
29336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29337 _("invalid offset, value too big (0x%08lX)"),
29339 newval
|= value
<< 6;
29342 case 8: /* Halfword load/store. */
29344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29345 _("invalid offset, value too big (0x%08lX)"),
29347 newval
|= value
<< 5; /* 6 - 1. */
29351 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29352 "Unable to process relocation for thumb opcode: %lx",
29353 (unsigned long) newval
);
29356 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29359 case BFD_RELOC_ARM_THUMB_ADD
:
29360 /* This is a complicated relocation, since we use it for all of
29361 the following immediate relocations:
29365 9bit ADD/SUB SP word-aligned
29366 10bit ADD PC/SP word-aligned
29368 The type of instruction being processed is encoded in the
29375 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29377 int rd
= (newval
>> 4) & 0xf;
29378 int rs
= newval
& 0xf;
29379 int subtract
= !!(newval
& 0x8000);
29381 /* Check for HI regs, only very restricted cases allowed:
29382 Adjusting SP, and using PC or SP to get an address. */
29383 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
29384 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
29385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29386 _("invalid Hi register with immediate"));
29388 /* If value is negative, choose the opposite instruction. */
29392 subtract
= !subtract
;
29394 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29395 _("immediate value out of range"));
29400 if (value
& ~0x1fc)
29401 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29402 _("invalid immediate for stack address calculation"));
29403 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
29404 newval
|= value
>> 2;
29406 else if (rs
== REG_PC
|| rs
== REG_SP
)
29408 /* PR gas/18541. If the addition is for a defined symbol
29409 within range of an ADR instruction then accept it. */
29412 && fixP
->fx_addsy
!= NULL
)
29416 if (! S_IS_DEFINED (fixP
->fx_addsy
)
29417 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
29418 || S_IS_WEAK (fixP
->fx_addsy
))
29420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29421 _("address calculation needs a strongly defined nearby symbol"));
29425 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
29427 /* Round up to the next 4-byte boundary. */
29432 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
29436 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29437 _("symbol too far away"));
29447 if (subtract
|| value
& ~0x3fc)
29448 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29449 _("invalid immediate for address calculation (value = 0x%08lX)"),
29450 (unsigned long) (subtract
? - value
: value
));
29451 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
29453 newval
|= value
>> 2;
29458 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29459 _("immediate value out of range"));
29460 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
29461 newval
|= (rd
<< 8) | value
;
29466 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29467 _("immediate value out of range"));
29468 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
29469 newval
|= rd
| (rs
<< 3) | (value
<< 6);
29472 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29475 case BFD_RELOC_ARM_THUMB_IMM
:
29476 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29477 if (value
< 0 || value
> 255)
29478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29479 _("invalid immediate: %ld is out of range"),
29482 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29485 case BFD_RELOC_ARM_THUMB_SHIFT
:
29486 /* 5bit shift value (0..32). LSL cannot take 32. */
29487 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
29488 temp
= newval
& 0xf800;
29489 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
29490 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29491 _("invalid shift value: %ld"), (long) value
);
29492 /* Shifts of zero must be encoded as LSL. */
29494 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
29495 /* Shifts of 32 are encoded as zero. */
29496 else if (value
== 32)
29498 newval
|= value
<< 6;
29499 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29502 case BFD_RELOC_VTABLE_INHERIT
:
29503 case BFD_RELOC_VTABLE_ENTRY
:
29507 case BFD_RELOC_ARM_MOVW
:
29508 case BFD_RELOC_ARM_MOVT
:
29509 case BFD_RELOC_ARM_THUMB_MOVW
:
29510 case BFD_RELOC_ARM_THUMB_MOVT
:
29511 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29513 /* REL format relocations are limited to a 16-bit addend. */
29514 if (!fixP
->fx_done
)
29516 if (value
< -0x8000 || value
> 0x7fff)
29517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29518 _("offset out of range"));
29520 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29521 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29526 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29527 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29529 newval
= get_thumb32_insn (buf
);
29530 newval
&= 0xfbf08f00;
29531 newval
|= (value
& 0xf000) << 4;
29532 newval
|= (value
& 0x0800) << 15;
29533 newval
|= (value
& 0x0700) << 4;
29534 newval
|= (value
& 0x00ff);
29535 put_thumb32_insn (buf
, newval
);
29539 newval
= md_chars_to_number (buf
, 4);
29540 newval
&= 0xfff0f000;
29541 newval
|= value
& 0x0fff;
29542 newval
|= (value
& 0xf000) << 4;
29543 md_number_to_chars (buf
, newval
, 4);
29548 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29549 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29550 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29551 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29552 gas_assert (!fixP
->fx_done
);
29555 bfd_boolean is_mov
;
29556 bfd_vma encoded_addend
= value
;
29558 /* Check that addend can be encoded in instruction. */
29559 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
29560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29561 _("the offset 0x%08lX is not representable"),
29562 (unsigned long) encoded_addend
);
29564 /* Extract the instruction. */
29565 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
29566 is_mov
= (insn
& 0xf800) == 0x2000;
29571 if (!seg
->use_rela_p
)
29572 insn
|= encoded_addend
;
29578 /* Extract the instruction. */
29579 /* Encoding is the following
29584 /* The following conditions must be true :
29589 rd
= (insn
>> 4) & 0xf;
29591 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
29592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29593 _("Unable to process relocation for thumb opcode: %lx"),
29594 (unsigned long) insn
);
29596 /* Encode as ADD immediate8 thumb 1 code. */
29597 insn
= 0x3000 | (rd
<< 8);
29599 /* Place the encoded addend into the first 8 bits of the
29601 if (!seg
->use_rela_p
)
29602 insn
|= encoded_addend
;
29605 /* Update the instruction. */
29606 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
29610 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29611 case BFD_RELOC_ARM_ALU_PC_G0
:
29612 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29613 case BFD_RELOC_ARM_ALU_PC_G1
:
29614 case BFD_RELOC_ARM_ALU_PC_G2
:
29615 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29616 case BFD_RELOC_ARM_ALU_SB_G0
:
29617 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29618 case BFD_RELOC_ARM_ALU_SB_G1
:
29619 case BFD_RELOC_ARM_ALU_SB_G2
:
29620 gas_assert (!fixP
->fx_done
);
29621 if (!seg
->use_rela_p
)
29624 bfd_vma encoded_addend
;
29625 bfd_vma addend_abs
= llabs (value
);
29627 /* Check that the absolute value of the addend can be
29628 expressed as an 8-bit constant plus a rotation. */
29629 encoded_addend
= encode_arm_immediate (addend_abs
);
29630 if (encoded_addend
== (unsigned int) FAIL
)
29631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29632 _("the offset 0x%08lX is not representable"),
29633 (unsigned long) addend_abs
);
29635 /* Extract the instruction. */
29636 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29638 /* If the addend is positive, use an ADD instruction.
29639 Otherwise use a SUB. Take care not to destroy the S bit. */
29640 insn
&= 0xff1fffff;
29646 /* Place the encoded addend into the first 12 bits of the
29648 insn
&= 0xfffff000;
29649 insn
|= encoded_addend
;
29651 /* Update the instruction. */
29652 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29656 case BFD_RELOC_ARM_LDR_PC_G0
:
29657 case BFD_RELOC_ARM_LDR_PC_G1
:
29658 case BFD_RELOC_ARM_LDR_PC_G2
:
29659 case BFD_RELOC_ARM_LDR_SB_G0
:
29660 case BFD_RELOC_ARM_LDR_SB_G1
:
29661 case BFD_RELOC_ARM_LDR_SB_G2
:
29662 gas_assert (!fixP
->fx_done
);
29663 if (!seg
->use_rela_p
)
29666 bfd_vma addend_abs
= llabs (value
);
29668 /* Check that the absolute value of the addend can be
29669 encoded in 12 bits. */
29670 if (addend_abs
>= 0x1000)
29671 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29672 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29673 (unsigned long) addend_abs
);
29675 /* Extract the instruction. */
29676 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29678 /* If the addend is negative, clear bit 23 of the instruction.
29679 Otherwise set it. */
29681 insn
&= ~(1 << 23);
29685 /* Place the absolute value of the addend into the first 12 bits
29686 of the instruction. */
29687 insn
&= 0xfffff000;
29688 insn
|= addend_abs
;
29690 /* Update the instruction. */
29691 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29695 case BFD_RELOC_ARM_LDRS_PC_G0
:
29696 case BFD_RELOC_ARM_LDRS_PC_G1
:
29697 case BFD_RELOC_ARM_LDRS_PC_G2
:
29698 case BFD_RELOC_ARM_LDRS_SB_G0
:
29699 case BFD_RELOC_ARM_LDRS_SB_G1
:
29700 case BFD_RELOC_ARM_LDRS_SB_G2
:
29701 gas_assert (!fixP
->fx_done
);
29702 if (!seg
->use_rela_p
)
29705 bfd_vma addend_abs
= llabs (value
);
29707 /* Check that the absolute value of the addend can be
29708 encoded in 8 bits. */
29709 if (addend_abs
>= 0x100)
29710 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29711 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29712 (unsigned long) addend_abs
);
29714 /* Extract the instruction. */
29715 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29717 /* If the addend is negative, clear bit 23 of the instruction.
29718 Otherwise set it. */
29720 insn
&= ~(1 << 23);
29724 /* Place the first four bits of the absolute value of the addend
29725 into the first 4 bits of the instruction, and the remaining
29726 four into bits 8 .. 11. */
29727 insn
&= 0xfffff0f0;
29728 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29730 /* Update the instruction. */
29731 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29735 case BFD_RELOC_ARM_LDC_PC_G0
:
29736 case BFD_RELOC_ARM_LDC_PC_G1
:
29737 case BFD_RELOC_ARM_LDC_PC_G2
:
29738 case BFD_RELOC_ARM_LDC_SB_G0
:
29739 case BFD_RELOC_ARM_LDC_SB_G1
:
29740 case BFD_RELOC_ARM_LDC_SB_G2
:
29741 gas_assert (!fixP
->fx_done
);
29742 if (!seg
->use_rela_p
)
29745 bfd_vma addend_abs
= llabs (value
);
29747 /* Check that the absolute value of the addend is a multiple of
29748 four and, when divided by four, fits in 8 bits. */
29749 if (addend_abs
& 0x3)
29750 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29751 _("bad offset 0x%08lX (must be word-aligned)"),
29752 (unsigned long) addend_abs
);
29754 if ((addend_abs
>> 2) > 0xff)
29755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29756 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29757 (unsigned long) addend_abs
);
29759 /* Extract the instruction. */
29760 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29762 /* If the addend is negative, clear bit 23 of the instruction.
29763 Otherwise set it. */
29765 insn
&= ~(1 << 23);
29769 /* Place the addend (divided by four) into the first eight
29770 bits of the instruction. */
29771 insn
&= 0xfffffff0;
29772 insn
|= addend_abs
>> 2;
29774 /* Update the instruction. */
29775 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29779 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29781 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29782 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29783 && ARM_IS_FUNC (fixP
->fx_addsy
)
29784 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29786 /* Force a relocation for a branch 5 bits wide. */
29789 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
29790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29793 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29795 addressT boff
= value
>> 1;
29797 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29798 newval
|= (boff
<< 7);
29799 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29803 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29805 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29806 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29807 && ARM_IS_FUNC (fixP
->fx_addsy
)
29808 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29812 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
29813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29814 _("branch out of range"));
29816 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29818 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29820 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29821 addressT diff
= value
- boff
;
29825 newval
|= 1 << 1; /* T bit. */
29827 else if (diff
!= 2)
29829 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29830 _("out of range label-relative fixup value"));
29832 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29836 case BFD_RELOC_ARM_THUMB_BF17
:
29838 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29839 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29840 && ARM_IS_FUNC (fixP
->fx_addsy
)
29841 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29843 /* Force a relocation for a branch 17 bits wide. */
29847 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
29848 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29851 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29854 addressT immA
, immB
, immC
;
29856 immA
= (value
& 0x0001f000) >> 12;
29857 immB
= (value
& 0x00000ffc) >> 2;
29858 immC
= (value
& 0x00000002) >> 1;
29860 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29861 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29863 newval2
|= (immC
<< 11) | (immB
<< 1);
29864 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29865 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29869 case BFD_RELOC_ARM_THUMB_BF19
:
29871 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29872 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29873 && ARM_IS_FUNC (fixP
->fx_addsy
)
29874 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29876 /* Force a relocation for a branch 19 bits wide. */
29880 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29884 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29887 addressT immA
, immB
, immC
;
29889 immA
= (value
& 0x0007f000) >> 12;
29890 immB
= (value
& 0x00000ffc) >> 2;
29891 immC
= (value
& 0x00000002) >> 1;
29893 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29894 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29896 newval2
|= (immC
<< 11) | (immB
<< 1);
29897 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29898 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29902 case BFD_RELOC_ARM_THUMB_BF13
:
29904 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29905 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29906 && ARM_IS_FUNC (fixP
->fx_addsy
)
29907 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29909 /* Force a relocation for a branch 13 bits wide. */
29913 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29917 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29920 addressT immA
, immB
, immC
;
29922 immA
= (value
& 0x00001000) >> 12;
29923 immB
= (value
& 0x00000ffc) >> 2;
29924 immC
= (value
& 0x00000002) >> 1;
29926 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29927 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29929 newval2
|= (immC
<< 11) | (immB
<< 1);
29930 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29931 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29935 case BFD_RELOC_ARM_THUMB_LOOP12
:
29937 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29938 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29939 && ARM_IS_FUNC (fixP
->fx_addsy
)
29940 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29942 /* Force a relocation for a branch 12 bits wide. */
29946 bfd_vma insn
= get_thumb32_insn (buf
);
29947 /* le lr, <label>, le <label> or letp lr, <label> */
29948 if (((insn
& 0xffffffff) == 0xf00fc001)
29949 || ((insn
& 0xffffffff) == 0xf02fc001)
29950 || ((insn
& 0xffffffff) == 0xf01fc001))
29953 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29954 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29956 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29958 addressT imml
, immh
;
29960 immh
= (value
& 0x00000ffc) >> 2;
29961 imml
= (value
& 0x00000002) >> 1;
29963 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29964 newval
|= (imml
<< 11) | (immh
<< 1);
29965 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29969 case BFD_RELOC_ARM_V4BX
:
29970 /* This will need to go in the object file. */
29974 case BFD_RELOC_UNUSED
:
29976 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29977 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29981 /* Translate internal representation of relocation info to BFD target
29985 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29988 bfd_reloc_code_real_type code
;
29990 reloc
= XNEW (arelent
);
29992 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29993 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29994 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29996 if (fixp
->fx_pcrel
)
29998 if (section
->use_rela_p
)
29999 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
30001 fixp
->fx_offset
= reloc
->address
;
30003 reloc
->addend
= fixp
->fx_offset
;
30005 switch (fixp
->fx_r_type
)
30008 if (fixp
->fx_pcrel
)
30010 code
= BFD_RELOC_8_PCREL
;
30013 /* Fall through. */
30016 if (fixp
->fx_pcrel
)
30018 code
= BFD_RELOC_16_PCREL
;
30021 /* Fall through. */
30024 if (fixp
->fx_pcrel
)
30026 code
= BFD_RELOC_32_PCREL
;
30029 /* Fall through. */
30031 case BFD_RELOC_ARM_MOVW
:
30032 if (fixp
->fx_pcrel
)
30034 code
= BFD_RELOC_ARM_MOVW_PCREL
;
30037 /* Fall through. */
30039 case BFD_RELOC_ARM_MOVT
:
30040 if (fixp
->fx_pcrel
)
30042 code
= BFD_RELOC_ARM_MOVT_PCREL
;
30045 /* Fall through. */
30047 case BFD_RELOC_ARM_THUMB_MOVW
:
30048 if (fixp
->fx_pcrel
)
30050 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
30053 /* Fall through. */
30055 case BFD_RELOC_ARM_THUMB_MOVT
:
30056 if (fixp
->fx_pcrel
)
30058 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
30061 /* Fall through. */
30063 case BFD_RELOC_NONE
:
30064 case BFD_RELOC_ARM_PCREL_BRANCH
:
30065 case BFD_RELOC_ARM_PCREL_BLX
:
30066 case BFD_RELOC_RVA
:
30067 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
30068 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
30069 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
30070 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30071 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30072 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30073 case BFD_RELOC_VTABLE_ENTRY
:
30074 case BFD_RELOC_VTABLE_INHERIT
:
30076 case BFD_RELOC_32_SECREL
:
30078 code
= fixp
->fx_r_type
;
30081 case BFD_RELOC_THUMB_PCREL_BLX
:
30083 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
30084 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
30087 code
= BFD_RELOC_THUMB_PCREL_BLX
;
30090 case BFD_RELOC_ARM_LITERAL
:
30091 case BFD_RELOC_ARM_HWLITERAL
:
30092 /* If this is called then the a literal has
30093 been referenced across a section boundary. */
30094 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30095 _("literal referenced across section boundary"));
30099 case BFD_RELOC_ARM_TLS_CALL
:
30100 case BFD_RELOC_ARM_THM_TLS_CALL
:
30101 case BFD_RELOC_ARM_TLS_DESCSEQ
:
30102 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
30103 case BFD_RELOC_ARM_GOT32
:
30104 case BFD_RELOC_ARM_GOTOFF
:
30105 case BFD_RELOC_ARM_GOT_PREL
:
30106 case BFD_RELOC_ARM_PLT32
:
30107 case BFD_RELOC_ARM_TARGET1
:
30108 case BFD_RELOC_ARM_ROSEGREL32
:
30109 case BFD_RELOC_ARM_SBREL32
:
30110 case BFD_RELOC_ARM_PREL31
:
30111 case BFD_RELOC_ARM_TARGET2
:
30112 case BFD_RELOC_ARM_TLS_LDO32
:
30113 case BFD_RELOC_ARM_PCREL_CALL
:
30114 case BFD_RELOC_ARM_PCREL_JUMP
:
30115 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
30116 case BFD_RELOC_ARM_ALU_PC_G0
:
30117 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
30118 case BFD_RELOC_ARM_ALU_PC_G1
:
30119 case BFD_RELOC_ARM_ALU_PC_G2
:
30120 case BFD_RELOC_ARM_LDR_PC_G0
:
30121 case BFD_RELOC_ARM_LDR_PC_G1
:
30122 case BFD_RELOC_ARM_LDR_PC_G2
:
30123 case BFD_RELOC_ARM_LDRS_PC_G0
:
30124 case BFD_RELOC_ARM_LDRS_PC_G1
:
30125 case BFD_RELOC_ARM_LDRS_PC_G2
:
30126 case BFD_RELOC_ARM_LDC_PC_G0
:
30127 case BFD_RELOC_ARM_LDC_PC_G1
:
30128 case BFD_RELOC_ARM_LDC_PC_G2
:
30129 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
30130 case BFD_RELOC_ARM_ALU_SB_G0
:
30131 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
30132 case BFD_RELOC_ARM_ALU_SB_G1
:
30133 case BFD_RELOC_ARM_ALU_SB_G2
:
30134 case BFD_RELOC_ARM_LDR_SB_G0
:
30135 case BFD_RELOC_ARM_LDR_SB_G1
:
30136 case BFD_RELOC_ARM_LDR_SB_G2
:
30137 case BFD_RELOC_ARM_LDRS_SB_G0
:
30138 case BFD_RELOC_ARM_LDRS_SB_G1
:
30139 case BFD_RELOC_ARM_LDRS_SB_G2
:
30140 case BFD_RELOC_ARM_LDC_SB_G0
:
30141 case BFD_RELOC_ARM_LDC_SB_G1
:
30142 case BFD_RELOC_ARM_LDC_SB_G2
:
30143 case BFD_RELOC_ARM_V4BX
:
30144 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
30145 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
30146 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
30147 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
30148 case BFD_RELOC_ARM_GOTFUNCDESC
:
30149 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
30150 case BFD_RELOC_ARM_FUNCDESC
:
30151 case BFD_RELOC_ARM_THUMB_BF17
:
30152 case BFD_RELOC_ARM_THUMB_BF19
:
30153 case BFD_RELOC_ARM_THUMB_BF13
:
30154 code
= fixp
->fx_r_type
;
30157 case BFD_RELOC_ARM_TLS_GOTDESC
:
30158 case BFD_RELOC_ARM_TLS_GD32
:
30159 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
30160 case BFD_RELOC_ARM_TLS_LE32
:
30161 case BFD_RELOC_ARM_TLS_IE32
:
30162 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
30163 case BFD_RELOC_ARM_TLS_LDM32
:
30164 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
30165 /* BFD will include the symbol's address in the addend.
30166 But we don't want that, so subtract it out again here. */
30167 if (!S_IS_COMMON (fixp
->fx_addsy
))
30168 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
30169 code
= fixp
->fx_r_type
;
30173 case BFD_RELOC_ARM_IMMEDIATE
:
30174 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30175 _("internal relocation (type: IMMEDIATE) not fixed up"));
30178 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
30179 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30180 _("ADRL used for a symbol not defined in the same file"));
30183 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
30184 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
30185 case BFD_RELOC_ARM_THUMB_LOOP12
:
30186 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30187 _("%s used for a symbol not defined in the same file"),
30188 bfd_get_reloc_code_name (fixp
->fx_r_type
));
30191 case BFD_RELOC_ARM_OFFSET_IMM
:
30192 if (section
->use_rela_p
)
30194 code
= fixp
->fx_r_type
;
30198 if (fixp
->fx_addsy
!= NULL
30199 && !S_IS_DEFINED (fixp
->fx_addsy
)
30200 && S_IS_LOCAL (fixp
->fx_addsy
))
30202 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30203 _("undefined local label `%s'"),
30204 S_GET_NAME (fixp
->fx_addsy
));
30208 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30209 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30216 switch (fixp
->fx_r_type
)
30218 case BFD_RELOC_NONE
: type
= "NONE"; break;
30219 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
30220 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
30221 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
30222 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
30223 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
30224 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
30225 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
30226 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
30227 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
30228 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
30229 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
30230 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
30231 default: type
= _("<unknown>"); break;
30233 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30234 _("cannot represent %s relocation in this object file format"),
30241 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
30243 && fixp
->fx_addsy
== GOT_symbol
)
30245 code
= BFD_RELOC_ARM_GOTPC
;
30246 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
30250 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
30252 if (reloc
->howto
== NULL
)
30254 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30255 _("cannot represent %s relocation in this object file format"),
30256 bfd_get_reloc_code_name (code
));
30260 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30261 vtable entry to be used in the relocation's section offset. */
30262 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30263 reloc
->address
= fixp
->fx_offset
;
30268 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
30271 cons_fix_new_arm (fragS
* frag
,
30275 bfd_reloc_code_real_type reloc
)
30280 FIXME: @@ Should look at CPU word size. */
30284 reloc
= BFD_RELOC_8
;
30287 reloc
= BFD_RELOC_16
;
30291 reloc
= BFD_RELOC_32
;
30294 reloc
= BFD_RELOC_64
;
30299 if (exp
->X_op
== O_secrel
)
30301 exp
->X_op
= O_symbol
;
30302 reloc
= BFD_RELOC_32_SECREL
;
30306 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
30309 #if defined (OBJ_COFF)
30311 arm_validate_fix (fixS
* fixP
)
30313 /* If the destination of the branch is a defined symbol which does not have
30314 the THUMB_FUNC attribute, then we must be calling a function which has
30315 the (interfacearm) attribute. We look for the Thumb entry point to that
30316 function and change the branch to refer to that function instead. */
30317 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
30318 && fixP
->fx_addsy
!= NULL
30319 && S_IS_DEFINED (fixP
->fx_addsy
)
30320 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
30322 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
30329 arm_force_relocation (struct fix
* fixp
)
30331 #if defined (OBJ_COFF) && defined (TE_PE)
30332 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
30336 /* In case we have a call or a branch to a function in ARM ISA mode from
30337 a thumb function or vice-versa force the relocation. These relocations
30338 are cleared off for some cores that might have blx and simple transformations
30342 switch (fixp
->fx_r_type
)
30344 case BFD_RELOC_ARM_PCREL_JUMP
:
30345 case BFD_RELOC_ARM_PCREL_CALL
:
30346 case BFD_RELOC_THUMB_PCREL_BLX
:
30347 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
30351 case BFD_RELOC_ARM_PCREL_BLX
:
30352 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30353 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30354 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30355 if (ARM_IS_FUNC (fixp
->fx_addsy
))
30364 /* Resolve these relocations even if the symbol is extern or weak.
30365 Technically this is probably wrong due to symbol preemption.
30366 In practice these relocations do not have enough range to be useful
30367 at dynamic link time, and some code (e.g. in the Linux kernel)
30368 expects these references to be resolved. */
30369 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
30370 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
30371 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
30372 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
30373 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
30374 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
30375 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
30376 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH12
30377 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
30378 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
30379 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
30380 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
30381 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
30382 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
30383 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
30386 /* Always leave these relocations for the linker. */
30387 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30388 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30389 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30392 /* Always generate relocations against function symbols. */
30393 if (fixp
->fx_r_type
== BFD_RELOC_32
30395 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
30398 return generic_force_reloc (fixp
);
30401 #if defined (OBJ_ELF) || defined (OBJ_COFF)
30402 /* Relocations against function names must be left unadjusted,
30403 so that the linker can use this information to generate interworking
30404 stubs. The MIPS version of this function
30405 also prevents relocations that are mips-16 specific, but I do not
30406 know why it does this.
30409 There is one other problem that ought to be addressed here, but
30410 which currently is not: Taking the address of a label (rather
30411 than a function) and then later jumping to that address. Such
30412 addresses also ought to have their bottom bit set (assuming that
30413 they reside in Thumb code), but at the moment they will not. */
30416 arm_fix_adjustable (fixS
* fixP
)
30418 if (fixP
->fx_addsy
== NULL
)
30421 /* Preserve relocations against symbols with function type. */
30422 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
30425 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
30426 && fixP
->fx_subsy
== NULL
)
30429 /* We need the symbol name for the VTABLE entries. */
30430 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
30431 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30434 /* Don't allow symbols to be discarded on GOT related relocs. */
30435 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
30436 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
30437 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
30438 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
30439 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
30440 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
30441 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
30442 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
30443 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
30444 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
30445 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
30446 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
30447 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
30448 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
30449 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
30450 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
30451 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
30454 /* Similarly for group relocations. */
30455 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30456 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30457 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30460 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
30461 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
30462 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
30463 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
30464 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
30465 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
30466 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
30467 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
30468 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
30471 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30472 offsets, so keep these symbols. */
30473 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30474 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
30479 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30483 elf32_arm_target_format (void)
30486 return (target_big_endian
30487 ? "elf32-bigarm-symbian"
30488 : "elf32-littlearm-symbian");
30489 #elif defined (TE_VXWORKS)
30490 return (target_big_endian
30491 ? "elf32-bigarm-vxworks"
30492 : "elf32-littlearm-vxworks");
30493 #elif defined (TE_NACL)
30494 return (target_big_endian
30495 ? "elf32-bigarm-nacl"
30496 : "elf32-littlearm-nacl");
30500 if (target_big_endian
)
30501 return "elf32-bigarm-fdpic";
30503 return "elf32-littlearm-fdpic";
30507 if (target_big_endian
)
30508 return "elf32-bigarm";
30510 return "elf32-littlearm";
30516 armelf_frob_symbol (symbolS
* symp
,
30519 elf_frob_symbol (symp
, puntp
);
30523 /* MD interface: Finalization. */
30528 literal_pool
* pool
;
30530 /* Ensure that all the predication blocks are properly closed. */
30531 check_pred_blocks_finished ();
30533 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
30535 /* Put it at the end of the relevant section. */
30536 subseg_set (pool
->section
, pool
->sub_section
);
30538 arm_elf_change_section ();
30545 /* Remove any excess mapping symbols generated for alignment frags in
30546 SEC. We may have created a mapping symbol before a zero byte
30547 alignment; remove it if there's a mapping symbol after the
30550 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
30551 void *dummy ATTRIBUTE_UNUSED
)
30553 segment_info_type
*seginfo
= seg_info (sec
);
30556 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
30559 for (fragp
= seginfo
->frchainP
->frch_root
;
30561 fragp
= fragp
->fr_next
)
30563 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
30564 fragS
*next
= fragp
->fr_next
;
30566 /* Variable-sized frags have been converted to fixed size by
30567 this point. But if this was variable-sized to start with,
30568 there will be a fixed-size frag after it. So don't handle
30570 if (sym
== NULL
|| next
== NULL
)
30573 if (S_GET_VALUE (sym
) < next
->fr_address
)
30574 /* Not at the end of this frag. */
30576 know (S_GET_VALUE (sym
) == next
->fr_address
);
30580 if (next
->tc_frag_data
.first_map
!= NULL
)
30582 /* Next frag starts with a mapping symbol. Discard this
30584 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30588 if (next
->fr_next
== NULL
)
30590 /* This mapping symbol is at the end of the section. Discard
30592 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
30593 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30597 /* As long as we have empty frags without any mapping symbols,
30599 /* If the next frag is non-empty and does not start with a
30600 mapping symbol, then this mapping symbol is required. */
30601 if (next
->fr_address
!= next
->fr_next
->fr_address
)
30604 next
= next
->fr_next
;
30606 while (next
!= NULL
);
30611 /* Adjust the symbol table. This marks Thumb symbols as distinct from
30615 arm_adjust_symtab (void)
30620 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30622 if (ARM_IS_THUMB (sym
))
30624 if (THUMB_IS_FUNC (sym
))
30626 /* Mark the symbol as a Thumb function. */
30627 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
30628 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
30629 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
30631 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
30632 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
30634 as_bad (_("%s: unexpected function type: %d"),
30635 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
30637 else switch (S_GET_STORAGE_CLASS (sym
))
30640 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
30643 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
30646 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
30654 if (ARM_IS_INTERWORK (sym
))
30655 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
30662 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30664 if (ARM_IS_THUMB (sym
))
30666 elf_symbol_type
* elf_sym
;
30668 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
30669 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
30671 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
30672 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
30674 /* If it's a .thumb_func, declare it as so,
30675 otherwise tag label as .code 16. */
30676 if (THUMB_IS_FUNC (sym
))
30677 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
30678 ST_BRANCH_TO_THUMB
);
30679 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30680 elf_sym
->internal_elf_sym
.st_info
=
30681 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
30686 /* Remove any overlapping mapping symbols generated by alignment frags. */
30687 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
30688 /* Now do generic ELF adjustments. */
30689 elf_adjust_symtab ();
30693 /* MD interface: Initialization. */
30696 set_constant_flonums (void)
30700 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30701 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30705 /* Auto-select Thumb mode if it's the only available instruction set for the
30706 given architecture. */
30709 autoselect_thumb_from_cpu_variant (void)
30711 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30712 opcode_select (16);
30721 if ( (arm_ops_hsh
= str_htab_create ()) == NULL
30722 || (arm_cond_hsh
= str_htab_create ()) == NULL
30723 || (arm_vcond_hsh
= str_htab_create ()) == NULL
30724 || (arm_shift_hsh
= str_htab_create ()) == NULL
30725 || (arm_psr_hsh
= str_htab_create ()) == NULL
30726 || (arm_v7m_psr_hsh
= str_htab_create ()) == NULL
30727 || (arm_reg_hsh
= str_htab_create ()) == NULL
30728 || (arm_reloc_hsh
= str_htab_create ()) == NULL
30729 || (arm_barrier_opt_hsh
= str_htab_create ()) == NULL
)
30730 as_fatal (_("virtual memory exhausted"));
30732 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30733 if (str_hash_find (arm_ops_hsh
, insns
[i
].template_name
) == NULL
)
30734 str_hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
30735 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30736 str_hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
30737 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30738 str_hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
30739 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30740 str_hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
30741 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30742 str_hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
30743 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30744 str_hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30745 (void *) (v7m_psrs
+ i
));
30746 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30747 str_hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
30749 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30751 str_hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30752 (void *) (barrier_opt_names
+ i
));
30754 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30756 struct reloc_entry
* entry
= reloc_names
+ i
;
30758 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30759 /* This makes encode_branch() use the EABI versions of this relocation. */
30760 entry
->reloc
= BFD_RELOC_UNUSED
;
30762 str_hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
30766 set_constant_flonums ();
30768 /* Set the cpu variant based on the command-line options. We prefer
30769 -mcpu= over -march= if both are set (as for GCC); and we prefer
30770 -mfpu= over any other way of setting the floating point unit.
30771 Use of legacy options with new options are faulted. */
30774 if (mcpu_cpu_opt
|| march_cpu_opt
)
30775 as_bad (_("use of old and new-style options to set CPU type"));
30777 selected_arch
= *legacy_cpu
;
30779 else if (mcpu_cpu_opt
)
30781 selected_arch
= *mcpu_cpu_opt
;
30782 selected_ext
= *mcpu_ext_opt
;
30784 else if (march_cpu_opt
)
30786 selected_arch
= *march_cpu_opt
;
30787 selected_ext
= *march_ext_opt
;
30789 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30794 as_bad (_("use of old and new-style options to set FPU type"));
30796 selected_fpu
= *legacy_fpu
;
30799 selected_fpu
= *mfpu_opt
;
30802 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30803 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30804 /* Some environments specify a default FPU. If they don't, infer it
30805 from the processor. */
30807 selected_fpu
= *mcpu_fpu_opt
;
30808 else if (march_fpu_opt
)
30809 selected_fpu
= *march_fpu_opt
;
30811 selected_fpu
= fpu_default
;
30815 if (ARM_FEATURE_ZERO (selected_fpu
))
30817 if (!no_cpu_selected ())
30818 selected_fpu
= fpu_default
;
30820 selected_fpu
= fpu_arch_fpa
;
30824 if (ARM_FEATURE_ZERO (selected_arch
))
30826 selected_arch
= cpu_default
;
30827 selected_cpu
= selected_arch
;
30829 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30831 /* Autodection of feature mode: allow all features in cpu_variant but leave
30832 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30833 after all instruction have been processed and we can decide what CPU
30834 should be selected. */
30835 if (ARM_FEATURE_ZERO (selected_arch
))
30836 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30838 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30841 autoselect_thumb_from_cpu_variant ();
30843 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30845 #if defined OBJ_COFF || defined OBJ_ELF
30847 unsigned int flags
= 0;
30849 #if defined OBJ_ELF
30850 flags
= meabi_flags
;
30852 switch (meabi_flags
)
30854 case EF_ARM_EABI_UNKNOWN
:
30856 /* Set the flags in the private structure. */
30857 if (uses_apcs_26
) flags
|= F_APCS26
;
30858 if (support_interwork
) flags
|= F_INTERWORK
;
30859 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30860 if (pic_code
) flags
|= F_PIC
;
30861 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30862 flags
|= F_SOFT_FLOAT
;
30864 switch (mfloat_abi_opt
)
30866 case ARM_FLOAT_ABI_SOFT
:
30867 case ARM_FLOAT_ABI_SOFTFP
:
30868 flags
|= F_SOFT_FLOAT
;
30871 case ARM_FLOAT_ABI_HARD
:
30872 if (flags
& F_SOFT_FLOAT
)
30873 as_bad (_("hard-float conflicts with specified fpu"));
30877 /* Using pure-endian doubles (even if soft-float). */
30878 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30879 flags
|= F_VFP_FLOAT
;
30881 #if defined OBJ_ELF
30882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30883 flags
|= EF_ARM_MAVERICK_FLOAT
;
30886 case EF_ARM_EABI_VER4
:
30887 case EF_ARM_EABI_VER5
:
30888 /* No additional flags to set. */
30895 bfd_set_private_flags (stdoutput
, flags
);
30897 /* We have run out flags in the COFF header to encode the
30898 status of ATPCS support, so instead we create a dummy,
30899 empty, debug section called .arm.atpcs. */
30904 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30908 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30909 bfd_set_section_size (sec
, 0);
30910 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30916 /* Record the CPU type as well. */
30917 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30918 mach
= bfd_mach_arm_iWMMXt2
;
30919 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30920 mach
= bfd_mach_arm_iWMMXt
;
30921 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30922 mach
= bfd_mach_arm_XScale
;
30923 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30924 mach
= bfd_mach_arm_ep9312
;
30925 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30926 mach
= bfd_mach_arm_5TE
;
30927 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30929 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30930 mach
= bfd_mach_arm_5T
;
30932 mach
= bfd_mach_arm_5
;
30934 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30936 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30937 mach
= bfd_mach_arm_4T
;
30939 mach
= bfd_mach_arm_4
;
30941 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30942 mach
= bfd_mach_arm_3M
;
30943 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30944 mach
= bfd_mach_arm_3
;
30945 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30946 mach
= bfd_mach_arm_2a
;
30947 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30948 mach
= bfd_mach_arm_2
;
30950 mach
= bfd_mach_arm_unknown
;
30952 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30955 /* Command line processing. */
30958 Invocation line includes a switch not recognized by the base assembler.
30959 See if it's a processor-specific option.
30961 This routine is somewhat complicated by the need for backwards
30962 compatibility (since older releases of gcc can't be changed).
30963 The new options try to make the interface as compatible as
30966 New options (supported) are:
30968 -mcpu=<cpu name> Assemble for selected processor
30969 -march=<architecture name> Assemble for selected architecture
30970 -mfpu=<fpu architecture> Assemble for selected FPU.
30971 -EB/-mbig-endian Big-endian
30972 -EL/-mlittle-endian Little-endian
30973 -k Generate PIC code
30974 -mthumb Start in Thumb mode
30975 -mthumb-interwork Code supports ARM/Thumb interworking
30977 -m[no-]warn-deprecated Warn about deprecated features
30978 -m[no-]warn-syms Warn when symbols match instructions
30980 For now we will also provide support for:
30982 -mapcs-32 32-bit Program counter
30983 -mapcs-26 26-bit Program counter
30984 -macps-float Floats passed in FP registers
30985 -mapcs-reentrant Reentrant code
30987 (sometime these will probably be replaced with -mapcs=<list of options>
30988 and -matpcs=<list of options>)
30990 The remaining options are only supported for back-wards compatibility.
30991 Cpu variants, the arm part is optional:
30992 -m[arm]1 Currently not supported.
30993 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30994 -m[arm]3 Arm 3 processor
30995 -m[arm]6[xx], Arm 6 processors
30996 -m[arm]7[xx][t][[d]m] Arm 7 processors
30997 -m[arm]8[10] Arm 8 processors
30998 -m[arm]9[20][tdmi] Arm 9 processors
30999 -mstrongarm[110[0]] StrongARM processors
31000 -mxscale XScale processors
31001 -m[arm]v[2345[t[e]]] Arm architectures
31002 -mall All (except the ARM1)
31004 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
31005 -mfpe-old (No float load/store multiples)
31006 -mvfpxd VFP Single precision
31008 -mno-fpu Disable all floating point instructions
31010 The following CPU names are recognized:
31011 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
31012 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31013 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31014 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31015 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31016 arm10t arm10e, arm1020t, arm1020e, arm10200e,
31017 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
31021 const char * md_shortopts
= "m:k";
31023 #ifdef ARM_BI_ENDIAN
31024 #define OPTION_EB (OPTION_MD_BASE + 0)
31025 #define OPTION_EL (OPTION_MD_BASE + 1)
31027 #if TARGET_BYTES_BIG_ENDIAN
31028 #define OPTION_EB (OPTION_MD_BASE + 0)
31030 #define OPTION_EL (OPTION_MD_BASE + 1)
31033 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
31034 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
31036 struct option md_longopts
[] =
31039 {"EB", no_argument
, NULL
, OPTION_EB
},
31042 {"EL", no_argument
, NULL
, OPTION_EL
},
31044 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
31046 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
31048 {NULL
, no_argument
, NULL
, 0}
31051 size_t md_longopts_size
= sizeof (md_longopts
);
31053 struct arm_option_table
31055 const char * option
; /* Option name to match. */
31056 const char * help
; /* Help information. */
31057 int * var
; /* Variable to change. */
31058 int value
; /* What to change it to. */
31059 const char * deprecated
; /* If non-null, print this message. */
31062 struct arm_option_table arm_opts
[] =
31064 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
31065 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
31066 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31067 &support_interwork
, 1, NULL
},
31068 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
31069 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
31070 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
31072 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
31073 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
31074 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
31075 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
31078 /* These are recognized by the assembler, but have no affect on code. */
31079 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
31080 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
31082 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
31083 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31084 &warn_on_deprecated
, 0, NULL
},
31086 {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31087 " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it
, 1, NULL
},
31088 {"mno-warn-restrict-it", NULL
, &warn_on_restrict_it
, 0, NULL
},
31090 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
31091 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
31092 {NULL
, NULL
, NULL
, 0, NULL
}
31095 struct arm_legacy_option_table
31097 const char * option
; /* Option name to match. */
31098 const arm_feature_set
** var
; /* Variable to change. */
31099 const arm_feature_set value
; /* What to change it to. */
31100 const char * deprecated
; /* If non-null, print this message. */
31103 const struct arm_legacy_option_table arm_legacy_opts
[] =
31105 /* DON'T add any new processors to this list -- we want the whole list
31106 to go away... Add them to the processors table instead. */
31107 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31108 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31109 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31110 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31111 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31112 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31113 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31114 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31115 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31116 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31117 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31118 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31119 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31120 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31121 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31122 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31123 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31124 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31125 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31126 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31127 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31128 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31129 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31130 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31131 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31132 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31133 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31134 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31135 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31136 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31137 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31138 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31139 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31140 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31141 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31142 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31143 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31144 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31145 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31146 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31147 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31148 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31149 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31150 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31151 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31152 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31153 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31154 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31155 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31156 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31157 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31158 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31159 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31160 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31161 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31162 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31163 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31164 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31165 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31166 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31167 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31168 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31169 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31170 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31171 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31172 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31173 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31174 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31175 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
31176 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
31177 N_("use -mcpu=strongarm110")},
31178 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
31179 N_("use -mcpu=strongarm1100")},
31180 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
31181 N_("use -mcpu=strongarm1110")},
31182 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
31183 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
31184 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
31186 /* Architecture variants -- don't add any more to this list either. */
31187 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31188 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31189 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31190 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31191 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31192 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31193 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31194 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31195 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31196 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31197 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31198 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31199 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31200 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31201 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31202 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31203 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31204 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31206 /* Floating point variants -- don't add any more to this list either. */
31207 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
31208 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
31209 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
31210 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
31211 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
31213 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
31216 struct arm_cpu_option_table
31220 const arm_feature_set value
;
31221 const arm_feature_set ext
;
31222 /* For some CPUs we assume an FPU unless the user explicitly sets
31224 const arm_feature_set default_fpu
;
31225 /* The canonical name of the CPU, or NULL to use NAME converted to upper
31227 const char * canonical_name
;
31230 /* This list should, at a minimum, contain all the cpu names
31231 recognized by GCC. */
31232 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
31234 static const struct arm_cpu_option_table arm_cpus
[] =
31236 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
31239 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
31242 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
31245 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
31248 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
31251 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
31254 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
31257 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
31260 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
31263 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
31266 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
31269 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
31272 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
31275 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
31278 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
31281 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
31284 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
31287 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
31290 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
31293 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
31296 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
31299 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
31302 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
31305 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
31308 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
31311 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
31314 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
31317 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
31320 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
31323 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
31326 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
31329 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
31332 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
31335 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
31338 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
31341 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
31344 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
31347 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
31350 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
31353 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
31356 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
31359 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
31362 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
31365 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
31368 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
31371 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
31375 /* For V5 or later processors we default to using VFP; but the user
31376 should really set the FPU type explicitly. */
31377 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
31380 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
31383 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31386 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31389 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
31392 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
31395 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
31398 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
31401 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
31404 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
31407 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
31410 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
31413 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
31416 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
31419 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
31422 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
31425 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
31428 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
31431 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
31434 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
31437 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
31440 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
31443 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
31446 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
31449 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
31452 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
31455 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
31458 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
31461 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
31464 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
31467 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
31470 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
31473 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
31476 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
31479 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
31482 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
31485 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
31486 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31488 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
31490 FPU_ARCH_NEON_VFP_V4
),
31491 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
31492 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31493 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31494 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
31495 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31496 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31497 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
31499 FPU_ARCH_NEON_VFP_V4
),
31500 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
31502 FPU_ARCH_NEON_VFP_V4
),
31503 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
31505 FPU_ARCH_NEON_VFP_V4
),
31506 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
31507 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31508 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31509 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
31510 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31511 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31512 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
31513 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31514 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31515 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
31516 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31517 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31518 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
31519 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31520 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31521 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
31522 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31523 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31524 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
31525 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31526 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31527 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
31528 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31529 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31530 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
31531 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31532 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31533 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
31534 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31535 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31536 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
31537 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31538 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31539 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
31540 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31541 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31542 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
31545 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
31547 FPU_ARCH_VFP_V3D16
),
31548 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
31549 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31551 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
31552 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31553 FPU_ARCH_VFP_V3D16
),
31554 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
31555 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31556 FPU_ARCH_VFP_V3D16
),
31557 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
31558 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31559 FPU_ARCH_NEON_VFP_ARMV8
),
31560 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
31561 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31563 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
31564 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31566 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
31569 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
31572 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
31575 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
31578 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
31581 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
31584 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
31587 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
31588 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31589 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31590 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
31591 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31592 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31593 /* ??? XSCALE is really an architecture. */
31594 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
31598 /* ??? iwmmxt is not a processor. */
31599 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
31602 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
31605 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
31610 ARM_CPU_OPT ("ep9312", "ARM920T",
31611 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
31612 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
31614 /* Marvell processors. */
31615 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
31616 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31617 FPU_ARCH_VFP_V3D16
),
31618 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
31619 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31620 FPU_ARCH_NEON_VFP_V4
),
31622 /* APM X-Gene family. */
31623 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
31625 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31626 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
31627 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31628 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31630 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31634 struct arm_ext_table
31638 const arm_feature_set merge
;
31639 const arm_feature_set clear
;
31642 struct arm_arch_option_table
31646 const arm_feature_set value
;
31647 const arm_feature_set default_fpu
;
31648 const struct arm_ext_table
* ext_table
;
31651 /* Used to add support for +E and +noE extension. */
31652 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31653 /* Used to add support for a +E extension. */
31654 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31655 /* Used to add support for a +noE extension. */
31656 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31658 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31659 ~0 & ~FPU_ENDIAN_PURE)
31661 static const struct arm_ext_table armv5te_ext_table
[] =
31663 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
31664 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31667 static const struct arm_ext_table armv7_ext_table
[] =
31669 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31670 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31673 static const struct arm_ext_table armv7ve_ext_table
[] =
31675 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
31676 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
31677 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31678 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31679 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31680 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
31681 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31683 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
31684 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31686 /* Aliases for +simd. */
31687 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31689 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31690 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31691 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31693 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31696 static const struct arm_ext_table armv7a_ext_table
[] =
31698 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31699 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31700 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31701 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31702 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31703 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31704 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31706 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31707 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31709 /* Aliases for +simd. */
31710 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31711 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31713 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31714 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31716 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31717 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31718 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31721 static const struct arm_ext_table armv7r_ext_table
[] =
31723 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31724 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31725 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31726 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31727 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31728 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31729 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31730 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31731 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31734 static const struct arm_ext_table armv7em_ext_table
[] =
31736 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31737 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31738 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31739 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31740 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31741 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31742 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31745 static const struct arm_ext_table armv8a_ext_table
[] =
31747 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31748 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31749 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31750 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31752 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31753 should use the +simd option to turn on FP. */
31754 ARM_REMOVE ("fp", ALL_FP
),
31755 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31756 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31757 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31761 static const struct arm_ext_table armv81a_ext_table
[] =
31763 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31764 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31765 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31767 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31768 should use the +simd option to turn on FP. */
31769 ARM_REMOVE ("fp", ALL_FP
),
31770 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31771 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31772 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31775 static const struct arm_ext_table armv82a_ext_table
[] =
31777 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31778 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31779 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31780 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31781 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31782 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31783 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31784 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31786 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31787 should use the +simd option to turn on FP. */
31788 ARM_REMOVE ("fp", ALL_FP
),
31789 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31790 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31791 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31794 static const struct arm_ext_table armv84a_ext_table
[] =
31796 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31797 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31798 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31799 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31800 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31801 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31803 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31804 should use the +simd option to turn on FP. */
31805 ARM_REMOVE ("fp", ALL_FP
),
31806 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31807 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31808 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31811 static const struct arm_ext_table armv85a_ext_table
[] =
31813 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31814 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31815 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31816 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31817 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31818 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31820 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31821 should use the +simd option to turn on FP. */
31822 ARM_REMOVE ("fp", ALL_FP
),
31823 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31826 static const struct arm_ext_table armv86a_ext_table
[] =
31828 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31829 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31832 #define CDE_EXTENSIONS \
31833 ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
31834 ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
31835 ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
31836 ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
31837 ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
31838 ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
31839 ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
31840 ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
31842 static const struct arm_ext_table armv8m_main_ext_table
[] =
31844 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31845 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31846 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31847 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31849 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31853 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31855 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31856 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31858 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31859 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31862 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31863 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31864 ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
, ARM_EXT2_MVE
, 0),
31865 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
)),
31867 ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
,
31868 ARM_EXT2_FP16_INST
| ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
,
31869 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31871 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31874 #undef CDE_EXTENSIONS
31876 static const struct arm_ext_table armv8r_ext_table
[] =
31878 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31879 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31880 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31881 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31882 ARM_REMOVE ("fp", ALL_FP
),
31883 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31884 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31887 /* This list should, at a minimum, contain all the architecture names
31888 recognized by GCC. */
31889 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31890 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31891 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31893 static const struct arm_arch_option_table arm_archs
[] =
31895 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31896 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31897 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31898 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31899 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31900 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31901 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31902 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31903 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31904 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31905 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31906 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31907 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31908 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31909 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31910 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31911 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31912 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31913 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31914 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31915 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31916 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31917 kept to preserve existing behaviour. */
31918 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31919 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31920 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31921 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31922 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31923 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31924 kept to preserve existing behaviour. */
31925 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31926 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31927 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31928 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31929 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31930 /* The official spelling of the ARMv7 profile variants is the dashed form.
31931 Accept the non-dashed form for compatibility with old toolchains. */
31932 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31933 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31934 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31935 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31936 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31937 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31938 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31939 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31940 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31941 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31943 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31945 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31946 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31947 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31948 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31949 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31950 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31951 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31952 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
31953 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31954 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31955 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31956 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31958 #undef ARM_ARCH_OPT
31960 /* ISA extensions in the co-processor and main instruction set space. */
31962 struct arm_option_extension_value_table
31966 const arm_feature_set merge_value
;
31967 const arm_feature_set clear_value
;
31968 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31969 indicates that an extension is available for all architectures while
31970 ARM_ANY marks an empty entry. */
31971 const arm_feature_set allowed_archs
[2];
31974 /* The following table must be in alphabetical order with a NULL last entry. */
31976 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31977 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31979 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31980 use the context sensitive approach using arm_ext_table's. */
31981 static const struct arm_option_extension_value_table arm_extensions
[] =
31983 ARM_EXT_OPT ("crc", ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
31984 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
31985 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31986 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31987 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31988 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31989 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31990 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31992 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31993 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31994 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31995 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31996 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31997 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31998 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32000 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32001 | ARM_EXT2_FP16_FML
),
32002 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32003 | ARM_EXT2_FP16_FML
),
32005 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32006 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32007 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32008 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32009 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
32010 Thumb divide instruction. Due to this having the same name as the
32011 previous entry, this will be ignored when doing command-line parsing and
32012 only considered by build attribute selection code. */
32013 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32014 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32015 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
32016 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
32017 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
32018 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
32019 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
32020 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
32021 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
32022 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32023 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32024 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32025 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32026 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32027 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32028 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
32029 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
32030 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
32031 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32032 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32033 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32035 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
32036 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
32037 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32038 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
32039 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
32040 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32041 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32042 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32044 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32045 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32046 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
32047 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32048 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
32049 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
32050 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32051 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
32053 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
32054 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32055 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
32056 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
32057 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
32061 /* ISA floating-point and Advanced SIMD extensions. */
32062 struct arm_option_fpu_value_table
32065 const arm_feature_set value
;
32068 /* This list should, at a minimum, contain all the fpu names
32069 recognized by GCC. */
32070 static const struct arm_option_fpu_value_table arm_fpus
[] =
32072 {"softfpa", FPU_NONE
},
32073 {"fpe", FPU_ARCH_FPE
},
32074 {"fpe2", FPU_ARCH_FPE
},
32075 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
32076 {"fpa", FPU_ARCH_FPA
},
32077 {"fpa10", FPU_ARCH_FPA
},
32078 {"fpa11", FPU_ARCH_FPA
},
32079 {"arm7500fe", FPU_ARCH_FPA
},
32080 {"softvfp", FPU_ARCH_VFP
},
32081 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
32082 {"vfp", FPU_ARCH_VFP_V2
},
32083 {"vfp9", FPU_ARCH_VFP_V2
},
32084 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
32085 {"vfp10", FPU_ARCH_VFP_V2
},
32086 {"vfp10-r0", FPU_ARCH_VFP_V1
},
32087 {"vfpxd", FPU_ARCH_VFP_V1xD
},
32088 {"vfpv2", FPU_ARCH_VFP_V2
},
32089 {"vfpv3", FPU_ARCH_VFP_V3
},
32090 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
32091 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
32092 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
32093 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
32094 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
32095 {"arm1020t", FPU_ARCH_VFP_V1
},
32096 {"arm1020e", FPU_ARCH_VFP_V2
},
32097 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
32098 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
32099 {"maverick", FPU_ARCH_MAVERICK
},
32100 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32101 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32102 {"neon-fp16", FPU_ARCH_NEON_FP16
},
32103 {"vfpv4", FPU_ARCH_VFP_V4
},
32104 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
32105 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
32106 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
32107 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
32108 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
32109 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
32110 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
32111 {"crypto-neon-fp-armv8",
32112 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
32113 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
32114 {"crypto-neon-fp-armv8.1",
32115 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
32116 {NULL
, ARM_ARCH_NONE
}
32119 struct arm_option_value_table
32125 static const struct arm_option_value_table arm_float_abis
[] =
32127 {"hard", ARM_FLOAT_ABI_HARD
},
32128 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
32129 {"soft", ARM_FLOAT_ABI_SOFT
},
32134 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
32135 static const struct arm_option_value_table arm_eabis
[] =
32137 {"gnu", EF_ARM_EABI_UNKNOWN
},
32138 {"4", EF_ARM_EABI_VER4
},
32139 {"5", EF_ARM_EABI_VER5
},
32144 struct arm_long_option_table
32146 const char * option
; /* Substring to match. */
32147 const char * help
; /* Help information. */
32148 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
32149 const char * deprecated
; /* If non-null, print this message. */
32153 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
32154 arm_feature_set
*ext_set
,
32155 const struct arm_ext_table
*ext_table
)
32157 /* We insist on extensions being specified in alphabetical order, and with
32158 extensions being added before being removed. We achieve this by having
32159 the global ARM_EXTENSIONS table in alphabetical order, and using the
32160 ADDING_VALUE variable to indicate whether we are adding an extension (1)
32161 or removing it (0) and only allowing it to change in the order
32163 const struct arm_option_extension_value_table
* opt
= NULL
;
32164 const arm_feature_set arm_any
= ARM_ANY
;
32165 int adding_value
= -1;
32167 while (str
!= NULL
&& *str
!= 0)
32174 as_bad (_("invalid architectural extension"));
32179 ext
= strchr (str
, '+');
32184 len
= strlen (str
);
32186 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
32188 if (adding_value
!= 0)
32191 opt
= arm_extensions
;
32199 if (adding_value
== -1)
32202 opt
= arm_extensions
;
32204 else if (adding_value
!= 1)
32206 as_bad (_("must specify extensions to add before specifying "
32207 "those to remove"));
32214 as_bad (_("missing architectural extension"));
32218 gas_assert (adding_value
!= -1);
32219 gas_assert (opt
!= NULL
);
32221 if (ext_table
!= NULL
)
32223 const struct arm_ext_table
* ext_opt
= ext_table
;
32224 bfd_boolean found
= FALSE
;
32225 for (; ext_opt
->name
!= NULL
; ext_opt
++)
32226 if (ext_opt
->name_len
== len
32227 && strncmp (ext_opt
->name
, str
, len
) == 0)
32231 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32232 /* TODO: Option not supported. When we remove the
32233 legacy table this case should error out. */
32236 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
32240 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
32241 /* TODO: Option not supported. When we remove the
32242 legacy table this case should error out. */
32244 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
32256 /* Scan over the options table trying to find an exact match. */
32257 for (; opt
->name
!= NULL
; opt
++)
32258 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32260 int i
, nb_allowed_archs
=
32261 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32262 /* Check we can apply the extension to this architecture. */
32263 for (i
= 0; i
< nb_allowed_archs
; i
++)
32266 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
32268 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
32271 if (i
== nb_allowed_archs
)
32273 as_bad (_("extension does not apply to the base architecture"));
32277 /* Add or remove the extension. */
32279 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
32281 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
32283 /* Allowing Thumb division instructions for ARMv7 in autodetection
32284 rely on this break so that duplicate extensions (extensions
32285 with the same name as a previous extension in the list) are not
32286 considered for command-line parsing. */
32290 if (opt
->name
== NULL
)
32292 /* Did we fail to find an extension because it wasn't specified in
32293 alphabetical order, or because it does not exist? */
32295 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32296 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32299 if (opt
->name
== NULL
)
32300 as_bad (_("unknown architectural extension `%s'"), str
);
32302 as_bad (_("architectural extensions must be specified in "
32303 "alphabetical order"));
32309 /* We should skip the extension we've just matched the next time
32321 arm_parse_fp16_opt (const char *str
)
32323 if (strcasecmp (str
, "ieee") == 0)
32324 fp16_format
= ARM_FP16_FORMAT_IEEE
;
32325 else if (strcasecmp (str
, "alternative") == 0)
32326 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
32329 as_bad (_("unrecognised float16 format \"%s\""), str
);
32337 arm_parse_cpu (const char *str
)
32339 const struct arm_cpu_option_table
*opt
;
32340 const char *ext
= strchr (str
, '+');
32346 len
= strlen (str
);
32350 as_bad (_("missing cpu name `%s'"), str
);
32354 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
32355 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32357 mcpu_cpu_opt
= &opt
->value
;
32358 if (mcpu_ext_opt
== NULL
)
32359 mcpu_ext_opt
= XNEW (arm_feature_set
);
32360 *mcpu_ext_opt
= opt
->ext
;
32361 mcpu_fpu_opt
= &opt
->default_fpu
;
32362 if (opt
->canonical_name
)
32364 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
32365 strcpy (selected_cpu_name
, opt
->canonical_name
);
32371 if (len
>= sizeof selected_cpu_name
)
32372 len
= (sizeof selected_cpu_name
) - 1;
32374 for (i
= 0; i
< len
; i
++)
32375 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32376 selected_cpu_name
[i
] = 0;
32380 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
32385 as_bad (_("unknown cpu `%s'"), str
);
32390 arm_parse_arch (const char *str
)
32392 const struct arm_arch_option_table
*opt
;
32393 const char *ext
= strchr (str
, '+');
32399 len
= strlen (str
);
32403 as_bad (_("missing architecture name `%s'"), str
);
32407 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
32408 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32410 march_cpu_opt
= &opt
->value
;
32411 if (march_ext_opt
== NULL
)
32412 march_ext_opt
= XNEW (arm_feature_set
);
32413 *march_ext_opt
= arm_arch_none
;
32414 march_fpu_opt
= &opt
->default_fpu
;
32415 selected_ctx_ext_table
= opt
->ext_table
;
32416 strcpy (selected_cpu_name
, opt
->name
);
32419 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
32425 as_bad (_("unknown architecture `%s'\n"), str
);
32430 arm_parse_fpu (const char * str
)
32432 const struct arm_option_fpu_value_table
* opt
;
32434 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32435 if (streq (opt
->name
, str
))
32437 mfpu_opt
= &opt
->value
;
32441 as_bad (_("unknown floating point format `%s'\n"), str
);
32446 arm_parse_float_abi (const char * str
)
32448 const struct arm_option_value_table
* opt
;
32450 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
32451 if (streq (opt
->name
, str
))
32453 mfloat_abi_opt
= opt
->value
;
32457 as_bad (_("unknown floating point abi `%s'\n"), str
);
32463 arm_parse_eabi (const char * str
)
32465 const struct arm_option_value_table
*opt
;
32467 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
32468 if (streq (opt
->name
, str
))
32470 meabi_flags
= opt
->value
;
32473 as_bad (_("unknown EABI `%s'\n"), str
);
32479 arm_parse_it_mode (const char * str
)
32481 bfd_boolean ret
= TRUE
;
32483 if (streq ("arm", str
))
32484 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
32485 else if (streq ("thumb", str
))
32486 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
32487 else if (streq ("always", str
))
32488 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
32489 else if (streq ("never", str
))
32490 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
32493 as_bad (_("unknown implicit IT mode `%s', should be "\
32494 "arm, thumb, always, or never."), str
);
32502 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
32504 codecomposer_syntax
= TRUE
;
32505 arm_comment_chars
[0] = ';';
32506 arm_line_separator_chars
[0] = 0;
32510 struct arm_long_option_table arm_long_opts
[] =
32512 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
32513 arm_parse_cpu
, NULL
},
32514 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
32515 arm_parse_arch
, NULL
},
32516 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
32517 arm_parse_fpu
, NULL
},
32518 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
32519 arm_parse_float_abi
, NULL
},
32521 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
32522 arm_parse_eabi
, NULL
},
32524 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
32525 arm_parse_it_mode
, NULL
},
32526 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
32527 arm_ccs_mode
, NULL
},
32529 N_("[ieee|alternative]\n\
32530 set the encoding for half precision floating point "
32531 "numbers to IEEE\n\
32532 or Arm alternative format."),
32533 arm_parse_fp16_opt
, NULL
},
32534 {NULL
, NULL
, 0, NULL
}
32538 md_parse_option (int c
, const char * arg
)
32540 struct arm_option_table
*opt
;
32541 const struct arm_legacy_option_table
*fopt
;
32542 struct arm_long_option_table
*lopt
;
32548 target_big_endian
= 1;
32554 target_big_endian
= 0;
32558 case OPTION_FIX_V4BX
:
32566 #endif /* OBJ_ELF */
32569 /* Listing option. Just ignore these, we don't support additional
32574 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32576 if (c
== opt
->option
[0]
32577 && ((arg
== NULL
&& opt
->option
[1] == 0)
32578 || streq (arg
, opt
->option
+ 1)))
32580 /* If the option is deprecated, tell the user. */
32581 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
32582 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32583 arg
? arg
: "", _(opt
->deprecated
));
32585 if (opt
->var
!= NULL
)
32586 *opt
->var
= opt
->value
;
32592 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
32594 if (c
== fopt
->option
[0]
32595 && ((arg
== NULL
&& fopt
->option
[1] == 0)
32596 || streq (arg
, fopt
->option
+ 1)))
32598 /* If the option is deprecated, tell the user. */
32599 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
32600 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32601 arg
? arg
: "", _(fopt
->deprecated
));
32603 if (fopt
->var
!= NULL
)
32604 *fopt
->var
= &fopt
->value
;
32610 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32612 /* These options are expected to have an argument. */
32613 if (c
== lopt
->option
[0]
32615 && strncmp (arg
, lopt
->option
+ 1,
32616 strlen (lopt
->option
+ 1)) == 0)
32618 /* If the option is deprecated, tell the user. */
32619 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
32620 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
32621 _(lopt
->deprecated
));
32623 /* Call the sup-option parser. */
32624 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
32635 md_show_usage (FILE * fp
)
32637 struct arm_option_table
*opt
;
32638 struct arm_long_option_table
*lopt
;
32640 fprintf (fp
, _(" ARM-specific assembler options:\n"));
32642 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32643 if (opt
->help
!= NULL
)
32644 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
32646 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32647 if (lopt
->help
!= NULL
)
32648 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
32652 -EB assemble code for a big-endian cpu\n"));
32657 -EL assemble code for a little-endian cpu\n"));
32661 --fix-v4bx Allow BX in ARMv4 code\n"));
32665 --fdpic generate an FDPIC object file\n"));
32666 #endif /* OBJ_ELF */
32674 arm_feature_set flags
;
32675 } cpu_arch_ver_table
;
32677 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32678 chronologically for architectures, with an exception for ARMv6-M and
32679 ARMv6S-M due to legacy reasons. No new architecture should have a
32680 special case. This allows for build attribute selection results to be
32681 stable when new architectures are added. */
32682 static const cpu_arch_ver_table cpu_arch_ver
[] =
32684 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
32685 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
32686 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
32687 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
32688 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
32689 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
32690 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
32691 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
32692 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
32693 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
32694 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
32695 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
32696 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
32697 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
32698 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
32699 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
32700 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
32701 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
32702 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
32703 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
32704 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
32705 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
32706 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
32707 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
32709 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32710 always selected build attributes to match those of ARMv6-M
32711 (resp. ARMv6S-M). However, due to these architectures being a strict
32712 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32713 would be selected when fully respecting chronology of architectures.
32714 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32715 move them before ARMv7 architectures. */
32716 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32717 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32719 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32720 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32721 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32722 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32723 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32724 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32725 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32726 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32727 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32728 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32729 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32730 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32731 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32732 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32733 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32734 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32735 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32736 {-1, ARM_ARCH_NONE
}
32739 /* Set an attribute if it has not already been set by the user. */
32742 aeabi_set_attribute_int (int tag
, int value
)
32745 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32746 || !attributes_set_explicitly
[tag
])
32747 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32751 aeabi_set_attribute_string (int tag
, const char *value
)
32754 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32755 || !attributes_set_explicitly
[tag
])
32756 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32759 /* Return whether features in the *NEEDED feature set are available via
32760 extensions for the architecture whose feature set is *ARCH_FSET. */
32763 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32764 const arm_feature_set
*needed
)
32766 int i
, nb_allowed_archs
;
32767 arm_feature_set ext_fset
;
32768 const struct arm_option_extension_value_table
*opt
;
32770 ext_fset
= arm_arch_none
;
32771 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32773 /* Extension does not provide any feature we need. */
32774 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32778 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32779 for (i
= 0; i
< nb_allowed_archs
; i
++)
32782 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32785 /* Extension is available, add it. */
32786 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32787 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32791 /* Can we enable all features in *needed? */
32792 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32795 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32796 a given architecture feature set *ARCH_EXT_FSET including extension feature
32797 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32798 - if true, check for an exact match of the architecture modulo extensions;
32799 - otherwise, select build attribute value of the first superset
32800 architecture released so that results remains stable when new architectures
32802 For -march/-mcpu=all the build attribute value of the most featureful
32803 architecture is returned. Tag_CPU_arch_profile result is returned in
32807 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32808 const arm_feature_set
*ext_fset
,
32809 char *profile
, int exact_match
)
32811 arm_feature_set arch_fset
;
32812 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32814 /* Select most featureful architecture with all its extensions if building
32815 for -march=all as the feature sets used to set build attributes. */
32816 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32818 /* Force revisiting of decision for each new architecture. */
32819 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32821 return TAG_CPU_ARCH_V8
;
32824 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32826 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32828 arm_feature_set known_arch_fset
;
32830 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32833 /* Base architecture match user-specified architecture and
32834 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32835 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32840 /* Base architecture match user-specified architecture only
32841 (eg. ARMv6-M in the same case as above). Record it in case we
32842 find a match with above condition. */
32843 else if (p_ver_ret
== NULL
32844 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32850 /* Architecture has all features wanted. */
32851 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32853 arm_feature_set added_fset
;
32855 /* Compute features added by this architecture over the one
32856 recorded in p_ver_ret. */
32857 if (p_ver_ret
!= NULL
)
32858 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32860 /* First architecture that match incl. with extensions, or the
32861 only difference in features over the recorded match is
32862 features that were optional and are now mandatory. */
32863 if (p_ver_ret
== NULL
32864 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32870 else if (p_ver_ret
== NULL
)
32872 arm_feature_set needed_ext_fset
;
32874 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32876 /* Architecture has all features needed when using some
32877 extensions. Record it and continue searching in case there
32878 exist an architecture providing all needed features without
32879 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32881 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32888 if (p_ver_ret
== NULL
)
32892 /* Tag_CPU_arch_profile. */
32893 if (!ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
)
32894 && (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32895 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32896 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32897 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
))))
32899 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
)
32900 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8r
))
32902 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32906 return p_ver_ret
->val
;
32909 /* Set the public EABI object attributes. */
32912 aeabi_set_public_attributes (void)
32914 char profile
= '\0';
32917 int fp16_optional
= 0;
32918 int skip_exact_match
= 0;
32919 arm_feature_set flags
, flags_arch
, flags_ext
;
32921 /* Autodetection mode, choose the architecture based the instructions
32923 if (no_cpu_selected ())
32925 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32927 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32928 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32930 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32931 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32933 /* Code run during relaxation relies on selected_cpu being set. */
32934 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32935 flags_ext
= arm_arch_none
;
32936 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32937 selected_ext
= flags_ext
;
32938 selected_cpu
= flags
;
32940 /* Otherwise, choose the architecture based on the capabilities of the
32944 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32945 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32946 flags_ext
= selected_ext
;
32947 flags
= selected_cpu
;
32949 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32951 /* Allow the user to override the reported architecture. */
32952 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32954 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32955 flags_ext
= arm_arch_none
;
32958 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32960 /* When this function is run again after relaxation has happened there is no
32961 way to determine whether an architecture or CPU was specified by the user:
32962 - selected_cpu is set above for relaxation to work;
32963 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32964 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32965 Therefore, if not in -march=all case we first try an exact match and fall
32966 back to autodetection. */
32967 if (!skip_exact_match
)
32968 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32970 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32972 as_bad (_("no architecture contains all the instructions used\n"));
32974 /* Tag_CPU_name. */
32975 if (selected_cpu_name
[0])
32979 q
= selected_cpu_name
;
32980 if (strncmp (q
, "armv", 4) == 0)
32985 for (i
= 0; q
[i
]; i
++)
32986 q
[i
] = TOUPPER (q
[i
]);
32988 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32991 /* Tag_CPU_arch. */
32992 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32994 /* Tag_CPU_arch_profile. */
32995 if (profile
!= '\0')
32996 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32998 /* Tag_DSP_extension. */
32999 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
33000 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
33002 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
33003 /* Tag_ARM_ISA_use. */
33004 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
33005 || ARM_FEATURE_ZERO (flags_arch
))
33006 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
33008 /* Tag_THUMB_ISA_use. */
33009 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
33010 || ARM_FEATURE_ZERO (flags_arch
))
33014 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33015 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
33017 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
33021 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
33024 /* Tag_VFP_arch. */
33025 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
33026 aeabi_set_attribute_int (Tag_VFP_arch
,
33027 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33029 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
33030 aeabi_set_attribute_int (Tag_VFP_arch
,
33031 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33033 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
33036 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
33038 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
33040 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
33043 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
33044 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
33045 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
33046 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
33047 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
33049 /* Tag_ABI_HardFP_use. */
33050 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
33051 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
33052 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
33054 /* Tag_WMMX_arch. */
33055 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
33056 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
33057 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
33058 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
33060 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
33061 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
33062 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
33063 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
33064 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
33065 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
33067 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
33069 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
33073 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
33078 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
33079 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
33080 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
33081 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
33083 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
33084 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
33085 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
33089 We set Tag_DIV_use to two when integer divide instructions have been used
33090 in ARM state, or when Thumb integer divide instructions have been used,
33091 but we have no architecture profile set, nor have we any ARM instructions.
33093 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33094 by the base architecture.
33096 For new architectures we will have to check these tests. */
33097 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
33098 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33099 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
33100 aeabi_set_attribute_int (Tag_DIV_use
, 0);
33101 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
33102 || (profile
== '\0'
33103 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
33104 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
33105 aeabi_set_attribute_int (Tag_DIV_use
, 2);
33107 /* Tag_MP_extension_use. */
33108 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
33109 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
33111 /* Tag Virtualization_use. */
33112 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
33114 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
33117 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
33119 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
33120 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
33123 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
33124 finished and free extension feature bits which will not be used anymore. */
33127 arm_md_post_relax (void)
33129 aeabi_set_public_attributes ();
33130 XDELETE (mcpu_ext_opt
);
33131 mcpu_ext_opt
= NULL
;
33132 XDELETE (march_ext_opt
);
33133 march_ext_opt
= NULL
;
33136 /* Add the default contents for the .ARM.attributes section. */
33141 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
33144 aeabi_set_public_attributes ();
33146 #endif /* OBJ_ELF */
33148 /* Parse a .cpu directive. */
33151 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
33153 const struct arm_cpu_option_table
*opt
;
33157 name
= input_line_pointer
;
33158 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33159 input_line_pointer
++;
33160 saved_char
= *input_line_pointer
;
33161 *input_line_pointer
= 0;
33163 /* Skip the first "all" entry. */
33164 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
33165 if (streq (opt
->name
, name
))
33167 selected_arch
= opt
->value
;
33168 selected_ext
= opt
->ext
;
33169 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33170 if (opt
->canonical_name
)
33171 strcpy (selected_cpu_name
, opt
->canonical_name
);
33175 for (i
= 0; opt
->name
[i
]; i
++)
33176 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
33178 selected_cpu_name
[i
] = 0;
33180 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33182 *input_line_pointer
= saved_char
;
33183 demand_empty_rest_of_line ();
33186 as_bad (_("unknown cpu `%s'"), name
);
33187 *input_line_pointer
= saved_char
;
33188 ignore_rest_of_line ();
33191 /* Parse a .arch directive. */
33194 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
33196 const struct arm_arch_option_table
*opt
;
33200 name
= input_line_pointer
;
33201 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33202 input_line_pointer
++;
33203 saved_char
= *input_line_pointer
;
33204 *input_line_pointer
= 0;
33206 /* Skip the first "all" entry. */
33207 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33208 if (streq (opt
->name
, name
))
33210 selected_arch
= opt
->value
;
33211 selected_ctx_ext_table
= opt
->ext_table
;
33212 selected_ext
= arm_arch_none
;
33213 selected_cpu
= selected_arch
;
33214 strcpy (selected_cpu_name
, opt
->name
);
33215 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33216 *input_line_pointer
= saved_char
;
33217 demand_empty_rest_of_line ();
33221 as_bad (_("unknown architecture `%s'\n"), name
);
33222 *input_line_pointer
= saved_char
;
33223 ignore_rest_of_line ();
33226 /* Parse a .object_arch directive. */
33229 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
33231 const struct arm_arch_option_table
*opt
;
33235 name
= input_line_pointer
;
33236 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33237 input_line_pointer
++;
33238 saved_char
= *input_line_pointer
;
33239 *input_line_pointer
= 0;
33241 /* Skip the first "all" entry. */
33242 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33243 if (streq (opt
->name
, name
))
33245 selected_object_arch
= opt
->value
;
33246 *input_line_pointer
= saved_char
;
33247 demand_empty_rest_of_line ();
33251 as_bad (_("unknown architecture `%s'\n"), name
);
33252 *input_line_pointer
= saved_char
;
33253 ignore_rest_of_line ();
33256 /* Parse a .arch_extension directive. */
33259 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
33261 const struct arm_option_extension_value_table
*opt
;
33264 int adding_value
= 1;
33266 name
= input_line_pointer
;
33267 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33268 input_line_pointer
++;
33269 saved_char
= *input_line_pointer
;
33270 *input_line_pointer
= 0;
33272 if (strlen (name
) >= 2
33273 && strncmp (name
, "no", 2) == 0)
33279 /* Check the context specific extension table */
33280 if (selected_ctx_ext_table
)
33282 const struct arm_ext_table
* ext_opt
;
33283 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
33285 if (streq (ext_opt
->name
, name
))
33289 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
33290 /* TODO: Option not supported. When we remove the
33291 legacy table this case should error out. */
33293 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33297 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
33299 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33300 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33301 *input_line_pointer
= saved_char
;
33302 demand_empty_rest_of_line ();
33308 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
33309 if (streq (opt
->name
, name
))
33311 int i
, nb_allowed_archs
=
33312 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
33313 for (i
= 0; i
< nb_allowed_archs
; i
++)
33316 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
33318 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
33322 if (i
== nb_allowed_archs
)
33324 as_bad (_("architectural extension `%s' is not allowed for the "
33325 "current base architecture"), name
);
33330 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33333 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
33335 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33336 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33337 *input_line_pointer
= saved_char
;
33338 demand_empty_rest_of_line ();
33339 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
33340 on this return so that duplicate extensions (extensions with the
33341 same name as a previous extension in the list) are not considered
33342 for command-line parsing. */
33346 if (opt
->name
== NULL
)
33347 as_bad (_("unknown architecture extension `%s'\n"), name
);
33349 *input_line_pointer
= saved_char
;
33350 ignore_rest_of_line ();
33353 /* Parse a .fpu directive. */
33356 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
33358 const struct arm_option_fpu_value_table
*opt
;
33362 name
= input_line_pointer
;
33363 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33364 input_line_pointer
++;
33365 saved_char
= *input_line_pointer
;
33366 *input_line_pointer
= 0;
33368 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
33369 if (streq (opt
->name
, name
))
33371 selected_fpu
= opt
->value
;
33372 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, fpu_any
);
33373 #ifndef CPU_DEFAULT
33374 if (no_cpu_selected ())
33375 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
33378 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33379 *input_line_pointer
= saved_char
;
33380 demand_empty_rest_of_line ();
33384 as_bad (_("unknown floating point format `%s'\n"), name
);
33385 *input_line_pointer
= saved_char
;
33386 ignore_rest_of_line ();
33389 /* Copy symbol information. */
33392 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
33394 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
33398 /* Given a symbolic attribute NAME, return the proper integer value.
33399 Returns -1 if the attribute is not known. */
33402 arm_convert_symbolic_attribute (const char *name
)
33404 static const struct
33409 attribute_table
[] =
33411 /* When you modify this table you should
33412 also modify the list in doc/c-arm.texi. */
33413 #define T(tag) {#tag, tag}
33414 T (Tag_CPU_raw_name
),
33417 T (Tag_CPU_arch_profile
),
33418 T (Tag_ARM_ISA_use
),
33419 T (Tag_THUMB_ISA_use
),
33423 T (Tag_Advanced_SIMD_arch
),
33424 T (Tag_PCS_config
),
33425 T (Tag_ABI_PCS_R9_use
),
33426 T (Tag_ABI_PCS_RW_data
),
33427 T (Tag_ABI_PCS_RO_data
),
33428 T (Tag_ABI_PCS_GOT_use
),
33429 T (Tag_ABI_PCS_wchar_t
),
33430 T (Tag_ABI_FP_rounding
),
33431 T (Tag_ABI_FP_denormal
),
33432 T (Tag_ABI_FP_exceptions
),
33433 T (Tag_ABI_FP_user_exceptions
),
33434 T (Tag_ABI_FP_number_model
),
33435 T (Tag_ABI_align_needed
),
33436 T (Tag_ABI_align8_needed
),
33437 T (Tag_ABI_align_preserved
),
33438 T (Tag_ABI_align8_preserved
),
33439 T (Tag_ABI_enum_size
),
33440 T (Tag_ABI_HardFP_use
),
33441 T (Tag_ABI_VFP_args
),
33442 T (Tag_ABI_WMMX_args
),
33443 T (Tag_ABI_optimization_goals
),
33444 T (Tag_ABI_FP_optimization_goals
),
33445 T (Tag_compatibility
),
33446 T (Tag_CPU_unaligned_access
),
33447 T (Tag_FP_HP_extension
),
33448 T (Tag_VFP_HP_extension
),
33449 T (Tag_ABI_FP_16bit_format
),
33450 T (Tag_MPextension_use
),
33452 T (Tag_nodefaults
),
33453 T (Tag_also_compatible_with
),
33454 T (Tag_conformance
),
33456 T (Tag_Virtualization_use
),
33457 T (Tag_DSP_extension
),
33459 /* We deliberately do not include Tag_MPextension_use_legacy. */
33467 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
33468 if (streq (name
, attribute_table
[i
].name
))
33469 return attribute_table
[i
].tag
;
33474 /* Apply sym value for relocations only in the case that they are for
33475 local symbols in the same segment as the fixup and you have the
33476 respective architectural feature for blx and simple switches. */
33479 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
33482 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
33483 /* PR 17444: If the local symbol is in a different section then a reloc
33484 will always be generated for it, so applying the symbol value now
33485 will result in a double offset being stored in the relocation. */
33486 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
33487 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
33489 switch (fixP
->fx_r_type
)
33491 case BFD_RELOC_ARM_PCREL_BLX
:
33492 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
33493 if (ARM_IS_FUNC (fixP
->fx_addsy
))
33497 case BFD_RELOC_ARM_PCREL_CALL
:
33498 case BFD_RELOC_THUMB_PCREL_BLX
:
33499 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
33510 #endif /* OBJ_ELF */