1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
188 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
221 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
222 static const arm_feature_set fpu_vfp_ext_d32
=
223 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
224 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
225 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
226 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
227 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
228 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
229 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
231 static int mfloat_abi_opt
= -1;
232 /* Record user cpu selection for object attributes. */
233 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
234 /* Must be long enough to hold any of the names in arm_cpus. */
235 static char selected_cpu_name
[16];
238 static int meabi_flags
= EABI_DEFAULT
;
240 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
243 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
248 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
253 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
254 symbolS
* GOT_symbol
;
257 /* 0: assemble for ARM,
258 1: assemble for Thumb,
259 2: assemble for Thumb even though target CPU does not support thumb
261 static int thumb_mode
= 0;
262 /* A value distinct from the possible values for thumb_mode that we
263 can use to record whether thumb_mode has been copied into the
264 tc_frag_data field of a frag. */
265 #define MODE_RECORDED (1 << 4)
267 /* Specifies the intrinsic IT insn behavior mode. */
268 enum implicit_it_mode
270 IMPLICIT_IT_MODE_NEVER
= 0x00,
271 IMPLICIT_IT_MODE_ARM
= 0x01,
272 IMPLICIT_IT_MODE_THUMB
= 0x02,
273 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
275 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
277 /* If unified_syntax is true, we are processing the new unified
278 ARM/Thumb syntax. Important differences from the old ARM mode:
280 - Immediate operands do not require a # prefix.
281 - Conditional affixes always appear at the end of the
282 instruction. (For backward compatibility, those instructions
283 that formerly had them in the middle, continue to accept them
285 - The IT instruction may appear, and if it does is validated
286 against subsequent conditional affixes. It does not generate
289 Important differences from the old Thumb mode:
291 - Immediate operands do not require a # prefix.
292 - Most of the V6T2 instructions are only available in unified mode.
293 - The .N and .W suffixes are recognized and honored (it is an error
294 if they cannot be honored).
295 - All instructions set the flags if and only if they have an 's' affix.
296 - Conditional affixes may be used. They are validated against
297 preceding IT instructions. Unlike ARM mode, you cannot use a
298 conditional affix except in the scope of an IT instruction. */
300 static bfd_boolean unified_syntax
= FALSE
;
315 enum neon_el_type type
;
319 #define NEON_MAX_TYPE_ELS 4
323 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
327 enum it_instruction_type
332 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
333 if inside, should be the last one. */
334 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
335 i.e. BKPT and NOP. */
336 IT_INSN
/* The IT insn has been parsed. */
342 unsigned long instruction
;
346 /* "uncond_value" is set to the value in place of the conditional field in
347 unconditional versions of the instruction, or -1 if nothing is
350 struct neon_type vectype
;
351 /* This does not indicate an actual NEON instruction, only that
352 the mnemonic accepts neon-style type suffixes. */
354 /* Set to the opcode if the instruction needs relaxation.
355 Zero if the instruction is not relaxed. */
359 bfd_reloc_code_real_type type
;
364 enum it_instruction_type it_insn_type
;
370 struct neon_type_el vectype
;
371 unsigned present
: 1; /* Operand present. */
372 unsigned isreg
: 1; /* Operand was a register. */
373 unsigned immisreg
: 1; /* .imm field is a second register. */
374 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
375 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
376 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
377 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
378 instructions. This allows us to disambiguate ARM <-> vector insns. */
379 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
380 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
381 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
382 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
383 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
384 unsigned writeback
: 1; /* Operand has trailing ! */
385 unsigned preind
: 1; /* Preindexed address. */
386 unsigned postind
: 1; /* Postindexed address. */
387 unsigned negative
: 1; /* Index register was negated. */
388 unsigned shifted
: 1; /* Shift applied to operation. */
389 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
393 static struct arm_it inst
;
395 #define NUM_FLOAT_VALS 8
397 const char * fp_const
[] =
399 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
402 /* Number of littlenums required to hold an extended precision number. */
403 #define MAX_LITTLENUMS 6
405 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
415 #define CP_T_X 0x00008000
416 #define CP_T_Y 0x00400000
418 #define CONDS_BIT 0x00100000
419 #define LOAD_BIT 0x00100000
421 #define DOUBLE_LOAD_FLAG 0x00000001
425 const char * template_name
;
429 #define COND_ALWAYS 0xE
433 const char * template_name
;
437 struct asm_barrier_opt
439 const char * template_name
;
443 /* The bit that distinguishes CPSR and SPSR. */
444 #define SPSR_BIT (1 << 22)
446 /* The individual PSR flag bits. */
447 #define PSR_c (1 << 16)
448 #define PSR_x (1 << 17)
449 #define PSR_s (1 << 18)
450 #define PSR_f (1 << 19)
455 bfd_reloc_code_real_type reloc
;
460 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
461 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
466 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
469 /* Bits for DEFINED field in neon_typed_alias. */
470 #define NTA_HASTYPE 1
471 #define NTA_HASINDEX 2
473 struct neon_typed_alias
475 unsigned char defined
;
477 struct neon_type_el eltype
;
480 /* ARM register categories. This includes coprocessor numbers and various
481 architecture extensions' registers. */
507 /* Structure for a hash table entry for a register.
508 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
509 information which states whether a vector type or index is specified (for a
510 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
514 unsigned char number
;
516 unsigned char builtin
;
517 struct neon_typed_alias
* neon
;
520 /* Diagnostics used when we don't get a register of the expected type. */
521 const char * const reg_expected_msgs
[] =
523 N_("ARM register expected"),
524 N_("bad or missing co-processor number"),
525 N_("co-processor register expected"),
526 N_("FPA register expected"),
527 N_("VFP single precision register expected"),
528 N_("VFP/Neon double precision register expected"),
529 N_("Neon quad precision register expected"),
530 N_("VFP single or double precision register expected"),
531 N_("Neon double or quad precision register expected"),
532 N_("VFP single, double or Neon quad precision register expected"),
533 N_("VFP system register expected"),
534 N_("Maverick MVF register expected"),
535 N_("Maverick MVD register expected"),
536 N_("Maverick MVFX register expected"),
537 N_("Maverick MVDX register expected"),
538 N_("Maverick MVAX register expected"),
539 N_("Maverick DSPSC register expected"),
540 N_("iWMMXt data register expected"),
541 N_("iWMMXt control register expected"),
542 N_("iWMMXt scalar register expected"),
543 N_("XScale accumulator register expected"),
546 /* Some well known registers that we refer to directly elsewhere. */
551 /* ARM instructions take 4bytes in the object file, Thumb instructions
557 /* Basic string to match. */
558 const char * template_name
;
560 /* Parameters to instruction. */
561 unsigned int operands
[8];
563 /* Conditional tag - see opcode_lookup. */
564 unsigned int tag
: 4;
566 /* Basic instruction code. */
567 unsigned int avalue
: 28;
569 /* Thumb-format instruction code. */
572 /* Which architecture variant provides this instruction. */
573 const arm_feature_set
* avariant
;
574 const arm_feature_set
* tvariant
;
576 /* Function to call to encode instruction in ARM format. */
577 void (* aencode
) (void);
579 /* Function to call to encode instruction in Thumb format. */
580 void (* tencode
) (void);
583 /* Defines for various bits that we will want to toggle. */
584 #define INST_IMMEDIATE 0x02000000
585 #define OFFSET_REG 0x02000000
586 #define HWOFFSET_IMM 0x00400000
587 #define SHIFT_BY_REG 0x00000010
588 #define PRE_INDEX 0x01000000
589 #define INDEX_UP 0x00800000
590 #define WRITE_BACK 0x00200000
591 #define LDM_TYPE_2_OR_3 0x00400000
592 #define CPSI_MMOD 0x00020000
594 #define LITERAL_MASK 0xf000f000
595 #define OPCODE_MASK 0xfe1fffff
596 #define V4_STR_BIT 0x00000020
598 #define T2_SUBS_PC_LR 0xf3de8f00
600 #define DATA_OP_SHIFT 21
602 #define T2_OPCODE_MASK 0xfe1fffff
603 #define T2_DATA_OP_SHIFT 21
605 /* Codes to distinguish the arithmetic instructions. */
616 #define OPCODE_CMP 10
617 #define OPCODE_CMN 11
618 #define OPCODE_ORR 12
619 #define OPCODE_MOV 13
620 #define OPCODE_BIC 14
621 #define OPCODE_MVN 15
623 #define T2_OPCODE_AND 0
624 #define T2_OPCODE_BIC 1
625 #define T2_OPCODE_ORR 2
626 #define T2_OPCODE_ORN 3
627 #define T2_OPCODE_EOR 4
628 #define T2_OPCODE_ADD 8
629 #define T2_OPCODE_ADC 10
630 #define T2_OPCODE_SBC 11
631 #define T2_OPCODE_SUB 13
632 #define T2_OPCODE_RSB 14
634 #define T_OPCODE_MUL 0x4340
635 #define T_OPCODE_TST 0x4200
636 #define T_OPCODE_CMN 0x42c0
637 #define T_OPCODE_NEG 0x4240
638 #define T_OPCODE_MVN 0x43c0
640 #define T_OPCODE_ADD_R3 0x1800
641 #define T_OPCODE_SUB_R3 0x1a00
642 #define T_OPCODE_ADD_HI 0x4400
643 #define T_OPCODE_ADD_ST 0xb000
644 #define T_OPCODE_SUB_ST 0xb080
645 #define T_OPCODE_ADD_SP 0xa800
646 #define T_OPCODE_ADD_PC 0xa000
647 #define T_OPCODE_ADD_I8 0x3000
648 #define T_OPCODE_SUB_I8 0x3800
649 #define T_OPCODE_ADD_I3 0x1c00
650 #define T_OPCODE_SUB_I3 0x1e00
652 #define T_OPCODE_ASR_R 0x4100
653 #define T_OPCODE_LSL_R 0x4080
654 #define T_OPCODE_LSR_R 0x40c0
655 #define T_OPCODE_ROR_R 0x41c0
656 #define T_OPCODE_ASR_I 0x1000
657 #define T_OPCODE_LSL_I 0x0000
658 #define T_OPCODE_LSR_I 0x0800
660 #define T_OPCODE_MOV_I8 0x2000
661 #define T_OPCODE_CMP_I8 0x2800
662 #define T_OPCODE_CMP_LR 0x4280
663 #define T_OPCODE_MOV_HR 0x4600
664 #define T_OPCODE_CMP_HR 0x4500
666 #define T_OPCODE_LDR_PC 0x4800
667 #define T_OPCODE_LDR_SP 0x9800
668 #define T_OPCODE_STR_SP 0x9000
669 #define T_OPCODE_LDR_IW 0x6800
670 #define T_OPCODE_STR_IW 0x6000
671 #define T_OPCODE_LDR_IH 0x8800
672 #define T_OPCODE_STR_IH 0x8000
673 #define T_OPCODE_LDR_IB 0x7800
674 #define T_OPCODE_STR_IB 0x7000
675 #define T_OPCODE_LDR_RW 0x5800
676 #define T_OPCODE_STR_RW 0x5000
677 #define T_OPCODE_LDR_RH 0x5a00
678 #define T_OPCODE_STR_RH 0x5200
679 #define T_OPCODE_LDR_RB 0x5c00
680 #define T_OPCODE_STR_RB 0x5400
682 #define T_OPCODE_PUSH 0xb400
683 #define T_OPCODE_POP 0xbc00
685 #define T_OPCODE_BRANCH 0xe000
687 #define THUMB_SIZE 2 /* Size of thumb instruction. */
688 #define THUMB_PP_PC_LR 0x0100
689 #define THUMB_LOAD_BIT 0x0800
690 #define THUMB2_LOAD_BIT 0x00100000
692 #define BAD_ARGS _("bad arguments to instruction")
693 #define BAD_SP _("r13 not allowed here")
694 #define BAD_PC _("r15 not allowed here")
695 #define BAD_COND _("instruction cannot be conditional")
696 #define BAD_OVERLAP _("registers may not be the same")
697 #define BAD_HIREG _("lo register required")
698 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
699 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
700 #define BAD_BRANCH _("branch must be last instruction in IT block")
701 #define BAD_NOT_IT _("instruction not allowed in IT block")
702 #define BAD_FPU _("selected FPU does not support instruction")
703 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
704 #define BAD_IT_COND _("incorrect condition in IT block")
705 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
706 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
707 #define BAD_PC_ADDRESSING \
708 _("cannot use register index with PC-relative addressing")
709 #define BAD_PC_WRITEBACK \
710 _("cannot use writeback with PC-relative addressing")
712 static struct hash_control
* arm_ops_hsh
;
713 static struct hash_control
* arm_cond_hsh
;
714 static struct hash_control
* arm_shift_hsh
;
715 static struct hash_control
* arm_psr_hsh
;
716 static struct hash_control
* arm_v7m_psr_hsh
;
717 static struct hash_control
* arm_reg_hsh
;
718 static struct hash_control
* arm_reloc_hsh
;
719 static struct hash_control
* arm_barrier_opt_hsh
;
721 /* Stuff needed to resolve the label ambiguity
730 symbolS
* last_label_seen
;
731 static int label_is_thumb_function_name
= FALSE
;
733 /* Literal pool structure. Held on a per-section
734 and per-sub-section basis. */
736 #define MAX_LITERAL_POOL_SIZE 1024
737 typedef struct literal_pool
739 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
740 unsigned int next_free_entry
;
745 struct literal_pool
* next
;
748 /* Pointer to a linked list of literal pools. */
749 literal_pool
* list_of_pools
= NULL
;
752 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
754 static struct current_it now_it
;
758 now_it_compatible (int cond
)
760 return (cond
& ~1) == (now_it
.cc
& ~1);
764 conditional_insn (void)
766 return inst
.cond
!= COND_ALWAYS
;
769 static int in_it_block (void);
771 static int handle_it_state (void);
773 static void force_automatic_it_block_close (void);
775 static void it_fsm_post_encode (void);
777 #define set_it_insn_type(type) \
780 inst.it_insn_type = type; \
781 if (handle_it_state () == FAIL) \
786 #define set_it_insn_type_nonvoid(type, failret) \
789 inst.it_insn_type = type; \
790 if (handle_it_state () == FAIL) \
795 #define set_it_insn_type_last() \
798 if (inst.cond == COND_ALWAYS) \
799 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
801 set_it_insn_type (INSIDE_IT_LAST_INSN); \
807 /* This array holds the chars that always start a comment. If the
808 pre-processor is disabled, these aren't very useful. */
809 const char comment_chars
[] = "@";
811 /* This array holds the chars that only start a comment at the beginning of
812 a line. If the line seems to have the form '# 123 filename'
813 .line and .file directives will appear in the pre-processed output. */
814 /* Note that input_file.c hand checks for '#' at the beginning of the
815 first line of the input file. This is because the compiler outputs
816 #NO_APP at the beginning of its output. */
817 /* Also note that comments like this one will always work. */
818 const char line_comment_chars
[] = "#";
820 const char line_separator_chars
[] = ";";
822 /* Chars that can be used to separate mant
823 from exp in floating point numbers. */
824 const char EXP_CHARS
[] = "eE";
826 /* Chars that mean this number is a floating point constant. */
830 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
832 /* Prefix characters that indicate the start of an immediate
834 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
836 /* Separator character handling. */
838 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
841 skip_past_char (char ** str
, char c
)
852 #define skip_past_comma(str) skip_past_char (str, ',')
854 /* Arithmetic expressions (possibly involving symbols). */
856 /* Return TRUE if anything in the expression is a bignum. */
859 walk_no_bignums (symbolS
* sp
)
861 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
864 if (symbol_get_value_expression (sp
)->X_add_symbol
)
866 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
867 || (symbol_get_value_expression (sp
)->X_op_symbol
868 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
874 static int in_my_get_expression
= 0;
876 /* Third argument to my_get_expression. */
877 #define GE_NO_PREFIX 0
878 #define GE_IMM_PREFIX 1
879 #define GE_OPT_PREFIX 2
880 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
881 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
882 #define GE_OPT_PREFIX_BIG 3
885 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
890 /* In unified syntax, all prefixes are optional. */
892 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
897 case GE_NO_PREFIX
: break;
899 if (!is_immediate_prefix (**str
))
901 inst
.error
= _("immediate expression requires a # prefix");
907 case GE_OPT_PREFIX_BIG
:
908 if (is_immediate_prefix (**str
))
914 memset (ep
, 0, sizeof (expressionS
));
916 save_in
= input_line_pointer
;
917 input_line_pointer
= *str
;
918 in_my_get_expression
= 1;
919 seg
= expression (ep
);
920 in_my_get_expression
= 0;
922 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
924 /* We found a bad or missing expression in md_operand(). */
925 *str
= input_line_pointer
;
926 input_line_pointer
= save_in
;
927 if (inst
.error
== NULL
)
928 inst
.error
= (ep
->X_op
== O_absent
929 ? _("missing expression") :_("bad expression"));
934 if (seg
!= absolute_section
935 && seg
!= text_section
936 && seg
!= data_section
937 && seg
!= bss_section
938 && seg
!= undefined_section
)
940 inst
.error
= _("bad segment");
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
949 /* Get rid of any bignums now, so that we don't generate an error for which
950 we can't establish a line number later on. Big numbers are never valid
951 in instructions, which is where this routine is always called. */
952 if (prefix_mode
!= GE_OPT_PREFIX_BIG
953 && (ep
->X_op
== O_big
955 && (walk_no_bignums (ep
->X_add_symbol
)
957 && walk_no_bignums (ep
->X_op_symbol
))))))
959 inst
.error
= _("invalid constant");
960 *str
= input_line_pointer
;
961 input_line_pointer
= save_in
;
965 *str
= input_line_pointer
;
966 input_line_pointer
= save_in
;
970 /* Turn a string in input_line_pointer into a floating point constant
971 of type TYPE, and store the appropriate bytes in *LITP. The number
972 of LITTLENUMS emitted is stored in *SIZEP. An error message is
973 returned, or NULL on OK.
975 Note that fp constants aren't represent in the normal way on the ARM.
976 In big endian mode, things are as expected. However, in little endian
977 mode fp constants are big-endian word-wise, and little-endian byte-wise
978 within the words. For example, (double) 1.1 in big endian mode is
979 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
980 the byte sequence 99 99 f1 3f 9a 99 99 99.
982 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
985 md_atof (int type
, char * litP
, int * sizeP
)
988 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1020 return _("Unrecognized or unsupported floating point constant");
1023 t
= atof_ieee (input_line_pointer
, type
, words
);
1025 input_line_pointer
= t
;
1026 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1028 if (target_big_endian
)
1030 for (i
= 0; i
< prec
; i
++)
1032 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1033 litP
+= sizeof (LITTLENUM_TYPE
);
1038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1039 for (i
= prec
- 1; i
>= 0; i
--)
1041 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1042 litP
+= sizeof (LITTLENUM_TYPE
);
1045 /* For a 4 byte float the order of elements in `words' is 1 0.
1046 For an 8 byte float the order is 1 0 3 2. */
1047 for (i
= 0; i
< prec
; i
+= 2)
1049 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1050 sizeof (LITTLENUM_TYPE
));
1051 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1052 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1053 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1060 /* We handle all bad expressions here, so that we can report the faulty
1061 instruction in the error message. */
1063 md_operand (expressionS
* exp
)
1065 if (in_my_get_expression
)
1066 exp
->X_op
= O_illegal
;
1069 /* Immediate values. */
1071 /* Generic immediate-value read function for use in directives.
1072 Accepts anything that 'expression' can fold to a constant.
1073 *val receives the number. */
1076 immediate_for_directive (int *val
)
1079 exp
.X_op
= O_illegal
;
1081 if (is_immediate_prefix (*input_line_pointer
))
1083 input_line_pointer
++;
1087 if (exp
.X_op
!= O_constant
)
1089 as_bad (_("expected #constant"));
1090 ignore_rest_of_line ();
1093 *val
= exp
.X_add_number
;
1098 /* Register parsing. */
1100 /* Generic register parser. CCP points to what should be the
1101 beginning of a register name. If it is indeed a valid register
1102 name, advance CCP over it and return the reg_entry structure;
1103 otherwise return NULL. Does not issue diagnostics. */
1105 static struct reg_entry
*
1106 arm_reg_parse_multi (char **ccp
)
1110 struct reg_entry
*reg
;
1112 #ifdef REGISTER_PREFIX
1113 if (*start
!= REGISTER_PREFIX
)
1117 #ifdef OPTIONAL_REGISTER_PREFIX
1118 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1123 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1128 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1130 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1140 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1141 enum arm_reg_type type
)
1143 /* Alternative syntaxes are accepted for a few register classes. */
1150 /* Generic coprocessor register names are allowed for these. */
1151 if (reg
&& reg
->type
== REG_TYPE_CN
)
1156 /* For backward compatibility, a bare number is valid here. */
1158 unsigned long processor
= strtoul (start
, ccp
, 10);
1159 if (*ccp
!= start
&& processor
<= 15)
1163 case REG_TYPE_MMXWC
:
1164 /* WC includes WCG. ??? I'm not sure this is true for all
1165 instructions that take WC registers. */
1166 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1177 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1178 return value is the register number or FAIL. */
1181 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1184 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1187 /* Do not allow a scalar (reg+index) to parse as a register. */
1188 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1191 if (reg
&& reg
->type
== type
)
1194 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1201 /* Parse a Neon type specifier. *STR should point at the leading '.'
1202 character. Does no verification at this stage that the type fits the opcode
1209 Can all be legally parsed by this function.
1211 Fills in neon_type struct pointer with parsed information, and updates STR
1212 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1213 type, FAIL if not. */
1216 parse_neon_type (struct neon_type
*type
, char **str
)
1223 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1225 enum neon_el_type thistype
= NT_untyped
;
1226 unsigned thissize
= -1u;
1233 /* Just a size without an explicit type. */
1237 switch (TOLOWER (*ptr
))
1239 case 'i': thistype
= NT_integer
; break;
1240 case 'f': thistype
= NT_float
; break;
1241 case 'p': thistype
= NT_poly
; break;
1242 case 's': thistype
= NT_signed
; break;
1243 case 'u': thistype
= NT_unsigned
; break;
1245 thistype
= NT_float
;
1250 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1256 /* .f is an abbreviation for .f32. */
1257 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1262 thissize
= strtoul (ptr
, &ptr
, 10);
1264 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1267 as_bad (_("bad size %d in type specifier"), thissize
);
1275 type
->el
[type
->elems
].type
= thistype
;
1276 type
->el
[type
->elems
].size
= thissize
;
1281 /* Empty/missing type is not a successful parse. */
1282 if (type
->elems
== 0)
1290 /* Errors may be set multiple times during parsing or bit encoding
1291 (particularly in the Neon bits), but usually the earliest error which is set
1292 will be the most meaningful. Avoid overwriting it with later (cascading)
1293 errors by calling this function. */
1296 first_error (const char *err
)
1302 /* Parse a single type, e.g. ".s32", leading period included. */
1304 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1307 struct neon_type optype
;
1311 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1313 if (optype
.elems
== 1)
1314 *vectype
= optype
.el
[0];
1317 first_error (_("only one type should be specified for operand"));
1323 first_error (_("vector type expected"));
1335 /* Special meanings for indices (which have a range of 0-7), which will fit into
1338 #define NEON_ALL_LANES 15
1339 #define NEON_INTERLEAVE_LANES 14
1341 /* Parse either a register or a scalar, with an optional type. Return the
1342 register number, and optionally fill in the actual type of the register
1343 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1344 type/index information in *TYPEINFO. */
1347 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1348 enum arm_reg_type
*rtype
,
1349 struct neon_typed_alias
*typeinfo
)
1352 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1353 struct neon_typed_alias atype
;
1354 struct neon_type_el parsetype
;
1358 atype
.eltype
.type
= NT_invtype
;
1359 atype
.eltype
.size
= -1;
1361 /* Try alternate syntax for some types of register. Note these are mutually
1362 exclusive with the Neon syntax extensions. */
1365 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1373 /* Undo polymorphism when a set of register types may be accepted. */
1374 if ((type
== REG_TYPE_NDQ
1375 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1376 || (type
== REG_TYPE_VFSD
1377 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1378 || (type
== REG_TYPE_NSDQ
1379 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1380 || reg
->type
== REG_TYPE_NQ
))
1381 || (type
== REG_TYPE_MMXWC
1382 && (reg
->type
== REG_TYPE_MMXWCG
)))
1383 type
= (enum arm_reg_type
) reg
->type
;
1385 if (type
!= reg
->type
)
1391 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1393 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1395 first_error (_("can't redefine type for operand"));
1398 atype
.defined
|= NTA_HASTYPE
;
1399 atype
.eltype
= parsetype
;
1402 if (skip_past_char (&str
, '[') == SUCCESS
)
1404 if (type
!= REG_TYPE_VFD
)
1406 first_error (_("only D registers may be indexed"));
1410 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1412 first_error (_("can't change index for operand"));
1416 atype
.defined
|= NTA_HASINDEX
;
1418 if (skip_past_char (&str
, ']') == SUCCESS
)
1419 atype
.index
= NEON_ALL_LANES
;
1424 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1426 if (exp
.X_op
!= O_constant
)
1428 first_error (_("constant expression required"));
1432 if (skip_past_char (&str
, ']') == FAIL
)
1435 atype
.index
= exp
.X_add_number
;
1450 /* Like arm_reg_parse, but allow allow the following extra features:
1451 - If RTYPE is non-zero, return the (possibly restricted) type of the
1452 register (e.g. Neon double or quad reg when either has been requested).
1453 - If this is a Neon vector type with additional type information, fill
1454 in the struct pointed to by VECTYPE (if non-NULL).
1455 This function will fault on encountering a scalar. */
1458 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1459 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1461 struct neon_typed_alias atype
;
1463 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1468 /* Do not allow a scalar (reg+index) to parse as a register. */
1469 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1471 first_error (_("register operand expected, but got scalar"));
1476 *vectype
= atype
.eltype
;
1483 #define NEON_SCALAR_REG(X) ((X) >> 4)
1484 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1486 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1487 have enough information to be able to do a good job bounds-checking. So, we
1488 just do easy checks here, and do further checks later. */
1491 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1495 struct neon_typed_alias atype
;
1497 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1499 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1502 if (atype
.index
== NEON_ALL_LANES
)
1504 first_error (_("scalar must have an index"));
1507 else if (atype
.index
>= 64 / elsize
)
1509 first_error (_("scalar index out of range"));
1514 *type
= atype
.eltype
;
1518 return reg
* 16 + atype
.index
;
1521 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1524 parse_reg_list (char ** strp
)
1526 char * str
= * strp
;
1530 /* We come back here if we get ranges concatenated by '+' or '|'. */
1545 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1547 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1557 first_error (_("bad range in register list"));
1561 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1563 if (range
& (1 << i
))
1565 (_("Warning: duplicated register (r%d) in register list"),
1573 if (range
& (1 << reg
))
1574 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1576 else if (reg
<= cur_reg
)
1577 as_tsktsk (_("Warning: register range not in ascending order"));
1582 while (skip_past_comma (&str
) != FAIL
1583 || (in_range
= 1, *str
++ == '-'));
1588 first_error (_("missing `}'"));
1596 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1599 if (exp
.X_op
== O_constant
)
1601 if (exp
.X_add_number
1602 != (exp
.X_add_number
& 0x0000ffff))
1604 inst
.error
= _("invalid register mask");
1608 if ((range
& exp
.X_add_number
) != 0)
1610 int regno
= range
& exp
.X_add_number
;
1613 regno
= (1 << regno
) - 1;
1615 (_("Warning: duplicated register (r%d) in register list"),
1619 range
|= exp
.X_add_number
;
1623 if (inst
.reloc
.type
!= 0)
1625 inst
.error
= _("expression too complex");
1629 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1630 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1631 inst
.reloc
.pc_rel
= 0;
1635 if (*str
== '|' || *str
== '+')
1641 while (another_range
);
1647 /* Types of registers in a list. */
1656 /* Parse a VFP register list. If the string is invalid return FAIL.
1657 Otherwise return the number of registers, and set PBASE to the first
1658 register. Parses registers of type ETYPE.
1659 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1660 - Q registers can be used to specify pairs of D registers
1661 - { } can be omitted from around a singleton register list
1662 FIXME: This is not implemented, as it would require backtracking in
1665 This could be done (the meaning isn't really ambiguous), but doesn't
1666 fit in well with the current parsing framework.
1667 - 32 D registers may be used (also true for VFPv3).
1668 FIXME: Types are ignored in these register lists, which is probably a
1672 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1677 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1681 unsigned long mask
= 0;
1686 inst
.error
= _("expecting {");
1695 regtype
= REG_TYPE_VFS
;
1700 regtype
= REG_TYPE_VFD
;
1703 case REGLIST_NEON_D
:
1704 regtype
= REG_TYPE_NDQ
;
1708 if (etype
!= REGLIST_VFP_S
)
1710 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1711 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1715 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1718 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1725 base_reg
= max_regs
;
1729 int setmask
= 1, addregs
= 1;
1731 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1733 if (new_base
== FAIL
)
1735 first_error (_(reg_expected_msgs
[regtype
]));
1739 if (new_base
>= max_regs
)
1741 first_error (_("register out of range in list"));
1745 /* Note: a value of 2 * n is returned for the register Q<n>. */
1746 if (regtype
== REG_TYPE_NQ
)
1752 if (new_base
< base_reg
)
1753 base_reg
= new_base
;
1755 if (mask
& (setmask
<< new_base
))
1757 first_error (_("invalid register list"));
1761 if ((mask
>> new_base
) != 0 && ! warned
)
1763 as_tsktsk (_("register list not in ascending order"));
1767 mask
|= setmask
<< new_base
;
1770 if (*str
== '-') /* We have the start of a range expression */
1776 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1779 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1783 if (high_range
>= max_regs
)
1785 first_error (_("register out of range in list"));
1789 if (regtype
== REG_TYPE_NQ
)
1790 high_range
= high_range
+ 1;
1792 if (high_range
<= new_base
)
1794 inst
.error
= _("register range not in ascending order");
1798 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1800 if (mask
& (setmask
<< new_base
))
1802 inst
.error
= _("invalid register list");
1806 mask
|= setmask
<< new_base
;
1811 while (skip_past_comma (&str
) != FAIL
);
1815 /* Sanity check -- should have raised a parse error above. */
1816 if (count
== 0 || count
> max_regs
)
1821 /* Final test -- the registers must be consecutive. */
1823 for (i
= 0; i
< count
; i
++)
1825 if ((mask
& (1u << i
)) == 0)
1827 inst
.error
= _("non-contiguous register range");
1837 /* True if two alias types are the same. */
1840 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1848 if (a
->defined
!= b
->defined
)
1851 if ((a
->defined
& NTA_HASTYPE
) != 0
1852 && (a
->eltype
.type
!= b
->eltype
.type
1853 || a
->eltype
.size
!= b
->eltype
.size
))
1856 if ((a
->defined
& NTA_HASINDEX
) != 0
1857 && (a
->index
!= b
->index
))
1863 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1864 The base register is put in *PBASE.
1865 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1867 The register stride (minus one) is put in bit 4 of the return value.
1868 Bits [6:5] encode the list length (minus one).
1869 The type of the list elements is put in *ELTYPE, if non-NULL. */
1871 #define NEON_LANE(X) ((X) & 0xf)
1872 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1873 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1876 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1877 struct neon_type_el
*eltype
)
1884 int leading_brace
= 0;
1885 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1886 const char *const incr_error
= _("register stride must be 1 or 2");
1887 const char *const type_error
= _("mismatched element/structure types in list");
1888 struct neon_typed_alias firsttype
;
1890 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1895 struct neon_typed_alias atype
;
1896 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1900 first_error (_(reg_expected_msgs
[rtype
]));
1907 if (rtype
== REG_TYPE_NQ
)
1913 else if (reg_incr
== -1)
1915 reg_incr
= getreg
- base_reg
;
1916 if (reg_incr
< 1 || reg_incr
> 2)
1918 first_error (_(incr_error
));
1922 else if (getreg
!= base_reg
+ reg_incr
* count
)
1924 first_error (_(incr_error
));
1928 if (! neon_alias_types_same (&atype
, &firsttype
))
1930 first_error (_(type_error
));
1934 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1938 struct neon_typed_alias htype
;
1939 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1941 lane
= NEON_INTERLEAVE_LANES
;
1942 else if (lane
!= NEON_INTERLEAVE_LANES
)
1944 first_error (_(type_error
));
1949 else if (reg_incr
!= 1)
1951 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1955 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1958 first_error (_(reg_expected_msgs
[rtype
]));
1961 if (! neon_alias_types_same (&htype
, &firsttype
))
1963 first_error (_(type_error
));
1966 count
+= hireg
+ dregs
- getreg
;
1970 /* If we're using Q registers, we can't use [] or [n] syntax. */
1971 if (rtype
== REG_TYPE_NQ
)
1977 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1981 else if (lane
!= atype
.index
)
1983 first_error (_(type_error
));
1987 else if (lane
== -1)
1988 lane
= NEON_INTERLEAVE_LANES
;
1989 else if (lane
!= NEON_INTERLEAVE_LANES
)
1991 first_error (_(type_error
));
1996 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1998 /* No lane set by [x]. We must be interleaving structures. */
2000 lane
= NEON_INTERLEAVE_LANES
;
2003 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2004 || (count
> 1 && reg_incr
== -1))
2006 first_error (_("error parsing element/structure list"));
2010 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2012 first_error (_("expected }"));
2020 *eltype
= firsttype
.eltype
;
2025 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2028 /* Parse an explicit relocation suffix on an expression. This is
2029 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2030 arm_reloc_hsh contains no entries, so this function can only
2031 succeed if there is no () after the word. Returns -1 on error,
2032 BFD_RELOC_UNUSED if there wasn't any suffix. */
2034 parse_reloc (char **str
)
2036 struct reloc_entry
*r
;
2040 return BFD_RELOC_UNUSED
;
2045 while (*q
&& *q
!= ')' && *q
!= ',')
2050 if ((r
= (struct reloc_entry
*)
2051 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2058 /* Directives: register aliases. */
2060 static struct reg_entry
*
2061 insert_reg_alias (char *str
, int number
, int type
)
2063 struct reg_entry
*new_reg
;
2066 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2068 if (new_reg
->builtin
)
2069 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2071 /* Only warn about a redefinition if it's not defined as the
2073 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2074 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2079 name
= xstrdup (str
);
2080 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2082 new_reg
->name
= name
;
2083 new_reg
->number
= number
;
2084 new_reg
->type
= type
;
2085 new_reg
->builtin
= FALSE
;
2086 new_reg
->neon
= NULL
;
2088 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2095 insert_neon_reg_alias (char *str
, int number
, int type
,
2096 struct neon_typed_alias
*atype
)
2098 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2102 first_error (_("attempt to redefine typed alias"));
2108 reg
->neon
= (struct neon_typed_alias
*)
2109 xmalloc (sizeof (struct neon_typed_alias
));
2110 *reg
->neon
= *atype
;
2114 /* Look for the .req directive. This is of the form:
2116 new_register_name .req existing_register_name
2118 If we find one, or if it looks sufficiently like one that we want to
2119 handle any error here, return TRUE. Otherwise return FALSE. */
2122 create_register_alias (char * newname
, char *p
)
2124 struct reg_entry
*old
;
2125 char *oldname
, *nbuf
;
2128 /* The input scrubber ensures that whitespace after the mnemonic is
2129 collapsed to single spaces. */
2131 if (strncmp (oldname
, " .req ", 6) != 0)
2135 if (*oldname
== '\0')
2138 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2141 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2145 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2146 the desired alias name, and p points to its end. If not, then
2147 the desired alias name is in the global original_case_string. */
2148 #ifdef TC_CASE_SENSITIVE
2151 newname
= original_case_string
;
2152 nlen
= strlen (newname
);
2155 nbuf
= (char *) alloca (nlen
+ 1);
2156 memcpy (nbuf
, newname
, nlen
);
2159 /* Create aliases under the new name as stated; an all-lowercase
2160 version of the new name; and an all-uppercase version of the new
2162 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2164 for (p
= nbuf
; *p
; p
++)
2167 if (strncmp (nbuf
, newname
, nlen
))
2169 /* If this attempt to create an additional alias fails, do not bother
2170 trying to create the all-lower case alias. We will fail and issue
2171 a second, duplicate error message. This situation arises when the
2172 programmer does something like:
2175 The second .req creates the "Foo" alias but then fails to create
2176 the artificial FOO alias because it has already been created by the
2178 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2182 for (p
= nbuf
; *p
; p
++)
2185 if (strncmp (nbuf
, newname
, nlen
))
2186 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2192 /* Create a Neon typed/indexed register alias using directives, e.g.:
2197 These typed registers can be used instead of the types specified after the
2198 Neon mnemonic, so long as all operands given have types. Types can also be
2199 specified directly, e.g.:
2200 vadd d0.s32, d1.s32, d2.s32 */
2203 create_neon_reg_alias (char *newname
, char *p
)
2205 enum arm_reg_type basetype
;
2206 struct reg_entry
*basereg
;
2207 struct reg_entry mybasereg
;
2208 struct neon_type ntype
;
2209 struct neon_typed_alias typeinfo
;
2210 char *namebuf
, *nameend
;
2213 typeinfo
.defined
= 0;
2214 typeinfo
.eltype
.type
= NT_invtype
;
2215 typeinfo
.eltype
.size
= -1;
2216 typeinfo
.index
= -1;
2220 if (strncmp (p
, " .dn ", 5) == 0)
2221 basetype
= REG_TYPE_VFD
;
2222 else if (strncmp (p
, " .qn ", 5) == 0)
2223 basetype
= REG_TYPE_NQ
;
2232 basereg
= arm_reg_parse_multi (&p
);
2234 if (basereg
&& basereg
->type
!= basetype
)
2236 as_bad (_("bad type for register"));
2240 if (basereg
== NULL
)
2243 /* Try parsing as an integer. */
2244 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2245 if (exp
.X_op
!= O_constant
)
2247 as_bad (_("expression must be constant"));
2250 basereg
= &mybasereg
;
2251 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2257 typeinfo
= *basereg
->neon
;
2259 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2261 /* We got a type. */
2262 if (typeinfo
.defined
& NTA_HASTYPE
)
2264 as_bad (_("can't redefine the type of a register alias"));
2268 typeinfo
.defined
|= NTA_HASTYPE
;
2269 if (ntype
.elems
!= 1)
2271 as_bad (_("you must specify a single type only"));
2274 typeinfo
.eltype
= ntype
.el
[0];
2277 if (skip_past_char (&p
, '[') == SUCCESS
)
2280 /* We got a scalar index. */
2282 if (typeinfo
.defined
& NTA_HASINDEX
)
2284 as_bad (_("can't redefine the index of a scalar alias"));
2288 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2290 if (exp
.X_op
!= O_constant
)
2292 as_bad (_("scalar index must be constant"));
2296 typeinfo
.defined
|= NTA_HASINDEX
;
2297 typeinfo
.index
= exp
.X_add_number
;
2299 if (skip_past_char (&p
, ']') == FAIL
)
2301 as_bad (_("expecting ]"));
2306 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2307 the desired alias name, and p points to its end. If not, then
2308 the desired alias name is in the global original_case_string. */
2309 #ifdef TC_CASE_SENSITIVE
2310 namelen
= nameend
- newname
;
2312 newname
= original_case_string
;
2313 namelen
= strlen (newname
);
2316 namebuf
= (char *) alloca (namelen
+ 1);
2317 strncpy (namebuf
, newname
, namelen
);
2318 namebuf
[namelen
] = '\0';
2320 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2321 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2323 /* Insert name in all uppercase. */
2324 for (p
= namebuf
; *p
; p
++)
2327 if (strncmp (namebuf
, newname
, namelen
))
2328 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2329 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2331 /* Insert name in all lowercase. */
2332 for (p
= namebuf
; *p
; p
++)
2335 if (strncmp (namebuf
, newname
, namelen
))
2336 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2337 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2342 /* Should never be called, as .req goes between the alias and the
2343 register name, not at the beginning of the line. */
2346 s_req (int a ATTRIBUTE_UNUSED
)
2348 as_bad (_("invalid syntax for .req directive"));
2352 s_dn (int a ATTRIBUTE_UNUSED
)
2354 as_bad (_("invalid syntax for .dn directive"));
2358 s_qn (int a ATTRIBUTE_UNUSED
)
2360 as_bad (_("invalid syntax for .qn directive"));
2363 /* The .unreq directive deletes an alias which was previously defined
2364 by .req. For example:
2370 s_unreq (int a ATTRIBUTE_UNUSED
)
2375 name
= input_line_pointer
;
2377 while (*input_line_pointer
!= 0
2378 && *input_line_pointer
!= ' '
2379 && *input_line_pointer
!= '\n')
2380 ++input_line_pointer
;
2382 saved_char
= *input_line_pointer
;
2383 *input_line_pointer
= 0;
2386 as_bad (_("invalid syntax for .unreq directive"));
2389 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2393 as_bad (_("unknown register alias '%s'"), name
);
2394 else if (reg
->builtin
)
2395 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2402 hash_delete (arm_reg_hsh
, name
, FALSE
);
2403 free ((char *) reg
->name
);
2408 /* Also locate the all upper case and all lower case versions.
2409 Do not complain if we cannot find one or the other as it
2410 was probably deleted above. */
2412 nbuf
= strdup (name
);
2413 for (p
= nbuf
; *p
; p
++)
2415 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2418 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2419 free ((char *) reg
->name
);
2425 for (p
= nbuf
; *p
; p
++)
2427 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2430 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2431 free ((char *) reg
->name
);
2441 *input_line_pointer
= saved_char
;
2442 demand_empty_rest_of_line ();
2445 /* Directives: Instruction set selection. */
2448 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2449 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2450 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2451 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2453 /* Create a new mapping symbol for the transition to STATE. */
2456 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2459 const char * symname
;
2466 type
= BSF_NO_FLAGS
;
2470 type
= BSF_NO_FLAGS
;
2474 type
= BSF_NO_FLAGS
;
2480 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2481 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2486 THUMB_SET_FUNC (symbolP
, 0);
2487 ARM_SET_THUMB (symbolP
, 0);
2488 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2492 THUMB_SET_FUNC (symbolP
, 1);
2493 ARM_SET_THUMB (symbolP
, 1);
2494 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2502 /* Save the mapping symbols for future reference. Also check that
2503 we do not place two mapping symbols at the same offset within a
2504 frag. We'll handle overlap between frags in
2505 check_mapping_symbols.
2507 If .fill or other data filling directive generates zero sized data,
2508 the mapping symbol for the following code will have the same value
2509 as the one generated for the data filling directive. In this case,
2510 we replace the old symbol with the new one at the same address. */
2513 if (frag
->tc_frag_data
.first_map
!= NULL
)
2515 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2516 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2518 frag
->tc_frag_data
.first_map
= symbolP
;
2520 if (frag
->tc_frag_data
.last_map
!= NULL
)
2522 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2523 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2524 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2526 frag
->tc_frag_data
.last_map
= symbolP
;
2529 /* We must sometimes convert a region marked as code to data during
2530 code alignment, if an odd number of bytes have to be padded. The
2531 code mapping symbol is pushed to an aligned address. */
2534 insert_data_mapping_symbol (enum mstate state
,
2535 valueT value
, fragS
*frag
, offsetT bytes
)
2537 /* If there was already a mapping symbol, remove it. */
2538 if (frag
->tc_frag_data
.last_map
!= NULL
2539 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2541 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2545 know (frag
->tc_frag_data
.first_map
== symp
);
2546 frag
->tc_frag_data
.first_map
= NULL
;
2548 frag
->tc_frag_data
.last_map
= NULL
;
2549 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2552 make_mapping_symbol (MAP_DATA
, value
, frag
);
2553 make_mapping_symbol (state
, value
+ bytes
, frag
);
2556 static void mapping_state_2 (enum mstate state
, int max_chars
);
2558 /* Set the mapping state to STATE. Only call this when about to
2559 emit some STATE bytes to the file. */
2562 mapping_state (enum mstate state
)
2564 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2566 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2568 if (mapstate
== state
)
2569 /* The mapping symbol has already been emitted.
2570 There is nothing else to do. */
2572 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2573 /* This case will be evaluated later in the next else. */
2575 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2576 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2578 /* Only add the symbol if the offset is > 0:
2579 if we're at the first frag, check it's size > 0;
2580 if we're not at the first frag, then for sure
2581 the offset is > 0. */
2582 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2583 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2586 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2589 mapping_state_2 (state
, 0);
2593 /* Same as mapping_state, but MAX_CHARS bytes have already been
2594 allocated. Put the mapping symbol that far back. */
2597 mapping_state_2 (enum mstate state
, int max_chars
)
2599 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2601 if (!SEG_NORMAL (now_seg
))
2604 if (mapstate
== state
)
2605 /* The mapping symbol has already been emitted.
2606 There is nothing else to do. */
2609 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2610 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2613 #define mapping_state(x) ((void)0)
2614 #define mapping_state_2(x, y) ((void)0)
2617 /* Find the real, Thumb encoded start of a Thumb function. */
2621 find_real_start (symbolS
* symbolP
)
2624 const char * name
= S_GET_NAME (symbolP
);
2625 symbolS
* new_target
;
2627 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2628 #define STUB_NAME ".real_start_of"
2633 /* The compiler may generate BL instructions to local labels because
2634 it needs to perform a branch to a far away location. These labels
2635 do not have a corresponding ".real_start_of" label. We check
2636 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2637 the ".real_start_of" convention for nonlocal branches. */
2638 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2641 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2642 new_target
= symbol_find (real_start
);
2644 if (new_target
== NULL
)
2646 as_warn (_("Failed to find real start of function: %s\n"), name
);
2647 new_target
= symbolP
;
2655 opcode_select (int width
)
2662 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2663 as_bad (_("selected processor does not support THUMB opcodes"));
2666 /* No need to force the alignment, since we will have been
2667 coming from ARM mode, which is word-aligned. */
2668 record_alignment (now_seg
, 1);
2675 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2676 as_bad (_("selected processor does not support ARM opcodes"));
2681 frag_align (2, 0, 0);
2683 record_alignment (now_seg
, 1);
2688 as_bad (_("invalid instruction size selected (%d)"), width
);
2693 s_arm (int ignore ATTRIBUTE_UNUSED
)
2696 demand_empty_rest_of_line ();
2700 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2703 demand_empty_rest_of_line ();
2707 s_code (int unused ATTRIBUTE_UNUSED
)
2711 temp
= get_absolute_expression ();
2716 opcode_select (temp
);
2720 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2725 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2727 /* If we are not already in thumb mode go into it, EVEN if
2728 the target processor does not support thumb instructions.
2729 This is used by gcc/config/arm/lib1funcs.asm for example
2730 to compile interworking support functions even if the
2731 target processor should not support interworking. */
2735 record_alignment (now_seg
, 1);
2738 demand_empty_rest_of_line ();
2742 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2746 /* The following label is the name/address of the start of a Thumb function.
2747 We need to know this for the interworking support. */
2748 label_is_thumb_function_name
= TRUE
;
2751 /* Perform a .set directive, but also mark the alias as
2752 being a thumb function. */
2755 s_thumb_set (int equiv
)
2757 /* XXX the following is a duplicate of the code for s_set() in read.c
2758 We cannot just call that code as we need to get at the symbol that
2765 /* Especial apologies for the random logic:
2766 This just grew, and could be parsed much more simply!
2768 name
= input_line_pointer
;
2769 delim
= get_symbol_end ();
2770 end_name
= input_line_pointer
;
2773 if (*input_line_pointer
!= ',')
2776 as_bad (_("expected comma after name \"%s\""), name
);
2778 ignore_rest_of_line ();
2782 input_line_pointer
++;
2785 if (name
[0] == '.' && name
[1] == '\0')
2787 /* XXX - this should not happen to .thumb_set. */
2791 if ((symbolP
= symbol_find (name
)) == NULL
2792 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2795 /* When doing symbol listings, play games with dummy fragments living
2796 outside the normal fragment chain to record the file and line info
2798 if (listing
& LISTING_SYMBOLS
)
2800 extern struct list_info_struct
* listing_tail
;
2801 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2803 memset (dummy_frag
, 0, sizeof (fragS
));
2804 dummy_frag
->fr_type
= rs_fill
;
2805 dummy_frag
->line
= listing_tail
;
2806 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2807 dummy_frag
->fr_symbol
= symbolP
;
2811 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2814 /* "set" symbols are local unless otherwise specified. */
2815 SF_SET_LOCAL (symbolP
);
2816 #endif /* OBJ_COFF */
2817 } /* Make a new symbol. */
2819 symbol_table_insert (symbolP
);
2824 && S_IS_DEFINED (symbolP
)
2825 && S_GET_SEGMENT (symbolP
) != reg_section
)
2826 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2828 pseudo_set (symbolP
);
2830 demand_empty_rest_of_line ();
2832 /* XXX Now we come to the Thumb specific bit of code. */
2834 THUMB_SET_FUNC (symbolP
, 1);
2835 ARM_SET_THUMB (symbolP
, 1);
2836 #if defined OBJ_ELF || defined OBJ_COFF
2837 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2841 /* Directives: Mode selection. */
2843 /* .syntax [unified|divided] - choose the new unified syntax
2844 (same for Arm and Thumb encoding, modulo slight differences in what
2845 can be represented) or the old divergent syntax for each mode. */
2847 s_syntax (int unused ATTRIBUTE_UNUSED
)
2851 name
= input_line_pointer
;
2852 delim
= get_symbol_end ();
2854 if (!strcasecmp (name
, "unified"))
2855 unified_syntax
= TRUE
;
2856 else if (!strcasecmp (name
, "divided"))
2857 unified_syntax
= FALSE
;
2860 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2863 *input_line_pointer
= delim
;
2864 demand_empty_rest_of_line ();
2867 /* Directives: sectioning and alignment. */
2869 /* Same as s_align_ptwo but align 0 => align 2. */
2872 s_align (int unused ATTRIBUTE_UNUSED
)
2877 long max_alignment
= 15;
2879 temp
= get_absolute_expression ();
2880 if (temp
> max_alignment
)
2881 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2884 as_bad (_("alignment negative. 0 assumed."));
2888 if (*input_line_pointer
== ',')
2890 input_line_pointer
++;
2891 temp_fill
= get_absolute_expression ();
2903 /* Only make a frag if we HAVE to. */
2904 if (temp
&& !need_pass_2
)
2906 if (!fill_p
&& subseg_text_p (now_seg
))
2907 frag_align_code (temp
, 0);
2909 frag_align (temp
, (int) temp_fill
, 0);
2911 demand_empty_rest_of_line ();
2913 record_alignment (now_seg
, temp
);
2917 s_bss (int ignore ATTRIBUTE_UNUSED
)
2919 /* We don't support putting frags in the BSS segment, we fake it by
2920 marking in_bss, then looking at s_skip for clues. */
2921 subseg_set (bss_section
, 0);
2922 demand_empty_rest_of_line ();
2924 #ifdef md_elf_section_change_hook
2925 md_elf_section_change_hook ();
2930 s_even (int ignore ATTRIBUTE_UNUSED
)
2932 /* Never make frag if expect extra pass. */
2934 frag_align (1, 0, 0);
2936 record_alignment (now_seg
, 1);
2938 demand_empty_rest_of_line ();
2941 /* Directives: Literal pools. */
2943 static literal_pool
*
2944 find_literal_pool (void)
2946 literal_pool
* pool
;
2948 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2950 if (pool
->section
== now_seg
2951 && pool
->sub_section
== now_subseg
)
2958 static literal_pool
*
2959 find_or_make_literal_pool (void)
2961 /* Next literal pool ID number. */
2962 static unsigned int latest_pool_num
= 1;
2963 literal_pool
* pool
;
2965 pool
= find_literal_pool ();
2969 /* Create a new pool. */
2970 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2974 pool
->next_free_entry
= 0;
2975 pool
->section
= now_seg
;
2976 pool
->sub_section
= now_subseg
;
2977 pool
->next
= list_of_pools
;
2978 pool
->symbol
= NULL
;
2980 /* Add it to the list. */
2981 list_of_pools
= pool
;
2984 /* New pools, and emptied pools, will have a NULL symbol. */
2985 if (pool
->symbol
== NULL
)
2987 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2988 (valueT
) 0, &zero_address_frag
);
2989 pool
->id
= latest_pool_num
++;
2996 /* Add the literal in the global 'inst'
2997 structure to the relevant literal pool. */
3000 add_to_lit_pool (void)
3002 literal_pool
* pool
;
3005 pool
= find_or_make_literal_pool ();
3007 /* Check if this literal value is already in the pool. */
3008 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3010 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3011 && (inst
.reloc
.exp
.X_op
== O_constant
)
3012 && (pool
->literals
[entry
].X_add_number
3013 == inst
.reloc
.exp
.X_add_number
)
3014 && (pool
->literals
[entry
].X_unsigned
3015 == inst
.reloc
.exp
.X_unsigned
))
3018 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3019 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3020 && (pool
->literals
[entry
].X_add_number
3021 == inst
.reloc
.exp
.X_add_number
)
3022 && (pool
->literals
[entry
].X_add_symbol
3023 == inst
.reloc
.exp
.X_add_symbol
)
3024 && (pool
->literals
[entry
].X_op_symbol
3025 == inst
.reloc
.exp
.X_op_symbol
))
3029 /* Do we need to create a new entry? */
3030 if (entry
== pool
->next_free_entry
)
3032 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3034 inst
.error
= _("literal pool overflow");
3038 pool
->literals
[entry
] = inst
.reloc
.exp
;
3039 pool
->next_free_entry
+= 1;
3042 inst
.reloc
.exp
.X_op
= O_symbol
;
3043 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3044 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3049 /* Can't use symbol_new here, so have to create a symbol and then at
3050 a later date assign it a value. Thats what these functions do. */
3053 symbol_locate (symbolS
* symbolP
,
3054 const char * name
, /* It is copied, the caller can modify. */
3055 segT segment
, /* Segment identifier (SEG_<something>). */
3056 valueT valu
, /* Symbol value. */
3057 fragS
* frag
) /* Associated fragment. */
3059 unsigned int name_length
;
3060 char * preserved_copy_of_name
;
3062 name_length
= strlen (name
) + 1; /* +1 for \0. */
3063 obstack_grow (¬es
, name
, name_length
);
3064 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3066 #ifdef tc_canonicalize_symbol_name
3067 preserved_copy_of_name
=
3068 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3071 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3073 S_SET_SEGMENT (symbolP
, segment
);
3074 S_SET_VALUE (symbolP
, valu
);
3075 symbol_clear_list_pointers (symbolP
);
3077 symbol_set_frag (symbolP
, frag
);
3079 /* Link to end of symbol chain. */
3081 extern int symbol_table_frozen
;
3083 if (symbol_table_frozen
)
3087 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3089 obj_symbol_new_hook (symbolP
);
3091 #ifdef tc_symbol_new_hook
3092 tc_symbol_new_hook (symbolP
);
3096 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3097 #endif /* DEBUG_SYMS */
3102 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3105 literal_pool
* pool
;
3108 pool
= find_literal_pool ();
3110 || pool
->symbol
== NULL
3111 || pool
->next_free_entry
== 0)
3114 mapping_state (MAP_DATA
);
3116 /* Align pool as you have word accesses.
3117 Only make a frag if we have to. */
3119 frag_align (2, 0, 0);
3121 record_alignment (now_seg
, 2);
3123 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3125 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3126 (valueT
) frag_now_fix (), frag_now
);
3127 symbol_table_insert (pool
->symbol
);
3129 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3131 #if defined OBJ_COFF || defined OBJ_ELF
3132 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3135 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3136 /* First output the expression in the instruction to the pool. */
3137 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3139 /* Mark the pool as empty. */
3140 pool
->next_free_entry
= 0;
3141 pool
->symbol
= NULL
;
3145 /* Forward declarations for functions below, in the MD interface
3147 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3148 static valueT
create_unwind_entry (int);
3149 static void start_unwind_section (const segT
, int);
3150 static void add_unwind_opcode (valueT
, int);
3151 static void flush_pending_unwind (void);
3153 /* Directives: Data. */
3156 s_arm_elf_cons (int nbytes
)
3160 #ifdef md_flush_pending_output
3161 md_flush_pending_output ();
3164 if (is_it_end_of_statement ())
3166 demand_empty_rest_of_line ();
3170 #ifdef md_cons_align
3171 md_cons_align (nbytes
);
3174 mapping_state (MAP_DATA
);
3178 char *base
= input_line_pointer
;
3182 if (exp
.X_op
!= O_symbol
)
3183 emit_expr (&exp
, (unsigned int) nbytes
);
3186 char *before_reloc
= input_line_pointer
;
3187 reloc
= parse_reloc (&input_line_pointer
);
3190 as_bad (_("unrecognized relocation suffix"));
3191 ignore_rest_of_line ();
3194 else if (reloc
== BFD_RELOC_UNUSED
)
3195 emit_expr (&exp
, (unsigned int) nbytes
);
3198 reloc_howto_type
*howto
= (reloc_howto_type
*)
3199 bfd_reloc_type_lookup (stdoutput
,
3200 (bfd_reloc_code_real_type
) reloc
);
3201 int size
= bfd_get_reloc_size (howto
);
3203 if (reloc
== BFD_RELOC_ARM_PLT32
)
3205 as_bad (_("(plt) is only valid on branch targets"));
3206 reloc
= BFD_RELOC_UNUSED
;
3211 as_bad (_("%s relocations do not fit in %d bytes"),
3212 howto
->name
, nbytes
);
3215 /* We've parsed an expression stopping at O_symbol.
3216 But there may be more expression left now that we
3217 have parsed the relocation marker. Parse it again.
3218 XXX Surely there is a cleaner way to do this. */
3219 char *p
= input_line_pointer
;
3221 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3222 memcpy (save_buf
, base
, input_line_pointer
- base
);
3223 memmove (base
+ (input_line_pointer
- before_reloc
),
3224 base
, before_reloc
- base
);
3226 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3228 memcpy (base
, save_buf
, p
- base
);
3230 offset
= nbytes
- size
;
3231 p
= frag_more ((int) nbytes
);
3232 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3233 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3238 while (*input_line_pointer
++ == ',');
3240 /* Put terminator back into stream. */
3241 input_line_pointer
--;
3242 demand_empty_rest_of_line ();
3245 /* Emit an expression containing a 32-bit thumb instruction.
3246 Implementation based on put_thumb32_insn. */
3249 emit_thumb32_expr (expressionS
* exp
)
3251 expressionS exp_high
= *exp
;
3253 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3254 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3255 exp
->X_add_number
&= 0xffff;
3256 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3259 /* Guess the instruction size based on the opcode. */
3262 thumb_insn_size (int opcode
)
3264 if ((unsigned int) opcode
< 0xe800u
)
3266 else if ((unsigned int) opcode
>= 0xe8000000u
)
3273 emit_insn (expressionS
*exp
, int nbytes
)
3277 if (exp
->X_op
== O_constant
)
3282 size
= thumb_insn_size (exp
->X_add_number
);
3286 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3288 as_bad (_(".inst.n operand too big. "\
3289 "Use .inst.w instead"));
3294 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3295 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3297 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3299 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3300 emit_thumb32_expr (exp
);
3302 emit_expr (exp
, (unsigned int) size
);
3304 it_fsm_post_encode ();
3308 as_bad (_("cannot determine Thumb instruction size. " \
3309 "Use .inst.n/.inst.w instead"));
3312 as_bad (_("constant expression required"));
3317 /* Like s_arm_elf_cons but do not use md_cons_align and
3318 set the mapping state to MAP_ARM/MAP_THUMB. */
3321 s_arm_elf_inst (int nbytes
)
3323 if (is_it_end_of_statement ())
3325 demand_empty_rest_of_line ();
3329 /* Calling mapping_state () here will not change ARM/THUMB,
3330 but will ensure not to be in DATA state. */
3333 mapping_state (MAP_THUMB
);
3338 as_bad (_("width suffixes are invalid in ARM mode"));
3339 ignore_rest_of_line ();
3345 mapping_state (MAP_ARM
);
3354 if (! emit_insn (& exp
, nbytes
))
3356 ignore_rest_of_line ();
3360 while (*input_line_pointer
++ == ',');
3362 /* Put terminator back into stream. */
3363 input_line_pointer
--;
3364 demand_empty_rest_of_line ();
3367 /* Parse a .rel31 directive. */
3370 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3377 if (*input_line_pointer
== '1')
3378 highbit
= 0x80000000;
3379 else if (*input_line_pointer
!= '0')
3380 as_bad (_("expected 0 or 1"));
3382 input_line_pointer
++;
3383 if (*input_line_pointer
!= ',')
3384 as_bad (_("missing comma"));
3385 input_line_pointer
++;
3387 #ifdef md_flush_pending_output
3388 md_flush_pending_output ();
3391 #ifdef md_cons_align
3395 mapping_state (MAP_DATA
);
3400 md_number_to_chars (p
, highbit
, 4);
3401 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3402 BFD_RELOC_ARM_PREL31
);
3404 demand_empty_rest_of_line ();
3407 /* Directives: AEABI stack-unwind tables. */
3409 /* Parse an unwind_fnstart directive. Simply records the current location. */
3412 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3414 demand_empty_rest_of_line ();
3415 if (unwind
.proc_start
)
3417 as_bad (_("duplicate .fnstart directive"));
3421 /* Mark the start of the function. */
3422 unwind
.proc_start
= expr_build_dot ();
3424 /* Reset the rest of the unwind info. */
3425 unwind
.opcode_count
= 0;
3426 unwind
.table_entry
= NULL
;
3427 unwind
.personality_routine
= NULL
;
3428 unwind
.personality_index
= -1;
3429 unwind
.frame_size
= 0;
3430 unwind
.fp_offset
= 0;
3431 unwind
.fp_reg
= REG_SP
;
3433 unwind
.sp_restored
= 0;
3437 /* Parse a handlerdata directive. Creates the exception handling table entry
3438 for the function. */
3441 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3443 demand_empty_rest_of_line ();
3444 if (!unwind
.proc_start
)
3445 as_bad (MISSING_FNSTART
);
3447 if (unwind
.table_entry
)
3448 as_bad (_("duplicate .handlerdata directive"));
3450 create_unwind_entry (1);
3453 /* Parse an unwind_fnend directive. Generates the index table entry. */
3456 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3461 unsigned int marked_pr_dependency
;
3463 demand_empty_rest_of_line ();
3465 if (!unwind
.proc_start
)
3467 as_bad (_(".fnend directive without .fnstart"));
3471 /* Add eh table entry. */
3472 if (unwind
.table_entry
== NULL
)
3473 val
= create_unwind_entry (0);
3477 /* Add index table entry. This is two words. */
3478 start_unwind_section (unwind
.saved_seg
, 1);
3479 frag_align (2, 0, 0);
3480 record_alignment (now_seg
, 2);
3482 ptr
= frag_more (8);
3483 where
= frag_now_fix () - 8;
3485 /* Self relative offset of the function start. */
3486 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3487 BFD_RELOC_ARM_PREL31
);
3489 /* Indicate dependency on EHABI-defined personality routines to the
3490 linker, if it hasn't been done already. */
3491 marked_pr_dependency
3492 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3493 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3494 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3496 static const char *const name
[] =
3498 "__aeabi_unwind_cpp_pr0",
3499 "__aeabi_unwind_cpp_pr1",
3500 "__aeabi_unwind_cpp_pr2"
3502 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3503 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3504 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3505 |= 1 << unwind
.personality_index
;
3509 /* Inline exception table entry. */
3510 md_number_to_chars (ptr
+ 4, val
, 4);
3512 /* Self relative offset of the table entry. */
3513 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3514 BFD_RELOC_ARM_PREL31
);
3516 /* Restore the original section. */
3517 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3519 unwind
.proc_start
= NULL
;
3523 /* Parse an unwind_cantunwind directive. */
3526 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3528 demand_empty_rest_of_line ();
3529 if (!unwind
.proc_start
)
3530 as_bad (MISSING_FNSTART
);
3532 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3533 as_bad (_("personality routine specified for cantunwind frame"));
3535 unwind
.personality_index
= -2;
3539 /* Parse a personalityindex directive. */
3542 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3546 if (!unwind
.proc_start
)
3547 as_bad (MISSING_FNSTART
);
3549 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3550 as_bad (_("duplicate .personalityindex directive"));
3554 if (exp
.X_op
!= O_constant
3555 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3557 as_bad (_("bad personality routine number"));
3558 ignore_rest_of_line ();
3562 unwind
.personality_index
= exp
.X_add_number
;
3564 demand_empty_rest_of_line ();
3568 /* Parse a personality directive. */
3571 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3575 if (!unwind
.proc_start
)
3576 as_bad (MISSING_FNSTART
);
3578 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3579 as_bad (_("duplicate .personality directive"));
3581 name
= input_line_pointer
;
3582 c
= get_symbol_end ();
3583 p
= input_line_pointer
;
3584 unwind
.personality_routine
= symbol_find_or_make (name
);
3586 demand_empty_rest_of_line ();
3590 /* Parse a directive saving core registers. */
3593 s_arm_unwind_save_core (void)
3599 range
= parse_reg_list (&input_line_pointer
);
3602 as_bad (_("expected register list"));
3603 ignore_rest_of_line ();
3607 demand_empty_rest_of_line ();
3609 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3610 into .unwind_save {..., sp...}. We aren't bothered about the value of
3611 ip because it is clobbered by calls. */
3612 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3613 && (range
& 0x3000) == 0x1000)
3615 unwind
.opcode_count
--;
3616 unwind
.sp_restored
= 0;
3617 range
= (range
| 0x2000) & ~0x1000;
3618 unwind
.pending_offset
= 0;
3624 /* See if we can use the short opcodes. These pop a block of up to 8
3625 registers starting with r4, plus maybe r14. */
3626 for (n
= 0; n
< 8; n
++)
3628 /* Break at the first non-saved register. */
3629 if ((range
& (1 << (n
+ 4))) == 0)
3632 /* See if there are any other bits set. */
3633 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3635 /* Use the long form. */
3636 op
= 0x8000 | ((range
>> 4) & 0xfff);
3637 add_unwind_opcode (op
, 2);
3641 /* Use the short form. */
3643 op
= 0xa8; /* Pop r14. */
3645 op
= 0xa0; /* Do not pop r14. */
3647 add_unwind_opcode (op
, 1);
3654 op
= 0xb100 | (range
& 0xf);
3655 add_unwind_opcode (op
, 2);
3658 /* Record the number of bytes pushed. */
3659 for (n
= 0; n
< 16; n
++)
3661 if (range
& (1 << n
))
3662 unwind
.frame_size
+= 4;
3667 /* Parse a directive saving FPA registers. */
3670 s_arm_unwind_save_fpa (int reg
)
3676 /* Get Number of registers to transfer. */
3677 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3680 exp
.X_op
= O_illegal
;
3682 if (exp
.X_op
!= O_constant
)
3684 as_bad (_("expected , <constant>"));
3685 ignore_rest_of_line ();
3689 num_regs
= exp
.X_add_number
;
3691 if (num_regs
< 1 || num_regs
> 4)
3693 as_bad (_("number of registers must be in the range [1:4]"));
3694 ignore_rest_of_line ();
3698 demand_empty_rest_of_line ();
3703 op
= 0xb4 | (num_regs
- 1);
3704 add_unwind_opcode (op
, 1);
3709 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3710 add_unwind_opcode (op
, 2);
3712 unwind
.frame_size
+= num_regs
* 12;
3716 /* Parse a directive saving VFP registers for ARMv6 and above. */
3719 s_arm_unwind_save_vfp_armv6 (void)
3724 int num_vfpv3_regs
= 0;
3725 int num_regs_below_16
;
3727 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3730 as_bad (_("expected register list"));
3731 ignore_rest_of_line ();
3735 demand_empty_rest_of_line ();
3737 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3738 than FSTMX/FLDMX-style ones). */
3740 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3742 num_vfpv3_regs
= count
;
3743 else if (start
+ count
> 16)
3744 num_vfpv3_regs
= start
+ count
- 16;
3746 if (num_vfpv3_regs
> 0)
3748 int start_offset
= start
> 16 ? start
- 16 : 0;
3749 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3750 add_unwind_opcode (op
, 2);
3753 /* Generate opcode for registers numbered in the range 0 .. 15. */
3754 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3755 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3756 if (num_regs_below_16
> 0)
3758 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3759 add_unwind_opcode (op
, 2);
3762 unwind
.frame_size
+= count
* 8;
3766 /* Parse a directive saving VFP registers for pre-ARMv6. */
3769 s_arm_unwind_save_vfp (void)
3775 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3778 as_bad (_("expected register list"));
3779 ignore_rest_of_line ();
3783 demand_empty_rest_of_line ();
3788 op
= 0xb8 | (count
- 1);
3789 add_unwind_opcode (op
, 1);
3794 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3795 add_unwind_opcode (op
, 2);
3797 unwind
.frame_size
+= count
* 8 + 4;
3801 /* Parse a directive saving iWMMXt data registers. */
3804 s_arm_unwind_save_mmxwr (void)
3812 if (*input_line_pointer
== '{')
3813 input_line_pointer
++;
3817 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3821 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3826 as_tsktsk (_("register list not in ascending order"));
3829 if (*input_line_pointer
== '-')
3831 input_line_pointer
++;
3832 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3835 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3838 else if (reg
>= hi_reg
)
3840 as_bad (_("bad register range"));
3843 for (; reg
< hi_reg
; reg
++)
3847 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3849 if (*input_line_pointer
== '}')
3850 input_line_pointer
++;
3852 demand_empty_rest_of_line ();
3854 /* Generate any deferred opcodes because we're going to be looking at
3856 flush_pending_unwind ();
3858 for (i
= 0; i
< 16; i
++)
3860 if (mask
& (1 << i
))
3861 unwind
.frame_size
+= 8;
3864 /* Attempt to combine with a previous opcode. We do this because gcc
3865 likes to output separate unwind directives for a single block of
3867 if (unwind
.opcode_count
> 0)
3869 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3870 if ((i
& 0xf8) == 0xc0)
3873 /* Only merge if the blocks are contiguous. */
3876 if ((mask
& 0xfe00) == (1 << 9))
3878 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3879 unwind
.opcode_count
--;
3882 else if (i
== 6 && unwind
.opcode_count
>= 2)
3884 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3888 op
= 0xffff << (reg
- 1);
3890 && ((mask
& op
) == (1u << (reg
- 1))))
3892 op
= (1 << (reg
+ i
+ 1)) - 1;
3893 op
&= ~((1 << reg
) - 1);
3895 unwind
.opcode_count
-= 2;
3902 /* We want to generate opcodes in the order the registers have been
3903 saved, ie. descending order. */
3904 for (reg
= 15; reg
>= -1; reg
--)
3906 /* Save registers in blocks. */
3908 || !(mask
& (1 << reg
)))
3910 /* We found an unsaved reg. Generate opcodes to save the
3917 op
= 0xc0 | (hi_reg
- 10);
3918 add_unwind_opcode (op
, 1);
3923 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3924 add_unwind_opcode (op
, 2);
3933 ignore_rest_of_line ();
3937 s_arm_unwind_save_mmxwcg (void)
3944 if (*input_line_pointer
== '{')
3945 input_line_pointer
++;
3949 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3953 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3959 as_tsktsk (_("register list not in ascending order"));
3962 if (*input_line_pointer
== '-')
3964 input_line_pointer
++;
3965 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3968 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3971 else if (reg
>= hi_reg
)
3973 as_bad (_("bad register range"));
3976 for (; reg
< hi_reg
; reg
++)
3980 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3982 if (*input_line_pointer
== '}')
3983 input_line_pointer
++;
3985 demand_empty_rest_of_line ();
3987 /* Generate any deferred opcodes because we're going to be looking at
3989 flush_pending_unwind ();
3991 for (reg
= 0; reg
< 16; reg
++)
3993 if (mask
& (1 << reg
))
3994 unwind
.frame_size
+= 4;
3997 add_unwind_opcode (op
, 2);
4000 ignore_rest_of_line ();
4004 /* Parse an unwind_save directive.
4005 If the argument is non-zero, this is a .vsave directive. */
4008 s_arm_unwind_save (int arch_v6
)
4011 struct reg_entry
*reg
;
4012 bfd_boolean had_brace
= FALSE
;
4014 if (!unwind
.proc_start
)
4015 as_bad (MISSING_FNSTART
);
4017 /* Figure out what sort of save we have. */
4018 peek
= input_line_pointer
;
4026 reg
= arm_reg_parse_multi (&peek
);
4030 as_bad (_("register expected"));
4031 ignore_rest_of_line ();
4040 as_bad (_("FPA .unwind_save does not take a register list"));
4041 ignore_rest_of_line ();
4044 input_line_pointer
= peek
;
4045 s_arm_unwind_save_fpa (reg
->number
);
4048 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4051 s_arm_unwind_save_vfp_armv6 ();
4053 s_arm_unwind_save_vfp ();
4055 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4056 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4059 as_bad (_(".unwind_save does not support this kind of register"));
4060 ignore_rest_of_line ();
4065 /* Parse an unwind_movsp directive. */
4068 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4074 if (!unwind
.proc_start
)
4075 as_bad (MISSING_FNSTART
);
4077 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4080 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4081 ignore_rest_of_line ();
4085 /* Optional constant. */
4086 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4088 if (immediate_for_directive (&offset
) == FAIL
)
4094 demand_empty_rest_of_line ();
4096 if (reg
== REG_SP
|| reg
== REG_PC
)
4098 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4102 if (unwind
.fp_reg
!= REG_SP
)
4103 as_bad (_("unexpected .unwind_movsp directive"));
4105 /* Generate opcode to restore the value. */
4107 add_unwind_opcode (op
, 1);
4109 /* Record the information for later. */
4110 unwind
.fp_reg
= reg
;
4111 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4112 unwind
.sp_restored
= 1;
4115 /* Parse an unwind_pad directive. */
4118 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4122 if (!unwind
.proc_start
)
4123 as_bad (MISSING_FNSTART
);
4125 if (immediate_for_directive (&offset
) == FAIL
)
4130 as_bad (_("stack increment must be multiple of 4"));
4131 ignore_rest_of_line ();
4135 /* Don't generate any opcodes, just record the details for later. */
4136 unwind
.frame_size
+= offset
;
4137 unwind
.pending_offset
+= offset
;
4139 demand_empty_rest_of_line ();
4142 /* Parse an unwind_setfp directive. */
4145 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4151 if (!unwind
.proc_start
)
4152 as_bad (MISSING_FNSTART
);
4154 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4155 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4158 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4160 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4162 as_bad (_("expected <reg>, <reg>"));
4163 ignore_rest_of_line ();
4167 /* Optional constant. */
4168 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4170 if (immediate_for_directive (&offset
) == FAIL
)
4176 demand_empty_rest_of_line ();
4178 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4180 as_bad (_("register must be either sp or set by a previous"
4181 "unwind_movsp directive"));
4185 /* Don't generate any opcodes, just record the information for later. */
4186 unwind
.fp_reg
= fp_reg
;
4188 if (sp_reg
== REG_SP
)
4189 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4191 unwind
.fp_offset
-= offset
;
4194 /* Parse an unwind_raw directive. */
4197 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4200 /* This is an arbitrary limit. */
4201 unsigned char op
[16];
4204 if (!unwind
.proc_start
)
4205 as_bad (MISSING_FNSTART
);
4208 if (exp
.X_op
== O_constant
4209 && skip_past_comma (&input_line_pointer
) != FAIL
)
4211 unwind
.frame_size
+= exp
.X_add_number
;
4215 exp
.X_op
= O_illegal
;
4217 if (exp
.X_op
!= O_constant
)
4219 as_bad (_("expected <offset>, <opcode>"));
4220 ignore_rest_of_line ();
4226 /* Parse the opcode. */
4231 as_bad (_("unwind opcode too long"));
4232 ignore_rest_of_line ();
4234 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4236 as_bad (_("invalid unwind opcode"));
4237 ignore_rest_of_line ();
4240 op
[count
++] = exp
.X_add_number
;
4242 /* Parse the next byte. */
4243 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4249 /* Add the opcode bytes in reverse order. */
4251 add_unwind_opcode (op
[count
], 1);
4253 demand_empty_rest_of_line ();
4257 /* Parse a .eabi_attribute directive. */
4260 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4262 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4264 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4265 attributes_set_explicitly
[tag
] = 1;
4267 #endif /* OBJ_ELF */
4269 static void s_arm_arch (int);
4270 static void s_arm_object_arch (int);
4271 static void s_arm_cpu (int);
4272 static void s_arm_fpu (int);
4277 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4284 if (exp
.X_op
== O_symbol
)
4285 exp
.X_op
= O_secrel
;
4287 emit_expr (&exp
, 4);
4289 while (*input_line_pointer
++ == ',');
4291 input_line_pointer
--;
4292 demand_empty_rest_of_line ();
4296 /* This table describes all the machine specific pseudo-ops the assembler
4297 has to support. The fields are:
4298 pseudo-op name without dot
4299 function to call to execute this pseudo-op
4300 Integer arg to pass to the function. */
4302 const pseudo_typeS md_pseudo_table
[] =
4304 /* Never called because '.req' does not start a line. */
4305 { "req", s_req
, 0 },
4306 /* Following two are likewise never called. */
4309 { "unreq", s_unreq
, 0 },
4310 { "bss", s_bss
, 0 },
4311 { "align", s_align
, 0 },
4312 { "arm", s_arm
, 0 },
4313 { "thumb", s_thumb
, 0 },
4314 { "code", s_code
, 0 },
4315 { "force_thumb", s_force_thumb
, 0 },
4316 { "thumb_func", s_thumb_func
, 0 },
4317 { "thumb_set", s_thumb_set
, 0 },
4318 { "even", s_even
, 0 },
4319 { "ltorg", s_ltorg
, 0 },
4320 { "pool", s_ltorg
, 0 },
4321 { "syntax", s_syntax
, 0 },
4322 { "cpu", s_arm_cpu
, 0 },
4323 { "arch", s_arm_arch
, 0 },
4324 { "object_arch", s_arm_object_arch
, 0 },
4325 { "fpu", s_arm_fpu
, 0 },
4327 { "word", s_arm_elf_cons
, 4 },
4328 { "long", s_arm_elf_cons
, 4 },
4329 { "inst.n", s_arm_elf_inst
, 2 },
4330 { "inst.w", s_arm_elf_inst
, 4 },
4331 { "inst", s_arm_elf_inst
, 0 },
4332 { "rel31", s_arm_rel31
, 0 },
4333 { "fnstart", s_arm_unwind_fnstart
, 0 },
4334 { "fnend", s_arm_unwind_fnend
, 0 },
4335 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4336 { "personality", s_arm_unwind_personality
, 0 },
4337 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4338 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4339 { "save", s_arm_unwind_save
, 0 },
4340 { "vsave", s_arm_unwind_save
, 1 },
4341 { "movsp", s_arm_unwind_movsp
, 0 },
4342 { "pad", s_arm_unwind_pad
, 0 },
4343 { "setfp", s_arm_unwind_setfp
, 0 },
4344 { "unwind_raw", s_arm_unwind_raw
, 0 },
4345 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4349 /* These are used for dwarf. */
4353 /* These are used for dwarf2. */
4354 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4355 { "loc", dwarf2_directive_loc
, 0 },
4356 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4358 { "extend", float_cons
, 'x' },
4359 { "ldouble", float_cons
, 'x' },
4360 { "packed", float_cons
, 'p' },
4362 {"secrel32", pe_directive_secrel
, 0},
4367 /* Parser functions used exclusively in instruction operands. */
4369 /* Generic immediate-value read function for use in insn parsing.
4370 STR points to the beginning of the immediate (the leading #);
4371 VAL receives the value; if the value is outside [MIN, MAX]
4372 issue an error. PREFIX_OPT is true if the immediate prefix is
4376 parse_immediate (char **str
, int *val
, int min
, int max
,
4377 bfd_boolean prefix_opt
)
4380 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4381 if (exp
.X_op
!= O_constant
)
4383 inst
.error
= _("constant expression required");
4387 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4389 inst
.error
= _("immediate value out of range");
4393 *val
= exp
.X_add_number
;
4397 /* Less-generic immediate-value read function with the possibility of loading a
4398 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4399 instructions. Puts the result directly in inst.operands[i]. */
4402 parse_big_immediate (char **str
, int i
)
4407 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4409 if (exp
.X_op
== O_constant
)
4411 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4412 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4413 O_constant. We have to be careful not to break compilation for
4414 32-bit X_add_number, though. */
4415 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4417 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4418 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4419 inst
.operands
[i
].regisimm
= 1;
4422 else if (exp
.X_op
== O_big
4423 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4425 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4427 /* Bignums have their least significant bits in
4428 generic_bignum[0]. Make sure we put 32 bits in imm and
4429 32 bits in reg, in a (hopefully) portable way. */
4430 gas_assert (parts
!= 0);
4432 /* Make sure that the number is not too big.
4433 PR 11972: Bignums can now be sign-extended to the
4434 size of a .octa so check that the out of range bits
4435 are all zero or all one. */
4436 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4438 LITTLENUM_TYPE m
= -1;
4440 if (generic_bignum
[parts
* 2] != 0
4441 && generic_bignum
[parts
* 2] != m
)
4444 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4445 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4449 inst
.operands
[i
].imm
= 0;
4450 for (j
= 0; j
< parts
; j
++, idx
++)
4451 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4452 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4453 inst
.operands
[i
].reg
= 0;
4454 for (j
= 0; j
< parts
; j
++, idx
++)
4455 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4456 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4457 inst
.operands
[i
].regisimm
= 1;
4467 /* Returns the pseudo-register number of an FPA immediate constant,
4468 or FAIL if there isn't a valid constant here. */
4471 parse_fpa_immediate (char ** str
)
4473 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4479 /* First try and match exact strings, this is to guarantee
4480 that some formats will work even for cross assembly. */
4482 for (i
= 0; fp_const
[i
]; i
++)
4484 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4488 *str
+= strlen (fp_const
[i
]);
4489 if (is_end_of_line
[(unsigned char) **str
])
4495 /* Just because we didn't get a match doesn't mean that the constant
4496 isn't valid, just that it is in a format that we don't
4497 automatically recognize. Try parsing it with the standard
4498 expression routines. */
4500 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4502 /* Look for a raw floating point number. */
4503 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4504 && is_end_of_line
[(unsigned char) *save_in
])
4506 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4508 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4510 if (words
[j
] != fp_values
[i
][j
])
4514 if (j
== MAX_LITTLENUMS
)
4522 /* Try and parse a more complex expression, this will probably fail
4523 unless the code uses a floating point prefix (eg "0f"). */
4524 save_in
= input_line_pointer
;
4525 input_line_pointer
= *str
;
4526 if (expression (&exp
) == absolute_section
4527 && exp
.X_op
== O_big
4528 && exp
.X_add_number
< 0)
4530 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4532 if (gen_to_words (words
, 5, (long) 15) == 0)
4534 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4536 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4538 if (words
[j
] != fp_values
[i
][j
])
4542 if (j
== MAX_LITTLENUMS
)
4544 *str
= input_line_pointer
;
4545 input_line_pointer
= save_in
;
4552 *str
= input_line_pointer
;
4553 input_line_pointer
= save_in
;
4554 inst
.error
= _("invalid FPA immediate expression");
4558 /* Returns 1 if a number has "quarter-precision" float format
4559 0baBbbbbbc defgh000 00000000 00000000. */
4562 is_quarter_float (unsigned imm
)
4564 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4565 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4568 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4569 0baBbbbbbc defgh000 00000000 00000000.
4570 The zero and minus-zero cases need special handling, since they can't be
4571 encoded in the "quarter-precision" float format, but can nonetheless be
4572 loaded as integer constants. */
4575 parse_qfloat_immediate (char **ccp
, int *immed
)
4579 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4580 int found_fpchar
= 0;
4582 skip_past_char (&str
, '#');
4584 /* We must not accidentally parse an integer as a floating-point number. Make
4585 sure that the value we parse is not an integer by checking for special
4586 characters '.' or 'e'.
4587 FIXME: This is a horrible hack, but doing better is tricky because type
4588 information isn't in a very usable state at parse time. */
4590 skip_whitespace (fpnum
);
4592 if (strncmp (fpnum
, "0x", 2) == 0)
4596 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4597 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4607 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4609 unsigned fpword
= 0;
4612 /* Our FP word must be 32 bits (single-precision FP). */
4613 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4615 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4619 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4632 /* Shift operands. */
4635 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4638 struct asm_shift_name
4641 enum shift_kind kind
;
4644 /* Third argument to parse_shift. */
4645 enum parse_shift_mode
4647 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4648 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4649 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4650 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4651 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4654 /* Parse a <shift> specifier on an ARM data processing instruction.
4655 This has three forms:
4657 (LSL|LSR|ASL|ASR|ROR) Rs
4658 (LSL|LSR|ASL|ASR|ROR) #imm
4661 Note that ASL is assimilated to LSL in the instruction encoding, and
4662 RRX to ROR #0 (which cannot be written as such). */
4665 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4667 const struct asm_shift_name
*shift_name
;
4668 enum shift_kind shift
;
4673 for (p
= *str
; ISALPHA (*p
); p
++)
4678 inst
.error
= _("shift expression expected");
4682 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4685 if (shift_name
== NULL
)
4687 inst
.error
= _("shift expression expected");
4691 shift
= shift_name
->kind
;
4695 case NO_SHIFT_RESTRICT
:
4696 case SHIFT_IMMEDIATE
: break;
4698 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4699 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4701 inst
.error
= _("'LSL' or 'ASR' required");
4706 case SHIFT_LSL_IMMEDIATE
:
4707 if (shift
!= SHIFT_LSL
)
4709 inst
.error
= _("'LSL' required");
4714 case SHIFT_ASR_IMMEDIATE
:
4715 if (shift
!= SHIFT_ASR
)
4717 inst
.error
= _("'ASR' required");
4725 if (shift
!= SHIFT_RRX
)
4727 /* Whitespace can appear here if the next thing is a bare digit. */
4728 skip_whitespace (p
);
4730 if (mode
== NO_SHIFT_RESTRICT
4731 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4733 inst
.operands
[i
].imm
= reg
;
4734 inst
.operands
[i
].immisreg
= 1;
4736 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4739 inst
.operands
[i
].shift_kind
= shift
;
4740 inst
.operands
[i
].shifted
= 1;
4745 /* Parse a <shifter_operand> for an ARM data processing instruction:
4748 #<immediate>, <rotate>
4752 where <shift> is defined by parse_shift above, and <rotate> is a
4753 multiple of 2 between 0 and 30. Validation of immediate operands
4754 is deferred to md_apply_fix. */
4757 parse_shifter_operand (char **str
, int i
)
4762 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4764 inst
.operands
[i
].reg
= value
;
4765 inst
.operands
[i
].isreg
= 1;
4767 /* parse_shift will override this if appropriate */
4768 inst
.reloc
.exp
.X_op
= O_constant
;
4769 inst
.reloc
.exp
.X_add_number
= 0;
4771 if (skip_past_comma (str
) == FAIL
)
4774 /* Shift operation on register. */
4775 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4778 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4781 if (skip_past_comma (str
) == SUCCESS
)
4783 /* #x, y -- ie explicit rotation by Y. */
4784 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4787 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4789 inst
.error
= _("constant expression expected");
4793 value
= exp
.X_add_number
;
4794 if (value
< 0 || value
> 30 || value
% 2 != 0)
4796 inst
.error
= _("invalid rotation");
4799 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4801 inst
.error
= _("invalid constant");
4805 /* Convert to decoded value. md_apply_fix will put it back. */
4806 inst
.reloc
.exp
.X_add_number
4807 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4808 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4811 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4812 inst
.reloc
.pc_rel
= 0;
4816 /* Group relocation information. Each entry in the table contains the
4817 textual name of the relocation as may appear in assembler source
4818 and must end with a colon.
4819 Along with this textual name are the relocation codes to be used if
4820 the corresponding instruction is an ALU instruction (ADD or SUB only),
4821 an LDR, an LDRS, or an LDC. */
4823 struct group_reloc_table_entry
4834 /* Varieties of non-ALU group relocation. */
4841 static struct group_reloc_table_entry group_reloc_table
[] =
4842 { /* Program counter relative: */
4844 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4849 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4850 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4851 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4852 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4854 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4859 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4860 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4861 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4862 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4864 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4865 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4866 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4867 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4868 /* Section base relative */
4870 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4875 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4876 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4877 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4878 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4880 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4885 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4886 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4887 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4888 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4890 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4891 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4892 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4893 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4895 /* Given the address of a pointer pointing to the textual name of a group
4896 relocation as may appear in assembler source, attempt to find its details
4897 in group_reloc_table. The pointer will be updated to the character after
4898 the trailing colon. On failure, FAIL will be returned; SUCCESS
4899 otherwise. On success, *entry will be updated to point at the relevant
4900 group_reloc_table entry. */
4903 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4906 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4908 int length
= strlen (group_reloc_table
[i
].name
);
4910 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4911 && (*str
)[length
] == ':')
4913 *out
= &group_reloc_table
[i
];
4914 *str
+= (length
+ 1);
4922 /* Parse a <shifter_operand> for an ARM data processing instruction
4923 (as for parse_shifter_operand) where group relocations are allowed:
4926 #<immediate>, <rotate>
4927 #:<group_reloc>:<expression>
4931 where <group_reloc> is one of the strings defined in group_reloc_table.
4932 The hashes are optional.
4934 Everything else is as for parse_shifter_operand. */
4936 static parse_operand_result
4937 parse_shifter_operand_group_reloc (char **str
, int i
)
4939 /* Determine if we have the sequence of characters #: or just :
4940 coming next. If we do, then we check for a group relocation.
4941 If we don't, punt the whole lot to parse_shifter_operand. */
4943 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4944 || (*str
)[0] == ':')
4946 struct group_reloc_table_entry
*entry
;
4948 if ((*str
)[0] == '#')
4953 /* Try to parse a group relocation. Anything else is an error. */
4954 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4956 inst
.error
= _("unknown group relocation");
4957 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4960 /* We now have the group relocation table entry corresponding to
4961 the name in the assembler source. Next, we parse the expression. */
4962 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4963 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4965 /* Record the relocation type (always the ALU variant here). */
4966 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4967 gas_assert (inst
.reloc
.type
!= 0);
4969 return PARSE_OPERAND_SUCCESS
;
4972 return parse_shifter_operand (str
, i
) == SUCCESS
4973 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4975 /* Never reached. */
4978 /* Parse a Neon alignment expression. Information is written to
4979 inst.operands[i]. We assume the initial ':' has been skipped.
4981 align .imm = align << 8, .immisalign=1, .preind=0 */
4982 static parse_operand_result
4983 parse_neon_alignment (char **str
, int i
)
4988 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4990 if (exp
.X_op
!= O_constant
)
4992 inst
.error
= _("alignment must be constant");
4993 return PARSE_OPERAND_FAIL
;
4996 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4997 inst
.operands
[i
].immisalign
= 1;
4998 /* Alignments are not pre-indexes. */
4999 inst
.operands
[i
].preind
= 0;
5002 return PARSE_OPERAND_SUCCESS
;
5005 /* Parse all forms of an ARM address expression. Information is written
5006 to inst.operands[i] and/or inst.reloc.
5008 Preindexed addressing (.preind=1):
5010 [Rn, #offset] .reg=Rn .reloc.exp=offset
5011 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5012 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5013 .shift_kind=shift .reloc.exp=shift_imm
5015 These three may have a trailing ! which causes .writeback to be set also.
5017 Postindexed addressing (.postind=1, .writeback=1):
5019 [Rn], #offset .reg=Rn .reloc.exp=offset
5020 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5021 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5022 .shift_kind=shift .reloc.exp=shift_imm
5024 Unindexed addressing (.preind=0, .postind=0):
5026 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5030 [Rn]{!} shorthand for [Rn,#0]{!}
5031 =immediate .isreg=0 .reloc.exp=immediate
5032 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5034 It is the caller's responsibility to check for addressing modes not
5035 supported by the instruction, and to set inst.reloc.type. */
5037 static parse_operand_result
5038 parse_address_main (char **str
, int i
, int group_relocations
,
5039 group_reloc_type group_type
)
5044 if (skip_past_char (&p
, '[') == FAIL
)
5046 if (skip_past_char (&p
, '=') == FAIL
)
5048 /* Bare address - translate to PC-relative offset. */
5049 inst
.reloc
.pc_rel
= 1;
5050 inst
.operands
[i
].reg
= REG_PC
;
5051 inst
.operands
[i
].isreg
= 1;
5052 inst
.operands
[i
].preind
= 1;
5054 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5056 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5057 return PARSE_OPERAND_FAIL
;
5060 return PARSE_OPERAND_SUCCESS
;
5063 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5065 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5066 return PARSE_OPERAND_FAIL
;
5068 inst
.operands
[i
].reg
= reg
;
5069 inst
.operands
[i
].isreg
= 1;
5071 if (skip_past_comma (&p
) == SUCCESS
)
5073 inst
.operands
[i
].preind
= 1;
5076 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5078 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5080 inst
.operands
[i
].imm
= reg
;
5081 inst
.operands
[i
].immisreg
= 1;
5083 if (skip_past_comma (&p
) == SUCCESS
)
5084 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5085 return PARSE_OPERAND_FAIL
;
5087 else if (skip_past_char (&p
, ':') == SUCCESS
)
5089 /* FIXME: '@' should be used here, but it's filtered out by generic
5090 code before we get to see it here. This may be subject to
5092 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5094 if (result
!= PARSE_OPERAND_SUCCESS
)
5099 if (inst
.operands
[i
].negative
)
5101 inst
.operands
[i
].negative
= 0;
5105 if (group_relocations
5106 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5108 struct group_reloc_table_entry
*entry
;
5110 /* Skip over the #: or : sequence. */
5116 /* Try to parse a group relocation. Anything else is an
5118 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5120 inst
.error
= _("unknown group relocation");
5121 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5124 /* We now have the group relocation table entry corresponding to
5125 the name in the assembler source. Next, we parse the
5127 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5128 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5130 /* Record the relocation type. */
5134 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5138 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5142 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5149 if (inst
.reloc
.type
== 0)
5151 inst
.error
= _("this group relocation is not allowed on this instruction");
5152 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5156 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5157 return PARSE_OPERAND_FAIL
;
5160 else if (skip_past_char (&p
, ':') == SUCCESS
)
5162 /* FIXME: '@' should be used here, but it's filtered out by generic code
5163 before we get to see it here. This may be subject to change. */
5164 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5166 if (result
!= PARSE_OPERAND_SUCCESS
)
5170 if (skip_past_char (&p
, ']') == FAIL
)
5172 inst
.error
= _("']' expected");
5173 return PARSE_OPERAND_FAIL
;
5176 if (skip_past_char (&p
, '!') == SUCCESS
)
5177 inst
.operands
[i
].writeback
= 1;
5179 else if (skip_past_comma (&p
) == SUCCESS
)
5181 if (skip_past_char (&p
, '{') == SUCCESS
)
5183 /* [Rn], {expr} - unindexed, with option */
5184 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5185 0, 255, TRUE
) == FAIL
)
5186 return PARSE_OPERAND_FAIL
;
5188 if (skip_past_char (&p
, '}') == FAIL
)
5190 inst
.error
= _("'}' expected at end of 'option' field");
5191 return PARSE_OPERAND_FAIL
;
5193 if (inst
.operands
[i
].preind
)
5195 inst
.error
= _("cannot combine index with option");
5196 return PARSE_OPERAND_FAIL
;
5199 return PARSE_OPERAND_SUCCESS
;
5203 inst
.operands
[i
].postind
= 1;
5204 inst
.operands
[i
].writeback
= 1;
5206 if (inst
.operands
[i
].preind
)
5208 inst
.error
= _("cannot combine pre- and post-indexing");
5209 return PARSE_OPERAND_FAIL
;
5213 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5215 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5217 /* We might be using the immediate for alignment already. If we
5218 are, OR the register number into the low-order bits. */
5219 if (inst
.operands
[i
].immisalign
)
5220 inst
.operands
[i
].imm
|= reg
;
5222 inst
.operands
[i
].imm
= reg
;
5223 inst
.operands
[i
].immisreg
= 1;
5225 if (skip_past_comma (&p
) == SUCCESS
)
5226 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5227 return PARSE_OPERAND_FAIL
;
5231 if (inst
.operands
[i
].negative
)
5233 inst
.operands
[i
].negative
= 0;
5236 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5237 return PARSE_OPERAND_FAIL
;
5242 /* If at this point neither .preind nor .postind is set, we have a
5243 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5244 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5246 inst
.operands
[i
].preind
= 1;
5247 inst
.reloc
.exp
.X_op
= O_constant
;
5248 inst
.reloc
.exp
.X_add_number
= 0;
5251 return PARSE_OPERAND_SUCCESS
;
5255 parse_address (char **str
, int i
)
5257 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5261 static parse_operand_result
5262 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5264 return parse_address_main (str
, i
, 1, type
);
5267 /* Parse an operand for a MOVW or MOVT instruction. */
5269 parse_half (char **str
)
5274 skip_past_char (&p
, '#');
5275 if (strncasecmp (p
, ":lower16:", 9) == 0)
5276 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5277 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5278 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5280 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5283 skip_whitespace (p
);
5286 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5289 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5291 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5293 inst
.error
= _("constant expression expected");
5296 if (inst
.reloc
.exp
.X_add_number
< 0
5297 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5299 inst
.error
= _("immediate value out of range");
5307 /* Miscellaneous. */
5309 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5310 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5312 parse_psr (char **str
)
5315 unsigned long psr_field
;
5316 const struct asm_psr
*psr
;
5319 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5320 feature for ease of use and backwards compatibility. */
5322 if (strncasecmp (p
, "SPSR", 4) == 0)
5323 psr_field
= SPSR_BIT
;
5324 else if (strncasecmp (p
, "CPSR", 4) == 0)
5331 while (ISALNUM (*p
) || *p
== '_');
5333 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5345 /* A suffix follows. */
5351 while (ISALNUM (*p
) || *p
== '_');
5353 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5358 psr_field
|= psr
->field
;
5363 goto error
; /* Garbage after "[CS]PSR". */
5365 psr_field
|= (PSR_c
| PSR_f
);
5371 inst
.error
= _("flag for {c}psr instruction expected");
5375 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5376 value suitable for splatting into the AIF field of the instruction. */
5379 parse_cps_flags (char **str
)
5388 case '\0': case ',':
5391 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5392 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5393 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5396 inst
.error
= _("unrecognized CPS flag");
5401 if (saw_a_flag
== 0)
5403 inst
.error
= _("missing CPS flags");
5411 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5412 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5415 parse_endian_specifier (char **str
)
5420 if (strncasecmp (s
, "BE", 2))
5422 else if (strncasecmp (s
, "LE", 2))
5426 inst
.error
= _("valid endian specifiers are be or le");
5430 if (ISALNUM (s
[2]) || s
[2] == '_')
5432 inst
.error
= _("valid endian specifiers are be or le");
5437 return little_endian
;
5440 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5441 value suitable for poking into the rotate field of an sxt or sxta
5442 instruction, or FAIL on error. */
5445 parse_ror (char **str
)
5450 if (strncasecmp (s
, "ROR", 3) == 0)
5454 inst
.error
= _("missing rotation field after comma");
5458 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5463 case 0: *str
= s
; return 0x0;
5464 case 8: *str
= s
; return 0x1;
5465 case 16: *str
= s
; return 0x2;
5466 case 24: *str
= s
; return 0x3;
5469 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5474 /* Parse a conditional code (from conds[] below). The value returned is in the
5475 range 0 .. 14, or FAIL. */
5477 parse_cond (char **str
)
5480 const struct asm_cond
*c
;
5482 /* Condition codes are always 2 characters, so matching up to
5483 3 characters is sufficient. */
5488 while (ISALPHA (*q
) && n
< 3)
5490 cond
[n
] = TOLOWER (*q
);
5495 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5498 inst
.error
= _("condition required");
5506 /* Parse an option for a barrier instruction. Returns the encoding for the
5509 parse_barrier (char **str
)
5512 const struct asm_barrier_opt
*o
;
5515 while (ISALPHA (*q
))
5518 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5527 /* Parse the operands of a table branch instruction. Similar to a memory
5530 parse_tb (char **str
)
5535 if (skip_past_char (&p
, '[') == FAIL
)
5537 inst
.error
= _("'[' expected");
5541 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5543 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5546 inst
.operands
[0].reg
= reg
;
5548 if (skip_past_comma (&p
) == FAIL
)
5550 inst
.error
= _("',' expected");
5554 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5556 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5559 inst
.operands
[0].imm
= reg
;
5561 if (skip_past_comma (&p
) == SUCCESS
)
5563 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5565 if (inst
.reloc
.exp
.X_add_number
!= 1)
5567 inst
.error
= _("invalid shift");
5570 inst
.operands
[0].shifted
= 1;
5573 if (skip_past_char (&p
, ']') == FAIL
)
5575 inst
.error
= _("']' expected");
5582 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5583 information on the types the operands can take and how they are encoded.
5584 Up to four operands may be read; this function handles setting the
5585 ".present" field for each read operand itself.
5586 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5587 else returns FAIL. */
5590 parse_neon_mov (char **str
, int *which_operand
)
5592 int i
= *which_operand
, val
;
5593 enum arm_reg_type rtype
;
5595 struct neon_type_el optype
;
5597 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5599 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5600 inst
.operands
[i
].reg
= val
;
5601 inst
.operands
[i
].isscalar
= 1;
5602 inst
.operands
[i
].vectype
= optype
;
5603 inst
.operands
[i
++].present
= 1;
5605 if (skip_past_comma (&ptr
) == FAIL
)
5608 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5611 inst
.operands
[i
].reg
= val
;
5612 inst
.operands
[i
].isreg
= 1;
5613 inst
.operands
[i
].present
= 1;
5615 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5618 /* Cases 0, 1, 2, 3, 5 (D only). */
5619 if (skip_past_comma (&ptr
) == FAIL
)
5622 inst
.operands
[i
].reg
= val
;
5623 inst
.operands
[i
].isreg
= 1;
5624 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5625 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5626 inst
.operands
[i
].isvec
= 1;
5627 inst
.operands
[i
].vectype
= optype
;
5628 inst
.operands
[i
++].present
= 1;
5630 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5632 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5633 Case 13: VMOV <Sd>, <Rm> */
5634 inst
.operands
[i
].reg
= val
;
5635 inst
.operands
[i
].isreg
= 1;
5636 inst
.operands
[i
].present
= 1;
5638 if (rtype
== REG_TYPE_NQ
)
5640 first_error (_("can't use Neon quad register here"));
5643 else if (rtype
!= REG_TYPE_VFS
)
5646 if (skip_past_comma (&ptr
) == FAIL
)
5648 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5650 inst
.operands
[i
].reg
= val
;
5651 inst
.operands
[i
].isreg
= 1;
5652 inst
.operands
[i
].present
= 1;
5655 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5658 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5659 Case 1: VMOV<c><q> <Dd>, <Dm>
5660 Case 8: VMOV.F32 <Sd>, <Sm>
5661 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5663 inst
.operands
[i
].reg
= val
;
5664 inst
.operands
[i
].isreg
= 1;
5665 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5666 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5667 inst
.operands
[i
].isvec
= 1;
5668 inst
.operands
[i
].vectype
= optype
;
5669 inst
.operands
[i
].present
= 1;
5671 if (skip_past_comma (&ptr
) == SUCCESS
)
5676 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5679 inst
.operands
[i
].reg
= val
;
5680 inst
.operands
[i
].isreg
= 1;
5681 inst
.operands
[i
++].present
= 1;
5683 if (skip_past_comma (&ptr
) == FAIL
)
5686 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5689 inst
.operands
[i
].reg
= val
;
5690 inst
.operands
[i
].isreg
= 1;
5691 inst
.operands
[i
++].present
= 1;
5694 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5695 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5696 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5697 Case 10: VMOV.F32 <Sd>, #<imm>
5698 Case 11: VMOV.F64 <Dd>, #<imm> */
5699 inst
.operands
[i
].immisfloat
= 1;
5700 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5701 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5702 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5706 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5710 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5713 inst
.operands
[i
].reg
= val
;
5714 inst
.operands
[i
].isreg
= 1;
5715 inst
.operands
[i
++].present
= 1;
5717 if (skip_past_comma (&ptr
) == FAIL
)
5720 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5722 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5723 inst
.operands
[i
].reg
= val
;
5724 inst
.operands
[i
].isscalar
= 1;
5725 inst
.operands
[i
].present
= 1;
5726 inst
.operands
[i
].vectype
= optype
;
5728 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5730 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5731 inst
.operands
[i
].reg
= val
;
5732 inst
.operands
[i
].isreg
= 1;
5733 inst
.operands
[i
++].present
= 1;
5735 if (skip_past_comma (&ptr
) == FAIL
)
5738 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5741 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5745 inst
.operands
[i
].reg
= val
;
5746 inst
.operands
[i
].isreg
= 1;
5747 inst
.operands
[i
].isvec
= 1;
5748 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5749 inst
.operands
[i
].vectype
= optype
;
5750 inst
.operands
[i
].present
= 1;
5752 if (rtype
== REG_TYPE_VFS
)
5756 if (skip_past_comma (&ptr
) == FAIL
)
5758 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5761 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5764 inst
.operands
[i
].reg
= val
;
5765 inst
.operands
[i
].isreg
= 1;
5766 inst
.operands
[i
].isvec
= 1;
5767 inst
.operands
[i
].issingle
= 1;
5768 inst
.operands
[i
].vectype
= optype
;
5769 inst
.operands
[i
].present
= 1;
5772 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5776 inst
.operands
[i
].reg
= val
;
5777 inst
.operands
[i
].isreg
= 1;
5778 inst
.operands
[i
].isvec
= 1;
5779 inst
.operands
[i
].issingle
= 1;
5780 inst
.operands
[i
].vectype
= optype
;
5781 inst
.operands
[i
++].present
= 1;
5786 first_error (_("parse error"));
5790 /* Successfully parsed the operands. Update args. */
5796 first_error (_("expected comma"));
5800 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5804 /* Use this macro when the operand constraints are different
5805 for ARM and THUMB (e.g. ldrd). */
5806 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5807 ((arm_operand) | ((thumb_operand) << 16))
5809 /* Matcher codes for parse_operands. */
5810 enum operand_parse_code
5812 OP_stop
, /* end of line */
5814 OP_RR
, /* ARM register */
5815 OP_RRnpc
, /* ARM register, not r15 */
5816 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5817 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5818 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5819 optional trailing ! */
5820 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5821 OP_RCP
, /* Coprocessor number */
5822 OP_RCN
, /* Coprocessor register */
5823 OP_RF
, /* FPA register */
5824 OP_RVS
, /* VFP single precision register */
5825 OP_RVD
, /* VFP double precision register (0..15) */
5826 OP_RND
, /* Neon double precision register (0..31) */
5827 OP_RNQ
, /* Neon quad precision register */
5828 OP_RVSD
, /* VFP single or double precision register */
5829 OP_RNDQ
, /* Neon double or quad precision register */
5830 OP_RNSDQ
, /* Neon single, double or quad precision register */
5831 OP_RNSC
, /* Neon scalar D[X] */
5832 OP_RVC
, /* VFP control register */
5833 OP_RMF
, /* Maverick F register */
5834 OP_RMD
, /* Maverick D register */
5835 OP_RMFX
, /* Maverick FX register */
5836 OP_RMDX
, /* Maverick DX register */
5837 OP_RMAX
, /* Maverick AX register */
5838 OP_RMDS
, /* Maverick DSPSC register */
5839 OP_RIWR
, /* iWMMXt wR register */
5840 OP_RIWC
, /* iWMMXt wC register */
5841 OP_RIWG
, /* iWMMXt wCG register */
5842 OP_RXA
, /* XScale accumulator register */
5844 OP_REGLST
, /* ARM register list */
5845 OP_VRSLST
, /* VFP single-precision register list */
5846 OP_VRDLST
, /* VFP double-precision register list */
5847 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5848 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5849 OP_NSTRLST
, /* Neon element/structure list */
5851 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5852 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5853 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5854 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5855 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5856 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5857 OP_VMOV
, /* Neon VMOV operands. */
5858 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5859 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5860 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5862 OP_I0
, /* immediate zero */
5863 OP_I7
, /* immediate value 0 .. 7 */
5864 OP_I15
, /* 0 .. 15 */
5865 OP_I16
, /* 1 .. 16 */
5866 OP_I16z
, /* 0 .. 16 */
5867 OP_I31
, /* 0 .. 31 */
5868 OP_I31w
, /* 0 .. 31, optional trailing ! */
5869 OP_I32
, /* 1 .. 32 */
5870 OP_I32z
, /* 0 .. 32 */
5871 OP_I63
, /* 0 .. 63 */
5872 OP_I63s
, /* -64 .. 63 */
5873 OP_I64
, /* 1 .. 64 */
5874 OP_I64z
, /* 0 .. 64 */
5875 OP_I255
, /* 0 .. 255 */
5877 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5878 OP_I7b
, /* 0 .. 7 */
5879 OP_I15b
, /* 0 .. 15 */
5880 OP_I31b
, /* 0 .. 31 */
5882 OP_SH
, /* shifter operand */
5883 OP_SHG
, /* shifter operand with possible group relocation */
5884 OP_ADDR
, /* Memory address expression (any mode) */
5885 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5886 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5887 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5888 OP_EXP
, /* arbitrary expression */
5889 OP_EXPi
, /* same, with optional immediate prefix */
5890 OP_EXPr
, /* same, with optional relocation suffix */
5891 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5893 OP_CPSF
, /* CPS flags */
5894 OP_ENDI
, /* Endianness specifier */
5895 OP_PSR
, /* CPSR/SPSR mask for msr */
5896 OP_COND
, /* conditional code */
5897 OP_TB
, /* Table branch. */
5899 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5900 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5902 OP_RRnpc_I0
, /* ARM register or literal 0 */
5903 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5904 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5905 OP_RF_IF
, /* FPA register or immediate */
5906 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5907 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5909 /* Optional operands. */
5910 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5911 OP_oI31b
, /* 0 .. 31 */
5912 OP_oI32b
, /* 1 .. 32 */
5913 OP_oIffffb
, /* 0 .. 65535 */
5914 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5916 OP_oRR
, /* ARM register */
5917 OP_oRRnpc
, /* ARM register, not the PC */
5918 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5919 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5920 OP_oRND
, /* Optional Neon double precision register */
5921 OP_oRNQ
, /* Optional Neon quad precision register */
5922 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5923 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5924 OP_oSHll
, /* LSL immediate */
5925 OP_oSHar
, /* ASR immediate */
5926 OP_oSHllar
, /* LSL or ASR immediate */
5927 OP_oROR
, /* ROR 0/8/16/24 */
5928 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
5930 /* Some pre-defined mixed (ARM/THUMB) operands. */
5931 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5932 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5933 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5935 OP_FIRST_OPTIONAL
= OP_oI7b
5938 /* Generic instruction operand parser. This does no encoding and no
5939 semantic validation; it merely squirrels values away in the inst
5940 structure. Returns SUCCESS or FAIL depending on whether the
5941 specified grammar matched. */
5943 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5945 unsigned const int *upat
= pattern
;
5946 char *backtrack_pos
= 0;
5947 const char *backtrack_error
= 0;
5948 int i
, val
, backtrack_index
= 0;
5949 enum arm_reg_type rtype
;
5950 parse_operand_result result
;
5951 unsigned int op_parse_code
;
5953 #define po_char_or_fail(chr) \
5956 if (skip_past_char (&str, chr) == FAIL) \
5961 #define po_reg_or_fail(regtype) \
5964 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5965 & inst.operands[i].vectype); \
5968 first_error (_(reg_expected_msgs[regtype])); \
5971 inst.operands[i].reg = val; \
5972 inst.operands[i].isreg = 1; \
5973 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5974 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5975 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5976 || rtype == REG_TYPE_VFD \
5977 || rtype == REG_TYPE_NQ); \
5981 #define po_reg_or_goto(regtype, label) \
5984 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5985 & inst.operands[i].vectype); \
5989 inst.operands[i].reg = val; \
5990 inst.operands[i].isreg = 1; \
5991 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5992 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5993 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5994 || rtype == REG_TYPE_VFD \
5995 || rtype == REG_TYPE_NQ); \
5999 #define po_imm_or_fail(min, max, popt) \
6002 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6004 inst.operands[i].imm = val; \
6008 #define po_scalar_or_goto(elsz, label) \
6011 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6014 inst.operands[i].reg = val; \
6015 inst.operands[i].isscalar = 1; \
6019 #define po_misc_or_fail(expr) \
6027 #define po_misc_or_fail_no_backtrack(expr) \
6031 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6032 backtrack_pos = 0; \
6033 if (result != PARSE_OPERAND_SUCCESS) \
6038 #define po_barrier_or_imm(str) \
6041 val = parse_barrier (&str); \
6044 if (ISALPHA (*str)) \
6051 if ((inst.instruction & 0xf0) == 0x60 \
6054 /* ISB can only take SY as an option. */ \
6055 inst.error = _("invalid barrier type"); \
6062 skip_whitespace (str
);
6064 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6066 op_parse_code
= upat
[i
];
6067 if (op_parse_code
>= 1<<16)
6068 op_parse_code
= thumb
? (op_parse_code
>> 16)
6069 : (op_parse_code
& ((1<<16)-1));
6071 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6073 /* Remember where we are in case we need to backtrack. */
6074 gas_assert (!backtrack_pos
);
6075 backtrack_pos
= str
;
6076 backtrack_error
= inst
.error
;
6077 backtrack_index
= i
;
6080 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6081 po_char_or_fail (',');
6083 switch (op_parse_code
)
6091 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6092 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6093 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6094 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6095 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6096 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6098 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6100 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6102 /* Also accept generic coprocessor regs for unknown registers. */
6104 po_reg_or_fail (REG_TYPE_CN
);
6106 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6107 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6108 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6109 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6110 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6111 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6112 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6113 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6114 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6115 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6117 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6119 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6120 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6122 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6124 /* Neon scalar. Using an element size of 8 means that some invalid
6125 scalars are accepted here, so deal with those in later code. */
6126 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6130 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6133 po_imm_or_fail (0, 0, TRUE
);
6138 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6143 po_scalar_or_goto (8, try_rr
);
6146 po_reg_or_fail (REG_TYPE_RN
);
6152 po_scalar_or_goto (8, try_nsdq
);
6155 po_reg_or_fail (REG_TYPE_NSDQ
);
6161 po_scalar_or_goto (8, try_ndq
);
6164 po_reg_or_fail (REG_TYPE_NDQ
);
6170 po_scalar_or_goto (8, try_vfd
);
6173 po_reg_or_fail (REG_TYPE_VFD
);
6178 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6179 not careful then bad things might happen. */
6180 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6185 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6188 /* There's a possibility of getting a 64-bit immediate here, so
6189 we need special handling. */
6190 if (parse_big_immediate (&str
, i
) == FAIL
)
6192 inst
.error
= _("immediate value is out of range");
6200 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6203 po_imm_or_fail (0, 63, TRUE
);
6208 po_char_or_fail ('[');
6209 po_reg_or_fail (REG_TYPE_RN
);
6210 po_char_or_fail (']');
6216 po_reg_or_fail (REG_TYPE_RN
);
6217 if (skip_past_char (&str
, '!') == SUCCESS
)
6218 inst
.operands
[i
].writeback
= 1;
6222 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6223 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6224 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6225 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6226 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6227 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6228 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6229 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6230 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6231 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6232 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6233 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6235 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6237 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6238 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6240 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6241 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6242 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6244 /* Immediate variants */
6246 po_char_or_fail ('{');
6247 po_imm_or_fail (0, 255, TRUE
);
6248 po_char_or_fail ('}');
6252 /* The expression parser chokes on a trailing !, so we have
6253 to find it first and zap it. */
6256 while (*s
&& *s
!= ',')
6261 inst
.operands
[i
].writeback
= 1;
6263 po_imm_or_fail (0, 31, TRUE
);
6271 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6276 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6281 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6283 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6285 val
= parse_reloc (&str
);
6288 inst
.error
= _("unrecognized relocation suffix");
6291 else if (val
!= BFD_RELOC_UNUSED
)
6293 inst
.operands
[i
].imm
= val
;
6294 inst
.operands
[i
].hasreloc
= 1;
6299 /* Operand for MOVW or MOVT. */
6301 po_misc_or_fail (parse_half (&str
));
6304 /* Register or expression. */
6305 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6306 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6308 /* Register or immediate. */
6309 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6310 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6312 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6314 if (!is_immediate_prefix (*str
))
6317 val
= parse_fpa_immediate (&str
);
6320 /* FPA immediates are encoded as registers 8-15.
6321 parse_fpa_immediate has already applied the offset. */
6322 inst
.operands
[i
].reg
= val
;
6323 inst
.operands
[i
].isreg
= 1;
6326 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6327 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6329 /* Two kinds of register. */
6332 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6334 || (rege
->type
!= REG_TYPE_MMXWR
6335 && rege
->type
!= REG_TYPE_MMXWC
6336 && rege
->type
!= REG_TYPE_MMXWCG
))
6338 inst
.error
= _("iWMMXt data or control register expected");
6341 inst
.operands
[i
].reg
= rege
->number
;
6342 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6348 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6350 || (rege
->type
!= REG_TYPE_MMXWC
6351 && rege
->type
!= REG_TYPE_MMXWCG
))
6353 inst
.error
= _("iWMMXt control register expected");
6356 inst
.operands
[i
].reg
= rege
->number
;
6357 inst
.operands
[i
].isreg
= 1;
6362 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6363 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6364 case OP_oROR
: val
= parse_ror (&str
); break;
6365 case OP_PSR
: val
= parse_psr (&str
); break;
6366 case OP_COND
: val
= parse_cond (&str
); break;
6367 case OP_oBARRIER_I15
:
6368 po_barrier_or_imm (str
); break;
6370 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6375 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6376 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6379 val
= parse_psr (&str
);
6383 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6386 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6388 if (strncasecmp (str
, "APSR_", 5) == 0)
6395 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6396 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6397 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6398 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6399 default: found
= 16;
6403 inst
.operands
[i
].isvec
= 1;
6404 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6405 inst
.operands
[i
].reg
= REG_PC
;
6412 po_misc_or_fail (parse_tb (&str
));
6415 /* Register lists. */
6417 val
= parse_reg_list (&str
);
6420 inst
.operands
[1].writeback
= 1;
6426 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6430 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6434 /* Allow Q registers too. */
6435 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6440 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6442 inst
.operands
[i
].issingle
= 1;
6447 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6452 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6453 &inst
.operands
[i
].vectype
);
6456 /* Addressing modes */
6458 po_misc_or_fail (parse_address (&str
, i
));
6462 po_misc_or_fail_no_backtrack (
6463 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6467 po_misc_or_fail_no_backtrack (
6468 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6472 po_misc_or_fail_no_backtrack (
6473 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6477 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6481 po_misc_or_fail_no_backtrack (
6482 parse_shifter_operand_group_reloc (&str
, i
));
6486 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6490 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6494 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6498 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6501 /* Various value-based sanity checks and shared operations. We
6502 do not signal immediate failures for the register constraints;
6503 this allows a syntax error to take precedence. */
6504 switch (op_parse_code
)
6512 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6513 inst
.error
= BAD_PC
;
6518 if (inst
.operands
[i
].isreg
)
6520 if (inst
.operands
[i
].reg
== REG_PC
)
6521 inst
.error
= BAD_PC
;
6522 else if (inst
.operands
[i
].reg
== REG_SP
)
6523 inst
.error
= BAD_SP
;
6528 if (inst
.operands
[i
].isreg
6529 && inst
.operands
[i
].reg
== REG_PC
6530 && (inst
.operands
[i
].writeback
|| thumb
))
6531 inst
.error
= BAD_PC
;
6540 case OP_oBARRIER_I15
:
6549 inst
.operands
[i
].imm
= val
;
6556 /* If we get here, this operand was successfully parsed. */
6557 inst
.operands
[i
].present
= 1;
6561 inst
.error
= BAD_ARGS
;
6566 /* The parse routine should already have set inst.error, but set a
6567 default here just in case. */
6569 inst
.error
= _("syntax error");
6573 /* Do not backtrack over a trailing optional argument that
6574 absorbed some text. We will only fail again, with the
6575 'garbage following instruction' error message, which is
6576 probably less helpful than the current one. */
6577 if (backtrack_index
== i
&& backtrack_pos
!= str
6578 && upat
[i
+1] == OP_stop
)
6581 inst
.error
= _("syntax error");
6585 /* Try again, skipping the optional argument at backtrack_pos. */
6586 str
= backtrack_pos
;
6587 inst
.error
= backtrack_error
;
6588 inst
.operands
[backtrack_index
].present
= 0;
6589 i
= backtrack_index
;
6593 /* Check that we have parsed all the arguments. */
6594 if (*str
!= '\0' && !inst
.error
)
6595 inst
.error
= _("garbage following instruction");
6597 return inst
.error
? FAIL
: SUCCESS
;
6600 #undef po_char_or_fail
6601 #undef po_reg_or_fail
6602 #undef po_reg_or_goto
6603 #undef po_imm_or_fail
6604 #undef po_scalar_or_fail
6605 #undef po_barrier_or_imm
6607 /* Shorthand macro for instruction encoding functions issuing errors. */
6608 #define constraint(expr, err) \
6619 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6620 instructions are unpredictable if these registers are used. This
6621 is the BadReg predicate in ARM's Thumb-2 documentation. */
6622 #define reject_bad_reg(reg) \
6624 if (reg == REG_SP || reg == REG_PC) \
6626 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6631 /* If REG is R13 (the stack pointer), warn that its use is
6633 #define warn_deprecated_sp(reg) \
6635 if (warn_on_deprecated && reg == REG_SP) \
6636 as_warn (_("use of r13 is deprecated")); \
6639 /* Functions for operand encoding. ARM, then Thumb. */
6641 #define rotate_left(v, n) (v << n | v >> (32 - n))
6643 /* If VAL can be encoded in the immediate field of an ARM instruction,
6644 return the encoded form. Otherwise, return FAIL. */
6647 encode_arm_immediate (unsigned int val
)
6651 for (i
= 0; i
< 32; i
+= 2)
6652 if ((a
= rotate_left (val
, i
)) <= 0xff)
6653 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6658 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6659 return the encoded form. Otherwise, return FAIL. */
6661 encode_thumb32_immediate (unsigned int val
)
6668 for (i
= 1; i
<= 24; i
++)
6671 if ((val
& ~(0xff << i
)) == 0)
6672 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6676 if (val
== ((a
<< 16) | a
))
6678 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6682 if (val
== ((a
<< 16) | a
))
6683 return 0x200 | (a
>> 8);
6687 /* Encode a VFP SP or DP register number into inst.instruction. */
6690 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6692 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6695 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6698 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6701 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6706 first_error (_("D register out of range for selected VFP version"));
6714 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6718 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6722 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6726 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6730 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6734 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6742 /* Encode a <shift> in an ARM-format instruction. The immediate,
6743 if any, is handled by md_apply_fix. */
6745 encode_arm_shift (int i
)
6747 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6748 inst
.instruction
|= SHIFT_ROR
<< 5;
6751 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6752 if (inst
.operands
[i
].immisreg
)
6754 inst
.instruction
|= SHIFT_BY_REG
;
6755 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6758 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6763 encode_arm_shifter_operand (int i
)
6765 if (inst
.operands
[i
].isreg
)
6767 inst
.instruction
|= inst
.operands
[i
].reg
;
6768 encode_arm_shift (i
);
6771 inst
.instruction
|= INST_IMMEDIATE
;
6774 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6776 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6778 gas_assert (inst
.operands
[i
].isreg
);
6779 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6781 if (inst
.operands
[i
].preind
)
6785 inst
.error
= _("instruction does not accept preindexed addressing");
6788 inst
.instruction
|= PRE_INDEX
;
6789 if (inst
.operands
[i
].writeback
)
6790 inst
.instruction
|= WRITE_BACK
;
6793 else if (inst
.operands
[i
].postind
)
6795 gas_assert (inst
.operands
[i
].writeback
);
6797 inst
.instruction
|= WRITE_BACK
;
6799 else /* unindexed - only for coprocessor */
6801 inst
.error
= _("instruction does not accept unindexed addressing");
6805 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6806 && (((inst
.instruction
& 0x000f0000) >> 16)
6807 == ((inst
.instruction
& 0x0000f000) >> 12)))
6808 as_warn ((inst
.instruction
& LOAD_BIT
)
6809 ? _("destination register same as write-back base")
6810 : _("source register same as write-back base"));
6813 /* inst.operands[i] was set up by parse_address. Encode it into an
6814 ARM-format mode 2 load or store instruction. If is_t is true,
6815 reject forms that cannot be used with a T instruction (i.e. not
6818 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6820 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6822 encode_arm_addr_mode_common (i
, is_t
);
6824 if (inst
.operands
[i
].immisreg
)
6826 constraint ((inst
.operands
[i
].imm
== REG_PC
6827 || (is_pc
&& inst
.operands
[i
].writeback
)),
6829 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6830 inst
.instruction
|= inst
.operands
[i
].imm
;
6831 if (!inst
.operands
[i
].negative
)
6832 inst
.instruction
|= INDEX_UP
;
6833 if (inst
.operands
[i
].shifted
)
6835 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6836 inst
.instruction
|= SHIFT_ROR
<< 5;
6839 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6840 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6844 else /* immediate offset in inst.reloc */
6846 if (is_pc
&& !inst
.reloc
.pc_rel
)
6848 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6850 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
6851 cannot use PC in addressing.
6852 PC cannot be used in writeback addressing, either. */
6853 constraint ((is_t
|| inst
.operands
[i
].writeback
),
6856 /* Use of PC in str is deprecated for ARMv7. */
6857 if (warn_on_deprecated
6859 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
6860 as_warn (_("use of PC in this instruction is deprecated"));
6863 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6864 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6868 /* inst.operands[i] was set up by parse_address. Encode it into an
6869 ARM-format mode 3 load or store instruction. Reject forms that
6870 cannot be used with such instructions. If is_t is true, reject
6871 forms that cannot be used with a T instruction (i.e. not
6874 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6876 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6878 inst
.error
= _("instruction does not accept scaled register index");
6882 encode_arm_addr_mode_common (i
, is_t
);
6884 if (inst
.operands
[i
].immisreg
)
6886 constraint ((inst
.operands
[i
].imm
== REG_PC
6887 || inst
.operands
[i
].reg
== REG_PC
),
6889 inst
.instruction
|= inst
.operands
[i
].imm
;
6890 if (!inst
.operands
[i
].negative
)
6891 inst
.instruction
|= INDEX_UP
;
6893 else /* immediate offset in inst.reloc */
6895 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6896 && inst
.operands
[i
].writeback
),
6898 inst
.instruction
|= HWOFFSET_IMM
;
6899 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6900 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6904 /* inst.operands[i] was set up by parse_address. Encode it into an
6905 ARM-format instruction. Reject all forms which cannot be encoded
6906 into a coprocessor load/store instruction. If wb_ok is false,
6907 reject use of writeback; if unind_ok is false, reject use of
6908 unindexed addressing. If reloc_override is not 0, use it instead
6909 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6910 (in which case it is preserved). */
6913 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6915 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6917 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6919 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6921 gas_assert (!inst
.operands
[i
].writeback
);
6924 inst
.error
= _("instruction does not support unindexed addressing");
6927 inst
.instruction
|= inst
.operands
[i
].imm
;
6928 inst
.instruction
|= INDEX_UP
;
6932 if (inst
.operands
[i
].preind
)
6933 inst
.instruction
|= PRE_INDEX
;
6935 if (inst
.operands
[i
].writeback
)
6937 if (inst
.operands
[i
].reg
== REG_PC
)
6939 inst
.error
= _("pc may not be used with write-back");
6944 inst
.error
= _("instruction does not support writeback");
6947 inst
.instruction
|= WRITE_BACK
;
6951 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6952 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6953 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6954 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6957 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6959 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6965 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6966 Determine whether it can be performed with a move instruction; if
6967 it can, convert inst.instruction to that move instruction and
6968 return TRUE; if it can't, convert inst.instruction to a literal-pool
6969 load and return FALSE. If this is not a valid thing to do in the
6970 current context, set inst.error and return TRUE.
6972 inst.operands[i] describes the destination register. */
6975 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6980 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6984 if ((inst
.instruction
& tbit
) == 0)
6986 inst
.error
= _("invalid pseudo operation");
6989 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6991 inst
.error
= _("constant expression expected");
6994 if (inst
.reloc
.exp
.X_op
== O_constant
)
6998 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7000 /* This can be done with a mov(1) instruction. */
7001 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7002 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7008 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7011 /* This can be done with a mov instruction. */
7012 inst
.instruction
&= LITERAL_MASK
;
7013 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7014 inst
.instruction
|= value
& 0xfff;
7018 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7021 /* This can be done with a mvn instruction. */
7022 inst
.instruction
&= LITERAL_MASK
;
7023 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7024 inst
.instruction
|= value
& 0xfff;
7030 if (add_to_lit_pool () == FAIL
)
7032 inst
.error
= _("literal pool insertion failed");
7035 inst
.operands
[1].reg
= REG_PC
;
7036 inst
.operands
[1].isreg
= 1;
7037 inst
.operands
[1].preind
= 1;
7038 inst
.reloc
.pc_rel
= 1;
7039 inst
.reloc
.type
= (thumb_p
7040 ? BFD_RELOC_ARM_THUMB_OFFSET
7042 ? BFD_RELOC_ARM_HWLITERAL
7043 : BFD_RELOC_ARM_LITERAL
));
7047 /* Functions for instruction encoding, sorted by sub-architecture.
7048 First some generics; their names are taken from the conventional
7049 bit positions for register arguments in ARM format instructions. */
7059 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7065 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7066 inst
.instruction
|= inst
.operands
[1].reg
;
7072 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7073 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7079 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7080 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7086 unsigned Rn
= inst
.operands
[2].reg
;
7087 /* Enforce restrictions on SWP instruction. */
7088 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7090 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7091 _("Rn must not overlap other operands"));
7093 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7094 if (warn_on_deprecated
7095 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7096 as_warn (_("swp{b} use is deprecated for this architecture"));
7099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7100 inst
.instruction
|= inst
.operands
[1].reg
;
7101 inst
.instruction
|= Rn
<< 16;
7107 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7108 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7109 inst
.instruction
|= inst
.operands
[2].reg
;
7115 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7116 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7117 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7118 || inst
.reloc
.exp
.X_add_number
!= 0),
7120 inst
.instruction
|= inst
.operands
[0].reg
;
7121 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7122 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7128 inst
.instruction
|= inst
.operands
[0].imm
;
7134 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7135 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7138 /* ARM instructions, in alphabetical order by function name (except
7139 that wrapper functions appear immediately after the function they
7142 /* This is a pseudo-op of the form "adr rd, label" to be converted
7143 into a relative address of the form "add rd, pc, #label-.-8". */
7148 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7150 /* Frag hacking will turn this into a sub instruction if the offset turns
7151 out to be negative. */
7152 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7153 inst
.reloc
.pc_rel
= 1;
7154 inst
.reloc
.exp
.X_add_number
-= 8;
7157 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7158 into a relative address of the form:
7159 add rd, pc, #low(label-.-8)"
7160 add rd, rd, #high(label-.-8)" */
7165 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7167 /* Frag hacking will turn this into a sub instruction if the offset turns
7168 out to be negative. */
7169 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7170 inst
.reloc
.pc_rel
= 1;
7171 inst
.size
= INSN_SIZE
* 2;
7172 inst
.reloc
.exp
.X_add_number
-= 8;
7178 if (!inst
.operands
[1].present
)
7179 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7180 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7181 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7182 encode_arm_shifter_operand (2);
7188 if (inst
.operands
[0].present
)
7190 constraint ((inst
.instruction
& 0xf0) != 0x40
7191 && inst
.operands
[0].imm
> 0xf
7192 && inst
.operands
[0].imm
< 0x0,
7193 _("bad barrier type"));
7194 inst
.instruction
|= inst
.operands
[0].imm
;
7197 inst
.instruction
|= 0xf;
7203 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7204 constraint (msb
> 32, _("bit-field extends past end of register"));
7205 /* The instruction encoding stores the LSB and MSB,
7206 not the LSB and width. */
7207 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7208 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7209 inst
.instruction
|= (msb
- 1) << 16;
7217 /* #0 in second position is alternative syntax for bfc, which is
7218 the same instruction but with REG_PC in the Rm field. */
7219 if (!inst
.operands
[1].isreg
)
7220 inst
.operands
[1].reg
= REG_PC
;
7222 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7223 constraint (msb
> 32, _("bit-field extends past end of register"));
7224 /* The instruction encoding stores the LSB and MSB,
7225 not the LSB and width. */
7226 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7227 inst
.instruction
|= inst
.operands
[1].reg
;
7228 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7229 inst
.instruction
|= (msb
- 1) << 16;
7235 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7236 _("bit-field extends past end of register"));
7237 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7238 inst
.instruction
|= inst
.operands
[1].reg
;
7239 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7240 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7243 /* ARM V5 breakpoint instruction (argument parse)
7244 BKPT <16 bit unsigned immediate>
7245 Instruction is not conditional.
7246 The bit pattern given in insns[] has the COND_ALWAYS condition,
7247 and it is an error if the caller tried to override that. */
7252 /* Top 12 of 16 bits to bits 19:8. */
7253 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7255 /* Bottom 4 of 16 bits to bits 3:0. */
7256 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7260 encode_branch (int default_reloc
)
7262 if (inst
.operands
[0].hasreloc
)
7264 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7265 _("the only suffix valid here is '(plt)'"));
7266 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7270 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7272 inst
.reloc
.pc_rel
= 1;
7279 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7280 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7283 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7290 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7292 if (inst
.cond
== COND_ALWAYS
)
7293 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7295 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7299 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7302 /* ARM V5 branch-link-exchange instruction (argument parse)
7303 BLX <target_addr> ie BLX(1)
7304 BLX{<condition>} <Rm> ie BLX(2)
7305 Unfortunately, there are two different opcodes for this mnemonic.
7306 So, the insns[].value is not used, and the code here zaps values
7307 into inst.instruction.
7308 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7313 if (inst
.operands
[0].isreg
)
7315 /* Arg is a register; the opcode provided by insns[] is correct.
7316 It is not illegal to do "blx pc", just useless. */
7317 if (inst
.operands
[0].reg
== REG_PC
)
7318 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7320 inst
.instruction
|= inst
.operands
[0].reg
;
7324 /* Arg is an address; this instruction cannot be executed
7325 conditionally, and the opcode must be adjusted.
7326 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7327 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7328 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7329 inst
.instruction
= 0xfa000000;
7330 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7337 bfd_boolean want_reloc
;
7339 if (inst
.operands
[0].reg
== REG_PC
)
7340 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7342 inst
.instruction
|= inst
.operands
[0].reg
;
7343 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7344 it is for ARMv4t or earlier. */
7345 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7346 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7350 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7355 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7359 /* ARM v5TEJ. Jump to Jazelle code. */
7364 if (inst
.operands
[0].reg
== REG_PC
)
7365 as_tsktsk (_("use of r15 in bxj is not really useful"));
7367 inst
.instruction
|= inst
.operands
[0].reg
;
7370 /* Co-processor data operation:
7371 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7372 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7376 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7377 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7378 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7379 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7380 inst
.instruction
|= inst
.operands
[4].reg
;
7381 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7387 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7388 encode_arm_shifter_operand (1);
7391 /* Transfer between coprocessor and ARM registers.
7392 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7397 No special properties. */
7404 Rd
= inst
.operands
[2].reg
;
7407 if (inst
.instruction
== 0xee000010
7408 || inst
.instruction
== 0xfe000010)
7410 reject_bad_reg (Rd
);
7413 constraint (Rd
== REG_SP
, BAD_SP
);
7418 if (inst
.instruction
== 0xe000010)
7419 constraint (Rd
== REG_PC
, BAD_PC
);
7423 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7424 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7425 inst
.instruction
|= Rd
<< 12;
7426 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7427 inst
.instruction
|= inst
.operands
[4].reg
;
7428 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7431 /* Transfer between coprocessor register and pair of ARM registers.
7432 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7437 Two XScale instructions are special cases of these:
7439 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7440 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7442 Result unpredictable if Rd or Rn is R15. */
7449 Rd
= inst
.operands
[2].reg
;
7450 Rn
= inst
.operands
[3].reg
;
7454 reject_bad_reg (Rd
);
7455 reject_bad_reg (Rn
);
7459 constraint (Rd
== REG_PC
, BAD_PC
);
7460 constraint (Rn
== REG_PC
, BAD_PC
);
7463 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7464 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7465 inst
.instruction
|= Rd
<< 12;
7466 inst
.instruction
|= Rn
<< 16;
7467 inst
.instruction
|= inst
.operands
[4].reg
;
7473 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7474 if (inst
.operands
[1].present
)
7476 inst
.instruction
|= CPSI_MMOD
;
7477 inst
.instruction
|= inst
.operands
[1].imm
;
7484 inst
.instruction
|= inst
.operands
[0].imm
;
7490 /* There is no IT instruction in ARM mode. We
7491 process it to do the validation as if in
7492 thumb mode, just in case the code gets
7493 assembled for thumb using the unified syntax. */
7498 set_it_insn_type (IT_INSN
);
7499 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7500 now_it
.cc
= inst
.operands
[0].imm
;
7507 int base_reg
= inst
.operands
[0].reg
;
7508 int range
= inst
.operands
[1].imm
;
7510 inst
.instruction
|= base_reg
<< 16;
7511 inst
.instruction
|= range
;
7513 if (inst
.operands
[1].writeback
)
7514 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7516 if (inst
.operands
[0].writeback
)
7518 inst
.instruction
|= WRITE_BACK
;
7519 /* Check for unpredictable uses of writeback. */
7520 if (inst
.instruction
& LOAD_BIT
)
7522 /* Not allowed in LDM type 2. */
7523 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7524 && ((range
& (1 << REG_PC
)) == 0))
7525 as_warn (_("writeback of base register is UNPREDICTABLE"));
7526 /* Only allowed if base reg not in list for other types. */
7527 else if (range
& (1 << base_reg
))
7528 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7532 /* Not allowed for type 2. */
7533 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7534 as_warn (_("writeback of base register is UNPREDICTABLE"));
7535 /* Only allowed if base reg not in list, or first in list. */
7536 else if ((range
& (1 << base_reg
))
7537 && (range
& ((1 << base_reg
) - 1)))
7538 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7543 /* ARMv5TE load-consecutive (argument parse)
7552 constraint (inst
.operands
[0].reg
% 2 != 0,
7553 _("first destination register must be even"));
7554 constraint (inst
.operands
[1].present
7555 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7556 _("can only load two consecutive registers"));
7557 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7558 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7560 if (!inst
.operands
[1].present
)
7561 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7563 if (inst
.instruction
& LOAD_BIT
)
7565 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7566 register and the first register written; we have to diagnose
7567 overlap between the base and the second register written here. */
7569 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7570 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7571 as_warn (_("base register written back, and overlaps "
7572 "second destination register"));
7574 /* For an index-register load, the index register must not overlap the
7575 destination (even if not write-back). */
7576 else if (inst
.operands
[2].immisreg
7577 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7578 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7579 as_warn (_("index register overlaps destination register"));
7582 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7583 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7589 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7590 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7591 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7592 || inst
.operands
[1].negative
7593 /* This can arise if the programmer has written
7595 or if they have mistakenly used a register name as the last
7598 It is very difficult to distinguish between these two cases
7599 because "rX" might actually be a label. ie the register
7600 name has been occluded by a symbol of the same name. So we
7601 just generate a general 'bad addressing mode' type error
7602 message and leave it up to the programmer to discover the
7603 true cause and fix their mistake. */
7604 || (inst
.operands
[1].reg
== REG_PC
),
7607 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7608 || inst
.reloc
.exp
.X_add_number
!= 0,
7609 _("offset must be zero in ARM encoding"));
7611 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7613 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7614 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7615 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7621 constraint (inst
.operands
[0].reg
% 2 != 0,
7622 _("even register required"));
7623 constraint (inst
.operands
[1].present
7624 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7625 _("can only load two consecutive registers"));
7626 /* If op 1 were present and equal to PC, this function wouldn't
7627 have been called in the first place. */
7628 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7630 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7631 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7637 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7638 if (!inst
.operands
[1].isreg
)
7639 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7641 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7647 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7649 if (inst
.operands
[1].preind
)
7651 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7652 || inst
.reloc
.exp
.X_add_number
!= 0,
7653 _("this instruction requires a post-indexed address"));
7655 inst
.operands
[1].preind
= 0;
7656 inst
.operands
[1].postind
= 1;
7657 inst
.operands
[1].writeback
= 1;
7659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7660 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7663 /* Halfword and signed-byte load/store operations. */
7668 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7669 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7670 if (!inst
.operands
[1].isreg
)
7671 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7673 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7679 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7681 if (inst
.operands
[1].preind
)
7683 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7684 || inst
.reloc
.exp
.X_add_number
!= 0,
7685 _("this instruction requires a post-indexed address"));
7687 inst
.operands
[1].preind
= 0;
7688 inst
.operands
[1].postind
= 1;
7689 inst
.operands
[1].writeback
= 1;
7691 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7692 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7695 /* Co-processor register load/store.
7696 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7700 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7701 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7702 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7708 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7709 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7710 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7711 && !(inst
.instruction
& 0x00400000))
7712 as_tsktsk (_("Rd and Rm should be different in mla"));
7714 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7715 inst
.instruction
|= inst
.operands
[1].reg
;
7716 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7717 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7723 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7724 encode_arm_shifter_operand (1);
7727 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7734 top
= (inst
.instruction
& 0x00400000) != 0;
7735 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7736 _(":lower16: not allowed this instruction"));
7737 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7738 _(":upper16: not allowed instruction"));
7739 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7740 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7742 imm
= inst
.reloc
.exp
.X_add_number
;
7743 /* The value is in two pieces: 0:11, 16:19. */
7744 inst
.instruction
|= (imm
& 0x00000fff);
7745 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7749 static void do_vfp_nsyn_opcode (const char *);
7752 do_vfp_nsyn_mrs (void)
7754 if (inst
.operands
[0].isvec
)
7756 if (inst
.operands
[1].reg
!= 1)
7757 first_error (_("operand 1 must be FPSCR"));
7758 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7759 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7760 do_vfp_nsyn_opcode ("fmstat");
7762 else if (inst
.operands
[1].isvec
)
7763 do_vfp_nsyn_opcode ("fmrx");
7771 do_vfp_nsyn_msr (void)
7773 if (inst
.operands
[0].isvec
)
7774 do_vfp_nsyn_opcode ("fmxr");
7784 unsigned Rt
= inst
.operands
[0].reg
;
7786 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7788 inst
.error
= BAD_SP
;
7792 /* APSR_ sets isvec. All other refs to PC are illegal. */
7793 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7795 inst
.error
= BAD_PC
;
7799 if (inst
.operands
[1].reg
!= 1)
7800 first_error (_("operand 1 must be FPSCR"));
7802 inst
.instruction
|= (Rt
<< 12);
7808 unsigned Rt
= inst
.operands
[1].reg
;
7811 reject_bad_reg (Rt
);
7812 else if (Rt
== REG_PC
)
7814 inst
.error
= BAD_PC
;
7818 if (inst
.operands
[0].reg
!= 1)
7819 first_error (_("operand 0 must be FPSCR"));
7821 inst
.instruction
|= (Rt
<< 12);
7827 if (do_vfp_nsyn_mrs () == SUCCESS
)
7830 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7831 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7833 _("'CPSR' or 'SPSR' expected"));
7834 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7835 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7836 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7839 /* Two possible forms:
7840 "{C|S}PSR_<field>, Rm",
7841 "{C|S}PSR_f, #expression". */
7846 if (do_vfp_nsyn_msr () == SUCCESS
)
7849 inst
.instruction
|= inst
.operands
[0].imm
;
7850 if (inst
.operands
[1].isreg
)
7851 inst
.instruction
|= inst
.operands
[1].reg
;
7854 inst
.instruction
|= INST_IMMEDIATE
;
7855 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7856 inst
.reloc
.pc_rel
= 0;
7863 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7865 if (!inst
.operands
[2].present
)
7866 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7867 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7868 inst
.instruction
|= inst
.operands
[1].reg
;
7869 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7871 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7872 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7873 as_tsktsk (_("Rd and Rm should be different in mul"));
7876 /* Long Multiply Parser
7877 UMULL RdLo, RdHi, Rm, Rs
7878 SMULL RdLo, RdHi, Rm, Rs
7879 UMLAL RdLo, RdHi, Rm, Rs
7880 SMLAL RdLo, RdHi, Rm, Rs. */
7885 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7886 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7887 inst
.instruction
|= inst
.operands
[2].reg
;
7888 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7890 /* rdhi and rdlo must be different. */
7891 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7892 as_tsktsk (_("rdhi and rdlo must be different"));
7894 /* rdhi, rdlo and rm must all be different before armv6. */
7895 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7896 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7897 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7898 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7904 if (inst
.operands
[0].present
7905 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7907 /* Architectural NOP hints are CPSR sets with no bits selected. */
7908 inst
.instruction
&= 0xf0000000;
7909 inst
.instruction
|= 0x0320f000;
7910 if (inst
.operands
[0].present
)
7911 inst
.instruction
|= inst
.operands
[0].imm
;
7915 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7916 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7917 Condition defaults to COND_ALWAYS.
7918 Error if Rd, Rn or Rm are R15. */
7923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7924 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7925 inst
.instruction
|= inst
.operands
[2].reg
;
7926 if (inst
.operands
[3].present
)
7927 encode_arm_shift (3);
7930 /* ARM V6 PKHTB (Argument Parse). */
7935 if (!inst
.operands
[3].present
)
7937 /* If the shift specifier is omitted, turn the instruction
7938 into pkhbt rd, rm, rn. */
7939 inst
.instruction
&= 0xfff00010;
7940 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7941 inst
.instruction
|= inst
.operands
[1].reg
;
7942 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7947 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7948 inst
.instruction
|= inst
.operands
[2].reg
;
7949 encode_arm_shift (3);
7953 /* ARMv5TE: Preload-Cache
7957 Syntactically, like LDR with B=1, W=0, L=1. */
7962 constraint (!inst
.operands
[0].isreg
,
7963 _("'[' expected after PLD mnemonic"));
7964 constraint (inst
.operands
[0].postind
,
7965 _("post-indexed expression used in preload instruction"));
7966 constraint (inst
.operands
[0].writeback
,
7967 _("writeback used in preload instruction"));
7968 constraint (!inst
.operands
[0].preind
,
7969 _("unindexed addressing used in preload instruction"));
7970 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7973 /* ARMv7: PLI <addr_mode> */
7977 constraint (!inst
.operands
[0].isreg
,
7978 _("'[' expected after PLI mnemonic"));
7979 constraint (inst
.operands
[0].postind
,
7980 _("post-indexed expression used in preload instruction"));
7981 constraint (inst
.operands
[0].writeback
,
7982 _("writeback used in preload instruction"));
7983 constraint (!inst
.operands
[0].preind
,
7984 _("unindexed addressing used in preload instruction"));
7985 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7986 inst
.instruction
&= ~PRE_INDEX
;
7992 inst
.operands
[1] = inst
.operands
[0];
7993 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7994 inst
.operands
[0].isreg
= 1;
7995 inst
.operands
[0].writeback
= 1;
7996 inst
.operands
[0].reg
= REG_SP
;
8000 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8001 word at the specified address and the following word
8003 Unconditionally executed.
8004 Error if Rn is R15. */
8009 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8010 if (inst
.operands
[0].writeback
)
8011 inst
.instruction
|= WRITE_BACK
;
8014 /* ARM V6 ssat (argument parse). */
8019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8020 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8021 inst
.instruction
|= inst
.operands
[2].reg
;
8023 if (inst
.operands
[3].present
)
8024 encode_arm_shift (3);
8027 /* ARM V6 usat (argument parse). */
8032 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8033 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8034 inst
.instruction
|= inst
.operands
[2].reg
;
8036 if (inst
.operands
[3].present
)
8037 encode_arm_shift (3);
8040 /* ARM V6 ssat16 (argument parse). */
8045 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8046 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8047 inst
.instruction
|= inst
.operands
[2].reg
;
8053 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8054 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8055 inst
.instruction
|= inst
.operands
[2].reg
;
8058 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8059 preserving the other bits.
8061 setend <endian_specifier>, where <endian_specifier> is either
8067 if (inst
.operands
[0].imm
)
8068 inst
.instruction
|= 0x200;
8074 unsigned int Rm
= (inst
.operands
[1].present
8075 ? inst
.operands
[1].reg
8076 : inst
.operands
[0].reg
);
8078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8079 inst
.instruction
|= Rm
;
8080 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8082 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8083 inst
.instruction
|= SHIFT_BY_REG
;
8086 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8092 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8093 inst
.reloc
.pc_rel
= 0;
8099 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8100 inst
.reloc
.pc_rel
= 0;
8103 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8104 SMLAxy{cond} Rd,Rm,Rs,Rn
8105 SMLAWy{cond} Rd,Rm,Rs,Rn
8106 Error if any register is R15. */
8111 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8112 inst
.instruction
|= inst
.operands
[1].reg
;
8113 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8114 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8117 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8118 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8119 Error if any register is R15.
8120 Warning if Rdlo == Rdhi. */
8125 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8126 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8127 inst
.instruction
|= inst
.operands
[2].reg
;
8128 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8130 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8131 as_tsktsk (_("rdhi and rdlo must be different"));
8134 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8135 SMULxy{cond} Rd,Rm,Rs
8136 Error if any register is R15. */
8141 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8142 inst
.instruction
|= inst
.operands
[1].reg
;
8143 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8146 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8147 the same for both ARM and Thumb-2. */
8154 if (inst
.operands
[0].present
)
8156 reg
= inst
.operands
[0].reg
;
8157 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8162 inst
.instruction
|= reg
<< 16;
8163 inst
.instruction
|= inst
.operands
[1].imm
;
8164 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8165 inst
.instruction
|= WRITE_BACK
;
8168 /* ARM V6 strex (argument parse). */
8173 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8174 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8175 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8176 || inst
.operands
[2].negative
8177 /* See comment in do_ldrex(). */
8178 || (inst
.operands
[2].reg
== REG_PC
),
8181 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8182 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8184 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8185 || inst
.reloc
.exp
.X_add_number
!= 0,
8186 _("offset must be zero in ARM encoding"));
8188 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8189 inst
.instruction
|= inst
.operands
[1].reg
;
8190 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8191 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8197 constraint (inst
.operands
[1].reg
% 2 != 0,
8198 _("even register required"));
8199 constraint (inst
.operands
[2].present
8200 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8201 _("can only store two consecutive registers"));
8202 /* If op 2 were present and equal to PC, this function wouldn't
8203 have been called in the first place. */
8204 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8206 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8207 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8208 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8211 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8212 inst
.instruction
|= inst
.operands
[1].reg
;
8213 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8216 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8217 extends it to 32-bits, and adds the result to a value in another
8218 register. You can specify a rotation by 0, 8, 16, or 24 bits
8219 before extracting the 16-bit value.
8220 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8221 Condition defaults to COND_ALWAYS.
8222 Error if any register uses R15. */
8227 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8228 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8229 inst
.instruction
|= inst
.operands
[2].reg
;
8230 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8235 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8236 Condition defaults to COND_ALWAYS.
8237 Error if any register uses R15. */
8242 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8243 inst
.instruction
|= inst
.operands
[1].reg
;
8244 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8247 /* VFP instructions. In a logical order: SP variant first, monad
8248 before dyad, arithmetic then move then load/store. */
8251 do_vfp_sp_monadic (void)
8253 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8254 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8258 do_vfp_sp_dyadic (void)
8260 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8261 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8262 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8266 do_vfp_sp_compare_z (void)
8268 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8272 do_vfp_dp_sp_cvt (void)
8274 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8275 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8279 do_vfp_sp_dp_cvt (void)
8281 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8282 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8286 do_vfp_reg_from_sp (void)
8288 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8289 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8293 do_vfp_reg2_from_sp2 (void)
8295 constraint (inst
.operands
[2].imm
!= 2,
8296 _("only two consecutive VFP SP registers allowed here"));
8297 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8298 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8299 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8303 do_vfp_sp_from_reg (void)
8305 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8306 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8310 do_vfp_sp2_from_reg2 (void)
8312 constraint (inst
.operands
[0].imm
!= 2,
8313 _("only two consecutive VFP SP registers allowed here"));
8314 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8315 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8316 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8320 do_vfp_sp_ldst (void)
8322 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8323 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8327 do_vfp_dp_ldst (void)
8329 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8330 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8335 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8337 if (inst
.operands
[0].writeback
)
8338 inst
.instruction
|= WRITE_BACK
;
8340 constraint (ldstm_type
!= VFP_LDSTMIA
,
8341 _("this addressing mode requires base-register writeback"));
8342 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8343 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8344 inst
.instruction
|= inst
.operands
[1].imm
;
8348 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8352 if (inst
.operands
[0].writeback
)
8353 inst
.instruction
|= WRITE_BACK
;
8355 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8356 _("this addressing mode requires base-register writeback"));
8358 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8359 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8361 count
= inst
.operands
[1].imm
<< 1;
8362 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8365 inst
.instruction
|= count
;
8369 do_vfp_sp_ldstmia (void)
8371 vfp_sp_ldstm (VFP_LDSTMIA
);
8375 do_vfp_sp_ldstmdb (void)
8377 vfp_sp_ldstm (VFP_LDSTMDB
);
8381 do_vfp_dp_ldstmia (void)
8383 vfp_dp_ldstm (VFP_LDSTMIA
);
8387 do_vfp_dp_ldstmdb (void)
8389 vfp_dp_ldstm (VFP_LDSTMDB
);
8393 do_vfp_xp_ldstmia (void)
8395 vfp_dp_ldstm (VFP_LDSTMIAX
);
8399 do_vfp_xp_ldstmdb (void)
8401 vfp_dp_ldstm (VFP_LDSTMDBX
);
8405 do_vfp_dp_rd_rm (void)
8407 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8408 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8412 do_vfp_dp_rn_rd (void)
8414 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8415 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8419 do_vfp_dp_rd_rn (void)
8421 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8422 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8426 do_vfp_dp_rd_rn_rm (void)
8428 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8429 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8430 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8436 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8440 do_vfp_dp_rm_rd_rn (void)
8442 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8443 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8444 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8447 /* VFPv3 instructions. */
8449 do_vfp_sp_const (void)
8451 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8452 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8453 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8457 do_vfp_dp_const (void)
8459 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8460 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8461 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8465 vfp_conv (int srcsize
)
8467 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8468 inst
.instruction
|= (immbits
& 1) << 5;
8469 inst
.instruction
|= (immbits
>> 1);
8473 do_vfp_sp_conv_16 (void)
8475 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8480 do_vfp_dp_conv_16 (void)
8482 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8487 do_vfp_sp_conv_32 (void)
8489 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8494 do_vfp_dp_conv_32 (void)
8496 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8500 /* FPA instructions. Also in a logical order. */
8505 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8506 inst
.instruction
|= inst
.operands
[1].reg
;
8510 do_fpa_ldmstm (void)
8512 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8513 switch (inst
.operands
[1].imm
)
8515 case 1: inst
.instruction
|= CP_T_X
; break;
8516 case 2: inst
.instruction
|= CP_T_Y
; break;
8517 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8522 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8524 /* The instruction specified "ea" or "fd", so we can only accept
8525 [Rn]{!}. The instruction does not really support stacking or
8526 unstacking, so we have to emulate these by setting appropriate
8527 bits and offsets. */
8528 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8529 || inst
.reloc
.exp
.X_add_number
!= 0,
8530 _("this instruction does not support indexing"));
8532 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8533 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8535 if (!(inst
.instruction
& INDEX_UP
))
8536 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8538 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8540 inst
.operands
[2].preind
= 0;
8541 inst
.operands
[2].postind
= 1;
8545 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8548 /* iWMMXt instructions: strictly in alphabetical order. */
8551 do_iwmmxt_tandorc (void)
8553 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8557 do_iwmmxt_textrc (void)
8559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8560 inst
.instruction
|= inst
.operands
[1].imm
;
8564 do_iwmmxt_textrm (void)
8566 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8567 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8568 inst
.instruction
|= inst
.operands
[2].imm
;
8572 do_iwmmxt_tinsr (void)
8574 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8575 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8576 inst
.instruction
|= inst
.operands
[2].imm
;
8580 do_iwmmxt_tmia (void)
8582 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8583 inst
.instruction
|= inst
.operands
[1].reg
;
8584 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8588 do_iwmmxt_waligni (void)
8590 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8591 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8592 inst
.instruction
|= inst
.operands
[2].reg
;
8593 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8597 do_iwmmxt_wmerge (void)
8599 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8600 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8601 inst
.instruction
|= inst
.operands
[2].reg
;
8602 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8606 do_iwmmxt_wmov (void)
8608 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8609 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8610 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8611 inst
.instruction
|= inst
.operands
[1].reg
;
8615 do_iwmmxt_wldstbh (void)
8618 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8620 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8622 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8623 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8627 do_iwmmxt_wldstw (void)
8629 /* RIWR_RIWC clears .isreg for a control register. */
8630 if (!inst
.operands
[0].isreg
)
8632 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8633 inst
.instruction
|= 0xf0000000;
8636 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8637 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8641 do_iwmmxt_wldstd (void)
8643 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8644 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8645 && inst
.operands
[1].immisreg
)
8647 inst
.instruction
&= ~0x1a000ff;
8648 inst
.instruction
|= (0xf << 28);
8649 if (inst
.operands
[1].preind
)
8650 inst
.instruction
|= PRE_INDEX
;
8651 if (!inst
.operands
[1].negative
)
8652 inst
.instruction
|= INDEX_UP
;
8653 if (inst
.operands
[1].writeback
)
8654 inst
.instruction
|= WRITE_BACK
;
8655 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8656 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8657 inst
.instruction
|= inst
.operands
[1].imm
;
8660 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8664 do_iwmmxt_wshufh (void)
8666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8667 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8668 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8669 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8673 do_iwmmxt_wzero (void)
8675 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8676 inst
.instruction
|= inst
.operands
[0].reg
;
8677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8678 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8682 do_iwmmxt_wrwrwr_or_imm5 (void)
8684 if (inst
.operands
[2].isreg
)
8687 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8688 _("immediate operand requires iWMMXt2"));
8690 if (inst
.operands
[2].imm
== 0)
8692 switch ((inst
.instruction
>> 20) & 0xf)
8698 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8699 inst
.operands
[2].imm
= 16;
8700 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8706 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8707 inst
.operands
[2].imm
= 32;
8708 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8715 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8717 wrn
= (inst
.instruction
>> 16) & 0xf;
8718 inst
.instruction
&= 0xff0fff0f;
8719 inst
.instruction
|= wrn
;
8720 /* Bail out here; the instruction is now assembled. */
8725 /* Map 32 -> 0, etc. */
8726 inst
.operands
[2].imm
&= 0x1f;
8727 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8731 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8732 operations first, then control, shift, and load/store. */
8734 /* Insns like "foo X,Y,Z". */
8737 do_mav_triple (void)
8739 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8740 inst
.instruction
|= inst
.operands
[1].reg
;
8741 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8744 /* Insns like "foo W,X,Y,Z".
8745 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8750 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8751 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8752 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8753 inst
.instruction
|= inst
.operands
[3].reg
;
8756 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8760 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8763 /* Maverick shift immediate instructions.
8764 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8765 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8770 int imm
= inst
.operands
[2].imm
;
8772 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8773 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8775 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8776 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8777 Bit 4 should be 0. */
8778 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8780 inst
.instruction
|= imm
;
8783 /* XScale instructions. Also sorted arithmetic before move. */
8785 /* Xscale multiply-accumulate (argument parse)
8788 MIAxycc acc0,Rm,Rs. */
8793 inst
.instruction
|= inst
.operands
[1].reg
;
8794 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8797 /* Xscale move-accumulator-register (argument parse)
8799 MARcc acc0,RdLo,RdHi. */
8804 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8805 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8808 /* Xscale move-register-accumulator (argument parse)
8810 MRAcc RdLo,RdHi,acc0. */
8815 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8816 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8817 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8820 /* Encoding functions relevant only to Thumb. */
8822 /* inst.operands[i] is a shifted-register operand; encode
8823 it into inst.instruction in the format used by Thumb32. */
8826 encode_thumb32_shifted_operand (int i
)
8828 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8829 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8831 constraint (inst
.operands
[i
].immisreg
,
8832 _("shift by register not allowed in thumb mode"));
8833 inst
.instruction
|= inst
.operands
[i
].reg
;
8834 if (shift
== SHIFT_RRX
)
8835 inst
.instruction
|= SHIFT_ROR
<< 4;
8838 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8839 _("expression too complex"));
8841 constraint (value
> 32
8842 || (value
== 32 && (shift
== SHIFT_LSL
8843 || shift
== SHIFT_ROR
)),
8844 _("shift expression is too large"));
8848 else if (value
== 32)
8851 inst
.instruction
|= shift
<< 4;
8852 inst
.instruction
|= (value
& 0x1c) << 10;
8853 inst
.instruction
|= (value
& 0x03) << 6;
8858 /* inst.operands[i] was set up by parse_address. Encode it into a
8859 Thumb32 format load or store instruction. Reject forms that cannot
8860 be used with such instructions. If is_t is true, reject forms that
8861 cannot be used with a T instruction; if is_d is true, reject forms
8862 that cannot be used with a D instruction. If it is a store insn,
8866 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8868 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8870 constraint (!inst
.operands
[i
].isreg
,
8871 _("Instruction does not support =N addresses"));
8873 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8874 if (inst
.operands
[i
].immisreg
)
8876 constraint (is_pc
, BAD_PC_ADDRESSING
);
8877 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8878 constraint (inst
.operands
[i
].negative
,
8879 _("Thumb does not support negative register indexing"));
8880 constraint (inst
.operands
[i
].postind
,
8881 _("Thumb does not support register post-indexing"));
8882 constraint (inst
.operands
[i
].writeback
,
8883 _("Thumb does not support register indexing with writeback"));
8884 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8885 _("Thumb supports only LSL in shifted register indexing"));
8887 inst
.instruction
|= inst
.operands
[i
].imm
;
8888 if (inst
.operands
[i
].shifted
)
8890 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8891 _("expression too complex"));
8892 constraint (inst
.reloc
.exp
.X_add_number
< 0
8893 || inst
.reloc
.exp
.X_add_number
> 3,
8894 _("shift out of range"));
8895 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8897 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8899 else if (inst
.operands
[i
].preind
)
8901 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8902 constraint (is_t
&& inst
.operands
[i
].writeback
,
8903 _("cannot use writeback with this instruction"));
8904 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8905 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8909 inst
.instruction
|= 0x01000000;
8910 if (inst
.operands
[i
].writeback
)
8911 inst
.instruction
|= 0x00200000;
8915 inst
.instruction
|= 0x00000c00;
8916 if (inst
.operands
[i
].writeback
)
8917 inst
.instruction
|= 0x00000100;
8919 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8921 else if (inst
.operands
[i
].postind
)
8923 gas_assert (inst
.operands
[i
].writeback
);
8924 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8925 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8928 inst
.instruction
|= 0x00200000;
8930 inst
.instruction
|= 0x00000900;
8931 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8933 else /* unindexed - only for coprocessor */
8934 inst
.error
= _("instruction does not accept unindexed addressing");
8937 /* Table of Thumb instructions which exist in both 16- and 32-bit
8938 encodings (the latter only in post-V6T2 cores). The index is the
8939 value used in the insns table below. When there is more than one
8940 possible 16-bit encoding for the instruction, this table always
8942 Also contains several pseudo-instructions used during relaxation. */
8943 #define T16_32_TAB \
8944 X(_adc, 4140, eb400000), \
8945 X(_adcs, 4140, eb500000), \
8946 X(_add, 1c00, eb000000), \
8947 X(_adds, 1c00, eb100000), \
8948 X(_addi, 0000, f1000000), \
8949 X(_addis, 0000, f1100000), \
8950 X(_add_pc,000f, f20f0000), \
8951 X(_add_sp,000d, f10d0000), \
8952 X(_adr, 000f, f20f0000), \
8953 X(_and, 4000, ea000000), \
8954 X(_ands, 4000, ea100000), \
8955 X(_asr, 1000, fa40f000), \
8956 X(_asrs, 1000, fa50f000), \
8957 X(_b, e000, f000b000), \
8958 X(_bcond, d000, f0008000), \
8959 X(_bic, 4380, ea200000), \
8960 X(_bics, 4380, ea300000), \
8961 X(_cmn, 42c0, eb100f00), \
8962 X(_cmp, 2800, ebb00f00), \
8963 X(_cpsie, b660, f3af8400), \
8964 X(_cpsid, b670, f3af8600), \
8965 X(_cpy, 4600, ea4f0000), \
8966 X(_dec_sp,80dd, f1ad0d00), \
8967 X(_eor, 4040, ea800000), \
8968 X(_eors, 4040, ea900000), \
8969 X(_inc_sp,00dd, f10d0d00), \
8970 X(_ldmia, c800, e8900000), \
8971 X(_ldr, 6800, f8500000), \
8972 X(_ldrb, 7800, f8100000), \
8973 X(_ldrh, 8800, f8300000), \
8974 X(_ldrsb, 5600, f9100000), \
8975 X(_ldrsh, 5e00, f9300000), \
8976 X(_ldr_pc,4800, f85f0000), \
8977 X(_ldr_pc2,4800, f85f0000), \
8978 X(_ldr_sp,9800, f85d0000), \
8979 X(_lsl, 0000, fa00f000), \
8980 X(_lsls, 0000, fa10f000), \
8981 X(_lsr, 0800, fa20f000), \
8982 X(_lsrs, 0800, fa30f000), \
8983 X(_mov, 2000, ea4f0000), \
8984 X(_movs, 2000, ea5f0000), \
8985 X(_mul, 4340, fb00f000), \
8986 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8987 X(_mvn, 43c0, ea6f0000), \
8988 X(_mvns, 43c0, ea7f0000), \
8989 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8990 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8991 X(_orr, 4300, ea400000), \
8992 X(_orrs, 4300, ea500000), \
8993 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8994 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8995 X(_rev, ba00, fa90f080), \
8996 X(_rev16, ba40, fa90f090), \
8997 X(_revsh, bac0, fa90f0b0), \
8998 X(_ror, 41c0, fa60f000), \
8999 X(_rors, 41c0, fa70f000), \
9000 X(_sbc, 4180, eb600000), \
9001 X(_sbcs, 4180, eb700000), \
9002 X(_stmia, c000, e8800000), \
9003 X(_str, 6000, f8400000), \
9004 X(_strb, 7000, f8000000), \
9005 X(_strh, 8000, f8200000), \
9006 X(_str_sp,9000, f84d0000), \
9007 X(_sub, 1e00, eba00000), \
9008 X(_subs, 1e00, ebb00000), \
9009 X(_subi, 8000, f1a00000), \
9010 X(_subis, 8000, f1b00000), \
9011 X(_sxtb, b240, fa4ff080), \
9012 X(_sxth, b200, fa0ff080), \
9013 X(_tst, 4200, ea100f00), \
9014 X(_uxtb, b2c0, fa5ff080), \
9015 X(_uxth, b280, fa1ff080), \
9016 X(_nop, bf00, f3af8000), \
9017 X(_yield, bf10, f3af8001), \
9018 X(_wfe, bf20, f3af8002), \
9019 X(_wfi, bf30, f3af8003), \
9020 X(_sev, bf40, f3af8004),
9022 /* To catch errors in encoding functions, the codes are all offset by
9023 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9024 as 16-bit instructions. */
9025 #define X(a,b,c) T_MNEM##a
9026 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9029 #define X(a,b,c) 0x##b
9030 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9031 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9034 #define X(a,b,c) 0x##c
9035 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9036 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9037 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9041 /* Thumb instruction encoders, in alphabetical order. */
9046 do_t_add_sub_w (void)
9050 Rd
= inst
.operands
[0].reg
;
9051 Rn
= inst
.operands
[1].reg
;
9053 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9054 is the SP-{plus,minus}-immediate form of the instruction. */
9056 constraint (Rd
== REG_PC
, BAD_PC
);
9058 reject_bad_reg (Rd
);
9060 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9061 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9064 /* Parse an add or subtract instruction. We get here with inst.instruction
9065 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9072 Rd
= inst
.operands
[0].reg
;
9073 Rs
= (inst
.operands
[1].present
9074 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9075 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9078 set_it_insn_type_last ();
9086 flags
= (inst
.instruction
== T_MNEM_adds
9087 || inst
.instruction
== T_MNEM_subs
);
9089 narrow
= !in_it_block ();
9091 narrow
= in_it_block ();
9092 if (!inst
.operands
[2].isreg
)
9096 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9098 add
= (inst
.instruction
== T_MNEM_add
9099 || inst
.instruction
== T_MNEM_adds
);
9101 if (inst
.size_req
!= 4)
9103 /* Attempt to use a narrow opcode, with relaxation if
9105 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9106 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9107 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9108 opcode
= T_MNEM_add_sp
;
9109 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9110 opcode
= T_MNEM_add_pc
;
9111 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9114 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9116 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9120 inst
.instruction
= THUMB_OP16(opcode
);
9121 inst
.instruction
|= (Rd
<< 4) | Rs
;
9122 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9123 if (inst
.size_req
!= 2)
9124 inst
.relax
= opcode
;
9127 constraint (inst
.size_req
== 2, BAD_HIREG
);
9129 if (inst
.size_req
== 4
9130 || (inst
.size_req
!= 2 && !opcode
))
9134 constraint (add
, BAD_PC
);
9135 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9136 _("only SUBS PC, LR, #const allowed"));
9137 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9138 _("expression too complex"));
9139 constraint (inst
.reloc
.exp
.X_add_number
< 0
9140 || inst
.reloc
.exp
.X_add_number
> 0xff,
9141 _("immediate value out of range"));
9142 inst
.instruction
= T2_SUBS_PC_LR
9143 | inst
.reloc
.exp
.X_add_number
;
9144 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9147 else if (Rs
== REG_PC
)
9149 /* Always use addw/subw. */
9150 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9151 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9155 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9156 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9159 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9161 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9163 inst
.instruction
|= Rd
<< 8;
9164 inst
.instruction
|= Rs
<< 16;
9169 Rn
= inst
.operands
[2].reg
;
9170 /* See if we can do this with a 16-bit instruction. */
9171 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9173 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9178 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9179 || inst
.instruction
== T_MNEM_add
)
9182 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9186 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9188 /* Thumb-1 cores (except v6-M) require at least one high
9189 register in a narrow non flag setting add. */
9190 if (Rd
> 7 || Rn
> 7
9191 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9192 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9199 inst
.instruction
= T_OPCODE_ADD_HI
;
9200 inst
.instruction
|= (Rd
& 8) << 4;
9201 inst
.instruction
|= (Rd
& 7);
9202 inst
.instruction
|= Rn
<< 3;
9208 constraint (Rd
== REG_PC
, BAD_PC
);
9209 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9210 constraint (Rs
== REG_PC
, BAD_PC
);
9211 reject_bad_reg (Rn
);
9213 /* If we get here, it can't be done in 16 bits. */
9214 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9215 _("shift must be constant"));
9216 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9217 inst
.instruction
|= Rd
<< 8;
9218 inst
.instruction
|= Rs
<< 16;
9219 encode_thumb32_shifted_operand (2);
9224 constraint (inst
.instruction
== T_MNEM_adds
9225 || inst
.instruction
== T_MNEM_subs
,
9228 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9230 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9231 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9234 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9236 inst
.instruction
|= (Rd
<< 4) | Rs
;
9237 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9241 Rn
= inst
.operands
[2].reg
;
9242 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9244 /* We now have Rd, Rs, and Rn set to registers. */
9245 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9247 /* Can't do this for SUB. */
9248 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9249 inst
.instruction
= T_OPCODE_ADD_HI
;
9250 inst
.instruction
|= (Rd
& 8) << 4;
9251 inst
.instruction
|= (Rd
& 7);
9253 inst
.instruction
|= Rn
<< 3;
9255 inst
.instruction
|= Rs
<< 3;
9257 constraint (1, _("dest must overlap one source register"));
9261 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9262 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9263 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9273 Rd
= inst
.operands
[0].reg
;
9274 reject_bad_reg (Rd
);
9276 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9278 /* Defer to section relaxation. */
9279 inst
.relax
= inst
.instruction
;
9280 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9281 inst
.instruction
|= Rd
<< 4;
9283 else if (unified_syntax
&& inst
.size_req
!= 2)
9285 /* Generate a 32-bit opcode. */
9286 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9287 inst
.instruction
|= Rd
<< 8;
9288 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9289 inst
.reloc
.pc_rel
= 1;
9293 /* Generate a 16-bit opcode. */
9294 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9295 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9296 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9297 inst
.reloc
.pc_rel
= 1;
9299 inst
.instruction
|= Rd
<< 4;
9303 /* Arithmetic instructions for which there is just one 16-bit
9304 instruction encoding, and it allows only two low registers.
9305 For maximal compatibility with ARM syntax, we allow three register
9306 operands even when Thumb-32 instructions are not available, as long
9307 as the first two are identical. For instance, both "sbc r0,r1" and
9308 "sbc r0,r0,r1" are allowed. */
9314 Rd
= inst
.operands
[0].reg
;
9315 Rs
= (inst
.operands
[1].present
9316 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9317 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9318 Rn
= inst
.operands
[2].reg
;
9320 reject_bad_reg (Rd
);
9321 reject_bad_reg (Rs
);
9322 if (inst
.operands
[2].isreg
)
9323 reject_bad_reg (Rn
);
9327 if (!inst
.operands
[2].isreg
)
9329 /* For an immediate, we always generate a 32-bit opcode;
9330 section relaxation will shrink it later if possible. */
9331 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9332 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9333 inst
.instruction
|= Rd
<< 8;
9334 inst
.instruction
|= Rs
<< 16;
9335 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9341 /* See if we can do this with a 16-bit instruction. */
9342 if (THUMB_SETS_FLAGS (inst
.instruction
))
9343 narrow
= !in_it_block ();
9345 narrow
= in_it_block ();
9347 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9349 if (inst
.operands
[2].shifted
)
9351 if (inst
.size_req
== 4)
9357 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9358 inst
.instruction
|= Rd
;
9359 inst
.instruction
|= Rn
<< 3;
9363 /* If we get here, it can't be done in 16 bits. */
9364 constraint (inst
.operands
[2].shifted
9365 && inst
.operands
[2].immisreg
,
9366 _("shift must be constant"));
9367 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9368 inst
.instruction
|= Rd
<< 8;
9369 inst
.instruction
|= Rs
<< 16;
9370 encode_thumb32_shifted_operand (2);
9375 /* On its face this is a lie - the instruction does set the
9376 flags. However, the only supported mnemonic in this mode
9378 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9380 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9381 _("unshifted register required"));
9382 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9383 constraint (Rd
!= Rs
,
9384 _("dest and source1 must be the same register"));
9386 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9387 inst
.instruction
|= Rd
;
9388 inst
.instruction
|= Rn
<< 3;
9392 /* Similarly, but for instructions where the arithmetic operation is
9393 commutative, so we can allow either of them to be different from
9394 the destination operand in a 16-bit instruction. For instance, all
9395 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9402 Rd
= inst
.operands
[0].reg
;
9403 Rs
= (inst
.operands
[1].present
9404 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9405 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9406 Rn
= inst
.operands
[2].reg
;
9408 reject_bad_reg (Rd
);
9409 reject_bad_reg (Rs
);
9410 if (inst
.operands
[2].isreg
)
9411 reject_bad_reg (Rn
);
9415 if (!inst
.operands
[2].isreg
)
9417 /* For an immediate, we always generate a 32-bit opcode;
9418 section relaxation will shrink it later if possible. */
9419 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9420 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9421 inst
.instruction
|= Rd
<< 8;
9422 inst
.instruction
|= Rs
<< 16;
9423 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9429 /* See if we can do this with a 16-bit instruction. */
9430 if (THUMB_SETS_FLAGS (inst
.instruction
))
9431 narrow
= !in_it_block ();
9433 narrow
= in_it_block ();
9435 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9437 if (inst
.operands
[2].shifted
)
9439 if (inst
.size_req
== 4)
9446 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9447 inst
.instruction
|= Rd
;
9448 inst
.instruction
|= Rn
<< 3;
9453 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9454 inst
.instruction
|= Rd
;
9455 inst
.instruction
|= Rs
<< 3;
9460 /* If we get here, it can't be done in 16 bits. */
9461 constraint (inst
.operands
[2].shifted
9462 && inst
.operands
[2].immisreg
,
9463 _("shift must be constant"));
9464 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9465 inst
.instruction
|= Rd
<< 8;
9466 inst
.instruction
|= Rs
<< 16;
9467 encode_thumb32_shifted_operand (2);
9472 /* On its face this is a lie - the instruction does set the
9473 flags. However, the only supported mnemonic in this mode
9475 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9477 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9478 _("unshifted register required"));
9479 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9481 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9482 inst
.instruction
|= Rd
;
9485 inst
.instruction
|= Rn
<< 3;
9487 inst
.instruction
|= Rs
<< 3;
9489 constraint (1, _("dest must overlap one source register"));
9496 if (inst
.operands
[0].present
)
9498 constraint ((inst
.instruction
& 0xf0) != 0x40
9499 && inst
.operands
[0].imm
> 0xf
9500 && inst
.operands
[0].imm
< 0x0,
9501 _("bad barrier type"));
9502 inst
.instruction
|= inst
.operands
[0].imm
;
9505 inst
.instruction
|= 0xf;
9512 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9513 constraint (msb
> 32, _("bit-field extends past end of register"));
9514 /* The instruction encoding stores the LSB and MSB,
9515 not the LSB and width. */
9516 Rd
= inst
.operands
[0].reg
;
9517 reject_bad_reg (Rd
);
9518 inst
.instruction
|= Rd
<< 8;
9519 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9520 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9521 inst
.instruction
|= msb
- 1;
9530 Rd
= inst
.operands
[0].reg
;
9531 reject_bad_reg (Rd
);
9533 /* #0 in second position is alternative syntax for bfc, which is
9534 the same instruction but with REG_PC in the Rm field. */
9535 if (!inst
.operands
[1].isreg
)
9539 Rn
= inst
.operands
[1].reg
;
9540 reject_bad_reg (Rn
);
9543 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9544 constraint (msb
> 32, _("bit-field extends past end of register"));
9545 /* The instruction encoding stores the LSB and MSB,
9546 not the LSB and width. */
9547 inst
.instruction
|= Rd
<< 8;
9548 inst
.instruction
|= Rn
<< 16;
9549 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9550 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9551 inst
.instruction
|= msb
- 1;
9559 Rd
= inst
.operands
[0].reg
;
9560 Rn
= inst
.operands
[1].reg
;
9562 reject_bad_reg (Rd
);
9563 reject_bad_reg (Rn
);
9565 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9566 _("bit-field extends past end of register"));
9567 inst
.instruction
|= Rd
<< 8;
9568 inst
.instruction
|= Rn
<< 16;
9569 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9570 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9571 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9574 /* ARM V5 Thumb BLX (argument parse)
9575 BLX <target_addr> which is BLX(1)
9576 BLX <Rm> which is BLX(2)
9577 Unfortunately, there are two different opcodes for this mnemonic.
9578 So, the insns[].value is not used, and the code here zaps values
9579 into inst.instruction.
9581 ??? How to take advantage of the additional two bits of displacement
9582 available in Thumb32 mode? Need new relocation? */
9587 set_it_insn_type_last ();
9589 if (inst
.operands
[0].isreg
)
9591 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9592 /* We have a register, so this is BLX(2). */
9593 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9597 /* No register. This must be BLX(1). */
9598 inst
.instruction
= 0xf000e800;
9599 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9600 inst
.reloc
.pc_rel
= 1;
9611 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9615 /* Conditional branches inside IT blocks are encoded as unconditional
9622 if (cond
!= COND_ALWAYS
)
9623 opcode
= T_MNEM_bcond
;
9625 opcode
= inst
.instruction
;
9627 if (unified_syntax
&& inst
.size_req
== 4)
9629 inst
.instruction
= THUMB_OP32(opcode
);
9630 if (cond
== COND_ALWAYS
)
9631 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9634 gas_assert (cond
!= 0xF);
9635 inst
.instruction
|= cond
<< 22;
9636 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9641 inst
.instruction
= THUMB_OP16(opcode
);
9642 if (cond
== COND_ALWAYS
)
9643 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9646 inst
.instruction
|= cond
<< 8;
9647 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9649 /* Allow section relaxation. */
9650 if (unified_syntax
&& inst
.size_req
!= 2)
9651 inst
.relax
= opcode
;
9654 inst
.reloc
.pc_rel
= 1;
9660 constraint (inst
.cond
!= COND_ALWAYS
,
9661 _("instruction is always unconditional"));
9662 if (inst
.operands
[0].present
)
9664 constraint (inst
.operands
[0].imm
> 255,
9665 _("immediate value out of range"));
9666 inst
.instruction
|= inst
.operands
[0].imm
;
9667 set_it_insn_type (NEUTRAL_IT_INSN
);
9672 do_t_branch23 (void)
9674 set_it_insn_type_last ();
9675 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9676 inst
.reloc
.pc_rel
= 1;
9678 #if defined(OBJ_COFF)
9679 /* If the destination of the branch is a defined symbol which does not have
9680 the THUMB_FUNC attribute, then we must be calling a function which has
9681 the (interfacearm) attribute. We look for the Thumb entry point to that
9682 function and change the branch to refer to that function instead. */
9683 if ( inst
.reloc
.exp
.X_op
== O_symbol
9684 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9685 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9686 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9687 inst
.reloc
.exp
.X_add_symbol
=
9688 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9695 set_it_insn_type_last ();
9696 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9697 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9698 should cause the alignment to be checked once it is known. This is
9699 because BX PC only works if the instruction is word aligned. */
9707 set_it_insn_type_last ();
9708 Rm
= inst
.operands
[0].reg
;
9709 reject_bad_reg (Rm
);
9710 inst
.instruction
|= Rm
<< 16;
9719 Rd
= inst
.operands
[0].reg
;
9720 Rm
= inst
.operands
[1].reg
;
9722 reject_bad_reg (Rd
);
9723 reject_bad_reg (Rm
);
9725 inst
.instruction
|= Rd
<< 8;
9726 inst
.instruction
|= Rm
<< 16;
9727 inst
.instruction
|= Rm
;
9733 set_it_insn_type (OUTSIDE_IT_INSN
);
9734 inst
.instruction
|= inst
.operands
[0].imm
;
9740 set_it_insn_type (OUTSIDE_IT_INSN
);
9742 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9743 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9745 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9746 inst
.instruction
= 0xf3af8000;
9747 inst
.instruction
|= imod
<< 9;
9748 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9749 if (inst
.operands
[1].present
)
9750 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9754 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9755 && (inst
.operands
[0].imm
& 4),
9756 _("selected processor does not support 'A' form "
9757 "of this instruction"));
9758 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9759 _("Thumb does not support the 2-argument "
9760 "form of this instruction"));
9761 inst
.instruction
|= inst
.operands
[0].imm
;
9765 /* THUMB CPY instruction (argument parse). */
9770 if (inst
.size_req
== 4)
9772 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9773 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9774 inst
.instruction
|= inst
.operands
[1].reg
;
9778 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9779 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9780 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9787 set_it_insn_type (OUTSIDE_IT_INSN
);
9788 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9789 inst
.instruction
|= inst
.operands
[0].reg
;
9790 inst
.reloc
.pc_rel
= 1;
9791 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9797 inst
.instruction
|= inst
.operands
[0].imm
;
9803 unsigned Rd
, Rn
, Rm
;
9805 Rd
= inst
.operands
[0].reg
;
9806 Rn
= (inst
.operands
[1].present
9807 ? inst
.operands
[1].reg
: Rd
);
9808 Rm
= inst
.operands
[2].reg
;
9810 reject_bad_reg (Rd
);
9811 reject_bad_reg (Rn
);
9812 reject_bad_reg (Rm
);
9814 inst
.instruction
|= Rd
<< 8;
9815 inst
.instruction
|= Rn
<< 16;
9816 inst
.instruction
|= Rm
;
9822 if (unified_syntax
&& inst
.size_req
== 4)
9823 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9825 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9831 unsigned int cond
= inst
.operands
[0].imm
;
9833 set_it_insn_type (IT_INSN
);
9834 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9837 /* If the condition is a negative condition, invert the mask. */
9838 if ((cond
& 0x1) == 0x0)
9840 unsigned int mask
= inst
.instruction
& 0x000f;
9842 if ((mask
& 0x7) == 0)
9843 /* no conversion needed */;
9844 else if ((mask
& 0x3) == 0)
9846 else if ((mask
& 0x1) == 0)
9851 inst
.instruction
&= 0xfff0;
9852 inst
.instruction
|= mask
;
9855 inst
.instruction
|= cond
<< 4;
9858 /* Helper function used for both push/pop and ldm/stm. */
9860 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9864 load
= (inst
.instruction
& (1 << 20)) != 0;
9866 if (mask
& (1 << 13))
9867 inst
.error
= _("SP not allowed in register list");
9869 if ((mask
& (1 << base
)) != 0
9871 inst
.error
= _("having the base register in the register list when "
9872 "using write back is UNPREDICTABLE");
9876 if (mask
& (1 << 15))
9878 if (mask
& (1 << 14))
9879 inst
.error
= _("LR and PC should not both be in register list");
9881 set_it_insn_type_last ();
9886 if (mask
& (1 << 15))
9887 inst
.error
= _("PC not allowed in register list");
9890 if ((mask
& (mask
- 1)) == 0)
9892 /* Single register transfers implemented as str/ldr. */
9895 if (inst
.instruction
& (1 << 23))
9896 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9898 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9902 if (inst
.instruction
& (1 << 23))
9903 inst
.instruction
= 0x00800000; /* ia -> [base] */
9905 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9908 inst
.instruction
|= 0xf8400000;
9910 inst
.instruction
|= 0x00100000;
9912 mask
= ffs (mask
) - 1;
9916 inst
.instruction
|= WRITE_BACK
;
9918 inst
.instruction
|= mask
;
9919 inst
.instruction
|= base
<< 16;
9925 /* This really doesn't seem worth it. */
9926 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9927 _("expression too complex"));
9928 constraint (inst
.operands
[1].writeback
,
9929 _("Thumb load/store multiple does not support {reglist}^"));
9937 /* See if we can use a 16-bit instruction. */
9938 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9939 && inst
.size_req
!= 4
9940 && !(inst
.operands
[1].imm
& ~0xff))
9942 mask
= 1 << inst
.operands
[0].reg
;
9944 if (inst
.operands
[0].reg
<= 7
9945 && (inst
.instruction
== T_MNEM_stmia
9946 ? inst
.operands
[0].writeback
9947 : (inst
.operands
[0].writeback
9948 == !(inst
.operands
[1].imm
& mask
))))
9950 if (inst
.instruction
== T_MNEM_stmia
9951 && (inst
.operands
[1].imm
& mask
)
9952 && (inst
.operands
[1].imm
& (mask
- 1)))
9953 as_warn (_("value stored for r%d is UNKNOWN"),
9954 inst
.operands
[0].reg
);
9956 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9957 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9958 inst
.instruction
|= inst
.operands
[1].imm
;
9961 else if (inst
.operands
[0] .reg
== REG_SP
9962 && inst
.operands
[0].writeback
)
9964 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9965 ? T_MNEM_push
: T_MNEM_pop
);
9966 inst
.instruction
|= inst
.operands
[1].imm
;
9973 if (inst
.instruction
< 0xffff)
9974 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9976 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9977 inst
.operands
[0].writeback
);
9982 constraint (inst
.operands
[0].reg
> 7
9983 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9984 constraint (inst
.instruction
!= T_MNEM_ldmia
9985 && inst
.instruction
!= T_MNEM_stmia
,
9986 _("Thumb-2 instruction only valid in unified syntax"));
9987 if (inst
.instruction
== T_MNEM_stmia
)
9989 if (!inst
.operands
[0].writeback
)
9990 as_warn (_("this instruction will write back the base register"));
9991 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9992 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9993 as_warn (_("value stored for r%d is UNKNOWN"),
9994 inst
.operands
[0].reg
);
9998 if (!inst
.operands
[0].writeback
9999 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10000 as_warn (_("this instruction will write back the base register"));
10001 else if (inst
.operands
[0].writeback
10002 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10003 as_warn (_("this instruction will not write back the base register"));
10006 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10007 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10008 inst
.instruction
|= inst
.operands
[1].imm
;
10015 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10016 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10017 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10018 || inst
.operands
[1].negative
,
10021 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10024 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10025 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10031 if (!inst
.operands
[1].present
)
10033 constraint (inst
.operands
[0].reg
== REG_LR
,
10034 _("r14 not allowed as first register "
10035 "when second register is omitted"));
10036 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10038 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10042 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10043 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10049 unsigned long opcode
;
10052 if (inst
.operands
[0].isreg
10053 && !inst
.operands
[0].preind
10054 && inst
.operands
[0].reg
== REG_PC
)
10055 set_it_insn_type_last ();
10057 opcode
= inst
.instruction
;
10058 if (unified_syntax
)
10060 if (!inst
.operands
[1].isreg
)
10062 if (opcode
<= 0xffff)
10063 inst
.instruction
= THUMB_OP32 (opcode
);
10064 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10067 if (inst
.operands
[1].isreg
10068 && !inst
.operands
[1].writeback
10069 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10070 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10071 && opcode
<= 0xffff
10072 && inst
.size_req
!= 4)
10074 /* Insn may have a 16-bit form. */
10075 Rn
= inst
.operands
[1].reg
;
10076 if (inst
.operands
[1].immisreg
)
10078 inst
.instruction
= THUMB_OP16 (opcode
);
10080 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10082 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10083 reject_bad_reg (inst
.operands
[1].imm
);
10085 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10086 && opcode
!= T_MNEM_ldrsb
)
10087 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10088 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10095 if (inst
.reloc
.pc_rel
)
10096 opcode
= T_MNEM_ldr_pc2
;
10098 opcode
= T_MNEM_ldr_pc
;
10102 if (opcode
== T_MNEM_ldr
)
10103 opcode
= T_MNEM_ldr_sp
;
10105 opcode
= T_MNEM_str_sp
;
10107 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10111 inst
.instruction
= inst
.operands
[0].reg
;
10112 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10114 inst
.instruction
|= THUMB_OP16 (opcode
);
10115 if (inst
.size_req
== 2)
10116 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10118 inst
.relax
= opcode
;
10122 /* Definitely a 32-bit variant. */
10124 /* Do some validations regarding addressing modes. */
10125 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10126 && opcode
!= T_MNEM_str
)
10127 reject_bad_reg (inst
.operands
[1].imm
);
10129 inst
.instruction
= THUMB_OP32 (opcode
);
10130 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10131 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10135 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10137 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10139 /* Only [Rn,Rm] is acceptable. */
10140 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10141 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10142 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10143 || inst
.operands
[1].negative
,
10144 _("Thumb does not support this addressing mode"));
10145 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10149 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10150 if (!inst
.operands
[1].isreg
)
10151 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10154 constraint (!inst
.operands
[1].preind
10155 || inst
.operands
[1].shifted
10156 || inst
.operands
[1].writeback
,
10157 _("Thumb does not support this addressing mode"));
10158 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10160 constraint (inst
.instruction
& 0x0600,
10161 _("byte or halfword not valid for base register"));
10162 constraint (inst
.operands
[1].reg
== REG_PC
10163 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10164 _("r15 based store not allowed"));
10165 constraint (inst
.operands
[1].immisreg
,
10166 _("invalid base register for register offset"));
10168 if (inst
.operands
[1].reg
== REG_PC
)
10169 inst
.instruction
= T_OPCODE_LDR_PC
;
10170 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10171 inst
.instruction
= T_OPCODE_LDR_SP
;
10173 inst
.instruction
= T_OPCODE_STR_SP
;
10175 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10176 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10180 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10181 if (!inst
.operands
[1].immisreg
)
10183 /* Immediate offset. */
10184 inst
.instruction
|= inst
.operands
[0].reg
;
10185 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10186 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10190 /* Register offset. */
10191 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10192 constraint (inst
.operands
[1].negative
,
10193 _("Thumb does not support this addressing mode"));
10196 switch (inst
.instruction
)
10198 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10199 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10200 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10201 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10202 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10203 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10204 case 0x5600 /* ldrsb */:
10205 case 0x5e00 /* ldrsh */: break;
10209 inst
.instruction
|= inst
.operands
[0].reg
;
10210 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10211 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10217 if (!inst
.operands
[1].present
)
10219 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10220 constraint (inst
.operands
[0].reg
== REG_LR
,
10221 _("r14 not allowed here"));
10223 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10224 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10225 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10232 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10238 unsigned Rd
, Rn
, Rm
, Ra
;
10240 Rd
= inst
.operands
[0].reg
;
10241 Rn
= inst
.operands
[1].reg
;
10242 Rm
= inst
.operands
[2].reg
;
10243 Ra
= inst
.operands
[3].reg
;
10245 reject_bad_reg (Rd
);
10246 reject_bad_reg (Rn
);
10247 reject_bad_reg (Rm
);
10248 reject_bad_reg (Ra
);
10250 inst
.instruction
|= Rd
<< 8;
10251 inst
.instruction
|= Rn
<< 16;
10252 inst
.instruction
|= Rm
;
10253 inst
.instruction
|= Ra
<< 12;
10259 unsigned RdLo
, RdHi
, Rn
, Rm
;
10261 RdLo
= inst
.operands
[0].reg
;
10262 RdHi
= inst
.operands
[1].reg
;
10263 Rn
= inst
.operands
[2].reg
;
10264 Rm
= inst
.operands
[3].reg
;
10266 reject_bad_reg (RdLo
);
10267 reject_bad_reg (RdHi
);
10268 reject_bad_reg (Rn
);
10269 reject_bad_reg (Rm
);
10271 inst
.instruction
|= RdLo
<< 12;
10272 inst
.instruction
|= RdHi
<< 8;
10273 inst
.instruction
|= Rn
<< 16;
10274 inst
.instruction
|= Rm
;
10278 do_t_mov_cmp (void)
10282 Rn
= inst
.operands
[0].reg
;
10283 Rm
= inst
.operands
[1].reg
;
10286 set_it_insn_type_last ();
10288 if (unified_syntax
)
10290 int r0off
= (inst
.instruction
== T_MNEM_mov
10291 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10292 unsigned long opcode
;
10293 bfd_boolean narrow
;
10294 bfd_boolean low_regs
;
10296 low_regs
= (Rn
<= 7 && Rm
<= 7);
10297 opcode
= inst
.instruction
;
10298 if (in_it_block ())
10299 narrow
= opcode
!= T_MNEM_movs
;
10301 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10302 if (inst
.size_req
== 4
10303 || inst
.operands
[1].shifted
)
10306 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10307 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10308 && !inst
.operands
[1].shifted
10312 inst
.instruction
= T2_SUBS_PC_LR
;
10316 if (opcode
== T_MNEM_cmp
)
10318 constraint (Rn
== REG_PC
, BAD_PC
);
10321 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10323 warn_deprecated_sp (Rm
);
10324 /* R15 was documented as a valid choice for Rm in ARMv6,
10325 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10326 tools reject R15, so we do too. */
10327 constraint (Rm
== REG_PC
, BAD_PC
);
10330 reject_bad_reg (Rm
);
10332 else if (opcode
== T_MNEM_mov
10333 || opcode
== T_MNEM_movs
)
10335 if (inst
.operands
[1].isreg
)
10337 if (opcode
== T_MNEM_movs
)
10339 reject_bad_reg (Rn
);
10340 reject_bad_reg (Rm
);
10344 /* This is mov.n. */
10345 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10346 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10348 as_warn (_("Use of r%u as a source register is "
10349 "deprecated when r%u is the destination "
10350 "register."), Rm
, Rn
);
10355 /* This is mov.w. */
10356 constraint (Rn
== REG_PC
, BAD_PC
);
10357 constraint (Rm
== REG_PC
, BAD_PC
);
10358 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10362 reject_bad_reg (Rn
);
10365 if (!inst
.operands
[1].isreg
)
10367 /* Immediate operand. */
10368 if (!in_it_block () && opcode
== T_MNEM_mov
)
10370 if (low_regs
&& narrow
)
10372 inst
.instruction
= THUMB_OP16 (opcode
);
10373 inst
.instruction
|= Rn
<< 8;
10374 if (inst
.size_req
== 2)
10375 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10377 inst
.relax
= opcode
;
10381 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10382 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10383 inst
.instruction
|= Rn
<< r0off
;
10384 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10387 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10388 && (inst
.instruction
== T_MNEM_mov
10389 || inst
.instruction
== T_MNEM_movs
))
10391 /* Register shifts are encoded as separate shift instructions. */
10392 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10394 if (in_it_block ())
10399 if (inst
.size_req
== 4)
10402 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10408 switch (inst
.operands
[1].shift_kind
)
10411 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10414 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10417 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10420 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10426 inst
.instruction
= opcode
;
10429 inst
.instruction
|= Rn
;
10430 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10435 inst
.instruction
|= CONDS_BIT
;
10437 inst
.instruction
|= Rn
<< 8;
10438 inst
.instruction
|= Rm
<< 16;
10439 inst
.instruction
|= inst
.operands
[1].imm
;
10444 /* Some mov with immediate shift have narrow variants.
10445 Register shifts are handled above. */
10446 if (low_regs
&& inst
.operands
[1].shifted
10447 && (inst
.instruction
== T_MNEM_mov
10448 || inst
.instruction
== T_MNEM_movs
))
10450 if (in_it_block ())
10451 narrow
= (inst
.instruction
== T_MNEM_mov
);
10453 narrow
= (inst
.instruction
== T_MNEM_movs
);
10458 switch (inst
.operands
[1].shift_kind
)
10460 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10461 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10462 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10463 default: narrow
= FALSE
; break;
10469 inst
.instruction
|= Rn
;
10470 inst
.instruction
|= Rm
<< 3;
10471 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10475 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10476 inst
.instruction
|= Rn
<< r0off
;
10477 encode_thumb32_shifted_operand (1);
10481 switch (inst
.instruction
)
10484 inst
.instruction
= T_OPCODE_MOV_HR
;
10485 inst
.instruction
|= (Rn
& 0x8) << 4;
10486 inst
.instruction
|= (Rn
& 0x7);
10487 inst
.instruction
|= Rm
<< 3;
10491 /* We know we have low registers at this point.
10492 Generate LSLS Rd, Rs, #0. */
10493 inst
.instruction
= T_OPCODE_LSL_I
;
10494 inst
.instruction
|= Rn
;
10495 inst
.instruction
|= Rm
<< 3;
10501 inst
.instruction
= T_OPCODE_CMP_LR
;
10502 inst
.instruction
|= Rn
;
10503 inst
.instruction
|= Rm
<< 3;
10507 inst
.instruction
= T_OPCODE_CMP_HR
;
10508 inst
.instruction
|= (Rn
& 0x8) << 4;
10509 inst
.instruction
|= (Rn
& 0x7);
10510 inst
.instruction
|= Rm
<< 3;
10517 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10519 /* PR 10443: Do not silently ignore shifted operands. */
10520 constraint (inst
.operands
[1].shifted
,
10521 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10523 if (inst
.operands
[1].isreg
)
10525 if (Rn
< 8 && Rm
< 8)
10527 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10528 since a MOV instruction produces unpredictable results. */
10529 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10530 inst
.instruction
= T_OPCODE_ADD_I3
;
10532 inst
.instruction
= T_OPCODE_CMP_LR
;
10534 inst
.instruction
|= Rn
;
10535 inst
.instruction
|= Rm
<< 3;
10539 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10540 inst
.instruction
= T_OPCODE_MOV_HR
;
10542 inst
.instruction
= T_OPCODE_CMP_HR
;
10548 constraint (Rn
> 7,
10549 _("only lo regs allowed with immediate"));
10550 inst
.instruction
|= Rn
<< 8;
10551 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10562 top
= (inst
.instruction
& 0x00800000) != 0;
10563 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10565 constraint (top
, _(":lower16: not allowed this instruction"));
10566 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10568 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10570 constraint (!top
, _(":upper16: not allowed this instruction"));
10571 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10574 Rd
= inst
.operands
[0].reg
;
10575 reject_bad_reg (Rd
);
10577 inst
.instruction
|= Rd
<< 8;
10578 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10580 imm
= inst
.reloc
.exp
.X_add_number
;
10581 inst
.instruction
|= (imm
& 0xf000) << 4;
10582 inst
.instruction
|= (imm
& 0x0800) << 15;
10583 inst
.instruction
|= (imm
& 0x0700) << 4;
10584 inst
.instruction
|= (imm
& 0x00ff);
10589 do_t_mvn_tst (void)
10593 Rn
= inst
.operands
[0].reg
;
10594 Rm
= inst
.operands
[1].reg
;
10596 if (inst
.instruction
== T_MNEM_cmp
10597 || inst
.instruction
== T_MNEM_cmn
)
10598 constraint (Rn
== REG_PC
, BAD_PC
);
10600 reject_bad_reg (Rn
);
10601 reject_bad_reg (Rm
);
10603 if (unified_syntax
)
10605 int r0off
= (inst
.instruction
== T_MNEM_mvn
10606 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10607 bfd_boolean narrow
;
10609 if (inst
.size_req
== 4
10610 || inst
.instruction
> 0xffff
10611 || inst
.operands
[1].shifted
10612 || Rn
> 7 || Rm
> 7)
10614 else if (inst
.instruction
== T_MNEM_cmn
)
10616 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10617 narrow
= !in_it_block ();
10619 narrow
= in_it_block ();
10621 if (!inst
.operands
[1].isreg
)
10623 /* For an immediate, we always generate a 32-bit opcode;
10624 section relaxation will shrink it later if possible. */
10625 if (inst
.instruction
< 0xffff)
10626 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10627 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10628 inst
.instruction
|= Rn
<< r0off
;
10629 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10633 /* See if we can do this with a 16-bit instruction. */
10636 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10637 inst
.instruction
|= Rn
;
10638 inst
.instruction
|= Rm
<< 3;
10642 constraint (inst
.operands
[1].shifted
10643 && inst
.operands
[1].immisreg
,
10644 _("shift must be constant"));
10645 if (inst
.instruction
< 0xffff)
10646 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10647 inst
.instruction
|= Rn
<< r0off
;
10648 encode_thumb32_shifted_operand (1);
10654 constraint (inst
.instruction
> 0xffff
10655 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10656 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10657 _("unshifted register required"));
10658 constraint (Rn
> 7 || Rm
> 7,
10661 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10662 inst
.instruction
|= Rn
;
10663 inst
.instruction
|= Rm
<< 3;
10673 if (do_vfp_nsyn_mrs () == SUCCESS
)
10676 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10679 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10680 _("selected processor does not support "
10681 "requested special purpose register"));
10685 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10686 _("selected processor does not support "
10687 "requested special purpose register"));
10688 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10689 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10690 _("'CPSR' or 'SPSR' expected"));
10693 Rd
= inst
.operands
[0].reg
;
10694 reject_bad_reg (Rd
);
10696 inst
.instruction
|= Rd
<< 8;
10697 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10698 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10707 if (do_vfp_nsyn_msr () == SUCCESS
)
10710 constraint (!inst
.operands
[1].isreg
,
10711 _("Thumb encoding does not support an immediate here"));
10712 flags
= inst
.operands
[0].imm
;
10715 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10716 _("selected processor does not support "
10717 "requested special purpose register"));
10721 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10722 _("selected processor does not support "
10723 "requested special purpose register"));
10727 Rn
= inst
.operands
[1].reg
;
10728 reject_bad_reg (Rn
);
10730 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10731 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10732 inst
.instruction
|= (flags
& 0xff);
10733 inst
.instruction
|= Rn
<< 16;
10739 bfd_boolean narrow
;
10740 unsigned Rd
, Rn
, Rm
;
10742 if (!inst
.operands
[2].present
)
10743 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10745 Rd
= inst
.operands
[0].reg
;
10746 Rn
= inst
.operands
[1].reg
;
10747 Rm
= inst
.operands
[2].reg
;
10749 if (unified_syntax
)
10751 if (inst
.size_req
== 4
10757 else if (inst
.instruction
== T_MNEM_muls
)
10758 narrow
= !in_it_block ();
10760 narrow
= in_it_block ();
10764 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10765 constraint (Rn
> 7 || Rm
> 7,
10772 /* 16-bit MULS/Conditional MUL. */
10773 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10774 inst
.instruction
|= Rd
;
10777 inst
.instruction
|= Rm
<< 3;
10779 inst
.instruction
|= Rn
<< 3;
10781 constraint (1, _("dest must overlap one source register"));
10785 constraint (inst
.instruction
!= T_MNEM_mul
,
10786 _("Thumb-2 MUL must not set flags"));
10788 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10789 inst
.instruction
|= Rd
<< 8;
10790 inst
.instruction
|= Rn
<< 16;
10791 inst
.instruction
|= Rm
<< 0;
10793 reject_bad_reg (Rd
);
10794 reject_bad_reg (Rn
);
10795 reject_bad_reg (Rm
);
10802 unsigned RdLo
, RdHi
, Rn
, Rm
;
10804 RdLo
= inst
.operands
[0].reg
;
10805 RdHi
= inst
.operands
[1].reg
;
10806 Rn
= inst
.operands
[2].reg
;
10807 Rm
= inst
.operands
[3].reg
;
10809 reject_bad_reg (RdLo
);
10810 reject_bad_reg (RdHi
);
10811 reject_bad_reg (Rn
);
10812 reject_bad_reg (Rm
);
10814 inst
.instruction
|= RdLo
<< 12;
10815 inst
.instruction
|= RdHi
<< 8;
10816 inst
.instruction
|= Rn
<< 16;
10817 inst
.instruction
|= Rm
;
10820 as_tsktsk (_("rdhi and rdlo must be different"));
10826 set_it_insn_type (NEUTRAL_IT_INSN
);
10828 if (unified_syntax
)
10830 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10832 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10833 inst
.instruction
|= inst
.operands
[0].imm
;
10837 /* PR9722: Check for Thumb2 availability before
10838 generating a thumb2 nop instruction. */
10839 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10841 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10842 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10845 inst
.instruction
= 0x46c0;
10850 constraint (inst
.operands
[0].present
,
10851 _("Thumb does not support NOP with hints"));
10852 inst
.instruction
= 0x46c0;
10859 if (unified_syntax
)
10861 bfd_boolean narrow
;
10863 if (THUMB_SETS_FLAGS (inst
.instruction
))
10864 narrow
= !in_it_block ();
10866 narrow
= in_it_block ();
10867 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10869 if (inst
.size_req
== 4)
10874 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10875 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10876 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10880 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10881 inst
.instruction
|= inst
.operands
[0].reg
;
10882 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10887 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10889 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10891 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10892 inst
.instruction
|= inst
.operands
[0].reg
;
10893 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10902 Rd
= inst
.operands
[0].reg
;
10903 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10905 reject_bad_reg (Rd
);
10906 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10907 reject_bad_reg (Rn
);
10909 inst
.instruction
|= Rd
<< 8;
10910 inst
.instruction
|= Rn
<< 16;
10912 if (!inst
.operands
[2].isreg
)
10914 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10915 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10921 Rm
= inst
.operands
[2].reg
;
10922 reject_bad_reg (Rm
);
10924 constraint (inst
.operands
[2].shifted
10925 && inst
.operands
[2].immisreg
,
10926 _("shift must be constant"));
10927 encode_thumb32_shifted_operand (2);
10934 unsigned Rd
, Rn
, Rm
;
10936 Rd
= inst
.operands
[0].reg
;
10937 Rn
= inst
.operands
[1].reg
;
10938 Rm
= inst
.operands
[2].reg
;
10940 reject_bad_reg (Rd
);
10941 reject_bad_reg (Rn
);
10942 reject_bad_reg (Rm
);
10944 inst
.instruction
|= Rd
<< 8;
10945 inst
.instruction
|= Rn
<< 16;
10946 inst
.instruction
|= Rm
;
10947 if (inst
.operands
[3].present
)
10949 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10950 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10951 _("expression too complex"));
10952 inst
.instruction
|= (val
& 0x1c) << 10;
10953 inst
.instruction
|= (val
& 0x03) << 6;
10960 if (!inst
.operands
[3].present
)
10964 inst
.instruction
&= ~0x00000020;
10966 /* PR 10168. Swap the Rm and Rn registers. */
10967 Rtmp
= inst
.operands
[1].reg
;
10968 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10969 inst
.operands
[2].reg
= Rtmp
;
10977 if (inst
.operands
[0].immisreg
)
10978 reject_bad_reg (inst
.operands
[0].imm
);
10980 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10984 do_t_push_pop (void)
10988 constraint (inst
.operands
[0].writeback
,
10989 _("push/pop do not support {reglist}^"));
10990 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10991 _("expression too complex"));
10993 mask
= inst
.operands
[0].imm
;
10994 if ((mask
& ~0xff) == 0)
10995 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10996 else if ((inst
.instruction
== T_MNEM_push
10997 && (mask
& ~0xff) == 1 << REG_LR
)
10998 || (inst
.instruction
== T_MNEM_pop
10999 && (mask
& ~0xff) == 1 << REG_PC
))
11001 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11002 inst
.instruction
|= THUMB_PP_PC_LR
;
11003 inst
.instruction
|= mask
& 0xff;
11005 else if (unified_syntax
)
11007 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11008 encode_thumb2_ldmstm (13, mask
, TRUE
);
11012 inst
.error
= _("invalid register list to push/pop instruction");
11022 Rd
= inst
.operands
[0].reg
;
11023 Rm
= inst
.operands
[1].reg
;
11025 reject_bad_reg (Rd
);
11026 reject_bad_reg (Rm
);
11028 inst
.instruction
|= Rd
<< 8;
11029 inst
.instruction
|= Rm
<< 16;
11030 inst
.instruction
|= Rm
;
11038 Rd
= inst
.operands
[0].reg
;
11039 Rm
= inst
.operands
[1].reg
;
11041 reject_bad_reg (Rd
);
11042 reject_bad_reg (Rm
);
11044 if (Rd
<= 7 && Rm
<= 7
11045 && inst
.size_req
!= 4)
11047 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11048 inst
.instruction
|= Rd
;
11049 inst
.instruction
|= Rm
<< 3;
11051 else if (unified_syntax
)
11053 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11054 inst
.instruction
|= Rd
<< 8;
11055 inst
.instruction
|= Rm
<< 16;
11056 inst
.instruction
|= Rm
;
11059 inst
.error
= BAD_HIREG
;
11067 Rd
= inst
.operands
[0].reg
;
11068 Rm
= inst
.operands
[1].reg
;
11070 reject_bad_reg (Rd
);
11071 reject_bad_reg (Rm
);
11073 inst
.instruction
|= Rd
<< 8;
11074 inst
.instruction
|= Rm
;
11082 Rd
= inst
.operands
[0].reg
;
11083 Rs
= (inst
.operands
[1].present
11084 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11085 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11087 reject_bad_reg (Rd
);
11088 reject_bad_reg (Rs
);
11089 if (inst
.operands
[2].isreg
)
11090 reject_bad_reg (inst
.operands
[2].reg
);
11092 inst
.instruction
|= Rd
<< 8;
11093 inst
.instruction
|= Rs
<< 16;
11094 if (!inst
.operands
[2].isreg
)
11096 bfd_boolean narrow
;
11098 if ((inst
.instruction
& 0x00100000) != 0)
11099 narrow
= !in_it_block ();
11101 narrow
= in_it_block ();
11103 if (Rd
> 7 || Rs
> 7)
11106 if (inst
.size_req
== 4 || !unified_syntax
)
11109 if (inst
.reloc
.exp
.X_op
!= O_constant
11110 || inst
.reloc
.exp
.X_add_number
!= 0)
11113 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11114 relaxation, but it doesn't seem worth the hassle. */
11117 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11118 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11119 inst
.instruction
|= Rs
<< 3;
11120 inst
.instruction
|= Rd
;
11124 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11125 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11129 encode_thumb32_shifted_operand (2);
11135 set_it_insn_type (OUTSIDE_IT_INSN
);
11136 if (inst
.operands
[0].imm
)
11137 inst
.instruction
|= 0x8;
11143 if (!inst
.operands
[1].present
)
11144 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11146 if (unified_syntax
)
11148 bfd_boolean narrow
;
11151 switch (inst
.instruction
)
11154 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11156 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11158 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11160 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11164 if (THUMB_SETS_FLAGS (inst
.instruction
))
11165 narrow
= !in_it_block ();
11167 narrow
= in_it_block ();
11168 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11170 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11172 if (inst
.operands
[2].isreg
11173 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11174 || inst
.operands
[2].reg
> 7))
11176 if (inst
.size_req
== 4)
11179 reject_bad_reg (inst
.operands
[0].reg
);
11180 reject_bad_reg (inst
.operands
[1].reg
);
11184 if (inst
.operands
[2].isreg
)
11186 reject_bad_reg (inst
.operands
[2].reg
);
11187 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11188 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11189 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11190 inst
.instruction
|= inst
.operands
[2].reg
;
11194 inst
.operands
[1].shifted
= 1;
11195 inst
.operands
[1].shift_kind
= shift_kind
;
11196 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11197 ? T_MNEM_movs
: T_MNEM_mov
);
11198 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11199 encode_thumb32_shifted_operand (1);
11200 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11201 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11206 if (inst
.operands
[2].isreg
)
11208 switch (shift_kind
)
11210 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11211 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11212 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11213 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11217 inst
.instruction
|= inst
.operands
[0].reg
;
11218 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11222 switch (shift_kind
)
11224 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11225 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11226 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11229 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11230 inst
.instruction
|= inst
.operands
[0].reg
;
11231 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11237 constraint (inst
.operands
[0].reg
> 7
11238 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11239 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11241 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11243 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11244 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11245 _("source1 and dest must be same register"));
11247 switch (inst
.instruction
)
11249 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11250 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11251 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11252 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11256 inst
.instruction
|= inst
.operands
[0].reg
;
11257 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11261 switch (inst
.instruction
)
11263 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11264 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11265 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11266 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11269 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11270 inst
.instruction
|= inst
.operands
[0].reg
;
11271 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11279 unsigned Rd
, Rn
, Rm
;
11281 Rd
= inst
.operands
[0].reg
;
11282 Rn
= inst
.operands
[1].reg
;
11283 Rm
= inst
.operands
[2].reg
;
11285 reject_bad_reg (Rd
);
11286 reject_bad_reg (Rn
);
11287 reject_bad_reg (Rm
);
11289 inst
.instruction
|= Rd
<< 8;
11290 inst
.instruction
|= Rn
<< 16;
11291 inst
.instruction
|= Rm
;
11297 unsigned Rd
, Rn
, Rm
;
11299 Rd
= inst
.operands
[0].reg
;
11300 Rm
= inst
.operands
[1].reg
;
11301 Rn
= inst
.operands
[2].reg
;
11303 reject_bad_reg (Rd
);
11304 reject_bad_reg (Rn
);
11305 reject_bad_reg (Rm
);
11307 inst
.instruction
|= Rd
<< 8;
11308 inst
.instruction
|= Rn
<< 16;
11309 inst
.instruction
|= Rm
;
11315 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11316 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11317 _("expression too complex"));
11318 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11319 inst
.instruction
|= (value
& 0xf000) >> 12;
11320 inst
.instruction
|= (value
& 0x0ff0);
11321 inst
.instruction
|= (value
& 0x000f) << 16;
11325 do_t_ssat_usat (int bias
)
11329 Rd
= inst
.operands
[0].reg
;
11330 Rn
= inst
.operands
[2].reg
;
11332 reject_bad_reg (Rd
);
11333 reject_bad_reg (Rn
);
11335 inst
.instruction
|= Rd
<< 8;
11336 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11337 inst
.instruction
|= Rn
<< 16;
11339 if (inst
.operands
[3].present
)
11341 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11343 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11345 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11346 _("expression too complex"));
11348 if (shift_amount
!= 0)
11350 constraint (shift_amount
> 31,
11351 _("shift expression is too large"));
11353 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11354 inst
.instruction
|= 0x00200000; /* sh bit. */
11356 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11357 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11365 do_t_ssat_usat (1);
11373 Rd
= inst
.operands
[0].reg
;
11374 Rn
= inst
.operands
[2].reg
;
11376 reject_bad_reg (Rd
);
11377 reject_bad_reg (Rn
);
11379 inst
.instruction
|= Rd
<< 8;
11380 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11381 inst
.instruction
|= Rn
<< 16;
11387 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11388 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11389 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11390 || inst
.operands
[2].negative
,
11393 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11395 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11396 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11397 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11398 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11404 if (!inst
.operands
[2].present
)
11405 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11407 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11408 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11409 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11412 inst
.instruction
|= inst
.operands
[0].reg
;
11413 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11414 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11415 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11421 unsigned Rd
, Rn
, Rm
;
11423 Rd
= inst
.operands
[0].reg
;
11424 Rn
= inst
.operands
[1].reg
;
11425 Rm
= inst
.operands
[2].reg
;
11427 reject_bad_reg (Rd
);
11428 reject_bad_reg (Rn
);
11429 reject_bad_reg (Rm
);
11431 inst
.instruction
|= Rd
<< 8;
11432 inst
.instruction
|= Rn
<< 16;
11433 inst
.instruction
|= Rm
;
11434 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11442 Rd
= inst
.operands
[0].reg
;
11443 Rm
= inst
.operands
[1].reg
;
11445 reject_bad_reg (Rd
);
11446 reject_bad_reg (Rm
);
11448 if (inst
.instruction
<= 0xffff
11449 && inst
.size_req
!= 4
11450 && Rd
<= 7 && Rm
<= 7
11451 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11453 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11454 inst
.instruction
|= Rd
;
11455 inst
.instruction
|= Rm
<< 3;
11457 else if (unified_syntax
)
11459 if (inst
.instruction
<= 0xffff)
11460 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11461 inst
.instruction
|= Rd
<< 8;
11462 inst
.instruction
|= Rm
;
11463 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11467 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11468 _("Thumb encoding does not support rotation"));
11469 constraint (1, BAD_HIREG
);
11476 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11485 half
= (inst
.instruction
& 0x10) != 0;
11486 set_it_insn_type_last ();
11487 constraint (inst
.operands
[0].immisreg
,
11488 _("instruction requires register index"));
11490 Rn
= inst
.operands
[0].reg
;
11491 Rm
= inst
.operands
[0].imm
;
11493 constraint (Rn
== REG_SP
, BAD_SP
);
11494 reject_bad_reg (Rm
);
11496 constraint (!half
&& inst
.operands
[0].shifted
,
11497 _("instruction does not allow shifted index"));
11498 inst
.instruction
|= (Rn
<< 16) | Rm
;
11504 do_t_ssat_usat (0);
11512 Rd
= inst
.operands
[0].reg
;
11513 Rn
= inst
.operands
[2].reg
;
11515 reject_bad_reg (Rd
);
11516 reject_bad_reg (Rn
);
11518 inst
.instruction
|= Rd
<< 8;
11519 inst
.instruction
|= inst
.operands
[1].imm
;
11520 inst
.instruction
|= Rn
<< 16;
11523 /* Neon instruction encoder helpers. */
11525 /* Encodings for the different types for various Neon opcodes. */
11527 /* An "invalid" code for the following tables. */
11530 struct neon_tab_entry
11533 unsigned float_or_poly
;
11534 unsigned scalar_or_imm
;
11537 /* Map overloaded Neon opcodes to their respective encodings. */
11538 #define NEON_ENC_TAB \
11539 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11540 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11541 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11542 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11543 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11544 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11545 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11546 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11547 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11548 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11549 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11550 /* Register variants of the following two instructions are encoded as
11551 vcge / vcgt with the operands reversed. */ \
11552 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11553 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11554 X(vfma, N_INV, 0x0000c10, N_INV), \
11555 X(vfms, N_INV, 0x0200c10, N_INV), \
11556 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11557 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11558 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11559 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11560 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11561 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11562 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11563 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11564 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11565 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11566 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11567 X(vshl, 0x0000400, N_INV, 0x0800510), \
11568 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11569 X(vand, 0x0000110, N_INV, 0x0800030), \
11570 X(vbic, 0x0100110, N_INV, 0x0800030), \
11571 X(veor, 0x1000110, N_INV, N_INV), \
11572 X(vorn, 0x0300110, N_INV, 0x0800010), \
11573 X(vorr, 0x0200110, N_INV, 0x0800010), \
11574 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11575 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11576 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11577 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11578 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11579 X(vst1, 0x0000000, 0x0800000, N_INV), \
11580 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11581 X(vst2, 0x0000100, 0x0800100, N_INV), \
11582 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11583 X(vst3, 0x0000200, 0x0800200, N_INV), \
11584 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11585 X(vst4, 0x0000300, 0x0800300, N_INV), \
11586 X(vmovn, 0x1b20200, N_INV, N_INV), \
11587 X(vtrn, 0x1b20080, N_INV, N_INV), \
11588 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11589 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11590 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11591 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11592 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11593 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11594 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11595 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11596 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11597 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11598 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11602 #define X(OPC,I,F,S) N_MNEM_##OPC
11607 static const struct neon_tab_entry neon_enc_tab
[] =
11609 #define X(OPC,I,F,S) { (I), (F), (S) }
11614 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11615 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11616 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11617 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11618 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11619 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11620 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11621 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11622 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11623 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11624 #define NEON_ENC_SINGLE_(X) \
11625 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11626 #define NEON_ENC_DOUBLE_(X) \
11627 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11629 #define NEON_ENCODE(type, inst) \
11632 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11633 inst.is_neon = 1; \
11637 #define check_neon_suffixes \
11640 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11642 as_bad (_("invalid neon suffix for non neon instruction")); \
11648 /* Define shapes for instruction operands. The following mnemonic characters
11649 are used in this table:
11651 F - VFP S<n> register
11652 D - Neon D<n> register
11653 Q - Neon Q<n> register
11657 L - D<n> register list
11659 This table is used to generate various data:
11660 - enumerations of the form NS_DDR to be used as arguments to
11662 - a table classifying shapes into single, double, quad, mixed.
11663 - a table used to drive neon_select_shape. */
11665 #define NEON_SHAPE_DEF \
11666 X(3, (D, D, D), DOUBLE), \
11667 X(3, (Q, Q, Q), QUAD), \
11668 X(3, (D, D, I), DOUBLE), \
11669 X(3, (Q, Q, I), QUAD), \
11670 X(3, (D, D, S), DOUBLE), \
11671 X(3, (Q, Q, S), QUAD), \
11672 X(2, (D, D), DOUBLE), \
11673 X(2, (Q, Q), QUAD), \
11674 X(2, (D, S), DOUBLE), \
11675 X(2, (Q, S), QUAD), \
11676 X(2, (D, R), DOUBLE), \
11677 X(2, (Q, R), QUAD), \
11678 X(2, (D, I), DOUBLE), \
11679 X(2, (Q, I), QUAD), \
11680 X(3, (D, L, D), DOUBLE), \
11681 X(2, (D, Q), MIXED), \
11682 X(2, (Q, D), MIXED), \
11683 X(3, (D, Q, I), MIXED), \
11684 X(3, (Q, D, I), MIXED), \
11685 X(3, (Q, D, D), MIXED), \
11686 X(3, (D, Q, Q), MIXED), \
11687 X(3, (Q, Q, D), MIXED), \
11688 X(3, (Q, D, S), MIXED), \
11689 X(3, (D, Q, S), MIXED), \
11690 X(4, (D, D, D, I), DOUBLE), \
11691 X(4, (Q, Q, Q, I), QUAD), \
11692 X(2, (F, F), SINGLE), \
11693 X(3, (F, F, F), SINGLE), \
11694 X(2, (F, I), SINGLE), \
11695 X(2, (F, D), MIXED), \
11696 X(2, (D, F), MIXED), \
11697 X(3, (F, F, I), MIXED), \
11698 X(4, (R, R, F, F), SINGLE), \
11699 X(4, (F, F, R, R), SINGLE), \
11700 X(3, (D, R, R), DOUBLE), \
11701 X(3, (R, R, D), DOUBLE), \
11702 X(2, (S, R), SINGLE), \
11703 X(2, (R, S), SINGLE), \
11704 X(2, (F, R), SINGLE), \
11705 X(2, (R, F), SINGLE)
11707 #define S2(A,B) NS_##A##B
11708 #define S3(A,B,C) NS_##A##B##C
11709 #define S4(A,B,C,D) NS_##A##B##C##D
11711 #define X(N, L, C) S##N L
11724 enum neon_shape_class
11732 #define X(N, L, C) SC_##C
11734 static enum neon_shape_class neon_shape_class
[] =
11752 /* Register widths of above. */
11753 static unsigned neon_shape_el_size
[] =
11764 struct neon_shape_info
11767 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11770 #define S2(A,B) { SE_##A, SE_##B }
11771 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11772 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11774 #define X(N, L, C) { N, S##N L }
11776 static struct neon_shape_info neon_shape_tab
[] =
11786 /* Bit masks used in type checking given instructions.
11787 'N_EQK' means the type must be the same as (or based on in some way) the key
11788 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11789 set, various other bits can be set as well in order to modify the meaning of
11790 the type constraint. */
11792 enum neon_type_mask
11815 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11816 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11817 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11818 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11819 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11820 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11821 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11822 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11823 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11824 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11826 N_MAX_NONSPECIAL
= N_F64
11829 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11831 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11832 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11833 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11834 #define N_SUF_32 (N_SU_32 | N_F32)
11835 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11836 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11838 /* Pass this as the first type argument to neon_check_type to ignore types
11840 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11842 /* Select a "shape" for the current instruction (describing register types or
11843 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11844 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11845 function of operand parsing, so this function doesn't need to be called.
11846 Shapes should be listed in order of decreasing length. */
11848 static enum neon_shape
11849 neon_select_shape (enum neon_shape shape
, ...)
11852 enum neon_shape first_shape
= shape
;
11854 /* Fix missing optional operands. FIXME: we don't know at this point how
11855 many arguments we should have, so this makes the assumption that we have
11856 > 1. This is true of all current Neon opcodes, I think, but may not be
11857 true in the future. */
11858 if (!inst
.operands
[1].present
)
11859 inst
.operands
[1] = inst
.operands
[0];
11861 va_start (ap
, shape
);
11863 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11868 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11870 if (!inst
.operands
[j
].present
)
11876 switch (neon_shape_tab
[shape
].el
[j
])
11879 if (!(inst
.operands
[j
].isreg
11880 && inst
.operands
[j
].isvec
11881 && inst
.operands
[j
].issingle
11882 && !inst
.operands
[j
].isquad
))
11887 if (!(inst
.operands
[j
].isreg
11888 && inst
.operands
[j
].isvec
11889 && !inst
.operands
[j
].isquad
11890 && !inst
.operands
[j
].issingle
))
11895 if (!(inst
.operands
[j
].isreg
11896 && !inst
.operands
[j
].isvec
))
11901 if (!(inst
.operands
[j
].isreg
11902 && inst
.operands
[j
].isvec
11903 && inst
.operands
[j
].isquad
11904 && !inst
.operands
[j
].issingle
))
11909 if (!(!inst
.operands
[j
].isreg
11910 && !inst
.operands
[j
].isscalar
))
11915 if (!(!inst
.operands
[j
].isreg
11916 && inst
.operands
[j
].isscalar
))
11932 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11933 first_error (_("invalid instruction shape"));
11938 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11939 means the Q bit should be set). */
11942 neon_quad (enum neon_shape shape
)
11944 return neon_shape_class
[shape
] == SC_QUAD
;
11948 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11951 /* Allow modification to be made to types which are constrained to be
11952 based on the key element, based on bits set alongside N_EQK. */
11953 if ((typebits
& N_EQK
) != 0)
11955 if ((typebits
& N_HLF
) != 0)
11957 else if ((typebits
& N_DBL
) != 0)
11959 if ((typebits
& N_SGN
) != 0)
11960 *g_type
= NT_signed
;
11961 else if ((typebits
& N_UNS
) != 0)
11962 *g_type
= NT_unsigned
;
11963 else if ((typebits
& N_INT
) != 0)
11964 *g_type
= NT_integer
;
11965 else if ((typebits
& N_FLT
) != 0)
11966 *g_type
= NT_float
;
11967 else if ((typebits
& N_SIZ
) != 0)
11968 *g_type
= NT_untyped
;
11972 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11973 operand type, i.e. the single type specified in a Neon instruction when it
11974 is the only one given. */
11976 static struct neon_type_el
11977 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11979 struct neon_type_el dest
= *key
;
11981 gas_assert ((thisarg
& N_EQK
) != 0);
11983 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11988 /* Convert Neon type and size into compact bitmask representation. */
11990 static enum neon_type_mask
11991 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11998 case 8: return N_8
;
11999 case 16: return N_16
;
12000 case 32: return N_32
;
12001 case 64: return N_64
;
12009 case 8: return N_I8
;
12010 case 16: return N_I16
;
12011 case 32: return N_I32
;
12012 case 64: return N_I64
;
12020 case 16: return N_F16
;
12021 case 32: return N_F32
;
12022 case 64: return N_F64
;
12030 case 8: return N_P8
;
12031 case 16: return N_P16
;
12039 case 8: return N_S8
;
12040 case 16: return N_S16
;
12041 case 32: return N_S32
;
12042 case 64: return N_S64
;
12050 case 8: return N_U8
;
12051 case 16: return N_U16
;
12052 case 32: return N_U32
;
12053 case 64: return N_U64
;
12064 /* Convert compact Neon bitmask type representation to a type and size. Only
12065 handles the case where a single bit is set in the mask. */
12068 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12069 enum neon_type_mask mask
)
12071 if ((mask
& N_EQK
) != 0)
12074 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12076 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12078 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12080 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12085 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12087 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12088 *type
= NT_unsigned
;
12089 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12090 *type
= NT_integer
;
12091 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12092 *type
= NT_untyped
;
12093 else if ((mask
& (N_P8
| N_P16
)) != 0)
12095 else if ((mask
& (N_F32
| N_F64
)) != 0)
12103 /* Modify a bitmask of allowed types. This is only needed for type
12107 modify_types_allowed (unsigned allowed
, unsigned mods
)
12110 enum neon_el_type type
;
12116 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12118 if (el_type_of_type_chk (&type
, &size
,
12119 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12121 neon_modify_type_size (mods
, &type
, &size
);
12122 destmask
|= type_chk_of_el_type (type
, size
);
12129 /* Check type and return type classification.
12130 The manual states (paraphrase): If one datatype is given, it indicates the
12132 - the second operand, if there is one
12133 - the operand, if there is no second operand
12134 - the result, if there are no operands.
12135 This isn't quite good enough though, so we use a concept of a "key" datatype
12136 which is set on a per-instruction basis, which is the one which matters when
12137 only one data type is written.
12138 Note: this function has side-effects (e.g. filling in missing operands). All
12139 Neon instructions should call it before performing bit encoding. */
12141 static struct neon_type_el
12142 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12145 unsigned i
, pass
, key_el
= 0;
12146 unsigned types
[NEON_MAX_TYPE_ELS
];
12147 enum neon_el_type k_type
= NT_invtype
;
12148 unsigned k_size
= -1u;
12149 struct neon_type_el badtype
= {NT_invtype
, -1};
12150 unsigned key_allowed
= 0;
12152 /* Optional registers in Neon instructions are always (not) in operand 1.
12153 Fill in the missing operand here, if it was omitted. */
12154 if (els
> 1 && !inst
.operands
[1].present
)
12155 inst
.operands
[1] = inst
.operands
[0];
12157 /* Suck up all the varargs. */
12159 for (i
= 0; i
< els
; i
++)
12161 unsigned thisarg
= va_arg (ap
, unsigned);
12162 if (thisarg
== N_IGNORE_TYPE
)
12167 types
[i
] = thisarg
;
12168 if ((thisarg
& N_KEY
) != 0)
12173 if (inst
.vectype
.elems
> 0)
12174 for (i
= 0; i
< els
; i
++)
12175 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12177 first_error (_("types specified in both the mnemonic and operands"));
12181 /* Duplicate inst.vectype elements here as necessary.
12182 FIXME: No idea if this is exactly the same as the ARM assembler,
12183 particularly when an insn takes one register and one non-register
12185 if (inst
.vectype
.elems
== 1 && els
> 1)
12188 inst
.vectype
.elems
= els
;
12189 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12190 for (j
= 0; j
< els
; j
++)
12192 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12195 else if (inst
.vectype
.elems
== 0 && els
> 0)
12198 /* No types were given after the mnemonic, so look for types specified
12199 after each operand. We allow some flexibility here; as long as the
12200 "key" operand has a type, we can infer the others. */
12201 for (j
= 0; j
< els
; j
++)
12202 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12203 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12205 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12207 for (j
= 0; j
< els
; j
++)
12208 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12209 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12214 first_error (_("operand types can't be inferred"));
12218 else if (inst
.vectype
.elems
!= els
)
12220 first_error (_("type specifier has the wrong number of parts"));
12224 for (pass
= 0; pass
< 2; pass
++)
12226 for (i
= 0; i
< els
; i
++)
12228 unsigned thisarg
= types
[i
];
12229 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12230 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12231 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12232 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12234 /* Decay more-specific signed & unsigned types to sign-insensitive
12235 integer types if sign-specific variants are unavailable. */
12236 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12237 && (types_allowed
& N_SU_ALL
) == 0)
12238 g_type
= NT_integer
;
12240 /* If only untyped args are allowed, decay any more specific types to
12241 them. Some instructions only care about signs for some element
12242 sizes, so handle that properly. */
12243 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12244 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12245 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12246 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12247 g_type
= NT_untyped
;
12251 if ((thisarg
& N_KEY
) != 0)
12255 key_allowed
= thisarg
& ~N_KEY
;
12260 if ((thisarg
& N_VFP
) != 0)
12262 enum neon_shape_el regshape
;
12263 unsigned regwidth
, match
;
12265 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12268 first_error (_("invalid instruction shape"));
12271 regshape
= neon_shape_tab
[ns
].el
[i
];
12272 regwidth
= neon_shape_el_size
[regshape
];
12274 /* In VFP mode, operands must match register widths. If we
12275 have a key operand, use its width, else use the width of
12276 the current operand. */
12282 if (regwidth
!= match
)
12284 first_error (_("operand size must match register width"));
12289 if ((thisarg
& N_EQK
) == 0)
12291 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12293 if ((given_type
& types_allowed
) == 0)
12295 first_error (_("bad type in Neon instruction"));
12301 enum neon_el_type mod_k_type
= k_type
;
12302 unsigned mod_k_size
= k_size
;
12303 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12304 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12306 first_error (_("inconsistent types in Neon instruction"));
12314 return inst
.vectype
.el
[key_el
];
12317 /* Neon-style VFP instruction forwarding. */
12319 /* Thumb VFP instructions have 0xE in the condition field. */
12322 do_vfp_cond_or_thumb (void)
12327 inst
.instruction
|= 0xe0000000;
12329 inst
.instruction
|= inst
.cond
<< 28;
12332 /* Look up and encode a simple mnemonic, for use as a helper function for the
12333 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12334 etc. It is assumed that operand parsing has already been done, and that the
12335 operands are in the form expected by the given opcode (this isn't necessarily
12336 the same as the form in which they were parsed, hence some massaging must
12337 take place before this function is called).
12338 Checks current arch version against that in the looked-up opcode. */
12341 do_vfp_nsyn_opcode (const char *opname
)
12343 const struct asm_opcode
*opcode
;
12345 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12350 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12351 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12358 inst
.instruction
= opcode
->tvalue
;
12359 opcode
->tencode ();
12363 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12364 opcode
->aencode ();
12369 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12371 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12376 do_vfp_nsyn_opcode ("fadds");
12378 do_vfp_nsyn_opcode ("fsubs");
12383 do_vfp_nsyn_opcode ("faddd");
12385 do_vfp_nsyn_opcode ("fsubd");
12389 /* Check operand types to see if this is a VFP instruction, and if so call
12393 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12395 enum neon_shape rs
;
12396 struct neon_type_el et
;
12401 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12402 et
= neon_check_type (2, rs
,
12403 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12407 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12408 et
= neon_check_type (3, rs
,
12409 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12416 if (et
.type
!= NT_invtype
)
12427 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12429 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12434 do_vfp_nsyn_opcode ("fmacs");
12436 do_vfp_nsyn_opcode ("fnmacs");
12441 do_vfp_nsyn_opcode ("fmacd");
12443 do_vfp_nsyn_opcode ("fnmacd");
12448 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12450 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12455 do_vfp_nsyn_opcode ("ffmas");
12457 do_vfp_nsyn_opcode ("ffnmas");
12462 do_vfp_nsyn_opcode ("ffmad");
12464 do_vfp_nsyn_opcode ("ffnmad");
12469 do_vfp_nsyn_mul (enum neon_shape rs
)
12472 do_vfp_nsyn_opcode ("fmuls");
12474 do_vfp_nsyn_opcode ("fmuld");
12478 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12480 int is_neg
= (inst
.instruction
& 0x80) != 0;
12481 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12486 do_vfp_nsyn_opcode ("fnegs");
12488 do_vfp_nsyn_opcode ("fabss");
12493 do_vfp_nsyn_opcode ("fnegd");
12495 do_vfp_nsyn_opcode ("fabsd");
12499 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12500 insns belong to Neon, and are handled elsewhere. */
12503 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12505 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12509 do_vfp_nsyn_opcode ("fldmdbs");
12511 do_vfp_nsyn_opcode ("fldmias");
12516 do_vfp_nsyn_opcode ("fstmdbs");
12518 do_vfp_nsyn_opcode ("fstmias");
12523 do_vfp_nsyn_sqrt (void)
12525 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12526 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12529 do_vfp_nsyn_opcode ("fsqrts");
12531 do_vfp_nsyn_opcode ("fsqrtd");
12535 do_vfp_nsyn_div (void)
12537 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12538 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12539 N_F32
| N_F64
| N_KEY
| N_VFP
);
12542 do_vfp_nsyn_opcode ("fdivs");
12544 do_vfp_nsyn_opcode ("fdivd");
12548 do_vfp_nsyn_nmul (void)
12550 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12551 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12552 N_F32
| N_F64
| N_KEY
| N_VFP
);
12556 NEON_ENCODE (SINGLE
, inst
);
12557 do_vfp_sp_dyadic ();
12561 NEON_ENCODE (DOUBLE
, inst
);
12562 do_vfp_dp_rd_rn_rm ();
12564 do_vfp_cond_or_thumb ();
12568 do_vfp_nsyn_cmp (void)
12570 if (inst
.operands
[1].isreg
)
12572 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12573 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12577 NEON_ENCODE (SINGLE
, inst
);
12578 do_vfp_sp_monadic ();
12582 NEON_ENCODE (DOUBLE
, inst
);
12583 do_vfp_dp_rd_rm ();
12588 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12589 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12591 switch (inst
.instruction
& 0x0fffffff)
12594 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12597 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12605 NEON_ENCODE (SINGLE
, inst
);
12606 do_vfp_sp_compare_z ();
12610 NEON_ENCODE (DOUBLE
, inst
);
12614 do_vfp_cond_or_thumb ();
12618 nsyn_insert_sp (void)
12620 inst
.operands
[1] = inst
.operands
[0];
12621 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12622 inst
.operands
[0].reg
= REG_SP
;
12623 inst
.operands
[0].isreg
= 1;
12624 inst
.operands
[0].writeback
= 1;
12625 inst
.operands
[0].present
= 1;
12629 do_vfp_nsyn_push (void)
12632 if (inst
.operands
[1].issingle
)
12633 do_vfp_nsyn_opcode ("fstmdbs");
12635 do_vfp_nsyn_opcode ("fstmdbd");
12639 do_vfp_nsyn_pop (void)
12642 if (inst
.operands
[1].issingle
)
12643 do_vfp_nsyn_opcode ("fldmias");
12645 do_vfp_nsyn_opcode ("fldmiad");
12648 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12649 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12652 neon_dp_fixup (struct arm_it
* insn
)
12654 unsigned int i
= insn
->instruction
;
12659 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12670 insn
->instruction
= i
;
12673 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12677 neon_logbits (unsigned x
)
12679 return ffs (x
) - 4;
12682 #define LOW4(R) ((R) & 0xf)
12683 #define HI1(R) (((R) >> 4) & 1)
12685 /* Encode insns with bit pattern:
12687 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12688 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12690 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12691 different meaning for some instruction. */
12694 neon_three_same (int isquad
, int ubit
, int size
)
12696 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12697 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12698 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12699 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12700 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12701 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12702 inst
.instruction
|= (isquad
!= 0) << 6;
12703 inst
.instruction
|= (ubit
!= 0) << 24;
12705 inst
.instruction
|= neon_logbits (size
) << 20;
12707 neon_dp_fixup (&inst
);
12710 /* Encode instructions of the form:
12712 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12713 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12715 Don't write size if SIZE == -1. */
12718 neon_two_same (int qbit
, int ubit
, int size
)
12720 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12721 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12722 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12723 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12724 inst
.instruction
|= (qbit
!= 0) << 6;
12725 inst
.instruction
|= (ubit
!= 0) << 24;
12728 inst
.instruction
|= neon_logbits (size
) << 18;
12730 neon_dp_fixup (&inst
);
12733 /* Neon instruction encoders, in approximate order of appearance. */
12736 do_neon_dyadic_i_su (void)
12738 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12739 struct neon_type_el et
= neon_check_type (3, rs
,
12740 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12741 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12745 do_neon_dyadic_i64_su (void)
12747 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12748 struct neon_type_el et
= neon_check_type (3, rs
,
12749 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12750 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12754 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12757 unsigned size
= et
.size
>> 3;
12758 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12759 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12760 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12761 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12762 inst
.instruction
|= (isquad
!= 0) << 6;
12763 inst
.instruction
|= immbits
<< 16;
12764 inst
.instruction
|= (size
>> 3) << 7;
12765 inst
.instruction
|= (size
& 0x7) << 19;
12767 inst
.instruction
|= (uval
!= 0) << 24;
12769 neon_dp_fixup (&inst
);
12773 do_neon_shl_imm (void)
12775 if (!inst
.operands
[2].isreg
)
12777 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12778 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12779 NEON_ENCODE (IMMED
, inst
);
12780 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12784 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12785 struct neon_type_el et
= neon_check_type (3, rs
,
12786 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12789 /* VSHL/VQSHL 3-register variants have syntax such as:
12791 whereas other 3-register operations encoded by neon_three_same have
12794 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12796 tmp
= inst
.operands
[2].reg
;
12797 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12798 inst
.operands
[1].reg
= tmp
;
12799 NEON_ENCODE (INTEGER
, inst
);
12800 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12805 do_neon_qshl_imm (void)
12807 if (!inst
.operands
[2].isreg
)
12809 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12810 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12812 NEON_ENCODE (IMMED
, inst
);
12813 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12814 inst
.operands
[2].imm
);
12818 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12819 struct neon_type_el et
= neon_check_type (3, rs
,
12820 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12823 /* See note in do_neon_shl_imm. */
12824 tmp
= inst
.operands
[2].reg
;
12825 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12826 inst
.operands
[1].reg
= tmp
;
12827 NEON_ENCODE (INTEGER
, inst
);
12828 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12833 do_neon_rshl (void)
12835 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12836 struct neon_type_el et
= neon_check_type (3, rs
,
12837 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12840 tmp
= inst
.operands
[2].reg
;
12841 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12842 inst
.operands
[1].reg
= tmp
;
12843 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12847 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12849 /* Handle .I8 pseudo-instructions. */
12852 /* Unfortunately, this will make everything apart from zero out-of-range.
12853 FIXME is this the intended semantics? There doesn't seem much point in
12854 accepting .I8 if so. */
12855 immediate
|= immediate
<< 8;
12861 if (immediate
== (immediate
& 0x000000ff))
12863 *immbits
= immediate
;
12866 else if (immediate
== (immediate
& 0x0000ff00))
12868 *immbits
= immediate
>> 8;
12871 else if (immediate
== (immediate
& 0x00ff0000))
12873 *immbits
= immediate
>> 16;
12876 else if (immediate
== (immediate
& 0xff000000))
12878 *immbits
= immediate
>> 24;
12881 if ((immediate
& 0xffff) != (immediate
>> 16))
12882 goto bad_immediate
;
12883 immediate
&= 0xffff;
12886 if (immediate
== (immediate
& 0x000000ff))
12888 *immbits
= immediate
;
12891 else if (immediate
== (immediate
& 0x0000ff00))
12893 *immbits
= immediate
>> 8;
12898 first_error (_("immediate value out of range"));
12902 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12906 neon_bits_same_in_bytes (unsigned imm
)
12908 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12909 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12910 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12911 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12914 /* For immediate of above form, return 0bABCD. */
12917 neon_squash_bits (unsigned imm
)
12919 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12920 | ((imm
& 0x01000000) >> 21);
12923 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12926 neon_qfloat_bits (unsigned imm
)
12928 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12931 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12932 the instruction. *OP is passed as the initial value of the op field, and
12933 may be set to a different value depending on the constant (i.e.
12934 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12935 MVN). If the immediate looks like a repeated pattern then also
12936 try smaller element sizes. */
12939 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12940 unsigned *immbits
, int *op
, int size
,
12941 enum neon_el_type type
)
12943 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12945 if (type
== NT_float
&& !float_p
)
12948 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12950 if (size
!= 32 || *op
== 1)
12952 *immbits
= neon_qfloat_bits (immlo
);
12958 if (neon_bits_same_in_bytes (immhi
)
12959 && neon_bits_same_in_bytes (immlo
))
12963 *immbits
= (neon_squash_bits (immhi
) << 4)
12964 | neon_squash_bits (immlo
);
12969 if (immhi
!= immlo
)
12975 if (immlo
== (immlo
& 0x000000ff))
12980 else if (immlo
== (immlo
& 0x0000ff00))
12982 *immbits
= immlo
>> 8;
12985 else if (immlo
== (immlo
& 0x00ff0000))
12987 *immbits
= immlo
>> 16;
12990 else if (immlo
== (immlo
& 0xff000000))
12992 *immbits
= immlo
>> 24;
12995 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12997 *immbits
= (immlo
>> 8) & 0xff;
13000 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13002 *immbits
= (immlo
>> 16) & 0xff;
13006 if ((immlo
& 0xffff) != (immlo
>> 16))
13013 if (immlo
== (immlo
& 0x000000ff))
13018 else if (immlo
== (immlo
& 0x0000ff00))
13020 *immbits
= immlo
>> 8;
13024 if ((immlo
& 0xff) != (immlo
>> 8))
13029 if (immlo
== (immlo
& 0x000000ff))
13031 /* Don't allow MVN with 8-bit immediate. */
13041 /* Write immediate bits [7:0] to the following locations:
13043 |28/24|23 19|18 16|15 4|3 0|
13044 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13046 This function is used by VMOV/VMVN/VORR/VBIC. */
13049 neon_write_immbits (unsigned immbits
)
13051 inst
.instruction
|= immbits
& 0xf;
13052 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13053 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13056 /* Invert low-order SIZE bits of XHI:XLO. */
13059 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13061 unsigned immlo
= xlo
? *xlo
: 0;
13062 unsigned immhi
= xhi
? *xhi
: 0;
13067 immlo
= (~immlo
) & 0xff;
13071 immlo
= (~immlo
) & 0xffff;
13075 immhi
= (~immhi
) & 0xffffffff;
13076 /* fall through. */
13079 immlo
= (~immlo
) & 0xffffffff;
13094 do_neon_logic (void)
13096 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13098 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13099 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13100 /* U bit and size field were set as part of the bitmask. */
13101 NEON_ENCODE (INTEGER
, inst
);
13102 neon_three_same (neon_quad (rs
), 0, -1);
13106 const int three_ops_form
= (inst
.operands
[2].present
13107 && !inst
.operands
[2].isreg
);
13108 const int immoperand
= (three_ops_form
? 2 : 1);
13109 enum neon_shape rs
= (three_ops_form
13110 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13111 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13112 struct neon_type_el et
= neon_check_type (2, rs
,
13113 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13114 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13118 if (et
.type
== NT_invtype
)
13121 if (three_ops_form
)
13122 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13123 _("first and second operands shall be the same register"));
13125 NEON_ENCODE (IMMED
, inst
);
13127 immbits
= inst
.operands
[immoperand
].imm
;
13130 /* .i64 is a pseudo-op, so the immediate must be a repeating
13132 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13133 inst
.operands
[immoperand
].reg
: 0))
13135 /* Set immbits to an invalid constant. */
13136 immbits
= 0xdeadbeef;
13143 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13147 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13151 /* Pseudo-instruction for VBIC. */
13152 neon_invert_size (&immbits
, 0, et
.size
);
13153 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13157 /* Pseudo-instruction for VORR. */
13158 neon_invert_size (&immbits
, 0, et
.size
);
13159 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13169 inst
.instruction
|= neon_quad (rs
) << 6;
13170 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13171 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13172 inst
.instruction
|= cmode
<< 8;
13173 neon_write_immbits (immbits
);
13175 neon_dp_fixup (&inst
);
13180 do_neon_bitfield (void)
13182 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13183 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13184 neon_three_same (neon_quad (rs
), 0, -1);
13188 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13191 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13192 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13194 if (et
.type
== NT_float
)
13196 NEON_ENCODE (FLOAT
, inst
);
13197 neon_three_same (neon_quad (rs
), 0, -1);
13201 NEON_ENCODE (INTEGER
, inst
);
13202 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13207 do_neon_dyadic_if_su (void)
13209 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13213 do_neon_dyadic_if_su_d (void)
13215 /* This version only allow D registers, but that constraint is enforced during
13216 operand parsing so we don't need to do anything extra here. */
13217 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13221 do_neon_dyadic_if_i_d (void)
13223 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13224 affected if we specify unsigned args. */
13225 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13228 enum vfp_or_neon_is_neon_bits
13231 NEON_CHECK_ARCH
= 2
13234 /* Call this function if an instruction which may have belonged to the VFP or
13235 Neon instruction sets, but turned out to be a Neon instruction (due to the
13236 operand types involved, etc.). We have to check and/or fix-up a couple of
13239 - Make sure the user hasn't attempted to make a Neon instruction
13241 - Alter the value in the condition code field if necessary.
13242 - Make sure that the arch supports Neon instructions.
13244 Which of these operations take place depends on bits from enum
13245 vfp_or_neon_is_neon_bits.
13247 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13248 current instruction's condition is COND_ALWAYS, the condition field is
13249 changed to inst.uncond_value. This is necessary because instructions shared
13250 between VFP and Neon may be conditional for the VFP variants only, and the
13251 unconditional Neon version must have, e.g., 0xF in the condition field. */
13254 vfp_or_neon_is_neon (unsigned check
)
13256 /* Conditions are always legal in Thumb mode (IT blocks). */
13257 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13259 if (inst
.cond
!= COND_ALWAYS
)
13261 first_error (_(BAD_COND
));
13264 if (inst
.uncond_value
!= -1)
13265 inst
.instruction
|= inst
.uncond_value
<< 28;
13268 if ((check
& NEON_CHECK_ARCH
)
13269 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13271 first_error (_(BAD_FPU
));
13279 do_neon_addsub_if_i (void)
13281 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13284 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13287 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13288 affected if we specify unsigned args. */
13289 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13292 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13294 V<op> A,B (A is operand 0, B is operand 2)
13299 so handle that case specially. */
13302 neon_exchange_operands (void)
13304 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13305 if (inst
.operands
[1].present
)
13307 /* Swap operands[1] and operands[2]. */
13308 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13309 inst
.operands
[1] = inst
.operands
[2];
13310 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13314 inst
.operands
[1] = inst
.operands
[2];
13315 inst
.operands
[2] = inst
.operands
[0];
13320 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13322 if (inst
.operands
[2].isreg
)
13325 neon_exchange_operands ();
13326 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13330 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13331 struct neon_type_el et
= neon_check_type (2, rs
,
13332 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13334 NEON_ENCODE (IMMED
, inst
);
13335 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13336 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13337 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13338 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13339 inst
.instruction
|= neon_quad (rs
) << 6;
13340 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13341 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13343 neon_dp_fixup (&inst
);
13350 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13354 do_neon_cmp_inv (void)
13356 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13362 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13365 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13366 scalars, which are encoded in 5 bits, M : Rm.
13367 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13368 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13372 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13374 unsigned regno
= NEON_SCALAR_REG (scalar
);
13375 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13380 if (regno
> 7 || elno
> 3)
13382 return regno
| (elno
<< 3);
13385 if (regno
> 15 || elno
> 1)
13387 return regno
| (elno
<< 4);
13391 first_error (_("scalar out of range for multiply instruction"));
13397 /* Encode multiply / multiply-accumulate scalar instructions. */
13400 neon_mul_mac (struct neon_type_el et
, int ubit
)
13404 /* Give a more helpful error message if we have an invalid type. */
13405 if (et
.type
== NT_invtype
)
13408 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13409 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13410 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13411 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13412 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13413 inst
.instruction
|= LOW4 (scalar
);
13414 inst
.instruction
|= HI1 (scalar
) << 5;
13415 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13416 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13417 inst
.instruction
|= (ubit
!= 0) << 24;
13419 neon_dp_fixup (&inst
);
13423 do_neon_mac_maybe_scalar (void)
13425 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13428 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13431 if (inst
.operands
[2].isscalar
)
13433 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13434 struct neon_type_el et
= neon_check_type (3, rs
,
13435 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13436 NEON_ENCODE (SCALAR
, inst
);
13437 neon_mul_mac (et
, neon_quad (rs
));
13441 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13442 affected if we specify unsigned args. */
13443 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13448 do_neon_fmac (void)
13450 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13453 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13456 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13462 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13463 struct neon_type_el et
= neon_check_type (3, rs
,
13464 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13465 neon_three_same (neon_quad (rs
), 0, et
.size
);
13468 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13469 same types as the MAC equivalents. The polynomial type for this instruction
13470 is encoded the same as the integer type. */
13475 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13478 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13481 if (inst
.operands
[2].isscalar
)
13482 do_neon_mac_maybe_scalar ();
13484 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13488 do_neon_qdmulh (void)
13490 if (inst
.operands
[2].isscalar
)
13492 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13493 struct neon_type_el et
= neon_check_type (3, rs
,
13494 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13495 NEON_ENCODE (SCALAR
, inst
);
13496 neon_mul_mac (et
, neon_quad (rs
));
13500 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13501 struct neon_type_el et
= neon_check_type (3, rs
,
13502 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13503 NEON_ENCODE (INTEGER
, inst
);
13504 /* The U bit (rounding) comes from bit mask. */
13505 neon_three_same (neon_quad (rs
), 0, et
.size
);
13510 do_neon_fcmp_absolute (void)
13512 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13513 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13514 /* Size field comes from bit mask. */
13515 neon_three_same (neon_quad (rs
), 1, -1);
13519 do_neon_fcmp_absolute_inv (void)
13521 neon_exchange_operands ();
13522 do_neon_fcmp_absolute ();
13526 do_neon_step (void)
13528 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13529 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13530 neon_three_same (neon_quad (rs
), 0, -1);
13534 do_neon_abs_neg (void)
13536 enum neon_shape rs
;
13537 struct neon_type_el et
;
13539 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13542 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13545 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13546 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13548 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13549 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13550 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13551 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13552 inst
.instruction
|= neon_quad (rs
) << 6;
13553 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13554 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13556 neon_dp_fixup (&inst
);
13562 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13563 struct neon_type_el et
= neon_check_type (2, rs
,
13564 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13565 int imm
= inst
.operands
[2].imm
;
13566 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13567 _("immediate out of range for insert"));
13568 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13574 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13575 struct neon_type_el et
= neon_check_type (2, rs
,
13576 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13577 int imm
= inst
.operands
[2].imm
;
13578 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13579 _("immediate out of range for insert"));
13580 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13584 do_neon_qshlu_imm (void)
13586 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13587 struct neon_type_el et
= neon_check_type (2, rs
,
13588 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13589 int imm
= inst
.operands
[2].imm
;
13590 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13591 _("immediate out of range for shift"));
13592 /* Only encodes the 'U present' variant of the instruction.
13593 In this case, signed types have OP (bit 8) set to 0.
13594 Unsigned types have OP set to 1. */
13595 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13596 /* The rest of the bits are the same as other immediate shifts. */
13597 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13601 do_neon_qmovn (void)
13603 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13604 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13605 /* Saturating move where operands can be signed or unsigned, and the
13606 destination has the same signedness. */
13607 NEON_ENCODE (INTEGER
, inst
);
13608 if (et
.type
== NT_unsigned
)
13609 inst
.instruction
|= 0xc0;
13611 inst
.instruction
|= 0x80;
13612 neon_two_same (0, 1, et
.size
/ 2);
13616 do_neon_qmovun (void)
13618 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13619 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13620 /* Saturating move with unsigned results. Operands must be signed. */
13621 NEON_ENCODE (INTEGER
, inst
);
13622 neon_two_same (0, 1, et
.size
/ 2);
13626 do_neon_rshift_sat_narrow (void)
13628 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13629 or unsigned. If operands are unsigned, results must also be unsigned. */
13630 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13631 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13632 int imm
= inst
.operands
[2].imm
;
13633 /* This gets the bounds check, size encoding and immediate bits calculation
13637 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13638 VQMOVN.I<size> <Dd>, <Qm>. */
13641 inst
.operands
[2].present
= 0;
13642 inst
.instruction
= N_MNEM_vqmovn
;
13647 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13648 _("immediate out of range"));
13649 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13653 do_neon_rshift_sat_narrow_u (void)
13655 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13656 or unsigned. If operands are unsigned, results must also be unsigned. */
13657 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13658 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13659 int imm
= inst
.operands
[2].imm
;
13660 /* This gets the bounds check, size encoding and immediate bits calculation
13664 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13665 VQMOVUN.I<size> <Dd>, <Qm>. */
13668 inst
.operands
[2].present
= 0;
13669 inst
.instruction
= N_MNEM_vqmovun
;
13674 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13675 _("immediate out of range"));
13676 /* FIXME: The manual is kind of unclear about what value U should have in
13677 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13679 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13683 do_neon_movn (void)
13685 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13686 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13687 NEON_ENCODE (INTEGER
, inst
);
13688 neon_two_same (0, 1, et
.size
/ 2);
13692 do_neon_rshift_narrow (void)
13694 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13695 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13696 int imm
= inst
.operands
[2].imm
;
13697 /* This gets the bounds check, size encoding and immediate bits calculation
13701 /* If immediate is zero then we are a pseudo-instruction for
13702 VMOVN.I<size> <Dd>, <Qm> */
13705 inst
.operands
[2].present
= 0;
13706 inst
.instruction
= N_MNEM_vmovn
;
13711 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13712 _("immediate out of range for narrowing operation"));
13713 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13717 do_neon_shll (void)
13719 /* FIXME: Type checking when lengthening. */
13720 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13721 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13722 unsigned imm
= inst
.operands
[2].imm
;
13724 if (imm
== et
.size
)
13726 /* Maximum shift variant. */
13727 NEON_ENCODE (INTEGER
, inst
);
13728 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13729 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13730 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13731 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13732 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13734 neon_dp_fixup (&inst
);
13738 /* A more-specific type check for non-max versions. */
13739 et
= neon_check_type (2, NS_QDI
,
13740 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13741 NEON_ENCODE (IMMED
, inst
);
13742 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13746 /* Check the various types for the VCVT instruction, and return which version
13747 the current instruction is. */
13750 neon_cvt_flavour (enum neon_shape rs
)
13752 #define CVT_VAR(C,X,Y) \
13753 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13754 if (et.type != NT_invtype) \
13756 inst.error = NULL; \
13759 struct neon_type_el et
;
13760 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13761 || rs
== NS_FF
) ? N_VFP
: 0;
13762 /* The instruction versions which take an immediate take one register
13763 argument, which is extended to the width of the full register. Thus the
13764 "source" and "destination" registers must have the same width. Hack that
13765 here by making the size equal to the key (wider, in this case) operand. */
13766 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13768 CVT_VAR (0, N_S32
, N_F32
);
13769 CVT_VAR (1, N_U32
, N_F32
);
13770 CVT_VAR (2, N_F32
, N_S32
);
13771 CVT_VAR (3, N_F32
, N_U32
);
13772 /* Half-precision conversions. */
13773 CVT_VAR (4, N_F32
, N_F16
);
13774 CVT_VAR (5, N_F16
, N_F32
);
13778 /* VFP instructions. */
13779 CVT_VAR (6, N_F32
, N_F64
);
13780 CVT_VAR (7, N_F64
, N_F32
);
13781 CVT_VAR (8, N_S32
, N_F64
| key
);
13782 CVT_VAR (9, N_U32
, N_F64
| key
);
13783 CVT_VAR (10, N_F64
| key
, N_S32
);
13784 CVT_VAR (11, N_F64
| key
, N_U32
);
13785 /* VFP instructions with bitshift. */
13786 CVT_VAR (12, N_F32
| key
, N_S16
);
13787 CVT_VAR (13, N_F32
| key
, N_U16
);
13788 CVT_VAR (14, N_F64
| key
, N_S16
);
13789 CVT_VAR (15, N_F64
| key
, N_U16
);
13790 CVT_VAR (16, N_S16
, N_F32
| key
);
13791 CVT_VAR (17, N_U16
, N_F32
| key
);
13792 CVT_VAR (18, N_S16
, N_F64
| key
);
13793 CVT_VAR (19, N_U16
, N_F64
| key
);
13799 /* Neon-syntax VFP conversions. */
13802 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13804 const char *opname
= 0;
13806 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13808 /* Conversions with immediate bitshift. */
13809 const char *enc
[] =
13833 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13835 opname
= enc
[flavour
];
13836 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13837 _("operands 0 and 1 must be the same register"));
13838 inst
.operands
[1] = inst
.operands
[2];
13839 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13844 /* Conversions without bitshift. */
13845 const char *enc
[] =
13861 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13862 opname
= enc
[flavour
];
13866 do_vfp_nsyn_opcode (opname
);
13870 do_vfp_nsyn_cvtz (void)
13872 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13873 int flavour
= neon_cvt_flavour (rs
);
13874 const char *enc
[] =
13888 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13889 do_vfp_nsyn_opcode (enc
[flavour
]);
13893 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13895 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13896 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13897 int flavour
= neon_cvt_flavour (rs
);
13899 /* PR11109: Handle round-to-zero for VCVT conversions. */
13901 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13902 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13903 && (rs
== NS_FD
|| rs
== NS_FF
))
13905 do_vfp_nsyn_cvtz ();
13909 /* VFP rather than Neon conversions. */
13912 do_vfp_nsyn_cvt (rs
, flavour
);
13922 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13924 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13927 /* Fixed-point conversion with #0 immediate is encoded as an
13928 integer conversion. */
13929 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13931 immbits
= 32 - inst
.operands
[2].imm
;
13932 NEON_ENCODE (IMMED
, inst
);
13934 inst
.instruction
|= enctab
[flavour
];
13935 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13936 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13937 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13938 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13939 inst
.instruction
|= neon_quad (rs
) << 6;
13940 inst
.instruction
|= 1 << 21;
13941 inst
.instruction
|= immbits
<< 16;
13943 neon_dp_fixup (&inst
);
13951 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13953 NEON_ENCODE (INTEGER
, inst
);
13955 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13959 inst
.instruction
|= enctab
[flavour
];
13961 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13962 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13963 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13964 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13965 inst
.instruction
|= neon_quad (rs
) << 6;
13966 inst
.instruction
|= 2 << 18;
13968 neon_dp_fixup (&inst
);
13972 /* Half-precision conversions for Advanced SIMD -- neon. */
13977 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13979 as_bad (_("operand size must match register width"));
13984 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13986 as_bad (_("operand size must match register width"));
13991 inst
.instruction
= 0x3b60600;
13993 inst
.instruction
= 0x3b60700;
13995 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13996 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13997 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13998 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13999 neon_dp_fixup (&inst
);
14003 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14004 do_vfp_nsyn_cvt (rs
, flavour
);
14009 do_neon_cvtr (void)
14011 do_neon_cvt_1 (FALSE
);
14017 do_neon_cvt_1 (TRUE
);
14021 do_neon_cvtb (void)
14023 inst
.instruction
= 0xeb20a40;
14025 /* The sizes are attached to the mnemonic. */
14026 if (inst
.vectype
.el
[0].type
!= NT_invtype
14027 && inst
.vectype
.el
[0].size
== 16)
14028 inst
.instruction
|= 0x00010000;
14030 /* Programmer's syntax: the sizes are attached to the operands. */
14031 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14032 && inst
.operands
[0].vectype
.size
== 16)
14033 inst
.instruction
|= 0x00010000;
14035 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14036 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14037 do_vfp_cond_or_thumb ();
14042 do_neon_cvtt (void)
14045 inst
.instruction
|= 0x80;
14049 neon_move_immediate (void)
14051 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14052 struct neon_type_el et
= neon_check_type (2, rs
,
14053 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14054 unsigned immlo
, immhi
= 0, immbits
;
14055 int op
, cmode
, float_p
;
14057 constraint (et
.type
== NT_invtype
,
14058 _("operand size must be specified for immediate VMOV"));
14060 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14061 op
= (inst
.instruction
& (1 << 5)) != 0;
14063 immlo
= inst
.operands
[1].imm
;
14064 if (inst
.operands
[1].regisimm
)
14065 immhi
= inst
.operands
[1].reg
;
14067 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14068 _("immediate has bits set outside the operand size"));
14070 float_p
= inst
.operands
[1].immisfloat
;
14072 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14073 et
.size
, et
.type
)) == FAIL
)
14075 /* Invert relevant bits only. */
14076 neon_invert_size (&immlo
, &immhi
, et
.size
);
14077 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14078 with one or the other; those cases are caught by
14079 neon_cmode_for_move_imm. */
14081 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14082 &op
, et
.size
, et
.type
)) == FAIL
)
14084 first_error (_("immediate out of range"));
14089 inst
.instruction
&= ~(1 << 5);
14090 inst
.instruction
|= op
<< 5;
14092 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14093 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14094 inst
.instruction
|= neon_quad (rs
) << 6;
14095 inst
.instruction
|= cmode
<< 8;
14097 neon_write_immbits (immbits
);
14103 if (inst
.operands
[1].isreg
)
14105 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14107 NEON_ENCODE (INTEGER
, inst
);
14108 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14109 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14110 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14111 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14112 inst
.instruction
|= neon_quad (rs
) << 6;
14116 NEON_ENCODE (IMMED
, inst
);
14117 neon_move_immediate ();
14120 neon_dp_fixup (&inst
);
14123 /* Encode instructions of form:
14125 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14126 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14129 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14131 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14132 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14133 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14134 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14135 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14136 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14137 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14138 inst
.instruction
|= neon_logbits (size
) << 20;
14140 neon_dp_fixup (&inst
);
14144 do_neon_dyadic_long (void)
14146 /* FIXME: Type checking for lengthening op. */
14147 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14148 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14149 neon_mixed_length (et
, et
.size
);
14153 do_neon_abal (void)
14155 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14156 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14157 neon_mixed_length (et
, et
.size
);
14161 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14163 if (inst
.operands
[2].isscalar
)
14165 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14166 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14167 NEON_ENCODE (SCALAR
, inst
);
14168 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14172 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14173 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14174 NEON_ENCODE (INTEGER
, inst
);
14175 neon_mixed_length (et
, et
.size
);
14180 do_neon_mac_maybe_scalar_long (void)
14182 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14186 do_neon_dyadic_wide (void)
14188 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14189 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14190 neon_mixed_length (et
, et
.size
);
14194 do_neon_dyadic_narrow (void)
14196 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14197 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14198 /* Operand sign is unimportant, and the U bit is part of the opcode,
14199 so force the operand type to integer. */
14200 et
.type
= NT_integer
;
14201 neon_mixed_length (et
, et
.size
/ 2);
14205 do_neon_mul_sat_scalar_long (void)
14207 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14211 do_neon_vmull (void)
14213 if (inst
.operands
[2].isscalar
)
14214 do_neon_mac_maybe_scalar_long ();
14217 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14218 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14219 if (et
.type
== NT_poly
)
14220 NEON_ENCODE (POLY
, inst
);
14222 NEON_ENCODE (INTEGER
, inst
);
14223 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14224 zero. Should be OK as-is. */
14225 neon_mixed_length (et
, et
.size
);
14232 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14233 struct neon_type_el et
= neon_check_type (3, rs
,
14234 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14235 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14237 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14238 _("shift out of range"));
14239 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14240 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14241 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14242 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14243 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14244 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14245 inst
.instruction
|= neon_quad (rs
) << 6;
14246 inst
.instruction
|= imm
<< 8;
14248 neon_dp_fixup (&inst
);
14254 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14255 struct neon_type_el et
= neon_check_type (2, rs
,
14256 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14257 unsigned op
= (inst
.instruction
>> 7) & 3;
14258 /* N (width of reversed regions) is encoded as part of the bitmask. We
14259 extract it here to check the elements to be reversed are smaller.
14260 Otherwise we'd get a reserved instruction. */
14261 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14262 gas_assert (elsize
!= 0);
14263 constraint (et
.size
>= elsize
,
14264 _("elements must be smaller than reversal region"));
14265 neon_two_same (neon_quad (rs
), 1, et
.size
);
14271 if (inst
.operands
[1].isscalar
)
14273 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14274 struct neon_type_el et
= neon_check_type (2, rs
,
14275 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14276 unsigned sizebits
= et
.size
>> 3;
14277 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14278 int logsize
= neon_logbits (et
.size
);
14279 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14281 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14284 NEON_ENCODE (SCALAR
, inst
);
14285 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14286 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14287 inst
.instruction
|= LOW4 (dm
);
14288 inst
.instruction
|= HI1 (dm
) << 5;
14289 inst
.instruction
|= neon_quad (rs
) << 6;
14290 inst
.instruction
|= x
<< 17;
14291 inst
.instruction
|= sizebits
<< 16;
14293 neon_dp_fixup (&inst
);
14297 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14298 struct neon_type_el et
= neon_check_type (2, rs
,
14299 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14300 /* Duplicate ARM register to lanes of vector. */
14301 NEON_ENCODE (ARMREG
, inst
);
14304 case 8: inst
.instruction
|= 0x400000; break;
14305 case 16: inst
.instruction
|= 0x000020; break;
14306 case 32: inst
.instruction
|= 0x000000; break;
14309 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14310 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14311 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14312 inst
.instruction
|= neon_quad (rs
) << 21;
14313 /* The encoding for this instruction is identical for the ARM and Thumb
14314 variants, except for the condition field. */
14315 do_vfp_cond_or_thumb ();
14319 /* VMOV has particularly many variations. It can be one of:
14320 0. VMOV<c><q> <Qd>, <Qm>
14321 1. VMOV<c><q> <Dd>, <Dm>
14322 (Register operations, which are VORR with Rm = Rn.)
14323 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14324 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14326 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14327 (ARM register to scalar.)
14328 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14329 (Two ARM registers to vector.)
14330 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14331 (Scalar to ARM register.)
14332 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14333 (Vector to two ARM registers.)
14334 8. VMOV.F32 <Sd>, <Sm>
14335 9. VMOV.F64 <Dd>, <Dm>
14336 (VFP register moves.)
14337 10. VMOV.F32 <Sd>, #imm
14338 11. VMOV.F64 <Dd>, #imm
14339 (VFP float immediate load.)
14340 12. VMOV <Rd>, <Sm>
14341 (VFP single to ARM reg.)
14342 13. VMOV <Sd>, <Rm>
14343 (ARM reg to VFP single.)
14344 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14345 (Two ARM regs to two VFP singles.)
14346 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14347 (Two VFP singles to two ARM regs.)
14349 These cases can be disambiguated using neon_select_shape, except cases 1/9
14350 and 3/11 which depend on the operand type too.
14352 All the encoded bits are hardcoded by this function.
14354 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14355 Cases 5, 7 may be used with VFPv2 and above.
14357 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14358 can specify a type where it doesn't make sense to, and is ignored). */
14363 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14364 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14366 struct neon_type_el et
;
14367 const char *ldconst
= 0;
14371 case NS_DD
: /* case 1/9. */
14372 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14373 /* It is not an error here if no type is given. */
14375 if (et
.type
== NT_float
&& et
.size
== 64)
14377 do_vfp_nsyn_opcode ("fcpyd");
14380 /* fall through. */
14382 case NS_QQ
: /* case 0/1. */
14384 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14386 /* The architecture manual I have doesn't explicitly state which
14387 value the U bit should have for register->register moves, but
14388 the equivalent VORR instruction has U = 0, so do that. */
14389 inst
.instruction
= 0x0200110;
14390 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14391 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14392 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14393 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14394 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14395 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14396 inst
.instruction
|= neon_quad (rs
) << 6;
14398 neon_dp_fixup (&inst
);
14402 case NS_DI
: /* case 3/11. */
14403 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14405 if (et
.type
== NT_float
&& et
.size
== 64)
14407 /* case 11 (fconstd). */
14408 ldconst
= "fconstd";
14409 goto encode_fconstd
;
14411 /* fall through. */
14413 case NS_QI
: /* case 2/3. */
14414 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14416 inst
.instruction
= 0x0800010;
14417 neon_move_immediate ();
14418 neon_dp_fixup (&inst
);
14421 case NS_SR
: /* case 4. */
14423 unsigned bcdebits
= 0;
14425 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14426 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14428 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14429 logsize
= neon_logbits (et
.size
);
14431 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14433 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14434 && et
.size
!= 32, _(BAD_FPU
));
14435 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14436 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14440 case 8: bcdebits
= 0x8; break;
14441 case 16: bcdebits
= 0x1; break;
14442 case 32: bcdebits
= 0x0; break;
14446 bcdebits
|= x
<< logsize
;
14448 inst
.instruction
= 0xe000b10;
14449 do_vfp_cond_or_thumb ();
14450 inst
.instruction
|= LOW4 (dn
) << 16;
14451 inst
.instruction
|= HI1 (dn
) << 7;
14452 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14453 inst
.instruction
|= (bcdebits
& 3) << 5;
14454 inst
.instruction
|= (bcdebits
>> 2) << 21;
14458 case NS_DRR
: /* case 5 (fmdrr). */
14459 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14462 inst
.instruction
= 0xc400b10;
14463 do_vfp_cond_or_thumb ();
14464 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14465 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14466 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14467 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14470 case NS_RS
: /* case 6. */
14473 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14474 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14475 unsigned abcdebits
= 0;
14477 et
= neon_check_type (2, NS_NULL
,
14478 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14479 logsize
= neon_logbits (et
.size
);
14481 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14483 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14484 && et
.size
!= 32, _(BAD_FPU
));
14485 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14486 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14490 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14491 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14492 case 32: abcdebits
= 0x00; break;
14496 abcdebits
|= x
<< logsize
;
14497 inst
.instruction
= 0xe100b10;
14498 do_vfp_cond_or_thumb ();
14499 inst
.instruction
|= LOW4 (dn
) << 16;
14500 inst
.instruction
|= HI1 (dn
) << 7;
14501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14502 inst
.instruction
|= (abcdebits
& 3) << 5;
14503 inst
.instruction
|= (abcdebits
>> 2) << 21;
14507 case NS_RRD
: /* case 7 (fmrrd). */
14508 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14511 inst
.instruction
= 0xc500b10;
14512 do_vfp_cond_or_thumb ();
14513 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14514 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14515 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14516 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14519 case NS_FF
: /* case 8 (fcpys). */
14520 do_vfp_nsyn_opcode ("fcpys");
14523 case NS_FI
: /* case 10 (fconsts). */
14524 ldconst
= "fconsts";
14526 if (is_quarter_float (inst
.operands
[1].imm
))
14528 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14529 do_vfp_nsyn_opcode (ldconst
);
14532 first_error (_("immediate out of range"));
14535 case NS_RF
: /* case 12 (fmrs). */
14536 do_vfp_nsyn_opcode ("fmrs");
14539 case NS_FR
: /* case 13 (fmsr). */
14540 do_vfp_nsyn_opcode ("fmsr");
14543 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14544 (one of which is a list), but we have parsed four. Do some fiddling to
14545 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14547 case NS_RRFF
: /* case 14 (fmrrs). */
14548 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14549 _("VFP registers must be adjacent"));
14550 inst
.operands
[2].imm
= 2;
14551 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14552 do_vfp_nsyn_opcode ("fmrrs");
14555 case NS_FFRR
: /* case 15 (fmsrr). */
14556 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14557 _("VFP registers must be adjacent"));
14558 inst
.operands
[1] = inst
.operands
[2];
14559 inst
.operands
[2] = inst
.operands
[3];
14560 inst
.operands
[0].imm
= 2;
14561 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14562 do_vfp_nsyn_opcode ("fmsrr");
14571 do_neon_rshift_round_imm (void)
14573 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14574 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14575 int imm
= inst
.operands
[2].imm
;
14577 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14580 inst
.operands
[2].present
= 0;
14585 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14586 _("immediate out of range for shift"));
14587 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14592 do_neon_movl (void)
14594 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14595 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14596 unsigned sizebits
= et
.size
>> 3;
14597 inst
.instruction
|= sizebits
<< 19;
14598 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14604 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14605 struct neon_type_el et
= neon_check_type (2, rs
,
14606 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14607 NEON_ENCODE (INTEGER
, inst
);
14608 neon_two_same (neon_quad (rs
), 1, et
.size
);
14612 do_neon_zip_uzp (void)
14614 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14615 struct neon_type_el et
= neon_check_type (2, rs
,
14616 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14617 if (rs
== NS_DD
&& et
.size
== 32)
14619 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14620 inst
.instruction
= N_MNEM_vtrn
;
14624 neon_two_same (neon_quad (rs
), 1, et
.size
);
14628 do_neon_sat_abs_neg (void)
14630 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14631 struct neon_type_el et
= neon_check_type (2, rs
,
14632 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14633 neon_two_same (neon_quad (rs
), 1, et
.size
);
14637 do_neon_pair_long (void)
14639 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14640 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14641 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14642 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14643 neon_two_same (neon_quad (rs
), 1, et
.size
);
14647 do_neon_recip_est (void)
14649 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14650 struct neon_type_el et
= neon_check_type (2, rs
,
14651 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14652 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14653 neon_two_same (neon_quad (rs
), 1, et
.size
);
14659 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14660 struct neon_type_el et
= neon_check_type (2, rs
,
14661 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14662 neon_two_same (neon_quad (rs
), 1, et
.size
);
14668 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14669 struct neon_type_el et
= neon_check_type (2, rs
,
14670 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14671 neon_two_same (neon_quad (rs
), 1, et
.size
);
14677 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14678 struct neon_type_el et
= neon_check_type (2, rs
,
14679 N_EQK
| N_INT
, N_8
| N_KEY
);
14680 neon_two_same (neon_quad (rs
), 1, et
.size
);
14686 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14687 neon_two_same (neon_quad (rs
), 1, -1);
14691 do_neon_tbl_tbx (void)
14693 unsigned listlenbits
;
14694 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14696 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14698 first_error (_("bad list length for table lookup"));
14702 listlenbits
= inst
.operands
[1].imm
- 1;
14703 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14704 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14705 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14706 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14707 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14708 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14709 inst
.instruction
|= listlenbits
<< 8;
14711 neon_dp_fixup (&inst
);
14715 do_neon_ldm_stm (void)
14717 /* P, U and L bits are part of bitmask. */
14718 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14719 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14721 if (inst
.operands
[1].issingle
)
14723 do_vfp_nsyn_ldm_stm (is_dbmode
);
14727 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14728 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14730 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14731 _("register list must contain at least 1 and at most 16 "
14734 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14735 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14736 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14737 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14739 inst
.instruction
|= offsetbits
;
14741 do_vfp_cond_or_thumb ();
14745 do_neon_ldr_str (void)
14747 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14749 if (inst
.operands
[0].issingle
)
14752 do_vfp_nsyn_opcode ("flds");
14754 do_vfp_nsyn_opcode ("fsts");
14759 do_vfp_nsyn_opcode ("fldd");
14761 do_vfp_nsyn_opcode ("fstd");
14765 /* "interleave" version also handles non-interleaving register VLD1/VST1
14769 do_neon_ld_st_interleave (void)
14771 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14772 N_8
| N_16
| N_32
| N_64
);
14773 unsigned alignbits
= 0;
14775 /* The bits in this table go:
14776 0: register stride of one (0) or two (1)
14777 1,2: register list length, minus one (1, 2, 3, 4).
14778 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14779 We use -1 for invalid entries. */
14780 const int typetable
[] =
14782 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14783 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14784 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14785 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14789 if (et
.type
== NT_invtype
)
14792 if (inst
.operands
[1].immisalign
)
14793 switch (inst
.operands
[1].imm
>> 8)
14795 case 64: alignbits
= 1; break;
14797 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14798 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14799 goto bad_alignment
;
14803 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14804 goto bad_alignment
;
14809 first_error (_("bad alignment"));
14813 inst
.instruction
|= alignbits
<< 4;
14814 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14816 /* Bits [4:6] of the immediate in a list specifier encode register stride
14817 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14818 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14819 up the right value for "type" in a table based on this value and the given
14820 list style, then stick it back. */
14821 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14822 | (((inst
.instruction
>> 8) & 3) << 3);
14824 typebits
= typetable
[idx
];
14826 constraint (typebits
== -1, _("bad list type for instruction"));
14828 inst
.instruction
&= ~0xf00;
14829 inst
.instruction
|= typebits
<< 8;
14832 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14833 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14834 otherwise. The variable arguments are a list of pairs of legal (size, align)
14835 values, terminated with -1. */
14838 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14841 int result
= FAIL
, thissize
, thisalign
;
14843 if (!inst
.operands
[1].immisalign
)
14849 va_start (ap
, do_align
);
14853 thissize
= va_arg (ap
, int);
14854 if (thissize
== -1)
14856 thisalign
= va_arg (ap
, int);
14858 if (size
== thissize
&& align
== thisalign
)
14861 while (result
!= SUCCESS
);
14865 if (result
== SUCCESS
)
14868 first_error (_("unsupported alignment for instruction"));
14874 do_neon_ld_st_lane (void)
14876 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14877 int align_good
, do_align
= 0;
14878 int logsize
= neon_logbits (et
.size
);
14879 int align
= inst
.operands
[1].imm
>> 8;
14880 int n
= (inst
.instruction
>> 8) & 3;
14881 int max_el
= 64 / et
.size
;
14883 if (et
.type
== NT_invtype
)
14886 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14887 _("bad list length"));
14888 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14889 _("scalar index out of range"));
14890 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14892 _("stride of 2 unavailable when element size is 8"));
14896 case 0: /* VLD1 / VST1. */
14897 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14899 if (align_good
== FAIL
)
14903 unsigned alignbits
= 0;
14906 case 16: alignbits
= 0x1; break;
14907 case 32: alignbits
= 0x3; break;
14910 inst
.instruction
|= alignbits
<< 4;
14914 case 1: /* VLD2 / VST2. */
14915 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14917 if (align_good
== FAIL
)
14920 inst
.instruction
|= 1 << 4;
14923 case 2: /* VLD3 / VST3. */
14924 constraint (inst
.operands
[1].immisalign
,
14925 _("can't use alignment with this instruction"));
14928 case 3: /* VLD4 / VST4. */
14929 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14930 16, 64, 32, 64, 32, 128, -1);
14931 if (align_good
== FAIL
)
14935 unsigned alignbits
= 0;
14938 case 8: alignbits
= 0x1; break;
14939 case 16: alignbits
= 0x1; break;
14940 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14943 inst
.instruction
|= alignbits
<< 4;
14950 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14951 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14952 inst
.instruction
|= 1 << (4 + logsize
);
14954 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14955 inst
.instruction
|= logsize
<< 10;
14958 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14961 do_neon_ld_dup (void)
14963 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14964 int align_good
, do_align
= 0;
14966 if (et
.type
== NT_invtype
)
14969 switch ((inst
.instruction
>> 8) & 3)
14971 case 0: /* VLD1. */
14972 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14973 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14974 &do_align
, 16, 16, 32, 32, -1);
14975 if (align_good
== FAIL
)
14977 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14980 case 2: inst
.instruction
|= 1 << 5; break;
14981 default: first_error (_("bad list length")); return;
14983 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14986 case 1: /* VLD2. */
14987 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14988 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14989 if (align_good
== FAIL
)
14991 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14992 _("bad list length"));
14993 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14994 inst
.instruction
|= 1 << 5;
14995 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14998 case 2: /* VLD3. */
14999 constraint (inst
.operands
[1].immisalign
,
15000 _("can't use alignment with this instruction"));
15001 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15002 _("bad list length"));
15003 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15004 inst
.instruction
|= 1 << 5;
15005 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15008 case 3: /* VLD4. */
15010 int align
= inst
.operands
[1].imm
>> 8;
15011 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15012 16, 64, 32, 64, 32, 128, -1);
15013 if (align_good
== FAIL
)
15015 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15016 _("bad list length"));
15017 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15018 inst
.instruction
|= 1 << 5;
15019 if (et
.size
== 32 && align
== 128)
15020 inst
.instruction
|= 0x3 << 6;
15022 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15029 inst
.instruction
|= do_align
<< 4;
15032 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15033 apart from bits [11:4]. */
15036 do_neon_ldx_stx (void)
15038 if (inst
.operands
[1].isreg
)
15039 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15041 switch (NEON_LANE (inst
.operands
[0].imm
))
15043 case NEON_INTERLEAVE_LANES
:
15044 NEON_ENCODE (INTERLV
, inst
);
15045 do_neon_ld_st_interleave ();
15048 case NEON_ALL_LANES
:
15049 NEON_ENCODE (DUP
, inst
);
15054 NEON_ENCODE (LANE
, inst
);
15055 do_neon_ld_st_lane ();
15058 /* L bit comes from bit mask. */
15059 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15060 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15061 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15063 if (inst
.operands
[1].postind
)
15065 int postreg
= inst
.operands
[1].imm
& 0xf;
15066 constraint (!inst
.operands
[1].immisreg
,
15067 _("post-index must be a register"));
15068 constraint (postreg
== 0xd || postreg
== 0xf,
15069 _("bad register for post-index"));
15070 inst
.instruction
|= postreg
;
15072 else if (inst
.operands
[1].writeback
)
15074 inst
.instruction
|= 0xd;
15077 inst
.instruction
|= 0xf;
15080 inst
.instruction
|= 0xf9000000;
15082 inst
.instruction
|= 0xf4000000;
15085 /* Overall per-instruction processing. */
15087 /* We need to be able to fix up arbitrary expressions in some statements.
15088 This is so that we can handle symbols that are an arbitrary distance from
15089 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15090 which returns part of an address in a form which will be valid for
15091 a data instruction. We do this by pushing the expression into a symbol
15092 in the expr_section, and creating a fix for that. */
15095 fix_new_arm (fragS
* frag
,
15110 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15111 (enum bfd_reloc_code_real
) reloc
);
15115 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15116 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15120 /* Mark whether the fix is to a THUMB instruction, or an ARM
15122 new_fix
->tc_fix_data
= thumb_mode
;
15125 /* Create a frg for an instruction requiring relaxation. */
15127 output_relax_insn (void)
15133 /* The size of the instruction is unknown, so tie the debug info to the
15134 start of the instruction. */
15135 dwarf2_emit_insn (0);
15137 switch (inst
.reloc
.exp
.X_op
)
15140 sym
= inst
.reloc
.exp
.X_add_symbol
;
15141 offset
= inst
.reloc
.exp
.X_add_number
;
15145 offset
= inst
.reloc
.exp
.X_add_number
;
15148 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15152 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15153 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15154 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15157 /* Write a 32-bit thumb instruction to buf. */
15159 put_thumb32_insn (char * buf
, unsigned long insn
)
15161 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15162 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15166 output_inst (const char * str
)
15172 as_bad ("%s -- `%s'", inst
.error
, str
);
15177 output_relax_insn ();
15180 if (inst
.size
== 0)
15183 to
= frag_more (inst
.size
);
15184 /* PR 9814: Record the thumb mode into the current frag so that we know
15185 what type of NOP padding to use, if necessary. We override any previous
15186 setting so that if the mode has changed then the NOPS that we use will
15187 match the encoding of the last instruction in the frag. */
15188 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15190 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15192 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15193 put_thumb32_insn (to
, inst
.instruction
);
15195 else if (inst
.size
> INSN_SIZE
)
15197 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15198 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15199 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15202 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15204 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15205 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15206 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15209 dwarf2_emit_insn (inst
.size
);
15213 output_it_inst (int cond
, int mask
, char * to
)
15215 unsigned long instruction
= 0xbf00;
15218 instruction
|= mask
;
15219 instruction
|= cond
<< 4;
15223 to
= frag_more (2);
15225 dwarf2_emit_insn (2);
15229 md_number_to_chars (to
, instruction
, 2);
15234 /* Tag values used in struct asm_opcode's tag field. */
15237 OT_unconditional
, /* Instruction cannot be conditionalized.
15238 The ARM condition field is still 0xE. */
15239 OT_unconditionalF
, /* Instruction cannot be conditionalized
15240 and carries 0xF in its ARM condition field. */
15241 OT_csuffix
, /* Instruction takes a conditional suffix. */
15242 OT_csuffixF
, /* Some forms of the instruction take a conditional
15243 suffix, others place 0xF where the condition field
15245 OT_cinfix3
, /* Instruction takes a conditional infix,
15246 beginning at character index 3. (In
15247 unified mode, it becomes a suffix.) */
15248 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15249 tsts, cmps, cmns, and teqs. */
15250 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15251 character index 3, even in unified mode. Used for
15252 legacy instructions where suffix and infix forms
15253 may be ambiguous. */
15254 OT_csuf_or_in3
, /* Instruction takes either a conditional
15255 suffix or an infix at character index 3. */
15256 OT_odd_infix_unc
, /* This is the unconditional variant of an
15257 instruction that takes a conditional infix
15258 at an unusual position. In unified mode,
15259 this variant will accept a suffix. */
15260 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15261 are the conditional variants of instructions that
15262 take conditional infixes in unusual positions.
15263 The infix appears at character index
15264 (tag - OT_odd_infix_0). These are not accepted
15265 in unified mode. */
15268 /* Subroutine of md_assemble, responsible for looking up the primary
15269 opcode from the mnemonic the user wrote. STR points to the
15270 beginning of the mnemonic.
15272 This is not simply a hash table lookup, because of conditional
15273 variants. Most instructions have conditional variants, which are
15274 expressed with a _conditional affix_ to the mnemonic. If we were
15275 to encode each conditional variant as a literal string in the opcode
15276 table, it would have approximately 20,000 entries.
15278 Most mnemonics take this affix as a suffix, and in unified syntax,
15279 'most' is upgraded to 'all'. However, in the divided syntax, some
15280 instructions take the affix as an infix, notably the s-variants of
15281 the arithmetic instructions. Of those instructions, all but six
15282 have the infix appear after the third character of the mnemonic.
15284 Accordingly, the algorithm for looking up primary opcodes given
15287 1. Look up the identifier in the opcode table.
15288 If we find a match, go to step U.
15290 2. Look up the last two characters of the identifier in the
15291 conditions table. If we find a match, look up the first N-2
15292 characters of the identifier in the opcode table. If we
15293 find a match, go to step CE.
15295 3. Look up the fourth and fifth characters of the identifier in
15296 the conditions table. If we find a match, extract those
15297 characters from the identifier, and look up the remaining
15298 characters in the opcode table. If we find a match, go
15303 U. Examine the tag field of the opcode structure, in case this is
15304 one of the six instructions with its conditional infix in an
15305 unusual place. If it is, the tag tells us where to find the
15306 infix; look it up in the conditions table and set inst.cond
15307 accordingly. Otherwise, this is an unconditional instruction.
15308 Again set inst.cond accordingly. Return the opcode structure.
15310 CE. Examine the tag field to make sure this is an instruction that
15311 should receive a conditional suffix. If it is not, fail.
15312 Otherwise, set inst.cond from the suffix we already looked up,
15313 and return the opcode structure.
15315 CM. Examine the tag field to make sure this is an instruction that
15316 should receive a conditional infix after the third character.
15317 If it is not, fail. Otherwise, undo the edits to the current
15318 line of input and proceed as for case CE. */
15320 static const struct asm_opcode
*
15321 opcode_lookup (char **str
)
15325 const struct asm_opcode
*opcode
;
15326 const struct asm_cond
*cond
;
15329 /* Scan up to the end of the mnemonic, which must end in white space,
15330 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15331 for (base
= end
= *str
; *end
!= '\0'; end
++)
15332 if (*end
== ' ' || *end
== '.')
15338 /* Handle a possible width suffix and/or Neon type suffix. */
15343 /* The .w and .n suffixes are only valid if the unified syntax is in
15345 if (unified_syntax
&& end
[1] == 'w')
15347 else if (unified_syntax
&& end
[1] == 'n')
15352 inst
.vectype
.elems
= 0;
15354 *str
= end
+ offset
;
15356 if (end
[offset
] == '.')
15358 /* See if we have a Neon type suffix (possible in either unified or
15359 non-unified ARM syntax mode). */
15360 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15363 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15369 /* Look for unaffixed or special-case affixed mnemonic. */
15370 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15375 if (opcode
->tag
< OT_odd_infix_0
)
15377 inst
.cond
= COND_ALWAYS
;
15381 if (warn_on_deprecated
&& unified_syntax
)
15382 as_warn (_("conditional infixes are deprecated in unified syntax"));
15383 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15384 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15387 inst
.cond
= cond
->value
;
15391 /* Cannot have a conditional suffix on a mnemonic of less than two
15393 if (end
- base
< 3)
15396 /* Look for suffixed mnemonic. */
15398 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15399 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15401 if (opcode
&& cond
)
15404 switch (opcode
->tag
)
15406 case OT_cinfix3_legacy
:
15407 /* Ignore conditional suffixes matched on infix only mnemonics. */
15411 case OT_cinfix3_deprecated
:
15412 case OT_odd_infix_unc
:
15413 if (!unified_syntax
)
15415 /* else fall through */
15419 case OT_csuf_or_in3
:
15420 inst
.cond
= cond
->value
;
15423 case OT_unconditional
:
15424 case OT_unconditionalF
:
15426 inst
.cond
= cond
->value
;
15429 /* Delayed diagnostic. */
15430 inst
.error
= BAD_COND
;
15431 inst
.cond
= COND_ALWAYS
;
15440 /* Cannot have a usual-position infix on a mnemonic of less than
15441 six characters (five would be a suffix). */
15442 if (end
- base
< 6)
15445 /* Look for infixed mnemonic in the usual position. */
15447 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15451 memcpy (save
, affix
, 2);
15452 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15453 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15455 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15456 memcpy (affix
, save
, 2);
15459 && (opcode
->tag
== OT_cinfix3
15460 || opcode
->tag
== OT_cinfix3_deprecated
15461 || opcode
->tag
== OT_csuf_or_in3
15462 || opcode
->tag
== OT_cinfix3_legacy
))
15465 if (warn_on_deprecated
&& unified_syntax
15466 && (opcode
->tag
== OT_cinfix3
15467 || opcode
->tag
== OT_cinfix3_deprecated
))
15468 as_warn (_("conditional infixes are deprecated in unified syntax"));
15470 inst
.cond
= cond
->value
;
15477 /* This function generates an initial IT instruction, leaving its block
15478 virtually open for the new instructions. Eventually,
15479 the mask will be updated by now_it_add_mask () each time
15480 a new instruction needs to be included in the IT block.
15481 Finally, the block is closed with close_automatic_it_block ().
15482 The block closure can be requested either from md_assemble (),
15483 a tencode (), or due to a label hook. */
15486 new_automatic_it_block (int cond
)
15488 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15489 now_it
.mask
= 0x18;
15491 now_it
.block_length
= 1;
15492 mapping_state (MAP_THUMB
);
15493 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15496 /* Close an automatic IT block.
15497 See comments in new_automatic_it_block (). */
15500 close_automatic_it_block (void)
15502 now_it
.mask
= 0x10;
15503 now_it
.block_length
= 0;
15506 /* Update the mask of the current automatically-generated IT
15507 instruction. See comments in new_automatic_it_block (). */
15510 now_it_add_mask (int cond
)
15512 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15513 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15514 | ((bitvalue) << (nbit)))
15515 const int resulting_bit
= (cond
& 1);
15517 now_it
.mask
&= 0xf;
15518 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15520 (5 - now_it
.block_length
));
15521 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15523 ((5 - now_it
.block_length
) - 1) );
15524 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15527 #undef SET_BIT_VALUE
15530 /* The IT blocks handling machinery is accessed through the these functions:
15531 it_fsm_pre_encode () from md_assemble ()
15532 set_it_insn_type () optional, from the tencode functions
15533 set_it_insn_type_last () ditto
15534 in_it_block () ditto
15535 it_fsm_post_encode () from md_assemble ()
15536 force_automatic_it_block_close () from label habdling functions
15539 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15540 initializing the IT insn type with a generic initial value depending
15541 on the inst.condition.
15542 2) During the tencode function, two things may happen:
15543 a) The tencode function overrides the IT insn type by
15544 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15545 b) The tencode function queries the IT block state by
15546 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15548 Both set_it_insn_type and in_it_block run the internal FSM state
15549 handling function (handle_it_state), because: a) setting the IT insn
15550 type may incur in an invalid state (exiting the function),
15551 and b) querying the state requires the FSM to be updated.
15552 Specifically we want to avoid creating an IT block for conditional
15553 branches, so it_fsm_pre_encode is actually a guess and we can't
15554 determine whether an IT block is required until the tencode () routine
15555 has decided what type of instruction this actually it.
15556 Because of this, if set_it_insn_type and in_it_block have to be used,
15557 set_it_insn_type has to be called first.
15559 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15560 determines the insn IT type depending on the inst.cond code.
15561 When a tencode () routine encodes an instruction that can be
15562 either outside an IT block, or, in the case of being inside, has to be
15563 the last one, set_it_insn_type_last () will determine the proper
15564 IT instruction type based on the inst.cond code. Otherwise,
15565 set_it_insn_type can be called for overriding that logic or
15566 for covering other cases.
15568 Calling handle_it_state () may not transition the IT block state to
15569 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15570 still queried. Instead, if the FSM determines that the state should
15571 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15572 after the tencode () function: that's what it_fsm_post_encode () does.
15574 Since in_it_block () calls the state handling function to get an
15575 updated state, an error may occur (due to invalid insns combination).
15576 In that case, inst.error is set.
15577 Therefore, inst.error has to be checked after the execution of
15578 the tencode () routine.
15580 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15581 any pending state change (if any) that didn't take place in
15582 handle_it_state () as explained above. */
15585 it_fsm_pre_encode (void)
15587 if (inst
.cond
!= COND_ALWAYS
)
15588 inst
.it_insn_type
= INSIDE_IT_INSN
;
15590 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15592 now_it
.state_handled
= 0;
15595 /* IT state FSM handling function. */
15598 handle_it_state (void)
15600 now_it
.state_handled
= 1;
15602 switch (now_it
.state
)
15604 case OUTSIDE_IT_BLOCK
:
15605 switch (inst
.it_insn_type
)
15607 case OUTSIDE_IT_INSN
:
15610 case INSIDE_IT_INSN
:
15611 case INSIDE_IT_LAST_INSN
:
15612 if (thumb_mode
== 0)
15615 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15616 as_tsktsk (_("Warning: conditional outside an IT block"\
15621 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15622 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15624 /* Automatically generate the IT instruction. */
15625 new_automatic_it_block (inst
.cond
);
15626 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15627 close_automatic_it_block ();
15631 inst
.error
= BAD_OUT_IT
;
15637 case IF_INSIDE_IT_LAST_INSN
:
15638 case NEUTRAL_IT_INSN
:
15642 now_it
.state
= MANUAL_IT_BLOCK
;
15643 now_it
.block_length
= 0;
15648 case AUTOMATIC_IT_BLOCK
:
15649 /* Three things may happen now:
15650 a) We should increment current it block size;
15651 b) We should close current it block (closing insn or 4 insns);
15652 c) We should close current it block and start a new one (due
15653 to incompatible conditions or
15654 4 insns-length block reached). */
15656 switch (inst
.it_insn_type
)
15658 case OUTSIDE_IT_INSN
:
15659 /* The closure of the block shall happen immediatelly,
15660 so any in_it_block () call reports the block as closed. */
15661 force_automatic_it_block_close ();
15664 case INSIDE_IT_INSN
:
15665 case INSIDE_IT_LAST_INSN
:
15666 case IF_INSIDE_IT_LAST_INSN
:
15667 now_it
.block_length
++;
15669 if (now_it
.block_length
> 4
15670 || !now_it_compatible (inst
.cond
))
15672 force_automatic_it_block_close ();
15673 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15674 new_automatic_it_block (inst
.cond
);
15678 now_it_add_mask (inst
.cond
);
15681 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15682 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15683 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15684 close_automatic_it_block ();
15687 case NEUTRAL_IT_INSN
:
15688 now_it
.block_length
++;
15690 if (now_it
.block_length
> 4)
15691 force_automatic_it_block_close ();
15693 now_it_add_mask (now_it
.cc
& 1);
15697 close_automatic_it_block ();
15698 now_it
.state
= MANUAL_IT_BLOCK
;
15703 case MANUAL_IT_BLOCK
:
15705 /* Check conditional suffixes. */
15706 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15709 now_it
.mask
&= 0x1f;
15710 is_last
= (now_it
.mask
== 0x10);
15712 switch (inst
.it_insn_type
)
15714 case OUTSIDE_IT_INSN
:
15715 inst
.error
= BAD_NOT_IT
;
15718 case INSIDE_IT_INSN
:
15719 if (cond
!= inst
.cond
)
15721 inst
.error
= BAD_IT_COND
;
15726 case INSIDE_IT_LAST_INSN
:
15727 case IF_INSIDE_IT_LAST_INSN
:
15728 if (cond
!= inst
.cond
)
15730 inst
.error
= BAD_IT_COND
;
15735 inst
.error
= BAD_BRANCH
;
15740 case NEUTRAL_IT_INSN
:
15741 /* The BKPT instruction is unconditional even in an IT block. */
15745 inst
.error
= BAD_IT_IT
;
15756 it_fsm_post_encode (void)
15760 if (!now_it
.state_handled
)
15761 handle_it_state ();
15763 is_last
= (now_it
.mask
== 0x10);
15766 now_it
.state
= OUTSIDE_IT_BLOCK
;
15772 force_automatic_it_block_close (void)
15774 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15776 close_automatic_it_block ();
15777 now_it
.state
= OUTSIDE_IT_BLOCK
;
15785 if (!now_it
.state_handled
)
15786 handle_it_state ();
15788 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15792 md_assemble (char *str
)
15795 const struct asm_opcode
* opcode
;
15797 /* Align the previous label if needed. */
15798 if (last_label_seen
!= NULL
)
15800 symbol_set_frag (last_label_seen
, frag_now
);
15801 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15802 S_SET_SEGMENT (last_label_seen
, now_seg
);
15805 memset (&inst
, '\0', sizeof (inst
));
15806 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15808 opcode
= opcode_lookup (&p
);
15811 /* It wasn't an instruction, but it might be a register alias of
15812 the form alias .req reg, or a Neon .dn/.qn directive. */
15813 if (! create_register_alias (str
, p
)
15814 && ! create_neon_reg_alias (str
, p
))
15815 as_bad (_("bad instruction `%s'"), str
);
15820 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15821 as_warn (_("s suffix on comparison instruction is deprecated"));
15823 /* The value which unconditional instructions should have in place of the
15824 condition field. */
15825 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15829 arm_feature_set variant
;
15831 variant
= cpu_variant
;
15832 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15833 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15834 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15835 /* Check that this instruction is supported for this CPU. */
15836 if (!opcode
->tvariant
15837 || (thumb_mode
== 1
15838 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15840 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15843 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15844 && opcode
->tencode
!= do_t_branch
)
15846 as_bad (_("Thumb does not support conditional execution"));
15850 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15852 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15853 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15854 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15856 /* Two things are addressed here.
15857 1) Implicit require narrow instructions on Thumb-1.
15858 This avoids relaxation accidentally introducing Thumb-2
15860 2) Reject wide instructions in non Thumb-2 cores. */
15861 if (inst
.size_req
== 0)
15863 else if (inst
.size_req
== 4)
15865 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
15871 inst
.instruction
= opcode
->tvalue
;
15873 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15875 /* Prepare the it_insn_type for those encodings that don't set
15877 it_fsm_pre_encode ();
15879 opcode
->tencode ();
15881 it_fsm_post_encode ();
15884 if (!(inst
.error
|| inst
.relax
))
15886 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15887 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15888 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15890 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15895 /* Something has gone badly wrong if we try to relax a fixed size
15897 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15899 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15900 *opcode
->tvariant
);
15901 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15902 set those bits when Thumb-2 32-bit instructions are seen. ie.
15903 anything other than bl/blx and v6-M instructions.
15904 This is overly pessimistic for relaxable instructions. */
15905 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15907 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15908 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15909 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15912 check_neon_suffixes
;
15916 mapping_state (MAP_THUMB
);
15919 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15923 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15924 is_bx
= (opcode
->aencode
== do_bx
);
15926 /* Check that this instruction is supported for this CPU. */
15927 if (!(is_bx
&& fix_v4bx
)
15928 && !(opcode
->avariant
&&
15929 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15931 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
15936 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15940 inst
.instruction
= opcode
->avalue
;
15941 if (opcode
->tag
== OT_unconditionalF
)
15942 inst
.instruction
|= 0xF << 28;
15944 inst
.instruction
|= inst
.cond
<< 28;
15945 inst
.size
= INSN_SIZE
;
15946 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
15948 it_fsm_pre_encode ();
15949 opcode
->aencode ();
15950 it_fsm_post_encode ();
15952 /* Arm mode bx is marked as both v4T and v5 because it's still required
15953 on a hypothetical non-thumb v5 core. */
15955 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15957 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15958 *opcode
->avariant
);
15960 check_neon_suffixes
;
15964 mapping_state (MAP_ARM
);
15969 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15977 check_it_blocks_finished (void)
15982 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15983 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15984 == MANUAL_IT_BLOCK
)
15986 as_warn (_("section '%s' finished with an open IT block."),
15990 if (now_it
.state
== MANUAL_IT_BLOCK
)
15991 as_warn (_("file finished with an open IT block."));
15995 /* Various frobbings of labels and their addresses. */
15998 arm_start_line_hook (void)
16000 last_label_seen
= NULL
;
16004 arm_frob_label (symbolS
* sym
)
16006 last_label_seen
= sym
;
16008 ARM_SET_THUMB (sym
, thumb_mode
);
16010 #if defined OBJ_COFF || defined OBJ_ELF
16011 ARM_SET_INTERWORK (sym
, support_interwork
);
16014 force_automatic_it_block_close ();
16016 /* Note - do not allow local symbols (.Lxxx) to be labelled
16017 as Thumb functions. This is because these labels, whilst
16018 they exist inside Thumb code, are not the entry points for
16019 possible ARM->Thumb calls. Also, these labels can be used
16020 as part of a computed goto or switch statement. eg gcc
16021 can generate code that looks like this:
16023 ldr r2, [pc, .Laaa]
16033 The first instruction loads the address of the jump table.
16034 The second instruction converts a table index into a byte offset.
16035 The third instruction gets the jump address out of the table.
16036 The fourth instruction performs the jump.
16038 If the address stored at .Laaa is that of a symbol which has the
16039 Thumb_Func bit set, then the linker will arrange for this address
16040 to have the bottom bit set, which in turn would mean that the
16041 address computation performed by the third instruction would end
16042 up with the bottom bit set. Since the ARM is capable of unaligned
16043 word loads, the instruction would then load the incorrect address
16044 out of the jump table, and chaos would ensue. */
16045 if (label_is_thumb_function_name
16046 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16047 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16049 /* When the address of a Thumb function is taken the bottom
16050 bit of that address should be set. This will allow
16051 interworking between Arm and Thumb functions to work
16054 THUMB_SET_FUNC (sym
, 1);
16056 label_is_thumb_function_name
= FALSE
;
16059 dwarf2_emit_label (sym
);
16063 arm_data_in_code (void)
16065 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16067 *input_line_pointer
= '/';
16068 input_line_pointer
+= 5;
16069 *input_line_pointer
= 0;
16077 arm_canonicalize_symbol_name (char * name
)
16081 if (thumb_mode
&& (len
= strlen (name
)) > 5
16082 && streq (name
+ len
- 5, "/data"))
16083 *(name
+ len
- 5) = 0;
16088 /* Table of all register names defined by default. The user can
16089 define additional names with .req. Note that all register names
16090 should appear in both upper and lowercase variants. Some registers
16091 also have mixed-case names. */
16093 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16094 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16095 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16096 #define REGSET(p,t) \
16097 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16098 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16099 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16100 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16101 #define REGSETH(p,t) \
16102 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16103 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16104 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16105 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16106 #define REGSET2(p,t) \
16107 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16108 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16109 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16110 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16112 static const struct reg_entry reg_names
[] =
16114 /* ARM integer registers. */
16115 REGSET(r
, RN
), REGSET(R
, RN
),
16117 /* ATPCS synonyms. */
16118 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16119 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16120 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16122 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16123 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16124 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16126 /* Well-known aliases. */
16127 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16128 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16130 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16131 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16133 /* Coprocessor numbers. */
16134 REGSET(p
, CP
), REGSET(P
, CP
),
16136 /* Coprocessor register numbers. The "cr" variants are for backward
16138 REGSET(c
, CN
), REGSET(C
, CN
),
16139 REGSET(cr
, CN
), REGSET(CR
, CN
),
16141 /* FPA registers. */
16142 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16143 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16145 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16146 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16148 /* VFP SP registers. */
16149 REGSET(s
,VFS
), REGSET(S
,VFS
),
16150 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16152 /* VFP DP Registers. */
16153 REGSET(d
,VFD
), REGSET(D
,VFD
),
16154 /* Extra Neon DP registers. */
16155 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16157 /* Neon QP registers. */
16158 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16160 /* VFP control registers. */
16161 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16162 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16163 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16164 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16165 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16166 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16168 /* Maverick DSP coprocessor registers. */
16169 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16170 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16172 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16173 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16174 REGDEF(dspsc
,0,DSPSC
),
16176 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16177 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16178 REGDEF(DSPSC
,0,DSPSC
),
16180 /* iWMMXt data registers - p0, c0-15. */
16181 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16183 /* iWMMXt control registers - p1, c0-3. */
16184 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16185 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16186 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16187 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16189 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16190 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16191 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16192 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16193 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16195 /* XScale accumulator registers. */
16196 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16202 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16203 within psr_required_here. */
16204 static const struct asm_psr psrs
[] =
16206 /* Backward compatibility notation. Note that "all" is no longer
16207 truly all possible PSR bits. */
16208 {"all", PSR_c
| PSR_f
},
16212 /* Individual flags. */
16217 /* Combinations of flags. */
16218 {"fs", PSR_f
| PSR_s
},
16219 {"fx", PSR_f
| PSR_x
},
16220 {"fc", PSR_f
| PSR_c
},
16221 {"sf", PSR_s
| PSR_f
},
16222 {"sx", PSR_s
| PSR_x
},
16223 {"sc", PSR_s
| PSR_c
},
16224 {"xf", PSR_x
| PSR_f
},
16225 {"xs", PSR_x
| PSR_s
},
16226 {"xc", PSR_x
| PSR_c
},
16227 {"cf", PSR_c
| PSR_f
},
16228 {"cs", PSR_c
| PSR_s
},
16229 {"cx", PSR_c
| PSR_x
},
16230 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16231 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16232 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16233 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16234 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16235 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16236 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16237 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16238 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16239 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16240 {"scf", PSR_s
| PSR_c
| PSR_f
},
16241 {"scx", PSR_s
| PSR_c
| PSR_x
},
16242 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16243 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16244 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16245 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16246 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16247 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16248 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16249 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16250 {"csf", PSR_c
| PSR_s
| PSR_f
},
16251 {"csx", PSR_c
| PSR_s
| PSR_x
},
16252 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16253 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16254 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16255 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16256 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16257 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16258 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16259 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16260 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16261 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16262 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16263 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16264 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16265 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16266 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16267 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16268 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16269 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16270 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16271 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16272 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16273 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16274 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16275 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16276 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16277 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16280 /* Table of V7M psr names. */
16281 static const struct asm_psr v7m_psrs
[] =
16283 {"apsr", 0 }, {"APSR", 0 },
16284 {"iapsr", 1 }, {"IAPSR", 1 },
16285 {"eapsr", 2 }, {"EAPSR", 2 },
16286 {"psr", 3 }, {"PSR", 3 },
16287 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16288 {"ipsr", 5 }, {"IPSR", 5 },
16289 {"epsr", 6 }, {"EPSR", 6 },
16290 {"iepsr", 7 }, {"IEPSR", 7 },
16291 {"msp", 8 }, {"MSP", 8 },
16292 {"psp", 9 }, {"PSP", 9 },
16293 {"primask", 16}, {"PRIMASK", 16},
16294 {"basepri", 17}, {"BASEPRI", 17},
16295 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16296 {"faultmask", 19}, {"FAULTMASK", 19},
16297 {"control", 20}, {"CONTROL", 20}
16300 /* Table of all shift-in-operand names. */
16301 static const struct asm_shift_name shift_names
[] =
16303 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16304 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16305 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16306 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16307 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16308 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16311 /* Table of all explicit relocation names. */
16313 static struct reloc_entry reloc_names
[] =
16315 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16316 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16317 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16318 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16319 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16320 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16321 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16322 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16323 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16324 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16325 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16326 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16330 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16331 static const struct asm_cond conds
[] =
16335 {"cs", 0x2}, {"hs", 0x2},
16336 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16350 static struct asm_barrier_opt barrier_opt_names
[] =
16352 { "sy", 0xf }, { "SY", 0xf },
16353 { "un", 0x7 }, { "UN", 0x7 },
16354 { "st", 0xe }, { "ST", 0xe },
16355 { "unst", 0x6 }, { "UNST", 0x6 },
16356 { "ish", 0xb }, { "ISH", 0xb },
16357 { "sh", 0xb }, { "SH", 0xb },
16358 { "ishst", 0xa }, { "ISHST", 0xa },
16359 { "shst", 0xa }, { "SHST", 0xa },
16360 { "nsh", 0x7 }, { "NSH", 0x7 },
16361 { "nshst", 0x6 }, { "NSHST", 0x6 },
16362 { "osh", 0x3 }, { "OSH", 0x3 },
16363 { "oshst", 0x2 }, { "OSHST", 0x2 }
16366 /* Table of ARM-format instructions. */
16368 /* Macros for gluing together operand strings. N.B. In all cases
16369 other than OPS0, the trailing OP_stop comes from default
16370 zero-initialization of the unspecified elements of the array. */
16371 #define OPS0() { OP_stop, }
16372 #define OPS1(a) { OP_##a, }
16373 #define OPS2(a,b) { OP_##a,OP_##b, }
16374 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16375 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16376 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16377 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16379 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16380 This is useful when mixing operands for ARM and THUMB, i.e. using the
16381 MIX_ARM_THUMB_OPERANDS macro.
16382 In order to use these macros, prefix the number of operands with _
16384 #define OPS_1(a) { a, }
16385 #define OPS_2(a,b) { a,b, }
16386 #define OPS_3(a,b,c) { a,b,c, }
16387 #define OPS_4(a,b,c,d) { a,b,c,d, }
16388 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16389 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16391 /* These macros abstract out the exact format of the mnemonic table and
16392 save some repeated characters. */
16394 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16395 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16396 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16397 THUMB_VARIANT, do_##ae, do_##te }
16399 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16400 a T_MNEM_xyz enumerator. */
16401 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16402 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16403 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16404 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16406 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16407 infix after the third character. */
16408 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16409 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16410 THUMB_VARIANT, do_##ae, do_##te }
16411 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16412 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16413 THUMB_VARIANT, do_##ae, do_##te }
16414 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16415 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16416 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16417 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16418 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16419 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16420 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16421 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16423 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16424 appear in the condition table. */
16425 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16426 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16427 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16429 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16430 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16431 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16432 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16433 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16434 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16435 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16436 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16437 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16438 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16439 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16440 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16441 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16442 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16443 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16444 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16445 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16446 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16447 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16448 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16450 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16451 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16452 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16453 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16455 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16456 field is still 0xE. Many of the Thumb variants can be executed
16457 conditionally, so this is checked separately. */
16458 #define TUE(mnem, op, top, nops, ops, ae, te) \
16459 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16460 THUMB_VARIANT, do_##ae, do_##te }
16462 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16463 condition code field. */
16464 #define TUF(mnem, op, top, nops, ops, ae, te) \
16465 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16466 THUMB_VARIANT, do_##ae, do_##te }
16468 /* ARM-only variants of all the above. */
16469 #define CE(mnem, op, nops, ops, ae) \
16470 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16472 #define C3(mnem, op, nops, ops, ae) \
16473 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16475 /* Legacy mnemonics that always have conditional infix after the third
16477 #define CL(mnem, op, nops, ops, ae) \
16478 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16479 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16481 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16482 #define cCE(mnem, op, nops, ops, ae) \
16483 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16485 /* Legacy coprocessor instructions where conditional infix and conditional
16486 suffix are ambiguous. For consistency this includes all FPA instructions,
16487 not just the potentially ambiguous ones. */
16488 #define cCL(mnem, op, nops, ops, ae) \
16489 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16490 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16492 /* Coprocessor, takes either a suffix or a position-3 infix
16493 (for an FPA corner case). */
16494 #define C3E(mnem, op, nops, ops, ae) \
16495 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16496 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16498 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16499 { m1 #m2 m3, OPS##nops ops, \
16500 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16501 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16503 #define CM(m1, m2, op, nops, ops, ae) \
16504 xCM_ (m1, , m2, op, nops, ops, ae), \
16505 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16506 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16507 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16508 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16509 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16510 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16511 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16512 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16513 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16514 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16515 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16516 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16517 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16518 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16519 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16520 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16521 xCM_ (m1, le, m2, op, nops, ops, ae), \
16522 xCM_ (m1, al, m2, op, nops, ops, ae)
16524 #define UE(mnem, op, nops, ops, ae) \
16525 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16527 #define UF(mnem, op, nops, ops, ae) \
16528 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16530 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16531 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16532 use the same encoding function for each. */
16533 #define NUF(mnem, op, nops, ops, enc) \
16534 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16535 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16537 /* Neon data processing, version which indirects through neon_enc_tab for
16538 the various overloaded versions of opcodes. */
16539 #define nUF(mnem, op, nops, ops, enc) \
16540 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16541 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16543 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16545 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16546 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16547 THUMB_VARIANT, do_##enc, do_##enc }
16549 #define NCE(mnem, op, nops, ops, enc) \
16550 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16552 #define NCEF(mnem, op, nops, ops, enc) \
16553 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16555 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16556 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16557 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16558 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16560 #define nCE(mnem, op, nops, ops, enc) \
16561 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16563 #define nCEF(mnem, op, nops, ops, enc) \
16564 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16568 static const struct asm_opcode insns
[] =
16570 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16571 #define THUMB_VARIANT &arm_ext_v4t
16572 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16573 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16574 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16575 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16576 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16577 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16578 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16579 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16580 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16581 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16582 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16583 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16584 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16585 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16586 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16587 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16589 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16590 for setting PSR flag bits. They are obsolete in V6 and do not
16591 have Thumb equivalents. */
16592 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16593 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16594 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16595 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16596 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16597 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16598 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16599 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16600 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16602 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16603 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16604 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16605 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16607 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16608 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16609 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16611 OP_ADDRGLDR
),ldst
, t_ldst
),
16612 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16614 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16615 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16616 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16617 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16618 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16619 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16621 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16622 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16623 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16624 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16627 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16628 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16629 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16631 /* Thumb-compatibility pseudo ops. */
16632 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16633 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16634 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16635 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16636 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16637 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16638 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16639 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16640 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16641 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16642 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16643 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16645 /* These may simplify to neg. */
16646 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16647 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16649 #undef THUMB_VARIANT
16650 #define THUMB_VARIANT & arm_ext_v6
16652 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16654 /* V1 instructions with no Thumb analogue prior to V6T2. */
16655 #undef THUMB_VARIANT
16656 #define THUMB_VARIANT & arm_ext_v6t2
16658 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16659 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16660 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16662 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16663 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16664 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16665 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16667 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16668 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16670 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16671 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16673 /* V1 instructions with no Thumb analogue at all. */
16674 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16675 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16677 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16678 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16679 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16680 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16681 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16682 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16683 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16684 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16687 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16688 #undef THUMB_VARIANT
16689 #define THUMB_VARIANT & arm_ext_v4t
16691 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16692 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16694 #undef THUMB_VARIANT
16695 #define THUMB_VARIANT & arm_ext_v6t2
16697 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16698 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16700 /* Generic coprocessor instructions. */
16701 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16702 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16703 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16704 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16705 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16706 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16707 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16710 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16712 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16713 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16716 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16717 #undef THUMB_VARIANT
16718 #define THUMB_VARIANT & arm_ext_msr
16720 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16721 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16724 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16725 #undef THUMB_VARIANT
16726 #define THUMB_VARIANT & arm_ext_v6t2
16728 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16729 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16730 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16731 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16732 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16733 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16734 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16735 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16738 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16739 #undef THUMB_VARIANT
16740 #define THUMB_VARIANT & arm_ext_v4t
16742 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16743 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16744 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16745 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16746 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16747 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16750 #define ARM_VARIANT & arm_ext_v4t_5
16752 /* ARM Architecture 4T. */
16753 /* Note: bx (and blx) are required on V5, even if the processor does
16754 not support Thumb. */
16755 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16758 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16759 #undef THUMB_VARIANT
16760 #define THUMB_VARIANT & arm_ext_v5t
16762 /* Note: blx has 2 variants; the .value coded here is for
16763 BLX(2). Only this variant has conditional execution. */
16764 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16765 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16767 #undef THUMB_VARIANT
16768 #define THUMB_VARIANT & arm_ext_v6t2
16770 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16771 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16772 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16773 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16774 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16775 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16776 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16777 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16780 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16781 #undef THUMB_VARIANT
16782 #define THUMB_VARIANT &arm_ext_v5exp
16784 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16785 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16786 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16787 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16789 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16790 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16792 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16793 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16794 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16795 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16797 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16798 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16799 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16800 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16802 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16803 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16805 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16806 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16807 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16808 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16811 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16812 #undef THUMB_VARIANT
16813 #define THUMB_VARIANT &arm_ext_v6t2
16815 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16816 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16818 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16819 ADDRGLDRS
), ldrd
, t_ldstd
),
16821 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16822 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16825 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16827 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16830 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16831 #undef THUMB_VARIANT
16832 #define THUMB_VARIANT & arm_ext_v6
16834 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16835 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16836 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16837 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16838 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16839 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16840 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16841 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16842 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16843 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16845 #undef THUMB_VARIANT
16846 #define THUMB_VARIANT & arm_ext_v6t2
16848 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16849 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16851 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16852 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16854 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16855 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16857 /* ARM V6 not included in V7M. */
16858 #undef THUMB_VARIANT
16859 #define THUMB_VARIANT & arm_ext_v6_notm
16860 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16861 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16862 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16863 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16864 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16865 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16866 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16867 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16868 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16869 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16870 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16871 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16873 /* ARM V6 not included in V7M (eg. integer SIMD). */
16874 #undef THUMB_VARIANT
16875 #define THUMB_VARIANT & arm_ext_v6_dsp
16876 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16877 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16878 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16879 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16880 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16881 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16882 /* Old name for QASX. */
16883 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16884 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16885 /* Old name for QSAX. */
16886 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16887 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16888 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16889 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16890 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16891 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16892 /* Old name for SASX. */
16893 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16894 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16895 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16896 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16897 /* Old name for SHASX. */
16898 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16899 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16900 /* Old name for SHSAX. */
16901 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16902 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16903 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16904 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16905 /* Old name for SSAX. */
16906 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16907 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16908 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16909 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16910 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16911 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16912 /* Old name for UASX. */
16913 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16914 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16915 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16916 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16917 /* Old name for UHASX. */
16918 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16919 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16920 /* Old name for UHSAX. */
16921 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16922 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16923 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16924 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16925 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16926 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16927 /* Old name for UQASX. */
16928 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16929 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16930 /* Old name for UQSAX. */
16931 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16932 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16933 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16934 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16935 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16936 /* Old name for USAX. */
16937 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16938 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16939 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16940 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16941 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16942 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16943 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16944 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16945 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16946 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16947 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16948 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16949 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16950 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16951 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16952 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16953 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16954 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16955 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16956 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16957 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16958 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16959 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16960 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16961 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16962 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16963 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16964 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16965 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16966 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16967 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16968 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16969 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16970 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16973 #define ARM_VARIANT & arm_ext_v6k
16974 #undef THUMB_VARIANT
16975 #define THUMB_VARIANT & arm_ext_v6k
16977 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16978 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16979 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16980 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16982 #undef THUMB_VARIANT
16983 #define THUMB_VARIANT & arm_ext_v6_notm
16984 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
16986 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
16987 RRnpcb
), strexd
, t_strexd
),
16989 #undef THUMB_VARIANT
16990 #define THUMB_VARIANT & arm_ext_v6t2
16991 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
16993 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
16995 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16997 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16999 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17002 #define ARM_VARIANT & arm_ext_v6z
17004 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17007 #define ARM_VARIANT & arm_ext_v6t2
17009 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17010 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17011 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17012 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17014 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17015 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17016 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17017 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17019 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17020 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17021 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17022 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17024 /* Thumb-only instructions. */
17026 #define ARM_VARIANT NULL
17027 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17028 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17030 /* ARM does not really have an IT instruction, so always allow it.
17031 The opcode is copied from Thumb in order to allow warnings in
17032 -mimplicit-it=[never | arm] modes. */
17034 #define ARM_VARIANT & arm_ext_v1
17036 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17037 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17038 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17039 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17040 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17041 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17042 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17043 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17044 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17045 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17046 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17047 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17048 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17049 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17050 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17051 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17052 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17053 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17055 /* Thumb2 only instructions. */
17057 #define ARM_VARIANT NULL
17059 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17060 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17061 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17062 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17063 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17064 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17066 /* Thumb-2 hardware division instructions (R and M profiles only). */
17067 #undef THUMB_VARIANT
17068 #define THUMB_VARIANT & arm_ext_div
17070 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17071 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17073 /* ARM V6M/V7 instructions. */
17075 #define ARM_VARIANT & arm_ext_barrier
17076 #undef THUMB_VARIANT
17077 #define THUMB_VARIANT & arm_ext_barrier
17079 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17080 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17081 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17083 /* ARM V7 instructions. */
17085 #define ARM_VARIANT & arm_ext_v7
17086 #undef THUMB_VARIANT
17087 #define THUMB_VARIANT & arm_ext_v7
17089 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17090 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17093 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17095 cCE("wfs", e200110
, 1, (RR
), rd
),
17096 cCE("rfs", e300110
, 1, (RR
), rd
),
17097 cCE("wfc", e400110
, 1, (RR
), rd
),
17098 cCE("rfc", e500110
, 1, (RR
), rd
),
17100 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17101 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17102 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17103 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17105 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17106 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17107 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17108 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17110 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17111 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17112 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17113 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17114 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17115 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17116 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17117 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17118 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17119 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17120 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17121 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17123 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17124 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17125 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17126 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17127 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17128 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17129 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17130 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17131 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17132 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17133 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17134 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17136 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17137 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17138 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17139 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17140 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17141 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17142 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17143 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17144 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17145 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17146 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17147 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17149 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17150 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17151 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17152 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17153 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17154 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17155 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17156 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17157 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17158 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17159 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17160 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17162 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17163 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17164 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17165 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17166 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17167 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17168 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17169 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17170 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17171 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17172 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17173 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17175 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17176 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17177 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17178 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17179 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17180 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17181 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17182 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17183 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17184 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17185 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17186 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17188 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17189 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17190 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17191 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17192 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17193 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17194 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17195 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17196 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17197 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17198 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17199 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17201 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17202 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17203 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17204 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17205 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17206 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17207 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17208 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17209 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17210 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17211 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17212 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17214 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17215 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17216 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17217 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17218 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17219 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17220 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17221 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17222 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17223 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17224 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17225 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17227 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17228 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17229 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17230 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17231 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17232 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17233 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17234 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17235 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17236 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17237 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17238 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17240 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17241 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17242 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17243 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17244 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17245 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17246 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17247 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17248 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17249 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17250 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17251 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17253 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17254 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17255 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17256 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17257 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17258 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17259 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17260 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17261 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17262 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17263 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17264 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17266 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17267 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17268 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17269 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17270 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17271 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17272 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17273 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17274 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17275 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17276 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17277 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17279 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17280 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17281 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17282 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17283 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17284 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17285 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17286 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17287 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17288 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17289 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17290 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17292 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17293 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17294 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17295 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17296 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17297 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17298 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17299 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17300 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17301 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17302 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17303 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17305 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17306 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17307 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17308 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17309 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17310 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17311 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17312 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17313 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17314 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17315 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17316 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17318 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17319 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17320 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17321 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17322 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17323 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17324 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17325 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17326 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17327 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17328 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17329 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17331 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17332 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17333 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17334 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17335 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17336 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17337 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17338 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17339 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17340 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17341 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17342 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17344 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17345 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17346 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17347 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17348 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17349 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17350 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17351 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17352 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17353 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17354 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17355 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17357 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17358 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17359 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17360 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17361 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17362 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17363 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17364 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17365 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17366 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17367 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17368 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17370 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17371 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17372 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17373 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17374 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17375 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17376 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17377 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17378 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17379 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17380 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17381 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17383 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17384 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17385 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17386 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17387 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17388 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17389 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17390 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17391 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17392 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17393 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17394 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17396 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17397 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17398 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17399 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17400 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17401 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17402 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17403 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17404 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17405 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17406 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17407 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17409 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17410 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17411 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17412 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17413 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17414 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17415 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17416 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17417 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17418 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17419 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17420 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17422 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17423 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17424 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17425 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17426 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17427 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17428 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17429 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17430 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17431 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17432 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17433 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17435 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17436 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17437 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17438 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17439 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17440 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17441 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17442 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17443 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17444 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17445 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17446 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17448 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17449 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17450 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17451 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17452 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17453 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17454 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17455 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17456 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17457 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17458 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17459 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17461 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17462 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17463 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17464 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17465 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17466 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17467 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17468 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17469 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17470 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17471 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17472 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17474 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17475 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17476 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17477 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17478 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17479 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17480 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17481 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17482 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17483 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17484 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17485 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17487 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17488 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17489 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17490 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17492 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17493 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17494 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17495 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17496 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17497 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17498 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17499 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17500 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17501 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17502 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17503 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17505 /* The implementation of the FIX instruction is broken on some
17506 assemblers, in that it accepts a precision specifier as well as a
17507 rounding specifier, despite the fact that this is meaningless.
17508 To be more compatible, we accept it as well, though of course it
17509 does not set any bits. */
17510 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17511 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17512 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17513 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17514 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17515 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17516 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17517 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17518 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17519 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17520 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17521 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17522 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17524 /* Instructions that were new with the real FPA, call them V2. */
17526 #define ARM_VARIANT & fpu_fpa_ext_v2
17528 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17529 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17530 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17531 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17532 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17533 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17536 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17538 /* Moves and type conversions. */
17539 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17540 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17541 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17542 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17543 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17544 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17545 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17546 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17547 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17548 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17549 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17550 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17551 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17552 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17554 /* Memory operations. */
17555 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17556 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17557 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17558 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17559 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17560 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17561 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17562 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17563 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17564 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17565 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17566 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17567 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17568 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17569 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17570 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17571 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17572 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17574 /* Monadic operations. */
17575 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17576 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17577 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17579 /* Dyadic operations. */
17580 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17581 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17582 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17583 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17584 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17585 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17586 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17587 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17588 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17591 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17592 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17593 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17594 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17596 /* Double precision load/store are still present on single precision
17597 implementations. */
17598 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17599 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17600 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17601 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17602 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17603 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17604 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17605 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17606 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17607 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17610 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17612 /* Moves and type conversions. */
17613 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17614 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17615 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17616 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17617 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17618 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17619 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17620 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17621 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17622 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17623 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17624 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17625 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17627 /* Monadic operations. */
17628 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17629 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17630 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17632 /* Dyadic operations. */
17633 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17634 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17635 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17636 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17637 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17638 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17639 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17640 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17641 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17644 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17645 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17646 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17647 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17650 #define ARM_VARIANT & fpu_vfp_ext_v2
17652 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17653 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17654 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17655 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17657 /* Instructions which may belong to either the Neon or VFP instruction sets.
17658 Individual encoder functions perform additional architecture checks. */
17660 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17661 #undef THUMB_VARIANT
17662 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17664 /* These mnemonics are unique to VFP. */
17665 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17666 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17667 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17668 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17669 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17670 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17671 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17672 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17673 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17674 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17676 /* Mnemonics shared by Neon and VFP. */
17677 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17678 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17679 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17681 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17682 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17684 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17685 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17687 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17688 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17689 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17690 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17691 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17692 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17693 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17694 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17696 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17697 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17698 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17699 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17702 /* NOTE: All VMOV encoding is special-cased! */
17703 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17704 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17706 #undef THUMB_VARIANT
17707 #define THUMB_VARIANT & fpu_neon_ext_v1
17709 #define ARM_VARIANT & fpu_neon_ext_v1
17711 /* Data processing with three registers of the same length. */
17712 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17713 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17714 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17715 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17716 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17717 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17718 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17719 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17720 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17721 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17722 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17723 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17724 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17725 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17726 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17727 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17728 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17729 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17730 /* If not immediate, fall back to neon_dyadic_i64_su.
17731 shl_imm should accept I8 I16 I32 I64,
17732 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17733 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17734 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17735 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17736 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17737 /* Logic ops, types optional & ignored. */
17738 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17739 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17740 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17741 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17742 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17743 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17744 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17745 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17746 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17747 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17748 /* Bitfield ops, untyped. */
17749 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17750 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17751 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17752 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17753 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17754 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17755 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17756 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17757 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17758 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17759 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17760 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17761 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17762 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17763 back to neon_dyadic_if_su. */
17764 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17765 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17766 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17767 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17768 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17769 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17770 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17771 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17772 /* Comparison. Type I8 I16 I32 F32. */
17773 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17774 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17775 /* As above, D registers only. */
17776 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17777 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17778 /* Int and float variants, signedness unimportant. */
17779 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17780 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17781 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17782 /* Add/sub take types I8 I16 I32 I64 F32. */
17783 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17784 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17785 /* vtst takes sizes 8, 16, 32. */
17786 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17787 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17788 /* VMUL takes I8 I16 I32 F32 P8. */
17789 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17790 /* VQD{R}MULH takes S16 S32. */
17791 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17792 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17793 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17794 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17795 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17796 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17797 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17798 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17799 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17800 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17801 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17802 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17803 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17804 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17805 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17806 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17808 /* Two address, int/float. Types S8 S16 S32 F32. */
17809 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17810 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17812 /* Data processing with two registers and a shift amount. */
17813 /* Right shifts, and variants with rounding.
17814 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17815 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17816 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17817 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17818 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17819 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17820 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17821 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17822 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17823 /* Shift and insert. Sizes accepted 8 16 32 64. */
17824 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17825 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17826 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17827 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17828 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17829 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17830 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17831 /* Right shift immediate, saturating & narrowing, with rounding variants.
17832 Types accepted S16 S32 S64 U16 U32 U64. */
17833 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17834 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17835 /* As above, unsigned. Types accepted S16 S32 S64. */
17836 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17837 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17838 /* Right shift narrowing. Types accepted I16 I32 I64. */
17839 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17840 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17841 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17842 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17843 /* CVT with optional immediate for fixed-point variant. */
17844 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17846 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17847 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17849 /* Data processing, three registers of different lengths. */
17850 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17851 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17852 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17853 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17854 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17855 /* If not scalar, fall back to neon_dyadic_long.
17856 Vector types as above, scalar types S16 S32 U16 U32. */
17857 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17858 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17859 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17860 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17861 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17862 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17863 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17864 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17865 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17866 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17867 /* Saturating doubling multiplies. Types S16 S32. */
17868 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17869 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17870 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17871 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17872 S16 S32 U16 U32. */
17873 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17875 /* Extract. Size 8. */
17876 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17877 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17879 /* Two registers, miscellaneous. */
17880 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17881 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17882 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17883 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17884 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17885 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17886 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17887 /* Vector replicate. Sizes 8 16 32. */
17888 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17889 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17890 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17891 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17892 /* VMOVN. Types I16 I32 I64. */
17893 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17894 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17895 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17896 /* VQMOVUN. Types S16 S32 S64. */
17897 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17898 /* VZIP / VUZP. Sizes 8 16 32. */
17899 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17900 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17901 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17902 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17903 /* VQABS / VQNEG. Types S8 S16 S32. */
17904 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17905 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17906 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17907 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17908 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17909 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17910 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17911 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17912 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17913 /* Reciprocal estimates. Types U32 F32. */
17914 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17915 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17916 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17917 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17918 /* VCLS. Types S8 S16 S32. */
17919 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17920 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17921 /* VCLZ. Types I8 I16 I32. */
17922 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17923 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17924 /* VCNT. Size 8. */
17925 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17926 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17927 /* Two address, untyped. */
17928 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17929 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17930 /* VTRN. Sizes 8 16 32. */
17931 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17932 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17934 /* Table lookup. Size 8. */
17935 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17936 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17938 #undef THUMB_VARIANT
17939 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17941 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17943 /* Neon element/structure load/store. */
17944 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17945 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17946 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17947 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17948 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17949 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17950 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17951 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17953 #undef THUMB_VARIANT
17954 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17956 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17957 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17958 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17959 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17960 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17961 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17962 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17963 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17964 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17965 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17967 #undef THUMB_VARIANT
17968 #define THUMB_VARIANT & fpu_vfp_ext_v3
17970 #define ARM_VARIANT & fpu_vfp_ext_v3
17972 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17973 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17974 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17975 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17976 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17977 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17978 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17979 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17980 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17983 #define ARM_VARIANT &fpu_vfp_ext_fma
17984 #undef THUMB_VARIANT
17985 #define THUMB_VARIANT &fpu_vfp_ext_fma
17986 /* Mnemonics shared by Neon and VFP. These are included in the
17987 VFP FMA variant; NEON and VFP FMA always includes the NEON
17988 FMA instructions. */
17989 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17990 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17991 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17992 the v form should always be used. */
17993 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17994 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17995 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17996 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17997 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17998 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18000 #undef THUMB_VARIANT
18002 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18004 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18005 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18006 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18007 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18008 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18009 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18010 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18011 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18014 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18016 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18017 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18018 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18019 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18020 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18021 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18022 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18023 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18024 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18025 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18026 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18027 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18028 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18029 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18030 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18031 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18032 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18033 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18034 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18035 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18036 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18037 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18038 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18039 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18040 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18041 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18042 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18043 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18044 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18045 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18046 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18047 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18048 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18049 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18050 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18051 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18052 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18053 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18054 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18055 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18056 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18057 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18058 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18059 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18060 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18061 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18062 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18063 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18064 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18065 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18066 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18067 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18068 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18069 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18070 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18071 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18072 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18073 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18074 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18075 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18076 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18077 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18078 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18079 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18080 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18081 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18082 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18083 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18084 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18085 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18086 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18087 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18088 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18089 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18090 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18091 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18092 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18093 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18094 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18095 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18096 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18097 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18098 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18099 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18100 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18101 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18102 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18103 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18104 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18105 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18106 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18107 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18108 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18109 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18110 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18111 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18112 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18113 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18114 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18115 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18116 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18117 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18118 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18119 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18120 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18121 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18122 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18123 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18124 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18125 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18126 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18127 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18128 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18129 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18130 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18131 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18132 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18133 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18134 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18135 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18136 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18137 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18138 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18139 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18140 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18141 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18142 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18143 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18144 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18145 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18146 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18147 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18148 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18149 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18150 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18151 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18152 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18153 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18154 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18155 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18156 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18157 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18158 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18159 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18160 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18161 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18162 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18163 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18164 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18165 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18166 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18167 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18168 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18169 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18170 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18171 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18172 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18173 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18174 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18175 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18176 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18177 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18180 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18182 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18183 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18184 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18185 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18186 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18187 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18188 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18189 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18190 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18191 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18192 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18193 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18194 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18195 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18196 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18197 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18198 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18199 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18200 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18201 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18202 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18203 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18204 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18205 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18206 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18207 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18208 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18209 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18210 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18211 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18212 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18213 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18214 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18215 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18216 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18217 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18218 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18219 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18220 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18221 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18222 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18223 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18224 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18225 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18226 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18227 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18228 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18229 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18230 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18231 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18232 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18233 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18234 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18235 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18236 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18237 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18238 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18241 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18243 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18244 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18245 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18246 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18247 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18248 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18249 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18250 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18251 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18252 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18253 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18254 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18255 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18256 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18257 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18258 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18259 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18260 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18261 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18262 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18263 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18264 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18265 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18266 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18267 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18268 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18269 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18270 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18271 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18272 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18273 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18274 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18275 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18276 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18277 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18278 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18279 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18280 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18281 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18282 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18283 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18284 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18285 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18286 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18287 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18288 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18289 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18290 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18291 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18292 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18293 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18294 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18295 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18296 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18297 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18298 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18299 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18300 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18301 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18302 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18303 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18304 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18305 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18306 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18307 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18308 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18309 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18310 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18311 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18312 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18313 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18314 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18315 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18316 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18317 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18318 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18321 #undef THUMB_VARIANT
18348 /* MD interface: bits in the object file. */
18350 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18351 for use in the a.out file, and stores them in the array pointed to by buf.
18352 This knows about the endian-ness of the target machine and does
18353 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18354 2 (short) and 4 (long) Floating numbers are put out as a series of
18355 LITTLENUMS (shorts, here at least). */
18358 md_number_to_chars (char * buf
, valueT val
, int n
)
18360 if (target_big_endian
)
18361 number_to_chars_bigendian (buf
, val
, n
);
18363 number_to_chars_littleendian (buf
, val
, n
);
18367 md_chars_to_number (char * buf
, int n
)
18370 unsigned char * where
= (unsigned char *) buf
;
18372 if (target_big_endian
)
18377 result
|= (*where
++ & 255);
18385 result
|= (where
[n
] & 255);
18392 /* MD interface: Sections. */
18394 /* Estimate the size of a frag before relaxing. Assume everything fits in
18398 md_estimate_size_before_relax (fragS
* fragp
,
18399 segT segtype ATTRIBUTE_UNUSED
)
18405 /* Convert a machine dependent frag. */
18408 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18410 unsigned long insn
;
18411 unsigned long old_op
;
18419 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18421 old_op
= bfd_get_16(abfd
, buf
);
18422 if (fragp
->fr_symbol
)
18424 exp
.X_op
= O_symbol
;
18425 exp
.X_add_symbol
= fragp
->fr_symbol
;
18429 exp
.X_op
= O_constant
;
18431 exp
.X_add_number
= fragp
->fr_offset
;
18432 opcode
= fragp
->fr_subtype
;
18435 case T_MNEM_ldr_pc
:
18436 case T_MNEM_ldr_pc2
:
18437 case T_MNEM_ldr_sp
:
18438 case T_MNEM_str_sp
:
18445 if (fragp
->fr_var
== 4)
18447 insn
= THUMB_OP32 (opcode
);
18448 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18450 insn
|= (old_op
& 0x700) << 4;
18454 insn
|= (old_op
& 7) << 12;
18455 insn
|= (old_op
& 0x38) << 13;
18457 insn
|= 0x00000c00;
18458 put_thumb32_insn (buf
, insn
);
18459 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18463 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18465 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18468 if (fragp
->fr_var
== 4)
18470 insn
= THUMB_OP32 (opcode
);
18471 insn
|= (old_op
& 0xf0) << 4;
18472 put_thumb32_insn (buf
, insn
);
18473 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18477 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18478 exp
.X_add_number
-= 4;
18486 if (fragp
->fr_var
== 4)
18488 int r0off
= (opcode
== T_MNEM_mov
18489 || opcode
== T_MNEM_movs
) ? 0 : 8;
18490 insn
= THUMB_OP32 (opcode
);
18491 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18492 insn
|= (old_op
& 0x700) << r0off
;
18493 put_thumb32_insn (buf
, insn
);
18494 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18498 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18503 if (fragp
->fr_var
== 4)
18505 insn
= THUMB_OP32(opcode
);
18506 put_thumb32_insn (buf
, insn
);
18507 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18510 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18514 if (fragp
->fr_var
== 4)
18516 insn
= THUMB_OP32(opcode
);
18517 insn
|= (old_op
& 0xf00) << 14;
18518 put_thumb32_insn (buf
, insn
);
18519 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18522 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18525 case T_MNEM_add_sp
:
18526 case T_MNEM_add_pc
:
18527 case T_MNEM_inc_sp
:
18528 case T_MNEM_dec_sp
:
18529 if (fragp
->fr_var
== 4)
18531 /* ??? Choose between add and addw. */
18532 insn
= THUMB_OP32 (opcode
);
18533 insn
|= (old_op
& 0xf0) << 4;
18534 put_thumb32_insn (buf
, insn
);
18535 if (opcode
== T_MNEM_add_pc
)
18536 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18538 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18541 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18549 if (fragp
->fr_var
== 4)
18551 insn
= THUMB_OP32 (opcode
);
18552 insn
|= (old_op
& 0xf0) << 4;
18553 insn
|= (old_op
& 0xf) << 16;
18554 put_thumb32_insn (buf
, insn
);
18555 if (insn
& (1 << 20))
18556 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18558 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18561 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18567 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18568 (enum bfd_reloc_code_real
) reloc_type
);
18569 fixp
->fx_file
= fragp
->fr_file
;
18570 fixp
->fx_line
= fragp
->fr_line
;
18571 fragp
->fr_fix
+= fragp
->fr_var
;
18574 /* Return the size of a relaxable immediate operand instruction.
18575 SHIFT and SIZE specify the form of the allowable immediate. */
18577 relax_immediate (fragS
*fragp
, int size
, int shift
)
18583 /* ??? Should be able to do better than this. */
18584 if (fragp
->fr_symbol
)
18587 low
= (1 << shift
) - 1;
18588 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18589 offset
= fragp
->fr_offset
;
18590 /* Force misaligned offsets to 32-bit variant. */
18593 if (offset
& ~mask
)
18598 /* Get the address of a symbol during relaxation. */
18600 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18606 sym
= fragp
->fr_symbol
;
18607 sym_frag
= symbol_get_frag (sym
);
18608 know (S_GET_SEGMENT (sym
) != absolute_section
18609 || sym_frag
== &zero_address_frag
);
18610 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18612 /* If frag has yet to be reached on this pass, assume it will
18613 move by STRETCH just as we did. If this is not so, it will
18614 be because some frag between grows, and that will force
18618 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18622 /* Adjust stretch for any alignment frag. Note that if have
18623 been expanding the earlier code, the symbol may be
18624 defined in what appears to be an earlier frag. FIXME:
18625 This doesn't handle the fr_subtype field, which specifies
18626 a maximum number of bytes to skip when doing an
18628 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18630 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18633 stretch
= - ((- stretch
)
18634 & ~ ((1 << (int) f
->fr_offset
) - 1));
18636 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18648 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18651 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18656 /* Assume worst case for symbols not known to be in the same section. */
18657 if (fragp
->fr_symbol
== NULL
18658 || !S_IS_DEFINED (fragp
->fr_symbol
)
18659 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18660 || S_IS_WEAK (fragp
->fr_symbol
))
18663 val
= relaxed_symbol_addr (fragp
, stretch
);
18664 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18665 addr
= (addr
+ 4) & ~3;
18666 /* Force misaligned targets to 32-bit variant. */
18670 if (val
< 0 || val
> 1020)
18675 /* Return the size of a relaxable add/sub immediate instruction. */
18677 relax_addsub (fragS
*fragp
, asection
*sec
)
18682 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18683 op
= bfd_get_16(sec
->owner
, buf
);
18684 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18685 return relax_immediate (fragp
, 8, 0);
18687 return relax_immediate (fragp
, 3, 0);
18691 /* Return the size of a relaxable branch instruction. BITS is the
18692 size of the offset field in the narrow instruction. */
18695 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18701 /* Assume worst case for symbols not known to be in the same section. */
18702 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18703 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18704 || S_IS_WEAK (fragp
->fr_symbol
))
18708 if (S_IS_DEFINED (fragp
->fr_symbol
)
18709 && ARM_IS_FUNC (fragp
->fr_symbol
))
18713 val
= relaxed_symbol_addr (fragp
, stretch
);
18714 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18717 /* Offset is a signed value *2 */
18719 if (val
>= limit
|| val
< -limit
)
18725 /* Relax a machine dependent frag. This returns the amount by which
18726 the current size of the frag should change. */
18729 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18734 oldsize
= fragp
->fr_var
;
18735 switch (fragp
->fr_subtype
)
18737 case T_MNEM_ldr_pc2
:
18738 newsize
= relax_adr (fragp
, sec
, stretch
);
18740 case T_MNEM_ldr_pc
:
18741 case T_MNEM_ldr_sp
:
18742 case T_MNEM_str_sp
:
18743 newsize
= relax_immediate (fragp
, 8, 2);
18747 newsize
= relax_immediate (fragp
, 5, 2);
18751 newsize
= relax_immediate (fragp
, 5, 1);
18755 newsize
= relax_immediate (fragp
, 5, 0);
18758 newsize
= relax_adr (fragp
, sec
, stretch
);
18764 newsize
= relax_immediate (fragp
, 8, 0);
18767 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18770 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18772 case T_MNEM_add_sp
:
18773 case T_MNEM_add_pc
:
18774 newsize
= relax_immediate (fragp
, 8, 2);
18776 case T_MNEM_inc_sp
:
18777 case T_MNEM_dec_sp
:
18778 newsize
= relax_immediate (fragp
, 7, 2);
18784 newsize
= relax_addsub (fragp
, sec
);
18790 fragp
->fr_var
= newsize
;
18791 /* Freeze wide instructions that are at or before the same location as
18792 in the previous pass. This avoids infinite loops.
18793 Don't freeze them unconditionally because targets may be artificially
18794 misaligned by the expansion of preceding frags. */
18795 if (stretch
<= 0 && newsize
> 2)
18797 md_convert_frag (sec
->owner
, sec
, fragp
);
18801 return newsize
- oldsize
;
18804 /* Round up a section size to the appropriate boundary. */
18807 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18810 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18811 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18813 /* For a.out, force the section size to be aligned. If we don't do
18814 this, BFD will align it for us, but it will not write out the
18815 final bytes of the section. This may be a bug in BFD, but it is
18816 easier to fix it here since that is how the other a.out targets
18820 align
= bfd_get_section_alignment (stdoutput
, segment
);
18821 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18828 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18829 of an rs_align_code fragment. */
18832 arm_handle_align (fragS
* fragP
)
18834 static char const arm_noop
[2][2][4] =
18837 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18838 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18841 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18842 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18845 static char const thumb_noop
[2][2][2] =
18848 {0xc0, 0x46}, /* LE */
18849 {0x46, 0xc0}, /* BE */
18852 {0x00, 0xbf}, /* LE */
18853 {0xbf, 0x00} /* BE */
18856 static char const wide_thumb_noop
[2][4] =
18857 { /* Wide Thumb-2 */
18858 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18859 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18862 unsigned bytes
, fix
, noop_size
;
18865 const char *narrow_noop
= NULL
;
18870 if (fragP
->fr_type
!= rs_align_code
)
18873 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18874 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18877 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18878 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18880 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18882 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18884 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18886 narrow_noop
= thumb_noop
[1][target_big_endian
];
18887 noop
= wide_thumb_noop
[target_big_endian
];
18890 noop
= thumb_noop
[0][target_big_endian
];
18898 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18899 [target_big_endian
];
18906 fragP
->fr_var
= noop_size
;
18908 if (bytes
& (noop_size
- 1))
18910 fix
= bytes
& (noop_size
- 1);
18912 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18914 memset (p
, 0, fix
);
18921 if (bytes
& noop_size
)
18923 /* Insert a narrow noop. */
18924 memcpy (p
, narrow_noop
, noop_size
);
18926 bytes
-= noop_size
;
18930 /* Use wide noops for the remainder */
18934 while (bytes
>= noop_size
)
18936 memcpy (p
, noop
, noop_size
);
18938 bytes
-= noop_size
;
18942 fragP
->fr_fix
+= fix
;
18945 /* Called from md_do_align. Used to create an alignment
18946 frag in a code section. */
18949 arm_frag_align_code (int n
, int max
)
18953 /* We assume that there will never be a requirement
18954 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18955 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18960 _("alignments greater than %d bytes not supported in .text sections."),
18961 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18962 as_fatal ("%s", err_msg
);
18965 p
= frag_var (rs_align_code
,
18966 MAX_MEM_FOR_RS_ALIGN_CODE
,
18968 (relax_substateT
) max
,
18975 /* Perform target specific initialisation of a frag.
18976 Note - despite the name this initialisation is not done when the frag
18977 is created, but only when its type is assigned. A frag can be created
18978 and used a long time before its type is set, so beware of assuming that
18979 this initialisationis performed first. */
18983 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18985 /* Record whether this frag is in an ARM or a THUMB area. */
18986 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18989 #else /* OBJ_ELF is defined. */
18991 arm_init_frag (fragS
* fragP
, int max_chars
)
18993 /* If the current ARM vs THUMB mode has not already
18994 been recorded into this frag then do so now. */
18995 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18997 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18999 /* Record a mapping symbol for alignment frags. We will delete this
19000 later if the alignment ends up empty. */
19001 switch (fragP
->fr_type
)
19004 case rs_align_test
:
19006 mapping_state_2 (MAP_DATA
, max_chars
);
19008 case rs_align_code
:
19009 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19017 /* When we change sections we need to issue a new mapping symbol. */
19020 arm_elf_change_section (void)
19022 /* Link an unlinked unwind index table section to the .text section. */
19023 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19024 && elf_linked_to_section (now_seg
) == NULL
)
19025 elf_linked_to_section (now_seg
) = text_section
;
19029 arm_elf_section_type (const char * str
, size_t len
)
19031 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19032 return SHT_ARM_EXIDX
;
19037 /* Code to deal with unwinding tables. */
19039 static void add_unwind_adjustsp (offsetT
);
19041 /* Generate any deferred unwind frame offset. */
19044 flush_pending_unwind (void)
19048 offset
= unwind
.pending_offset
;
19049 unwind
.pending_offset
= 0;
19051 add_unwind_adjustsp (offset
);
19054 /* Add an opcode to this list for this function. Two-byte opcodes should
19055 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19059 add_unwind_opcode (valueT op
, int length
)
19061 /* Add any deferred stack adjustment. */
19062 if (unwind
.pending_offset
)
19063 flush_pending_unwind ();
19065 unwind
.sp_restored
= 0;
19067 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19069 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19070 if (unwind
.opcodes
)
19071 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19072 unwind
.opcode_alloc
);
19074 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19079 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19081 unwind
.opcode_count
++;
19085 /* Add unwind opcodes to adjust the stack pointer. */
19088 add_unwind_adjustsp (offsetT offset
)
19092 if (offset
> 0x200)
19094 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19099 /* Long form: 0xb2, uleb128. */
19100 /* This might not fit in a word so add the individual bytes,
19101 remembering the list is built in reverse order. */
19102 o
= (valueT
) ((offset
- 0x204) >> 2);
19104 add_unwind_opcode (0, 1);
19106 /* Calculate the uleb128 encoding of the offset. */
19110 bytes
[n
] = o
& 0x7f;
19116 /* Add the insn. */
19118 add_unwind_opcode (bytes
[n
- 1], 1);
19119 add_unwind_opcode (0xb2, 1);
19121 else if (offset
> 0x100)
19123 /* Two short opcodes. */
19124 add_unwind_opcode (0x3f, 1);
19125 op
= (offset
- 0x104) >> 2;
19126 add_unwind_opcode (op
, 1);
19128 else if (offset
> 0)
19130 /* Short opcode. */
19131 op
= (offset
- 4) >> 2;
19132 add_unwind_opcode (op
, 1);
19134 else if (offset
< 0)
19137 while (offset
> 0x100)
19139 add_unwind_opcode (0x7f, 1);
19142 op
= ((offset
- 4) >> 2) | 0x40;
19143 add_unwind_opcode (op
, 1);
19147 /* Finish the list of unwind opcodes for this function. */
19149 finish_unwind_opcodes (void)
19153 if (unwind
.fp_used
)
19155 /* Adjust sp as necessary. */
19156 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19157 flush_pending_unwind ();
19159 /* After restoring sp from the frame pointer. */
19160 op
= 0x90 | unwind
.fp_reg
;
19161 add_unwind_opcode (op
, 1);
19164 flush_pending_unwind ();
19168 /* Start an exception table entry. If idx is nonzero this is an index table
19172 start_unwind_section (const segT text_seg
, int idx
)
19174 const char * text_name
;
19175 const char * prefix
;
19176 const char * prefix_once
;
19177 const char * group_name
;
19181 size_t sec_name_len
;
19188 prefix
= ELF_STRING_ARM_unwind
;
19189 prefix_once
= ELF_STRING_ARM_unwind_once
;
19190 type
= SHT_ARM_EXIDX
;
19194 prefix
= ELF_STRING_ARM_unwind_info
;
19195 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19196 type
= SHT_PROGBITS
;
19199 text_name
= segment_name (text_seg
);
19200 if (streq (text_name
, ".text"))
19203 if (strncmp (text_name
, ".gnu.linkonce.t.",
19204 strlen (".gnu.linkonce.t.")) == 0)
19206 prefix
= prefix_once
;
19207 text_name
+= strlen (".gnu.linkonce.t.");
19210 prefix_len
= strlen (prefix
);
19211 text_len
= strlen (text_name
);
19212 sec_name_len
= prefix_len
+ text_len
;
19213 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19214 memcpy (sec_name
, prefix
, prefix_len
);
19215 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19216 sec_name
[prefix_len
+ text_len
] = '\0';
19222 /* Handle COMDAT group. */
19223 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19225 group_name
= elf_group_name (text_seg
);
19226 if (group_name
== NULL
)
19228 as_bad (_("Group section `%s' has no group signature"),
19229 segment_name (text_seg
));
19230 ignore_rest_of_line ();
19233 flags
|= SHF_GROUP
;
19237 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19239 /* Set the section link for index tables. */
19241 elf_linked_to_section (now_seg
) = text_seg
;
19245 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19246 personality routine data. Returns zero, or the index table value for
19247 and inline entry. */
19250 create_unwind_entry (int have_data
)
19255 /* The current word of data. */
19257 /* The number of bytes left in this word. */
19260 finish_unwind_opcodes ();
19262 /* Remember the current text section. */
19263 unwind
.saved_seg
= now_seg
;
19264 unwind
.saved_subseg
= now_subseg
;
19266 start_unwind_section (now_seg
, 0);
19268 if (unwind
.personality_routine
== NULL
)
19270 if (unwind
.personality_index
== -2)
19273 as_bad (_("handlerdata in cantunwind frame"));
19274 return 1; /* EXIDX_CANTUNWIND. */
19277 /* Use a default personality routine if none is specified. */
19278 if (unwind
.personality_index
== -1)
19280 if (unwind
.opcode_count
> 3)
19281 unwind
.personality_index
= 1;
19283 unwind
.personality_index
= 0;
19286 /* Space for the personality routine entry. */
19287 if (unwind
.personality_index
== 0)
19289 if (unwind
.opcode_count
> 3)
19290 as_bad (_("too many unwind opcodes for personality routine 0"));
19294 /* All the data is inline in the index table. */
19297 while (unwind
.opcode_count
> 0)
19299 unwind
.opcode_count
--;
19300 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19304 /* Pad with "finish" opcodes. */
19306 data
= (data
<< 8) | 0xb0;
19313 /* We get two opcodes "free" in the first word. */
19314 size
= unwind
.opcode_count
- 2;
19317 /* An extra byte is required for the opcode count. */
19318 size
= unwind
.opcode_count
+ 1;
19320 size
= (size
+ 3) >> 2;
19322 as_bad (_("too many unwind opcodes"));
19324 frag_align (2, 0, 0);
19325 record_alignment (now_seg
, 2);
19326 unwind
.table_entry
= expr_build_dot ();
19328 /* Allocate the table entry. */
19329 ptr
= frag_more ((size
<< 2) + 4);
19330 where
= frag_now_fix () - ((size
<< 2) + 4);
19332 switch (unwind
.personality_index
)
19335 /* ??? Should this be a PLT generating relocation? */
19336 /* Custom personality routine. */
19337 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19338 BFD_RELOC_ARM_PREL31
);
19343 /* Set the first byte to the number of additional words. */
19348 /* ABI defined personality routines. */
19350 /* Three opcodes bytes are packed into the first word. */
19357 /* The size and first two opcode bytes go in the first word. */
19358 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19363 /* Should never happen. */
19367 /* Pack the opcodes into words (MSB first), reversing the list at the same
19369 while (unwind
.opcode_count
> 0)
19373 md_number_to_chars (ptr
, data
, 4);
19378 unwind
.opcode_count
--;
19380 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19383 /* Finish off the last word. */
19386 /* Pad with "finish" opcodes. */
19388 data
= (data
<< 8) | 0xb0;
19390 md_number_to_chars (ptr
, data
, 4);
19395 /* Add an empty descriptor if there is no user-specified data. */
19396 ptr
= frag_more (4);
19397 md_number_to_chars (ptr
, 0, 4);
19404 /* Initialize the DWARF-2 unwind information for this procedure. */
19407 tc_arm_frame_initial_instructions (void)
19409 cfi_add_CFA_def_cfa (REG_SP
, 0);
19411 #endif /* OBJ_ELF */
19413 /* Convert REGNAME to a DWARF-2 register number. */
19416 tc_arm_regname_to_dw2regnum (char *regname
)
19418 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19428 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19432 exp
.X_op
= O_secrel
;
19433 exp
.X_add_symbol
= symbol
;
19434 exp
.X_add_number
= 0;
19435 emit_expr (&exp
, size
);
19439 /* MD interface: Symbol and relocation handling. */
19441 /* Return the address within the segment that a PC-relative fixup is
19442 relative to. For ARM, PC-relative fixups applied to instructions
19443 are generally relative to the location of the fixup plus 8 bytes.
19444 Thumb branches are offset by 4, and Thumb loads relative to PC
19445 require special handling. */
19448 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19450 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19452 /* If this is pc-relative and we are going to emit a relocation
19453 then we just want to put out any pipeline compensation that the linker
19454 will need. Otherwise we want to use the calculated base.
19455 For WinCE we skip the bias for externals as well, since this
19456 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19458 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19459 || (arm_force_relocation (fixP
)
19461 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19467 switch (fixP
->fx_r_type
)
19469 /* PC relative addressing on the Thumb is slightly odd as the
19470 bottom two bits of the PC are forced to zero for the
19471 calculation. This happens *after* application of the
19472 pipeline offset. However, Thumb adrl already adjusts for
19473 this, so we need not do it again. */
19474 case BFD_RELOC_ARM_THUMB_ADD
:
19477 case BFD_RELOC_ARM_THUMB_OFFSET
:
19478 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19479 case BFD_RELOC_ARM_T32_ADD_PC12
:
19480 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19481 return (base
+ 4) & ~3;
19483 /* Thumb branches are simply offset by +4. */
19484 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19485 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19486 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19487 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19488 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19491 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19493 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19494 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19495 && ARM_IS_FUNC (fixP
->fx_addsy
)
19496 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19497 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19500 /* BLX is like branches above, but forces the low two bits of PC to
19502 case BFD_RELOC_THUMB_PCREL_BLX
:
19504 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19505 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19506 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19507 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19508 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19509 return (base
+ 4) & ~3;
19511 /* ARM mode branches are offset by +8. However, the Windows CE
19512 loader expects the relocation not to take this into account. */
19513 case BFD_RELOC_ARM_PCREL_BLX
:
19515 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19516 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19517 && ARM_IS_FUNC (fixP
->fx_addsy
)
19518 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19519 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19522 case BFD_RELOC_ARM_PCREL_CALL
:
19524 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19525 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19526 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19527 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19528 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19531 case BFD_RELOC_ARM_PCREL_BRANCH
:
19532 case BFD_RELOC_ARM_PCREL_JUMP
:
19533 case BFD_RELOC_ARM_PLT32
:
19535 /* When handling fixups immediately, because we have already
19536 discovered the value of a symbol, or the address of the frag involved
19537 we must account for the offset by +8, as the OS loader will never see the reloc.
19538 see fixup_segment() in write.c
19539 The S_IS_EXTERNAL test handles the case of global symbols.
19540 Those need the calculated base, not just the pipe compensation the linker will need. */
19542 && fixP
->fx_addsy
!= NULL
19543 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19544 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19552 /* ARM mode loads relative to PC are also offset by +8. Unlike
19553 branches, the Windows CE loader *does* expect the relocation
19554 to take this into account. */
19555 case BFD_RELOC_ARM_OFFSET_IMM
:
19556 case BFD_RELOC_ARM_OFFSET_IMM8
:
19557 case BFD_RELOC_ARM_HWLITERAL
:
19558 case BFD_RELOC_ARM_LITERAL
:
19559 case BFD_RELOC_ARM_CP_OFF_IMM
:
19563 /* Other PC-relative relocations are un-offset. */
19569 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19570 Otherwise we have no need to default values of symbols. */
19573 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19576 if (name
[0] == '_' && name
[1] == 'G'
19577 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19581 if (symbol_find (name
))
19582 as_bad (_("GOT already in the symbol table"));
19584 GOT_symbol
= symbol_new (name
, undefined_section
,
19585 (valueT
) 0, & zero_address_frag
);
19595 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19596 computed as two separate immediate values, added together. We
19597 already know that this value cannot be computed by just one ARM
19600 static unsigned int
19601 validate_immediate_twopart (unsigned int val
,
19602 unsigned int * highpart
)
19607 for (i
= 0; i
< 32; i
+= 2)
19608 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19614 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19616 else if (a
& 0xff0000)
19618 if (a
& 0xff000000)
19620 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19624 gas_assert (a
& 0xff000000);
19625 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19628 return (a
& 0xff) | (i
<< 7);
19635 validate_offset_imm (unsigned int val
, int hwse
)
19637 if ((hwse
&& val
> 255) || val
> 4095)
19642 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19643 negative immediate constant by altering the instruction. A bit of
19648 by inverting the second operand, and
19651 by negating the second operand. */
19654 negate_data_op (unsigned long * instruction
,
19655 unsigned long value
)
19658 unsigned long negated
, inverted
;
19660 negated
= encode_arm_immediate (-value
);
19661 inverted
= encode_arm_immediate (~value
);
19663 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19666 /* First negates. */
19667 case OPCODE_SUB
: /* ADD <-> SUB */
19668 new_inst
= OPCODE_ADD
;
19673 new_inst
= OPCODE_SUB
;
19677 case OPCODE_CMP
: /* CMP <-> CMN */
19678 new_inst
= OPCODE_CMN
;
19683 new_inst
= OPCODE_CMP
;
19687 /* Now Inverted ops. */
19688 case OPCODE_MOV
: /* MOV <-> MVN */
19689 new_inst
= OPCODE_MVN
;
19694 new_inst
= OPCODE_MOV
;
19698 case OPCODE_AND
: /* AND <-> BIC */
19699 new_inst
= OPCODE_BIC
;
19704 new_inst
= OPCODE_AND
;
19708 case OPCODE_ADC
: /* ADC <-> SBC */
19709 new_inst
= OPCODE_SBC
;
19714 new_inst
= OPCODE_ADC
;
19718 /* We cannot do anything. */
19723 if (value
== (unsigned) FAIL
)
19726 *instruction
&= OPCODE_MASK
;
19727 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19731 /* Like negate_data_op, but for Thumb-2. */
19733 static unsigned int
19734 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19738 unsigned int negated
, inverted
;
19740 negated
= encode_thumb32_immediate (-value
);
19741 inverted
= encode_thumb32_immediate (~value
);
19743 rd
= (*instruction
>> 8) & 0xf;
19744 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19747 /* ADD <-> SUB. Includes CMP <-> CMN. */
19748 case T2_OPCODE_SUB
:
19749 new_inst
= T2_OPCODE_ADD
;
19753 case T2_OPCODE_ADD
:
19754 new_inst
= T2_OPCODE_SUB
;
19758 /* ORR <-> ORN. Includes MOV <-> MVN. */
19759 case T2_OPCODE_ORR
:
19760 new_inst
= T2_OPCODE_ORN
;
19764 case T2_OPCODE_ORN
:
19765 new_inst
= T2_OPCODE_ORR
;
19769 /* AND <-> BIC. TST has no inverted equivalent. */
19770 case T2_OPCODE_AND
:
19771 new_inst
= T2_OPCODE_BIC
;
19778 case T2_OPCODE_BIC
:
19779 new_inst
= T2_OPCODE_AND
;
19784 case T2_OPCODE_ADC
:
19785 new_inst
= T2_OPCODE_SBC
;
19789 case T2_OPCODE_SBC
:
19790 new_inst
= T2_OPCODE_ADC
;
19794 /* We cannot do anything. */
19799 if (value
== (unsigned int)FAIL
)
19802 *instruction
&= T2_OPCODE_MASK
;
19803 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19807 /* Read a 32-bit thumb instruction from buf. */
19808 static unsigned long
19809 get_thumb32_insn (char * buf
)
19811 unsigned long insn
;
19812 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19813 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19819 /* We usually want to set the low bit on the address of thumb function
19820 symbols. In particular .word foo - . should have the low bit set.
19821 Generic code tries to fold the difference of two symbols to
19822 a constant. Prevent this and force a relocation when the first symbols
19823 is a thumb function. */
19826 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19828 if (op
== O_subtract
19829 && l
->X_op
== O_symbol
19830 && r
->X_op
== O_symbol
19831 && THUMB_IS_FUNC (l
->X_add_symbol
))
19833 l
->X_op
= O_subtract
;
19834 l
->X_op_symbol
= r
->X_add_symbol
;
19835 l
->X_add_number
-= r
->X_add_number
;
19839 /* Process as normal. */
19843 /* Encode Thumb2 unconditional branches and calls. The encoding
19844 for the 2 are identical for the immediate values. */
19847 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19849 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19852 addressT S
, I1
, I2
, lo
, hi
;
19854 S
= (value
>> 24) & 0x01;
19855 I1
= (value
>> 23) & 0x01;
19856 I2
= (value
>> 22) & 0x01;
19857 hi
= (value
>> 12) & 0x3ff;
19858 lo
= (value
>> 1) & 0x7ff;
19859 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19860 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19861 newval
|= (S
<< 10) | hi
;
19862 newval2
&= ~T2I1I2MASK
;
19863 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19864 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19865 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19869 md_apply_fix (fixS
* fixP
,
19873 offsetT value
= * valP
;
19875 unsigned int newimm
;
19876 unsigned long temp
;
19878 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19880 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19882 /* Note whether this will delete the relocation. */
19884 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19887 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19888 consistency with the behaviour on 32-bit hosts. Remember value
19890 value
&= 0xffffffff;
19891 value
^= 0x80000000;
19892 value
-= 0x80000000;
19895 fixP
->fx_addnumber
= value
;
19897 /* Same treatment for fixP->fx_offset. */
19898 fixP
->fx_offset
&= 0xffffffff;
19899 fixP
->fx_offset
^= 0x80000000;
19900 fixP
->fx_offset
-= 0x80000000;
19902 switch (fixP
->fx_r_type
)
19904 case BFD_RELOC_NONE
:
19905 /* This will need to go in the object file. */
19909 case BFD_RELOC_ARM_IMMEDIATE
:
19910 /* We claim that this fixup has been processed here,
19911 even if in fact we generate an error because we do
19912 not have a reloc for it, so tc_gen_reloc will reject it. */
19915 if (fixP
->fx_addsy
)
19917 const char *msg
= 0;
19919 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19920 msg
= _("undefined symbol %s used as an immediate value");
19921 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19922 msg
= _("symbol %s is in a different section");
19923 else if (S_IS_WEAK (fixP
->fx_addsy
))
19924 msg
= _("symbol %s is weak and may be overridden later");
19928 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19929 msg
, S_GET_NAME (fixP
->fx_addsy
));
19934 newimm
= encode_arm_immediate (value
);
19935 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19937 /* If the instruction will fail, see if we can fix things up by
19938 changing the opcode. */
19939 if (newimm
== (unsigned int) FAIL
19940 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19943 _("invalid constant (%lx) after fixup"),
19944 (unsigned long) value
);
19948 newimm
|= (temp
& 0xfffff000);
19949 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19952 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19954 unsigned int highpart
= 0;
19955 unsigned int newinsn
= 0xe1a00000; /* nop. */
19957 if (fixP
->fx_addsy
)
19959 const char *msg
= 0;
19961 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19962 msg
= _("undefined symbol %s used as an immediate value");
19963 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19964 msg
= _("symbol %s is in a different section");
19965 else if (S_IS_WEAK (fixP
->fx_addsy
))
19966 msg
= _("symbol %s is weak and may be overridden later");
19970 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19971 msg
, S_GET_NAME (fixP
->fx_addsy
));
19976 newimm
= encode_arm_immediate (value
);
19977 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19979 /* If the instruction will fail, see if we can fix things up by
19980 changing the opcode. */
19981 if (newimm
== (unsigned int) FAIL
19982 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19984 /* No ? OK - try using two ADD instructions to generate
19986 newimm
= validate_immediate_twopart (value
, & highpart
);
19988 /* Yes - then make sure that the second instruction is
19990 if (newimm
!= (unsigned int) FAIL
)
19992 /* Still No ? Try using a negated value. */
19993 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19994 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19995 /* Otherwise - give up. */
19998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19999 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20004 /* Replace the first operand in the 2nd instruction (which
20005 is the PC) with the destination register. We have
20006 already added in the PC in the first instruction and we
20007 do not want to do it again. */
20008 newinsn
&= ~ 0xf0000;
20009 newinsn
|= ((newinsn
& 0x0f000) << 4);
20012 newimm
|= (temp
& 0xfffff000);
20013 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20015 highpart
|= (newinsn
& 0xfffff000);
20016 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20020 case BFD_RELOC_ARM_OFFSET_IMM
:
20021 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20024 case BFD_RELOC_ARM_LITERAL
:
20030 if (validate_offset_imm (value
, 0) == FAIL
)
20032 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20034 _("invalid literal constant: pool needs to be closer"));
20036 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20037 _("bad immediate value for offset (%ld)"),
20042 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20043 newval
&= 0xff7ff000;
20044 newval
|= value
| (sign
? INDEX_UP
: 0);
20045 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20048 case BFD_RELOC_ARM_OFFSET_IMM8
:
20049 case BFD_RELOC_ARM_HWLITERAL
:
20055 if (validate_offset_imm (value
, 1) == FAIL
)
20057 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20058 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20059 _("invalid literal constant: pool needs to be closer"));
20061 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20066 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20067 newval
&= 0xff7ff0f0;
20068 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20069 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20072 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20073 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20074 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20075 _("bad immediate value for offset (%ld)"), (long) value
);
20078 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20080 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20083 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20084 /* This is a complicated relocation used for all varieties of Thumb32
20085 load/store instruction with immediate offset:
20087 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20088 *4, optional writeback(W)
20089 (doubleword load/store)
20091 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20092 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20093 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20094 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20095 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20097 Uppercase letters indicate bits that are already encoded at
20098 this point. Lowercase letters are our problem. For the
20099 second block of instructions, the secondary opcode nybble
20100 (bits 8..11) is present, and bit 23 is zero, even if this is
20101 a PC-relative operation. */
20102 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20104 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20106 if ((newval
& 0xf0000000) == 0xe0000000)
20108 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20110 newval
|= (1 << 23);
20113 if (value
% 4 != 0)
20115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20116 _("offset not a multiple of 4"));
20122 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20123 _("offset out of range"));
20128 else if ((newval
& 0x000f0000) == 0x000f0000)
20130 /* PC-relative, 12-bit offset. */
20132 newval
|= (1 << 23);
20137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20138 _("offset out of range"));
20143 else if ((newval
& 0x00000100) == 0x00000100)
20145 /* Writeback: 8-bit, +/- offset. */
20147 newval
|= (1 << 9);
20152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20153 _("offset out of range"));
20158 else if ((newval
& 0x00000f00) == 0x00000e00)
20160 /* T-instruction: positive 8-bit offset. */
20161 if (value
< 0 || value
> 0xff)
20163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20164 _("offset out of range"));
20172 /* Positive 12-bit or negative 8-bit offset. */
20176 newval
|= (1 << 23);
20186 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20187 _("offset out of range"));
20194 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20195 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20198 case BFD_RELOC_ARM_SHIFT_IMM
:
20199 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20200 if (((unsigned long) value
) > 32
20202 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20205 _("shift expression is too large"));
20210 /* Shifts of zero must be done as lsl. */
20212 else if (value
== 32)
20214 newval
&= 0xfffff07f;
20215 newval
|= (value
& 0x1f) << 7;
20216 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20219 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20220 case BFD_RELOC_ARM_T32_ADD_IMM
:
20221 case BFD_RELOC_ARM_T32_IMM12
:
20222 case BFD_RELOC_ARM_T32_ADD_PC12
:
20223 /* We claim that this fixup has been processed here,
20224 even if in fact we generate an error because we do
20225 not have a reloc for it, so tc_gen_reloc will reject it. */
20229 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20231 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20232 _("undefined symbol %s used as an immediate value"),
20233 S_GET_NAME (fixP
->fx_addsy
));
20237 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20239 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20242 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20243 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20245 newimm
= encode_thumb32_immediate (value
);
20246 if (newimm
== (unsigned int) FAIL
)
20247 newimm
= thumb32_negate_data_op (&newval
, value
);
20249 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20250 && newimm
== (unsigned int) FAIL
)
20252 /* Turn add/sum into addw/subw. */
20253 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20254 newval
= (newval
& 0xfeffffff) | 0x02000000;
20256 /* 12 bit immediate for addw/subw. */
20260 newval
^= 0x00a00000;
20263 newimm
= (unsigned int) FAIL
;
20268 if (newimm
== (unsigned int)FAIL
)
20270 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20271 _("invalid constant (%lx) after fixup"),
20272 (unsigned long) value
);
20276 newval
|= (newimm
& 0x800) << 15;
20277 newval
|= (newimm
& 0x700) << 4;
20278 newval
|= (newimm
& 0x0ff);
20280 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20281 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20284 case BFD_RELOC_ARM_SMC
:
20285 if (((unsigned long) value
) > 0xffff)
20286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20287 _("invalid smc expression"));
20288 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20289 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20290 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20293 case BFD_RELOC_ARM_SWI
:
20294 if (fixP
->tc_fix_data
!= 0)
20296 if (((unsigned long) value
) > 0xff)
20297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20298 _("invalid swi expression"));
20299 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20301 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20305 if (((unsigned long) value
) > 0x00ffffff)
20306 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20307 _("invalid swi expression"));
20308 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20310 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20314 case BFD_RELOC_ARM_MULTI
:
20315 if (((unsigned long) value
) > 0xffff)
20316 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20317 _("invalid expression in load/store multiple"));
20318 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20319 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20323 case BFD_RELOC_ARM_PCREL_CALL
:
20325 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20327 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20328 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20329 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20330 /* Flip the bl to blx. This is a simple flip
20331 bit here because we generate PCREL_CALL for
20332 unconditional bls. */
20334 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20335 newval
= newval
| 0x10000000;
20336 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20342 goto arm_branch_common
;
20344 case BFD_RELOC_ARM_PCREL_JUMP
:
20345 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20347 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20348 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20349 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20351 /* This would map to a bl<cond>, b<cond>,
20352 b<always> to a Thumb function. We
20353 need to force a relocation for this particular
20355 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20359 case BFD_RELOC_ARM_PLT32
:
20361 case BFD_RELOC_ARM_PCREL_BRANCH
:
20363 goto arm_branch_common
;
20365 case BFD_RELOC_ARM_PCREL_BLX
:
20368 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20370 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20371 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20372 && ARM_IS_FUNC (fixP
->fx_addsy
))
20374 /* Flip the blx to a bl and warn. */
20375 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20376 newval
= 0xeb000000;
20377 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20378 _("blx to '%s' an ARM ISA state function changed to bl"),
20380 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20386 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20387 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20391 /* We are going to store value (shifted right by two) in the
20392 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20393 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20394 also be be clear. */
20396 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20397 _("misaligned branch destination"));
20398 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20399 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20401 _("branch out of range"));
20403 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20405 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20406 newval
|= (value
>> 2) & 0x00ffffff;
20407 /* Set the H bit on BLX instructions. */
20411 newval
|= 0x01000000;
20413 newval
&= ~0x01000000;
20415 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20419 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20420 /* CBZ can only branch forward. */
20422 /* Attempts to use CBZ to branch to the next instruction
20423 (which, strictly speaking, are prohibited) will be turned into
20426 FIXME: It may be better to remove the instruction completely and
20427 perform relaxation. */
20430 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20431 newval
= 0xbf00; /* NOP encoding T1 */
20432 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20438 _("branch out of range"));
20440 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20442 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20443 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20444 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20449 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20450 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20451 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20452 _("branch out of range"));
20454 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20456 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20457 newval
|= (value
& 0x1ff) >> 1;
20458 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20462 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20463 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20464 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20465 _("branch out of range"));
20467 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20469 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20470 newval
|= (value
& 0xfff) >> 1;
20471 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20475 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20477 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20478 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20479 && S_IS_DEFINED (fixP
->fx_addsy
)
20480 && ARM_IS_FUNC (fixP
->fx_addsy
)
20481 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20483 /* Force a relocation for a branch 20 bits wide. */
20486 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20488 _("conditional branch out of range"));
20490 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20493 addressT S
, J1
, J2
, lo
, hi
;
20495 S
= (value
& 0x00100000) >> 20;
20496 J2
= (value
& 0x00080000) >> 19;
20497 J1
= (value
& 0x00040000) >> 18;
20498 hi
= (value
& 0x0003f000) >> 12;
20499 lo
= (value
& 0x00000ffe) >> 1;
20501 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20502 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20503 newval
|= (S
<< 10) | hi
;
20504 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20505 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20506 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20510 case BFD_RELOC_THUMB_PCREL_BLX
:
20512 /* If there is a blx from a thumb state function to
20513 another thumb function flip this to a bl and warn
20517 && S_IS_DEFINED (fixP
->fx_addsy
)
20518 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20519 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20520 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20522 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20523 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20524 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20526 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20527 newval
= newval
| 0x1000;
20528 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20529 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20534 goto thumb_bl_common
;
20536 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20538 /* A bl from Thumb state ISA to an internal ARM state function
20539 is converted to a blx. */
20541 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20542 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20543 && S_IS_DEFINED (fixP
->fx_addsy
)
20544 && ARM_IS_FUNC (fixP
->fx_addsy
)
20545 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20547 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20548 newval
= newval
& ~0x1000;
20549 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20550 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20557 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20558 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20559 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20562 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20563 /* For a BLX instruction, make sure that the relocation is rounded up
20564 to a word boundary. This follows the semantics of the instruction
20565 which specifies that bit 1 of the target address will come from bit
20566 1 of the base address. */
20567 value
= (value
+ 1) & ~ 1;
20570 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20572 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20575 _("branch out of range"));
20577 else if ((value
& ~0x1ffffff)
20578 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20581 _("Thumb2 branch out of range"));
20585 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20586 encode_thumb2_b_bl_offset (buf
, value
);
20590 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20591 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20592 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20593 _("branch out of range"));
20595 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20596 encode_thumb2_b_bl_offset (buf
, value
);
20601 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20602 md_number_to_chars (buf
, value
, 1);
20606 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20607 md_number_to_chars (buf
, value
, 2);
20611 case BFD_RELOC_ARM_TLS_GD32
:
20612 case BFD_RELOC_ARM_TLS_LE32
:
20613 case BFD_RELOC_ARM_TLS_IE32
:
20614 case BFD_RELOC_ARM_TLS_LDM32
:
20615 case BFD_RELOC_ARM_TLS_LDO32
:
20616 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20619 case BFD_RELOC_ARM_GOT32
:
20620 case BFD_RELOC_ARM_GOTOFF
:
20621 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20622 md_number_to_chars (buf
, 0, 4);
20625 case BFD_RELOC_ARM_GOT_PREL
:
20626 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20627 md_number_to_chars (buf
, value
, 4);
20630 case BFD_RELOC_ARM_TARGET2
:
20631 /* TARGET2 is not partial-inplace, so we need to write the
20632 addend here for REL targets, because it won't be written out
20633 during reloc processing later. */
20634 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20635 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20639 case BFD_RELOC_RVA
:
20641 case BFD_RELOC_ARM_TARGET1
:
20642 case BFD_RELOC_ARM_ROSEGREL32
:
20643 case BFD_RELOC_ARM_SBREL32
:
20644 case BFD_RELOC_32_PCREL
:
20646 case BFD_RELOC_32_SECREL
:
20648 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20650 /* For WinCE we only do this for pcrel fixups. */
20651 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20653 md_number_to_chars (buf
, value
, 4);
20657 case BFD_RELOC_ARM_PREL31
:
20658 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20660 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20661 if ((value
^ (value
>> 1)) & 0x40000000)
20663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20664 _("rel31 relocation overflow"));
20666 newval
|= value
& 0x7fffffff;
20667 md_number_to_chars (buf
, newval
, 4);
20672 case BFD_RELOC_ARM_CP_OFF_IMM
:
20673 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20674 if (value
< -1023 || value
> 1023 || (value
& 3))
20675 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20676 _("co-processor offset out of range"));
20681 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20682 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20683 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20685 newval
= get_thumb32_insn (buf
);
20686 newval
&= 0xff7fff00;
20687 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20688 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20689 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20690 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20692 put_thumb32_insn (buf
, newval
);
20695 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20696 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20697 if (value
< -255 || value
> 255)
20698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20699 _("co-processor offset out of range"));
20701 goto cp_off_common
;
20703 case BFD_RELOC_ARM_THUMB_OFFSET
:
20704 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20705 /* Exactly what ranges, and where the offset is inserted depends
20706 on the type of instruction, we can establish this from the
20708 switch (newval
>> 12)
20710 case 4: /* PC load. */
20711 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20712 forced to zero for these loads; md_pcrel_from has already
20713 compensated for this. */
20715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20716 _("invalid offset, target not word aligned (0x%08lX)"),
20717 (((unsigned long) fixP
->fx_frag
->fr_address
20718 + (unsigned long) fixP
->fx_where
) & ~3)
20719 + (unsigned long) value
);
20721 if (value
& ~0x3fc)
20722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20723 _("invalid offset, value too big (0x%08lX)"),
20726 newval
|= value
>> 2;
20729 case 9: /* SP load/store. */
20730 if (value
& ~0x3fc)
20731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20732 _("invalid offset, value too big (0x%08lX)"),
20734 newval
|= value
>> 2;
20737 case 6: /* Word load/store. */
20739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20740 _("invalid offset, value too big (0x%08lX)"),
20742 newval
|= value
<< 4; /* 6 - 2. */
20745 case 7: /* Byte load/store. */
20747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20748 _("invalid offset, value too big (0x%08lX)"),
20750 newval
|= value
<< 6;
20753 case 8: /* Halfword load/store. */
20755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20756 _("invalid offset, value too big (0x%08lX)"),
20758 newval
|= value
<< 5; /* 6 - 1. */
20762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20763 "Unable to process relocation for thumb opcode: %lx",
20764 (unsigned long) newval
);
20767 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20770 case BFD_RELOC_ARM_THUMB_ADD
:
20771 /* This is a complicated relocation, since we use it for all of
20772 the following immediate relocations:
20776 9bit ADD/SUB SP word-aligned
20777 10bit ADD PC/SP word-aligned
20779 The type of instruction being processed is encoded in the
20786 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20788 int rd
= (newval
>> 4) & 0xf;
20789 int rs
= newval
& 0xf;
20790 int subtract
= !!(newval
& 0x8000);
20792 /* Check for HI regs, only very restricted cases allowed:
20793 Adjusting SP, and using PC or SP to get an address. */
20794 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20795 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20797 _("invalid Hi register with immediate"));
20799 /* If value is negative, choose the opposite instruction. */
20803 subtract
= !subtract
;
20805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20806 _("immediate value out of range"));
20811 if (value
& ~0x1fc)
20812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20813 _("invalid immediate for stack address calculation"));
20814 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20815 newval
|= value
>> 2;
20817 else if (rs
== REG_PC
|| rs
== REG_SP
)
20819 if (subtract
|| value
& ~0x3fc)
20820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20821 _("invalid immediate for address calculation (value = 0x%08lX)"),
20822 (unsigned long) value
);
20823 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20825 newval
|= value
>> 2;
20830 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20831 _("immediate value out of range"));
20832 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20833 newval
|= (rd
<< 8) | value
;
20838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20839 _("immediate value out of range"));
20840 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20841 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20844 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20847 case BFD_RELOC_ARM_THUMB_IMM
:
20848 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20849 if (value
< 0 || value
> 255)
20850 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20851 _("invalid immediate: %ld is out of range"),
20854 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20857 case BFD_RELOC_ARM_THUMB_SHIFT
:
20858 /* 5bit shift value (0..32). LSL cannot take 32. */
20859 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20860 temp
= newval
& 0xf800;
20861 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20862 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20863 _("invalid shift value: %ld"), (long) value
);
20864 /* Shifts of zero must be encoded as LSL. */
20866 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20867 /* Shifts of 32 are encoded as zero. */
20868 else if (value
== 32)
20870 newval
|= value
<< 6;
20871 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20874 case BFD_RELOC_VTABLE_INHERIT
:
20875 case BFD_RELOC_VTABLE_ENTRY
:
20879 case BFD_RELOC_ARM_MOVW
:
20880 case BFD_RELOC_ARM_MOVT
:
20881 case BFD_RELOC_ARM_THUMB_MOVW
:
20882 case BFD_RELOC_ARM_THUMB_MOVT
:
20883 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20885 /* REL format relocations are limited to a 16-bit addend. */
20886 if (!fixP
->fx_done
)
20888 if (value
< -0x8000 || value
> 0x7fff)
20889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20890 _("offset out of range"));
20892 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20893 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20898 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20899 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20901 newval
= get_thumb32_insn (buf
);
20902 newval
&= 0xfbf08f00;
20903 newval
|= (value
& 0xf000) << 4;
20904 newval
|= (value
& 0x0800) << 15;
20905 newval
|= (value
& 0x0700) << 4;
20906 newval
|= (value
& 0x00ff);
20907 put_thumb32_insn (buf
, newval
);
20911 newval
= md_chars_to_number (buf
, 4);
20912 newval
&= 0xfff0f000;
20913 newval
|= value
& 0x0fff;
20914 newval
|= (value
& 0xf000) << 4;
20915 md_number_to_chars (buf
, newval
, 4);
20920 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20921 case BFD_RELOC_ARM_ALU_PC_G0
:
20922 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20923 case BFD_RELOC_ARM_ALU_PC_G1
:
20924 case BFD_RELOC_ARM_ALU_PC_G2
:
20925 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20926 case BFD_RELOC_ARM_ALU_SB_G0
:
20927 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20928 case BFD_RELOC_ARM_ALU_SB_G1
:
20929 case BFD_RELOC_ARM_ALU_SB_G2
:
20930 gas_assert (!fixP
->fx_done
);
20931 if (!seg
->use_rela_p
)
20934 bfd_vma encoded_addend
;
20935 bfd_vma addend_abs
= abs (value
);
20937 /* Check that the absolute value of the addend can be
20938 expressed as an 8-bit constant plus a rotation. */
20939 encoded_addend
= encode_arm_immediate (addend_abs
);
20940 if (encoded_addend
== (unsigned int) FAIL
)
20941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20942 _("the offset 0x%08lX is not representable"),
20943 (unsigned long) addend_abs
);
20945 /* Extract the instruction. */
20946 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20948 /* If the addend is positive, use an ADD instruction.
20949 Otherwise use a SUB. Take care not to destroy the S bit. */
20950 insn
&= 0xff1fffff;
20956 /* Place the encoded addend into the first 12 bits of the
20958 insn
&= 0xfffff000;
20959 insn
|= encoded_addend
;
20961 /* Update the instruction. */
20962 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20966 case BFD_RELOC_ARM_LDR_PC_G0
:
20967 case BFD_RELOC_ARM_LDR_PC_G1
:
20968 case BFD_RELOC_ARM_LDR_PC_G2
:
20969 case BFD_RELOC_ARM_LDR_SB_G0
:
20970 case BFD_RELOC_ARM_LDR_SB_G1
:
20971 case BFD_RELOC_ARM_LDR_SB_G2
:
20972 gas_assert (!fixP
->fx_done
);
20973 if (!seg
->use_rela_p
)
20976 bfd_vma addend_abs
= abs (value
);
20978 /* Check that the absolute value of the addend can be
20979 encoded in 12 bits. */
20980 if (addend_abs
>= 0x1000)
20981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20982 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20983 (unsigned long) addend_abs
);
20985 /* Extract the instruction. */
20986 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20988 /* If the addend is negative, clear bit 23 of the instruction.
20989 Otherwise set it. */
20991 insn
&= ~(1 << 23);
20995 /* Place the absolute value of the addend into the first 12 bits
20996 of the instruction. */
20997 insn
&= 0xfffff000;
20998 insn
|= addend_abs
;
21000 /* Update the instruction. */
21001 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21005 case BFD_RELOC_ARM_LDRS_PC_G0
:
21006 case BFD_RELOC_ARM_LDRS_PC_G1
:
21007 case BFD_RELOC_ARM_LDRS_PC_G2
:
21008 case BFD_RELOC_ARM_LDRS_SB_G0
:
21009 case BFD_RELOC_ARM_LDRS_SB_G1
:
21010 case BFD_RELOC_ARM_LDRS_SB_G2
:
21011 gas_assert (!fixP
->fx_done
);
21012 if (!seg
->use_rela_p
)
21015 bfd_vma addend_abs
= abs (value
);
21017 /* Check that the absolute value of the addend can be
21018 encoded in 8 bits. */
21019 if (addend_abs
>= 0x100)
21020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21021 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21022 (unsigned long) addend_abs
);
21024 /* Extract the instruction. */
21025 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21027 /* If the addend is negative, clear bit 23 of the instruction.
21028 Otherwise set it. */
21030 insn
&= ~(1 << 23);
21034 /* Place the first four bits of the absolute value of the addend
21035 into the first 4 bits of the instruction, and the remaining
21036 four into bits 8 .. 11. */
21037 insn
&= 0xfffff0f0;
21038 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21040 /* Update the instruction. */
21041 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21045 case BFD_RELOC_ARM_LDC_PC_G0
:
21046 case BFD_RELOC_ARM_LDC_PC_G1
:
21047 case BFD_RELOC_ARM_LDC_PC_G2
:
21048 case BFD_RELOC_ARM_LDC_SB_G0
:
21049 case BFD_RELOC_ARM_LDC_SB_G1
:
21050 case BFD_RELOC_ARM_LDC_SB_G2
:
21051 gas_assert (!fixP
->fx_done
);
21052 if (!seg
->use_rela_p
)
21055 bfd_vma addend_abs
= abs (value
);
21057 /* Check that the absolute value of the addend is a multiple of
21058 four and, when divided by four, fits in 8 bits. */
21059 if (addend_abs
& 0x3)
21060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21061 _("bad offset 0x%08lX (must be word-aligned)"),
21062 (unsigned long) addend_abs
);
21064 if ((addend_abs
>> 2) > 0xff)
21065 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21066 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21067 (unsigned long) addend_abs
);
21069 /* Extract the instruction. */
21070 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21072 /* If the addend is negative, clear bit 23 of the instruction.
21073 Otherwise set it. */
21075 insn
&= ~(1 << 23);
21079 /* Place the addend (divided by four) into the first eight
21080 bits of the instruction. */
21081 insn
&= 0xfffffff0;
21082 insn
|= addend_abs
>> 2;
21084 /* Update the instruction. */
21085 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21089 case BFD_RELOC_ARM_V4BX
:
21090 /* This will need to go in the object file. */
21094 case BFD_RELOC_UNUSED
:
21096 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21097 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21101 /* Translate internal representation of relocation info to BFD target
21105 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21108 bfd_reloc_code_real_type code
;
21110 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21112 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21113 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21114 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21116 if (fixp
->fx_pcrel
)
21118 if (section
->use_rela_p
)
21119 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21121 fixp
->fx_offset
= reloc
->address
;
21123 reloc
->addend
= fixp
->fx_offset
;
21125 switch (fixp
->fx_r_type
)
21128 if (fixp
->fx_pcrel
)
21130 code
= BFD_RELOC_8_PCREL
;
21135 if (fixp
->fx_pcrel
)
21137 code
= BFD_RELOC_16_PCREL
;
21142 if (fixp
->fx_pcrel
)
21144 code
= BFD_RELOC_32_PCREL
;
21148 case BFD_RELOC_ARM_MOVW
:
21149 if (fixp
->fx_pcrel
)
21151 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21155 case BFD_RELOC_ARM_MOVT
:
21156 if (fixp
->fx_pcrel
)
21158 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21162 case BFD_RELOC_ARM_THUMB_MOVW
:
21163 if (fixp
->fx_pcrel
)
21165 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21169 case BFD_RELOC_ARM_THUMB_MOVT
:
21170 if (fixp
->fx_pcrel
)
21172 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21176 case BFD_RELOC_NONE
:
21177 case BFD_RELOC_ARM_PCREL_BRANCH
:
21178 case BFD_RELOC_ARM_PCREL_BLX
:
21179 case BFD_RELOC_RVA
:
21180 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21181 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21182 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21183 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21184 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21185 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21186 case BFD_RELOC_VTABLE_ENTRY
:
21187 case BFD_RELOC_VTABLE_INHERIT
:
21189 case BFD_RELOC_32_SECREL
:
21191 code
= fixp
->fx_r_type
;
21194 case BFD_RELOC_THUMB_PCREL_BLX
:
21196 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21197 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21200 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21203 case BFD_RELOC_ARM_LITERAL
:
21204 case BFD_RELOC_ARM_HWLITERAL
:
21205 /* If this is called then the a literal has
21206 been referenced across a section boundary. */
21207 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21208 _("literal referenced across section boundary"));
21212 case BFD_RELOC_ARM_GOT32
:
21213 case BFD_RELOC_ARM_GOTOFF
:
21214 case BFD_RELOC_ARM_GOT_PREL
:
21215 case BFD_RELOC_ARM_PLT32
:
21216 case BFD_RELOC_ARM_TARGET1
:
21217 case BFD_RELOC_ARM_ROSEGREL32
:
21218 case BFD_RELOC_ARM_SBREL32
:
21219 case BFD_RELOC_ARM_PREL31
:
21220 case BFD_RELOC_ARM_TARGET2
:
21221 case BFD_RELOC_ARM_TLS_LE32
:
21222 case BFD_RELOC_ARM_TLS_LDO32
:
21223 case BFD_RELOC_ARM_PCREL_CALL
:
21224 case BFD_RELOC_ARM_PCREL_JUMP
:
21225 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21226 case BFD_RELOC_ARM_ALU_PC_G0
:
21227 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21228 case BFD_RELOC_ARM_ALU_PC_G1
:
21229 case BFD_RELOC_ARM_ALU_PC_G2
:
21230 case BFD_RELOC_ARM_LDR_PC_G0
:
21231 case BFD_RELOC_ARM_LDR_PC_G1
:
21232 case BFD_RELOC_ARM_LDR_PC_G2
:
21233 case BFD_RELOC_ARM_LDRS_PC_G0
:
21234 case BFD_RELOC_ARM_LDRS_PC_G1
:
21235 case BFD_RELOC_ARM_LDRS_PC_G2
:
21236 case BFD_RELOC_ARM_LDC_PC_G0
:
21237 case BFD_RELOC_ARM_LDC_PC_G1
:
21238 case BFD_RELOC_ARM_LDC_PC_G2
:
21239 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21240 case BFD_RELOC_ARM_ALU_SB_G0
:
21241 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21242 case BFD_RELOC_ARM_ALU_SB_G1
:
21243 case BFD_RELOC_ARM_ALU_SB_G2
:
21244 case BFD_RELOC_ARM_LDR_SB_G0
:
21245 case BFD_RELOC_ARM_LDR_SB_G1
:
21246 case BFD_RELOC_ARM_LDR_SB_G2
:
21247 case BFD_RELOC_ARM_LDRS_SB_G0
:
21248 case BFD_RELOC_ARM_LDRS_SB_G1
:
21249 case BFD_RELOC_ARM_LDRS_SB_G2
:
21250 case BFD_RELOC_ARM_LDC_SB_G0
:
21251 case BFD_RELOC_ARM_LDC_SB_G1
:
21252 case BFD_RELOC_ARM_LDC_SB_G2
:
21253 case BFD_RELOC_ARM_V4BX
:
21254 code
= fixp
->fx_r_type
;
21257 case BFD_RELOC_ARM_TLS_GD32
:
21258 case BFD_RELOC_ARM_TLS_IE32
:
21259 case BFD_RELOC_ARM_TLS_LDM32
:
21260 /* BFD will include the symbol's address in the addend.
21261 But we don't want that, so subtract it out again here. */
21262 if (!S_IS_COMMON (fixp
->fx_addsy
))
21263 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21264 code
= fixp
->fx_r_type
;
21268 case BFD_RELOC_ARM_IMMEDIATE
:
21269 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21270 _("internal relocation (type: IMMEDIATE) not fixed up"));
21273 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21274 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21275 _("ADRL used for a symbol not defined in the same file"));
21278 case BFD_RELOC_ARM_OFFSET_IMM
:
21279 if (section
->use_rela_p
)
21281 code
= fixp
->fx_r_type
;
21285 if (fixp
->fx_addsy
!= NULL
21286 && !S_IS_DEFINED (fixp
->fx_addsy
)
21287 && S_IS_LOCAL (fixp
->fx_addsy
))
21289 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21290 _("undefined local label `%s'"),
21291 S_GET_NAME (fixp
->fx_addsy
));
21295 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21296 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21303 switch (fixp
->fx_r_type
)
21305 case BFD_RELOC_NONE
: type
= "NONE"; break;
21306 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21307 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21308 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21309 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21310 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21311 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21312 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21313 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21314 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21315 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21316 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21317 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21318 default: type
= _("<unknown>"); break;
21320 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21321 _("cannot represent %s relocation in this object file format"),
21328 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21330 && fixp
->fx_addsy
== GOT_symbol
)
21332 code
= BFD_RELOC_ARM_GOTPC
;
21333 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21337 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21339 if (reloc
->howto
== NULL
)
21341 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21342 _("cannot represent %s relocation in this object file format"),
21343 bfd_get_reloc_code_name (code
));
21347 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21348 vtable entry to be used in the relocation's section offset. */
21349 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21350 reloc
->address
= fixp
->fx_offset
;
21355 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21358 cons_fix_new_arm (fragS
* frag
,
21363 bfd_reloc_code_real_type type
;
21367 FIXME: @@ Should look at CPU word size. */
21371 type
= BFD_RELOC_8
;
21374 type
= BFD_RELOC_16
;
21378 type
= BFD_RELOC_32
;
21381 type
= BFD_RELOC_64
;
21386 if (exp
->X_op
== O_secrel
)
21388 exp
->X_op
= O_symbol
;
21389 type
= BFD_RELOC_32_SECREL
;
21393 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21396 #if defined (OBJ_COFF)
21398 arm_validate_fix (fixS
* fixP
)
21400 /* If the destination of the branch is a defined symbol which does not have
21401 the THUMB_FUNC attribute, then we must be calling a function which has
21402 the (interfacearm) attribute. We look for the Thumb entry point to that
21403 function and change the branch to refer to that function instead. */
21404 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21405 && fixP
->fx_addsy
!= NULL
21406 && S_IS_DEFINED (fixP
->fx_addsy
)
21407 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21409 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21416 arm_force_relocation (struct fix
* fixp
)
21418 #if defined (OBJ_COFF) && defined (TE_PE)
21419 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21423 /* In case we have a call or a branch to a function in ARM ISA mode from
21424 a thumb function or vice-versa force the relocation. These relocations
21425 are cleared off for some cores that might have blx and simple transformations
21429 switch (fixp
->fx_r_type
)
21431 case BFD_RELOC_ARM_PCREL_JUMP
:
21432 case BFD_RELOC_ARM_PCREL_CALL
:
21433 case BFD_RELOC_THUMB_PCREL_BLX
:
21434 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21438 case BFD_RELOC_ARM_PCREL_BLX
:
21439 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21440 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21441 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21442 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21451 /* Resolve these relocations even if the symbol is extern or weak. */
21452 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21453 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21454 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21455 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21456 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21457 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21458 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21461 /* Always leave these relocations for the linker. */
21462 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21463 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21464 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21467 /* Always generate relocations against function symbols. */
21468 if (fixp
->fx_r_type
== BFD_RELOC_32
21470 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21473 return generic_force_reloc (fixp
);
21476 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21477 /* Relocations against function names must be left unadjusted,
21478 so that the linker can use this information to generate interworking
21479 stubs. The MIPS version of this function
21480 also prevents relocations that are mips-16 specific, but I do not
21481 know why it does this.
21484 There is one other problem that ought to be addressed here, but
21485 which currently is not: Taking the address of a label (rather
21486 than a function) and then later jumping to that address. Such
21487 addresses also ought to have their bottom bit set (assuming that
21488 they reside in Thumb code), but at the moment they will not. */
21491 arm_fix_adjustable (fixS
* fixP
)
21493 if (fixP
->fx_addsy
== NULL
)
21496 /* Preserve relocations against symbols with function type. */
21497 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21500 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21501 && fixP
->fx_subsy
== NULL
)
21504 /* We need the symbol name for the VTABLE entries. */
21505 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21506 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21509 /* Don't allow symbols to be discarded on GOT related relocs. */
21510 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21511 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21512 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21513 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21514 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21515 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21516 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21517 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21518 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21521 /* Similarly for group relocations. */
21522 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21523 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21524 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21527 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21528 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21529 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21530 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21531 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21532 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21533 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21534 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21535 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21540 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21545 elf32_arm_target_format (void)
21548 return (target_big_endian
21549 ? "elf32-bigarm-symbian"
21550 : "elf32-littlearm-symbian");
21551 #elif defined (TE_VXWORKS)
21552 return (target_big_endian
21553 ? "elf32-bigarm-vxworks"
21554 : "elf32-littlearm-vxworks");
21556 if (target_big_endian
)
21557 return "elf32-bigarm";
21559 return "elf32-littlearm";
21564 armelf_frob_symbol (symbolS
* symp
,
21567 elf_frob_symbol (symp
, puntp
);
21571 /* MD interface: Finalization. */
21576 literal_pool
* pool
;
21578 /* Ensure that all the IT blocks are properly closed. */
21579 check_it_blocks_finished ();
21581 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21583 /* Put it at the end of the relevant section. */
21584 subseg_set (pool
->section
, pool
->sub_section
);
21586 arm_elf_change_section ();
21593 /* Remove any excess mapping symbols generated for alignment frags in
21594 SEC. We may have created a mapping symbol before a zero byte
21595 alignment; remove it if there's a mapping symbol after the
21598 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21599 void *dummy ATTRIBUTE_UNUSED
)
21601 segment_info_type
*seginfo
= seg_info (sec
);
21604 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21607 for (fragp
= seginfo
->frchainP
->frch_root
;
21609 fragp
= fragp
->fr_next
)
21611 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21612 fragS
*next
= fragp
->fr_next
;
21614 /* Variable-sized frags have been converted to fixed size by
21615 this point. But if this was variable-sized to start with,
21616 there will be a fixed-size frag after it. So don't handle
21618 if (sym
== NULL
|| next
== NULL
)
21621 if (S_GET_VALUE (sym
) < next
->fr_address
)
21622 /* Not at the end of this frag. */
21624 know (S_GET_VALUE (sym
) == next
->fr_address
);
21628 if (next
->tc_frag_data
.first_map
!= NULL
)
21630 /* Next frag starts with a mapping symbol. Discard this
21632 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21636 if (next
->fr_next
== NULL
)
21638 /* This mapping symbol is at the end of the section. Discard
21640 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21641 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21645 /* As long as we have empty frags without any mapping symbols,
21647 /* If the next frag is non-empty and does not start with a
21648 mapping symbol, then this mapping symbol is required. */
21649 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21652 next
= next
->fr_next
;
21654 while (next
!= NULL
);
21659 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21663 arm_adjust_symtab (void)
21668 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21670 if (ARM_IS_THUMB (sym
))
21672 if (THUMB_IS_FUNC (sym
))
21674 /* Mark the symbol as a Thumb function. */
21675 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21676 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21677 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21679 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21680 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21682 as_bad (_("%s: unexpected function type: %d"),
21683 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21685 else switch (S_GET_STORAGE_CLASS (sym
))
21688 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21691 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21694 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21702 if (ARM_IS_INTERWORK (sym
))
21703 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21710 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21712 if (ARM_IS_THUMB (sym
))
21714 elf_symbol_type
* elf_sym
;
21716 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21717 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21719 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21720 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21722 /* If it's a .thumb_func, declare it as so,
21723 otherwise tag label as .code 16. */
21724 if (THUMB_IS_FUNC (sym
))
21725 elf_sym
->internal_elf_sym
.st_info
=
21726 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21727 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21728 elf_sym
->internal_elf_sym
.st_info
=
21729 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21734 /* Remove any overlapping mapping symbols generated by alignment frags. */
21735 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21739 /* MD interface: Initialization. */
21742 set_constant_flonums (void)
21746 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21747 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21751 /* Auto-select Thumb mode if it's the only available instruction set for the
21752 given architecture. */
21755 autoselect_thumb_from_cpu_variant (void)
21757 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21758 opcode_select (16);
21767 if ( (arm_ops_hsh
= hash_new ()) == NULL
21768 || (arm_cond_hsh
= hash_new ()) == NULL
21769 || (arm_shift_hsh
= hash_new ()) == NULL
21770 || (arm_psr_hsh
= hash_new ()) == NULL
21771 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21772 || (arm_reg_hsh
= hash_new ()) == NULL
21773 || (arm_reloc_hsh
= hash_new ()) == NULL
21774 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21775 as_fatal (_("virtual memory exhausted"));
21777 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21778 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21779 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21780 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21781 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21782 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21783 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21784 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21785 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21786 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21787 (void *) (v7m_psrs
+ i
));
21788 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21789 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21791 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21793 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21794 (void *) (barrier_opt_names
+ i
));
21796 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21797 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21800 set_constant_flonums ();
21802 /* Set the cpu variant based on the command-line options. We prefer
21803 -mcpu= over -march= if both are set (as for GCC); and we prefer
21804 -mfpu= over any other way of setting the floating point unit.
21805 Use of legacy options with new options are faulted. */
21808 if (mcpu_cpu_opt
|| march_cpu_opt
)
21809 as_bad (_("use of old and new-style options to set CPU type"));
21811 mcpu_cpu_opt
= legacy_cpu
;
21813 else if (!mcpu_cpu_opt
)
21814 mcpu_cpu_opt
= march_cpu_opt
;
21819 as_bad (_("use of old and new-style options to set FPU type"));
21821 mfpu_opt
= legacy_fpu
;
21823 else if (!mfpu_opt
)
21825 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21826 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21827 /* Some environments specify a default FPU. If they don't, infer it
21828 from the processor. */
21830 mfpu_opt
= mcpu_fpu_opt
;
21832 mfpu_opt
= march_fpu_opt
;
21834 mfpu_opt
= &fpu_default
;
21840 if (mcpu_cpu_opt
!= NULL
)
21841 mfpu_opt
= &fpu_default
;
21842 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21843 mfpu_opt
= &fpu_arch_vfp_v2
;
21845 mfpu_opt
= &fpu_arch_fpa
;
21851 mcpu_cpu_opt
= &cpu_default
;
21852 selected_cpu
= cpu_default
;
21856 selected_cpu
= *mcpu_cpu_opt
;
21858 mcpu_cpu_opt
= &arm_arch_any
;
21861 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21863 autoselect_thumb_from_cpu_variant ();
21865 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21867 #if defined OBJ_COFF || defined OBJ_ELF
21869 unsigned int flags
= 0;
21871 #if defined OBJ_ELF
21872 flags
= meabi_flags
;
21874 switch (meabi_flags
)
21876 case EF_ARM_EABI_UNKNOWN
:
21878 /* Set the flags in the private structure. */
21879 if (uses_apcs_26
) flags
|= F_APCS26
;
21880 if (support_interwork
) flags
|= F_INTERWORK
;
21881 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21882 if (pic_code
) flags
|= F_PIC
;
21883 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21884 flags
|= F_SOFT_FLOAT
;
21886 switch (mfloat_abi_opt
)
21888 case ARM_FLOAT_ABI_SOFT
:
21889 case ARM_FLOAT_ABI_SOFTFP
:
21890 flags
|= F_SOFT_FLOAT
;
21893 case ARM_FLOAT_ABI_HARD
:
21894 if (flags
& F_SOFT_FLOAT
)
21895 as_bad (_("hard-float conflicts with specified fpu"));
21899 /* Using pure-endian doubles (even if soft-float). */
21900 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21901 flags
|= F_VFP_FLOAT
;
21903 #if defined OBJ_ELF
21904 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21905 flags
|= EF_ARM_MAVERICK_FLOAT
;
21908 case EF_ARM_EABI_VER4
:
21909 case EF_ARM_EABI_VER5
:
21910 /* No additional flags to set. */
21917 bfd_set_private_flags (stdoutput
, flags
);
21919 /* We have run out flags in the COFF header to encode the
21920 status of ATPCS support, so instead we create a dummy,
21921 empty, debug section called .arm.atpcs. */
21926 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21930 bfd_set_section_flags
21931 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21932 bfd_set_section_size (stdoutput
, sec
, 0);
21933 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21939 /* Record the CPU type as well. */
21940 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21941 mach
= bfd_mach_arm_iWMMXt2
;
21942 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21943 mach
= bfd_mach_arm_iWMMXt
;
21944 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21945 mach
= bfd_mach_arm_XScale
;
21946 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21947 mach
= bfd_mach_arm_ep9312
;
21948 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21949 mach
= bfd_mach_arm_5TE
;
21950 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21952 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21953 mach
= bfd_mach_arm_5T
;
21955 mach
= bfd_mach_arm_5
;
21957 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21959 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21960 mach
= bfd_mach_arm_4T
;
21962 mach
= bfd_mach_arm_4
;
21964 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21965 mach
= bfd_mach_arm_3M
;
21966 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21967 mach
= bfd_mach_arm_3
;
21968 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21969 mach
= bfd_mach_arm_2a
;
21970 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21971 mach
= bfd_mach_arm_2
;
21973 mach
= bfd_mach_arm_unknown
;
21975 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21978 /* Command line processing. */
21981 Invocation line includes a switch not recognized by the base assembler.
21982 See if it's a processor-specific option.
21984 This routine is somewhat complicated by the need for backwards
21985 compatibility (since older releases of gcc can't be changed).
21986 The new options try to make the interface as compatible as
21989 New options (supported) are:
21991 -mcpu=<cpu name> Assemble for selected processor
21992 -march=<architecture name> Assemble for selected architecture
21993 -mfpu=<fpu architecture> Assemble for selected FPU.
21994 -EB/-mbig-endian Big-endian
21995 -EL/-mlittle-endian Little-endian
21996 -k Generate PIC code
21997 -mthumb Start in Thumb mode
21998 -mthumb-interwork Code supports ARM/Thumb interworking
22000 -m[no-]warn-deprecated Warn about deprecated features
22002 For now we will also provide support for:
22004 -mapcs-32 32-bit Program counter
22005 -mapcs-26 26-bit Program counter
22006 -macps-float Floats passed in FP registers
22007 -mapcs-reentrant Reentrant code
22009 (sometime these will probably be replaced with -mapcs=<list of options>
22010 and -matpcs=<list of options>)
22012 The remaining options are only supported for back-wards compatibility.
22013 Cpu variants, the arm part is optional:
22014 -m[arm]1 Currently not supported.
22015 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22016 -m[arm]3 Arm 3 processor
22017 -m[arm]6[xx], Arm 6 processors
22018 -m[arm]7[xx][t][[d]m] Arm 7 processors
22019 -m[arm]8[10] Arm 8 processors
22020 -m[arm]9[20][tdmi] Arm 9 processors
22021 -mstrongarm[110[0]] StrongARM processors
22022 -mxscale XScale processors
22023 -m[arm]v[2345[t[e]]] Arm architectures
22024 -mall All (except the ARM1)
22026 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22027 -mfpe-old (No float load/store multiples)
22028 -mvfpxd VFP Single precision
22030 -mno-fpu Disable all floating point instructions
22032 The following CPU names are recognized:
22033 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22034 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22035 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22036 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22037 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22038 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22039 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22043 const char * md_shortopts
= "m:k";
22045 #ifdef ARM_BI_ENDIAN
22046 #define OPTION_EB (OPTION_MD_BASE + 0)
22047 #define OPTION_EL (OPTION_MD_BASE + 1)
22049 #if TARGET_BYTES_BIG_ENDIAN
22050 #define OPTION_EB (OPTION_MD_BASE + 0)
22052 #define OPTION_EL (OPTION_MD_BASE + 1)
22055 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22057 struct option md_longopts
[] =
22060 {"EB", no_argument
, NULL
, OPTION_EB
},
22063 {"EL", no_argument
, NULL
, OPTION_EL
},
22065 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22066 {NULL
, no_argument
, NULL
, 0}
22069 size_t md_longopts_size
= sizeof (md_longopts
);
22071 struct arm_option_table
22073 char *option
; /* Option name to match. */
22074 char *help
; /* Help information. */
22075 int *var
; /* Variable to change. */
22076 int value
; /* What to change it to. */
22077 char *deprecated
; /* If non-null, print this message. */
22080 struct arm_option_table arm_opts
[] =
22082 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22083 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22084 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22085 &support_interwork
, 1, NULL
},
22086 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22087 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22088 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22090 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22091 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22092 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22093 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22096 /* These are recognized by the assembler, but have no affect on code. */
22097 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22098 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22100 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22101 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22102 &warn_on_deprecated
, 0, NULL
},
22103 {NULL
, NULL
, NULL
, 0, NULL
}
22106 struct arm_legacy_option_table
22108 char *option
; /* Option name to match. */
22109 const arm_feature_set
**var
; /* Variable to change. */
22110 const arm_feature_set value
; /* What to change it to. */
22111 char *deprecated
; /* If non-null, print this message. */
22114 const struct arm_legacy_option_table arm_legacy_opts
[] =
22116 /* DON'T add any new processors to this list -- we want the whole list
22117 to go away... Add them to the processors table instead. */
22118 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22119 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22120 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22121 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22122 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22123 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22124 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22125 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22126 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22127 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22128 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22129 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22130 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22131 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22132 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22133 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22134 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22135 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22136 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22137 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22138 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22139 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22140 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22141 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22142 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22143 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22144 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22145 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22146 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22147 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22148 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22149 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22150 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22151 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22152 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22153 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22154 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22155 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22156 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22157 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22158 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22159 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22160 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22161 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22162 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22163 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22164 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22165 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22166 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22167 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22168 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22169 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22170 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22171 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22172 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22173 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22174 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22175 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22176 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22177 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22178 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22179 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22180 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22181 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22182 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22183 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22184 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22185 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22186 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22187 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22188 N_("use -mcpu=strongarm110")},
22189 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22190 N_("use -mcpu=strongarm1100")},
22191 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22192 N_("use -mcpu=strongarm1110")},
22193 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22194 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22195 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22197 /* Architecture variants -- don't add any more to this list either. */
22198 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22199 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22200 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22201 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22202 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22203 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22204 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22205 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22206 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22207 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22208 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22209 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22210 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22211 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22212 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22213 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22214 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22215 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22217 /* Floating point variants -- don't add any more to this list either. */
22218 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22219 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22220 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22221 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22222 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22224 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22227 struct arm_cpu_option_table
22230 const arm_feature_set value
;
22231 /* For some CPUs we assume an FPU unless the user explicitly sets
22233 const arm_feature_set default_fpu
;
22234 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22236 const char *canonical_name
;
22239 /* This list should, at a minimum, contain all the cpu names
22240 recognized by GCC. */
22241 static const struct arm_cpu_option_table arm_cpus
[] =
22243 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22244 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22245 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22246 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22247 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22248 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22249 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22250 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22251 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22252 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22253 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22254 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22255 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22256 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22257 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22258 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22259 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22260 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22261 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22262 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22263 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22264 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22265 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22266 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22267 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22268 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22269 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22270 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22271 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22272 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22273 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22274 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22275 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22276 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22277 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22278 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22279 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22280 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22281 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22282 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22283 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22284 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22285 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22286 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22287 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22288 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22289 /* For V5 or later processors we default to using VFP; but the user
22290 should really set the FPU type explicitly. */
22291 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22292 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22293 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22294 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22295 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22296 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22297 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22298 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22299 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22300 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22301 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22302 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22303 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22304 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22305 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22306 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22307 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22308 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22309 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22310 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22311 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22312 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22313 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22314 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22315 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22316 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22317 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22318 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
22319 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
22320 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22321 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22322 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22323 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22324 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
22325 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22326 | FPU_NEON_EXT_V1
),
22328 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22329 | FPU_NEON_EXT_V1
),
22331 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
22332 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
22333 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, NULL
},
22334 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
22335 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22336 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22337 /* ??? XSCALE is really an architecture. */
22338 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22339 /* ??? iwmmxt is not a processor. */
22340 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22341 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22342 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22344 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22345 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22348 struct arm_arch_option_table
22351 const arm_feature_set value
;
22352 const arm_feature_set default_fpu
;
22355 /* This list should, at a minimum, contain all the architecture names
22356 recognized by GCC. */
22357 static const struct arm_arch_option_table arm_archs
[] =
22359 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22360 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22361 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22362 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22363 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22364 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22365 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22366 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22367 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22368 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22369 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22370 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22371 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22372 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22373 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22374 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22375 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22376 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22377 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22378 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22379 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22380 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22381 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22382 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22383 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22384 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22385 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22386 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22387 /* The official spelling of the ARMv7 profile variants is the dashed form.
22388 Accept the non-dashed form for compatibility with old toolchains. */
22389 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22390 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22391 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22392 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22393 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22394 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22395 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22396 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22397 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22398 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22399 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22402 /* ISA extensions in the co-processor space. */
22403 struct arm_option_cpu_value_table
22406 const arm_feature_set value
;
22409 static const struct arm_option_cpu_value_table arm_extensions
[] =
22411 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22412 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22413 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22414 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22415 {NULL
, ARM_ARCH_NONE
}
22418 /* This list should, at a minimum, contain all the fpu names
22419 recognized by GCC. */
22420 static const struct arm_option_cpu_value_table arm_fpus
[] =
22422 {"softfpa", FPU_NONE
},
22423 {"fpe", FPU_ARCH_FPE
},
22424 {"fpe2", FPU_ARCH_FPE
},
22425 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22426 {"fpa", FPU_ARCH_FPA
},
22427 {"fpa10", FPU_ARCH_FPA
},
22428 {"fpa11", FPU_ARCH_FPA
},
22429 {"arm7500fe", FPU_ARCH_FPA
},
22430 {"softvfp", FPU_ARCH_VFP
},
22431 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22432 {"vfp", FPU_ARCH_VFP_V2
},
22433 {"vfp9", FPU_ARCH_VFP_V2
},
22434 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22435 {"vfp10", FPU_ARCH_VFP_V2
},
22436 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22437 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22438 {"vfpv2", FPU_ARCH_VFP_V2
},
22439 {"vfpv3", FPU_ARCH_VFP_V3
},
22440 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22441 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22442 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22443 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22444 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22445 {"arm1020t", FPU_ARCH_VFP_V1
},
22446 {"arm1020e", FPU_ARCH_VFP_V2
},
22447 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22448 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22449 {"maverick", FPU_ARCH_MAVERICK
},
22450 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22451 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22452 {"vfpv4", FPU_ARCH_VFP_V4
},
22453 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22454 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22455 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22456 {NULL
, ARM_ARCH_NONE
}
22459 struct arm_option_value_table
22465 static const struct arm_option_value_table arm_float_abis
[] =
22467 {"hard", ARM_FLOAT_ABI_HARD
},
22468 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22469 {"soft", ARM_FLOAT_ABI_SOFT
},
22474 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22475 static const struct arm_option_value_table arm_eabis
[] =
22477 {"gnu", EF_ARM_EABI_UNKNOWN
},
22478 {"4", EF_ARM_EABI_VER4
},
22479 {"5", EF_ARM_EABI_VER5
},
22484 struct arm_long_option_table
22486 char * option
; /* Substring to match. */
22487 char * help
; /* Help information. */
22488 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22489 char * deprecated
; /* If non-null, print this message. */
22493 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22495 arm_feature_set
*ext_set
= (arm_feature_set
*)
22496 xmalloc (sizeof (arm_feature_set
));
22498 /* Copy the feature set, so that we can modify it. */
22499 *ext_set
= **opt_p
;
22502 while (str
!= NULL
&& *str
!= 0)
22504 const struct arm_option_cpu_value_table
* opt
;
22510 as_bad (_("invalid architectural extension"));
22515 ext
= strchr (str
, '+');
22518 optlen
= ext
- str
;
22520 optlen
= strlen (str
);
22524 as_bad (_("missing architectural extension"));
22528 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22529 if (strncmp (opt
->name
, str
, optlen
) == 0)
22531 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22535 if (opt
->name
== NULL
)
22537 as_bad (_("unknown architectural extension `%s'"), str
);
22548 arm_parse_cpu (char * str
)
22550 const struct arm_cpu_option_table
* opt
;
22551 char * ext
= strchr (str
, '+');
22555 optlen
= ext
- str
;
22557 optlen
= strlen (str
);
22561 as_bad (_("missing cpu name `%s'"), str
);
22565 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22566 if (strncmp (opt
->name
, str
, optlen
) == 0)
22568 mcpu_cpu_opt
= &opt
->value
;
22569 mcpu_fpu_opt
= &opt
->default_fpu
;
22570 if (opt
->canonical_name
)
22571 strcpy (selected_cpu_name
, opt
->canonical_name
);
22576 for (i
= 0; i
< optlen
; i
++)
22577 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22578 selected_cpu_name
[i
] = 0;
22582 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22587 as_bad (_("unknown cpu `%s'"), str
);
22592 arm_parse_arch (char * str
)
22594 const struct arm_arch_option_table
*opt
;
22595 char *ext
= strchr (str
, '+');
22599 optlen
= ext
- str
;
22601 optlen
= strlen (str
);
22605 as_bad (_("missing architecture name `%s'"), str
);
22609 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22610 if (streq (opt
->name
, str
))
22612 march_cpu_opt
= &opt
->value
;
22613 march_fpu_opt
= &opt
->default_fpu
;
22614 strcpy (selected_cpu_name
, opt
->name
);
22617 return arm_parse_extension (ext
, &march_cpu_opt
);
22622 as_bad (_("unknown architecture `%s'\n"), str
);
22627 arm_parse_fpu (char * str
)
22629 const struct arm_option_cpu_value_table
* opt
;
22631 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22632 if (streq (opt
->name
, str
))
22634 mfpu_opt
= &opt
->value
;
22638 as_bad (_("unknown floating point format `%s'\n"), str
);
22643 arm_parse_float_abi (char * str
)
22645 const struct arm_option_value_table
* opt
;
22647 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22648 if (streq (opt
->name
, str
))
22650 mfloat_abi_opt
= opt
->value
;
22654 as_bad (_("unknown floating point abi `%s'\n"), str
);
22660 arm_parse_eabi (char * str
)
22662 const struct arm_option_value_table
*opt
;
22664 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22665 if (streq (opt
->name
, str
))
22667 meabi_flags
= opt
->value
;
22670 as_bad (_("unknown EABI `%s'\n"), str
);
22676 arm_parse_it_mode (char * str
)
22678 bfd_boolean ret
= TRUE
;
22680 if (streq ("arm", str
))
22681 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22682 else if (streq ("thumb", str
))
22683 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22684 else if (streq ("always", str
))
22685 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22686 else if (streq ("never", str
))
22687 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22690 as_bad (_("unknown implicit IT mode `%s', should be "\
22691 "arm, thumb, always, or never."), str
);
22698 struct arm_long_option_table arm_long_opts
[] =
22700 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22701 arm_parse_cpu
, NULL
},
22702 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22703 arm_parse_arch
, NULL
},
22704 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22705 arm_parse_fpu
, NULL
},
22706 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22707 arm_parse_float_abi
, NULL
},
22709 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22710 arm_parse_eabi
, NULL
},
22712 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22713 arm_parse_it_mode
, NULL
},
22714 {NULL
, NULL
, 0, NULL
}
22718 md_parse_option (int c
, char * arg
)
22720 struct arm_option_table
*opt
;
22721 const struct arm_legacy_option_table
*fopt
;
22722 struct arm_long_option_table
*lopt
;
22728 target_big_endian
= 1;
22734 target_big_endian
= 0;
22738 case OPTION_FIX_V4BX
:
22743 /* Listing option. Just ignore these, we don't support additional
22748 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22750 if (c
== opt
->option
[0]
22751 && ((arg
== NULL
&& opt
->option
[1] == 0)
22752 || streq (arg
, opt
->option
+ 1)))
22754 /* If the option is deprecated, tell the user. */
22755 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22756 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22757 arg
? arg
: "", _(opt
->deprecated
));
22759 if (opt
->var
!= NULL
)
22760 *opt
->var
= opt
->value
;
22766 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22768 if (c
== fopt
->option
[0]
22769 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22770 || streq (arg
, fopt
->option
+ 1)))
22772 /* If the option is deprecated, tell the user. */
22773 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22774 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22775 arg
? arg
: "", _(fopt
->deprecated
));
22777 if (fopt
->var
!= NULL
)
22778 *fopt
->var
= &fopt
->value
;
22784 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22786 /* These options are expected to have an argument. */
22787 if (c
== lopt
->option
[0]
22789 && strncmp (arg
, lopt
->option
+ 1,
22790 strlen (lopt
->option
+ 1)) == 0)
22792 /* If the option is deprecated, tell the user. */
22793 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22794 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22795 _(lopt
->deprecated
));
22797 /* Call the sup-option parser. */
22798 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22809 md_show_usage (FILE * fp
)
22811 struct arm_option_table
*opt
;
22812 struct arm_long_option_table
*lopt
;
22814 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22816 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22817 if (opt
->help
!= NULL
)
22818 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22820 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22821 if (lopt
->help
!= NULL
)
22822 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22826 -EB assemble code for a big-endian cpu\n"));
22831 -EL assemble code for a little-endian cpu\n"));
22835 --fix-v4bx Allow BX in ARMv4 code\n"));
22843 arm_feature_set flags
;
22844 } cpu_arch_ver_table
;
22846 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22847 least features first. */
22848 static const cpu_arch_ver_table cpu_arch_ver
[] =
22854 {4, ARM_ARCH_V5TE
},
22855 {5, ARM_ARCH_V5TEJ
},
22859 {11, ARM_ARCH_V6M
},
22860 {8, ARM_ARCH_V6T2
},
22861 {10, ARM_ARCH_V7A
},
22862 {10, ARM_ARCH_V7R
},
22863 {10, ARM_ARCH_V7M
},
22867 /* Set an attribute if it has not already been set by the user. */
22869 aeabi_set_attribute_int (int tag
, int value
)
22872 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22873 || !attributes_set_explicitly
[tag
])
22874 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22878 aeabi_set_attribute_string (int tag
, const char *value
)
22881 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22882 || !attributes_set_explicitly
[tag
])
22883 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22886 /* Set the public EABI object attributes. */
22888 aeabi_set_public_attributes (void)
22891 arm_feature_set flags
;
22892 arm_feature_set tmp
;
22893 const cpu_arch_ver_table
*p
;
22895 /* Choose the architecture based on the capabilities of the requested cpu
22896 (if any) and/or the instructions actually used. */
22897 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22898 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22899 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22900 /*Allow the user to override the reported architecture. */
22903 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22904 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22909 for (p
= cpu_arch_ver
; p
->val
; p
++)
22911 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22914 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22918 /* The table lookup above finds the last architecture to contribute
22919 a new feature. Unfortunately, Tag13 is a subset of the union of
22920 v6T2 and v7-M, so it is never seen as contributing a new feature.
22921 We can not search for the last entry which is entirely used,
22922 because if no CPU is specified we build up only those flags
22923 actually used. Perhaps we should separate out the specified
22924 and implicit cases. Avoid taking this path for -march=all by
22925 checking for contradictory v7-A / v7-M features. */
22927 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22928 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22929 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22932 /* Tag_CPU_name. */
22933 if (selected_cpu_name
[0])
22937 q
= selected_cpu_name
;
22938 if (strncmp (q
, "armv", 4) == 0)
22943 for (i
= 0; q
[i
]; i
++)
22944 q
[i
] = TOUPPER (q
[i
]);
22946 aeabi_set_attribute_string (Tag_CPU_name
, q
);
22949 /* Tag_CPU_arch. */
22950 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22952 /* Tag_CPU_arch_profile. */
22953 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22954 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22955 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22956 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22957 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22958 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22960 /* Tag_ARM_ISA_use. */
22961 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22963 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22965 /* Tag_THUMB_ISA_use. */
22966 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22968 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22969 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22971 /* Tag_VFP_arch. */
22972 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22973 aeabi_set_attribute_int (Tag_VFP_arch
,
22974 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22976 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22977 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22978 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
22979 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22980 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22981 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22982 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22983 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22984 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22986 /* Tag_ABI_HardFP_use. */
22987 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
22988 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
22989 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
22991 /* Tag_WMMX_arch. */
22992 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22993 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22994 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22995 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22997 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22998 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22999 aeabi_set_attribute_int
23000 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23003 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23004 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23005 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23008 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23009 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23010 /* Fill this in when gas supports v7a sdiv/udiv.
23011 else if (... v7a with div extension used ...)
23012 aeabi_set_attribute_int (Tag_DIV_use, 2); */
23014 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23017 /* Add the default contents for the .ARM.attributes section. */
23021 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23024 aeabi_set_public_attributes ();
23026 #endif /* OBJ_ELF */
23029 /* Parse a .cpu directive. */
23032 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23034 const struct arm_cpu_option_table
*opt
;
23038 name
= input_line_pointer
;
23039 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23040 input_line_pointer
++;
23041 saved_char
= *input_line_pointer
;
23042 *input_line_pointer
= 0;
23044 /* Skip the first "all" entry. */
23045 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23046 if (streq (opt
->name
, name
))
23048 mcpu_cpu_opt
= &opt
->value
;
23049 selected_cpu
= opt
->value
;
23050 if (opt
->canonical_name
)
23051 strcpy (selected_cpu_name
, opt
->canonical_name
);
23055 for (i
= 0; opt
->name
[i
]; i
++)
23056 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23057 selected_cpu_name
[i
] = 0;
23059 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23060 *input_line_pointer
= saved_char
;
23061 demand_empty_rest_of_line ();
23064 as_bad (_("unknown cpu `%s'"), name
);
23065 *input_line_pointer
= saved_char
;
23066 ignore_rest_of_line ();
23070 /* Parse a .arch directive. */
23073 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23075 const struct arm_arch_option_table
*opt
;
23079 name
= input_line_pointer
;
23080 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23081 input_line_pointer
++;
23082 saved_char
= *input_line_pointer
;
23083 *input_line_pointer
= 0;
23085 /* Skip the first "all" entry. */
23086 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23087 if (streq (opt
->name
, name
))
23089 mcpu_cpu_opt
= &opt
->value
;
23090 selected_cpu
= opt
->value
;
23091 strcpy (selected_cpu_name
, opt
->name
);
23092 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23093 *input_line_pointer
= saved_char
;
23094 demand_empty_rest_of_line ();
23098 as_bad (_("unknown architecture `%s'\n"), name
);
23099 *input_line_pointer
= saved_char
;
23100 ignore_rest_of_line ();
23104 /* Parse a .object_arch directive. */
23107 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23109 const struct arm_arch_option_table
*opt
;
23113 name
= input_line_pointer
;
23114 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23115 input_line_pointer
++;
23116 saved_char
= *input_line_pointer
;
23117 *input_line_pointer
= 0;
23119 /* Skip the first "all" entry. */
23120 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23121 if (streq (opt
->name
, name
))
23123 object_arch
= &opt
->value
;
23124 *input_line_pointer
= saved_char
;
23125 demand_empty_rest_of_line ();
23129 as_bad (_("unknown architecture `%s'\n"), name
);
23130 *input_line_pointer
= saved_char
;
23131 ignore_rest_of_line ();
23134 /* Parse a .fpu directive. */
23137 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23139 const struct arm_option_cpu_value_table
*opt
;
23143 name
= input_line_pointer
;
23144 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23145 input_line_pointer
++;
23146 saved_char
= *input_line_pointer
;
23147 *input_line_pointer
= 0;
23149 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23150 if (streq (opt
->name
, name
))
23152 mfpu_opt
= &opt
->value
;
23153 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23154 *input_line_pointer
= saved_char
;
23155 demand_empty_rest_of_line ();
23159 as_bad (_("unknown floating point format `%s'\n"), name
);
23160 *input_line_pointer
= saved_char
;
23161 ignore_rest_of_line ();
23164 /* Copy symbol information. */
23167 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23169 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23173 /* Given a symbolic attribute NAME, return the proper integer value.
23174 Returns -1 if the attribute is not known. */
23177 arm_convert_symbolic_attribute (const char *name
)
23179 static const struct
23184 attribute_table
[] =
23186 /* When you modify this table you should
23187 also modify the list in doc/c-arm.texi. */
23188 #define T(tag) {#tag, tag}
23189 T (Tag_CPU_raw_name
),
23192 T (Tag_CPU_arch_profile
),
23193 T (Tag_ARM_ISA_use
),
23194 T (Tag_THUMB_ISA_use
),
23198 T (Tag_Advanced_SIMD_arch
),
23199 T (Tag_PCS_config
),
23200 T (Tag_ABI_PCS_R9_use
),
23201 T (Tag_ABI_PCS_RW_data
),
23202 T (Tag_ABI_PCS_RO_data
),
23203 T (Tag_ABI_PCS_GOT_use
),
23204 T (Tag_ABI_PCS_wchar_t
),
23205 T (Tag_ABI_FP_rounding
),
23206 T (Tag_ABI_FP_denormal
),
23207 T (Tag_ABI_FP_exceptions
),
23208 T (Tag_ABI_FP_user_exceptions
),
23209 T (Tag_ABI_FP_number_model
),
23210 T (Tag_ABI_align_needed
),
23211 T (Tag_ABI_align8_needed
),
23212 T (Tag_ABI_align_preserved
),
23213 T (Tag_ABI_align8_preserved
),
23214 T (Tag_ABI_enum_size
),
23215 T (Tag_ABI_HardFP_use
),
23216 T (Tag_ABI_VFP_args
),
23217 T (Tag_ABI_WMMX_args
),
23218 T (Tag_ABI_optimization_goals
),
23219 T (Tag_ABI_FP_optimization_goals
),
23220 T (Tag_compatibility
),
23221 T (Tag_CPU_unaligned_access
),
23222 T (Tag_FP_HP_extension
),
23223 T (Tag_VFP_HP_extension
),
23224 T (Tag_ABI_FP_16bit_format
),
23225 T (Tag_MPextension_use
),
23227 T (Tag_nodefaults
),
23228 T (Tag_also_compatible_with
),
23229 T (Tag_conformance
),
23231 T (Tag_Virtualization_use
),
23232 /* We deliberately do not include Tag_MPextension_use_legacy. */
23240 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23241 if (streq (name
, attribute_table
[i
].name
))
23242 return attribute_table
[i
].tag
;
23248 /* Apply sym value for relocations only in the case that
23249 they are for local symbols and you have the respective
23250 architectural feature for blx and simple switches. */
23252 arm_apply_sym_value (struct fix
* fixP
)
23255 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23256 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23258 switch (fixP
->fx_r_type
)
23260 case BFD_RELOC_ARM_PCREL_BLX
:
23261 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23262 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23266 case BFD_RELOC_ARM_PCREL_CALL
:
23267 case BFD_RELOC_THUMB_PCREL_BLX
:
23268 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23279 #endif /* OBJ_ELF */