1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
158 static const arm_feature_set
*object_arch
= NULL
;
160 /* Constants for known architecture features. */
161 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
162 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
163 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
164 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
165 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
166 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
167 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
168 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
169 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
172 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
175 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
177 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
178 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
179 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
180 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
181 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
182 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
183 static const arm_feature_set arm_ext_v4t_5
=
184 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
186 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
187 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
188 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
189 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
190 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
191 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
192 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
193 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
194 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
195 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
196 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
197 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
198 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_arch_any
= ARM_ANY
;
201 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
202 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
203 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
205 static const arm_feature_set arm_cext_iwmmxt2
=
206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
207 static const arm_feature_set arm_cext_iwmmxt
=
208 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
209 static const arm_feature_set arm_cext_xscale
=
210 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
211 static const arm_feature_set arm_cext_maverick
=
212 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
213 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
214 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
215 static const arm_feature_set fpu_vfp_ext_v1xd
=
216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
217 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
218 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
219 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
220 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
221 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
222 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
224 static int mfloat_abi_opt
= -1;
225 /* Record user cpu selection for object attributes. */
226 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
227 /* Must be long enough to hold any of the names in arm_cpus. */
228 static char selected_cpu_name
[16];
231 static int meabi_flags
= EABI_DEFAULT
;
233 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
239 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
244 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
245 symbolS
* GOT_symbol
;
248 /* 0: assemble for ARM,
249 1: assemble for Thumb,
250 2: assemble for Thumb even though target CPU does not support thumb
252 static int thumb_mode
= 0;
254 /* If unified_syntax is true, we are processing the new unified
255 ARM/Thumb syntax. Important differences from the old ARM mode:
257 - Immediate operands do not require a # prefix.
258 - Conditional affixes always appear at the end of the
259 instruction. (For backward compatibility, those instructions
260 that formerly had them in the middle, continue to accept them
262 - The IT instruction may appear, and if it does is validated
263 against subsequent conditional affixes. It does not generate
266 Important differences from the old Thumb mode:
268 - Immediate operands do not require a # prefix.
269 - Most of the V6T2 instructions are only available in unified mode.
270 - The .N and .W suffixes are recognized and honored (it is an error
271 if they cannot be honored).
272 - All instructions set the flags if and only if they have an 's' affix.
273 - Conditional affixes may be used. They are validated against
274 preceding IT instructions. Unlike ARM mode, you cannot use a
275 conditional affix except in the scope of an IT instruction. */
277 static bfd_boolean unified_syntax
= FALSE
;
292 enum neon_el_type type
;
296 #define NEON_MAX_TYPE_ELS 4
300 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
307 unsigned long instruction
;
311 /* "uncond_value" is set to the value in place of the conditional field in
312 unconditional versions of the instruction, or -1 if nothing is
315 struct neon_type vectype
;
316 /* Set to the opcode if the instruction needs relaxation.
317 Zero if the instruction is not relaxed. */
321 bfd_reloc_code_real_type type
;
330 struct neon_type_el vectype
;
331 unsigned present
: 1; /* Operand present. */
332 unsigned isreg
: 1; /* Operand was a register. */
333 unsigned immisreg
: 1; /* .imm field is a second register. */
334 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
335 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
336 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
338 instructions. This allows us to disambiguate ARM <-> vector insns. */
339 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
340 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
341 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
342 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
343 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
344 unsigned writeback
: 1; /* Operand has trailing ! */
345 unsigned preind
: 1; /* Preindexed address. */
346 unsigned postind
: 1; /* Postindexed address. */
347 unsigned negative
: 1; /* Index register was negated. */
348 unsigned shifted
: 1; /* Shift applied to operation. */
349 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
353 static struct arm_it inst
;
355 #define NUM_FLOAT_VALS 8
357 const char * fp_const
[] =
359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
362 /* Number of littlenums required to hold an extended precision number. */
363 #define MAX_LITTLENUMS 6
365 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
375 #define CP_T_X 0x00008000
376 #define CP_T_Y 0x00400000
378 #define CONDS_BIT 0x00100000
379 #define LOAD_BIT 0x00100000
381 #define DOUBLE_LOAD_FLAG 0x00000001
385 const char * template;
389 #define COND_ALWAYS 0xE
393 const char *template;
397 struct asm_barrier_opt
399 const char *template;
403 /* The bit that distinguishes CPSR and SPSR. */
404 #define SPSR_BIT (1 << 22)
406 /* The individual PSR flag bits. */
407 #define PSR_c (1 << 16)
408 #define PSR_x (1 << 17)
409 #define PSR_s (1 << 18)
410 #define PSR_f (1 << 19)
415 bfd_reloc_code_real_type reloc
;
420 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
421 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
426 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
429 /* Bits for DEFINED field in neon_typed_alias. */
430 #define NTA_HASTYPE 1
431 #define NTA_HASINDEX 2
433 struct neon_typed_alias
435 unsigned char defined
;
437 struct neon_type_el eltype
;
440 /* ARM register categories. This includes coprocessor numbers and various
441 architecture extensions' registers. */
467 /* Structure for a hash table entry for a register.
468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
469 information which states whether a vector type or index is specified (for a
470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
474 unsigned char number
;
476 unsigned char builtin
;
477 struct neon_typed_alias
*neon
;
480 /* Diagnostics used when we don't get a register of the expected type. */
481 const char *const reg_expected_msgs
[] =
483 N_("ARM register expected"),
484 N_("bad or missing co-processor number"),
485 N_("co-processor register expected"),
486 N_("FPA register expected"),
487 N_("VFP single precision register expected"),
488 N_("VFP/Neon double precision register expected"),
489 N_("Neon quad precision register expected"),
490 N_("VFP single or double precision register expected"),
491 N_("Neon double or quad precision register expected"),
492 N_("VFP single, double or Neon quad precision register expected"),
493 N_("VFP system register expected"),
494 N_("Maverick MVF register expected"),
495 N_("Maverick MVD register expected"),
496 N_("Maverick MVFX register expected"),
497 N_("Maverick MVDX register expected"),
498 N_("Maverick MVAX register expected"),
499 N_("Maverick DSPSC register expected"),
500 N_("iWMMXt data register expected"),
501 N_("iWMMXt control register expected"),
502 N_("iWMMXt scalar register expected"),
503 N_("XScale accumulator register expected"),
506 /* Some well known registers that we refer to directly elsewhere. */
511 /* ARM instructions take 4bytes in the object file, Thumb instructions
517 /* Basic string to match. */
518 const char *template;
520 /* Parameters to instruction. */
521 unsigned char operands
[8];
523 /* Conditional tag - see opcode_lookup. */
524 unsigned int tag
: 4;
526 /* Basic instruction code. */
527 unsigned int avalue
: 28;
529 /* Thumb-format instruction code. */
532 /* Which architecture variant provides this instruction. */
533 const arm_feature_set
*avariant
;
534 const arm_feature_set
*tvariant
;
536 /* Function to call to encode instruction in ARM format. */
537 void (* aencode
) (void);
539 /* Function to call to encode instruction in Thumb format. */
540 void (* tencode
) (void);
543 /* Defines for various bits that we will want to toggle. */
544 #define INST_IMMEDIATE 0x02000000
545 #define OFFSET_REG 0x02000000
546 #define HWOFFSET_IMM 0x00400000
547 #define SHIFT_BY_REG 0x00000010
548 #define PRE_INDEX 0x01000000
549 #define INDEX_UP 0x00800000
550 #define WRITE_BACK 0x00200000
551 #define LDM_TYPE_2_OR_3 0x00400000
552 #define CPSI_MMOD 0x00020000
554 #define LITERAL_MASK 0xf000f000
555 #define OPCODE_MASK 0xfe1fffff
556 #define V4_STR_BIT 0x00000020
558 #define T2_SUBS_PC_LR 0xf3de8f00
560 #define DATA_OP_SHIFT 21
562 #define T2_OPCODE_MASK 0xfe1fffff
563 #define T2_DATA_OP_SHIFT 21
565 /* Codes to distinguish the arithmetic instructions. */
576 #define OPCODE_CMP 10
577 #define OPCODE_CMN 11
578 #define OPCODE_ORR 12
579 #define OPCODE_MOV 13
580 #define OPCODE_BIC 14
581 #define OPCODE_MVN 15
583 #define T2_OPCODE_AND 0
584 #define T2_OPCODE_BIC 1
585 #define T2_OPCODE_ORR 2
586 #define T2_OPCODE_ORN 3
587 #define T2_OPCODE_EOR 4
588 #define T2_OPCODE_ADD 8
589 #define T2_OPCODE_ADC 10
590 #define T2_OPCODE_SBC 11
591 #define T2_OPCODE_SUB 13
592 #define T2_OPCODE_RSB 14
594 #define T_OPCODE_MUL 0x4340
595 #define T_OPCODE_TST 0x4200
596 #define T_OPCODE_CMN 0x42c0
597 #define T_OPCODE_NEG 0x4240
598 #define T_OPCODE_MVN 0x43c0
600 #define T_OPCODE_ADD_R3 0x1800
601 #define T_OPCODE_SUB_R3 0x1a00
602 #define T_OPCODE_ADD_HI 0x4400
603 #define T_OPCODE_ADD_ST 0xb000
604 #define T_OPCODE_SUB_ST 0xb080
605 #define T_OPCODE_ADD_SP 0xa800
606 #define T_OPCODE_ADD_PC 0xa000
607 #define T_OPCODE_ADD_I8 0x3000
608 #define T_OPCODE_SUB_I8 0x3800
609 #define T_OPCODE_ADD_I3 0x1c00
610 #define T_OPCODE_SUB_I3 0x1e00
612 #define T_OPCODE_ASR_R 0x4100
613 #define T_OPCODE_LSL_R 0x4080
614 #define T_OPCODE_LSR_R 0x40c0
615 #define T_OPCODE_ROR_R 0x41c0
616 #define T_OPCODE_ASR_I 0x1000
617 #define T_OPCODE_LSL_I 0x0000
618 #define T_OPCODE_LSR_I 0x0800
620 #define T_OPCODE_MOV_I8 0x2000
621 #define T_OPCODE_CMP_I8 0x2800
622 #define T_OPCODE_CMP_LR 0x4280
623 #define T_OPCODE_MOV_HR 0x4600
624 #define T_OPCODE_CMP_HR 0x4500
626 #define T_OPCODE_LDR_PC 0x4800
627 #define T_OPCODE_LDR_SP 0x9800
628 #define T_OPCODE_STR_SP 0x9000
629 #define T_OPCODE_LDR_IW 0x6800
630 #define T_OPCODE_STR_IW 0x6000
631 #define T_OPCODE_LDR_IH 0x8800
632 #define T_OPCODE_STR_IH 0x8000
633 #define T_OPCODE_LDR_IB 0x7800
634 #define T_OPCODE_STR_IB 0x7000
635 #define T_OPCODE_LDR_RW 0x5800
636 #define T_OPCODE_STR_RW 0x5000
637 #define T_OPCODE_LDR_RH 0x5a00
638 #define T_OPCODE_STR_RH 0x5200
639 #define T_OPCODE_LDR_RB 0x5c00
640 #define T_OPCODE_STR_RB 0x5400
642 #define T_OPCODE_PUSH 0xb400
643 #define T_OPCODE_POP 0xbc00
645 #define T_OPCODE_BRANCH 0xe000
647 #define THUMB_SIZE 2 /* Size of thumb instruction. */
648 #define THUMB_PP_PC_LR 0x0100
649 #define THUMB_LOAD_BIT 0x0800
650 #define THUMB2_LOAD_BIT 0x00100000
652 #define BAD_ARGS _("bad arguments to instruction")
653 #define BAD_PC _("r15 not allowed here")
654 #define BAD_COND _("instruction cannot be conditional")
655 #define BAD_OVERLAP _("registers may not be the same")
656 #define BAD_HIREG _("lo register required")
657 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
658 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
659 #define BAD_BRANCH _("branch must be last instruction in IT block")
660 #define BAD_NOT_IT _("instruction not allowed in IT block")
661 #define BAD_FPU _("selected FPU does not support instruction")
663 static struct hash_control
*arm_ops_hsh
;
664 static struct hash_control
*arm_cond_hsh
;
665 static struct hash_control
*arm_shift_hsh
;
666 static struct hash_control
*arm_psr_hsh
;
667 static struct hash_control
*arm_v7m_psr_hsh
;
668 static struct hash_control
*arm_reg_hsh
;
669 static struct hash_control
*arm_reloc_hsh
;
670 static struct hash_control
*arm_barrier_opt_hsh
;
672 /* Stuff needed to resolve the label ambiguity
681 symbolS
* last_label_seen
;
682 static int label_is_thumb_function_name
= FALSE
;
684 /* Literal pool structure. Held on a per-section
685 and per-sub-section basis. */
687 #define MAX_LITERAL_POOL_SIZE 1024
688 typedef struct literal_pool
690 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
691 unsigned int next_free_entry
;
696 struct literal_pool
* next
;
699 /* Pointer to a linked list of literal pools. */
700 literal_pool
* list_of_pools
= NULL
;
702 /* State variables for IT block handling. */
703 static bfd_boolean current_it_mask
= 0;
704 static int current_cc
;
708 /* This array holds the chars that always start a comment. If the
709 pre-processor is disabled, these aren't very useful. */
710 const char comment_chars
[] = "@";
712 /* This array holds the chars that only start a comment at the beginning of
713 a line. If the line seems to have the form '# 123 filename'
714 .line and .file directives will appear in the pre-processed output. */
715 /* Note that input_file.c hand checks for '#' at the beginning of the
716 first line of the input file. This is because the compiler outputs
717 #NO_APP at the beginning of its output. */
718 /* Also note that comments like this one will always work. */
719 const char line_comment_chars
[] = "#";
721 const char line_separator_chars
[] = ";";
723 /* Chars that can be used to separate mant
724 from exp in floating point numbers. */
725 const char EXP_CHARS
[] = "eE";
727 /* Chars that mean this number is a floating point constant. */
731 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
733 /* Prefix characters that indicate the start of an immediate
735 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
737 /* Separator character handling. */
739 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
742 skip_past_char (char ** str
, char c
)
752 #define skip_past_comma(str) skip_past_char (str, ',')
754 /* Arithmetic expressions (possibly involving symbols). */
756 /* Return TRUE if anything in the expression is a bignum. */
759 walk_no_bignums (symbolS
* sp
)
761 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
764 if (symbol_get_value_expression (sp
)->X_add_symbol
)
766 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
767 || (symbol_get_value_expression (sp
)->X_op_symbol
768 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
774 static int in_my_get_expression
= 0;
776 /* Third argument to my_get_expression. */
777 #define GE_NO_PREFIX 0
778 #define GE_IMM_PREFIX 1
779 #define GE_OPT_PREFIX 2
780 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
781 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
782 #define GE_OPT_PREFIX_BIG 3
785 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
790 /* In unified syntax, all prefixes are optional. */
792 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
797 case GE_NO_PREFIX
: break;
799 if (!is_immediate_prefix (**str
))
801 inst
.error
= _("immediate expression requires a # prefix");
807 case GE_OPT_PREFIX_BIG
:
808 if (is_immediate_prefix (**str
))
814 memset (ep
, 0, sizeof (expressionS
));
816 save_in
= input_line_pointer
;
817 input_line_pointer
= *str
;
818 in_my_get_expression
= 1;
819 seg
= expression (ep
);
820 in_my_get_expression
= 0;
822 if (ep
->X_op
== O_illegal
)
824 /* We found a bad expression in md_operand(). */
825 *str
= input_line_pointer
;
826 input_line_pointer
= save_in
;
827 if (inst
.error
== NULL
)
828 inst
.error
= _("bad expression");
833 if (seg
!= absolute_section
834 && seg
!= text_section
835 && seg
!= data_section
836 && seg
!= bss_section
837 && seg
!= undefined_section
)
839 inst
.error
= _("bad segment");
840 *str
= input_line_pointer
;
841 input_line_pointer
= save_in
;
846 /* Get rid of any bignums now, so that we don't generate an error for which
847 we can't establish a line number later on. Big numbers are never valid
848 in instructions, which is where this routine is always called. */
849 if (prefix_mode
!= GE_OPT_PREFIX_BIG
850 && (ep
->X_op
== O_big
852 && (walk_no_bignums (ep
->X_add_symbol
)
854 && walk_no_bignums (ep
->X_op_symbol
))))))
856 inst
.error
= _("invalid constant");
857 *str
= input_line_pointer
;
858 input_line_pointer
= save_in
;
862 *str
= input_line_pointer
;
863 input_line_pointer
= save_in
;
867 /* Turn a string in input_line_pointer into a floating point constant
868 of type TYPE, and store the appropriate bytes in *LITP. The number
869 of LITTLENUMS emitted is stored in *SIZEP. An error message is
870 returned, or NULL on OK.
872 Note that fp constants aren't represent in the normal way on the ARM.
873 In big endian mode, things are as expected. However, in little endian
874 mode fp constants are big-endian word-wise, and little-endian byte-wise
875 within the words. For example, (double) 1.1 in big endian mode is
876 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
877 the byte sequence 99 99 f1 3f 9a 99 99 99.
879 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
882 md_atof (int type
, char * litP
, int * sizeP
)
885 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
917 return _("Unrecognized or unsupported floating point constant");
920 t
= atof_ieee (input_line_pointer
, type
, words
);
922 input_line_pointer
= t
;
923 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
925 if (target_big_endian
)
927 for (i
= 0; i
< prec
; i
++)
929 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
930 litP
+= sizeof (LITTLENUM_TYPE
);
935 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
936 for (i
= prec
- 1; i
>= 0; i
--)
938 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
939 litP
+= sizeof (LITTLENUM_TYPE
);
942 /* For a 4 byte float the order of elements in `words' is 1 0.
943 For an 8 byte float the order is 1 0 3 2. */
944 for (i
= 0; i
< prec
; i
+= 2)
946 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
947 sizeof (LITTLENUM_TYPE
));
948 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
949 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
950 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
957 /* We handle all bad expressions here, so that we can report the faulty
958 instruction in the error message. */
960 md_operand (expressionS
* expr
)
962 if (in_my_get_expression
)
963 expr
->X_op
= O_illegal
;
966 /* Immediate values. */
968 /* Generic immediate-value read function for use in directives.
969 Accepts anything that 'expression' can fold to a constant.
970 *val receives the number. */
973 immediate_for_directive (int *val
)
976 exp
.X_op
= O_illegal
;
978 if (is_immediate_prefix (*input_line_pointer
))
980 input_line_pointer
++;
984 if (exp
.X_op
!= O_constant
)
986 as_bad (_("expected #constant"));
987 ignore_rest_of_line ();
990 *val
= exp
.X_add_number
;
995 /* Register parsing. */
997 /* Generic register parser. CCP points to what should be the
998 beginning of a register name. If it is indeed a valid register
999 name, advance CCP over it and return the reg_entry structure;
1000 otherwise return NULL. Does not issue diagnostics. */
1002 static struct reg_entry
*
1003 arm_reg_parse_multi (char **ccp
)
1007 struct reg_entry
*reg
;
1009 #ifdef REGISTER_PREFIX
1010 if (*start
!= REGISTER_PREFIX
)
1014 #ifdef OPTIONAL_REGISTER_PREFIX
1015 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1020 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1025 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1027 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1037 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1038 enum arm_reg_type type
)
1040 /* Alternative syntaxes are accepted for a few register classes. */
1047 /* Generic coprocessor register names are allowed for these. */
1048 if (reg
&& reg
->type
== REG_TYPE_CN
)
1053 /* For backward compatibility, a bare number is valid here. */
1055 unsigned long processor
= strtoul (start
, ccp
, 10);
1056 if (*ccp
!= start
&& processor
<= 15)
1060 case REG_TYPE_MMXWC
:
1061 /* WC includes WCG. ??? I'm not sure this is true for all
1062 instructions that take WC registers. */
1063 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1074 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1075 return value is the register number or FAIL. */
1078 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1081 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1084 /* Do not allow a scalar (reg+index) to parse as a register. */
1085 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1088 if (reg
&& reg
->type
== type
)
1091 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1098 /* Parse a Neon type specifier. *STR should point at the leading '.'
1099 character. Does no verification at this stage that the type fits the opcode
1106 Can all be legally parsed by this function.
1108 Fills in neon_type struct pointer with parsed information, and updates STR
1109 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1110 type, FAIL if not. */
1113 parse_neon_type (struct neon_type
*type
, char **str
)
1120 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1122 enum neon_el_type thistype
= NT_untyped
;
1123 unsigned thissize
= -1u;
1130 /* Just a size without an explicit type. */
1134 switch (TOLOWER (*ptr
))
1136 case 'i': thistype
= NT_integer
; break;
1137 case 'f': thistype
= NT_float
; break;
1138 case 'p': thistype
= NT_poly
; break;
1139 case 's': thistype
= NT_signed
; break;
1140 case 'u': thistype
= NT_unsigned
; break;
1142 thistype
= NT_float
;
1147 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1153 /* .f is an abbreviation for .f32. */
1154 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1159 thissize
= strtoul (ptr
, &ptr
, 10);
1161 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1164 as_bad (_("bad size %d in type specifier"), thissize
);
1172 type
->el
[type
->elems
].type
= thistype
;
1173 type
->el
[type
->elems
].size
= thissize
;
1178 /* Empty/missing type is not a successful parse. */
1179 if (type
->elems
== 0)
1187 /* Errors may be set multiple times during parsing or bit encoding
1188 (particularly in the Neon bits), but usually the earliest error which is set
1189 will be the most meaningful. Avoid overwriting it with later (cascading)
1190 errors by calling this function. */
1193 first_error (const char *err
)
1199 /* Parse a single type, e.g. ".s32", leading period included. */
1201 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1204 struct neon_type optype
;
1208 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1210 if (optype
.elems
== 1)
1211 *vectype
= optype
.el
[0];
1214 first_error (_("only one type should be specified for operand"));
1220 first_error (_("vector type expected"));
1232 /* Special meanings for indices (which have a range of 0-7), which will fit into
1235 #define NEON_ALL_LANES 15
1236 #define NEON_INTERLEAVE_LANES 14
1238 /* Parse either a register or a scalar, with an optional type. Return the
1239 register number, and optionally fill in the actual type of the register
1240 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1241 type/index information in *TYPEINFO. */
1244 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1245 enum arm_reg_type
*rtype
,
1246 struct neon_typed_alias
*typeinfo
)
1249 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1250 struct neon_typed_alias atype
;
1251 struct neon_type_el parsetype
;
1255 atype
.eltype
.type
= NT_invtype
;
1256 atype
.eltype
.size
= -1;
1258 /* Try alternate syntax for some types of register. Note these are mutually
1259 exclusive with the Neon syntax extensions. */
1262 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1270 /* Undo polymorphism when a set of register types may be accepted. */
1271 if ((type
== REG_TYPE_NDQ
1272 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1273 || (type
== REG_TYPE_VFSD
1274 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1275 || (type
== REG_TYPE_NSDQ
1276 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1277 || reg
->type
== REG_TYPE_NQ
))
1278 || (type
== REG_TYPE_MMXWC
1279 && (reg
->type
== REG_TYPE_MMXWCG
)))
1282 if (type
!= reg
->type
)
1288 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1290 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1292 first_error (_("can't redefine type for operand"));
1295 atype
.defined
|= NTA_HASTYPE
;
1296 atype
.eltype
= parsetype
;
1299 if (skip_past_char (&str
, '[') == SUCCESS
)
1301 if (type
!= REG_TYPE_VFD
)
1303 first_error (_("only D registers may be indexed"));
1307 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1309 first_error (_("can't change index for operand"));
1313 atype
.defined
|= NTA_HASINDEX
;
1315 if (skip_past_char (&str
, ']') == SUCCESS
)
1316 atype
.index
= NEON_ALL_LANES
;
1321 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1323 if (exp
.X_op
!= O_constant
)
1325 first_error (_("constant expression required"));
1329 if (skip_past_char (&str
, ']') == FAIL
)
1332 atype
.index
= exp
.X_add_number
;
1347 /* Like arm_reg_parse, but allow allow the following extra features:
1348 - If RTYPE is non-zero, return the (possibly restricted) type of the
1349 register (e.g. Neon double or quad reg when either has been requested).
1350 - If this is a Neon vector type with additional type information, fill
1351 in the struct pointed to by VECTYPE (if non-NULL).
1352 This function will fault on encountering a scalar. */
1355 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1356 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1358 struct neon_typed_alias atype
;
1360 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1365 /* Do not allow a scalar (reg+index) to parse as a register. */
1366 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1368 first_error (_("register operand expected, but got scalar"));
1373 *vectype
= atype
.eltype
;
1380 #define NEON_SCALAR_REG(X) ((X) >> 4)
1381 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1383 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1384 have enough information to be able to do a good job bounds-checking. So, we
1385 just do easy checks here, and do further checks later. */
1388 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1392 struct neon_typed_alias atype
;
1394 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1396 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1399 if (atype
.index
== NEON_ALL_LANES
)
1401 first_error (_("scalar must have an index"));
1404 else if (atype
.index
>= 64 / elsize
)
1406 first_error (_("scalar index out of range"));
1411 *type
= atype
.eltype
;
1415 return reg
* 16 + atype
.index
;
1418 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1420 parse_reg_list (char ** strp
)
1422 char * str
= * strp
;
1426 /* We come back here if we get ranges concatenated by '+' or '|'. */
1441 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1443 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1453 first_error (_("bad range in register list"));
1457 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1459 if (range
& (1 << i
))
1461 (_("Warning: duplicated register (r%d) in register list"),
1469 if (range
& (1 << reg
))
1470 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1472 else if (reg
<= cur_reg
)
1473 as_tsktsk (_("Warning: register range not in ascending order"));
1478 while (skip_past_comma (&str
) != FAIL
1479 || (in_range
= 1, *str
++ == '-'));
1484 first_error (_("missing `}'"));
1492 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1495 if (expr
.X_op
== O_constant
)
1497 if (expr
.X_add_number
1498 != (expr
.X_add_number
& 0x0000ffff))
1500 inst
.error
= _("invalid register mask");
1504 if ((range
& expr
.X_add_number
) != 0)
1506 int regno
= range
& expr
.X_add_number
;
1509 regno
= (1 << regno
) - 1;
1511 (_("Warning: duplicated register (r%d) in register list"),
1515 range
|= expr
.X_add_number
;
1519 if (inst
.reloc
.type
!= 0)
1521 inst
.error
= _("expression too complex");
1525 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1526 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1527 inst
.reloc
.pc_rel
= 0;
1531 if (*str
== '|' || *str
== '+')
1537 while (another_range
);
1543 /* Types of registers in a list. */
1552 /* Parse a VFP register list. If the string is invalid return FAIL.
1553 Otherwise return the number of registers, and set PBASE to the first
1554 register. Parses registers of type ETYPE.
1555 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1556 - Q registers can be used to specify pairs of D registers
1557 - { } can be omitted from around a singleton register list
1558 FIXME: This is not implemented, as it would require backtracking in
1561 This could be done (the meaning isn't really ambiguous), but doesn't
1562 fit in well with the current parsing framework.
1563 - 32 D registers may be used (also true for VFPv3).
1564 FIXME: Types are ignored in these register lists, which is probably a
1568 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1573 enum arm_reg_type regtype
= 0;
1577 unsigned long mask
= 0;
1582 inst
.error
= _("expecting {");
1591 regtype
= REG_TYPE_VFS
;
1596 regtype
= REG_TYPE_VFD
;
1599 case REGLIST_NEON_D
:
1600 regtype
= REG_TYPE_NDQ
;
1604 if (etype
!= REGLIST_VFP_S
)
1606 /* VFPv3 allows 32 D registers. */
1607 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1611 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1614 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1621 base_reg
= max_regs
;
1625 int setmask
= 1, addregs
= 1;
1627 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1629 if (new_base
== FAIL
)
1631 first_error (_(reg_expected_msgs
[regtype
]));
1635 if (new_base
>= max_regs
)
1637 first_error (_("register out of range in list"));
1641 /* Note: a value of 2 * n is returned for the register Q<n>. */
1642 if (regtype
== REG_TYPE_NQ
)
1648 if (new_base
< base_reg
)
1649 base_reg
= new_base
;
1651 if (mask
& (setmask
<< new_base
))
1653 first_error (_("invalid register list"));
1657 if ((mask
>> new_base
) != 0 && ! warned
)
1659 as_tsktsk (_("register list not in ascending order"));
1663 mask
|= setmask
<< new_base
;
1666 if (*str
== '-') /* We have the start of a range expression */
1672 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1675 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1679 if (high_range
>= max_regs
)
1681 first_error (_("register out of range in list"));
1685 if (regtype
== REG_TYPE_NQ
)
1686 high_range
= high_range
+ 1;
1688 if (high_range
<= new_base
)
1690 inst
.error
= _("register range not in ascending order");
1694 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1696 if (mask
& (setmask
<< new_base
))
1698 inst
.error
= _("invalid register list");
1702 mask
|= setmask
<< new_base
;
1707 while (skip_past_comma (&str
) != FAIL
);
1711 /* Sanity check -- should have raised a parse error above. */
1712 if (count
== 0 || count
> max_regs
)
1717 /* Final test -- the registers must be consecutive. */
1719 for (i
= 0; i
< count
; i
++)
1721 if ((mask
& (1u << i
)) == 0)
1723 inst
.error
= _("non-contiguous register range");
1733 /* True if two alias types are the same. */
1736 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1744 if (a
->defined
!= b
->defined
)
1747 if ((a
->defined
& NTA_HASTYPE
) != 0
1748 && (a
->eltype
.type
!= b
->eltype
.type
1749 || a
->eltype
.size
!= b
->eltype
.size
))
1752 if ((a
->defined
& NTA_HASINDEX
) != 0
1753 && (a
->index
!= b
->index
))
1759 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1760 The base register is put in *PBASE.
1761 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1763 The register stride (minus one) is put in bit 4 of the return value.
1764 Bits [6:5] encode the list length (minus one).
1765 The type of the list elements is put in *ELTYPE, if non-NULL. */
1767 #define NEON_LANE(X) ((X) & 0xf)
1768 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1769 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1772 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1773 struct neon_type_el
*eltype
)
1780 int leading_brace
= 0;
1781 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1783 const char *const incr_error
= "register stride must be 1 or 2";
1784 const char *const type_error
= "mismatched element/structure types in list";
1785 struct neon_typed_alias firsttype
;
1787 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1792 struct neon_typed_alias atype
;
1793 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1797 first_error (_(reg_expected_msgs
[rtype
]));
1804 if (rtype
== REG_TYPE_NQ
)
1811 else if (reg_incr
== -1)
1813 reg_incr
= getreg
- base_reg
;
1814 if (reg_incr
< 1 || reg_incr
> 2)
1816 first_error (_(incr_error
));
1820 else if (getreg
!= base_reg
+ reg_incr
* count
)
1822 first_error (_(incr_error
));
1826 if (!neon_alias_types_same (&atype
, &firsttype
))
1828 first_error (_(type_error
));
1832 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1836 struct neon_typed_alias htype
;
1837 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1839 lane
= NEON_INTERLEAVE_LANES
;
1840 else if (lane
!= NEON_INTERLEAVE_LANES
)
1842 first_error (_(type_error
));
1847 else if (reg_incr
!= 1)
1849 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1853 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1856 first_error (_(reg_expected_msgs
[rtype
]));
1859 if (!neon_alias_types_same (&htype
, &firsttype
))
1861 first_error (_(type_error
));
1864 count
+= hireg
+ dregs
- getreg
;
1868 /* If we're using Q registers, we can't use [] or [n] syntax. */
1869 if (rtype
== REG_TYPE_NQ
)
1875 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1879 else if (lane
!= atype
.index
)
1881 first_error (_(type_error
));
1885 else if (lane
== -1)
1886 lane
= NEON_INTERLEAVE_LANES
;
1887 else if (lane
!= NEON_INTERLEAVE_LANES
)
1889 first_error (_(type_error
));
1894 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1896 /* No lane set by [x]. We must be interleaving structures. */
1898 lane
= NEON_INTERLEAVE_LANES
;
1901 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1902 || (count
> 1 && reg_incr
== -1))
1904 first_error (_("error parsing element/structure list"));
1908 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1910 first_error (_("expected }"));
1918 *eltype
= firsttype
.eltype
;
1923 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1926 /* Parse an explicit relocation suffix on an expression. This is
1927 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1928 arm_reloc_hsh contains no entries, so this function can only
1929 succeed if there is no () after the word. Returns -1 on error,
1930 BFD_RELOC_UNUSED if there wasn't any suffix. */
1932 parse_reloc (char **str
)
1934 struct reloc_entry
*r
;
1938 return BFD_RELOC_UNUSED
;
1943 while (*q
&& *q
!= ')' && *q
!= ',')
1948 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1955 /* Directives: register aliases. */
1957 static struct reg_entry
*
1958 insert_reg_alias (char *str
, int number
, int type
)
1960 struct reg_entry
*new;
1963 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1966 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1968 /* Only warn about a redefinition if it's not defined as the
1970 else if (new->number
!= number
|| new->type
!= type
)
1971 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1976 name
= xstrdup (str
);
1977 new = xmalloc (sizeof (struct reg_entry
));
1980 new->number
= number
;
1982 new->builtin
= FALSE
;
1985 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1992 insert_neon_reg_alias (char *str
, int number
, int type
,
1993 struct neon_typed_alias
*atype
)
1995 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1999 first_error (_("attempt to redefine typed alias"));
2005 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2006 *reg
->neon
= *atype
;
2010 /* Look for the .req directive. This is of the form:
2012 new_register_name .req existing_register_name
2014 If we find one, or if it looks sufficiently like one that we want to
2015 handle any error here, return TRUE. Otherwise return FALSE. */
2018 create_register_alias (char * newname
, char *p
)
2020 struct reg_entry
*old
;
2021 char *oldname
, *nbuf
;
2024 /* The input scrubber ensures that whitespace after the mnemonic is
2025 collapsed to single spaces. */
2027 if (strncmp (oldname
, " .req ", 6) != 0)
2031 if (*oldname
== '\0')
2034 old
= hash_find (arm_reg_hsh
, oldname
);
2037 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2041 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2042 the desired alias name, and p points to its end. If not, then
2043 the desired alias name is in the global original_case_string. */
2044 #ifdef TC_CASE_SENSITIVE
2047 newname
= original_case_string
;
2048 nlen
= strlen (newname
);
2051 nbuf
= alloca (nlen
+ 1);
2052 memcpy (nbuf
, newname
, nlen
);
2055 /* Create aliases under the new name as stated; an all-lowercase
2056 version of the new name; and an all-uppercase version of the new
2058 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2060 for (p
= nbuf
; *p
; p
++)
2063 if (strncmp (nbuf
, newname
, nlen
))
2065 /* If this attempt to create an additional alias fails, do not bother
2066 trying to create the all-lower case alias. We will fail and issue
2067 a second, duplicate error message. This situation arises when the
2068 programmer does something like:
2071 The second .req creates the "Foo" alias but then fails to create
2072 the artificial FOO alias because it has already been created by the
2074 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2078 for (p
= nbuf
; *p
; p
++)
2081 if (strncmp (nbuf
, newname
, nlen
))
2082 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2088 /* Create a Neon typed/indexed register alias using directives, e.g.:
2093 These typed registers can be used instead of the types specified after the
2094 Neon mnemonic, so long as all operands given have types. Types can also be
2095 specified directly, e.g.:
2096 vadd d0.s32, d1.s32, d2.s32 */
2099 create_neon_reg_alias (char *newname
, char *p
)
2101 enum arm_reg_type basetype
;
2102 struct reg_entry
*basereg
;
2103 struct reg_entry mybasereg
;
2104 struct neon_type ntype
;
2105 struct neon_typed_alias typeinfo
;
2106 char *namebuf
, *nameend
;
2109 typeinfo
.defined
= 0;
2110 typeinfo
.eltype
.type
= NT_invtype
;
2111 typeinfo
.eltype
.size
= -1;
2112 typeinfo
.index
= -1;
2116 if (strncmp (p
, " .dn ", 5) == 0)
2117 basetype
= REG_TYPE_VFD
;
2118 else if (strncmp (p
, " .qn ", 5) == 0)
2119 basetype
= REG_TYPE_NQ
;
2128 basereg
= arm_reg_parse_multi (&p
);
2130 if (basereg
&& basereg
->type
!= basetype
)
2132 as_bad (_("bad type for register"));
2136 if (basereg
== NULL
)
2139 /* Try parsing as an integer. */
2140 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2141 if (exp
.X_op
!= O_constant
)
2143 as_bad (_("expression must be constant"));
2146 basereg
= &mybasereg
;
2147 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2153 typeinfo
= *basereg
->neon
;
2155 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2157 /* We got a type. */
2158 if (typeinfo
.defined
& NTA_HASTYPE
)
2160 as_bad (_("can't redefine the type of a register alias"));
2164 typeinfo
.defined
|= NTA_HASTYPE
;
2165 if (ntype
.elems
!= 1)
2167 as_bad (_("you must specify a single type only"));
2170 typeinfo
.eltype
= ntype
.el
[0];
2173 if (skip_past_char (&p
, '[') == SUCCESS
)
2176 /* We got a scalar index. */
2178 if (typeinfo
.defined
& NTA_HASINDEX
)
2180 as_bad (_("can't redefine the index of a scalar alias"));
2184 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2186 if (exp
.X_op
!= O_constant
)
2188 as_bad (_("scalar index must be constant"));
2192 typeinfo
.defined
|= NTA_HASINDEX
;
2193 typeinfo
.index
= exp
.X_add_number
;
2195 if (skip_past_char (&p
, ']') == FAIL
)
2197 as_bad (_("expecting ]"));
2202 namelen
= nameend
- newname
;
2203 namebuf
= alloca (namelen
+ 1);
2204 strncpy (namebuf
, newname
, namelen
);
2205 namebuf
[namelen
] = '\0';
2207 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2208 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2210 /* Insert name in all uppercase. */
2211 for (p
= namebuf
; *p
; p
++)
2214 if (strncmp (namebuf
, newname
, namelen
))
2215 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2216 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2218 /* Insert name in all lowercase. */
2219 for (p
= namebuf
; *p
; p
++)
2222 if (strncmp (namebuf
, newname
, namelen
))
2223 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2224 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2229 /* Should never be called, as .req goes between the alias and the
2230 register name, not at the beginning of the line. */
2232 s_req (int a ATTRIBUTE_UNUSED
)
2234 as_bad (_("invalid syntax for .req directive"));
2238 s_dn (int a ATTRIBUTE_UNUSED
)
2240 as_bad (_("invalid syntax for .dn directive"));
2244 s_qn (int a ATTRIBUTE_UNUSED
)
2246 as_bad (_("invalid syntax for .qn directive"));
2249 /* The .unreq directive deletes an alias which was previously defined
2250 by .req. For example:
2256 s_unreq (int a ATTRIBUTE_UNUSED
)
2261 name
= input_line_pointer
;
2263 while (*input_line_pointer
!= 0
2264 && *input_line_pointer
!= ' '
2265 && *input_line_pointer
!= '\n')
2266 ++input_line_pointer
;
2268 saved_char
= *input_line_pointer
;
2269 *input_line_pointer
= 0;
2272 as_bad (_("invalid syntax for .unreq directive"));
2275 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2278 as_bad (_("unknown register alias '%s'"), name
);
2279 else if (reg
->builtin
)
2280 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2287 hash_delete (arm_reg_hsh
, name
);
2288 free ((char *) reg
->name
);
2293 /* Also locate the all upper case and all lower case versions.
2294 Do not complain if we cannot find one or the other as it
2295 was probably deleted above. */
2297 nbuf
= strdup (name
);
2298 for (p
= nbuf
; *p
; p
++)
2300 reg
= hash_find (arm_reg_hsh
, nbuf
);
2303 hash_delete (arm_reg_hsh
, nbuf
);
2304 free ((char *) reg
->name
);
2310 for (p
= nbuf
; *p
; p
++)
2312 reg
= hash_find (arm_reg_hsh
, nbuf
);
2315 hash_delete (arm_reg_hsh
, nbuf
);
2316 free ((char *) reg
->name
);
2326 *input_line_pointer
= saved_char
;
2327 demand_empty_rest_of_line ();
2330 /* Directives: Instruction set selection. */
2333 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2334 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2335 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2336 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2338 static enum mstate mapstate
= MAP_UNDEFINED
;
2341 mapping_state (enum mstate state
)
2344 const char * symname
;
2347 if (mapstate
== state
)
2348 /* The mapping symbol has already been emitted.
2349 There is nothing else to do. */
2358 type
= BSF_NO_FLAGS
;
2362 type
= BSF_NO_FLAGS
;
2366 type
= BSF_NO_FLAGS
;
2374 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2376 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2377 symbol_table_insert (symbolP
);
2378 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2383 THUMB_SET_FUNC (symbolP
, 0);
2384 ARM_SET_THUMB (symbolP
, 0);
2385 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2389 THUMB_SET_FUNC (symbolP
, 1);
2390 ARM_SET_THUMB (symbolP
, 1);
2391 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2400 #define mapping_state(x) /* nothing */
2403 /* Find the real, Thumb encoded start of a Thumb function. */
2406 find_real_start (symbolS
* symbolP
)
2409 const char * name
= S_GET_NAME (symbolP
);
2410 symbolS
* new_target
;
2412 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2413 #define STUB_NAME ".real_start_of"
2418 /* The compiler may generate BL instructions to local labels because
2419 it needs to perform a branch to a far away location. These labels
2420 do not have a corresponding ".real_start_of" label. We check
2421 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2422 the ".real_start_of" convention for nonlocal branches. */
2423 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2426 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2427 new_target
= symbol_find (real_start
);
2429 if (new_target
== NULL
)
2431 as_warn (_("Failed to find real start of function: %s\n"), name
);
2432 new_target
= symbolP
;
2439 opcode_select (int width
)
2446 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2447 as_bad (_("selected processor does not support THUMB opcodes"));
2450 /* No need to force the alignment, since we will have been
2451 coming from ARM mode, which is word-aligned. */
2452 record_alignment (now_seg
, 1);
2454 mapping_state (MAP_THUMB
);
2460 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2461 as_bad (_("selected processor does not support ARM opcodes"));
2466 frag_align (2, 0, 0);
2468 record_alignment (now_seg
, 1);
2470 mapping_state (MAP_ARM
);
2474 as_bad (_("invalid instruction size selected (%d)"), width
);
2479 s_arm (int ignore ATTRIBUTE_UNUSED
)
2482 demand_empty_rest_of_line ();
2486 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2489 demand_empty_rest_of_line ();
2493 s_code (int unused ATTRIBUTE_UNUSED
)
2497 temp
= get_absolute_expression ();
2502 opcode_select (temp
);
2506 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2511 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2513 /* If we are not already in thumb mode go into it, EVEN if
2514 the target processor does not support thumb instructions.
2515 This is used by gcc/config/arm/lib1funcs.asm for example
2516 to compile interworking support functions even if the
2517 target processor should not support interworking. */
2521 record_alignment (now_seg
, 1);
2524 demand_empty_rest_of_line ();
2528 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2532 /* The following label is the name/address of the start of a Thumb function.
2533 We need to know this for the interworking support. */
2534 label_is_thumb_function_name
= TRUE
;
2537 /* Perform a .set directive, but also mark the alias as
2538 being a thumb function. */
2541 s_thumb_set (int equiv
)
2543 /* XXX the following is a duplicate of the code for s_set() in read.c
2544 We cannot just call that code as we need to get at the symbol that
2551 /* Especial apologies for the random logic:
2552 This just grew, and could be parsed much more simply!
2554 name
= input_line_pointer
;
2555 delim
= get_symbol_end ();
2556 end_name
= input_line_pointer
;
2559 if (*input_line_pointer
!= ',')
2562 as_bad (_("expected comma after name \"%s\""), name
);
2564 ignore_rest_of_line ();
2568 input_line_pointer
++;
2571 if (name
[0] == '.' && name
[1] == '\0')
2573 /* XXX - this should not happen to .thumb_set. */
2577 if ((symbolP
= symbol_find (name
)) == NULL
2578 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2581 /* When doing symbol listings, play games with dummy fragments living
2582 outside the normal fragment chain to record the file and line info
2584 if (listing
& LISTING_SYMBOLS
)
2586 extern struct list_info_struct
* listing_tail
;
2587 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2589 memset (dummy_frag
, 0, sizeof (fragS
));
2590 dummy_frag
->fr_type
= rs_fill
;
2591 dummy_frag
->line
= listing_tail
;
2592 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2593 dummy_frag
->fr_symbol
= symbolP
;
2597 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2600 /* "set" symbols are local unless otherwise specified. */
2601 SF_SET_LOCAL (symbolP
);
2602 #endif /* OBJ_COFF */
2603 } /* Make a new symbol. */
2605 symbol_table_insert (symbolP
);
2610 && S_IS_DEFINED (symbolP
)
2611 && S_GET_SEGMENT (symbolP
) != reg_section
)
2612 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2614 pseudo_set (symbolP
);
2616 demand_empty_rest_of_line ();
2618 /* XXX Now we come to the Thumb specific bit of code. */
2620 THUMB_SET_FUNC (symbolP
, 1);
2621 ARM_SET_THUMB (symbolP
, 1);
2622 #if defined OBJ_ELF || defined OBJ_COFF
2623 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2627 /* Directives: Mode selection. */
2629 /* .syntax [unified|divided] - choose the new unified syntax
2630 (same for Arm and Thumb encoding, modulo slight differences in what
2631 can be represented) or the old divergent syntax for each mode. */
2633 s_syntax (int unused ATTRIBUTE_UNUSED
)
2637 name
= input_line_pointer
;
2638 delim
= get_symbol_end ();
2640 if (!strcasecmp (name
, "unified"))
2641 unified_syntax
= TRUE
;
2642 else if (!strcasecmp (name
, "divided"))
2643 unified_syntax
= FALSE
;
2646 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2649 *input_line_pointer
= delim
;
2650 demand_empty_rest_of_line ();
2653 /* Directives: sectioning and alignment. */
2655 /* Same as s_align_ptwo but align 0 => align 2. */
2658 s_align (int unused ATTRIBUTE_UNUSED
)
2663 long max_alignment
= 15;
2665 temp
= get_absolute_expression ();
2666 if (temp
> max_alignment
)
2667 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2670 as_bad (_("alignment negative. 0 assumed."));
2674 if (*input_line_pointer
== ',')
2676 input_line_pointer
++;
2677 temp_fill
= get_absolute_expression ();
2689 /* Only make a frag if we HAVE to. */
2690 if (temp
&& !need_pass_2
)
2692 if (!fill_p
&& subseg_text_p (now_seg
))
2693 frag_align_code (temp
, 0);
2695 frag_align (temp
, (int) temp_fill
, 0);
2697 demand_empty_rest_of_line ();
2699 record_alignment (now_seg
, temp
);
2703 s_bss (int ignore ATTRIBUTE_UNUSED
)
2705 /* We don't support putting frags in the BSS segment, we fake it by
2706 marking in_bss, then looking at s_skip for clues. */
2707 subseg_set (bss_section
, 0);
2708 demand_empty_rest_of_line ();
2709 mapping_state (MAP_DATA
);
2713 s_even (int ignore ATTRIBUTE_UNUSED
)
2715 /* Never make frag if expect extra pass. */
2717 frag_align (1, 0, 0);
2719 record_alignment (now_seg
, 1);
2721 demand_empty_rest_of_line ();
2724 /* Directives: Literal pools. */
2726 static literal_pool
*
2727 find_literal_pool (void)
2729 literal_pool
* pool
;
2731 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2733 if (pool
->section
== now_seg
2734 && pool
->sub_section
== now_subseg
)
2741 static literal_pool
*
2742 find_or_make_literal_pool (void)
2744 /* Next literal pool ID number. */
2745 static unsigned int latest_pool_num
= 1;
2746 literal_pool
* pool
;
2748 pool
= find_literal_pool ();
2752 /* Create a new pool. */
2753 pool
= xmalloc (sizeof (* pool
));
2757 pool
->next_free_entry
= 0;
2758 pool
->section
= now_seg
;
2759 pool
->sub_section
= now_subseg
;
2760 pool
->next
= list_of_pools
;
2761 pool
->symbol
= NULL
;
2763 /* Add it to the list. */
2764 list_of_pools
= pool
;
2767 /* New pools, and emptied pools, will have a NULL symbol. */
2768 if (pool
->symbol
== NULL
)
2770 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2771 (valueT
) 0, &zero_address_frag
);
2772 pool
->id
= latest_pool_num
++;
2779 /* Add the literal in the global 'inst'
2780 structure to the relevant literal pool. */
2783 add_to_lit_pool (void)
2785 literal_pool
* pool
;
2788 pool
= find_or_make_literal_pool ();
2790 /* Check if this literal value is already in the pool. */
2791 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2793 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2794 && (inst
.reloc
.exp
.X_op
== O_constant
)
2795 && (pool
->literals
[entry
].X_add_number
2796 == inst
.reloc
.exp
.X_add_number
)
2797 && (pool
->literals
[entry
].X_unsigned
2798 == inst
.reloc
.exp
.X_unsigned
))
2801 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2802 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2803 && (pool
->literals
[entry
].X_add_number
2804 == inst
.reloc
.exp
.X_add_number
)
2805 && (pool
->literals
[entry
].X_add_symbol
2806 == inst
.reloc
.exp
.X_add_symbol
)
2807 && (pool
->literals
[entry
].X_op_symbol
2808 == inst
.reloc
.exp
.X_op_symbol
))
2812 /* Do we need to create a new entry? */
2813 if (entry
== pool
->next_free_entry
)
2815 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2817 inst
.error
= _("literal pool overflow");
2821 pool
->literals
[entry
] = inst
.reloc
.exp
;
2822 pool
->next_free_entry
+= 1;
2825 inst
.reloc
.exp
.X_op
= O_symbol
;
2826 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2827 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2832 /* Can't use symbol_new here, so have to create a symbol and then at
2833 a later date assign it a value. Thats what these functions do. */
2836 symbol_locate (symbolS
* symbolP
,
2837 const char * name
, /* It is copied, the caller can modify. */
2838 segT segment
, /* Segment identifier (SEG_<something>). */
2839 valueT valu
, /* Symbol value. */
2840 fragS
* frag
) /* Associated fragment. */
2842 unsigned int name_length
;
2843 char * preserved_copy_of_name
;
2845 name_length
= strlen (name
) + 1; /* +1 for \0. */
2846 obstack_grow (¬es
, name
, name_length
);
2847 preserved_copy_of_name
= obstack_finish (¬es
);
2849 #ifdef tc_canonicalize_symbol_name
2850 preserved_copy_of_name
=
2851 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2854 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2856 S_SET_SEGMENT (symbolP
, segment
);
2857 S_SET_VALUE (symbolP
, valu
);
2858 symbol_clear_list_pointers (symbolP
);
2860 symbol_set_frag (symbolP
, frag
);
2862 /* Link to end of symbol chain. */
2864 extern int symbol_table_frozen
;
2866 if (symbol_table_frozen
)
2870 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2872 obj_symbol_new_hook (symbolP
);
2874 #ifdef tc_symbol_new_hook
2875 tc_symbol_new_hook (symbolP
);
2879 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2880 #endif /* DEBUG_SYMS */
2885 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2888 literal_pool
* pool
;
2891 pool
= find_literal_pool ();
2893 || pool
->symbol
== NULL
2894 || pool
->next_free_entry
== 0)
2897 mapping_state (MAP_DATA
);
2899 /* Align pool as you have word accesses.
2900 Only make a frag if we have to. */
2902 frag_align (2, 0, 0);
2904 record_alignment (now_seg
, 2);
2906 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2908 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2909 (valueT
) frag_now_fix (), frag_now
);
2910 symbol_table_insert (pool
->symbol
);
2912 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2914 #if defined OBJ_COFF || defined OBJ_ELF
2915 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2918 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2919 /* First output the expression in the instruction to the pool. */
2920 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2922 /* Mark the pool as empty. */
2923 pool
->next_free_entry
= 0;
2924 pool
->symbol
= NULL
;
2928 /* Forward declarations for functions below, in the MD interface
2930 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2931 static valueT
create_unwind_entry (int);
2932 static void start_unwind_section (const segT
, int);
2933 static void add_unwind_opcode (valueT
, int);
2934 static void flush_pending_unwind (void);
2936 /* Directives: Data. */
2939 s_arm_elf_cons (int nbytes
)
2943 #ifdef md_flush_pending_output
2944 md_flush_pending_output ();
2947 if (is_it_end_of_statement ())
2949 demand_empty_rest_of_line ();
2953 #ifdef md_cons_align
2954 md_cons_align (nbytes
);
2957 mapping_state (MAP_DATA
);
2961 char *base
= input_line_pointer
;
2965 if (exp
.X_op
!= O_symbol
)
2966 emit_expr (&exp
, (unsigned int) nbytes
);
2969 char *before_reloc
= input_line_pointer
;
2970 reloc
= parse_reloc (&input_line_pointer
);
2973 as_bad (_("unrecognized relocation suffix"));
2974 ignore_rest_of_line ();
2977 else if (reloc
== BFD_RELOC_UNUSED
)
2978 emit_expr (&exp
, (unsigned int) nbytes
);
2981 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2982 int size
= bfd_get_reloc_size (howto
);
2984 if (reloc
== BFD_RELOC_ARM_PLT32
)
2986 as_bad (_("(plt) is only valid on branch targets"));
2987 reloc
= BFD_RELOC_UNUSED
;
2992 as_bad (_("%s relocations do not fit in %d bytes"),
2993 howto
->name
, nbytes
);
2996 /* We've parsed an expression stopping at O_symbol.
2997 But there may be more expression left now that we
2998 have parsed the relocation marker. Parse it again.
2999 XXX Surely there is a cleaner way to do this. */
3000 char *p
= input_line_pointer
;
3002 char *save_buf
= alloca (input_line_pointer
- base
);
3003 memcpy (save_buf
, base
, input_line_pointer
- base
);
3004 memmove (base
+ (input_line_pointer
- before_reloc
),
3005 base
, before_reloc
- base
);
3007 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3009 memcpy (base
, save_buf
, p
- base
);
3011 offset
= nbytes
- size
;
3012 p
= frag_more ((int) nbytes
);
3013 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3014 size
, &exp
, 0, reloc
);
3019 while (*input_line_pointer
++ == ',');
3021 /* Put terminator back into stream. */
3022 input_line_pointer
--;
3023 demand_empty_rest_of_line ();
3027 /* Parse a .rel31 directive. */
3030 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3037 if (*input_line_pointer
== '1')
3038 highbit
= 0x80000000;
3039 else if (*input_line_pointer
!= '0')
3040 as_bad (_("expected 0 or 1"));
3042 input_line_pointer
++;
3043 if (*input_line_pointer
!= ',')
3044 as_bad (_("missing comma"));
3045 input_line_pointer
++;
3047 #ifdef md_flush_pending_output
3048 md_flush_pending_output ();
3051 #ifdef md_cons_align
3055 mapping_state (MAP_DATA
);
3060 md_number_to_chars (p
, highbit
, 4);
3061 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3062 BFD_RELOC_ARM_PREL31
);
3064 demand_empty_rest_of_line ();
3067 /* Directives: AEABI stack-unwind tables. */
3069 /* Parse an unwind_fnstart directive. Simply records the current location. */
3072 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3074 demand_empty_rest_of_line ();
3075 /* Mark the start of the function. */
3076 unwind
.proc_start
= expr_build_dot ();
3078 /* Reset the rest of the unwind info. */
3079 unwind
.opcode_count
= 0;
3080 unwind
.table_entry
= NULL
;
3081 unwind
.personality_routine
= NULL
;
3082 unwind
.personality_index
= -1;
3083 unwind
.frame_size
= 0;
3084 unwind
.fp_offset
= 0;
3087 unwind
.sp_restored
= 0;
3091 /* Parse a handlerdata directive. Creates the exception handling table entry
3092 for the function. */
3095 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3097 demand_empty_rest_of_line ();
3098 if (unwind
.table_entry
)
3099 as_bad (_("duplicate .handlerdata directive"));
3101 create_unwind_entry (1);
3104 /* Parse an unwind_fnend directive. Generates the index table entry. */
3107 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3113 demand_empty_rest_of_line ();
3115 /* Add eh table entry. */
3116 if (unwind
.table_entry
== NULL
)
3117 val
= create_unwind_entry (0);
3121 /* Add index table entry. This is two words. */
3122 start_unwind_section (unwind
.saved_seg
, 1);
3123 frag_align (2, 0, 0);
3124 record_alignment (now_seg
, 2);
3126 ptr
= frag_more (8);
3127 where
= frag_now_fix () - 8;
3129 /* Self relative offset of the function start. */
3130 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3131 BFD_RELOC_ARM_PREL31
);
3133 /* Indicate dependency on EHABI-defined personality routines to the
3134 linker, if it hasn't been done already. */
3135 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3136 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3138 static const char *const name
[] =
3140 "__aeabi_unwind_cpp_pr0",
3141 "__aeabi_unwind_cpp_pr1",
3142 "__aeabi_unwind_cpp_pr2"
3144 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3145 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3146 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3147 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3148 = marked_pr_dependency
;
3152 /* Inline exception table entry. */
3153 md_number_to_chars (ptr
+ 4, val
, 4);
3155 /* Self relative offset of the table entry. */
3156 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3157 BFD_RELOC_ARM_PREL31
);
3159 /* Restore the original section. */
3160 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3164 /* Parse an unwind_cantunwind directive. */
3167 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3169 demand_empty_rest_of_line ();
3170 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3171 as_bad (_("personality routine specified for cantunwind frame"));
3173 unwind
.personality_index
= -2;
3177 /* Parse a personalityindex directive. */
3180 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3184 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3185 as_bad (_("duplicate .personalityindex directive"));
3189 if (exp
.X_op
!= O_constant
3190 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3192 as_bad (_("bad personality routine number"));
3193 ignore_rest_of_line ();
3197 unwind
.personality_index
= exp
.X_add_number
;
3199 demand_empty_rest_of_line ();
3203 /* Parse a personality directive. */
3206 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3210 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3211 as_bad (_("duplicate .personality directive"));
3213 name
= input_line_pointer
;
3214 c
= get_symbol_end ();
3215 p
= input_line_pointer
;
3216 unwind
.personality_routine
= symbol_find_or_make (name
);
3218 demand_empty_rest_of_line ();
3222 /* Parse a directive saving core registers. */
3225 s_arm_unwind_save_core (void)
3231 range
= parse_reg_list (&input_line_pointer
);
3234 as_bad (_("expected register list"));
3235 ignore_rest_of_line ();
3239 demand_empty_rest_of_line ();
3241 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3242 into .unwind_save {..., sp...}. We aren't bothered about the value of
3243 ip because it is clobbered by calls. */
3244 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3245 && (range
& 0x3000) == 0x1000)
3247 unwind
.opcode_count
--;
3248 unwind
.sp_restored
= 0;
3249 range
= (range
| 0x2000) & ~0x1000;
3250 unwind
.pending_offset
= 0;
3256 /* See if we can use the short opcodes. These pop a block of up to 8
3257 registers starting with r4, plus maybe r14. */
3258 for (n
= 0; n
< 8; n
++)
3260 /* Break at the first non-saved register. */
3261 if ((range
& (1 << (n
+ 4))) == 0)
3264 /* See if there are any other bits set. */
3265 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3267 /* Use the long form. */
3268 op
= 0x8000 | ((range
>> 4) & 0xfff);
3269 add_unwind_opcode (op
, 2);
3273 /* Use the short form. */
3275 op
= 0xa8; /* Pop r14. */
3277 op
= 0xa0; /* Do not pop r14. */
3279 add_unwind_opcode (op
, 1);
3286 op
= 0xb100 | (range
& 0xf);
3287 add_unwind_opcode (op
, 2);
3290 /* Record the number of bytes pushed. */
3291 for (n
= 0; n
< 16; n
++)
3293 if (range
& (1 << n
))
3294 unwind
.frame_size
+= 4;
3299 /* Parse a directive saving FPA registers. */
3302 s_arm_unwind_save_fpa (int reg
)
3308 /* Get Number of registers to transfer. */
3309 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3312 exp
.X_op
= O_illegal
;
3314 if (exp
.X_op
!= O_constant
)
3316 as_bad (_("expected , <constant>"));
3317 ignore_rest_of_line ();
3321 num_regs
= exp
.X_add_number
;
3323 if (num_regs
< 1 || num_regs
> 4)
3325 as_bad (_("number of registers must be in the range [1:4]"));
3326 ignore_rest_of_line ();
3330 demand_empty_rest_of_line ();
3335 op
= 0xb4 | (num_regs
- 1);
3336 add_unwind_opcode (op
, 1);
3341 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3342 add_unwind_opcode (op
, 2);
3344 unwind
.frame_size
+= num_regs
* 12;
3348 /* Parse a directive saving VFP registers for ARMv6 and above. */
3351 s_arm_unwind_save_vfp_armv6 (void)
3356 int num_vfpv3_regs
= 0;
3357 int num_regs_below_16
;
3359 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3362 as_bad (_("expected register list"));
3363 ignore_rest_of_line ();
3367 demand_empty_rest_of_line ();
3369 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3370 than FSTMX/FLDMX-style ones). */
3372 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3374 num_vfpv3_regs
= count
;
3375 else if (start
+ count
> 16)
3376 num_vfpv3_regs
= start
+ count
- 16;
3378 if (num_vfpv3_regs
> 0)
3380 int start_offset
= start
> 16 ? start
- 16 : 0;
3381 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3382 add_unwind_opcode (op
, 2);
3385 /* Generate opcode for registers numbered in the range 0 .. 15. */
3386 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3387 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3388 if (num_regs_below_16
> 0)
3390 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3391 add_unwind_opcode (op
, 2);
3394 unwind
.frame_size
+= count
* 8;
3398 /* Parse a directive saving VFP registers for pre-ARMv6. */
3401 s_arm_unwind_save_vfp (void)
3407 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3410 as_bad (_("expected register list"));
3411 ignore_rest_of_line ();
3415 demand_empty_rest_of_line ();
3420 op
= 0xb8 | (count
- 1);
3421 add_unwind_opcode (op
, 1);
3426 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3427 add_unwind_opcode (op
, 2);
3429 unwind
.frame_size
+= count
* 8 + 4;
3433 /* Parse a directive saving iWMMXt data registers. */
3436 s_arm_unwind_save_mmxwr (void)
3444 if (*input_line_pointer
== '{')
3445 input_line_pointer
++;
3449 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3453 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3458 as_tsktsk (_("register list not in ascending order"));
3461 if (*input_line_pointer
== '-')
3463 input_line_pointer
++;
3464 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3467 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3470 else if (reg
>= hi_reg
)
3472 as_bad (_("bad register range"));
3475 for (; reg
< hi_reg
; reg
++)
3479 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3481 if (*input_line_pointer
== '}')
3482 input_line_pointer
++;
3484 demand_empty_rest_of_line ();
3486 /* Generate any deferred opcodes because we're going to be looking at
3488 flush_pending_unwind ();
3490 for (i
= 0; i
< 16; i
++)
3492 if (mask
& (1 << i
))
3493 unwind
.frame_size
+= 8;
3496 /* Attempt to combine with a previous opcode. We do this because gcc
3497 likes to output separate unwind directives for a single block of
3499 if (unwind
.opcode_count
> 0)
3501 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3502 if ((i
& 0xf8) == 0xc0)
3505 /* Only merge if the blocks are contiguous. */
3508 if ((mask
& 0xfe00) == (1 << 9))
3510 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3511 unwind
.opcode_count
--;
3514 else if (i
== 6 && unwind
.opcode_count
>= 2)
3516 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3520 op
= 0xffff << (reg
- 1);
3522 && ((mask
& op
) == (1u << (reg
- 1))))
3524 op
= (1 << (reg
+ i
+ 1)) - 1;
3525 op
&= ~((1 << reg
) - 1);
3527 unwind
.opcode_count
-= 2;
3534 /* We want to generate opcodes in the order the registers have been
3535 saved, ie. descending order. */
3536 for (reg
= 15; reg
>= -1; reg
--)
3538 /* Save registers in blocks. */
3540 || !(mask
& (1 << reg
)))
3542 /* We found an unsaved reg. Generate opcodes to save the
3549 op
= 0xc0 | (hi_reg
- 10);
3550 add_unwind_opcode (op
, 1);
3555 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3556 add_unwind_opcode (op
, 2);
3565 ignore_rest_of_line ();
3569 s_arm_unwind_save_mmxwcg (void)
3576 if (*input_line_pointer
== '{')
3577 input_line_pointer
++;
3581 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3585 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3591 as_tsktsk (_("register list not in ascending order"));
3594 if (*input_line_pointer
== '-')
3596 input_line_pointer
++;
3597 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3600 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3603 else if (reg
>= hi_reg
)
3605 as_bad (_("bad register range"));
3608 for (; reg
< hi_reg
; reg
++)
3612 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3614 if (*input_line_pointer
== '}')
3615 input_line_pointer
++;
3617 demand_empty_rest_of_line ();
3619 /* Generate any deferred opcodes because we're going to be looking at
3621 flush_pending_unwind ();
3623 for (reg
= 0; reg
< 16; reg
++)
3625 if (mask
& (1 << reg
))
3626 unwind
.frame_size
+= 4;
3629 add_unwind_opcode (op
, 2);
3632 ignore_rest_of_line ();
3636 /* Parse an unwind_save directive.
3637 If the argument is non-zero, this is a .vsave directive. */
3640 s_arm_unwind_save (int arch_v6
)
3643 struct reg_entry
*reg
;
3644 bfd_boolean had_brace
= FALSE
;
3646 /* Figure out what sort of save we have. */
3647 peek
= input_line_pointer
;
3655 reg
= arm_reg_parse_multi (&peek
);
3659 as_bad (_("register expected"));
3660 ignore_rest_of_line ();
3669 as_bad (_("FPA .unwind_save does not take a register list"));
3670 ignore_rest_of_line ();
3673 s_arm_unwind_save_fpa (reg
->number
);
3676 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3679 s_arm_unwind_save_vfp_armv6 ();
3681 s_arm_unwind_save_vfp ();
3683 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3684 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3687 as_bad (_(".unwind_save does not support this kind of register"));
3688 ignore_rest_of_line ();
3693 /* Parse an unwind_movsp directive. */
3696 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3702 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3705 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3706 ignore_rest_of_line ();
3710 /* Optional constant. */
3711 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3713 if (immediate_for_directive (&offset
) == FAIL
)
3719 demand_empty_rest_of_line ();
3721 if (reg
== REG_SP
|| reg
== REG_PC
)
3723 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3727 if (unwind
.fp_reg
!= REG_SP
)
3728 as_bad (_("unexpected .unwind_movsp directive"));
3730 /* Generate opcode to restore the value. */
3732 add_unwind_opcode (op
, 1);
3734 /* Record the information for later. */
3735 unwind
.fp_reg
= reg
;
3736 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3737 unwind
.sp_restored
= 1;
3740 /* Parse an unwind_pad directive. */
3743 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3747 if (immediate_for_directive (&offset
) == FAIL
)
3752 as_bad (_("stack increment must be multiple of 4"));
3753 ignore_rest_of_line ();
3757 /* Don't generate any opcodes, just record the details for later. */
3758 unwind
.frame_size
+= offset
;
3759 unwind
.pending_offset
+= offset
;
3761 demand_empty_rest_of_line ();
3764 /* Parse an unwind_setfp directive. */
3767 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3773 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3774 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3777 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3779 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3781 as_bad (_("expected <reg>, <reg>"));
3782 ignore_rest_of_line ();
3786 /* Optional constant. */
3787 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3789 if (immediate_for_directive (&offset
) == FAIL
)
3795 demand_empty_rest_of_line ();
3797 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3799 as_bad (_("register must be either sp or set by a previous"
3800 "unwind_movsp directive"));
3804 /* Don't generate any opcodes, just record the information for later. */
3805 unwind
.fp_reg
= fp_reg
;
3808 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3810 unwind
.fp_offset
-= offset
;
3813 /* Parse an unwind_raw directive. */
3816 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3819 /* This is an arbitrary limit. */
3820 unsigned char op
[16];
3824 if (exp
.X_op
== O_constant
3825 && skip_past_comma (&input_line_pointer
) != FAIL
)
3827 unwind
.frame_size
+= exp
.X_add_number
;
3831 exp
.X_op
= O_illegal
;
3833 if (exp
.X_op
!= O_constant
)
3835 as_bad (_("expected <offset>, <opcode>"));
3836 ignore_rest_of_line ();
3842 /* Parse the opcode. */
3847 as_bad (_("unwind opcode too long"));
3848 ignore_rest_of_line ();
3850 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3852 as_bad (_("invalid unwind opcode"));
3853 ignore_rest_of_line ();
3856 op
[count
++] = exp
.X_add_number
;
3858 /* Parse the next byte. */
3859 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3865 /* Add the opcode bytes in reverse order. */
3867 add_unwind_opcode (op
[count
], 1);
3869 demand_empty_rest_of_line ();
3873 /* Parse a .eabi_attribute directive. */
3876 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3878 s_vendor_attribute (OBJ_ATTR_PROC
);
3880 #endif /* OBJ_ELF */
3882 static void s_arm_arch (int);
3883 static void s_arm_object_arch (int);
3884 static void s_arm_cpu (int);
3885 static void s_arm_fpu (int);
3890 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3897 if (exp
.X_op
== O_symbol
)
3898 exp
.X_op
= O_secrel
;
3900 emit_expr (&exp
, 4);
3902 while (*input_line_pointer
++ == ',');
3904 input_line_pointer
--;
3905 demand_empty_rest_of_line ();
3909 /* This table describes all the machine specific pseudo-ops the assembler
3910 has to support. The fields are:
3911 pseudo-op name without dot
3912 function to call to execute this pseudo-op
3913 Integer arg to pass to the function. */
3915 const pseudo_typeS md_pseudo_table
[] =
3917 /* Never called because '.req' does not start a line. */
3918 { "req", s_req
, 0 },
3919 /* Following two are likewise never called. */
3922 { "unreq", s_unreq
, 0 },
3923 { "bss", s_bss
, 0 },
3924 { "align", s_align
, 0 },
3925 { "arm", s_arm
, 0 },
3926 { "thumb", s_thumb
, 0 },
3927 { "code", s_code
, 0 },
3928 { "force_thumb", s_force_thumb
, 0 },
3929 { "thumb_func", s_thumb_func
, 0 },
3930 { "thumb_set", s_thumb_set
, 0 },
3931 { "even", s_even
, 0 },
3932 { "ltorg", s_ltorg
, 0 },
3933 { "pool", s_ltorg
, 0 },
3934 { "syntax", s_syntax
, 0 },
3935 { "cpu", s_arm_cpu
, 0 },
3936 { "arch", s_arm_arch
, 0 },
3937 { "object_arch", s_arm_object_arch
, 0 },
3938 { "fpu", s_arm_fpu
, 0 },
3940 { "word", s_arm_elf_cons
, 4 },
3941 { "long", s_arm_elf_cons
, 4 },
3942 { "rel31", s_arm_rel31
, 0 },
3943 { "fnstart", s_arm_unwind_fnstart
, 0 },
3944 { "fnend", s_arm_unwind_fnend
, 0 },
3945 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3946 { "personality", s_arm_unwind_personality
, 0 },
3947 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3948 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3949 { "save", s_arm_unwind_save
, 0 },
3950 { "vsave", s_arm_unwind_save
, 1 },
3951 { "movsp", s_arm_unwind_movsp
, 0 },
3952 { "pad", s_arm_unwind_pad
, 0 },
3953 { "setfp", s_arm_unwind_setfp
, 0 },
3954 { "unwind_raw", s_arm_unwind_raw
, 0 },
3955 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3959 /* These are used for dwarf. */
3963 /* These are used for dwarf2. */
3964 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3965 { "loc", dwarf2_directive_loc
, 0 },
3966 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3968 { "extend", float_cons
, 'x' },
3969 { "ldouble", float_cons
, 'x' },
3970 { "packed", float_cons
, 'p' },
3972 {"secrel32", pe_directive_secrel
, 0},
3977 /* Parser functions used exclusively in instruction operands. */
3979 /* Generic immediate-value read function for use in insn parsing.
3980 STR points to the beginning of the immediate (the leading #);
3981 VAL receives the value; if the value is outside [MIN, MAX]
3982 issue an error. PREFIX_OPT is true if the immediate prefix is
3986 parse_immediate (char **str
, int *val
, int min
, int max
,
3987 bfd_boolean prefix_opt
)
3990 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3991 if (exp
.X_op
!= O_constant
)
3993 inst
.error
= _("constant expression required");
3997 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
3999 inst
.error
= _("immediate value out of range");
4003 *val
= exp
.X_add_number
;
4007 /* Less-generic immediate-value read function with the possibility of loading a
4008 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4009 instructions. Puts the result directly in inst.operands[i]. */
4012 parse_big_immediate (char **str
, int i
)
4017 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4019 if (exp
.X_op
== O_constant
)
4021 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4022 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4023 O_constant. We have to be careful not to break compilation for
4024 32-bit X_add_number, though. */
4025 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4027 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4028 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4029 inst
.operands
[i
].regisimm
= 1;
4032 else if (exp
.X_op
== O_big
4033 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4034 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4036 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4037 /* Bignums have their least significant bits in
4038 generic_bignum[0]. Make sure we put 32 bits in imm and
4039 32 bits in reg, in a (hopefully) portable way. */
4040 assert (parts
!= 0);
4041 inst
.operands
[i
].imm
= 0;
4042 for (j
= 0; j
< parts
; j
++, idx
++)
4043 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4044 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4045 inst
.operands
[i
].reg
= 0;
4046 for (j
= 0; j
< parts
; j
++, idx
++)
4047 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4048 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4049 inst
.operands
[i
].regisimm
= 1;
4059 /* Returns the pseudo-register number of an FPA immediate constant,
4060 or FAIL if there isn't a valid constant here. */
4063 parse_fpa_immediate (char ** str
)
4065 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4071 /* First try and match exact strings, this is to guarantee
4072 that some formats will work even for cross assembly. */
4074 for (i
= 0; fp_const
[i
]; i
++)
4076 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4080 *str
+= strlen (fp_const
[i
]);
4081 if (is_end_of_line
[(unsigned char) **str
])
4087 /* Just because we didn't get a match doesn't mean that the constant
4088 isn't valid, just that it is in a format that we don't
4089 automatically recognize. Try parsing it with the standard
4090 expression routines. */
4092 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4094 /* Look for a raw floating point number. */
4095 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4096 && is_end_of_line
[(unsigned char) *save_in
])
4098 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4100 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4102 if (words
[j
] != fp_values
[i
][j
])
4106 if (j
== MAX_LITTLENUMS
)
4114 /* Try and parse a more complex expression, this will probably fail
4115 unless the code uses a floating point prefix (eg "0f"). */
4116 save_in
= input_line_pointer
;
4117 input_line_pointer
= *str
;
4118 if (expression (&exp
) == absolute_section
4119 && exp
.X_op
== O_big
4120 && exp
.X_add_number
< 0)
4122 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4124 if (gen_to_words (words
, 5, (long) 15) == 0)
4126 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4128 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4130 if (words
[j
] != fp_values
[i
][j
])
4134 if (j
== MAX_LITTLENUMS
)
4136 *str
= input_line_pointer
;
4137 input_line_pointer
= save_in
;
4144 *str
= input_line_pointer
;
4145 input_line_pointer
= save_in
;
4146 inst
.error
= _("invalid FPA immediate expression");
4150 /* Returns 1 if a number has "quarter-precision" float format
4151 0baBbbbbbc defgh000 00000000 00000000. */
4154 is_quarter_float (unsigned imm
)
4156 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4157 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4160 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4161 0baBbbbbbc defgh000 00000000 00000000.
4162 The zero and minus-zero cases need special handling, since they can't be
4163 encoded in the "quarter-precision" float format, but can nonetheless be
4164 loaded as integer constants. */
4167 parse_qfloat_immediate (char **ccp
, int *immed
)
4171 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4172 int found_fpchar
= 0;
4174 skip_past_char (&str
, '#');
4176 /* We must not accidentally parse an integer as a floating-point number. Make
4177 sure that the value we parse is not an integer by checking for special
4178 characters '.' or 'e'.
4179 FIXME: This is a horrible hack, but doing better is tricky because type
4180 information isn't in a very usable state at parse time. */
4182 skip_whitespace (fpnum
);
4184 if (strncmp (fpnum
, "0x", 2) == 0)
4188 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4189 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4199 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4201 unsigned fpword
= 0;
4204 /* Our FP word must be 32 bits (single-precision FP). */
4205 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4207 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4211 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4224 /* Shift operands. */
4227 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4230 struct asm_shift_name
4233 enum shift_kind kind
;
4236 /* Third argument to parse_shift. */
4237 enum parse_shift_mode
4239 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4240 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4241 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4242 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4243 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4246 /* Parse a <shift> specifier on an ARM data processing instruction.
4247 This has three forms:
4249 (LSL|LSR|ASL|ASR|ROR) Rs
4250 (LSL|LSR|ASL|ASR|ROR) #imm
4253 Note that ASL is assimilated to LSL in the instruction encoding, and
4254 RRX to ROR #0 (which cannot be written as such). */
4257 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4259 const struct asm_shift_name
*shift_name
;
4260 enum shift_kind shift
;
4265 for (p
= *str
; ISALPHA (*p
); p
++)
4270 inst
.error
= _("shift expression expected");
4274 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4276 if (shift_name
== NULL
)
4278 inst
.error
= _("shift expression expected");
4282 shift
= shift_name
->kind
;
4286 case NO_SHIFT_RESTRICT
:
4287 case SHIFT_IMMEDIATE
: break;
4289 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4290 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4292 inst
.error
= _("'LSL' or 'ASR' required");
4297 case SHIFT_LSL_IMMEDIATE
:
4298 if (shift
!= SHIFT_LSL
)
4300 inst
.error
= _("'LSL' required");
4305 case SHIFT_ASR_IMMEDIATE
:
4306 if (shift
!= SHIFT_ASR
)
4308 inst
.error
= _("'ASR' required");
4316 if (shift
!= SHIFT_RRX
)
4318 /* Whitespace can appear here if the next thing is a bare digit. */
4319 skip_whitespace (p
);
4321 if (mode
== NO_SHIFT_RESTRICT
4322 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4324 inst
.operands
[i
].imm
= reg
;
4325 inst
.operands
[i
].immisreg
= 1;
4327 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4330 inst
.operands
[i
].shift_kind
= shift
;
4331 inst
.operands
[i
].shifted
= 1;
4336 /* Parse a <shifter_operand> for an ARM data processing instruction:
4339 #<immediate>, <rotate>
4343 where <shift> is defined by parse_shift above, and <rotate> is a
4344 multiple of 2 between 0 and 30. Validation of immediate operands
4345 is deferred to md_apply_fix. */
4348 parse_shifter_operand (char **str
, int i
)
4353 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4355 inst
.operands
[i
].reg
= value
;
4356 inst
.operands
[i
].isreg
= 1;
4358 /* parse_shift will override this if appropriate */
4359 inst
.reloc
.exp
.X_op
= O_constant
;
4360 inst
.reloc
.exp
.X_add_number
= 0;
4362 if (skip_past_comma (str
) == FAIL
)
4365 /* Shift operation on register. */
4366 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4369 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4372 if (skip_past_comma (str
) == SUCCESS
)
4374 /* #x, y -- ie explicit rotation by Y. */
4375 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4378 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4380 inst
.error
= _("constant expression expected");
4384 value
= expr
.X_add_number
;
4385 if (value
< 0 || value
> 30 || value
% 2 != 0)
4387 inst
.error
= _("invalid rotation");
4390 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4392 inst
.error
= _("invalid constant");
4396 /* Convert to decoded value. md_apply_fix will put it back. */
4397 inst
.reloc
.exp
.X_add_number
4398 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4399 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4402 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4403 inst
.reloc
.pc_rel
= 0;
4407 /* Group relocation information. Each entry in the table contains the
4408 textual name of the relocation as may appear in assembler source
4409 and must end with a colon.
4410 Along with this textual name are the relocation codes to be used if
4411 the corresponding instruction is an ALU instruction (ADD or SUB only),
4412 an LDR, an LDRS, or an LDC. */
4414 struct group_reloc_table_entry
4425 /* Varieties of non-ALU group relocation. */
4432 static struct group_reloc_table_entry group_reloc_table
[] =
4433 { /* Program counter relative: */
4435 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4440 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4441 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4442 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4443 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4445 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4450 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4451 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4452 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4453 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4455 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4456 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4457 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4458 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4459 /* Section base relative */
4461 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4466 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4467 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4468 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4469 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4471 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4476 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4477 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4478 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4479 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4481 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4482 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4483 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4484 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4486 /* Given the address of a pointer pointing to the textual name of a group
4487 relocation as may appear in assembler source, attempt to find its details
4488 in group_reloc_table. The pointer will be updated to the character after
4489 the trailing colon. On failure, FAIL will be returned; SUCCESS
4490 otherwise. On success, *entry will be updated to point at the relevant
4491 group_reloc_table entry. */
4494 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4497 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4499 int length
= strlen (group_reloc_table
[i
].name
);
4501 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4502 && (*str
)[length
] == ':')
4504 *out
= &group_reloc_table
[i
];
4505 *str
+= (length
+ 1);
4513 /* Parse a <shifter_operand> for an ARM data processing instruction
4514 (as for parse_shifter_operand) where group relocations are allowed:
4517 #<immediate>, <rotate>
4518 #:<group_reloc>:<expression>
4522 where <group_reloc> is one of the strings defined in group_reloc_table.
4523 The hashes are optional.
4525 Everything else is as for parse_shifter_operand. */
4527 static parse_operand_result
4528 parse_shifter_operand_group_reloc (char **str
, int i
)
4530 /* Determine if we have the sequence of characters #: or just :
4531 coming next. If we do, then we check for a group relocation.
4532 If we don't, punt the whole lot to parse_shifter_operand. */
4534 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4535 || (*str
)[0] == ':')
4537 struct group_reloc_table_entry
*entry
;
4539 if ((*str
)[0] == '#')
4544 /* Try to parse a group relocation. Anything else is an error. */
4545 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4547 inst
.error
= _("unknown group relocation");
4548 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4551 /* We now have the group relocation table entry corresponding to
4552 the name in the assembler source. Next, we parse the expression. */
4553 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4554 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4556 /* Record the relocation type (always the ALU variant here). */
4557 inst
.reloc
.type
= entry
->alu_code
;
4558 assert (inst
.reloc
.type
!= 0);
4560 return PARSE_OPERAND_SUCCESS
;
4563 return parse_shifter_operand (str
, i
) == SUCCESS
4564 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4566 /* Never reached. */
4569 /* Parse all forms of an ARM address expression. Information is written
4570 to inst.operands[i] and/or inst.reloc.
4572 Preindexed addressing (.preind=1):
4574 [Rn, #offset] .reg=Rn .reloc.exp=offset
4575 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4576 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4577 .shift_kind=shift .reloc.exp=shift_imm
4579 These three may have a trailing ! which causes .writeback to be set also.
4581 Postindexed addressing (.postind=1, .writeback=1):
4583 [Rn], #offset .reg=Rn .reloc.exp=offset
4584 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4585 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4586 .shift_kind=shift .reloc.exp=shift_imm
4588 Unindexed addressing (.preind=0, .postind=0):
4590 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4594 [Rn]{!} shorthand for [Rn,#0]{!}
4595 =immediate .isreg=0 .reloc.exp=immediate
4596 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4598 It is the caller's responsibility to check for addressing modes not
4599 supported by the instruction, and to set inst.reloc.type. */
4601 static parse_operand_result
4602 parse_address_main (char **str
, int i
, int group_relocations
,
4603 group_reloc_type group_type
)
4608 if (skip_past_char (&p
, '[') == FAIL
)
4610 if (skip_past_char (&p
, '=') == FAIL
)
4612 /* bare address - translate to PC-relative offset */
4613 inst
.reloc
.pc_rel
= 1;
4614 inst
.operands
[i
].reg
= REG_PC
;
4615 inst
.operands
[i
].isreg
= 1;
4616 inst
.operands
[i
].preind
= 1;
4618 /* else a load-constant pseudo op, no special treatment needed here */
4620 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4621 return PARSE_OPERAND_FAIL
;
4624 return PARSE_OPERAND_SUCCESS
;
4627 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4629 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4630 return PARSE_OPERAND_FAIL
;
4632 inst
.operands
[i
].reg
= reg
;
4633 inst
.operands
[i
].isreg
= 1;
4635 if (skip_past_comma (&p
) == SUCCESS
)
4637 inst
.operands
[i
].preind
= 1;
4640 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4642 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4644 inst
.operands
[i
].imm
= reg
;
4645 inst
.operands
[i
].immisreg
= 1;
4647 if (skip_past_comma (&p
) == SUCCESS
)
4648 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4649 return PARSE_OPERAND_FAIL
;
4651 else if (skip_past_char (&p
, ':') == SUCCESS
)
4653 /* FIXME: '@' should be used here, but it's filtered out by generic
4654 code before we get to see it here. This may be subject to
4657 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4658 if (exp
.X_op
!= O_constant
)
4660 inst
.error
= _("alignment must be constant");
4661 return PARSE_OPERAND_FAIL
;
4663 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4664 inst
.operands
[i
].immisalign
= 1;
4665 /* Alignments are not pre-indexes. */
4666 inst
.operands
[i
].preind
= 0;
4670 if (inst
.operands
[i
].negative
)
4672 inst
.operands
[i
].negative
= 0;
4676 if (group_relocations
4677 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4679 struct group_reloc_table_entry
*entry
;
4681 /* Skip over the #: or : sequence. */
4687 /* Try to parse a group relocation. Anything else is an
4689 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4691 inst
.error
= _("unknown group relocation");
4692 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4695 /* We now have the group relocation table entry corresponding to
4696 the name in the assembler source. Next, we parse the
4698 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4699 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4701 /* Record the relocation type. */
4705 inst
.reloc
.type
= entry
->ldr_code
;
4709 inst
.reloc
.type
= entry
->ldrs_code
;
4713 inst
.reloc
.type
= entry
->ldc_code
;
4720 if (inst
.reloc
.type
== 0)
4722 inst
.error
= _("this group relocation is not allowed on this instruction");
4723 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4727 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4728 return PARSE_OPERAND_FAIL
;
4732 if (skip_past_char (&p
, ']') == FAIL
)
4734 inst
.error
= _("']' expected");
4735 return PARSE_OPERAND_FAIL
;
4738 if (skip_past_char (&p
, '!') == SUCCESS
)
4739 inst
.operands
[i
].writeback
= 1;
4741 else if (skip_past_comma (&p
) == SUCCESS
)
4743 if (skip_past_char (&p
, '{') == SUCCESS
)
4745 /* [Rn], {expr} - unindexed, with option */
4746 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4747 0, 255, TRUE
) == FAIL
)
4748 return PARSE_OPERAND_FAIL
;
4750 if (skip_past_char (&p
, '}') == FAIL
)
4752 inst
.error
= _("'}' expected at end of 'option' field");
4753 return PARSE_OPERAND_FAIL
;
4755 if (inst
.operands
[i
].preind
)
4757 inst
.error
= _("cannot combine index with option");
4758 return PARSE_OPERAND_FAIL
;
4761 return PARSE_OPERAND_SUCCESS
;
4765 inst
.operands
[i
].postind
= 1;
4766 inst
.operands
[i
].writeback
= 1;
4768 if (inst
.operands
[i
].preind
)
4770 inst
.error
= _("cannot combine pre- and post-indexing");
4771 return PARSE_OPERAND_FAIL
;
4775 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4777 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4779 /* We might be using the immediate for alignment already. If we
4780 are, OR the register number into the low-order bits. */
4781 if (inst
.operands
[i
].immisalign
)
4782 inst
.operands
[i
].imm
|= reg
;
4784 inst
.operands
[i
].imm
= reg
;
4785 inst
.operands
[i
].immisreg
= 1;
4787 if (skip_past_comma (&p
) == SUCCESS
)
4788 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4789 return PARSE_OPERAND_FAIL
;
4793 if (inst
.operands
[i
].negative
)
4795 inst
.operands
[i
].negative
= 0;
4798 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4799 return PARSE_OPERAND_FAIL
;
4804 /* If at this point neither .preind nor .postind is set, we have a
4805 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4806 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4808 inst
.operands
[i
].preind
= 1;
4809 inst
.reloc
.exp
.X_op
= O_constant
;
4810 inst
.reloc
.exp
.X_add_number
= 0;
4813 return PARSE_OPERAND_SUCCESS
;
4817 parse_address (char **str
, int i
)
4819 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4823 static parse_operand_result
4824 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4826 return parse_address_main (str
, i
, 1, type
);
4829 /* Parse an operand for a MOVW or MOVT instruction. */
4831 parse_half (char **str
)
4836 skip_past_char (&p
, '#');
4837 if (strncasecmp (p
, ":lower16:", 9) == 0)
4838 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4839 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4840 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4842 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4845 skip_whitespace (p
);
4848 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4851 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4853 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4855 inst
.error
= _("constant expression expected");
4858 if (inst
.reloc
.exp
.X_add_number
< 0
4859 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4861 inst
.error
= _("immediate value out of range");
4869 /* Miscellaneous. */
4871 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4872 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4874 parse_psr (char **str
)
4877 unsigned long psr_field
;
4878 const struct asm_psr
*psr
;
4881 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4882 feature for ease of use and backwards compatibility. */
4884 if (strncasecmp (p
, "SPSR", 4) == 0)
4885 psr_field
= SPSR_BIT
;
4886 else if (strncasecmp (p
, "CPSR", 4) == 0)
4893 while (ISALNUM (*p
) || *p
== '_');
4895 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4906 /* A suffix follows. */
4912 while (ISALNUM (*p
) || *p
== '_');
4914 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4918 psr_field
|= psr
->field
;
4923 goto error
; /* Garbage after "[CS]PSR". */
4925 psr_field
|= (PSR_c
| PSR_f
);
4931 inst
.error
= _("flag for {c}psr instruction expected");
4935 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4936 value suitable for splatting into the AIF field of the instruction. */
4939 parse_cps_flags (char **str
)
4948 case '\0': case ',':
4951 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4952 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4953 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4956 inst
.error
= _("unrecognized CPS flag");
4961 if (saw_a_flag
== 0)
4963 inst
.error
= _("missing CPS flags");
4971 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4972 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4975 parse_endian_specifier (char **str
)
4980 if (strncasecmp (s
, "BE", 2))
4982 else if (strncasecmp (s
, "LE", 2))
4986 inst
.error
= _("valid endian specifiers are be or le");
4990 if (ISALNUM (s
[2]) || s
[2] == '_')
4992 inst
.error
= _("valid endian specifiers are be or le");
4997 return little_endian
;
5000 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5001 value suitable for poking into the rotate field of an sxt or sxta
5002 instruction, or FAIL on error. */
5005 parse_ror (char **str
)
5010 if (strncasecmp (s
, "ROR", 3) == 0)
5014 inst
.error
= _("missing rotation field after comma");
5018 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5023 case 0: *str
= s
; return 0x0;
5024 case 8: *str
= s
; return 0x1;
5025 case 16: *str
= s
; return 0x2;
5026 case 24: *str
= s
; return 0x3;
5029 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5034 /* Parse a conditional code (from conds[] below). The value returned is in the
5035 range 0 .. 14, or FAIL. */
5037 parse_cond (char **str
)
5040 const struct asm_cond
*c
;
5043 while (ISALPHA (*q
))
5046 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5049 inst
.error
= _("condition required");
5057 /* Parse an option for a barrier instruction. Returns the encoding for the
5060 parse_barrier (char **str
)
5063 const struct asm_barrier_opt
*o
;
5066 while (ISALPHA (*q
))
5069 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5077 /* Parse the operands of a table branch instruction. Similar to a memory
5080 parse_tb (char **str
)
5085 if (skip_past_char (&p
, '[') == FAIL
)
5087 inst
.error
= _("'[' expected");
5091 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5093 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5096 inst
.operands
[0].reg
= reg
;
5098 if (skip_past_comma (&p
) == FAIL
)
5100 inst
.error
= _("',' expected");
5104 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5106 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5109 inst
.operands
[0].imm
= reg
;
5111 if (skip_past_comma (&p
) == SUCCESS
)
5113 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5115 if (inst
.reloc
.exp
.X_add_number
!= 1)
5117 inst
.error
= _("invalid shift");
5120 inst
.operands
[0].shifted
= 1;
5123 if (skip_past_char (&p
, ']') == FAIL
)
5125 inst
.error
= _("']' expected");
5132 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5133 information on the types the operands can take and how they are encoded.
5134 Up to four operands may be read; this function handles setting the
5135 ".present" field for each read operand itself.
5136 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5137 else returns FAIL. */
5140 parse_neon_mov (char **str
, int *which_operand
)
5142 int i
= *which_operand
, val
;
5143 enum arm_reg_type rtype
;
5145 struct neon_type_el optype
;
5147 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5149 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5150 inst
.operands
[i
].reg
= val
;
5151 inst
.operands
[i
].isscalar
= 1;
5152 inst
.operands
[i
].vectype
= optype
;
5153 inst
.operands
[i
++].present
= 1;
5155 if (skip_past_comma (&ptr
) == FAIL
)
5158 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5161 inst
.operands
[i
].reg
= val
;
5162 inst
.operands
[i
].isreg
= 1;
5163 inst
.operands
[i
].present
= 1;
5165 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5168 /* Cases 0, 1, 2, 3, 5 (D only). */
5169 if (skip_past_comma (&ptr
) == FAIL
)
5172 inst
.operands
[i
].reg
= val
;
5173 inst
.operands
[i
].isreg
= 1;
5174 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5175 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5176 inst
.operands
[i
].isvec
= 1;
5177 inst
.operands
[i
].vectype
= optype
;
5178 inst
.operands
[i
++].present
= 1;
5180 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5182 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5183 Case 13: VMOV <Sd>, <Rm> */
5184 inst
.operands
[i
].reg
= val
;
5185 inst
.operands
[i
].isreg
= 1;
5186 inst
.operands
[i
].present
= 1;
5188 if (rtype
== REG_TYPE_NQ
)
5190 first_error (_("can't use Neon quad register here"));
5193 else if (rtype
!= REG_TYPE_VFS
)
5196 if (skip_past_comma (&ptr
) == FAIL
)
5198 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5200 inst
.operands
[i
].reg
= val
;
5201 inst
.operands
[i
].isreg
= 1;
5202 inst
.operands
[i
].present
= 1;
5205 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5206 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5207 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5208 Case 10: VMOV.F32 <Sd>, #<imm>
5209 Case 11: VMOV.F64 <Dd>, #<imm> */
5210 inst
.operands
[i
].immisfloat
= 1;
5211 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5212 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5213 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5215 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5218 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5219 Case 1: VMOV<c><q> <Dd>, <Dm>
5220 Case 8: VMOV.F32 <Sd>, <Sm>
5221 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5223 inst
.operands
[i
].reg
= val
;
5224 inst
.operands
[i
].isreg
= 1;
5225 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5226 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5227 inst
.operands
[i
].isvec
= 1;
5228 inst
.operands
[i
].vectype
= optype
;
5229 inst
.operands
[i
].present
= 1;
5231 if (skip_past_comma (&ptr
) == SUCCESS
)
5236 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5239 inst
.operands
[i
].reg
= val
;
5240 inst
.operands
[i
].isreg
= 1;
5241 inst
.operands
[i
++].present
= 1;
5243 if (skip_past_comma (&ptr
) == FAIL
)
5246 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5249 inst
.operands
[i
].reg
= val
;
5250 inst
.operands
[i
].isreg
= 1;
5251 inst
.operands
[i
++].present
= 1;
5256 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5260 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5263 inst
.operands
[i
].reg
= val
;
5264 inst
.operands
[i
].isreg
= 1;
5265 inst
.operands
[i
++].present
= 1;
5267 if (skip_past_comma (&ptr
) == FAIL
)
5270 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5272 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5273 inst
.operands
[i
].reg
= val
;
5274 inst
.operands
[i
].isscalar
= 1;
5275 inst
.operands
[i
].present
= 1;
5276 inst
.operands
[i
].vectype
= optype
;
5278 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5280 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5281 inst
.operands
[i
].reg
= val
;
5282 inst
.operands
[i
].isreg
= 1;
5283 inst
.operands
[i
++].present
= 1;
5285 if (skip_past_comma (&ptr
) == FAIL
)
5288 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5291 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5295 inst
.operands
[i
].reg
= val
;
5296 inst
.operands
[i
].isreg
= 1;
5297 inst
.operands
[i
].isvec
= 1;
5298 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5299 inst
.operands
[i
].vectype
= optype
;
5300 inst
.operands
[i
].present
= 1;
5302 if (rtype
== REG_TYPE_VFS
)
5306 if (skip_past_comma (&ptr
) == FAIL
)
5308 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5311 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5314 inst
.operands
[i
].reg
= val
;
5315 inst
.operands
[i
].isreg
= 1;
5316 inst
.operands
[i
].isvec
= 1;
5317 inst
.operands
[i
].issingle
= 1;
5318 inst
.operands
[i
].vectype
= optype
;
5319 inst
.operands
[i
].present
= 1;
5322 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5326 inst
.operands
[i
].reg
= val
;
5327 inst
.operands
[i
].isreg
= 1;
5328 inst
.operands
[i
].isvec
= 1;
5329 inst
.operands
[i
].issingle
= 1;
5330 inst
.operands
[i
].vectype
= optype
;
5331 inst
.operands
[i
++].present
= 1;
5336 first_error (_("parse error"));
5340 /* Successfully parsed the operands. Update args. */
5346 first_error (_("expected comma"));
5350 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5354 /* Matcher codes for parse_operands. */
5355 enum operand_parse_code
5357 OP_stop
, /* end of line */
5359 OP_RR
, /* ARM register */
5360 OP_RRnpc
, /* ARM register, not r15 */
5361 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5362 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5363 OP_RCP
, /* Coprocessor number */
5364 OP_RCN
, /* Coprocessor register */
5365 OP_RF
, /* FPA register */
5366 OP_RVS
, /* VFP single precision register */
5367 OP_RVD
, /* VFP double precision register (0..15) */
5368 OP_RND
, /* Neon double precision register (0..31) */
5369 OP_RNQ
, /* Neon quad precision register */
5370 OP_RVSD
, /* VFP single or double precision register */
5371 OP_RNDQ
, /* Neon double or quad precision register */
5372 OP_RNSDQ
, /* Neon single, double or quad precision register */
5373 OP_RNSC
, /* Neon scalar D[X] */
5374 OP_RVC
, /* VFP control register */
5375 OP_RMF
, /* Maverick F register */
5376 OP_RMD
, /* Maverick D register */
5377 OP_RMFX
, /* Maverick FX register */
5378 OP_RMDX
, /* Maverick DX register */
5379 OP_RMAX
, /* Maverick AX register */
5380 OP_RMDS
, /* Maverick DSPSC register */
5381 OP_RIWR
, /* iWMMXt wR register */
5382 OP_RIWC
, /* iWMMXt wC register */
5383 OP_RIWG
, /* iWMMXt wCG register */
5384 OP_RXA
, /* XScale accumulator register */
5386 OP_REGLST
, /* ARM register list */
5387 OP_VRSLST
, /* VFP single-precision register list */
5388 OP_VRDLST
, /* VFP double-precision register list */
5389 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5390 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5391 OP_NSTRLST
, /* Neon element/structure list */
5393 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5394 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5395 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5396 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5397 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5398 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5399 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5400 OP_VMOV
, /* Neon VMOV operands. */
5401 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5402 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5403 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5405 OP_I0
, /* immediate zero */
5406 OP_I7
, /* immediate value 0 .. 7 */
5407 OP_I15
, /* 0 .. 15 */
5408 OP_I16
, /* 1 .. 16 */
5409 OP_I16z
, /* 0 .. 16 */
5410 OP_I31
, /* 0 .. 31 */
5411 OP_I31w
, /* 0 .. 31, optional trailing ! */
5412 OP_I32
, /* 1 .. 32 */
5413 OP_I32z
, /* 0 .. 32 */
5414 OP_I63
, /* 0 .. 63 */
5415 OP_I63s
, /* -64 .. 63 */
5416 OP_I64
, /* 1 .. 64 */
5417 OP_I64z
, /* 0 .. 64 */
5418 OP_I255
, /* 0 .. 255 */
5420 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5421 OP_I7b
, /* 0 .. 7 */
5422 OP_I15b
, /* 0 .. 15 */
5423 OP_I31b
, /* 0 .. 31 */
5425 OP_SH
, /* shifter operand */
5426 OP_SHG
, /* shifter operand with possible group relocation */
5427 OP_ADDR
, /* Memory address expression (any mode) */
5428 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5429 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5430 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5431 OP_EXP
, /* arbitrary expression */
5432 OP_EXPi
, /* same, with optional immediate prefix */
5433 OP_EXPr
, /* same, with optional relocation suffix */
5434 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5436 OP_CPSF
, /* CPS flags */
5437 OP_ENDI
, /* Endianness specifier */
5438 OP_PSR
, /* CPSR/SPSR mask for msr */
5439 OP_COND
, /* conditional code */
5440 OP_TB
, /* Table branch. */
5442 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5443 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5445 OP_RRnpc_I0
, /* ARM register or literal 0 */
5446 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5447 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5448 OP_RF_IF
, /* FPA register or immediate */
5449 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5450 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5452 /* Optional operands. */
5453 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5454 OP_oI31b
, /* 0 .. 31 */
5455 OP_oI32b
, /* 1 .. 32 */
5456 OP_oIffffb
, /* 0 .. 65535 */
5457 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5459 OP_oRR
, /* ARM register */
5460 OP_oRRnpc
, /* ARM register, not the PC */
5461 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5462 OP_oRND
, /* Optional Neon double precision register */
5463 OP_oRNQ
, /* Optional Neon quad precision register */
5464 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5465 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5466 OP_oSHll
, /* LSL immediate */
5467 OP_oSHar
, /* ASR immediate */
5468 OP_oSHllar
, /* LSL or ASR immediate */
5469 OP_oROR
, /* ROR 0/8/16/24 */
5470 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5472 OP_FIRST_OPTIONAL
= OP_oI7b
5475 /* Generic instruction operand parser. This does no encoding and no
5476 semantic validation; it merely squirrels values away in the inst
5477 structure. Returns SUCCESS or FAIL depending on whether the
5478 specified grammar matched. */
5480 parse_operands (char *str
, const unsigned char *pattern
)
5482 unsigned const char *upat
= pattern
;
5483 char *backtrack_pos
= 0;
5484 const char *backtrack_error
= 0;
5485 int i
, val
, backtrack_index
= 0;
5486 enum arm_reg_type rtype
;
5487 parse_operand_result result
;
5489 #define po_char_or_fail(chr) do { \
5490 if (skip_past_char (&str, chr) == FAIL) \
5494 #define po_reg_or_fail(regtype) do { \
5495 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5496 &inst.operands[i].vectype); \
5499 first_error (_(reg_expected_msgs[regtype])); \
5502 inst.operands[i].reg = val; \
5503 inst.operands[i].isreg = 1; \
5504 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5505 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5506 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5507 || rtype == REG_TYPE_VFD \
5508 || rtype == REG_TYPE_NQ); \
5511 #define po_reg_or_goto(regtype, label) do { \
5512 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5513 &inst.operands[i].vectype); \
5517 inst.operands[i].reg = val; \
5518 inst.operands[i].isreg = 1; \
5519 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5520 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5521 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5522 || rtype == REG_TYPE_VFD \
5523 || rtype == REG_TYPE_NQ); \
5526 #define po_imm_or_fail(min, max, popt) do { \
5527 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5529 inst.operands[i].imm = val; \
5532 #define po_scalar_or_goto(elsz, label) do { \
5533 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5536 inst.operands[i].reg = val; \
5537 inst.operands[i].isscalar = 1; \
5540 #define po_misc_or_fail(expr) do { \
5545 #define po_misc_or_fail_no_backtrack(expr) do { \
5547 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5548 backtrack_pos = 0; \
5549 if (result != PARSE_OPERAND_SUCCESS) \
5553 skip_whitespace (str
);
5555 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5557 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5559 /* Remember where we are in case we need to backtrack. */
5560 assert (!backtrack_pos
);
5561 backtrack_pos
= str
;
5562 backtrack_error
= inst
.error
;
5563 backtrack_index
= i
;
5566 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5567 po_char_or_fail (',');
5575 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5576 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5577 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5578 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5579 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5580 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5582 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5584 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5586 /* Also accept generic coprocessor regs for unknown registers. */
5588 po_reg_or_fail (REG_TYPE_CN
);
5590 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5591 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5592 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5593 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5594 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5595 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5596 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5597 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5598 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5599 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5601 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5603 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5604 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5606 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5608 /* Neon scalar. Using an element size of 8 means that some invalid
5609 scalars are accepted here, so deal with those in later code. */
5610 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5612 /* WARNING: We can expand to two operands here. This has the potential
5613 to totally confuse the backtracking mechanism! It will be OK at
5614 least as long as we don't try to use optional args as well,
5618 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5619 inst
.operands
[i
].present
= 1;
5621 skip_past_comma (&str
);
5622 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5625 /* Optional register operand was omitted. Unfortunately, it's in
5626 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5627 here (this is a bit grotty). */
5628 inst
.operands
[i
] = inst
.operands
[i
-1];
5629 inst
.operands
[i
-1].present
= 0;
5632 /* There's a possibility of getting a 64-bit immediate here, so
5633 we need special handling. */
5634 if (parse_big_immediate (&str
, i
) == FAIL
)
5636 inst
.error
= _("immediate value is out of range");
5644 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5647 po_imm_or_fail (0, 0, TRUE
);
5652 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5657 po_scalar_or_goto (8, try_rr
);
5660 po_reg_or_fail (REG_TYPE_RN
);
5666 po_scalar_or_goto (8, try_nsdq
);
5669 po_reg_or_fail (REG_TYPE_NSDQ
);
5675 po_scalar_or_goto (8, try_ndq
);
5678 po_reg_or_fail (REG_TYPE_NDQ
);
5684 po_scalar_or_goto (8, try_vfd
);
5687 po_reg_or_fail (REG_TYPE_VFD
);
5692 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5693 not careful then bad things might happen. */
5694 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5699 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5702 /* There's a possibility of getting a 64-bit immediate here, so
5703 we need special handling. */
5704 if (parse_big_immediate (&str
, i
) == FAIL
)
5706 inst
.error
= _("immediate value is out of range");
5714 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5717 po_imm_or_fail (0, 63, TRUE
);
5722 po_char_or_fail ('[');
5723 po_reg_or_fail (REG_TYPE_RN
);
5724 po_char_or_fail (']');
5729 po_reg_or_fail (REG_TYPE_RN
);
5730 if (skip_past_char (&str
, '!') == SUCCESS
)
5731 inst
.operands
[i
].writeback
= 1;
5735 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5736 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5737 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5738 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5739 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5740 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5741 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5742 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5743 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5744 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5745 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5746 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5748 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5750 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5751 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5753 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5754 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5755 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5757 /* Immediate variants */
5759 po_char_or_fail ('{');
5760 po_imm_or_fail (0, 255, TRUE
);
5761 po_char_or_fail ('}');
5765 /* The expression parser chokes on a trailing !, so we have
5766 to find it first and zap it. */
5769 while (*s
&& *s
!= ',')
5774 inst
.operands
[i
].writeback
= 1;
5776 po_imm_or_fail (0, 31, TRUE
);
5784 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5789 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5794 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5796 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5798 val
= parse_reloc (&str
);
5801 inst
.error
= _("unrecognized relocation suffix");
5804 else if (val
!= BFD_RELOC_UNUSED
)
5806 inst
.operands
[i
].imm
= val
;
5807 inst
.operands
[i
].hasreloc
= 1;
5812 /* Operand for MOVW or MOVT. */
5814 po_misc_or_fail (parse_half (&str
));
5817 /* Register or expression */
5818 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5819 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5821 /* Register or immediate */
5822 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5823 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5825 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5827 if (!is_immediate_prefix (*str
))
5830 val
= parse_fpa_immediate (&str
);
5833 /* FPA immediates are encoded as registers 8-15.
5834 parse_fpa_immediate has already applied the offset. */
5835 inst
.operands
[i
].reg
= val
;
5836 inst
.operands
[i
].isreg
= 1;
5839 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5840 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5842 /* Two kinds of register */
5845 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5847 || (rege
->type
!= REG_TYPE_MMXWR
5848 && rege
->type
!= REG_TYPE_MMXWC
5849 && rege
->type
!= REG_TYPE_MMXWCG
))
5851 inst
.error
= _("iWMMXt data or control register expected");
5854 inst
.operands
[i
].reg
= rege
->number
;
5855 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5861 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5863 || (rege
->type
!= REG_TYPE_MMXWC
5864 && rege
->type
!= REG_TYPE_MMXWCG
))
5866 inst
.error
= _("iWMMXt control register expected");
5869 inst
.operands
[i
].reg
= rege
->number
;
5870 inst
.operands
[i
].isreg
= 1;
5875 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5876 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5877 case OP_oROR
: val
= parse_ror (&str
); break;
5878 case OP_PSR
: val
= parse_psr (&str
); break;
5879 case OP_COND
: val
= parse_cond (&str
); break;
5880 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5883 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5884 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5887 val
= parse_psr (&str
);
5891 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5894 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5896 if (strncasecmp (str
, "APSR_", 5) == 0)
5903 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5904 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5905 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5906 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5907 default: found
= 16;
5911 inst
.operands
[i
].isvec
= 1;
5918 po_misc_or_fail (parse_tb (&str
));
5921 /* Register lists */
5923 val
= parse_reg_list (&str
);
5926 inst
.operands
[1].writeback
= 1;
5932 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5936 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5940 /* Allow Q registers too. */
5941 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5946 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5948 inst
.operands
[i
].issingle
= 1;
5953 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5958 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5959 &inst
.operands
[i
].vectype
);
5962 /* Addressing modes */
5964 po_misc_or_fail (parse_address (&str
, i
));
5968 po_misc_or_fail_no_backtrack (
5969 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5973 po_misc_or_fail_no_backtrack (
5974 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5978 po_misc_or_fail_no_backtrack (
5979 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5983 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5987 po_misc_or_fail_no_backtrack (
5988 parse_shifter_operand_group_reloc (&str
, i
));
5992 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5996 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6000 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6004 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6007 /* Various value-based sanity checks and shared operations. We
6008 do not signal immediate failures for the register constraints;
6009 this allows a syntax error to take precedence. */
6018 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6019 inst
.error
= BAD_PC
;
6037 inst
.operands
[i
].imm
= val
;
6044 /* If we get here, this operand was successfully parsed. */
6045 inst
.operands
[i
].present
= 1;
6049 inst
.error
= BAD_ARGS
;
6054 /* The parse routine should already have set inst.error, but set a
6055 default here just in case. */
6057 inst
.error
= _("syntax error");
6061 /* Do not backtrack over a trailing optional argument that
6062 absorbed some text. We will only fail again, with the
6063 'garbage following instruction' error message, which is
6064 probably less helpful than the current one. */
6065 if (backtrack_index
== i
&& backtrack_pos
!= str
6066 && upat
[i
+1] == OP_stop
)
6069 inst
.error
= _("syntax error");
6073 /* Try again, skipping the optional argument at backtrack_pos. */
6074 str
= backtrack_pos
;
6075 inst
.error
= backtrack_error
;
6076 inst
.operands
[backtrack_index
].present
= 0;
6077 i
= backtrack_index
;
6081 /* Check that we have parsed all the arguments. */
6082 if (*str
!= '\0' && !inst
.error
)
6083 inst
.error
= _("garbage following instruction");
6085 return inst
.error
? FAIL
: SUCCESS
;
6088 #undef po_char_or_fail
6089 #undef po_reg_or_fail
6090 #undef po_reg_or_goto
6091 #undef po_imm_or_fail
6092 #undef po_scalar_or_fail
6094 /* Shorthand macro for instruction encoding functions issuing errors. */
6095 #define constraint(expr, err) do { \
6103 /* Functions for operand encoding. ARM, then Thumb. */
6105 #define rotate_left(v, n) (v << n | v >> (32 - n))
6107 /* If VAL can be encoded in the immediate field of an ARM instruction,
6108 return the encoded form. Otherwise, return FAIL. */
6111 encode_arm_immediate (unsigned int val
)
6115 for (i
= 0; i
< 32; i
+= 2)
6116 if ((a
= rotate_left (val
, i
)) <= 0xff)
6117 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6122 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6123 return the encoded form. Otherwise, return FAIL. */
6125 encode_thumb32_immediate (unsigned int val
)
6132 for (i
= 1; i
<= 24; i
++)
6135 if ((val
& ~(0xff << i
)) == 0)
6136 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6140 if (val
== ((a
<< 16) | a
))
6142 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6146 if (val
== ((a
<< 16) | a
))
6147 return 0x200 | (a
>> 8);
6151 /* Encode a VFP SP or DP register number into inst.instruction. */
6154 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6156 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6159 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6162 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6165 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6170 first_error (_("D register out of range for selected VFP version"));
6178 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6182 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6186 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6190 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6194 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6198 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6206 /* Encode a <shift> in an ARM-format instruction. The immediate,
6207 if any, is handled by md_apply_fix. */
6209 encode_arm_shift (int i
)
6211 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6212 inst
.instruction
|= SHIFT_ROR
<< 5;
6215 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6216 if (inst
.operands
[i
].immisreg
)
6218 inst
.instruction
|= SHIFT_BY_REG
;
6219 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6222 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6227 encode_arm_shifter_operand (int i
)
6229 if (inst
.operands
[i
].isreg
)
6231 inst
.instruction
|= inst
.operands
[i
].reg
;
6232 encode_arm_shift (i
);
6235 inst
.instruction
|= INST_IMMEDIATE
;
6238 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6240 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6242 assert (inst
.operands
[i
].isreg
);
6243 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6245 if (inst
.operands
[i
].preind
)
6249 inst
.error
= _("instruction does not accept preindexed addressing");
6252 inst
.instruction
|= PRE_INDEX
;
6253 if (inst
.operands
[i
].writeback
)
6254 inst
.instruction
|= WRITE_BACK
;
6257 else if (inst
.operands
[i
].postind
)
6259 assert (inst
.operands
[i
].writeback
);
6261 inst
.instruction
|= WRITE_BACK
;
6263 else /* unindexed - only for coprocessor */
6265 inst
.error
= _("instruction does not accept unindexed addressing");
6269 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6270 && (((inst
.instruction
& 0x000f0000) >> 16)
6271 == ((inst
.instruction
& 0x0000f000) >> 12)))
6272 as_warn ((inst
.instruction
& LOAD_BIT
)
6273 ? _("destination register same as write-back base")
6274 : _("source register same as write-back base"));
6277 /* inst.operands[i] was set up by parse_address. Encode it into an
6278 ARM-format mode 2 load or store instruction. If is_t is true,
6279 reject forms that cannot be used with a T instruction (i.e. not
6282 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6284 encode_arm_addr_mode_common (i
, is_t
);
6286 if (inst
.operands
[i
].immisreg
)
6288 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6289 inst
.instruction
|= inst
.operands
[i
].imm
;
6290 if (!inst
.operands
[i
].negative
)
6291 inst
.instruction
|= INDEX_UP
;
6292 if (inst
.operands
[i
].shifted
)
6294 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6295 inst
.instruction
|= SHIFT_ROR
<< 5;
6298 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6299 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6303 else /* immediate offset in inst.reloc */
6305 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6306 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6310 /* inst.operands[i] was set up by parse_address. Encode it into an
6311 ARM-format mode 3 load or store instruction. Reject forms that
6312 cannot be used with such instructions. If is_t is true, reject
6313 forms that cannot be used with a T instruction (i.e. not
6316 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6318 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6320 inst
.error
= _("instruction does not accept scaled register index");
6324 encode_arm_addr_mode_common (i
, is_t
);
6326 if (inst
.operands
[i
].immisreg
)
6328 inst
.instruction
|= inst
.operands
[i
].imm
;
6329 if (!inst
.operands
[i
].negative
)
6330 inst
.instruction
|= INDEX_UP
;
6332 else /* immediate offset in inst.reloc */
6334 inst
.instruction
|= HWOFFSET_IMM
;
6335 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6336 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6340 /* inst.operands[i] was set up by parse_address. Encode it into an
6341 ARM-format instruction. Reject all forms which cannot be encoded
6342 into a coprocessor load/store instruction. If wb_ok is false,
6343 reject use of writeback; if unind_ok is false, reject use of
6344 unindexed addressing. If reloc_override is not 0, use it instead
6345 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6346 (in which case it is preserved). */
6349 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6351 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6353 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6355 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6357 assert (!inst
.operands
[i
].writeback
);
6360 inst
.error
= _("instruction does not support unindexed addressing");
6363 inst
.instruction
|= inst
.operands
[i
].imm
;
6364 inst
.instruction
|= INDEX_UP
;
6368 if (inst
.operands
[i
].preind
)
6369 inst
.instruction
|= PRE_INDEX
;
6371 if (inst
.operands
[i
].writeback
)
6373 if (inst
.operands
[i
].reg
== REG_PC
)
6375 inst
.error
= _("pc may not be used with write-back");
6380 inst
.error
= _("instruction does not support writeback");
6383 inst
.instruction
|= WRITE_BACK
;
6387 inst
.reloc
.type
= reloc_override
;
6388 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6389 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6390 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6393 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6395 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6401 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6402 Determine whether it can be performed with a move instruction; if
6403 it can, convert inst.instruction to that move instruction and
6404 return 1; if it can't, convert inst.instruction to a literal-pool
6405 load and return 0. If this is not a valid thing to do in the
6406 current context, set inst.error and return 1.
6408 inst.operands[i] describes the destination register. */
6411 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6416 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6420 if ((inst
.instruction
& tbit
) == 0)
6422 inst
.error
= _("invalid pseudo operation");
6425 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6427 inst
.error
= _("constant expression expected");
6430 if (inst
.reloc
.exp
.X_op
== O_constant
)
6434 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6436 /* This can be done with a mov(1) instruction. */
6437 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6438 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6444 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6447 /* This can be done with a mov instruction. */
6448 inst
.instruction
&= LITERAL_MASK
;
6449 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6450 inst
.instruction
|= value
& 0xfff;
6454 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6457 /* This can be done with a mvn instruction. */
6458 inst
.instruction
&= LITERAL_MASK
;
6459 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6460 inst
.instruction
|= value
& 0xfff;
6466 if (add_to_lit_pool () == FAIL
)
6468 inst
.error
= _("literal pool insertion failed");
6471 inst
.operands
[1].reg
= REG_PC
;
6472 inst
.operands
[1].isreg
= 1;
6473 inst
.operands
[1].preind
= 1;
6474 inst
.reloc
.pc_rel
= 1;
6475 inst
.reloc
.type
= (thumb_p
6476 ? BFD_RELOC_ARM_THUMB_OFFSET
6478 ? BFD_RELOC_ARM_HWLITERAL
6479 : BFD_RELOC_ARM_LITERAL
));
6483 /* Functions for instruction encoding, sorted by sub-architecture.
6484 First some generics; their names are taken from the conventional
6485 bit positions for register arguments in ARM format instructions. */
6495 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6502 inst
.instruction
|= inst
.operands
[1].reg
;
6508 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6509 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6515 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6516 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6522 unsigned Rn
= inst
.operands
[2].reg
;
6523 /* Enforce restrictions on SWP instruction. */
6524 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6525 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6526 _("Rn must not overlap other operands"));
6527 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6528 inst
.instruction
|= inst
.operands
[1].reg
;
6529 inst
.instruction
|= Rn
<< 16;
6535 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6536 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6537 inst
.instruction
|= inst
.operands
[2].reg
;
6543 inst
.instruction
|= inst
.operands
[0].reg
;
6544 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6545 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6551 inst
.instruction
|= inst
.operands
[0].imm
;
6557 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6558 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6561 /* ARM instructions, in alphabetical order by function name (except
6562 that wrapper functions appear immediately after the function they
6565 /* This is a pseudo-op of the form "adr rd, label" to be converted
6566 into a relative address of the form "add rd, pc, #label-.-8". */
6571 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6573 /* Frag hacking will turn this into a sub instruction if the offset turns
6574 out to be negative. */
6575 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6576 inst
.reloc
.pc_rel
= 1;
6577 inst
.reloc
.exp
.X_add_number
-= 8;
6580 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6581 into a relative address of the form:
6582 add rd, pc, #low(label-.-8)"
6583 add rd, rd, #high(label-.-8)" */
6588 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6590 /* Frag hacking will turn this into a sub instruction if the offset turns
6591 out to be negative. */
6592 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6593 inst
.reloc
.pc_rel
= 1;
6594 inst
.size
= INSN_SIZE
* 2;
6595 inst
.reloc
.exp
.X_add_number
-= 8;
6601 if (!inst
.operands
[1].present
)
6602 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6603 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6604 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6605 encode_arm_shifter_operand (2);
6611 if (inst
.operands
[0].present
)
6613 constraint ((inst
.instruction
& 0xf0) != 0x40
6614 && inst
.operands
[0].imm
!= 0xf,
6615 _("bad barrier type"));
6616 inst
.instruction
|= inst
.operands
[0].imm
;
6619 inst
.instruction
|= 0xf;
6625 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6626 constraint (msb
> 32, _("bit-field extends past end of register"));
6627 /* The instruction encoding stores the LSB and MSB,
6628 not the LSB and width. */
6629 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6630 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6631 inst
.instruction
|= (msb
- 1) << 16;
6639 /* #0 in second position is alternative syntax for bfc, which is
6640 the same instruction but with REG_PC in the Rm field. */
6641 if (!inst
.operands
[1].isreg
)
6642 inst
.operands
[1].reg
= REG_PC
;
6644 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6645 constraint (msb
> 32, _("bit-field extends past end of register"));
6646 /* The instruction encoding stores the LSB and MSB,
6647 not the LSB and width. */
6648 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6649 inst
.instruction
|= inst
.operands
[1].reg
;
6650 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6651 inst
.instruction
|= (msb
- 1) << 16;
6657 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6658 _("bit-field extends past end of register"));
6659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6660 inst
.instruction
|= inst
.operands
[1].reg
;
6661 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6662 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6665 /* ARM V5 breakpoint instruction (argument parse)
6666 BKPT <16 bit unsigned immediate>
6667 Instruction is not conditional.
6668 The bit pattern given in insns[] has the COND_ALWAYS condition,
6669 and it is an error if the caller tried to override that. */
6674 /* Top 12 of 16 bits to bits 19:8. */
6675 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6677 /* Bottom 4 of 16 bits to bits 3:0. */
6678 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6682 encode_branch (int default_reloc
)
6684 if (inst
.operands
[0].hasreloc
)
6686 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6687 _("the only suffix valid here is '(plt)'"));
6688 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6692 inst
.reloc
.type
= default_reloc
;
6694 inst
.reloc
.pc_rel
= 1;
6701 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6702 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6705 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6712 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6714 if (inst
.cond
== COND_ALWAYS
)
6715 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6717 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6721 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6724 /* ARM V5 branch-link-exchange instruction (argument parse)
6725 BLX <target_addr> ie BLX(1)
6726 BLX{<condition>} <Rm> ie BLX(2)
6727 Unfortunately, there are two different opcodes for this mnemonic.
6728 So, the insns[].value is not used, and the code here zaps values
6729 into inst.instruction.
6730 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6735 if (inst
.operands
[0].isreg
)
6737 /* Arg is a register; the opcode provided by insns[] is correct.
6738 It is not illegal to do "blx pc", just useless. */
6739 if (inst
.operands
[0].reg
== REG_PC
)
6740 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6742 inst
.instruction
|= inst
.operands
[0].reg
;
6746 /* Arg is an address; this instruction cannot be executed
6747 conditionally, and the opcode must be adjusted. */
6748 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6749 inst
.instruction
= 0xfa000000;
6751 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6752 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6755 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6762 if (inst
.operands
[0].reg
== REG_PC
)
6763 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6765 inst
.instruction
|= inst
.operands
[0].reg
;
6769 /* ARM v5TEJ. Jump to Jazelle code. */
6774 if (inst
.operands
[0].reg
== REG_PC
)
6775 as_tsktsk (_("use of r15 in bxj is not really useful"));
6777 inst
.instruction
|= inst
.operands
[0].reg
;
6780 /* Co-processor data operation:
6781 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6782 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6786 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6787 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6788 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6789 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6790 inst
.instruction
|= inst
.operands
[4].reg
;
6791 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6797 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6798 encode_arm_shifter_operand (1);
6801 /* Transfer between coprocessor and ARM registers.
6802 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6807 No special properties. */
6812 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6813 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6814 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6815 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6816 inst
.instruction
|= inst
.operands
[4].reg
;
6817 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6820 /* Transfer between coprocessor register and pair of ARM registers.
6821 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6826 Two XScale instructions are special cases of these:
6828 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6829 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6831 Result unpredictable if Rd or Rn is R15. */
6836 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6837 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6838 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6839 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6840 inst
.instruction
|= inst
.operands
[4].reg
;
6846 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6847 if (inst
.operands
[1].present
)
6849 inst
.instruction
|= CPSI_MMOD
;
6850 inst
.instruction
|= inst
.operands
[1].imm
;
6857 inst
.instruction
|= inst
.operands
[0].imm
;
6863 /* There is no IT instruction in ARM mode. We
6864 process it but do not generate code for it. */
6871 int base_reg
= inst
.operands
[0].reg
;
6872 int range
= inst
.operands
[1].imm
;
6874 inst
.instruction
|= base_reg
<< 16;
6875 inst
.instruction
|= range
;
6877 if (inst
.operands
[1].writeback
)
6878 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6880 if (inst
.operands
[0].writeback
)
6882 inst
.instruction
|= WRITE_BACK
;
6883 /* Check for unpredictable uses of writeback. */
6884 if (inst
.instruction
& LOAD_BIT
)
6886 /* Not allowed in LDM type 2. */
6887 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6888 && ((range
& (1 << REG_PC
)) == 0))
6889 as_warn (_("writeback of base register is UNPREDICTABLE"));
6890 /* Only allowed if base reg not in list for other types. */
6891 else if (range
& (1 << base_reg
))
6892 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6896 /* Not allowed for type 2. */
6897 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6898 as_warn (_("writeback of base register is UNPREDICTABLE"));
6899 /* Only allowed if base reg not in list, or first in list. */
6900 else if ((range
& (1 << base_reg
))
6901 && (range
& ((1 << base_reg
) - 1)))
6902 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6907 /* ARMv5TE load-consecutive (argument parse)
6916 constraint (inst
.operands
[0].reg
% 2 != 0,
6917 _("first destination register must be even"));
6918 constraint (inst
.operands
[1].present
6919 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6920 _("can only load two consecutive registers"));
6921 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6922 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6924 if (!inst
.operands
[1].present
)
6925 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6927 if (inst
.instruction
& LOAD_BIT
)
6929 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6930 register and the first register written; we have to diagnose
6931 overlap between the base and the second register written here. */
6933 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6934 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6935 as_warn (_("base register written back, and overlaps "
6936 "second destination register"));
6938 /* For an index-register load, the index register must not overlap the
6939 destination (even if not write-back). */
6940 else if (inst
.operands
[2].immisreg
6941 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6942 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6943 as_warn (_("index register overlaps destination register"));
6946 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6947 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6953 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6954 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6955 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6956 || inst
.operands
[1].negative
6957 /* This can arise if the programmer has written
6959 or if they have mistakenly used a register name as the last
6962 It is very difficult to distinguish between these two cases
6963 because "rX" might actually be a label. ie the register
6964 name has been occluded by a symbol of the same name. So we
6965 just generate a general 'bad addressing mode' type error
6966 message and leave it up to the programmer to discover the
6967 true cause and fix their mistake. */
6968 || (inst
.operands
[1].reg
== REG_PC
),
6971 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6972 || inst
.reloc
.exp
.X_add_number
!= 0,
6973 _("offset must be zero in ARM encoding"));
6975 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6976 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6977 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6983 constraint (inst
.operands
[0].reg
% 2 != 0,
6984 _("even register required"));
6985 constraint (inst
.operands
[1].present
6986 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6987 _("can only load two consecutive registers"));
6988 /* If op 1 were present and equal to PC, this function wouldn't
6989 have been called in the first place. */
6990 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6992 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6993 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6999 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7000 if (!inst
.operands
[1].isreg
)
7001 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7003 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7009 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7011 if (inst
.operands
[1].preind
)
7013 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7014 || inst
.reloc
.exp
.X_add_number
!= 0,
7015 _("this instruction requires a post-indexed address"));
7017 inst
.operands
[1].preind
= 0;
7018 inst
.operands
[1].postind
= 1;
7019 inst
.operands
[1].writeback
= 1;
7021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7022 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7025 /* Halfword and signed-byte load/store operations. */
7030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7031 if (!inst
.operands
[1].isreg
)
7032 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7034 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7040 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7042 if (inst
.operands
[1].preind
)
7044 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7045 || inst
.reloc
.exp
.X_add_number
!= 0,
7046 _("this instruction requires a post-indexed address"));
7048 inst
.operands
[1].preind
= 0;
7049 inst
.operands
[1].postind
= 1;
7050 inst
.operands
[1].writeback
= 1;
7052 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7053 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7056 /* Co-processor register load/store.
7057 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7061 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7062 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7063 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7069 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7070 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7071 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7072 && !(inst
.instruction
& 0x00400000))
7073 as_tsktsk (_("Rd and Rm should be different in mla"));
7075 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7076 inst
.instruction
|= inst
.operands
[1].reg
;
7077 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7078 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7085 encode_arm_shifter_operand (1);
7088 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7095 top
= (inst
.instruction
& 0x00400000) != 0;
7096 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7097 _(":lower16: not allowed this instruction"));
7098 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7099 _(":upper16: not allowed instruction"));
7100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7101 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7103 imm
= inst
.reloc
.exp
.X_add_number
;
7104 /* The value is in two pieces: 0:11, 16:19. */
7105 inst
.instruction
|= (imm
& 0x00000fff);
7106 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7110 static void do_vfp_nsyn_opcode (const char *);
7113 do_vfp_nsyn_mrs (void)
7115 if (inst
.operands
[0].isvec
)
7117 if (inst
.operands
[1].reg
!= 1)
7118 first_error (_("operand 1 must be FPSCR"));
7119 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7120 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7121 do_vfp_nsyn_opcode ("fmstat");
7123 else if (inst
.operands
[1].isvec
)
7124 do_vfp_nsyn_opcode ("fmrx");
7132 do_vfp_nsyn_msr (void)
7134 if (inst
.operands
[0].isvec
)
7135 do_vfp_nsyn_opcode ("fmxr");
7145 if (do_vfp_nsyn_mrs () == SUCCESS
)
7148 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7149 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7151 _("'CPSR' or 'SPSR' expected"));
7152 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7153 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7156 /* Two possible forms:
7157 "{C|S}PSR_<field>, Rm",
7158 "{C|S}PSR_f, #expression". */
7163 if (do_vfp_nsyn_msr () == SUCCESS
)
7166 inst
.instruction
|= inst
.operands
[0].imm
;
7167 if (inst
.operands
[1].isreg
)
7168 inst
.instruction
|= inst
.operands
[1].reg
;
7171 inst
.instruction
|= INST_IMMEDIATE
;
7172 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7173 inst
.reloc
.pc_rel
= 0;
7180 if (!inst
.operands
[2].present
)
7181 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7182 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7183 inst
.instruction
|= inst
.operands
[1].reg
;
7184 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7186 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7187 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7188 as_tsktsk (_("Rd and Rm should be different in mul"));
7191 /* Long Multiply Parser
7192 UMULL RdLo, RdHi, Rm, Rs
7193 SMULL RdLo, RdHi, Rm, Rs
7194 UMLAL RdLo, RdHi, Rm, Rs
7195 SMLAL RdLo, RdHi, Rm, Rs. */
7200 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7201 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7202 inst
.instruction
|= inst
.operands
[2].reg
;
7203 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7205 /* rdhi, rdlo and rm must all be different. */
7206 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7207 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7208 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7209 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7215 if (inst
.operands
[0].present
)
7217 /* Architectural NOP hints are CPSR sets with no bits selected. */
7218 inst
.instruction
&= 0xf0000000;
7219 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7223 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7224 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7225 Condition defaults to COND_ALWAYS.
7226 Error if Rd, Rn or Rm are R15. */
7231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7232 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7233 inst
.instruction
|= inst
.operands
[2].reg
;
7234 if (inst
.operands
[3].present
)
7235 encode_arm_shift (3);
7238 /* ARM V6 PKHTB (Argument Parse). */
7243 if (!inst
.operands
[3].present
)
7245 /* If the shift specifier is omitted, turn the instruction
7246 into pkhbt rd, rm, rn. */
7247 inst
.instruction
&= 0xfff00010;
7248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7249 inst
.instruction
|= inst
.operands
[1].reg
;
7250 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7254 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7255 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7256 inst
.instruction
|= inst
.operands
[2].reg
;
7257 encode_arm_shift (3);
7261 /* ARMv5TE: Preload-Cache
7265 Syntactically, like LDR with B=1, W=0, L=1. */
7270 constraint (!inst
.operands
[0].isreg
,
7271 _("'[' expected after PLD mnemonic"));
7272 constraint (inst
.operands
[0].postind
,
7273 _("post-indexed expression used in preload instruction"));
7274 constraint (inst
.operands
[0].writeback
,
7275 _("writeback used in preload instruction"));
7276 constraint (!inst
.operands
[0].preind
,
7277 _("unindexed addressing used in preload instruction"));
7278 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7281 /* ARMv7: PLI <addr_mode> */
7285 constraint (!inst
.operands
[0].isreg
,
7286 _("'[' expected after PLI mnemonic"));
7287 constraint (inst
.operands
[0].postind
,
7288 _("post-indexed expression used in preload instruction"));
7289 constraint (inst
.operands
[0].writeback
,
7290 _("writeback used in preload instruction"));
7291 constraint (!inst
.operands
[0].preind
,
7292 _("unindexed addressing used in preload instruction"));
7293 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7294 inst
.instruction
&= ~PRE_INDEX
;
7300 inst
.operands
[1] = inst
.operands
[0];
7301 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7302 inst
.operands
[0].isreg
= 1;
7303 inst
.operands
[0].writeback
= 1;
7304 inst
.operands
[0].reg
= REG_SP
;
7308 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7309 word at the specified address and the following word
7311 Unconditionally executed.
7312 Error if Rn is R15. */
7317 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7318 if (inst
.operands
[0].writeback
)
7319 inst
.instruction
|= WRITE_BACK
;
7322 /* ARM V6 ssat (argument parse). */
7327 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7328 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7329 inst
.instruction
|= inst
.operands
[2].reg
;
7331 if (inst
.operands
[3].present
)
7332 encode_arm_shift (3);
7335 /* ARM V6 usat (argument parse). */
7340 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7341 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7342 inst
.instruction
|= inst
.operands
[2].reg
;
7344 if (inst
.operands
[3].present
)
7345 encode_arm_shift (3);
7348 /* ARM V6 ssat16 (argument parse). */
7353 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7354 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7355 inst
.instruction
|= inst
.operands
[2].reg
;
7361 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7362 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7363 inst
.instruction
|= inst
.operands
[2].reg
;
7366 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7367 preserving the other bits.
7369 setend <endian_specifier>, where <endian_specifier> is either
7375 if (inst
.operands
[0].imm
)
7376 inst
.instruction
|= 0x200;
7382 unsigned int Rm
= (inst
.operands
[1].present
7383 ? inst
.operands
[1].reg
7384 : inst
.operands
[0].reg
);
7386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7387 inst
.instruction
|= Rm
;
7388 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7390 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7391 inst
.instruction
|= SHIFT_BY_REG
;
7394 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7400 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7401 inst
.reloc
.pc_rel
= 0;
7407 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7408 inst
.reloc
.pc_rel
= 0;
7411 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7412 SMLAxy{cond} Rd,Rm,Rs,Rn
7413 SMLAWy{cond} Rd,Rm,Rs,Rn
7414 Error if any register is R15. */
7419 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7420 inst
.instruction
|= inst
.operands
[1].reg
;
7421 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7422 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7425 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7426 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7427 Error if any register is R15.
7428 Warning if Rdlo == Rdhi. */
7433 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7434 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7435 inst
.instruction
|= inst
.operands
[2].reg
;
7436 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7438 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7439 as_tsktsk (_("rdhi and rdlo must be different"));
7442 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7443 SMULxy{cond} Rd,Rm,Rs
7444 Error if any register is R15. */
7449 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7450 inst
.instruction
|= inst
.operands
[1].reg
;
7451 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7454 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7455 the same for both ARM and Thumb-2. */
7462 if (inst
.operands
[0].present
)
7464 reg
= inst
.operands
[0].reg
;
7465 constraint (reg
!= 13, _("SRS base register must be r13"));
7470 inst
.instruction
|= reg
<< 16;
7471 inst
.instruction
|= inst
.operands
[1].imm
;
7472 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7473 inst
.instruction
|= WRITE_BACK
;
7476 /* ARM V6 strex (argument parse). */
7481 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7482 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7483 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7484 || inst
.operands
[2].negative
7485 /* See comment in do_ldrex(). */
7486 || (inst
.operands
[2].reg
== REG_PC
),
7489 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7490 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7492 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7493 || inst
.reloc
.exp
.X_add_number
!= 0,
7494 _("offset must be zero in ARM encoding"));
7496 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7497 inst
.instruction
|= inst
.operands
[1].reg
;
7498 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7499 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7505 constraint (inst
.operands
[1].reg
% 2 != 0,
7506 _("even register required"));
7507 constraint (inst
.operands
[2].present
7508 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7509 _("can only store two consecutive registers"));
7510 /* If op 2 were present and equal to PC, this function wouldn't
7511 have been called in the first place. */
7512 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7514 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7515 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7516 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7519 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7520 inst
.instruction
|= inst
.operands
[1].reg
;
7521 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7524 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7525 extends it to 32-bits, and adds the result to a value in another
7526 register. You can specify a rotation by 0, 8, 16, or 24 bits
7527 before extracting the 16-bit value.
7528 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7529 Condition defaults to COND_ALWAYS.
7530 Error if any register uses R15. */
7535 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7536 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7537 inst
.instruction
|= inst
.operands
[2].reg
;
7538 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7543 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7544 Condition defaults to COND_ALWAYS.
7545 Error if any register uses R15. */
7550 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7551 inst
.instruction
|= inst
.operands
[1].reg
;
7552 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7555 /* VFP instructions. In a logical order: SP variant first, monad
7556 before dyad, arithmetic then move then load/store. */
7559 do_vfp_sp_monadic (void)
7561 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7562 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7566 do_vfp_sp_dyadic (void)
7568 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7569 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7570 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7574 do_vfp_sp_compare_z (void)
7576 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7580 do_vfp_dp_sp_cvt (void)
7582 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7583 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7587 do_vfp_sp_dp_cvt (void)
7589 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7590 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7594 do_vfp_reg_from_sp (void)
7596 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7597 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7601 do_vfp_reg2_from_sp2 (void)
7603 constraint (inst
.operands
[2].imm
!= 2,
7604 _("only two consecutive VFP SP registers allowed here"));
7605 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7606 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7607 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7611 do_vfp_sp_from_reg (void)
7613 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7614 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7618 do_vfp_sp2_from_reg2 (void)
7620 constraint (inst
.operands
[0].imm
!= 2,
7621 _("only two consecutive VFP SP registers allowed here"));
7622 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7623 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7624 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7628 do_vfp_sp_ldst (void)
7630 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7631 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7635 do_vfp_dp_ldst (void)
7637 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7638 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7643 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7645 if (inst
.operands
[0].writeback
)
7646 inst
.instruction
|= WRITE_BACK
;
7648 constraint (ldstm_type
!= VFP_LDSTMIA
,
7649 _("this addressing mode requires base-register writeback"));
7650 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7651 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7652 inst
.instruction
|= inst
.operands
[1].imm
;
7656 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7660 if (inst
.operands
[0].writeback
)
7661 inst
.instruction
|= WRITE_BACK
;
7663 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7664 _("this addressing mode requires base-register writeback"));
7666 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7667 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7669 count
= inst
.operands
[1].imm
<< 1;
7670 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7673 inst
.instruction
|= count
;
7677 do_vfp_sp_ldstmia (void)
7679 vfp_sp_ldstm (VFP_LDSTMIA
);
7683 do_vfp_sp_ldstmdb (void)
7685 vfp_sp_ldstm (VFP_LDSTMDB
);
7689 do_vfp_dp_ldstmia (void)
7691 vfp_dp_ldstm (VFP_LDSTMIA
);
7695 do_vfp_dp_ldstmdb (void)
7697 vfp_dp_ldstm (VFP_LDSTMDB
);
7701 do_vfp_xp_ldstmia (void)
7703 vfp_dp_ldstm (VFP_LDSTMIAX
);
7707 do_vfp_xp_ldstmdb (void)
7709 vfp_dp_ldstm (VFP_LDSTMDBX
);
7713 do_vfp_dp_rd_rm (void)
7715 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7716 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7720 do_vfp_dp_rn_rd (void)
7722 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7723 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7727 do_vfp_dp_rd_rn (void)
7729 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7730 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7734 do_vfp_dp_rd_rn_rm (void)
7736 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7737 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7738 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7744 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7748 do_vfp_dp_rm_rd_rn (void)
7750 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7751 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7752 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7755 /* VFPv3 instructions. */
7757 do_vfp_sp_const (void)
7759 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7760 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7761 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7765 do_vfp_dp_const (void)
7767 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7768 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7769 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7773 vfp_conv (int srcsize
)
7775 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7776 inst
.instruction
|= (immbits
& 1) << 5;
7777 inst
.instruction
|= (immbits
>> 1);
7781 do_vfp_sp_conv_16 (void)
7783 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7788 do_vfp_dp_conv_16 (void)
7790 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7795 do_vfp_sp_conv_32 (void)
7797 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7802 do_vfp_dp_conv_32 (void)
7804 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7808 /* FPA instructions. Also in a logical order. */
7813 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7814 inst
.instruction
|= inst
.operands
[1].reg
;
7818 do_fpa_ldmstm (void)
7820 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7821 switch (inst
.operands
[1].imm
)
7823 case 1: inst
.instruction
|= CP_T_X
; break;
7824 case 2: inst
.instruction
|= CP_T_Y
; break;
7825 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7830 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7832 /* The instruction specified "ea" or "fd", so we can only accept
7833 [Rn]{!}. The instruction does not really support stacking or
7834 unstacking, so we have to emulate these by setting appropriate
7835 bits and offsets. */
7836 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7837 || inst
.reloc
.exp
.X_add_number
!= 0,
7838 _("this instruction does not support indexing"));
7840 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7841 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7843 if (!(inst
.instruction
& INDEX_UP
))
7844 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7846 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7848 inst
.operands
[2].preind
= 0;
7849 inst
.operands
[2].postind
= 1;
7853 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7856 /* iWMMXt instructions: strictly in alphabetical order. */
7859 do_iwmmxt_tandorc (void)
7861 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7865 do_iwmmxt_textrc (void)
7867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7868 inst
.instruction
|= inst
.operands
[1].imm
;
7872 do_iwmmxt_textrm (void)
7874 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7875 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7876 inst
.instruction
|= inst
.operands
[2].imm
;
7880 do_iwmmxt_tinsr (void)
7882 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7883 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7884 inst
.instruction
|= inst
.operands
[2].imm
;
7888 do_iwmmxt_tmia (void)
7890 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7891 inst
.instruction
|= inst
.operands
[1].reg
;
7892 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7896 do_iwmmxt_waligni (void)
7898 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7899 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7900 inst
.instruction
|= inst
.operands
[2].reg
;
7901 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7905 do_iwmmxt_wmerge (void)
7907 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7908 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7909 inst
.instruction
|= inst
.operands
[2].reg
;
7910 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
7914 do_iwmmxt_wmov (void)
7916 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7917 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7918 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7919 inst
.instruction
|= inst
.operands
[1].reg
;
7923 do_iwmmxt_wldstbh (void)
7926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7928 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7930 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7931 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7935 do_iwmmxt_wldstw (void)
7937 /* RIWR_RIWC clears .isreg for a control register. */
7938 if (!inst
.operands
[0].isreg
)
7940 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7941 inst
.instruction
|= 0xf0000000;
7944 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7945 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7949 do_iwmmxt_wldstd (void)
7951 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7952 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
7953 && inst
.operands
[1].immisreg
)
7955 inst
.instruction
&= ~0x1a000ff;
7956 inst
.instruction
|= (0xf << 28);
7957 if (inst
.operands
[1].preind
)
7958 inst
.instruction
|= PRE_INDEX
;
7959 if (!inst
.operands
[1].negative
)
7960 inst
.instruction
|= INDEX_UP
;
7961 if (inst
.operands
[1].writeback
)
7962 inst
.instruction
|= WRITE_BACK
;
7963 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7964 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
7965 inst
.instruction
|= inst
.operands
[1].imm
;
7968 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7972 do_iwmmxt_wshufh (void)
7974 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7975 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7976 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7977 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7981 do_iwmmxt_wzero (void)
7983 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7984 inst
.instruction
|= inst
.operands
[0].reg
;
7985 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7986 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7990 do_iwmmxt_wrwrwr_or_imm5 (void)
7992 if (inst
.operands
[2].isreg
)
7995 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
7996 _("immediate operand requires iWMMXt2"));
7998 if (inst
.operands
[2].imm
== 0)
8000 switch ((inst
.instruction
>> 20) & 0xf)
8006 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8007 inst
.operands
[2].imm
= 16;
8008 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8014 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8015 inst
.operands
[2].imm
= 32;
8016 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8023 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8025 wrn
= (inst
.instruction
>> 16) & 0xf;
8026 inst
.instruction
&= 0xff0fff0f;
8027 inst
.instruction
|= wrn
;
8028 /* Bail out here; the instruction is now assembled. */
8033 /* Map 32 -> 0, etc. */
8034 inst
.operands
[2].imm
&= 0x1f;
8035 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8039 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8040 operations first, then control, shift, and load/store. */
8042 /* Insns like "foo X,Y,Z". */
8045 do_mav_triple (void)
8047 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8048 inst
.instruction
|= inst
.operands
[1].reg
;
8049 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8052 /* Insns like "foo W,X,Y,Z".
8053 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8058 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8059 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8060 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8061 inst
.instruction
|= inst
.operands
[3].reg
;
8064 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8068 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8071 /* Maverick shift immediate instructions.
8072 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8073 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8078 int imm
= inst
.operands
[2].imm
;
8080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8083 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8084 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8085 Bit 4 should be 0. */
8086 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8088 inst
.instruction
|= imm
;
8091 /* XScale instructions. Also sorted arithmetic before move. */
8093 /* Xscale multiply-accumulate (argument parse)
8096 MIAxycc acc0,Rm,Rs. */
8101 inst
.instruction
|= inst
.operands
[1].reg
;
8102 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8105 /* Xscale move-accumulator-register (argument parse)
8107 MARcc acc0,RdLo,RdHi. */
8112 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8113 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8116 /* Xscale move-register-accumulator (argument parse)
8118 MRAcc RdLo,RdHi,acc0. */
8123 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8124 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8125 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8128 /* Encoding functions relevant only to Thumb. */
8130 /* inst.operands[i] is a shifted-register operand; encode
8131 it into inst.instruction in the format used by Thumb32. */
8134 encode_thumb32_shifted_operand (int i
)
8136 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8137 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8139 constraint (inst
.operands
[i
].immisreg
,
8140 _("shift by register not allowed in thumb mode"));
8141 inst
.instruction
|= inst
.operands
[i
].reg
;
8142 if (shift
== SHIFT_RRX
)
8143 inst
.instruction
|= SHIFT_ROR
<< 4;
8146 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8147 _("expression too complex"));
8149 constraint (value
> 32
8150 || (value
== 32 && (shift
== SHIFT_LSL
8151 || shift
== SHIFT_ROR
)),
8152 _("shift expression is too large"));
8156 else if (value
== 32)
8159 inst
.instruction
|= shift
<< 4;
8160 inst
.instruction
|= (value
& 0x1c) << 10;
8161 inst
.instruction
|= (value
& 0x03) << 6;
8166 /* inst.operands[i] was set up by parse_address. Encode it into a
8167 Thumb32 format load or store instruction. Reject forms that cannot
8168 be used with such instructions. If is_t is true, reject forms that
8169 cannot be used with a T instruction; if is_d is true, reject forms
8170 that cannot be used with a D instruction. */
8173 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8175 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8177 constraint (!inst
.operands
[i
].isreg
,
8178 _("Instruction does not support =N addresses"));
8180 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8181 if (inst
.operands
[i
].immisreg
)
8183 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8184 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8185 constraint (inst
.operands
[i
].negative
,
8186 _("Thumb does not support negative register indexing"));
8187 constraint (inst
.operands
[i
].postind
,
8188 _("Thumb does not support register post-indexing"));
8189 constraint (inst
.operands
[i
].writeback
,
8190 _("Thumb does not support register indexing with writeback"));
8191 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8192 _("Thumb supports only LSL in shifted register indexing"));
8194 inst
.instruction
|= inst
.operands
[i
].imm
;
8195 if (inst
.operands
[i
].shifted
)
8197 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8198 _("expression too complex"));
8199 constraint (inst
.reloc
.exp
.X_add_number
< 0
8200 || inst
.reloc
.exp
.X_add_number
> 3,
8201 _("shift out of range"));
8202 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8204 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8206 else if (inst
.operands
[i
].preind
)
8208 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8209 _("cannot use writeback with PC-relative addressing"));
8210 constraint (is_t
&& inst
.operands
[i
].writeback
,
8211 _("cannot use writeback with this instruction"));
8215 inst
.instruction
|= 0x01000000;
8216 if (inst
.operands
[i
].writeback
)
8217 inst
.instruction
|= 0x00200000;
8221 inst
.instruction
|= 0x00000c00;
8222 if (inst
.operands
[i
].writeback
)
8223 inst
.instruction
|= 0x00000100;
8225 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8227 else if (inst
.operands
[i
].postind
)
8229 assert (inst
.operands
[i
].writeback
);
8230 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8231 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8234 inst
.instruction
|= 0x00200000;
8236 inst
.instruction
|= 0x00000900;
8237 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8239 else /* unindexed - only for coprocessor */
8240 inst
.error
= _("instruction does not accept unindexed addressing");
8243 /* Table of Thumb instructions which exist in both 16- and 32-bit
8244 encodings (the latter only in post-V6T2 cores). The index is the
8245 value used in the insns table below. When there is more than one
8246 possible 16-bit encoding for the instruction, this table always
8248 Also contains several pseudo-instructions used during relaxation. */
8249 #define T16_32_TAB \
8250 X(adc, 4140, eb400000), \
8251 X(adcs, 4140, eb500000), \
8252 X(add, 1c00, eb000000), \
8253 X(adds, 1c00, eb100000), \
8254 X(addi, 0000, f1000000), \
8255 X(addis, 0000, f1100000), \
8256 X(add_pc,000f, f20f0000), \
8257 X(add_sp,000d, f10d0000), \
8258 X(adr, 000f, f20f0000), \
8259 X(and, 4000, ea000000), \
8260 X(ands, 4000, ea100000), \
8261 X(asr, 1000, fa40f000), \
8262 X(asrs, 1000, fa50f000), \
8263 X(b, e000, f000b000), \
8264 X(bcond, d000, f0008000), \
8265 X(bic, 4380, ea200000), \
8266 X(bics, 4380, ea300000), \
8267 X(cmn, 42c0, eb100f00), \
8268 X(cmp, 2800, ebb00f00), \
8269 X(cpsie, b660, f3af8400), \
8270 X(cpsid, b670, f3af8600), \
8271 X(cpy, 4600, ea4f0000), \
8272 X(dec_sp,80dd, f1ad0d00), \
8273 X(eor, 4040, ea800000), \
8274 X(eors, 4040, ea900000), \
8275 X(inc_sp,00dd, f10d0d00), \
8276 X(ldmia, c800, e8900000), \
8277 X(ldr, 6800, f8500000), \
8278 X(ldrb, 7800, f8100000), \
8279 X(ldrh, 8800, f8300000), \
8280 X(ldrsb, 5600, f9100000), \
8281 X(ldrsh, 5e00, f9300000), \
8282 X(ldr_pc,4800, f85f0000), \
8283 X(ldr_pc2,4800, f85f0000), \
8284 X(ldr_sp,9800, f85d0000), \
8285 X(lsl, 0000, fa00f000), \
8286 X(lsls, 0000, fa10f000), \
8287 X(lsr, 0800, fa20f000), \
8288 X(lsrs, 0800, fa30f000), \
8289 X(mov, 2000, ea4f0000), \
8290 X(movs, 2000, ea5f0000), \
8291 X(mul, 4340, fb00f000), \
8292 X(muls, 4340, ffffffff), /* no 32b muls */ \
8293 X(mvn, 43c0, ea6f0000), \
8294 X(mvns, 43c0, ea7f0000), \
8295 X(neg, 4240, f1c00000), /* rsb #0 */ \
8296 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8297 X(orr, 4300, ea400000), \
8298 X(orrs, 4300, ea500000), \
8299 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8300 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8301 X(rev, ba00, fa90f080), \
8302 X(rev16, ba40, fa90f090), \
8303 X(revsh, bac0, fa90f0b0), \
8304 X(ror, 41c0, fa60f000), \
8305 X(rors, 41c0, fa70f000), \
8306 X(sbc, 4180, eb600000), \
8307 X(sbcs, 4180, eb700000), \
8308 X(stmia, c000, e8800000), \
8309 X(str, 6000, f8400000), \
8310 X(strb, 7000, f8000000), \
8311 X(strh, 8000, f8200000), \
8312 X(str_sp,9000, f84d0000), \
8313 X(sub, 1e00, eba00000), \
8314 X(subs, 1e00, ebb00000), \
8315 X(subi, 8000, f1a00000), \
8316 X(subis, 8000, f1b00000), \
8317 X(sxtb, b240, fa4ff080), \
8318 X(sxth, b200, fa0ff080), \
8319 X(tst, 4200, ea100f00), \
8320 X(uxtb, b2c0, fa5ff080), \
8321 X(uxth, b280, fa1ff080), \
8322 X(nop, bf00, f3af8000), \
8323 X(yield, bf10, f3af8001), \
8324 X(wfe, bf20, f3af8002), \
8325 X(wfi, bf30, f3af8003), \
8326 X(sev, bf40, f3af9004), /* typo, 8004? */
8328 /* To catch errors in encoding functions, the codes are all offset by
8329 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8330 as 16-bit instructions. */
8331 #define X(a,b,c) T_MNEM_##a
8332 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8335 #define X(a,b,c) 0x##b
8336 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8337 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8340 #define X(a,b,c) 0x##c
8341 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8342 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8343 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8347 /* Thumb instruction encoders, in alphabetical order. */
8351 do_t_add_sub_w (void)
8355 Rd
= inst
.operands
[0].reg
;
8356 Rn
= inst
.operands
[1].reg
;
8358 constraint (Rd
== 15, _("PC not allowed as destination"));
8359 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8360 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8363 /* Parse an add or subtract instruction. We get here with inst.instruction
8364 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8371 Rd
= inst
.operands
[0].reg
;
8372 Rs
= (inst
.operands
[1].present
8373 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8374 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8382 flags
= (inst
.instruction
== T_MNEM_adds
8383 || inst
.instruction
== T_MNEM_subs
);
8385 narrow
= (current_it_mask
== 0);
8387 narrow
= (current_it_mask
!= 0);
8388 if (!inst
.operands
[2].isreg
)
8392 add
= (inst
.instruction
== T_MNEM_add
8393 || inst
.instruction
== T_MNEM_adds
);
8395 if (inst
.size_req
!= 4)
8397 /* Attempt to use a narrow opcode, with relaxation if
8399 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8400 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8401 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8402 opcode
= T_MNEM_add_sp
;
8403 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8404 opcode
= T_MNEM_add_pc
;
8405 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8408 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8410 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8414 inst
.instruction
= THUMB_OP16(opcode
);
8415 inst
.instruction
|= (Rd
<< 4) | Rs
;
8416 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8417 if (inst
.size_req
!= 2)
8418 inst
.relax
= opcode
;
8421 constraint (inst
.size_req
== 2, BAD_HIREG
);
8423 if (inst
.size_req
== 4
8424 || (inst
.size_req
!= 2 && !opcode
))
8428 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8429 _("only SUBS PC, LR, #const allowed"));
8430 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8431 _("expression too complex"));
8432 constraint (inst
.reloc
.exp
.X_add_number
< 0
8433 || inst
.reloc
.exp
.X_add_number
> 0xff,
8434 _("immediate value out of range"));
8435 inst
.instruction
= T2_SUBS_PC_LR
8436 | inst
.reloc
.exp
.X_add_number
;
8437 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8440 else if (Rs
== REG_PC
)
8442 /* Always use addw/subw. */
8443 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8444 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8448 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8449 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8452 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8454 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8456 inst
.instruction
|= Rd
<< 8;
8457 inst
.instruction
|= Rs
<< 16;
8462 Rn
= inst
.operands
[2].reg
;
8463 /* See if we can do this with a 16-bit instruction. */
8464 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8466 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8471 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8472 || inst
.instruction
== T_MNEM_add
)
8475 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8479 if (inst
.instruction
== T_MNEM_add
)
8483 inst
.instruction
= T_OPCODE_ADD_HI
;
8484 inst
.instruction
|= (Rd
& 8) << 4;
8485 inst
.instruction
|= (Rd
& 7);
8486 inst
.instruction
|= Rn
<< 3;
8489 /* ... because addition is commutative! */
8492 inst
.instruction
= T_OPCODE_ADD_HI
;
8493 inst
.instruction
|= (Rd
& 8) << 4;
8494 inst
.instruction
|= (Rd
& 7);
8495 inst
.instruction
|= Rs
<< 3;
8500 /* If we get here, it can't be done in 16 bits. */
8501 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8502 _("shift must be constant"));
8503 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8504 inst
.instruction
|= Rd
<< 8;
8505 inst
.instruction
|= Rs
<< 16;
8506 encode_thumb32_shifted_operand (2);
8511 constraint (inst
.instruction
== T_MNEM_adds
8512 || inst
.instruction
== T_MNEM_subs
,
8515 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8517 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8518 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8521 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8523 inst
.instruction
|= (Rd
<< 4) | Rs
;
8524 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8528 Rn
= inst
.operands
[2].reg
;
8529 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8531 /* We now have Rd, Rs, and Rn set to registers. */
8532 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8534 /* Can't do this for SUB. */
8535 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8536 inst
.instruction
= T_OPCODE_ADD_HI
;
8537 inst
.instruction
|= (Rd
& 8) << 4;
8538 inst
.instruction
|= (Rd
& 7);
8540 inst
.instruction
|= Rn
<< 3;
8542 inst
.instruction
|= Rs
<< 3;
8544 constraint (1, _("dest must overlap one source register"));
8548 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8549 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8550 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8558 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8560 /* Defer to section relaxation. */
8561 inst
.relax
= inst
.instruction
;
8562 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8563 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8565 else if (unified_syntax
&& inst
.size_req
!= 2)
8567 /* Generate a 32-bit opcode. */
8568 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8569 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8570 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8571 inst
.reloc
.pc_rel
= 1;
8575 /* Generate a 16-bit opcode. */
8576 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8577 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8578 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8579 inst
.reloc
.pc_rel
= 1;
8581 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8585 /* Arithmetic instructions for which there is just one 16-bit
8586 instruction encoding, and it allows only two low registers.
8587 For maximal compatibility with ARM syntax, we allow three register
8588 operands even when Thumb-32 instructions are not available, as long
8589 as the first two are identical. For instance, both "sbc r0,r1" and
8590 "sbc r0,r0,r1" are allowed. */
8596 Rd
= inst
.operands
[0].reg
;
8597 Rs
= (inst
.operands
[1].present
8598 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8599 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8600 Rn
= inst
.operands
[2].reg
;
8604 if (!inst
.operands
[2].isreg
)
8606 /* For an immediate, we always generate a 32-bit opcode;
8607 section relaxation will shrink it later if possible. */
8608 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8609 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8610 inst
.instruction
|= Rd
<< 8;
8611 inst
.instruction
|= Rs
<< 16;
8612 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8618 /* See if we can do this with a 16-bit instruction. */
8619 if (THUMB_SETS_FLAGS (inst
.instruction
))
8620 narrow
= current_it_mask
== 0;
8622 narrow
= current_it_mask
!= 0;
8624 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8626 if (inst
.operands
[2].shifted
)
8628 if (inst
.size_req
== 4)
8634 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8635 inst
.instruction
|= Rd
;
8636 inst
.instruction
|= Rn
<< 3;
8640 /* If we get here, it can't be done in 16 bits. */
8641 constraint (inst
.operands
[2].shifted
8642 && inst
.operands
[2].immisreg
,
8643 _("shift must be constant"));
8644 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8645 inst
.instruction
|= Rd
<< 8;
8646 inst
.instruction
|= Rs
<< 16;
8647 encode_thumb32_shifted_operand (2);
8652 /* On its face this is a lie - the instruction does set the
8653 flags. However, the only supported mnemonic in this mode
8655 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8657 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8658 _("unshifted register required"));
8659 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8660 constraint (Rd
!= Rs
,
8661 _("dest and source1 must be the same register"));
8663 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8664 inst
.instruction
|= Rd
;
8665 inst
.instruction
|= Rn
<< 3;
8669 /* Similarly, but for instructions where the arithmetic operation is
8670 commutative, so we can allow either of them to be different from
8671 the destination operand in a 16-bit instruction. For instance, all
8672 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8679 Rd
= inst
.operands
[0].reg
;
8680 Rs
= (inst
.operands
[1].present
8681 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8682 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8683 Rn
= inst
.operands
[2].reg
;
8687 if (!inst
.operands
[2].isreg
)
8689 /* For an immediate, we always generate a 32-bit opcode;
8690 section relaxation will shrink it later if possible. */
8691 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8692 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8693 inst
.instruction
|= Rd
<< 8;
8694 inst
.instruction
|= Rs
<< 16;
8695 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8701 /* See if we can do this with a 16-bit instruction. */
8702 if (THUMB_SETS_FLAGS (inst
.instruction
))
8703 narrow
= current_it_mask
== 0;
8705 narrow
= current_it_mask
!= 0;
8707 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8709 if (inst
.operands
[2].shifted
)
8711 if (inst
.size_req
== 4)
8718 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8719 inst
.instruction
|= Rd
;
8720 inst
.instruction
|= Rn
<< 3;
8725 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8726 inst
.instruction
|= Rd
;
8727 inst
.instruction
|= Rs
<< 3;
8732 /* If we get here, it can't be done in 16 bits. */
8733 constraint (inst
.operands
[2].shifted
8734 && inst
.operands
[2].immisreg
,
8735 _("shift must be constant"));
8736 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8737 inst
.instruction
|= Rd
<< 8;
8738 inst
.instruction
|= Rs
<< 16;
8739 encode_thumb32_shifted_operand (2);
8744 /* On its face this is a lie - the instruction does set the
8745 flags. However, the only supported mnemonic in this mode
8747 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8749 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8750 _("unshifted register required"));
8751 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8753 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8754 inst
.instruction
|= Rd
;
8757 inst
.instruction
|= Rn
<< 3;
8759 inst
.instruction
|= Rs
<< 3;
8761 constraint (1, _("dest must overlap one source register"));
8768 if (inst
.operands
[0].present
)
8770 constraint ((inst
.instruction
& 0xf0) != 0x40
8771 && inst
.operands
[0].imm
!= 0xf,
8772 _("bad barrier type"));
8773 inst
.instruction
|= inst
.operands
[0].imm
;
8776 inst
.instruction
|= 0xf;
8782 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8783 constraint (msb
> 32, _("bit-field extends past end of register"));
8784 /* The instruction encoding stores the LSB and MSB,
8785 not the LSB and width. */
8786 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8787 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8788 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8789 inst
.instruction
|= msb
- 1;
8797 /* #0 in second position is alternative syntax for bfc, which is
8798 the same instruction but with REG_PC in the Rm field. */
8799 if (!inst
.operands
[1].isreg
)
8800 inst
.operands
[1].reg
= REG_PC
;
8802 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8803 constraint (msb
> 32, _("bit-field extends past end of register"));
8804 /* The instruction encoding stores the LSB and MSB,
8805 not the LSB and width. */
8806 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8807 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8808 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8809 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8810 inst
.instruction
|= msb
- 1;
8816 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8817 _("bit-field extends past end of register"));
8818 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8819 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8820 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8821 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8822 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8825 /* ARM V5 Thumb BLX (argument parse)
8826 BLX <target_addr> which is BLX(1)
8827 BLX <Rm> which is BLX(2)
8828 Unfortunately, there are two different opcodes for this mnemonic.
8829 So, the insns[].value is not used, and the code here zaps values
8830 into inst.instruction.
8832 ??? How to take advantage of the additional two bits of displacement
8833 available in Thumb32 mode? Need new relocation? */
8838 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8839 if (inst
.operands
[0].isreg
)
8840 /* We have a register, so this is BLX(2). */
8841 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8844 /* No register. This must be BLX(1). */
8845 inst
.instruction
= 0xf000e800;
8847 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8848 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8851 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8852 inst
.reloc
.pc_rel
= 1;
8862 if (current_it_mask
)
8864 /* Conditional branches inside IT blocks are encoded as unconditional
8867 /* A branch must be the last instruction in an IT block. */
8868 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8873 if (cond
!= COND_ALWAYS
)
8874 opcode
= T_MNEM_bcond
;
8876 opcode
= inst
.instruction
;
8878 if (unified_syntax
&& inst
.size_req
== 4)
8880 inst
.instruction
= THUMB_OP32(opcode
);
8881 if (cond
== COND_ALWAYS
)
8882 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8885 assert (cond
!= 0xF);
8886 inst
.instruction
|= cond
<< 22;
8887 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8892 inst
.instruction
= THUMB_OP16(opcode
);
8893 if (cond
== COND_ALWAYS
)
8894 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8897 inst
.instruction
|= cond
<< 8;
8898 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8900 /* Allow section relaxation. */
8901 if (unified_syntax
&& inst
.size_req
!= 2)
8902 inst
.relax
= opcode
;
8905 inst
.reloc
.pc_rel
= 1;
8911 constraint (inst
.cond
!= COND_ALWAYS
,
8912 _("instruction is always unconditional"));
8913 if (inst
.operands
[0].present
)
8915 constraint (inst
.operands
[0].imm
> 255,
8916 _("immediate value out of range"));
8917 inst
.instruction
|= inst
.operands
[0].imm
;
8922 do_t_branch23 (void)
8924 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8925 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8926 inst
.reloc
.pc_rel
= 1;
8928 /* If the destination of the branch is a defined symbol which does not have
8929 the THUMB_FUNC attribute, then we must be calling a function which has
8930 the (interfacearm) attribute. We look for the Thumb entry point to that
8931 function and change the branch to refer to that function instead. */
8932 if ( inst
.reloc
.exp
.X_op
== O_symbol
8933 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8934 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8935 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8936 inst
.reloc
.exp
.X_add_symbol
=
8937 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8943 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8944 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8945 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8946 should cause the alignment to be checked once it is known. This is
8947 because BX PC only works if the instruction is word aligned. */
8953 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8954 if (inst
.operands
[0].reg
== REG_PC
)
8955 as_tsktsk (_("use of r15 in bxj is not really useful"));
8957 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8963 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8964 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8965 inst
.instruction
|= inst
.operands
[1].reg
;
8971 constraint (current_it_mask
, BAD_NOT_IT
);
8972 inst
.instruction
|= inst
.operands
[0].imm
;
8978 constraint (current_it_mask
, BAD_NOT_IT
);
8980 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8981 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8983 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8984 inst
.instruction
= 0xf3af8000;
8985 inst
.instruction
|= imod
<< 9;
8986 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8987 if (inst
.operands
[1].present
)
8988 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8992 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8993 && (inst
.operands
[0].imm
& 4),
8994 _("selected processor does not support 'A' form "
8995 "of this instruction"));
8996 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
8997 _("Thumb does not support the 2-argument "
8998 "form of this instruction"));
8999 inst
.instruction
|= inst
.operands
[0].imm
;
9003 /* THUMB CPY instruction (argument parse). */
9008 if (inst
.size_req
== 4)
9010 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9011 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9012 inst
.instruction
|= inst
.operands
[1].reg
;
9016 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9017 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9018 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9025 constraint (current_it_mask
, BAD_NOT_IT
);
9026 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9027 inst
.instruction
|= inst
.operands
[0].reg
;
9028 inst
.reloc
.pc_rel
= 1;
9029 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9035 inst
.instruction
|= inst
.operands
[0].imm
;
9041 if (!inst
.operands
[1].present
)
9042 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9043 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9044 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9045 inst
.instruction
|= inst
.operands
[2].reg
;
9051 if (unified_syntax
&& inst
.size_req
== 4)
9052 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9054 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9060 unsigned int cond
= inst
.operands
[0].imm
;
9062 constraint (current_it_mask
, BAD_NOT_IT
);
9063 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9066 /* If the condition is a negative condition, invert the mask. */
9067 if ((cond
& 0x1) == 0x0)
9069 unsigned int mask
= inst
.instruction
& 0x000f;
9071 if ((mask
& 0x7) == 0)
9072 /* no conversion needed */;
9073 else if ((mask
& 0x3) == 0)
9075 else if ((mask
& 0x1) == 0)
9080 inst
.instruction
&= 0xfff0;
9081 inst
.instruction
|= mask
;
9084 inst
.instruction
|= cond
<< 4;
9087 /* Helper function used for both push/pop and ldm/stm. */
9089 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9093 load
= (inst
.instruction
& (1 << 20)) != 0;
9095 if (mask
& (1 << 13))
9096 inst
.error
= _("SP not allowed in register list");
9099 if (mask
& (1 << 14)
9100 && mask
& (1 << 15))
9101 inst
.error
= _("LR and PC should not both be in register list");
9103 if ((mask
& (1 << base
)) != 0
9105 as_warn (_("base register should not be in register list "
9106 "when written back"));
9110 if (mask
& (1 << 15))
9111 inst
.error
= _("PC not allowed in register list");
9113 if (mask
& (1 << base
))
9114 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9117 if ((mask
& (mask
- 1)) == 0)
9119 /* Single register transfers implemented as str/ldr. */
9122 if (inst
.instruction
& (1 << 23))
9123 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9125 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9129 if (inst
.instruction
& (1 << 23))
9130 inst
.instruction
= 0x00800000; /* ia -> [base] */
9132 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9135 inst
.instruction
|= 0xf8400000;
9137 inst
.instruction
|= 0x00100000;
9139 mask
= ffs (mask
) - 1;
9143 inst
.instruction
|= WRITE_BACK
;
9145 inst
.instruction
|= mask
;
9146 inst
.instruction
|= base
<< 16;
9152 /* This really doesn't seem worth it. */
9153 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9154 _("expression too complex"));
9155 constraint (inst
.operands
[1].writeback
,
9156 _("Thumb load/store multiple does not support {reglist}^"));
9164 /* See if we can use a 16-bit instruction. */
9165 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9166 && inst
.size_req
!= 4
9167 && !(inst
.operands
[1].imm
& ~0xff))
9169 mask
= 1 << inst
.operands
[0].reg
;
9171 if (inst
.operands
[0].reg
<= 7
9172 && (inst
.instruction
== T_MNEM_stmia
9173 ? inst
.operands
[0].writeback
9174 : (inst
.operands
[0].writeback
9175 == !(inst
.operands
[1].imm
& mask
))))
9177 if (inst
.instruction
== T_MNEM_stmia
9178 && (inst
.operands
[1].imm
& mask
)
9179 && (inst
.operands
[1].imm
& (mask
- 1)))
9180 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9181 inst
.operands
[0].reg
);
9183 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9184 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9185 inst
.instruction
|= inst
.operands
[1].imm
;
9188 else if (inst
.operands
[0] .reg
== REG_SP
9189 && inst
.operands
[0].writeback
)
9191 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9192 ? T_MNEM_push
: T_MNEM_pop
);
9193 inst
.instruction
|= inst
.operands
[1].imm
;
9200 if (inst
.instruction
< 0xffff)
9201 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9203 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9204 inst
.operands
[0].writeback
);
9209 constraint (inst
.operands
[0].reg
> 7
9210 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9211 constraint (inst
.instruction
!= T_MNEM_ldmia
9212 && inst
.instruction
!= T_MNEM_stmia
,
9213 _("Thumb-2 instruction only valid in unified syntax"));
9214 if (inst
.instruction
== T_MNEM_stmia
)
9216 if (!inst
.operands
[0].writeback
)
9217 as_warn (_("this instruction will write back the base register"));
9218 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9219 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9220 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9221 inst
.operands
[0].reg
);
9225 if (!inst
.operands
[0].writeback
9226 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9227 as_warn (_("this instruction will write back the base register"));
9228 else if (inst
.operands
[0].writeback
9229 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9230 as_warn (_("this instruction will not write back the base register"));
9233 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9234 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9235 inst
.instruction
|= inst
.operands
[1].imm
;
9242 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9243 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9244 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9245 || inst
.operands
[1].negative
,
9248 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9249 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9250 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9256 if (!inst
.operands
[1].present
)
9258 constraint (inst
.operands
[0].reg
== REG_LR
,
9259 _("r14 not allowed as first register "
9260 "when second register is omitted"));
9261 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9263 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9266 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9267 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9268 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9274 unsigned long opcode
;
9277 opcode
= inst
.instruction
;
9280 if (!inst
.operands
[1].isreg
)
9282 if (opcode
<= 0xffff)
9283 inst
.instruction
= THUMB_OP32 (opcode
);
9284 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9287 if (inst
.operands
[1].isreg
9288 && !inst
.operands
[1].writeback
9289 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9290 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9292 && inst
.size_req
!= 4)
9294 /* Insn may have a 16-bit form. */
9295 Rn
= inst
.operands
[1].reg
;
9296 if (inst
.operands
[1].immisreg
)
9298 inst
.instruction
= THUMB_OP16 (opcode
);
9300 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9303 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9304 && opcode
!= T_MNEM_ldrsb
)
9305 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9306 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9313 if (inst
.reloc
.pc_rel
)
9314 opcode
= T_MNEM_ldr_pc2
;
9316 opcode
= T_MNEM_ldr_pc
;
9320 if (opcode
== T_MNEM_ldr
)
9321 opcode
= T_MNEM_ldr_sp
;
9323 opcode
= T_MNEM_str_sp
;
9325 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9329 inst
.instruction
= inst
.operands
[0].reg
;
9330 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9332 inst
.instruction
|= THUMB_OP16 (opcode
);
9333 if (inst
.size_req
== 2)
9334 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9336 inst
.relax
= opcode
;
9340 /* Definitely a 32-bit variant. */
9341 inst
.instruction
= THUMB_OP32 (opcode
);
9342 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9343 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9347 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9349 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9351 /* Only [Rn,Rm] is acceptable. */
9352 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9353 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9354 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9355 || inst
.operands
[1].negative
,
9356 _("Thumb does not support this addressing mode"));
9357 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9361 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9362 if (!inst
.operands
[1].isreg
)
9363 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9366 constraint (!inst
.operands
[1].preind
9367 || inst
.operands
[1].shifted
9368 || inst
.operands
[1].writeback
,
9369 _("Thumb does not support this addressing mode"));
9370 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9372 constraint (inst
.instruction
& 0x0600,
9373 _("byte or halfword not valid for base register"));
9374 constraint (inst
.operands
[1].reg
== REG_PC
9375 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9376 _("r15 based store not allowed"));
9377 constraint (inst
.operands
[1].immisreg
,
9378 _("invalid base register for register offset"));
9380 if (inst
.operands
[1].reg
== REG_PC
)
9381 inst
.instruction
= T_OPCODE_LDR_PC
;
9382 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9383 inst
.instruction
= T_OPCODE_LDR_SP
;
9385 inst
.instruction
= T_OPCODE_STR_SP
;
9387 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9388 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9392 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9393 if (!inst
.operands
[1].immisreg
)
9395 /* Immediate offset. */
9396 inst
.instruction
|= inst
.operands
[0].reg
;
9397 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9398 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9402 /* Register offset. */
9403 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9404 constraint (inst
.operands
[1].negative
,
9405 _("Thumb does not support this addressing mode"));
9408 switch (inst
.instruction
)
9410 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9411 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9412 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9413 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9414 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9415 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9416 case 0x5600 /* ldrsb */:
9417 case 0x5e00 /* ldrsh */: break;
9421 inst
.instruction
|= inst
.operands
[0].reg
;
9422 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9423 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9429 if (!inst
.operands
[1].present
)
9431 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9432 constraint (inst
.operands
[0].reg
== REG_LR
,
9433 _("r14 not allowed here"));
9435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9436 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9437 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9443 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9444 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9450 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9451 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9452 inst
.instruction
|= inst
.operands
[2].reg
;
9453 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9459 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9460 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9461 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9462 inst
.instruction
|= inst
.operands
[3].reg
;
9470 int r0off
= (inst
.instruction
== T_MNEM_mov
9471 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9472 unsigned long opcode
;
9474 bfd_boolean low_regs
;
9476 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9477 opcode
= inst
.instruction
;
9478 if (current_it_mask
)
9479 narrow
= opcode
!= T_MNEM_movs
;
9481 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9482 if (inst
.size_req
== 4
9483 || inst
.operands
[1].shifted
)
9486 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9487 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9488 && !inst
.operands
[1].shifted
9489 && inst
.operands
[0].reg
== REG_PC
9490 && inst
.operands
[1].reg
== REG_LR
)
9492 inst
.instruction
= T2_SUBS_PC_LR
;
9496 if (!inst
.operands
[1].isreg
)
9498 /* Immediate operand. */
9499 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9501 if (low_regs
&& narrow
)
9503 inst
.instruction
= THUMB_OP16 (opcode
);
9504 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9505 if (inst
.size_req
== 2)
9506 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9508 inst
.relax
= opcode
;
9512 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9513 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9514 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9515 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9518 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9519 && (inst
.instruction
== T_MNEM_mov
9520 || inst
.instruction
== T_MNEM_movs
))
9522 /* Register shifts are encoded as separate shift instructions. */
9523 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9525 if (current_it_mask
)
9530 if (inst
.size_req
== 4)
9533 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9536 if (inst
.operands
[0].reg
!= inst
.operands
[1].reg
)
9539 switch (inst
.operands
[1].shift_kind
)
9542 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9545 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9548 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9551 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9557 inst
.instruction
= opcode
;
9560 inst
.instruction
|= inst
.operands
[0].reg
;
9561 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9566 inst
.instruction
|= CONDS_BIT
;
9568 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9569 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9570 inst
.instruction
|= inst
.operands
[1].imm
;
9575 /* Some mov with immediate shift have narrow variants.
9576 Register shifts are handled above. */
9577 if (low_regs
&& inst
.operands
[1].shifted
9578 && (inst
.instruction
== T_MNEM_mov
9579 || inst
.instruction
== T_MNEM_movs
))
9581 if (current_it_mask
)
9582 narrow
= (inst
.instruction
== T_MNEM_mov
);
9584 narrow
= (inst
.instruction
== T_MNEM_movs
);
9589 switch (inst
.operands
[1].shift_kind
)
9591 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9592 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9593 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9594 default: narrow
= FALSE
; break;
9600 inst
.instruction
|= inst
.operands
[0].reg
;
9601 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9602 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9606 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9607 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9608 encode_thumb32_shifted_operand (1);
9612 switch (inst
.instruction
)
9615 inst
.instruction
= T_OPCODE_MOV_HR
;
9616 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9617 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9618 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9622 /* We know we have low registers at this point.
9623 Generate ADD Rd, Rs, #0. */
9624 inst
.instruction
= T_OPCODE_ADD_I3
;
9625 inst
.instruction
|= inst
.operands
[0].reg
;
9626 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9632 inst
.instruction
= T_OPCODE_CMP_LR
;
9633 inst
.instruction
|= inst
.operands
[0].reg
;
9634 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9638 inst
.instruction
= T_OPCODE_CMP_HR
;
9639 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9640 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9641 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9648 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9649 if (inst
.operands
[1].isreg
)
9651 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9653 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9654 since a MOV instruction produces unpredictable results. */
9655 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9656 inst
.instruction
= T_OPCODE_ADD_I3
;
9658 inst
.instruction
= T_OPCODE_CMP_LR
;
9660 inst
.instruction
|= inst
.operands
[0].reg
;
9661 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9665 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9666 inst
.instruction
= T_OPCODE_MOV_HR
;
9668 inst
.instruction
= T_OPCODE_CMP_HR
;
9674 constraint (inst
.operands
[0].reg
> 7,
9675 _("only lo regs allowed with immediate"));
9676 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9677 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9687 top
= (inst
.instruction
& 0x00800000) != 0;
9688 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9690 constraint (top
, _(":lower16: not allowed this instruction"));
9691 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9693 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9695 constraint (!top
, _(":upper16: not allowed this instruction"));
9696 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9699 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9700 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9702 imm
= inst
.reloc
.exp
.X_add_number
;
9703 inst
.instruction
|= (imm
& 0xf000) << 4;
9704 inst
.instruction
|= (imm
& 0x0800) << 15;
9705 inst
.instruction
|= (imm
& 0x0700) << 4;
9706 inst
.instruction
|= (imm
& 0x00ff);
9715 int r0off
= (inst
.instruction
== T_MNEM_mvn
9716 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9719 if (inst
.size_req
== 4
9720 || inst
.instruction
> 0xffff
9721 || inst
.operands
[1].shifted
9722 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9724 else if (inst
.instruction
== T_MNEM_cmn
)
9726 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9727 narrow
= (current_it_mask
== 0);
9729 narrow
= (current_it_mask
!= 0);
9731 if (!inst
.operands
[1].isreg
)
9733 /* For an immediate, we always generate a 32-bit opcode;
9734 section relaxation will shrink it later if possible. */
9735 if (inst
.instruction
< 0xffff)
9736 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9737 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9738 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9739 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9743 /* See if we can do this with a 16-bit instruction. */
9746 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9747 inst
.instruction
|= inst
.operands
[0].reg
;
9748 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9752 constraint (inst
.operands
[1].shifted
9753 && inst
.operands
[1].immisreg
,
9754 _("shift must be constant"));
9755 if (inst
.instruction
< 0xffff)
9756 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9757 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9758 encode_thumb32_shifted_operand (1);
9764 constraint (inst
.instruction
> 0xffff
9765 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9766 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9767 _("unshifted register required"));
9768 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9771 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9772 inst
.instruction
|= inst
.operands
[0].reg
;
9773 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9782 if (do_vfp_nsyn_mrs () == SUCCESS
)
9785 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9788 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9789 _("selected processor does not support "
9790 "requested special purpose register"));
9794 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9795 _("selected processor does not support "
9796 "requested special purpose register %x"));
9797 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9798 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9799 _("'CPSR' or 'SPSR' expected"));
9802 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9803 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9804 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9812 if (do_vfp_nsyn_msr () == SUCCESS
)
9815 constraint (!inst
.operands
[1].isreg
,
9816 _("Thumb encoding does not support an immediate here"));
9817 flags
= inst
.operands
[0].imm
;
9820 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9821 _("selected processor does not support "
9822 "requested special purpose register"));
9826 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9827 _("selected processor does not support "
9828 "requested special purpose register"));
9831 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9832 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9833 inst
.instruction
|= (flags
& 0xff);
9834 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9840 if (!inst
.operands
[2].present
)
9841 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9843 /* There is no 32-bit MULS and no 16-bit MUL. */
9844 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9846 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9847 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9848 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9849 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9853 constraint (!unified_syntax
9854 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9855 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9858 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9859 inst
.instruction
|= inst
.operands
[0].reg
;
9861 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9862 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9863 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9864 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9866 constraint (1, _("dest must overlap one source register"));
9873 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9874 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9875 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9876 inst
.instruction
|= inst
.operands
[3].reg
;
9878 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9879 as_tsktsk (_("rdhi and rdlo must be different"));
9887 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9889 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9890 inst
.instruction
|= inst
.operands
[0].imm
;
9894 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9895 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9900 constraint (inst
.operands
[0].present
,
9901 _("Thumb does not support NOP with hints"));
9902 inst
.instruction
= 0x46c0;
9913 if (THUMB_SETS_FLAGS (inst
.instruction
))
9914 narrow
= (current_it_mask
== 0);
9916 narrow
= (current_it_mask
!= 0);
9917 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9919 if (inst
.size_req
== 4)
9924 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9925 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9926 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9930 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9931 inst
.instruction
|= inst
.operands
[0].reg
;
9932 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9937 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9939 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9941 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9942 inst
.instruction
|= inst
.operands
[0].reg
;
9943 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9950 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9951 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9952 inst
.instruction
|= inst
.operands
[2].reg
;
9953 if (inst
.operands
[3].present
)
9955 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9956 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9957 _("expression too complex"));
9958 inst
.instruction
|= (val
& 0x1c) << 10;
9959 inst
.instruction
|= (val
& 0x03) << 6;
9966 if (!inst
.operands
[3].present
)
9967 inst
.instruction
&= ~0x00000020;
9974 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9978 do_t_push_pop (void)
9982 constraint (inst
.operands
[0].writeback
,
9983 _("push/pop do not support {reglist}^"));
9984 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9985 _("expression too complex"));
9987 mask
= inst
.operands
[0].imm
;
9988 if ((mask
& ~0xff) == 0)
9989 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
9990 else if ((inst
.instruction
== T_MNEM_push
9991 && (mask
& ~0xff) == 1 << REG_LR
)
9992 || (inst
.instruction
== T_MNEM_pop
9993 && (mask
& ~0xff) == 1 << REG_PC
))
9995 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9996 inst
.instruction
|= THUMB_PP_PC_LR
;
9997 inst
.instruction
|= mask
& 0xff;
9999 else if (unified_syntax
)
10001 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10002 encode_thumb2_ldmstm (13, mask
, TRUE
);
10006 inst
.error
= _("invalid register list to push/pop instruction");
10014 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10015 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10021 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10022 && inst
.size_req
!= 4)
10024 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10025 inst
.instruction
|= inst
.operands
[0].reg
;
10026 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10028 else if (unified_syntax
)
10030 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10031 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10032 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10033 inst
.instruction
|= inst
.operands
[1].reg
;
10036 inst
.error
= BAD_HIREG
;
10044 Rd
= inst
.operands
[0].reg
;
10045 Rs
= (inst
.operands
[1].present
10046 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10047 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10049 inst
.instruction
|= Rd
<< 8;
10050 inst
.instruction
|= Rs
<< 16;
10051 if (!inst
.operands
[2].isreg
)
10053 bfd_boolean narrow
;
10055 if ((inst
.instruction
& 0x00100000) != 0)
10056 narrow
= (current_it_mask
== 0);
10058 narrow
= (current_it_mask
!= 0);
10060 if (Rd
> 7 || Rs
> 7)
10063 if (inst
.size_req
== 4 || !unified_syntax
)
10066 if (inst
.reloc
.exp
.X_op
!= O_constant
10067 || inst
.reloc
.exp
.X_add_number
!= 0)
10070 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10071 relaxation, but it doesn't seem worth the hassle. */
10074 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10075 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10076 inst
.instruction
|= Rs
<< 3;
10077 inst
.instruction
|= Rd
;
10081 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10082 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10086 encode_thumb32_shifted_operand (2);
10092 constraint (current_it_mask
, BAD_NOT_IT
);
10093 if (inst
.operands
[0].imm
)
10094 inst
.instruction
|= 0x8;
10100 if (!inst
.operands
[1].present
)
10101 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10103 if (unified_syntax
)
10105 bfd_boolean narrow
;
10108 switch (inst
.instruction
)
10111 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10113 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10115 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10117 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10121 if (THUMB_SETS_FLAGS (inst
.instruction
))
10122 narrow
= (current_it_mask
== 0);
10124 narrow
= (current_it_mask
!= 0);
10125 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10127 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10129 if (inst
.operands
[2].isreg
10130 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10131 || inst
.operands
[2].reg
> 7))
10133 if (inst
.size_req
== 4)
10138 if (inst
.operands
[2].isreg
)
10140 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10141 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10142 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10143 inst
.instruction
|= inst
.operands
[2].reg
;
10147 inst
.operands
[1].shifted
= 1;
10148 inst
.operands
[1].shift_kind
= shift_kind
;
10149 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10150 ? T_MNEM_movs
: T_MNEM_mov
);
10151 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10152 encode_thumb32_shifted_operand (1);
10153 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10154 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10159 if (inst
.operands
[2].isreg
)
10161 switch (shift_kind
)
10163 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10164 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10165 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10166 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10170 inst
.instruction
|= inst
.operands
[0].reg
;
10171 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10175 switch (shift_kind
)
10177 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10178 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10179 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10182 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10183 inst
.instruction
|= inst
.operands
[0].reg
;
10184 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10190 constraint (inst
.operands
[0].reg
> 7
10191 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10192 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10194 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10196 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10197 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10198 _("source1 and dest must be same register"));
10200 switch (inst
.instruction
)
10202 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10203 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10204 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10205 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10209 inst
.instruction
|= inst
.operands
[0].reg
;
10210 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10214 switch (inst
.instruction
)
10216 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10217 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10218 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10219 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10222 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10223 inst
.instruction
|= inst
.operands
[0].reg
;
10224 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10232 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10233 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10234 inst
.instruction
|= inst
.operands
[2].reg
;
10240 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10241 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10242 _("expression too complex"));
10243 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10244 inst
.instruction
|= (value
& 0xf000) >> 12;
10245 inst
.instruction
|= (value
& 0x0ff0);
10246 inst
.instruction
|= (value
& 0x000f) << 16;
10252 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10253 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10254 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10256 if (inst
.operands
[3].present
)
10258 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10259 _("expression too complex"));
10261 if (inst
.reloc
.exp
.X_add_number
!= 0)
10263 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10264 inst
.instruction
|= 0x00200000; /* sh bit */
10265 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10266 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10268 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10275 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10276 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10277 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10283 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10284 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10285 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10286 || inst
.operands
[2].negative
,
10289 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10290 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10291 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10292 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10298 if (!inst
.operands
[2].present
)
10299 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10301 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10302 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10303 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10304 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10307 inst
.instruction
|= inst
.operands
[0].reg
;
10308 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10309 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10310 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10316 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10317 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10318 inst
.instruction
|= inst
.operands
[2].reg
;
10319 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10325 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10326 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10327 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10329 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10330 inst
.instruction
|= inst
.operands
[0].reg
;
10331 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10333 else if (unified_syntax
)
10335 if (inst
.instruction
<= 0xffff)
10336 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10337 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10338 inst
.instruction
|= inst
.operands
[1].reg
;
10339 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10343 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10344 _("Thumb encoding does not support rotation"));
10345 constraint (1, BAD_HIREG
);
10352 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10360 half
= (inst
.instruction
& 0x10) != 0;
10361 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10362 constraint (inst
.operands
[0].immisreg
,
10363 _("instruction requires register index"));
10364 constraint (inst
.operands
[0].imm
== 15,
10365 _("PC is not a valid index register"));
10366 constraint (!half
&& inst
.operands
[0].shifted
,
10367 _("instruction does not allow shifted index"));
10368 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10374 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10375 inst
.instruction
|= inst
.operands
[1].imm
;
10376 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10378 if (inst
.operands
[3].present
)
10380 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10381 _("expression too complex"));
10382 if (inst
.reloc
.exp
.X_add_number
!= 0)
10384 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10385 inst
.instruction
|= 0x00200000; /* sh bit */
10387 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10388 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10390 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10397 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10398 inst
.instruction
|= inst
.operands
[1].imm
;
10399 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10402 /* Neon instruction encoder helpers. */
10404 /* Encodings for the different types for various Neon opcodes. */
10406 /* An "invalid" code for the following tables. */
10409 struct neon_tab_entry
10412 unsigned float_or_poly
;
10413 unsigned scalar_or_imm
;
10416 /* Map overloaded Neon opcodes to their respective encodings. */
10417 #define NEON_ENC_TAB \
10418 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10419 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10420 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10421 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10422 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10423 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10424 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10425 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10426 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10427 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10428 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10429 /* Register variants of the following two instructions are encoded as
10430 vcge / vcgt with the operands reversed. */ \
10431 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10432 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10433 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10434 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10435 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10436 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10437 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10438 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10439 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10440 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10441 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10442 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10443 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10444 X(vshl, 0x0000400, N_INV, 0x0800510), \
10445 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10446 X(vand, 0x0000110, N_INV, 0x0800030), \
10447 X(vbic, 0x0100110, N_INV, 0x0800030), \
10448 X(veor, 0x1000110, N_INV, N_INV), \
10449 X(vorn, 0x0300110, N_INV, 0x0800010), \
10450 X(vorr, 0x0200110, N_INV, 0x0800010), \
10451 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10452 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10453 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10454 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10455 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10456 X(vst1, 0x0000000, 0x0800000, N_INV), \
10457 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10458 X(vst2, 0x0000100, 0x0800100, N_INV), \
10459 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10460 X(vst3, 0x0000200, 0x0800200, N_INV), \
10461 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10462 X(vst4, 0x0000300, 0x0800300, N_INV), \
10463 X(vmovn, 0x1b20200, N_INV, N_INV), \
10464 X(vtrn, 0x1b20080, N_INV, N_INV), \
10465 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10466 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10467 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10468 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10469 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10470 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10471 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10472 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10473 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10477 #define X(OPC,I,F,S) N_MNEM_##OPC
10482 static const struct neon_tab_entry neon_enc_tab
[] =
10484 #define X(OPC,I,F,S) { (I), (F), (S) }
10489 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10490 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10491 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10492 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10493 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10494 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10495 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10496 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10497 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10498 #define NEON_ENC_SINGLE(X) \
10499 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10500 #define NEON_ENC_DOUBLE(X) \
10501 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10503 /* Define shapes for instruction operands. The following mnemonic characters
10504 are used in this table:
10506 F - VFP S<n> register
10507 D - Neon D<n> register
10508 Q - Neon Q<n> register
10512 L - D<n> register list
10514 This table is used to generate various data:
10515 - enumerations of the form NS_DDR to be used as arguments to
10517 - a table classifying shapes into single, double, quad, mixed.
10518 - a table used to drive neon_select_shape. */
10520 #define NEON_SHAPE_DEF \
10521 X(3, (D, D, D), DOUBLE), \
10522 X(3, (Q, Q, Q), QUAD), \
10523 X(3, (D, D, I), DOUBLE), \
10524 X(3, (Q, Q, I), QUAD), \
10525 X(3, (D, D, S), DOUBLE), \
10526 X(3, (Q, Q, S), QUAD), \
10527 X(2, (D, D), DOUBLE), \
10528 X(2, (Q, Q), QUAD), \
10529 X(2, (D, S), DOUBLE), \
10530 X(2, (Q, S), QUAD), \
10531 X(2, (D, R), DOUBLE), \
10532 X(2, (Q, R), QUAD), \
10533 X(2, (D, I), DOUBLE), \
10534 X(2, (Q, I), QUAD), \
10535 X(3, (D, L, D), DOUBLE), \
10536 X(2, (D, Q), MIXED), \
10537 X(2, (Q, D), MIXED), \
10538 X(3, (D, Q, I), MIXED), \
10539 X(3, (Q, D, I), MIXED), \
10540 X(3, (Q, D, D), MIXED), \
10541 X(3, (D, Q, Q), MIXED), \
10542 X(3, (Q, Q, D), MIXED), \
10543 X(3, (Q, D, S), MIXED), \
10544 X(3, (D, Q, S), MIXED), \
10545 X(4, (D, D, D, I), DOUBLE), \
10546 X(4, (Q, Q, Q, I), QUAD), \
10547 X(2, (F, F), SINGLE), \
10548 X(3, (F, F, F), SINGLE), \
10549 X(2, (F, I), SINGLE), \
10550 X(2, (F, D), MIXED), \
10551 X(2, (D, F), MIXED), \
10552 X(3, (F, F, I), MIXED), \
10553 X(4, (R, R, F, F), SINGLE), \
10554 X(4, (F, F, R, R), SINGLE), \
10555 X(3, (D, R, R), DOUBLE), \
10556 X(3, (R, R, D), DOUBLE), \
10557 X(2, (S, R), SINGLE), \
10558 X(2, (R, S), SINGLE), \
10559 X(2, (F, R), SINGLE), \
10560 X(2, (R, F), SINGLE)
10562 #define S2(A,B) NS_##A##B
10563 #define S3(A,B,C) NS_##A##B##C
10564 #define S4(A,B,C,D) NS_##A##B##C##D
10566 #define X(N, L, C) S##N L
10579 enum neon_shape_class
10587 #define X(N, L, C) SC_##C
10589 static enum neon_shape_class neon_shape_class
[] =
10607 /* Register widths of above. */
10608 static unsigned neon_shape_el_size
[] =
10619 struct neon_shape_info
10622 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10625 #define S2(A,B) { SE_##A, SE_##B }
10626 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10627 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10629 #define X(N, L, C) { N, S##N L }
10631 static struct neon_shape_info neon_shape_tab
[] =
10641 /* Bit masks used in type checking given instructions.
10642 'N_EQK' means the type must be the same as (or based on in some way) the key
10643 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10644 set, various other bits can be set as well in order to modify the meaning of
10645 the type constraint. */
10647 enum neon_type_mask
10669 N_KEY
= 0x100000, /* key element (main type specifier). */
10670 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10671 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10672 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10673 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10674 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10675 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10676 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10677 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10678 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10680 N_MAX_NONSPECIAL
= N_F64
10683 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10685 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10686 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10687 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10688 #define N_SUF_32 (N_SU_32 | N_F32)
10689 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10690 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10692 /* Pass this as the first type argument to neon_check_type to ignore types
10694 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10696 /* Select a "shape" for the current instruction (describing register types or
10697 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10698 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10699 function of operand parsing, so this function doesn't need to be called.
10700 Shapes should be listed in order of decreasing length. */
10702 static enum neon_shape
10703 neon_select_shape (enum neon_shape shape
, ...)
10706 enum neon_shape first_shape
= shape
;
10708 /* Fix missing optional operands. FIXME: we don't know at this point how
10709 many arguments we should have, so this makes the assumption that we have
10710 > 1. This is true of all current Neon opcodes, I think, but may not be
10711 true in the future. */
10712 if (!inst
.operands
[1].present
)
10713 inst
.operands
[1] = inst
.operands
[0];
10715 va_start (ap
, shape
);
10717 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10722 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10724 if (!inst
.operands
[j
].present
)
10730 switch (neon_shape_tab
[shape
].el
[j
])
10733 if (!(inst
.operands
[j
].isreg
10734 && inst
.operands
[j
].isvec
10735 && inst
.operands
[j
].issingle
10736 && !inst
.operands
[j
].isquad
))
10741 if (!(inst
.operands
[j
].isreg
10742 && inst
.operands
[j
].isvec
10743 && !inst
.operands
[j
].isquad
10744 && !inst
.operands
[j
].issingle
))
10749 if (!(inst
.operands
[j
].isreg
10750 && !inst
.operands
[j
].isvec
))
10755 if (!(inst
.operands
[j
].isreg
10756 && inst
.operands
[j
].isvec
10757 && inst
.operands
[j
].isquad
10758 && !inst
.operands
[j
].issingle
))
10763 if (!(!inst
.operands
[j
].isreg
10764 && !inst
.operands
[j
].isscalar
))
10769 if (!(!inst
.operands
[j
].isreg
10770 && inst
.operands
[j
].isscalar
))
10784 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10785 first_error (_("invalid instruction shape"));
10790 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10791 means the Q bit should be set). */
10794 neon_quad (enum neon_shape shape
)
10796 return neon_shape_class
[shape
] == SC_QUAD
;
10800 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10803 /* Allow modification to be made to types which are constrained to be
10804 based on the key element, based on bits set alongside N_EQK. */
10805 if ((typebits
& N_EQK
) != 0)
10807 if ((typebits
& N_HLF
) != 0)
10809 else if ((typebits
& N_DBL
) != 0)
10811 if ((typebits
& N_SGN
) != 0)
10812 *g_type
= NT_signed
;
10813 else if ((typebits
& N_UNS
) != 0)
10814 *g_type
= NT_unsigned
;
10815 else if ((typebits
& N_INT
) != 0)
10816 *g_type
= NT_integer
;
10817 else if ((typebits
& N_FLT
) != 0)
10818 *g_type
= NT_float
;
10819 else if ((typebits
& N_SIZ
) != 0)
10820 *g_type
= NT_untyped
;
10824 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10825 operand type, i.e. the single type specified in a Neon instruction when it
10826 is the only one given. */
10828 static struct neon_type_el
10829 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10831 struct neon_type_el dest
= *key
;
10833 assert ((thisarg
& N_EQK
) != 0);
10835 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10840 /* Convert Neon type and size into compact bitmask representation. */
10842 static enum neon_type_mask
10843 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10850 case 8: return N_8
;
10851 case 16: return N_16
;
10852 case 32: return N_32
;
10853 case 64: return N_64
;
10861 case 8: return N_I8
;
10862 case 16: return N_I16
;
10863 case 32: return N_I32
;
10864 case 64: return N_I64
;
10872 case 32: return N_F32
;
10873 case 64: return N_F64
;
10881 case 8: return N_P8
;
10882 case 16: return N_P16
;
10890 case 8: return N_S8
;
10891 case 16: return N_S16
;
10892 case 32: return N_S32
;
10893 case 64: return N_S64
;
10901 case 8: return N_U8
;
10902 case 16: return N_U16
;
10903 case 32: return N_U32
;
10904 case 64: return N_U64
;
10915 /* Convert compact Neon bitmask type representation to a type and size. Only
10916 handles the case where a single bit is set in the mask. */
10919 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10920 enum neon_type_mask mask
)
10922 if ((mask
& N_EQK
) != 0)
10925 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10927 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10929 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10931 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10936 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10938 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10939 *type
= NT_unsigned
;
10940 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10941 *type
= NT_integer
;
10942 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10943 *type
= NT_untyped
;
10944 else if ((mask
& (N_P8
| N_P16
)) != 0)
10946 else if ((mask
& (N_F32
| N_F64
)) != 0)
10954 /* Modify a bitmask of allowed types. This is only needed for type
10958 modify_types_allowed (unsigned allowed
, unsigned mods
)
10961 enum neon_el_type type
;
10967 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10969 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10971 neon_modify_type_size (mods
, &type
, &size
);
10972 destmask
|= type_chk_of_el_type (type
, size
);
10979 /* Check type and return type classification.
10980 The manual states (paraphrase): If one datatype is given, it indicates the
10982 - the second operand, if there is one
10983 - the operand, if there is no second operand
10984 - the result, if there are no operands.
10985 This isn't quite good enough though, so we use a concept of a "key" datatype
10986 which is set on a per-instruction basis, which is the one which matters when
10987 only one data type is written.
10988 Note: this function has side-effects (e.g. filling in missing operands). All
10989 Neon instructions should call it before performing bit encoding. */
10991 static struct neon_type_el
10992 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10995 unsigned i
, pass
, key_el
= 0;
10996 unsigned types
[NEON_MAX_TYPE_ELS
];
10997 enum neon_el_type k_type
= NT_invtype
;
10998 unsigned k_size
= -1u;
10999 struct neon_type_el badtype
= {NT_invtype
, -1};
11000 unsigned key_allowed
= 0;
11002 /* Optional registers in Neon instructions are always (not) in operand 1.
11003 Fill in the missing operand here, if it was omitted. */
11004 if (els
> 1 && !inst
.operands
[1].present
)
11005 inst
.operands
[1] = inst
.operands
[0];
11007 /* Suck up all the varargs. */
11009 for (i
= 0; i
< els
; i
++)
11011 unsigned thisarg
= va_arg (ap
, unsigned);
11012 if (thisarg
== N_IGNORE_TYPE
)
11017 types
[i
] = thisarg
;
11018 if ((thisarg
& N_KEY
) != 0)
11023 if (inst
.vectype
.elems
> 0)
11024 for (i
= 0; i
< els
; i
++)
11025 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11027 first_error (_("types specified in both the mnemonic and operands"));
11031 /* Duplicate inst.vectype elements here as necessary.
11032 FIXME: No idea if this is exactly the same as the ARM assembler,
11033 particularly when an insn takes one register and one non-register
11035 if (inst
.vectype
.elems
== 1 && els
> 1)
11038 inst
.vectype
.elems
= els
;
11039 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11040 for (j
= 0; j
< els
; j
++)
11042 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11045 else if (inst
.vectype
.elems
== 0 && els
> 0)
11048 /* No types were given after the mnemonic, so look for types specified
11049 after each operand. We allow some flexibility here; as long as the
11050 "key" operand has a type, we can infer the others. */
11051 for (j
= 0; j
< els
; j
++)
11052 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11053 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11055 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11057 for (j
= 0; j
< els
; j
++)
11058 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11059 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11064 first_error (_("operand types can't be inferred"));
11068 else if (inst
.vectype
.elems
!= els
)
11070 first_error (_("type specifier has the wrong number of parts"));
11074 for (pass
= 0; pass
< 2; pass
++)
11076 for (i
= 0; i
< els
; i
++)
11078 unsigned thisarg
= types
[i
];
11079 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11080 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11081 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11082 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11084 /* Decay more-specific signed & unsigned types to sign-insensitive
11085 integer types if sign-specific variants are unavailable. */
11086 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11087 && (types_allowed
& N_SU_ALL
) == 0)
11088 g_type
= NT_integer
;
11090 /* If only untyped args are allowed, decay any more specific types to
11091 them. Some instructions only care about signs for some element
11092 sizes, so handle that properly. */
11093 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11094 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11095 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11096 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11097 g_type
= NT_untyped
;
11101 if ((thisarg
& N_KEY
) != 0)
11105 key_allowed
= thisarg
& ~N_KEY
;
11110 if ((thisarg
& N_VFP
) != 0)
11112 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11113 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11115 /* In VFP mode, operands must match register widths. If we
11116 have a key operand, use its width, else use the width of
11117 the current operand. */
11123 if (regwidth
!= match
)
11125 first_error (_("operand size must match register width"));
11130 if ((thisarg
& N_EQK
) == 0)
11132 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11134 if ((given_type
& types_allowed
) == 0)
11136 first_error (_("bad type in Neon instruction"));
11142 enum neon_el_type mod_k_type
= k_type
;
11143 unsigned mod_k_size
= k_size
;
11144 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11145 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11147 first_error (_("inconsistent types in Neon instruction"));
11155 return inst
.vectype
.el
[key_el
];
11158 /* Neon-style VFP instruction forwarding. */
11160 /* Thumb VFP instructions have 0xE in the condition field. */
11163 do_vfp_cond_or_thumb (void)
11166 inst
.instruction
|= 0xe0000000;
11168 inst
.instruction
|= inst
.cond
<< 28;
11171 /* Look up and encode a simple mnemonic, for use as a helper function for the
11172 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11173 etc. It is assumed that operand parsing has already been done, and that the
11174 operands are in the form expected by the given opcode (this isn't necessarily
11175 the same as the form in which they were parsed, hence some massaging must
11176 take place before this function is called).
11177 Checks current arch version against that in the looked-up opcode. */
11180 do_vfp_nsyn_opcode (const char *opname
)
11182 const struct asm_opcode
*opcode
;
11184 opcode
= hash_find (arm_ops_hsh
, opname
);
11189 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11190 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11195 inst
.instruction
= opcode
->tvalue
;
11196 opcode
->tencode ();
11200 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11201 opcode
->aencode ();
11206 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11208 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11213 do_vfp_nsyn_opcode ("fadds");
11215 do_vfp_nsyn_opcode ("fsubs");
11220 do_vfp_nsyn_opcode ("faddd");
11222 do_vfp_nsyn_opcode ("fsubd");
11226 /* Check operand types to see if this is a VFP instruction, and if so call
11230 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11232 enum neon_shape rs
;
11233 struct neon_type_el et
;
11238 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11239 et
= neon_check_type (2, rs
,
11240 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11244 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11245 et
= neon_check_type (3, rs
,
11246 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11253 if (et
.type
!= NT_invtype
)
11265 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11267 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11272 do_vfp_nsyn_opcode ("fmacs");
11274 do_vfp_nsyn_opcode ("fmscs");
11279 do_vfp_nsyn_opcode ("fmacd");
11281 do_vfp_nsyn_opcode ("fmscd");
11286 do_vfp_nsyn_mul (enum neon_shape rs
)
11289 do_vfp_nsyn_opcode ("fmuls");
11291 do_vfp_nsyn_opcode ("fmuld");
11295 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11297 int is_neg
= (inst
.instruction
& 0x80) != 0;
11298 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11303 do_vfp_nsyn_opcode ("fnegs");
11305 do_vfp_nsyn_opcode ("fabss");
11310 do_vfp_nsyn_opcode ("fnegd");
11312 do_vfp_nsyn_opcode ("fabsd");
11316 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11317 insns belong to Neon, and are handled elsewhere. */
11320 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11322 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11326 do_vfp_nsyn_opcode ("fldmdbs");
11328 do_vfp_nsyn_opcode ("fldmias");
11333 do_vfp_nsyn_opcode ("fstmdbs");
11335 do_vfp_nsyn_opcode ("fstmias");
11340 do_vfp_nsyn_sqrt (void)
11342 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11343 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11346 do_vfp_nsyn_opcode ("fsqrts");
11348 do_vfp_nsyn_opcode ("fsqrtd");
11352 do_vfp_nsyn_div (void)
11354 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11355 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11356 N_F32
| N_F64
| N_KEY
| N_VFP
);
11359 do_vfp_nsyn_opcode ("fdivs");
11361 do_vfp_nsyn_opcode ("fdivd");
11365 do_vfp_nsyn_nmul (void)
11367 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11368 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11369 N_F32
| N_F64
| N_KEY
| N_VFP
);
11373 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11374 do_vfp_sp_dyadic ();
11378 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11379 do_vfp_dp_rd_rn_rm ();
11381 do_vfp_cond_or_thumb ();
11385 do_vfp_nsyn_cmp (void)
11387 if (inst
.operands
[1].isreg
)
11389 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11390 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11394 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11395 do_vfp_sp_monadic ();
11399 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11400 do_vfp_dp_rd_rm ();
11405 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11406 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11408 switch (inst
.instruction
& 0x0fffffff)
11411 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11414 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11422 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11423 do_vfp_sp_compare_z ();
11427 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11431 do_vfp_cond_or_thumb ();
11435 nsyn_insert_sp (void)
11437 inst
.operands
[1] = inst
.operands
[0];
11438 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11439 inst
.operands
[0].reg
= 13;
11440 inst
.operands
[0].isreg
= 1;
11441 inst
.operands
[0].writeback
= 1;
11442 inst
.operands
[0].present
= 1;
11446 do_vfp_nsyn_push (void)
11449 if (inst
.operands
[1].issingle
)
11450 do_vfp_nsyn_opcode ("fstmdbs");
11452 do_vfp_nsyn_opcode ("fstmdbd");
11456 do_vfp_nsyn_pop (void)
11459 if (inst
.operands
[1].issingle
)
11460 do_vfp_nsyn_opcode ("fldmias");
11462 do_vfp_nsyn_opcode ("fldmiad");
11465 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11466 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11469 neon_dp_fixup (unsigned i
)
11473 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11487 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11491 neon_logbits (unsigned x
)
11493 return ffs (x
) - 4;
11496 #define LOW4(R) ((R) & 0xf)
11497 #define HI1(R) (((R) >> 4) & 1)
11499 /* Encode insns with bit pattern:
11501 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11502 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11504 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11505 different meaning for some instruction. */
11508 neon_three_same (int isquad
, int ubit
, int size
)
11510 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11511 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11512 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11513 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11514 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11515 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11516 inst
.instruction
|= (isquad
!= 0) << 6;
11517 inst
.instruction
|= (ubit
!= 0) << 24;
11519 inst
.instruction
|= neon_logbits (size
) << 20;
11521 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11524 /* Encode instructions of the form:
11526 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11527 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11529 Don't write size if SIZE == -1. */
11532 neon_two_same (int qbit
, int ubit
, int size
)
11534 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11535 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11536 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11537 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11538 inst
.instruction
|= (qbit
!= 0) << 6;
11539 inst
.instruction
|= (ubit
!= 0) << 24;
11542 inst
.instruction
|= neon_logbits (size
) << 18;
11544 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11547 /* Neon instruction encoders, in approximate order of appearance. */
11550 do_neon_dyadic_i_su (void)
11552 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11553 struct neon_type_el et
= neon_check_type (3, rs
,
11554 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11555 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11559 do_neon_dyadic_i64_su (void)
11561 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11562 struct neon_type_el et
= neon_check_type (3, rs
,
11563 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11564 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11568 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11571 unsigned size
= et
.size
>> 3;
11572 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11573 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11574 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11575 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11576 inst
.instruction
|= (isquad
!= 0) << 6;
11577 inst
.instruction
|= immbits
<< 16;
11578 inst
.instruction
|= (size
>> 3) << 7;
11579 inst
.instruction
|= (size
& 0x7) << 19;
11581 inst
.instruction
|= (uval
!= 0) << 24;
11583 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11587 do_neon_shl_imm (void)
11589 if (!inst
.operands
[2].isreg
)
11591 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11592 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11593 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11594 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11598 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11599 struct neon_type_el et
= neon_check_type (3, rs
,
11600 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11603 /* VSHL/VQSHL 3-register variants have syntax such as:
11605 whereas other 3-register operations encoded by neon_three_same have
11608 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
11610 tmp
= inst
.operands
[2].reg
;
11611 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11612 inst
.operands
[1].reg
= tmp
;
11613 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11614 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11619 do_neon_qshl_imm (void)
11621 if (!inst
.operands
[2].isreg
)
11623 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11624 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11626 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11627 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11628 inst
.operands
[2].imm
);
11632 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11633 struct neon_type_el et
= neon_check_type (3, rs
,
11634 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11637 /* See note in do_neon_shl_imm. */
11638 tmp
= inst
.operands
[2].reg
;
11639 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11640 inst
.operands
[1].reg
= tmp
;
11641 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11642 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11647 do_neon_rshl (void)
11649 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11650 struct neon_type_el et
= neon_check_type (3, rs
,
11651 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11654 tmp
= inst
.operands
[2].reg
;
11655 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
11656 inst
.operands
[1].reg
= tmp
;
11657 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11661 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11663 /* Handle .I8 pseudo-instructions. */
11666 /* Unfortunately, this will make everything apart from zero out-of-range.
11667 FIXME is this the intended semantics? There doesn't seem much point in
11668 accepting .I8 if so. */
11669 immediate
|= immediate
<< 8;
11675 if (immediate
== (immediate
& 0x000000ff))
11677 *immbits
= immediate
;
11680 else if (immediate
== (immediate
& 0x0000ff00))
11682 *immbits
= immediate
>> 8;
11685 else if (immediate
== (immediate
& 0x00ff0000))
11687 *immbits
= immediate
>> 16;
11690 else if (immediate
== (immediate
& 0xff000000))
11692 *immbits
= immediate
>> 24;
11695 if ((immediate
& 0xffff) != (immediate
>> 16))
11696 goto bad_immediate
;
11697 immediate
&= 0xffff;
11700 if (immediate
== (immediate
& 0x000000ff))
11702 *immbits
= immediate
;
11705 else if (immediate
== (immediate
& 0x0000ff00))
11707 *immbits
= immediate
>> 8;
11712 first_error (_("immediate value out of range"));
11716 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11720 neon_bits_same_in_bytes (unsigned imm
)
11722 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11723 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11724 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11725 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11728 /* For immediate of above form, return 0bABCD. */
11731 neon_squash_bits (unsigned imm
)
11733 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11734 | ((imm
& 0x01000000) >> 21);
11737 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11740 neon_qfloat_bits (unsigned imm
)
11742 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11745 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11746 the instruction. *OP is passed as the initial value of the op field, and
11747 may be set to a different value depending on the constant (i.e.
11748 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11749 MVN). If the immediate looks like a repeated pattern then also
11750 try smaller element sizes. */
11753 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
11754 unsigned *immbits
, int *op
, int size
,
11755 enum neon_el_type type
)
11757 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
11759 if (type
== NT_float
&& !float_p
)
11762 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11764 if (size
!= 32 || *op
== 1)
11766 *immbits
= neon_qfloat_bits (immlo
);
11772 if (neon_bits_same_in_bytes (immhi
)
11773 && neon_bits_same_in_bytes (immlo
))
11777 *immbits
= (neon_squash_bits (immhi
) << 4)
11778 | neon_squash_bits (immlo
);
11783 if (immhi
!= immlo
)
11789 if (immlo
== (immlo
& 0x000000ff))
11794 else if (immlo
== (immlo
& 0x0000ff00))
11796 *immbits
= immlo
>> 8;
11799 else if (immlo
== (immlo
& 0x00ff0000))
11801 *immbits
= immlo
>> 16;
11804 else if (immlo
== (immlo
& 0xff000000))
11806 *immbits
= immlo
>> 24;
11809 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11811 *immbits
= (immlo
>> 8) & 0xff;
11814 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11816 *immbits
= (immlo
>> 16) & 0xff;
11820 if ((immlo
& 0xffff) != (immlo
>> 16))
11827 if (immlo
== (immlo
& 0x000000ff))
11832 else if (immlo
== (immlo
& 0x0000ff00))
11834 *immbits
= immlo
>> 8;
11838 if ((immlo
& 0xff) != (immlo
>> 8))
11843 if (immlo
== (immlo
& 0x000000ff))
11845 /* Don't allow MVN with 8-bit immediate. */
11855 /* Write immediate bits [7:0] to the following locations:
11857 |28/24|23 19|18 16|15 4|3 0|
11858 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11860 This function is used by VMOV/VMVN/VORR/VBIC. */
11863 neon_write_immbits (unsigned immbits
)
11865 inst
.instruction
|= immbits
& 0xf;
11866 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11867 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11870 /* Invert low-order SIZE bits of XHI:XLO. */
11873 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11875 unsigned immlo
= xlo
? *xlo
: 0;
11876 unsigned immhi
= xhi
? *xhi
: 0;
11881 immlo
= (~immlo
) & 0xff;
11885 immlo
= (~immlo
) & 0xffff;
11889 immhi
= (~immhi
) & 0xffffffff;
11890 /* fall through. */
11893 immlo
= (~immlo
) & 0xffffffff;
11908 do_neon_logic (void)
11910 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11912 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11913 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11914 /* U bit and size field were set as part of the bitmask. */
11915 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11916 neon_three_same (neon_quad (rs
), 0, -1);
11920 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11921 struct neon_type_el et
= neon_check_type (2, rs
,
11922 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11923 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11927 if (et
.type
== NT_invtype
)
11930 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11932 immbits
= inst
.operands
[1].imm
;
11935 /* .i64 is a pseudo-op, so the immediate must be a repeating
11937 if (immbits
!= (inst
.operands
[1].regisimm
?
11938 inst
.operands
[1].reg
: 0))
11940 /* Set immbits to an invalid constant. */
11941 immbits
= 0xdeadbeef;
11948 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11952 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11956 /* Pseudo-instruction for VBIC. */
11957 neon_invert_size (&immbits
, 0, et
.size
);
11958 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11962 /* Pseudo-instruction for VORR. */
11963 neon_invert_size (&immbits
, 0, et
.size
);
11964 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11974 inst
.instruction
|= neon_quad (rs
) << 6;
11975 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11976 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11977 inst
.instruction
|= cmode
<< 8;
11978 neon_write_immbits (immbits
);
11980 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11985 do_neon_bitfield (void)
11987 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11988 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11989 neon_three_same (neon_quad (rs
), 0, -1);
11993 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
11996 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11997 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
11999 if (et
.type
== NT_float
)
12001 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12002 neon_three_same (neon_quad (rs
), 0, -1);
12006 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12007 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12012 do_neon_dyadic_if_su (void)
12014 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12018 do_neon_dyadic_if_su_d (void)
12020 /* This version only allow D registers, but that constraint is enforced during
12021 operand parsing so we don't need to do anything extra here. */
12022 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12026 do_neon_dyadic_if_i_d (void)
12028 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12029 affected if we specify unsigned args. */
12030 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12033 enum vfp_or_neon_is_neon_bits
12036 NEON_CHECK_ARCH
= 2
12039 /* Call this function if an instruction which may have belonged to the VFP or
12040 Neon instruction sets, but turned out to be a Neon instruction (due to the
12041 operand types involved, etc.). We have to check and/or fix-up a couple of
12044 - Make sure the user hasn't attempted to make a Neon instruction
12046 - Alter the value in the condition code field if necessary.
12047 - Make sure that the arch supports Neon instructions.
12049 Which of these operations take place depends on bits from enum
12050 vfp_or_neon_is_neon_bits.
12052 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12053 current instruction's condition is COND_ALWAYS, the condition field is
12054 changed to inst.uncond_value. This is necessary because instructions shared
12055 between VFP and Neon may be conditional for the VFP variants only, and the
12056 unconditional Neon version must have, e.g., 0xF in the condition field. */
12059 vfp_or_neon_is_neon (unsigned check
)
12061 /* Conditions are always legal in Thumb mode (IT blocks). */
12062 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12064 if (inst
.cond
!= COND_ALWAYS
)
12066 first_error (_(BAD_COND
));
12069 if (inst
.uncond_value
!= -1)
12070 inst
.instruction
|= inst
.uncond_value
<< 28;
12073 if ((check
& NEON_CHECK_ARCH
)
12074 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12076 first_error (_(BAD_FPU
));
12084 do_neon_addsub_if_i (void)
12086 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12089 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12092 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12093 affected if we specify unsigned args. */
12094 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12097 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12099 V<op> A,B (A is operand 0, B is operand 2)
12104 so handle that case specially. */
12107 neon_exchange_operands (void)
12109 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12110 if (inst
.operands
[1].present
)
12112 /* Swap operands[1] and operands[2]. */
12113 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12114 inst
.operands
[1] = inst
.operands
[2];
12115 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12119 inst
.operands
[1] = inst
.operands
[2];
12120 inst
.operands
[2] = inst
.operands
[0];
12125 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12127 if (inst
.operands
[2].isreg
)
12130 neon_exchange_operands ();
12131 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12135 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12136 struct neon_type_el et
= neon_check_type (2, rs
,
12137 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12139 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12140 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12141 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12142 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12143 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12144 inst
.instruction
|= neon_quad (rs
) << 6;
12145 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12146 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12148 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12155 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12159 do_neon_cmp_inv (void)
12161 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12167 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12170 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12171 scalars, which are encoded in 5 bits, M : Rm.
12172 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12173 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12177 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12179 unsigned regno
= NEON_SCALAR_REG (scalar
);
12180 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12185 if (regno
> 7 || elno
> 3)
12187 return regno
| (elno
<< 3);
12190 if (regno
> 15 || elno
> 1)
12192 return regno
| (elno
<< 4);
12196 first_error (_("scalar out of range for multiply instruction"));
12202 /* Encode multiply / multiply-accumulate scalar instructions. */
12205 neon_mul_mac (struct neon_type_el et
, int ubit
)
12209 /* Give a more helpful error message if we have an invalid type. */
12210 if (et
.type
== NT_invtype
)
12213 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12214 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12215 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12216 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12217 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12218 inst
.instruction
|= LOW4 (scalar
);
12219 inst
.instruction
|= HI1 (scalar
) << 5;
12220 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12221 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12222 inst
.instruction
|= (ubit
!= 0) << 24;
12224 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12228 do_neon_mac_maybe_scalar (void)
12230 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12233 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12236 if (inst
.operands
[2].isscalar
)
12238 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12239 struct neon_type_el et
= neon_check_type (3, rs
,
12240 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12241 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12242 neon_mul_mac (et
, neon_quad (rs
));
12246 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12247 affected if we specify unsigned args. */
12248 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12255 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12256 struct neon_type_el et
= neon_check_type (3, rs
,
12257 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12258 neon_three_same (neon_quad (rs
), 0, et
.size
);
12261 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12262 same types as the MAC equivalents. The polynomial type for this instruction
12263 is encoded the same as the integer type. */
12268 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12271 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12274 if (inst
.operands
[2].isscalar
)
12275 do_neon_mac_maybe_scalar ();
12277 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12281 do_neon_qdmulh (void)
12283 if (inst
.operands
[2].isscalar
)
12285 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12286 struct neon_type_el et
= neon_check_type (3, rs
,
12287 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12288 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12289 neon_mul_mac (et
, neon_quad (rs
));
12293 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12294 struct neon_type_el et
= neon_check_type (3, rs
,
12295 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12296 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12297 /* The U bit (rounding) comes from bit mask. */
12298 neon_three_same (neon_quad (rs
), 0, et
.size
);
12303 do_neon_fcmp_absolute (void)
12305 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12306 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12307 /* Size field comes from bit mask. */
12308 neon_three_same (neon_quad (rs
), 1, -1);
12312 do_neon_fcmp_absolute_inv (void)
12314 neon_exchange_operands ();
12315 do_neon_fcmp_absolute ();
12319 do_neon_step (void)
12321 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12322 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12323 neon_three_same (neon_quad (rs
), 0, -1);
12327 do_neon_abs_neg (void)
12329 enum neon_shape rs
;
12330 struct neon_type_el et
;
12332 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12335 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12338 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12339 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12341 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12342 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12343 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12344 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12345 inst
.instruction
|= neon_quad (rs
) << 6;
12346 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12347 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12349 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12355 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12356 struct neon_type_el et
= neon_check_type (2, rs
,
12357 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12358 int imm
= inst
.operands
[2].imm
;
12359 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12360 _("immediate out of range for insert"));
12361 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12367 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12368 struct neon_type_el et
= neon_check_type (2, rs
,
12369 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12370 int imm
= inst
.operands
[2].imm
;
12371 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12372 _("immediate out of range for insert"));
12373 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12377 do_neon_qshlu_imm (void)
12379 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12380 struct neon_type_el et
= neon_check_type (2, rs
,
12381 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12382 int imm
= inst
.operands
[2].imm
;
12383 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12384 _("immediate out of range for shift"));
12385 /* Only encodes the 'U present' variant of the instruction.
12386 In this case, signed types have OP (bit 8) set to 0.
12387 Unsigned types have OP set to 1. */
12388 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12389 /* The rest of the bits are the same as other immediate shifts. */
12390 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12394 do_neon_qmovn (void)
12396 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12397 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12398 /* Saturating move where operands can be signed or unsigned, and the
12399 destination has the same signedness. */
12400 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12401 if (et
.type
== NT_unsigned
)
12402 inst
.instruction
|= 0xc0;
12404 inst
.instruction
|= 0x80;
12405 neon_two_same (0, 1, et
.size
/ 2);
12409 do_neon_qmovun (void)
12411 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12412 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12413 /* Saturating move with unsigned results. Operands must be signed. */
12414 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12415 neon_two_same (0, 1, et
.size
/ 2);
12419 do_neon_rshift_sat_narrow (void)
12421 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12422 or unsigned. If operands are unsigned, results must also be unsigned. */
12423 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12424 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12425 int imm
= inst
.operands
[2].imm
;
12426 /* This gets the bounds check, size encoding and immediate bits calculation
12430 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12431 VQMOVN.I<size> <Dd>, <Qm>. */
12434 inst
.operands
[2].present
= 0;
12435 inst
.instruction
= N_MNEM_vqmovn
;
12440 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12441 _("immediate out of range"));
12442 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12446 do_neon_rshift_sat_narrow_u (void)
12448 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12449 or unsigned. If operands are unsigned, results must also be unsigned. */
12450 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12451 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12452 int imm
= inst
.operands
[2].imm
;
12453 /* This gets the bounds check, size encoding and immediate bits calculation
12457 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12458 VQMOVUN.I<size> <Dd>, <Qm>. */
12461 inst
.operands
[2].present
= 0;
12462 inst
.instruction
= N_MNEM_vqmovun
;
12467 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12468 _("immediate out of range"));
12469 /* FIXME: The manual is kind of unclear about what value U should have in
12470 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12472 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12476 do_neon_movn (void)
12478 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12479 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12480 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12481 neon_two_same (0, 1, et
.size
/ 2);
12485 do_neon_rshift_narrow (void)
12487 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12488 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12489 int imm
= inst
.operands
[2].imm
;
12490 /* This gets the bounds check, size encoding and immediate bits calculation
12494 /* If immediate is zero then we are a pseudo-instruction for
12495 VMOVN.I<size> <Dd>, <Qm> */
12498 inst
.operands
[2].present
= 0;
12499 inst
.instruction
= N_MNEM_vmovn
;
12504 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12505 _("immediate out of range for narrowing operation"));
12506 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12510 do_neon_shll (void)
12512 /* FIXME: Type checking when lengthening. */
12513 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12514 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12515 unsigned imm
= inst
.operands
[2].imm
;
12517 if (imm
== et
.size
)
12519 /* Maximum shift variant. */
12520 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12521 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12522 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12523 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12524 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12525 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12527 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12531 /* A more-specific type check for non-max versions. */
12532 et
= neon_check_type (2, NS_QDI
,
12533 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12534 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12535 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12539 /* Check the various types for the VCVT instruction, and return which version
12540 the current instruction is. */
12543 neon_cvt_flavour (enum neon_shape rs
)
12545 #define CVT_VAR(C,X,Y) \
12546 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12547 if (et.type != NT_invtype) \
12549 inst.error = NULL; \
12552 struct neon_type_el et
;
12553 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12554 || rs
== NS_FF
) ? N_VFP
: 0;
12555 /* The instruction versions which take an immediate take one register
12556 argument, which is extended to the width of the full register. Thus the
12557 "source" and "destination" registers must have the same width. Hack that
12558 here by making the size equal to the key (wider, in this case) operand. */
12559 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12561 CVT_VAR (0, N_S32
, N_F32
);
12562 CVT_VAR (1, N_U32
, N_F32
);
12563 CVT_VAR (2, N_F32
, N_S32
);
12564 CVT_VAR (3, N_F32
, N_U32
);
12568 /* VFP instructions. */
12569 CVT_VAR (4, N_F32
, N_F64
);
12570 CVT_VAR (5, N_F64
, N_F32
);
12571 CVT_VAR (6, N_S32
, N_F64
| key
);
12572 CVT_VAR (7, N_U32
, N_F64
| key
);
12573 CVT_VAR (8, N_F64
| key
, N_S32
);
12574 CVT_VAR (9, N_F64
| key
, N_U32
);
12575 /* VFP instructions with bitshift. */
12576 CVT_VAR (10, N_F32
| key
, N_S16
);
12577 CVT_VAR (11, N_F32
| key
, N_U16
);
12578 CVT_VAR (12, N_F64
| key
, N_S16
);
12579 CVT_VAR (13, N_F64
| key
, N_U16
);
12580 CVT_VAR (14, N_S16
, N_F32
| key
);
12581 CVT_VAR (15, N_U16
, N_F32
| key
);
12582 CVT_VAR (16, N_S16
, N_F64
| key
);
12583 CVT_VAR (17, N_U16
, N_F64
| key
);
12589 /* Neon-syntax VFP conversions. */
12592 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12594 const char *opname
= 0;
12596 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12598 /* Conversions with immediate bitshift. */
12599 const char *enc
[] =
12621 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12623 opname
= enc
[flavour
];
12624 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12625 _("operands 0 and 1 must be the same register"));
12626 inst
.operands
[1] = inst
.operands
[2];
12627 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12632 /* Conversions without bitshift. */
12633 const char *enc
[] =
12647 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12648 opname
= enc
[flavour
];
12652 do_vfp_nsyn_opcode (opname
);
12656 do_vfp_nsyn_cvtz (void)
12658 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12659 int flavour
= neon_cvt_flavour (rs
);
12660 const char *enc
[] =
12672 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12673 do_vfp_nsyn_opcode (enc
[flavour
]);
12679 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12680 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12681 int flavour
= neon_cvt_flavour (rs
);
12683 /* VFP rather than Neon conversions. */
12686 do_vfp_nsyn_cvt (rs
, flavour
);
12695 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12698 /* Fixed-point conversion with #0 immediate is encoded as an
12699 integer conversion. */
12700 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12702 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12703 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12704 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12706 inst
.instruction
|= enctab
[flavour
];
12707 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12708 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12709 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12710 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12711 inst
.instruction
|= neon_quad (rs
) << 6;
12712 inst
.instruction
|= 1 << 21;
12713 inst
.instruction
|= immbits
<< 16;
12715 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12723 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12725 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12727 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12731 inst
.instruction
|= enctab
[flavour
];
12733 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12734 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12735 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12736 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12737 inst
.instruction
|= neon_quad (rs
) << 6;
12738 inst
.instruction
|= 2 << 18;
12740 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12745 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12746 do_vfp_nsyn_cvt (rs
, flavour
);
12751 neon_move_immediate (void)
12753 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12754 struct neon_type_el et
= neon_check_type (2, rs
,
12755 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12756 unsigned immlo
, immhi
= 0, immbits
;
12757 int op
, cmode
, float_p
;
12759 constraint (et
.type
== NT_invtype
,
12760 _("operand size must be specified for immediate VMOV"));
12762 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12763 op
= (inst
.instruction
& (1 << 5)) != 0;
12765 immlo
= inst
.operands
[1].imm
;
12766 if (inst
.operands
[1].regisimm
)
12767 immhi
= inst
.operands
[1].reg
;
12769 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12770 _("immediate has bits set outside the operand size"));
12772 float_p
= inst
.operands
[1].immisfloat
;
12774 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
12775 et
.size
, et
.type
)) == FAIL
)
12777 /* Invert relevant bits only. */
12778 neon_invert_size (&immlo
, &immhi
, et
.size
);
12779 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12780 with one or the other; those cases are caught by
12781 neon_cmode_for_move_imm. */
12783 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
12784 &op
, et
.size
, et
.type
)) == FAIL
)
12786 first_error (_("immediate out of range"));
12791 inst
.instruction
&= ~(1 << 5);
12792 inst
.instruction
|= op
<< 5;
12794 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12795 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12796 inst
.instruction
|= neon_quad (rs
) << 6;
12797 inst
.instruction
|= cmode
<< 8;
12799 neon_write_immbits (immbits
);
12805 if (inst
.operands
[1].isreg
)
12807 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12809 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12810 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12811 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12812 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12813 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12814 inst
.instruction
|= neon_quad (rs
) << 6;
12818 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12819 neon_move_immediate ();
12822 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12825 /* Encode instructions of form:
12827 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12828 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
12831 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12833 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12834 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12835 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12836 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12837 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12838 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12839 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12840 inst
.instruction
|= neon_logbits (size
) << 20;
12842 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12846 do_neon_dyadic_long (void)
12848 /* FIXME: Type checking for lengthening op. */
12849 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12850 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12851 neon_mixed_length (et
, et
.size
);
12855 do_neon_abal (void)
12857 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12858 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12859 neon_mixed_length (et
, et
.size
);
12863 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12865 if (inst
.operands
[2].isscalar
)
12867 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12868 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12869 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12870 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12874 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12875 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12876 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12877 neon_mixed_length (et
, et
.size
);
12882 do_neon_mac_maybe_scalar_long (void)
12884 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12888 do_neon_dyadic_wide (void)
12890 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12891 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12892 neon_mixed_length (et
, et
.size
);
12896 do_neon_dyadic_narrow (void)
12898 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12899 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12900 /* Operand sign is unimportant, and the U bit is part of the opcode,
12901 so force the operand type to integer. */
12902 et
.type
= NT_integer
;
12903 neon_mixed_length (et
, et
.size
/ 2);
12907 do_neon_mul_sat_scalar_long (void)
12909 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12913 do_neon_vmull (void)
12915 if (inst
.operands
[2].isscalar
)
12916 do_neon_mac_maybe_scalar_long ();
12919 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12920 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12921 if (et
.type
== NT_poly
)
12922 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12924 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12925 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12926 zero. Should be OK as-is. */
12927 neon_mixed_length (et
, et
.size
);
12934 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12935 struct neon_type_el et
= neon_check_type (3, rs
,
12936 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12937 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12938 constraint (imm
>= (neon_quad (rs
) ? 16 : 8), _("shift out of range"));
12939 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12940 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12941 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12942 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12943 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12944 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12945 inst
.instruction
|= neon_quad (rs
) << 6;
12946 inst
.instruction
|= imm
<< 8;
12948 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12954 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12955 struct neon_type_el et
= neon_check_type (2, rs
,
12956 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12957 unsigned op
= (inst
.instruction
>> 7) & 3;
12958 /* N (width of reversed regions) is encoded as part of the bitmask. We
12959 extract it here to check the elements to be reversed are smaller.
12960 Otherwise we'd get a reserved instruction. */
12961 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12962 assert (elsize
!= 0);
12963 constraint (et
.size
>= elsize
,
12964 _("elements must be smaller than reversal region"));
12965 neon_two_same (neon_quad (rs
), 1, et
.size
);
12971 if (inst
.operands
[1].isscalar
)
12973 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12974 struct neon_type_el et
= neon_check_type (2, rs
,
12975 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12976 unsigned sizebits
= et
.size
>> 3;
12977 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12978 int logsize
= neon_logbits (et
.size
);
12979 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12981 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12984 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12985 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12986 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12987 inst
.instruction
|= LOW4 (dm
);
12988 inst
.instruction
|= HI1 (dm
) << 5;
12989 inst
.instruction
|= neon_quad (rs
) << 6;
12990 inst
.instruction
|= x
<< 17;
12991 inst
.instruction
|= sizebits
<< 16;
12993 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12997 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
12998 struct neon_type_el et
= neon_check_type (2, rs
,
12999 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13000 /* Duplicate ARM register to lanes of vector. */
13001 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13004 case 8: inst
.instruction
|= 0x400000; break;
13005 case 16: inst
.instruction
|= 0x000020; break;
13006 case 32: inst
.instruction
|= 0x000000; break;
13009 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13010 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13011 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13012 inst
.instruction
|= neon_quad (rs
) << 21;
13013 /* The encoding for this instruction is identical for the ARM and Thumb
13014 variants, except for the condition field. */
13015 do_vfp_cond_or_thumb ();
13019 /* VMOV has particularly many variations. It can be one of:
13020 0. VMOV<c><q> <Qd>, <Qm>
13021 1. VMOV<c><q> <Dd>, <Dm>
13022 (Register operations, which are VORR with Rm = Rn.)
13023 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13024 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13026 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13027 (ARM register to scalar.)
13028 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13029 (Two ARM registers to vector.)
13030 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13031 (Scalar to ARM register.)
13032 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13033 (Vector to two ARM registers.)
13034 8. VMOV.F32 <Sd>, <Sm>
13035 9. VMOV.F64 <Dd>, <Dm>
13036 (VFP register moves.)
13037 10. VMOV.F32 <Sd>, #imm
13038 11. VMOV.F64 <Dd>, #imm
13039 (VFP float immediate load.)
13040 12. VMOV <Rd>, <Sm>
13041 (VFP single to ARM reg.)
13042 13. VMOV <Sd>, <Rm>
13043 (ARM reg to VFP single.)
13044 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13045 (Two ARM regs to two VFP singles.)
13046 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13047 (Two VFP singles to two ARM regs.)
13049 These cases can be disambiguated using neon_select_shape, except cases 1/9
13050 and 3/11 which depend on the operand type too.
13052 All the encoded bits are hardcoded by this function.
13054 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13055 Cases 5, 7 may be used with VFPv2 and above.
13057 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13058 can specify a type where it doesn't make sense to, and is ignored). */
13063 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13064 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13066 struct neon_type_el et
;
13067 const char *ldconst
= 0;
13071 case NS_DD
: /* case 1/9. */
13072 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13073 /* It is not an error here if no type is given. */
13075 if (et
.type
== NT_float
&& et
.size
== 64)
13077 do_vfp_nsyn_opcode ("fcpyd");
13080 /* fall through. */
13082 case NS_QQ
: /* case 0/1. */
13084 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13086 /* The architecture manual I have doesn't explicitly state which
13087 value the U bit should have for register->register moves, but
13088 the equivalent VORR instruction has U = 0, so do that. */
13089 inst
.instruction
= 0x0200110;
13090 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13091 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13092 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13093 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13094 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13095 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13096 inst
.instruction
|= neon_quad (rs
) << 6;
13098 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13102 case NS_DI
: /* case 3/11. */
13103 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13105 if (et
.type
== NT_float
&& et
.size
== 64)
13107 /* case 11 (fconstd). */
13108 ldconst
= "fconstd";
13109 goto encode_fconstd
;
13111 /* fall through. */
13113 case NS_QI
: /* case 2/3. */
13114 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13116 inst
.instruction
= 0x0800010;
13117 neon_move_immediate ();
13118 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13121 case NS_SR
: /* case 4. */
13123 unsigned bcdebits
= 0;
13124 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13125 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13126 int logsize
= neon_logbits (et
.size
);
13127 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13128 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13130 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13132 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13133 && et
.size
!= 32, _(BAD_FPU
));
13134 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13135 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13139 case 8: bcdebits
= 0x8; break;
13140 case 16: bcdebits
= 0x1; break;
13141 case 32: bcdebits
= 0x0; break;
13145 bcdebits
|= x
<< logsize
;
13147 inst
.instruction
= 0xe000b10;
13148 do_vfp_cond_or_thumb ();
13149 inst
.instruction
|= LOW4 (dn
) << 16;
13150 inst
.instruction
|= HI1 (dn
) << 7;
13151 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13152 inst
.instruction
|= (bcdebits
& 3) << 5;
13153 inst
.instruction
|= (bcdebits
>> 2) << 21;
13157 case NS_DRR
: /* case 5 (fmdrr). */
13158 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13161 inst
.instruction
= 0xc400b10;
13162 do_vfp_cond_or_thumb ();
13163 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13164 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13165 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13166 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13169 case NS_RS
: /* case 6. */
13171 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13172 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13173 unsigned logsize
= neon_logbits (et
.size
);
13174 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13175 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13176 unsigned abcdebits
= 0;
13178 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13180 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13181 && et
.size
!= 32, _(BAD_FPU
));
13182 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13183 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13187 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13188 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13189 case 32: abcdebits
= 0x00; break;
13193 abcdebits
|= x
<< logsize
;
13194 inst
.instruction
= 0xe100b10;
13195 do_vfp_cond_or_thumb ();
13196 inst
.instruction
|= LOW4 (dn
) << 16;
13197 inst
.instruction
|= HI1 (dn
) << 7;
13198 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13199 inst
.instruction
|= (abcdebits
& 3) << 5;
13200 inst
.instruction
|= (abcdebits
>> 2) << 21;
13204 case NS_RRD
: /* case 7 (fmrrd). */
13205 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13208 inst
.instruction
= 0xc500b10;
13209 do_vfp_cond_or_thumb ();
13210 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13211 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13212 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13213 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13216 case NS_FF
: /* case 8 (fcpys). */
13217 do_vfp_nsyn_opcode ("fcpys");
13220 case NS_FI
: /* case 10 (fconsts). */
13221 ldconst
= "fconsts";
13223 if (is_quarter_float (inst
.operands
[1].imm
))
13225 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13226 do_vfp_nsyn_opcode (ldconst
);
13229 first_error (_("immediate out of range"));
13232 case NS_RF
: /* case 12 (fmrs). */
13233 do_vfp_nsyn_opcode ("fmrs");
13236 case NS_FR
: /* case 13 (fmsr). */
13237 do_vfp_nsyn_opcode ("fmsr");
13240 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13241 (one of which is a list), but we have parsed four. Do some fiddling to
13242 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13244 case NS_RRFF
: /* case 14 (fmrrs). */
13245 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13246 _("VFP registers must be adjacent"));
13247 inst
.operands
[2].imm
= 2;
13248 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13249 do_vfp_nsyn_opcode ("fmrrs");
13252 case NS_FFRR
: /* case 15 (fmsrr). */
13253 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13254 _("VFP registers must be adjacent"));
13255 inst
.operands
[1] = inst
.operands
[2];
13256 inst
.operands
[2] = inst
.operands
[3];
13257 inst
.operands
[0].imm
= 2;
13258 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13259 do_vfp_nsyn_opcode ("fmsrr");
13268 do_neon_rshift_round_imm (void)
13270 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13271 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13272 int imm
= inst
.operands
[2].imm
;
13274 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13277 inst
.operands
[2].present
= 0;
13282 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13283 _("immediate out of range for shift"));
13284 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13289 do_neon_movl (void)
13291 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13292 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13293 unsigned sizebits
= et
.size
>> 3;
13294 inst
.instruction
|= sizebits
<< 19;
13295 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13301 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13302 struct neon_type_el et
= neon_check_type (2, rs
,
13303 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13304 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13305 neon_two_same (neon_quad (rs
), 1, et
.size
);
13309 do_neon_zip_uzp (void)
13311 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13312 struct neon_type_el et
= neon_check_type (2, rs
,
13313 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13314 if (rs
== NS_DD
&& et
.size
== 32)
13316 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13317 inst
.instruction
= N_MNEM_vtrn
;
13321 neon_two_same (neon_quad (rs
), 1, et
.size
);
13325 do_neon_sat_abs_neg (void)
13327 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13328 struct neon_type_el et
= neon_check_type (2, rs
,
13329 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13330 neon_two_same (neon_quad (rs
), 1, et
.size
);
13334 do_neon_pair_long (void)
13336 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13337 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13338 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13339 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13340 neon_two_same (neon_quad (rs
), 1, et
.size
);
13344 do_neon_recip_est (void)
13346 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13347 struct neon_type_el et
= neon_check_type (2, rs
,
13348 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13349 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13350 neon_two_same (neon_quad (rs
), 1, et
.size
);
13356 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13357 struct neon_type_el et
= neon_check_type (2, rs
,
13358 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13359 neon_two_same (neon_quad (rs
), 1, et
.size
);
13365 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13366 struct neon_type_el et
= neon_check_type (2, rs
,
13367 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13368 neon_two_same (neon_quad (rs
), 1, et
.size
);
13374 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13375 struct neon_type_el et
= neon_check_type (2, rs
,
13376 N_EQK
| N_INT
, N_8
| N_KEY
);
13377 neon_two_same (neon_quad (rs
), 1, et
.size
);
13383 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13384 neon_two_same (neon_quad (rs
), 1, -1);
13388 do_neon_tbl_tbx (void)
13390 unsigned listlenbits
;
13391 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13393 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13395 first_error (_("bad list length for table lookup"));
13399 listlenbits
= inst
.operands
[1].imm
- 1;
13400 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13401 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13402 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13403 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13404 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13405 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13406 inst
.instruction
|= listlenbits
<< 8;
13408 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13412 do_neon_ldm_stm (void)
13414 /* P, U and L bits are part of bitmask. */
13415 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13416 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13418 if (inst
.operands
[1].issingle
)
13420 do_vfp_nsyn_ldm_stm (is_dbmode
);
13424 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13425 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13427 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13428 _("register list must contain at least 1 and at most 16 "
13431 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13432 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13433 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13434 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13436 inst
.instruction
|= offsetbits
;
13438 do_vfp_cond_or_thumb ();
13442 do_neon_ldr_str (void)
13444 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13446 if (inst
.operands
[0].issingle
)
13449 do_vfp_nsyn_opcode ("flds");
13451 do_vfp_nsyn_opcode ("fsts");
13456 do_vfp_nsyn_opcode ("fldd");
13458 do_vfp_nsyn_opcode ("fstd");
13462 /* "interleave" version also handles non-interleaving register VLD1/VST1
13466 do_neon_ld_st_interleave (void)
13468 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13469 N_8
| N_16
| N_32
| N_64
);
13470 unsigned alignbits
= 0;
13472 /* The bits in this table go:
13473 0: register stride of one (0) or two (1)
13474 1,2: register list length, minus one (1, 2, 3, 4).
13475 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13476 We use -1 for invalid entries. */
13477 const int typetable
[] =
13479 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13480 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13481 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13482 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13486 if (et
.type
== NT_invtype
)
13489 if (inst
.operands
[1].immisalign
)
13490 switch (inst
.operands
[1].imm
>> 8)
13492 case 64: alignbits
= 1; break;
13494 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13495 goto bad_alignment
;
13499 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13500 goto bad_alignment
;
13505 first_error (_("bad alignment"));
13509 inst
.instruction
|= alignbits
<< 4;
13510 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13512 /* Bits [4:6] of the immediate in a list specifier encode register stride
13513 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13514 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13515 up the right value for "type" in a table based on this value and the given
13516 list style, then stick it back. */
13517 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13518 | (((inst
.instruction
>> 8) & 3) << 3);
13520 typebits
= typetable
[idx
];
13522 constraint (typebits
== -1, _("bad list type for instruction"));
13524 inst
.instruction
&= ~0xf00;
13525 inst
.instruction
|= typebits
<< 8;
13528 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13529 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13530 otherwise. The variable arguments are a list of pairs of legal (size, align)
13531 values, terminated with -1. */
13534 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13537 int result
= FAIL
, thissize
, thisalign
;
13539 if (!inst
.operands
[1].immisalign
)
13545 va_start (ap
, do_align
);
13549 thissize
= va_arg (ap
, int);
13550 if (thissize
== -1)
13552 thisalign
= va_arg (ap
, int);
13554 if (size
== thissize
&& align
== thisalign
)
13557 while (result
!= SUCCESS
);
13561 if (result
== SUCCESS
)
13564 first_error (_("unsupported alignment for instruction"));
13570 do_neon_ld_st_lane (void)
13572 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13573 int align_good
, do_align
= 0;
13574 int logsize
= neon_logbits (et
.size
);
13575 int align
= inst
.operands
[1].imm
>> 8;
13576 int n
= (inst
.instruction
>> 8) & 3;
13577 int max_el
= 64 / et
.size
;
13579 if (et
.type
== NT_invtype
)
13582 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13583 _("bad list length"));
13584 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13585 _("scalar index out of range"));
13586 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13588 _("stride of 2 unavailable when element size is 8"));
13592 case 0: /* VLD1 / VST1. */
13593 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13595 if (align_good
== FAIL
)
13599 unsigned alignbits
= 0;
13602 case 16: alignbits
= 0x1; break;
13603 case 32: alignbits
= 0x3; break;
13606 inst
.instruction
|= alignbits
<< 4;
13610 case 1: /* VLD2 / VST2. */
13611 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13613 if (align_good
== FAIL
)
13616 inst
.instruction
|= 1 << 4;
13619 case 2: /* VLD3 / VST3. */
13620 constraint (inst
.operands
[1].immisalign
,
13621 _("can't use alignment with this instruction"));
13624 case 3: /* VLD4 / VST4. */
13625 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13626 16, 64, 32, 64, 32, 128, -1);
13627 if (align_good
== FAIL
)
13631 unsigned alignbits
= 0;
13634 case 8: alignbits
= 0x1; break;
13635 case 16: alignbits
= 0x1; break;
13636 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13639 inst
.instruction
|= alignbits
<< 4;
13646 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13647 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13648 inst
.instruction
|= 1 << (4 + logsize
);
13650 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13651 inst
.instruction
|= logsize
<< 10;
13654 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13657 do_neon_ld_dup (void)
13659 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13660 int align_good
, do_align
= 0;
13662 if (et
.type
== NT_invtype
)
13665 switch ((inst
.instruction
>> 8) & 3)
13667 case 0: /* VLD1. */
13668 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13669 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13670 &do_align
, 16, 16, 32, 32, -1);
13671 if (align_good
== FAIL
)
13673 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13676 case 2: inst
.instruction
|= 1 << 5; break;
13677 default: first_error (_("bad list length")); return;
13679 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13682 case 1: /* VLD2. */
13683 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13684 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13685 if (align_good
== FAIL
)
13687 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13688 _("bad list length"));
13689 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13690 inst
.instruction
|= 1 << 5;
13691 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13694 case 2: /* VLD3. */
13695 constraint (inst
.operands
[1].immisalign
,
13696 _("can't use alignment with this instruction"));
13697 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13698 _("bad list length"));
13699 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13700 inst
.instruction
|= 1 << 5;
13701 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13704 case 3: /* VLD4. */
13706 int align
= inst
.operands
[1].imm
>> 8;
13707 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13708 16, 64, 32, 64, 32, 128, -1);
13709 if (align_good
== FAIL
)
13711 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13712 _("bad list length"));
13713 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13714 inst
.instruction
|= 1 << 5;
13715 if (et
.size
== 32 && align
== 128)
13716 inst
.instruction
|= 0x3 << 6;
13718 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13725 inst
.instruction
|= do_align
<< 4;
13728 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13729 apart from bits [11:4]. */
13732 do_neon_ldx_stx (void)
13734 switch (NEON_LANE (inst
.operands
[0].imm
))
13736 case NEON_INTERLEAVE_LANES
:
13737 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13738 do_neon_ld_st_interleave ();
13741 case NEON_ALL_LANES
:
13742 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13747 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13748 do_neon_ld_st_lane ();
13751 /* L bit comes from bit mask. */
13752 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13753 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13754 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13756 if (inst
.operands
[1].postind
)
13758 int postreg
= inst
.operands
[1].imm
& 0xf;
13759 constraint (!inst
.operands
[1].immisreg
,
13760 _("post-index must be a register"));
13761 constraint (postreg
== 0xd || postreg
== 0xf,
13762 _("bad register for post-index"));
13763 inst
.instruction
|= postreg
;
13765 else if (inst
.operands
[1].writeback
)
13767 inst
.instruction
|= 0xd;
13770 inst
.instruction
|= 0xf;
13773 inst
.instruction
|= 0xf9000000;
13775 inst
.instruction
|= 0xf4000000;
13778 /* Overall per-instruction processing. */
13780 /* We need to be able to fix up arbitrary expressions in some statements.
13781 This is so that we can handle symbols that are an arbitrary distance from
13782 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13783 which returns part of an address in a form which will be valid for
13784 a data instruction. We do this by pushing the expression into a symbol
13785 in the expr_section, and creating a fix for that. */
13788 fix_new_arm (fragS
* frag
,
13803 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13807 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13812 /* Mark whether the fix is to a THUMB instruction, or an ARM
13814 new_fix
->tc_fix_data
= thumb_mode
;
13817 /* Create a frg for an instruction requiring relaxation. */
13819 output_relax_insn (void)
13825 /* The size of the instruction is unknown, so tie the debug info to the
13826 start of the instruction. */
13827 dwarf2_emit_insn (0);
13829 switch (inst
.reloc
.exp
.X_op
)
13832 sym
= inst
.reloc
.exp
.X_add_symbol
;
13833 offset
= inst
.reloc
.exp
.X_add_number
;
13837 offset
= inst
.reloc
.exp
.X_add_number
;
13840 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13844 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13845 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13846 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13849 /* Write a 32-bit thumb instruction to buf. */
13851 put_thumb32_insn (char * buf
, unsigned long insn
)
13853 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13854 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13858 output_inst (const char * str
)
13864 as_bad ("%s -- `%s'", inst
.error
, str
);
13869 output_relax_insn ();
13872 if (inst
.size
== 0)
13875 to
= frag_more (inst
.size
);
13877 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13879 assert (inst
.size
== (2 * THUMB_SIZE
));
13880 put_thumb32_insn (to
, inst
.instruction
);
13882 else if (inst
.size
> INSN_SIZE
)
13884 assert (inst
.size
== (2 * INSN_SIZE
));
13885 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13886 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13889 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13891 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13892 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13893 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13896 dwarf2_emit_insn (inst
.size
);
13899 /* Tag values used in struct asm_opcode's tag field. */
13902 OT_unconditional
, /* Instruction cannot be conditionalized.
13903 The ARM condition field is still 0xE. */
13904 OT_unconditionalF
, /* Instruction cannot be conditionalized
13905 and carries 0xF in its ARM condition field. */
13906 OT_csuffix
, /* Instruction takes a conditional suffix. */
13907 OT_csuffixF
, /* Some forms of the instruction take a conditional
13908 suffix, others place 0xF where the condition field
13910 OT_cinfix3
, /* Instruction takes a conditional infix,
13911 beginning at character index 3. (In
13912 unified mode, it becomes a suffix.) */
13913 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13914 tsts, cmps, cmns, and teqs. */
13915 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13916 character index 3, even in unified mode. Used for
13917 legacy instructions where suffix and infix forms
13918 may be ambiguous. */
13919 OT_csuf_or_in3
, /* Instruction takes either a conditional
13920 suffix or an infix at character index 3. */
13921 OT_odd_infix_unc
, /* This is the unconditional variant of an
13922 instruction that takes a conditional infix
13923 at an unusual position. In unified mode,
13924 this variant will accept a suffix. */
13925 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13926 are the conditional variants of instructions that
13927 take conditional infixes in unusual positions.
13928 The infix appears at character index
13929 (tag - OT_odd_infix_0). These are not accepted
13930 in unified mode. */
13933 /* Subroutine of md_assemble, responsible for looking up the primary
13934 opcode from the mnemonic the user wrote. STR points to the
13935 beginning of the mnemonic.
13937 This is not simply a hash table lookup, because of conditional
13938 variants. Most instructions have conditional variants, which are
13939 expressed with a _conditional affix_ to the mnemonic. If we were
13940 to encode each conditional variant as a literal string in the opcode
13941 table, it would have approximately 20,000 entries.
13943 Most mnemonics take this affix as a suffix, and in unified syntax,
13944 'most' is upgraded to 'all'. However, in the divided syntax, some
13945 instructions take the affix as an infix, notably the s-variants of
13946 the arithmetic instructions. Of those instructions, all but six
13947 have the infix appear after the third character of the mnemonic.
13949 Accordingly, the algorithm for looking up primary opcodes given
13952 1. Look up the identifier in the opcode table.
13953 If we find a match, go to step U.
13955 2. Look up the last two characters of the identifier in the
13956 conditions table. If we find a match, look up the first N-2
13957 characters of the identifier in the opcode table. If we
13958 find a match, go to step CE.
13960 3. Look up the fourth and fifth characters of the identifier in
13961 the conditions table. If we find a match, extract those
13962 characters from the identifier, and look up the remaining
13963 characters in the opcode table. If we find a match, go
13968 U. Examine the tag field of the opcode structure, in case this is
13969 one of the six instructions with its conditional infix in an
13970 unusual place. If it is, the tag tells us where to find the
13971 infix; look it up in the conditions table and set inst.cond
13972 accordingly. Otherwise, this is an unconditional instruction.
13973 Again set inst.cond accordingly. Return the opcode structure.
13975 CE. Examine the tag field to make sure this is an instruction that
13976 should receive a conditional suffix. If it is not, fail.
13977 Otherwise, set inst.cond from the suffix we already looked up,
13978 and return the opcode structure.
13980 CM. Examine the tag field to make sure this is an instruction that
13981 should receive a conditional infix after the third character.
13982 If it is not, fail. Otherwise, undo the edits to the current
13983 line of input and proceed as for case CE. */
13985 static const struct asm_opcode
*
13986 opcode_lookup (char **str
)
13990 const struct asm_opcode
*opcode
;
13991 const struct asm_cond
*cond
;
13993 bfd_boolean neon_supported
;
13995 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
13997 /* Scan up to the end of the mnemonic, which must end in white space,
13998 '.' (in unified mode, or for Neon instructions), or end of string. */
13999 for (base
= end
= *str
; *end
!= '\0'; end
++)
14000 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14006 /* Handle a possible width suffix and/or Neon type suffix. */
14011 /* The .w and .n suffixes are only valid if the unified syntax is in
14013 if (unified_syntax
&& end
[1] == 'w')
14015 else if (unified_syntax
&& end
[1] == 'n')
14020 inst
.vectype
.elems
= 0;
14022 *str
= end
+ offset
;
14024 if (end
[offset
] == '.')
14026 /* See if we have a Neon type suffix (possible in either unified or
14027 non-unified ARM syntax mode). */
14028 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14031 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14037 /* Look for unaffixed or special-case affixed mnemonic. */
14038 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14042 if (opcode
->tag
< OT_odd_infix_0
)
14044 inst
.cond
= COND_ALWAYS
;
14048 if (unified_syntax
)
14049 as_warn (_("conditional infixes are deprecated in unified syntax"));
14050 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14051 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14054 inst
.cond
= cond
->value
;
14058 /* Cannot have a conditional suffix on a mnemonic of less than two
14060 if (end
- base
< 3)
14063 /* Look for suffixed mnemonic. */
14065 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14066 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14067 if (opcode
&& cond
)
14070 switch (opcode
->tag
)
14072 case OT_cinfix3_legacy
:
14073 /* Ignore conditional suffixes matched on infix only mnemonics. */
14077 case OT_cinfix3_deprecated
:
14078 case OT_odd_infix_unc
:
14079 if (!unified_syntax
)
14081 /* else fall through */
14085 case OT_csuf_or_in3
:
14086 inst
.cond
= cond
->value
;
14089 case OT_unconditional
:
14090 case OT_unconditionalF
:
14093 inst
.cond
= cond
->value
;
14097 /* delayed diagnostic */
14098 inst
.error
= BAD_COND
;
14099 inst
.cond
= COND_ALWAYS
;
14108 /* Cannot have a usual-position infix on a mnemonic of less than
14109 six characters (five would be a suffix). */
14110 if (end
- base
< 6)
14113 /* Look for infixed mnemonic in the usual position. */
14115 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14119 memcpy (save
, affix
, 2);
14120 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14121 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14122 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14123 memcpy (affix
, save
, 2);
14126 && (opcode
->tag
== OT_cinfix3
14127 || opcode
->tag
== OT_cinfix3_deprecated
14128 || opcode
->tag
== OT_csuf_or_in3
14129 || opcode
->tag
== OT_cinfix3_legacy
))
14133 && (opcode
->tag
== OT_cinfix3
14134 || opcode
->tag
== OT_cinfix3_deprecated
))
14135 as_warn (_("conditional infixes are deprecated in unified syntax"));
14137 inst
.cond
= cond
->value
;
14145 md_assemble (char *str
)
14148 const struct asm_opcode
* opcode
;
14150 /* Align the previous label if needed. */
14151 if (last_label_seen
!= NULL
)
14153 symbol_set_frag (last_label_seen
, frag_now
);
14154 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14155 S_SET_SEGMENT (last_label_seen
, now_seg
);
14158 memset (&inst
, '\0', sizeof (inst
));
14159 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14161 opcode
= opcode_lookup (&p
);
14164 /* It wasn't an instruction, but it might be a register alias of
14165 the form alias .req reg, or a Neon .dn/.qn directive. */
14166 if (!create_register_alias (str
, p
)
14167 && !create_neon_reg_alias (str
, p
))
14168 as_bad (_("bad instruction `%s'"), str
);
14173 if (opcode
->tag
== OT_cinfix3_deprecated
)
14174 as_warn (_("s suffix on comparison instruction is deprecated"));
14176 /* The value which unconditional instructions should have in place of the
14177 condition field. */
14178 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14182 arm_feature_set variant
;
14184 variant
= cpu_variant
;
14185 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14186 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14187 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14188 /* Check that this instruction is supported for this CPU. */
14189 if (!opcode
->tvariant
14190 || (thumb_mode
== 1
14191 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14193 as_bad (_("selected processor does not support `%s'"), str
);
14196 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14197 && opcode
->tencode
!= do_t_branch
)
14199 as_bad (_("Thumb does not support conditional execution"));
14203 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14205 /* Implicit require narrow instructions on Thumb-1. This avoids
14206 relaxation accidentally introducing Thumb-2 instructions. */
14207 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
)
14211 /* Check conditional suffixes. */
14212 if (current_it_mask
)
14215 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14216 current_it_mask
<<= 1;
14217 current_it_mask
&= 0x1f;
14218 /* The BKPT instruction is unconditional even in an IT block. */
14220 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14222 as_bad (_("incorrect condition in IT block"));
14226 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14228 as_bad (_("thumb conditional instruction not in IT block"));
14232 mapping_state (MAP_THUMB
);
14233 inst
.instruction
= opcode
->tvalue
;
14235 if (!parse_operands (p
, opcode
->operands
))
14236 opcode
->tencode ();
14238 /* Clear current_it_mask at the end of an IT block. */
14239 if (current_it_mask
== 0x10)
14240 current_it_mask
= 0;
14242 if (!(inst
.error
|| inst
.relax
))
14244 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14245 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14246 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14248 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14253 /* Something has gone badly wrong if we try to relax a fixed size
14255 assert (inst
.size_req
== 0 || !inst
.relax
);
14257 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14258 *opcode
->tvariant
);
14259 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14260 set those bits when Thumb-2 32-bit instructions are seen. ie.
14261 anything other than bl/blx.
14262 This is overly pessimistic for relaxable instructions. */
14263 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14265 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14268 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14270 /* Check that this instruction is supported for this CPU. */
14271 if (!opcode
->avariant
||
14272 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
14274 as_bad (_("selected processor does not support `%s'"), str
);
14279 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14283 mapping_state (MAP_ARM
);
14284 inst
.instruction
= opcode
->avalue
;
14285 if (opcode
->tag
== OT_unconditionalF
)
14286 inst
.instruction
|= 0xF << 28;
14288 inst
.instruction
|= inst
.cond
<< 28;
14289 inst
.size
= INSN_SIZE
;
14290 if (!parse_operands (p
, opcode
->operands
))
14291 opcode
->aencode ();
14292 /* Arm mode bx is marked as both v4T and v5 because it's still required
14293 on a hypothetical non-thumb v5 core. */
14294 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
14295 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
14296 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14298 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14299 *opcode
->avariant
);
14303 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14310 /* Various frobbings of labels and their addresses. */
14313 arm_start_line_hook (void)
14315 last_label_seen
= NULL
;
14319 arm_frob_label (symbolS
* sym
)
14321 last_label_seen
= sym
;
14323 ARM_SET_THUMB (sym
, thumb_mode
);
14325 #if defined OBJ_COFF || defined OBJ_ELF
14326 ARM_SET_INTERWORK (sym
, support_interwork
);
14329 /* Note - do not allow local symbols (.Lxxx) to be labelled
14330 as Thumb functions. This is because these labels, whilst
14331 they exist inside Thumb code, are not the entry points for
14332 possible ARM->Thumb calls. Also, these labels can be used
14333 as part of a computed goto or switch statement. eg gcc
14334 can generate code that looks like this:
14336 ldr r2, [pc, .Laaa]
14346 The first instruction loads the address of the jump table.
14347 The second instruction converts a table index into a byte offset.
14348 The third instruction gets the jump address out of the table.
14349 The fourth instruction performs the jump.
14351 If the address stored at .Laaa is that of a symbol which has the
14352 Thumb_Func bit set, then the linker will arrange for this address
14353 to have the bottom bit set, which in turn would mean that the
14354 address computation performed by the third instruction would end
14355 up with the bottom bit set. Since the ARM is capable of unaligned
14356 word loads, the instruction would then load the incorrect address
14357 out of the jump table, and chaos would ensue. */
14358 if (label_is_thumb_function_name
14359 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14360 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14362 /* When the address of a Thumb function is taken the bottom
14363 bit of that address should be set. This will allow
14364 interworking between Arm and Thumb functions to work
14367 THUMB_SET_FUNC (sym
, 1);
14369 label_is_thumb_function_name
= FALSE
;
14372 dwarf2_emit_label (sym
);
14376 arm_data_in_code (void)
14378 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14380 *input_line_pointer
= '/';
14381 input_line_pointer
+= 5;
14382 *input_line_pointer
= 0;
14390 arm_canonicalize_symbol_name (char * name
)
14394 if (thumb_mode
&& (len
= strlen (name
)) > 5
14395 && streq (name
+ len
- 5, "/data"))
14396 *(name
+ len
- 5) = 0;
14401 /* Table of all register names defined by default. The user can
14402 define additional names with .req. Note that all register names
14403 should appear in both upper and lowercase variants. Some registers
14404 also have mixed-case names. */
14406 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14407 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14408 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14409 #define REGSET(p,t) \
14410 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14411 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14412 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14413 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14414 #define REGSETH(p,t) \
14415 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14416 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14417 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14418 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14419 #define REGSET2(p,t) \
14420 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14421 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14422 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14423 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14425 static const struct reg_entry reg_names
[] =
14427 /* ARM integer registers. */
14428 REGSET(r
, RN
), REGSET(R
, RN
),
14430 /* ATPCS synonyms. */
14431 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14432 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14433 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14435 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14436 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14437 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14439 /* Well-known aliases. */
14440 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14441 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14443 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14444 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14446 /* Coprocessor numbers. */
14447 REGSET(p
, CP
), REGSET(P
, CP
),
14449 /* Coprocessor register numbers. The "cr" variants are for backward
14451 REGSET(c
, CN
), REGSET(C
, CN
),
14452 REGSET(cr
, CN
), REGSET(CR
, CN
),
14454 /* FPA registers. */
14455 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14456 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14458 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14459 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14461 /* VFP SP registers. */
14462 REGSET(s
,VFS
), REGSET(S
,VFS
),
14463 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14465 /* VFP DP Registers. */
14466 REGSET(d
,VFD
), REGSET(D
,VFD
),
14467 /* Extra Neon DP registers. */
14468 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14470 /* Neon QP registers. */
14471 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14473 /* VFP control registers. */
14474 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14475 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14476 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
14477 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
14478 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
14479 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
14481 /* Maverick DSP coprocessor registers. */
14482 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14483 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14485 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14486 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14487 REGDEF(dspsc
,0,DSPSC
),
14489 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14490 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14491 REGDEF(DSPSC
,0,DSPSC
),
14493 /* iWMMXt data registers - p0, c0-15. */
14494 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14496 /* iWMMXt control registers - p1, c0-3. */
14497 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14498 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14499 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14500 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14502 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14503 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14504 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14505 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14506 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14508 /* XScale accumulator registers. */
14509 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14515 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14516 within psr_required_here. */
14517 static const struct asm_psr psrs
[] =
14519 /* Backward compatibility notation. Note that "all" is no longer
14520 truly all possible PSR bits. */
14521 {"all", PSR_c
| PSR_f
},
14525 /* Individual flags. */
14530 /* Combinations of flags. */
14531 {"fs", PSR_f
| PSR_s
},
14532 {"fx", PSR_f
| PSR_x
},
14533 {"fc", PSR_f
| PSR_c
},
14534 {"sf", PSR_s
| PSR_f
},
14535 {"sx", PSR_s
| PSR_x
},
14536 {"sc", PSR_s
| PSR_c
},
14537 {"xf", PSR_x
| PSR_f
},
14538 {"xs", PSR_x
| PSR_s
},
14539 {"xc", PSR_x
| PSR_c
},
14540 {"cf", PSR_c
| PSR_f
},
14541 {"cs", PSR_c
| PSR_s
},
14542 {"cx", PSR_c
| PSR_x
},
14543 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14544 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14545 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14546 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14547 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14548 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14549 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14550 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14551 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14552 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14553 {"scf", PSR_s
| PSR_c
| PSR_f
},
14554 {"scx", PSR_s
| PSR_c
| PSR_x
},
14555 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14556 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14557 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14558 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14559 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14560 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14561 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14562 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14563 {"csf", PSR_c
| PSR_s
| PSR_f
},
14564 {"csx", PSR_c
| PSR_s
| PSR_x
},
14565 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14566 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14567 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14568 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14569 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14570 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14571 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14572 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14573 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14574 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14575 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14576 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14577 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14578 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14579 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14580 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14581 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14582 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14583 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14584 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14585 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14586 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14587 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14588 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14589 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14590 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14593 /* Table of V7M psr names. */
14594 static const struct asm_psr v7m_psrs
[] =
14596 {"apsr", 0 }, {"APSR", 0 },
14597 {"iapsr", 1 }, {"IAPSR", 1 },
14598 {"eapsr", 2 }, {"EAPSR", 2 },
14599 {"psr", 3 }, {"PSR", 3 },
14600 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
14601 {"ipsr", 5 }, {"IPSR", 5 },
14602 {"epsr", 6 }, {"EPSR", 6 },
14603 {"iepsr", 7 }, {"IEPSR", 7 },
14604 {"msp", 8 }, {"MSP", 8 },
14605 {"psp", 9 }, {"PSP", 9 },
14606 {"primask", 16}, {"PRIMASK", 16},
14607 {"basepri", 17}, {"BASEPRI", 17},
14608 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
14609 {"faultmask", 19}, {"FAULTMASK", 19},
14610 {"control", 20}, {"CONTROL", 20}
14613 /* Table of all shift-in-operand names. */
14614 static const struct asm_shift_name shift_names
[] =
14616 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14617 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14618 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14619 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14620 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14621 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14624 /* Table of all explicit relocation names. */
14626 static struct reloc_entry reloc_names
[] =
14628 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14629 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14630 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14631 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14632 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14633 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14634 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14635 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14636 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14637 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14638 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14642 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14643 static const struct asm_cond conds
[] =
14647 {"cs", 0x2}, {"hs", 0x2},
14648 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14662 static struct asm_barrier_opt barrier_opt_names
[] =
14670 /* Table of ARM-format instructions. */
14672 /* Macros for gluing together operand strings. N.B. In all cases
14673 other than OPS0, the trailing OP_stop comes from default
14674 zero-initialization of the unspecified elements of the array. */
14675 #define OPS0() { OP_stop, }
14676 #define OPS1(a) { OP_##a, }
14677 #define OPS2(a,b) { OP_##a,OP_##b, }
14678 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14679 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14680 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14681 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14683 /* These macros abstract out the exact format of the mnemonic table and
14684 save some repeated characters. */
14686 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14687 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14688 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14689 THUMB_VARIANT, do_##ae, do_##te }
14691 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14692 a T_MNEM_xyz enumerator. */
14693 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14694 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14695 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14696 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14698 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14699 infix after the third character. */
14700 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14701 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14702 THUMB_VARIANT, do_##ae, do_##te }
14703 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14704 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14705 THUMB_VARIANT, do_##ae, do_##te }
14706 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14707 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14708 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14709 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14710 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14711 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14712 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14713 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14715 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14716 appear in the condition table. */
14717 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14718 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14719 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14721 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14722 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14723 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14724 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14725 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14726 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14727 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14728 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14729 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14730 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14731 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14732 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14733 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14734 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14735 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14736 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14737 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14738 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14739 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14740 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14742 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14743 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14744 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14745 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14747 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14748 field is still 0xE. Many of the Thumb variants can be executed
14749 conditionally, so this is checked separately. */
14750 #define TUE(mnem, op, top, nops, ops, ae, te) \
14751 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14752 THUMB_VARIANT, do_##ae, do_##te }
14754 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14755 condition code field. */
14756 #define TUF(mnem, op, top, nops, ops, ae, te) \
14757 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14758 THUMB_VARIANT, do_##ae, do_##te }
14760 /* ARM-only variants of all the above. */
14761 #define CE(mnem, op, nops, ops, ae) \
14762 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14764 #define C3(mnem, op, nops, ops, ae) \
14765 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14767 /* Legacy mnemonics that always have conditional infix after the third
14769 #define CL(mnem, op, nops, ops, ae) \
14770 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14771 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14773 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14774 #define cCE(mnem, op, nops, ops, ae) \
14775 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14777 /* Legacy coprocessor instructions where conditional infix and conditional
14778 suffix are ambiguous. For consistency this includes all FPA instructions,
14779 not just the potentially ambiguous ones. */
14780 #define cCL(mnem, op, nops, ops, ae) \
14781 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14782 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14784 /* Coprocessor, takes either a suffix or a position-3 infix
14785 (for an FPA corner case). */
14786 #define C3E(mnem, op, nops, ops, ae) \
14787 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14788 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14790 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14791 { #m1 #m2 #m3, OPS##nops ops, \
14792 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14793 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14795 #define CM(m1, m2, op, nops, ops, ae) \
14796 xCM_(m1, , m2, op, nops, ops, ae), \
14797 xCM_(m1, eq, m2, op, nops, ops, ae), \
14798 xCM_(m1, ne, m2, op, nops, ops, ae), \
14799 xCM_(m1, cs, m2, op, nops, ops, ae), \
14800 xCM_(m1, hs, m2, op, nops, ops, ae), \
14801 xCM_(m1, cc, m2, op, nops, ops, ae), \
14802 xCM_(m1, ul, m2, op, nops, ops, ae), \
14803 xCM_(m1, lo, m2, op, nops, ops, ae), \
14804 xCM_(m1, mi, m2, op, nops, ops, ae), \
14805 xCM_(m1, pl, m2, op, nops, ops, ae), \
14806 xCM_(m1, vs, m2, op, nops, ops, ae), \
14807 xCM_(m1, vc, m2, op, nops, ops, ae), \
14808 xCM_(m1, hi, m2, op, nops, ops, ae), \
14809 xCM_(m1, ls, m2, op, nops, ops, ae), \
14810 xCM_(m1, ge, m2, op, nops, ops, ae), \
14811 xCM_(m1, lt, m2, op, nops, ops, ae), \
14812 xCM_(m1, gt, m2, op, nops, ops, ae), \
14813 xCM_(m1, le, m2, op, nops, ops, ae), \
14814 xCM_(m1, al, m2, op, nops, ops, ae)
14816 #define UE(mnem, op, nops, ops, ae) \
14817 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14819 #define UF(mnem, op, nops, ops, ae) \
14820 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14822 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14823 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14824 use the same encoding function for each. */
14825 #define NUF(mnem, op, nops, ops, enc) \
14826 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14827 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14829 /* Neon data processing, version which indirects through neon_enc_tab for
14830 the various overloaded versions of opcodes. */
14831 #define nUF(mnem, op, nops, ops, enc) \
14832 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14833 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14835 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14837 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14838 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14839 THUMB_VARIANT, do_##enc, do_##enc }
14841 #define NCE(mnem, op, nops, ops, enc) \
14842 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14844 #define NCEF(mnem, op, nops, ops, enc) \
14845 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14847 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14848 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14849 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14850 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14852 #define nCE(mnem, op, nops, ops, enc) \
14853 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14855 #define nCEF(mnem, op, nops, ops, enc) \
14856 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14860 /* Thumb-only, unconditional. */
14861 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14863 static const struct asm_opcode insns
[] =
14865 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14866 #define THUMB_VARIANT &arm_ext_v4t
14867 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14868 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14869 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14870 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14871 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14872 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14873 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14874 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14875 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14876 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14877 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14878 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14879 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14880 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14881 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14882 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14884 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14885 for setting PSR flag bits. They are obsolete in V6 and do not
14886 have Thumb equivalents. */
14887 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14888 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14889 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14890 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14891 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14892 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14893 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14894 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14895 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14897 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14898 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14899 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14900 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14902 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14903 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14904 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14905 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14907 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14908 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14909 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14910 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14911 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14912 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14914 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14915 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14916 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14917 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14920 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14921 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14922 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14924 /* Thumb-compatibility pseudo ops. */
14925 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14926 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14927 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14928 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14929 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14930 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14931 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14932 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14933 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14934 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14935 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14936 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14938 /* These may simplify to neg. */
14939 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14940 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14942 #undef THUMB_VARIANT
14943 #define THUMB_VARIANT &arm_ext_v6
14944 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14946 /* V1 instructions with no Thumb analogue prior to V6T2. */
14947 #undef THUMB_VARIANT
14948 #define THUMB_VARIANT &arm_ext_v6t2
14949 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14950 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14951 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14953 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14954 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14955 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14956 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14958 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14959 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14961 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14962 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14964 /* V1 instructions with no Thumb analogue at all. */
14965 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14966 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14968 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14969 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14970 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14971 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14972 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14973 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14974 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14975 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14978 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14979 #undef THUMB_VARIANT
14980 #define THUMB_VARIANT &arm_ext_v4t
14981 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14982 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14984 #undef THUMB_VARIANT
14985 #define THUMB_VARIANT &arm_ext_v6t2
14986 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14987 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14989 /* Generic coprocessor instructions. */
14990 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14991 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14992 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14993 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14994 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14995 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14996 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14999 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15000 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15001 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15004 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15005 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15006 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15009 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15010 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15011 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15012 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15013 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15014 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15015 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15016 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15017 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15020 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15021 #undef THUMB_VARIANT
15022 #define THUMB_VARIANT &arm_ext_v4t
15023 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15024 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15025 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15026 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15027 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15028 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15031 #define ARM_VARIANT &arm_ext_v4t_5
15032 /* ARM Architecture 4T. */
15033 /* Note: bx (and blx) are required on V5, even if the processor does
15034 not support Thumb. */
15035 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15038 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15039 #undef THUMB_VARIANT
15040 #define THUMB_VARIANT &arm_ext_v5t
15041 /* Note: blx has 2 variants; the .value coded here is for
15042 BLX(2). Only this variant has conditional execution. */
15043 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15044 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15046 #undef THUMB_VARIANT
15047 #define THUMB_VARIANT &arm_ext_v6t2
15048 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15049 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15050 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15051 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15052 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15053 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15054 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15055 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15058 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15059 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15060 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15061 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15062 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15064 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15065 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15067 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15068 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15069 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15070 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15072 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15073 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15074 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15075 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15077 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15078 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15080 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15081 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15082 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15083 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
15086 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15087 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15088 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15089 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15091 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15092 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15095 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15096 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15099 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15100 #undef THUMB_VARIANT
15101 #define THUMB_VARIANT &arm_ext_v6
15102 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15103 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15104 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15105 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15106 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15107 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15108 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15109 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15110 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15111 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15113 #undef THUMB_VARIANT
15114 #define THUMB_VARIANT &arm_ext_v6t2
15115 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15116 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15117 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15118 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15120 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15121 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15123 /* ARM V6 not included in V7M (eg. integer SIMD). */
15124 #undef THUMB_VARIANT
15125 #define THUMB_VARIANT &arm_ext_v6_notm
15126 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15127 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15128 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15129 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15130 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15131 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15132 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15133 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15134 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15135 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15136 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15137 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15138 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15139 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15140 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15141 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15142 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15143 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15144 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15145 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15146 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15147 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15148 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15149 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15150 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15151 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15152 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15153 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15154 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15155 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15156 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15157 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15158 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15159 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15160 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15161 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15162 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15163 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15164 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15165 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15166 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15167 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15168 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15169 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15170 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15171 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15172 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15173 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15174 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15175 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15176 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15177 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15178 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15179 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15180 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15181 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15182 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15183 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15184 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15185 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15186 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15187 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15188 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15189 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15190 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15191 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15192 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15193 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15194 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15195 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15196 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15197 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15198 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15199 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15200 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15201 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15202 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15203 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15204 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15205 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15206 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15207 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15208 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15211 #define ARM_VARIANT &arm_ext_v6k
15212 #undef THUMB_VARIANT
15213 #define THUMB_VARIANT &arm_ext_v6k
15214 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15215 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15216 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15217 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15219 #undef THUMB_VARIANT
15220 #define THUMB_VARIANT &arm_ext_v6_notm
15221 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15222 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15224 #undef THUMB_VARIANT
15225 #define THUMB_VARIANT &arm_ext_v6t2
15226 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15227 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15228 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15229 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15230 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15233 #define ARM_VARIANT &arm_ext_v6z
15234 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15237 #define ARM_VARIANT &arm_ext_v6t2
15238 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15239 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15240 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15241 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15243 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15244 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15245 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15246 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15248 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15249 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15250 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15251 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15253 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15254 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15255 /* ARM does not really have an IT instruction, so always allow it. */
15257 #define ARM_VARIANT &arm_ext_v1
15258 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15259 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15260 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15261 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15262 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15263 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15264 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15265 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15266 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15267 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15268 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15269 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15270 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15271 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15272 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15274 /* Thumb2 only instructions. */
15276 #define ARM_VARIANT NULL
15278 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15279 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15280 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15281 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15283 /* Thumb-2 hardware division instructions (R and M profiles only). */
15284 #undef THUMB_VARIANT
15285 #define THUMB_VARIANT &arm_ext_div
15286 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15287 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15289 /* ARM V7 instructions. */
15291 #define ARM_VARIANT &arm_ext_v7
15292 #undef THUMB_VARIANT
15293 #define THUMB_VARIANT &arm_ext_v7
15294 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15295 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15296 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15297 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15298 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15301 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15302 cCE(wfs
, e200110
, 1, (RR
), rd
),
15303 cCE(rfs
, e300110
, 1, (RR
), rd
),
15304 cCE(wfc
, e400110
, 1, (RR
), rd
),
15305 cCE(rfc
, e500110
, 1, (RR
), rd
),
15307 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15308 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15309 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15310 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15312 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15313 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15314 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15315 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15317 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15318 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15319 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15320 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15321 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15322 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15323 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15324 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15325 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15326 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15327 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15328 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15330 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15331 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15332 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15333 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15334 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15335 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15336 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15337 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15338 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15339 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15340 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15341 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15343 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15344 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15345 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15346 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15347 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15348 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15349 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15350 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15351 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15352 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15353 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15354 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15356 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15357 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15358 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15359 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15360 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15361 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15362 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15363 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15364 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15365 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15366 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15367 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15369 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15370 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15371 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15372 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15373 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15374 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15375 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15376 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15377 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15378 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15379 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15380 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15382 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15383 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15384 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15385 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15386 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15387 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15388 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15389 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15390 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15391 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15392 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15393 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15395 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15396 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15397 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15398 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15399 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15400 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15401 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15402 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15403 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15404 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15405 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15406 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15408 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15409 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
15410 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
15411 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
15412 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
15413 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
15414 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
15415 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
15416 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
15417 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
15418 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
15419 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
15421 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
15422 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
15423 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
15424 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
15425 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
15426 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
15427 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
15428 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
15429 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15430 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15431 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15432 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15434 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15435 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15436 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15437 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15438 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15439 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15440 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15441 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15442 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15443 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15444 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15445 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15447 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15448 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15449 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15450 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15451 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15452 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15453 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15454 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15455 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15456 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15457 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15458 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15460 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15461 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15462 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15463 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15464 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15465 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15466 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15467 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15468 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15469 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15470 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15471 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15473 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15474 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15475 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15476 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15477 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15478 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15479 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15480 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15481 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15482 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15483 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15484 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15486 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15487 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15488 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15489 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15490 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15491 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15492 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15493 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15494 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15495 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15496 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15497 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15499 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15500 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15501 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15502 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15503 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15504 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15505 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15506 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15507 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15508 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15509 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15510 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15512 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15513 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15514 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15515 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15516 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15517 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15518 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15519 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15520 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15521 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15522 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15523 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15525 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15526 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15527 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15528 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15529 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15530 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15531 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15532 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15533 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15534 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15535 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15536 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15538 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15539 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15540 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15541 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15542 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15543 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15544 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15545 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15546 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15547 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15548 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15549 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15551 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15552 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15553 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15554 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15555 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15556 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15557 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15558 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15559 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15560 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15561 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15562 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15564 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15565 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15566 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15567 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15568 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15569 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15570 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15571 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15572 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15573 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15574 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15575 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15577 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15578 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15579 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15580 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15581 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15582 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15583 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15584 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15585 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15586 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15587 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15588 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15590 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15591 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15592 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15593 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15594 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15595 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15596 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15597 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15598 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15599 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15600 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15601 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15603 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15604 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15605 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15606 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15607 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15608 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15609 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15610 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15611 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15612 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15613 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15614 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15616 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15617 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15618 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15619 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15620 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15621 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15622 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15623 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15624 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15625 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15626 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15627 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15629 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15630 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15631 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15632 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15633 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15634 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15635 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15636 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15637 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15638 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15639 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15640 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15642 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15643 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15644 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15645 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15646 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15647 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15648 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15649 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15650 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15651 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15652 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15653 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15655 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15656 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15657 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15658 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15659 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15660 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15661 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15662 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15663 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15664 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15665 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15666 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15668 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15669 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15670 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15671 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15672 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15673 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15674 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15675 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15676 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15677 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15678 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15679 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15681 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15682 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15683 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15684 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15685 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15686 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15687 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15688 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15689 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15690 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15691 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15692 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15694 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15695 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15696 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15697 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15699 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15700 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15701 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15702 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15703 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15704 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15705 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15706 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15707 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15708 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15709 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15710 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15712 /* The implementation of the FIX instruction is broken on some
15713 assemblers, in that it accepts a precision specifier as well as a
15714 rounding specifier, despite the fact that this is meaningless.
15715 To be more compatible, we accept it as well, though of course it
15716 does not set any bits. */
15717 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15718 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15719 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15720 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15721 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15722 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15723 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15724 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15725 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15726 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15727 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15728 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15729 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15731 /* Instructions that were new with the real FPA, call them V2. */
15733 #define ARM_VARIANT &fpu_fpa_ext_v2
15734 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15735 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15736 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15737 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15738 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15739 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15742 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15743 /* Moves and type conversions. */
15744 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15745 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15746 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15747 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15748 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15749 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15750 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15751 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15752 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15753 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15754 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15755 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15757 /* Memory operations. */
15758 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15759 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15760 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15761 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15762 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15763 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15764 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15765 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15766 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15767 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15768 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15769 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15770 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15771 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15772 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15773 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15774 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15775 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15777 /* Monadic operations. */
15778 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15779 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15780 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15782 /* Dyadic operations. */
15783 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15784 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15785 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15786 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15787 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15788 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15789 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15790 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15791 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15794 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15795 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15796 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15797 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15800 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15801 /* Moves and type conversions. */
15802 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15803 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15804 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15805 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15806 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15807 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15808 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15809 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15810 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15811 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15812 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15813 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15814 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15816 /* Memory operations. */
15817 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15818 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15819 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15820 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15821 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15822 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15823 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15824 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15825 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15826 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15828 /* Monadic operations. */
15829 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15830 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15831 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15833 /* Dyadic operations. */
15834 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15835 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15836 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15837 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15838 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15839 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15840 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15841 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15842 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15845 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15846 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15847 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15848 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15851 #define ARM_VARIANT &fpu_vfp_ext_v2
15852 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15853 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15854 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15855 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15857 /* Instructions which may belong to either the Neon or VFP instruction sets.
15858 Individual encoder functions perform additional architecture checks. */
15860 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15861 #undef THUMB_VARIANT
15862 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15863 /* These mnemonics are unique to VFP. */
15864 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15865 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15866 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15867 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15868 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15869 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15870 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15871 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15872 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15873 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15875 /* Mnemonics shared by Neon and VFP. */
15876 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15877 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15878 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15880 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15881 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15883 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15884 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15886 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15887 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15888 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15889 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15890 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15891 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15892 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15893 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15895 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15897 /* NOTE: All VMOV encoding is special-cased! */
15898 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15899 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15901 #undef THUMB_VARIANT
15902 #define THUMB_VARIANT &fpu_neon_ext_v1
15904 #define ARM_VARIANT &fpu_neon_ext_v1
15905 /* Data processing with three registers of the same length. */
15906 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15907 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15908 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15909 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15910 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15911 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15912 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15913 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15914 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15915 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15916 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15917 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15918 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15919 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15920 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15921 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15922 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
15923 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
15924 /* If not immediate, fall back to neon_dyadic_i64_su.
15925 shl_imm should accept I8 I16 I32 I64,
15926 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15927 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15928 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15929 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15930 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15931 /* Logic ops, types optional & ignored. */
15932 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15933 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15934 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15935 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15936 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15937 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15938 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15939 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15940 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15941 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15942 /* Bitfield ops, untyped. */
15943 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15944 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15945 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15946 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15947 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15948 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15949 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15950 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15951 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15952 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15953 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15954 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15955 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15956 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15957 back to neon_dyadic_if_su. */
15958 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15959 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15960 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15961 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15962 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15963 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15964 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15965 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15966 /* Comparison. Type I8 I16 I32 F32. */
15967 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15968 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15969 /* As above, D registers only. */
15970 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15971 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15972 /* Int and float variants, signedness unimportant. */
15973 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15974 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15975 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15976 /* Add/sub take types I8 I16 I32 I64 F32. */
15977 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15978 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15979 /* vtst takes sizes 8, 16, 32. */
15980 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15981 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15982 /* VMUL takes I8 I16 I32 F32 P8. */
15983 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15984 /* VQD{R}MULH takes S16 S32. */
15985 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15986 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15987 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15988 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15989 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15990 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15991 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15992 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15993 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15994 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15995 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15996 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15997 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15998 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15999 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16000 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16002 /* Two address, int/float. Types S8 S16 S32 F32. */
16003 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16004 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16006 /* Data processing with two registers and a shift amount. */
16007 /* Right shifts, and variants with rounding.
16008 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16009 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16010 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16011 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16012 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16013 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16014 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16015 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16016 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16017 /* Shift and insert. Sizes accepted 8 16 32 64. */
16018 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16019 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16020 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16021 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16022 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16023 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16024 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16025 /* Right shift immediate, saturating & narrowing, with rounding variants.
16026 Types accepted S16 S32 S64 U16 U32 U64. */
16027 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16028 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16029 /* As above, unsigned. Types accepted S16 S32 S64. */
16030 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16031 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16032 /* Right shift narrowing. Types accepted I16 I32 I64. */
16033 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16034 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16035 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16036 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16037 /* CVT with optional immediate for fixed-point variant. */
16038 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16040 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16041 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16043 /* Data processing, three registers of different lengths. */
16044 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16045 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16046 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16047 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16048 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16049 /* If not scalar, fall back to neon_dyadic_long.
16050 Vector types as above, scalar types S16 S32 U16 U32. */
16051 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16052 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16053 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16054 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16055 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16056 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16057 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16058 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16059 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16060 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16061 /* Saturating doubling multiplies. Types S16 S32. */
16062 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16063 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16064 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16065 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16066 S16 S32 U16 U32. */
16067 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16069 /* Extract. Size 8. */
16070 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16071 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16073 /* Two registers, miscellaneous. */
16074 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16075 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16076 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16077 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16078 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16079 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16080 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16081 /* Vector replicate. Sizes 8 16 32. */
16082 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16083 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16084 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16085 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16086 /* VMOVN. Types I16 I32 I64. */
16087 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16088 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16089 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16090 /* VQMOVUN. Types S16 S32 S64. */
16091 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16092 /* VZIP / VUZP. Sizes 8 16 32. */
16093 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16094 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16095 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16096 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16097 /* VQABS / VQNEG. Types S8 S16 S32. */
16098 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16099 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16100 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16101 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16102 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16103 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16104 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16105 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16106 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16107 /* Reciprocal estimates. Types U32 F32. */
16108 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16109 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16110 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16111 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16112 /* VCLS. Types S8 S16 S32. */
16113 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16114 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16115 /* VCLZ. Types I8 I16 I32. */
16116 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16117 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16118 /* VCNT. Size 8. */
16119 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16120 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16121 /* Two address, untyped. */
16122 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16123 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16124 /* VTRN. Sizes 8 16 32. */
16125 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16126 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16128 /* Table lookup. Size 8. */
16129 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16130 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16132 #undef THUMB_VARIANT
16133 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16135 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16136 /* Neon element/structure load/store. */
16137 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16138 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16139 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16140 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16141 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16142 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16143 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16144 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16146 #undef THUMB_VARIANT
16147 #define THUMB_VARIANT &fpu_vfp_ext_v3
16149 #define ARM_VARIANT &fpu_vfp_ext_v3
16150 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16151 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16152 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16153 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16154 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16155 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16156 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16157 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16158 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16159 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16160 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16161 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16162 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16163 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16164 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16165 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16166 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16167 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16169 #undef THUMB_VARIANT
16171 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16172 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16173 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16174 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16175 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16176 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16177 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16178 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16179 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16182 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16183 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16184 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16185 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16186 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16187 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16188 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16189 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16190 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16191 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16192 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16193 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16194 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16195 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16196 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16197 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16198 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16199 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16200 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16201 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16202 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16203 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16204 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16205 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16206 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16207 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16208 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16209 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16210 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16211 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16212 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16213 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16214 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16215 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16216 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16217 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16218 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16219 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16220 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16221 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16222 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16223 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16224 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16225 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16226 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16227 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16228 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16229 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16230 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16231 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16232 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16233 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16234 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16235 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16236 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16237 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16238 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16239 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16240 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16241 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16242 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16243 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16244 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16245 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16246 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16247 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16248 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16249 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16250 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16251 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16252 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16253 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16254 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16255 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16256 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16257 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16258 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16259 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16260 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16261 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16262 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16263 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16264 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16265 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16266 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16267 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16268 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16269 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16270 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16271 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16272 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16273 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16274 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16275 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16276 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16277 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16278 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16279 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16280 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16281 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16282 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16283 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16284 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16285 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16286 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16287 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16288 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16289 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16290 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16291 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16292 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16293 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16294 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16295 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16296 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16297 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16298 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16299 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16300 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16301 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16302 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16303 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16304 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16305 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16306 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16307 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16308 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16309 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16310 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16311 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16312 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16313 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16314 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16315 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16316 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16317 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16318 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16319 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16320 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16321 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16322 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16323 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16324 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16325 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16326 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16327 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16328 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16329 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16330 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16331 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16332 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16333 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16334 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16335 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16336 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16337 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16338 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16339 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16340 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16341 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16342 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16343 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16344 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16347 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16348 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16349 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16350 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16351 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16352 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16353 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16354 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16355 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16356 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16357 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16358 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16359 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16360 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16361 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16362 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16363 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16364 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16365 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16366 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16367 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16368 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16369 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16370 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16371 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16372 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16373 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16374 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16375 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16376 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16377 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16378 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16379 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16380 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16381 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16382 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16383 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16384 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16385 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16386 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16387 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16388 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16389 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16390 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16391 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16392 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16393 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16394 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16395 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16396 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16397 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16398 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16399 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16400 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16401 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16402 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16403 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16404 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16407 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
16408 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16409 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16410 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16411 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16412 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
16413 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
16414 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
16415 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
16416 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
16417 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
16418 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
16419 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
16420 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
16421 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
16422 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
16423 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
16424 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
16425 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
16426 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
16427 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
16428 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
16429 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
16430 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
16431 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
16432 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
16433 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
16434 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
16435 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
16436 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
16437 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
16438 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
16439 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
16440 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
16441 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
16442 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
16443 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
16444 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
16445 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
16446 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
16447 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
16448 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
16449 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
16450 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
16451 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
16452 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
16453 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
16454 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
16455 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
16456 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
16457 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
16458 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
16459 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
16460 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
16461 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
16462 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16463 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16464 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16465 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16466 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
16467 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
16468 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
16469 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
16470 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
16471 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
16472 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16473 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16474 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16475 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16476 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16477 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
16478 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16479 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
16480 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16481 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
16482 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16483 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
16486 #undef THUMB_VARIANT
16513 /* MD interface: bits in the object file. */
16515 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16516 for use in the a.out file, and stores them in the array pointed to by buf.
16517 This knows about the endian-ness of the target machine and does
16518 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16519 2 (short) and 4 (long) Floating numbers are put out as a series of
16520 LITTLENUMS (shorts, here at least). */
16523 md_number_to_chars (char * buf
, valueT val
, int n
)
16525 if (target_big_endian
)
16526 number_to_chars_bigendian (buf
, val
, n
);
16528 number_to_chars_littleendian (buf
, val
, n
);
16532 md_chars_to_number (char * buf
, int n
)
16535 unsigned char * where
= (unsigned char *) buf
;
16537 if (target_big_endian
)
16542 result
|= (*where
++ & 255);
16550 result
|= (where
[n
] & 255);
16557 /* MD interface: Sections. */
16559 /* Estimate the size of a frag before relaxing. Assume everything fits in
16563 md_estimate_size_before_relax (fragS
* fragp
,
16564 segT segtype ATTRIBUTE_UNUSED
)
16570 /* Convert a machine dependent frag. */
16573 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16575 unsigned long insn
;
16576 unsigned long old_op
;
16584 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16586 old_op
= bfd_get_16(abfd
, buf
);
16587 if (fragp
->fr_symbol
)
16589 exp
.X_op
= O_symbol
;
16590 exp
.X_add_symbol
= fragp
->fr_symbol
;
16594 exp
.X_op
= O_constant
;
16596 exp
.X_add_number
= fragp
->fr_offset
;
16597 opcode
= fragp
->fr_subtype
;
16600 case T_MNEM_ldr_pc
:
16601 case T_MNEM_ldr_pc2
:
16602 case T_MNEM_ldr_sp
:
16603 case T_MNEM_str_sp
:
16610 if (fragp
->fr_var
== 4)
16612 insn
= THUMB_OP32 (opcode
);
16613 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16615 insn
|= (old_op
& 0x700) << 4;
16619 insn
|= (old_op
& 7) << 12;
16620 insn
|= (old_op
& 0x38) << 13;
16622 insn
|= 0x00000c00;
16623 put_thumb32_insn (buf
, insn
);
16624 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16628 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16630 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16633 if (fragp
->fr_var
== 4)
16635 insn
= THUMB_OP32 (opcode
);
16636 insn
|= (old_op
& 0xf0) << 4;
16637 put_thumb32_insn (buf
, insn
);
16638 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16642 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16643 exp
.X_add_number
-= 4;
16651 if (fragp
->fr_var
== 4)
16653 int r0off
= (opcode
== T_MNEM_mov
16654 || opcode
== T_MNEM_movs
) ? 0 : 8;
16655 insn
= THUMB_OP32 (opcode
);
16656 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16657 insn
|= (old_op
& 0x700) << r0off
;
16658 put_thumb32_insn (buf
, insn
);
16659 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16663 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16668 if (fragp
->fr_var
== 4)
16670 insn
= THUMB_OP32(opcode
);
16671 put_thumb32_insn (buf
, insn
);
16672 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16675 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16679 if (fragp
->fr_var
== 4)
16681 insn
= THUMB_OP32(opcode
);
16682 insn
|= (old_op
& 0xf00) << 14;
16683 put_thumb32_insn (buf
, insn
);
16684 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16687 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16690 case T_MNEM_add_sp
:
16691 case T_MNEM_add_pc
:
16692 case T_MNEM_inc_sp
:
16693 case T_MNEM_dec_sp
:
16694 if (fragp
->fr_var
== 4)
16696 /* ??? Choose between add and addw. */
16697 insn
= THUMB_OP32 (opcode
);
16698 insn
|= (old_op
& 0xf0) << 4;
16699 put_thumb32_insn (buf
, insn
);
16700 if (opcode
== T_MNEM_add_pc
)
16701 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16703 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16706 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16714 if (fragp
->fr_var
== 4)
16716 insn
= THUMB_OP32 (opcode
);
16717 insn
|= (old_op
& 0xf0) << 4;
16718 insn
|= (old_op
& 0xf) << 16;
16719 put_thumb32_insn (buf
, insn
);
16720 if (insn
& (1 << 20))
16721 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16723 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16726 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16732 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16734 fixp
->fx_file
= fragp
->fr_file
;
16735 fixp
->fx_line
= fragp
->fr_line
;
16736 fragp
->fr_fix
+= fragp
->fr_var
;
16739 /* Return the size of a relaxable immediate operand instruction.
16740 SHIFT and SIZE specify the form of the allowable immediate. */
16742 relax_immediate (fragS
*fragp
, int size
, int shift
)
16748 /* ??? Should be able to do better than this. */
16749 if (fragp
->fr_symbol
)
16752 low
= (1 << shift
) - 1;
16753 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16754 offset
= fragp
->fr_offset
;
16755 /* Force misaligned offsets to 32-bit variant. */
16758 if (offset
& ~mask
)
16763 /* Get the address of a symbol during relaxation. */
16765 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
16771 sym
= fragp
->fr_symbol
;
16772 sym_frag
= symbol_get_frag (sym
);
16773 know (S_GET_SEGMENT (sym
) != absolute_section
16774 || sym_frag
== &zero_address_frag
);
16775 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
16777 /* If frag has yet to be reached on this pass, assume it will
16778 move by STRETCH just as we did. If this is not so, it will
16779 be because some frag between grows, and that will force
16783 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
16787 /* Adjust stretch for any alignment frag. Note that if have
16788 been expanding the earlier code, the symbol may be
16789 defined in what appears to be an earlier frag. FIXME:
16790 This doesn't handle the fr_subtype field, which specifies
16791 a maximum number of bytes to skip when doing an
16793 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
16795 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
16798 stretch
= - ((- stretch
)
16799 & ~ ((1 << (int) f
->fr_offset
) - 1));
16801 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
16813 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16816 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
16821 /* Assume worst case for symbols not known to be in the same section. */
16822 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16823 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16826 val
= relaxed_symbol_addr (fragp
, stretch
);
16827 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16828 addr
= (addr
+ 4) & ~3;
16829 /* Force misaligned targets to 32-bit variant. */
16833 if (val
< 0 || val
> 1020)
16838 /* Return the size of a relaxable add/sub immediate instruction. */
16840 relax_addsub (fragS
*fragp
, asection
*sec
)
16845 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16846 op
= bfd_get_16(sec
->owner
, buf
);
16847 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16848 return relax_immediate (fragp
, 8, 0);
16850 return relax_immediate (fragp
, 3, 0);
16854 /* Return the size of a relaxable branch instruction. BITS is the
16855 size of the offset field in the narrow instruction. */
16858 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
16864 /* Assume worst case for symbols not known to be in the same section. */
16865 if (!S_IS_DEFINED (fragp
->fr_symbol
)
16866 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16869 val
= relaxed_symbol_addr (fragp
, stretch
);
16870 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16873 /* Offset is a signed value *2 */
16875 if (val
>= limit
|| val
< -limit
)
16881 /* Relax a machine dependent frag. This returns the amount by which
16882 the current size of the frag should change. */
16885 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
16890 oldsize
= fragp
->fr_var
;
16891 switch (fragp
->fr_subtype
)
16893 case T_MNEM_ldr_pc2
:
16894 newsize
= relax_adr (fragp
, sec
, stretch
);
16896 case T_MNEM_ldr_pc
:
16897 case T_MNEM_ldr_sp
:
16898 case T_MNEM_str_sp
:
16899 newsize
= relax_immediate (fragp
, 8, 2);
16903 newsize
= relax_immediate (fragp
, 5, 2);
16907 newsize
= relax_immediate (fragp
, 5, 1);
16911 newsize
= relax_immediate (fragp
, 5, 0);
16914 newsize
= relax_adr (fragp
, sec
, stretch
);
16920 newsize
= relax_immediate (fragp
, 8, 0);
16923 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
16926 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
16928 case T_MNEM_add_sp
:
16929 case T_MNEM_add_pc
:
16930 newsize
= relax_immediate (fragp
, 8, 2);
16932 case T_MNEM_inc_sp
:
16933 case T_MNEM_dec_sp
:
16934 newsize
= relax_immediate (fragp
, 7, 2);
16940 newsize
= relax_addsub (fragp
, sec
);
16946 fragp
->fr_var
= newsize
;
16947 /* Freeze wide instructions that are at or before the same location as
16948 in the previous pass. This avoids infinite loops.
16949 Don't freeze them unconditionally because targets may be artificially
16950 misaligned by the expansion of preceding frags. */
16951 if (stretch
<= 0 && newsize
> 2)
16953 md_convert_frag (sec
->owner
, sec
, fragp
);
16957 return newsize
- oldsize
;
16960 /* Round up a section size to the appropriate boundary. */
16963 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16966 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16967 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16969 /* For a.out, force the section size to be aligned. If we don't do
16970 this, BFD will align it for us, but it will not write out the
16971 final bytes of the section. This may be a bug in BFD, but it is
16972 easier to fix it here since that is how the other a.out targets
16976 align
= bfd_get_section_alignment (stdoutput
, segment
);
16977 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
16984 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16985 of an rs_align_code fragment. */
16988 arm_handle_align (fragS
* fragP
)
16990 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16991 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16992 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16993 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16995 int bytes
, fix
, noop_size
;
16999 if (fragP
->fr_type
!= rs_align_code
)
17002 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17003 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17006 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17007 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17009 if (fragP
->tc_frag_data
)
17011 if (target_big_endian
)
17012 noop
= thumb_bigend_noop
;
17015 noop_size
= sizeof (thumb_noop
);
17019 if (target_big_endian
)
17020 noop
= arm_bigend_noop
;
17023 noop_size
= sizeof (arm_noop
);
17026 if (bytes
& (noop_size
- 1))
17028 fix
= bytes
& (noop_size
- 1);
17029 memset (p
, 0, fix
);
17034 while (bytes
>= noop_size
)
17036 memcpy (p
, noop
, noop_size
);
17038 bytes
-= noop_size
;
17042 fragP
->fr_fix
+= fix
;
17043 fragP
->fr_var
= noop_size
;
17046 /* Called from md_do_align. Used to create an alignment
17047 frag in a code section. */
17050 arm_frag_align_code (int n
, int max
)
17054 /* We assume that there will never be a requirement
17055 to support alignments greater than 32 bytes. */
17056 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17057 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17059 p
= frag_var (rs_align_code
,
17060 MAX_MEM_FOR_RS_ALIGN_CODE
,
17062 (relax_substateT
) max
,
17069 /* Perform target specific initialisation of a frag. */
17072 arm_init_frag (fragS
* fragP
)
17074 /* Record whether this frag is in an ARM or a THUMB area. */
17075 fragP
->tc_frag_data
= thumb_mode
;
17079 /* When we change sections we need to issue a new mapping symbol. */
17082 arm_elf_change_section (void)
17085 segment_info_type
*seginfo
;
17087 /* Link an unlinked unwind index table section to the .text section. */
17088 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17089 && elf_linked_to_section (now_seg
) == NULL
)
17090 elf_linked_to_section (now_seg
) = text_section
;
17092 if (!SEG_NORMAL (now_seg
))
17095 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17097 /* We can ignore sections that only contain debug info. */
17098 if ((flags
& SEC_ALLOC
) == 0)
17101 seginfo
= seg_info (now_seg
);
17102 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17103 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17107 arm_elf_section_type (const char * str
, size_t len
)
17109 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17110 return SHT_ARM_EXIDX
;
17115 /* Code to deal with unwinding tables. */
17117 static void add_unwind_adjustsp (offsetT
);
17119 /* Generate any deferred unwind frame offset. */
17122 flush_pending_unwind (void)
17126 offset
= unwind
.pending_offset
;
17127 unwind
.pending_offset
= 0;
17129 add_unwind_adjustsp (offset
);
17132 /* Add an opcode to this list for this function. Two-byte opcodes should
17133 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17137 add_unwind_opcode (valueT op
, int length
)
17139 /* Add any deferred stack adjustment. */
17140 if (unwind
.pending_offset
)
17141 flush_pending_unwind ();
17143 unwind
.sp_restored
= 0;
17145 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17147 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17148 if (unwind
.opcodes
)
17149 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17150 unwind
.opcode_alloc
);
17152 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17157 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17159 unwind
.opcode_count
++;
17163 /* Add unwind opcodes to adjust the stack pointer. */
17166 add_unwind_adjustsp (offsetT offset
)
17170 if (offset
> 0x200)
17172 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17177 /* Long form: 0xb2, uleb128. */
17178 /* This might not fit in a word so add the individual bytes,
17179 remembering the list is built in reverse order. */
17180 o
= (valueT
) ((offset
- 0x204) >> 2);
17182 add_unwind_opcode (0, 1);
17184 /* Calculate the uleb128 encoding of the offset. */
17188 bytes
[n
] = o
& 0x7f;
17194 /* Add the insn. */
17196 add_unwind_opcode (bytes
[n
- 1], 1);
17197 add_unwind_opcode (0xb2, 1);
17199 else if (offset
> 0x100)
17201 /* Two short opcodes. */
17202 add_unwind_opcode (0x3f, 1);
17203 op
= (offset
- 0x104) >> 2;
17204 add_unwind_opcode (op
, 1);
17206 else if (offset
> 0)
17208 /* Short opcode. */
17209 op
= (offset
- 4) >> 2;
17210 add_unwind_opcode (op
, 1);
17212 else if (offset
< 0)
17215 while (offset
> 0x100)
17217 add_unwind_opcode (0x7f, 1);
17220 op
= ((offset
- 4) >> 2) | 0x40;
17221 add_unwind_opcode (op
, 1);
17225 /* Finish the list of unwind opcodes for this function. */
17227 finish_unwind_opcodes (void)
17231 if (unwind
.fp_used
)
17233 /* Adjust sp as necessary. */
17234 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17235 flush_pending_unwind ();
17237 /* After restoring sp from the frame pointer. */
17238 op
= 0x90 | unwind
.fp_reg
;
17239 add_unwind_opcode (op
, 1);
17242 flush_pending_unwind ();
17246 /* Start an exception table entry. If idx is nonzero this is an index table
17250 start_unwind_section (const segT text_seg
, int idx
)
17252 const char * text_name
;
17253 const char * prefix
;
17254 const char * prefix_once
;
17255 const char * group_name
;
17259 size_t sec_name_len
;
17266 prefix
= ELF_STRING_ARM_unwind
;
17267 prefix_once
= ELF_STRING_ARM_unwind_once
;
17268 type
= SHT_ARM_EXIDX
;
17272 prefix
= ELF_STRING_ARM_unwind_info
;
17273 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17274 type
= SHT_PROGBITS
;
17277 text_name
= segment_name (text_seg
);
17278 if (streq (text_name
, ".text"))
17281 if (strncmp (text_name
, ".gnu.linkonce.t.",
17282 strlen (".gnu.linkonce.t.")) == 0)
17284 prefix
= prefix_once
;
17285 text_name
+= strlen (".gnu.linkonce.t.");
17288 prefix_len
= strlen (prefix
);
17289 text_len
= strlen (text_name
);
17290 sec_name_len
= prefix_len
+ text_len
;
17291 sec_name
= xmalloc (sec_name_len
+ 1);
17292 memcpy (sec_name
, prefix
, prefix_len
);
17293 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17294 sec_name
[prefix_len
+ text_len
] = '\0';
17300 /* Handle COMDAT group. */
17301 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17303 group_name
= elf_group_name (text_seg
);
17304 if (group_name
== NULL
)
17306 as_bad (_("Group section `%s' has no group signature"),
17307 segment_name (text_seg
));
17308 ignore_rest_of_line ();
17311 flags
|= SHF_GROUP
;
17315 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17317 /* Set the section link for index tables. */
17319 elf_linked_to_section (now_seg
) = text_seg
;
17323 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17324 personality routine data. Returns zero, or the index table value for
17325 and inline entry. */
17328 create_unwind_entry (int have_data
)
17333 /* The current word of data. */
17335 /* The number of bytes left in this word. */
17338 finish_unwind_opcodes ();
17340 /* Remember the current text section. */
17341 unwind
.saved_seg
= now_seg
;
17342 unwind
.saved_subseg
= now_subseg
;
17344 start_unwind_section (now_seg
, 0);
17346 if (unwind
.personality_routine
== NULL
)
17348 if (unwind
.personality_index
== -2)
17351 as_bad (_("handlerdata in cantunwind frame"));
17352 return 1; /* EXIDX_CANTUNWIND. */
17355 /* Use a default personality routine if none is specified. */
17356 if (unwind
.personality_index
== -1)
17358 if (unwind
.opcode_count
> 3)
17359 unwind
.personality_index
= 1;
17361 unwind
.personality_index
= 0;
17364 /* Space for the personality routine entry. */
17365 if (unwind
.personality_index
== 0)
17367 if (unwind
.opcode_count
> 3)
17368 as_bad (_("too many unwind opcodes for personality routine 0"));
17372 /* All the data is inline in the index table. */
17375 while (unwind
.opcode_count
> 0)
17377 unwind
.opcode_count
--;
17378 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17382 /* Pad with "finish" opcodes. */
17384 data
= (data
<< 8) | 0xb0;
17391 /* We get two opcodes "free" in the first word. */
17392 size
= unwind
.opcode_count
- 2;
17395 /* An extra byte is required for the opcode count. */
17396 size
= unwind
.opcode_count
+ 1;
17398 size
= (size
+ 3) >> 2;
17400 as_bad (_("too many unwind opcodes"));
17402 frag_align (2, 0, 0);
17403 record_alignment (now_seg
, 2);
17404 unwind
.table_entry
= expr_build_dot ();
17406 /* Allocate the table entry. */
17407 ptr
= frag_more ((size
<< 2) + 4);
17408 where
= frag_now_fix () - ((size
<< 2) + 4);
17410 switch (unwind
.personality_index
)
17413 /* ??? Should this be a PLT generating relocation? */
17414 /* Custom personality routine. */
17415 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
17416 BFD_RELOC_ARM_PREL31
);
17421 /* Set the first byte to the number of additional words. */
17426 /* ABI defined personality routines. */
17428 /* Three opcodes bytes are packed into the first word. */
17435 /* The size and first two opcode bytes go in the first word. */
17436 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
17441 /* Should never happen. */
17445 /* Pack the opcodes into words (MSB first), reversing the list at the same
17447 while (unwind
.opcode_count
> 0)
17451 md_number_to_chars (ptr
, data
, 4);
17456 unwind
.opcode_count
--;
17458 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17461 /* Finish off the last word. */
17464 /* Pad with "finish" opcodes. */
17466 data
= (data
<< 8) | 0xb0;
17468 md_number_to_chars (ptr
, data
, 4);
17473 /* Add an empty descriptor if there is no user-specified data. */
17474 ptr
= frag_more (4);
17475 md_number_to_chars (ptr
, 0, 4);
17482 /* Initialize the DWARF-2 unwind information for this procedure. */
17485 tc_arm_frame_initial_instructions (void)
17487 cfi_add_CFA_def_cfa (REG_SP
, 0);
17489 #endif /* OBJ_ELF */
17491 /* Convert REGNAME to a DWARF-2 register number. */
17494 tc_arm_regname_to_dw2regnum (char *regname
)
17496 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
17506 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
17510 expr
.X_op
= O_secrel
;
17511 expr
.X_add_symbol
= symbol
;
17512 expr
.X_add_number
= 0;
17513 emit_expr (&expr
, size
);
17517 /* MD interface: Symbol and relocation handling. */
17519 /* Return the address within the segment that a PC-relative fixup is
17520 relative to. For ARM, PC-relative fixups applied to instructions
17521 are generally relative to the location of the fixup plus 8 bytes.
17522 Thumb branches are offset by 4, and Thumb loads relative to PC
17523 require special handling. */
17526 md_pcrel_from_section (fixS
* fixP
, segT seg
)
17528 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
17530 /* If this is pc-relative and we are going to emit a relocation
17531 then we just want to put out any pipeline compensation that the linker
17532 will need. Otherwise we want to use the calculated base.
17533 For WinCE we skip the bias for externals as well, since this
17534 is how the MS ARM-CE assembler behaves and we want to be compatible. */
17536 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
17537 || (arm_force_relocation (fixP
)
17539 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17544 switch (fixP
->fx_r_type
)
17546 /* PC relative addressing on the Thumb is slightly odd as the
17547 bottom two bits of the PC are forced to zero for the
17548 calculation. This happens *after* application of the
17549 pipeline offset. However, Thumb adrl already adjusts for
17550 this, so we need not do it again. */
17551 case BFD_RELOC_ARM_THUMB_ADD
:
17554 case BFD_RELOC_ARM_THUMB_OFFSET
:
17555 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17556 case BFD_RELOC_ARM_T32_ADD_PC12
:
17557 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17558 return (base
+ 4) & ~3;
17560 /* Thumb branches are simply offset by +4. */
17561 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17562 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17563 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17564 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17565 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17566 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17567 case BFD_RELOC_THUMB_PCREL_BLX
:
17570 /* ARM mode branches are offset by +8. However, the Windows CE
17571 loader expects the relocation not to take this into account. */
17572 case BFD_RELOC_ARM_PCREL_BRANCH
:
17573 case BFD_RELOC_ARM_PCREL_CALL
:
17574 case BFD_RELOC_ARM_PCREL_JUMP
:
17575 case BFD_RELOC_ARM_PCREL_BLX
:
17576 case BFD_RELOC_ARM_PLT32
:
17578 /* When handling fixups immediately, because we have already
17579 discovered the value of a symbol, or the address of the frag involved
17580 we must account for the offset by +8, as the OS loader will never see the reloc.
17581 see fixup_segment() in write.c
17582 The S_IS_EXTERNAL test handles the case of global symbols.
17583 Those need the calculated base, not just the pipe compensation the linker will need. */
17585 && fixP
->fx_addsy
!= NULL
17586 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17587 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17594 /* ARM mode loads relative to PC are also offset by +8. Unlike
17595 branches, the Windows CE loader *does* expect the relocation
17596 to take this into account. */
17597 case BFD_RELOC_ARM_OFFSET_IMM
:
17598 case BFD_RELOC_ARM_OFFSET_IMM8
:
17599 case BFD_RELOC_ARM_HWLITERAL
:
17600 case BFD_RELOC_ARM_LITERAL
:
17601 case BFD_RELOC_ARM_CP_OFF_IMM
:
17605 /* Other PC-relative relocations are un-offset. */
17611 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17612 Otherwise we have no need to default values of symbols. */
17615 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17618 if (name
[0] == '_' && name
[1] == 'G'
17619 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17623 if (symbol_find (name
))
17624 as_bad (_("GOT already in the symbol table"));
17626 GOT_symbol
= symbol_new (name
, undefined_section
,
17627 (valueT
) 0, & zero_address_frag
);
17637 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17638 computed as two separate immediate values, added together. We
17639 already know that this value cannot be computed by just one ARM
17642 static unsigned int
17643 validate_immediate_twopart (unsigned int val
,
17644 unsigned int * highpart
)
17649 for (i
= 0; i
< 32; i
+= 2)
17650 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17656 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17658 else if (a
& 0xff0000)
17660 if (a
& 0xff000000)
17662 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17666 assert (a
& 0xff000000);
17667 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17670 return (a
& 0xff) | (i
<< 7);
17677 validate_offset_imm (unsigned int val
, int hwse
)
17679 if ((hwse
&& val
> 255) || val
> 4095)
17684 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17685 negative immediate constant by altering the instruction. A bit of
17690 by inverting the second operand, and
17693 by negating the second operand. */
17696 negate_data_op (unsigned long * instruction
,
17697 unsigned long value
)
17700 unsigned long negated
, inverted
;
17702 negated
= encode_arm_immediate (-value
);
17703 inverted
= encode_arm_immediate (~value
);
17705 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17708 /* First negates. */
17709 case OPCODE_SUB
: /* ADD <-> SUB */
17710 new_inst
= OPCODE_ADD
;
17715 new_inst
= OPCODE_SUB
;
17719 case OPCODE_CMP
: /* CMP <-> CMN */
17720 new_inst
= OPCODE_CMN
;
17725 new_inst
= OPCODE_CMP
;
17729 /* Now Inverted ops. */
17730 case OPCODE_MOV
: /* MOV <-> MVN */
17731 new_inst
= OPCODE_MVN
;
17736 new_inst
= OPCODE_MOV
;
17740 case OPCODE_AND
: /* AND <-> BIC */
17741 new_inst
= OPCODE_BIC
;
17746 new_inst
= OPCODE_AND
;
17750 case OPCODE_ADC
: /* ADC <-> SBC */
17751 new_inst
= OPCODE_SBC
;
17756 new_inst
= OPCODE_ADC
;
17760 /* We cannot do anything. */
17765 if (value
== (unsigned) FAIL
)
17768 *instruction
&= OPCODE_MASK
;
17769 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17773 /* Like negate_data_op, but for Thumb-2. */
17775 static unsigned int
17776 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
17780 unsigned int negated
, inverted
;
17782 negated
= encode_thumb32_immediate (-value
);
17783 inverted
= encode_thumb32_immediate (~value
);
17785 rd
= (*instruction
>> 8) & 0xf;
17786 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17789 /* ADD <-> SUB. Includes CMP <-> CMN. */
17790 case T2_OPCODE_SUB
:
17791 new_inst
= T2_OPCODE_ADD
;
17795 case T2_OPCODE_ADD
:
17796 new_inst
= T2_OPCODE_SUB
;
17800 /* ORR <-> ORN. Includes MOV <-> MVN. */
17801 case T2_OPCODE_ORR
:
17802 new_inst
= T2_OPCODE_ORN
;
17806 case T2_OPCODE_ORN
:
17807 new_inst
= T2_OPCODE_ORR
;
17811 /* AND <-> BIC. TST has no inverted equivalent. */
17812 case T2_OPCODE_AND
:
17813 new_inst
= T2_OPCODE_BIC
;
17820 case T2_OPCODE_BIC
:
17821 new_inst
= T2_OPCODE_AND
;
17826 case T2_OPCODE_ADC
:
17827 new_inst
= T2_OPCODE_SBC
;
17831 case T2_OPCODE_SBC
:
17832 new_inst
= T2_OPCODE_ADC
;
17836 /* We cannot do anything. */
17841 if (value
== (unsigned int)FAIL
)
17844 *instruction
&= T2_OPCODE_MASK
;
17845 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17849 /* Read a 32-bit thumb instruction from buf. */
17850 static unsigned long
17851 get_thumb32_insn (char * buf
)
17853 unsigned long insn
;
17854 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17855 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17861 /* We usually want to set the low bit on the address of thumb function
17862 symbols. In particular .word foo - . should have the low bit set.
17863 Generic code tries to fold the difference of two symbols to
17864 a constant. Prevent this and force a relocation when the first symbols
17865 is a thumb function. */
17867 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17869 if (op
== O_subtract
17870 && l
->X_op
== O_symbol
17871 && r
->X_op
== O_symbol
17872 && THUMB_IS_FUNC (l
->X_add_symbol
))
17874 l
->X_op
= O_subtract
;
17875 l
->X_op_symbol
= r
->X_add_symbol
;
17876 l
->X_add_number
-= r
->X_add_number
;
17879 /* Process as normal. */
17884 md_apply_fix (fixS
* fixP
,
17888 offsetT value
= * valP
;
17890 unsigned int newimm
;
17891 unsigned long temp
;
17893 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17895 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17897 /* Note whether this will delete the relocation. */
17899 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17902 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17903 consistency with the behaviour on 32-bit hosts. Remember value
17905 value
&= 0xffffffff;
17906 value
^= 0x80000000;
17907 value
-= 0x80000000;
17910 fixP
->fx_addnumber
= value
;
17912 /* Same treatment for fixP->fx_offset. */
17913 fixP
->fx_offset
&= 0xffffffff;
17914 fixP
->fx_offset
^= 0x80000000;
17915 fixP
->fx_offset
-= 0x80000000;
17917 switch (fixP
->fx_r_type
)
17919 case BFD_RELOC_NONE
:
17920 /* This will need to go in the object file. */
17924 case BFD_RELOC_ARM_IMMEDIATE
:
17925 /* We claim that this fixup has been processed here,
17926 even if in fact we generate an error because we do
17927 not have a reloc for it, so tc_gen_reloc will reject it. */
17931 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17934 _("undefined symbol %s used as an immediate value"),
17935 S_GET_NAME (fixP
->fx_addsy
));
17939 newimm
= encode_arm_immediate (value
);
17940 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17942 /* If the instruction will fail, see if we can fix things up by
17943 changing the opcode. */
17944 if (newimm
== (unsigned int) FAIL
17945 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17948 _("invalid constant (%lx) after fixup"),
17949 (unsigned long) value
);
17953 newimm
|= (temp
& 0xfffff000);
17954 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17957 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17959 unsigned int highpart
= 0;
17960 unsigned int newinsn
= 0xe1a00000; /* nop. */
17962 newimm
= encode_arm_immediate (value
);
17963 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17965 /* If the instruction will fail, see if we can fix things up by
17966 changing the opcode. */
17967 if (newimm
== (unsigned int) FAIL
17968 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17970 /* No ? OK - try using two ADD instructions to generate
17972 newimm
= validate_immediate_twopart (value
, & highpart
);
17974 /* Yes - then make sure that the second instruction is
17976 if (newimm
!= (unsigned int) FAIL
)
17978 /* Still No ? Try using a negated value. */
17979 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17980 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17981 /* Otherwise - give up. */
17984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17985 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17990 /* Replace the first operand in the 2nd instruction (which
17991 is the PC) with the destination register. We have
17992 already added in the PC in the first instruction and we
17993 do not want to do it again. */
17994 newinsn
&= ~ 0xf0000;
17995 newinsn
|= ((newinsn
& 0x0f000) << 4);
17998 newimm
|= (temp
& 0xfffff000);
17999 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18001 highpart
|= (newinsn
& 0xfffff000);
18002 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18006 case BFD_RELOC_ARM_OFFSET_IMM
:
18007 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18010 case BFD_RELOC_ARM_LITERAL
:
18016 if (validate_offset_imm (value
, 0) == FAIL
)
18018 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18020 _("invalid literal constant: pool needs to be closer"));
18022 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18023 _("bad immediate value for offset (%ld)"),
18028 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18029 newval
&= 0xff7ff000;
18030 newval
|= value
| (sign
? INDEX_UP
: 0);
18031 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18034 case BFD_RELOC_ARM_OFFSET_IMM8
:
18035 case BFD_RELOC_ARM_HWLITERAL
:
18041 if (validate_offset_imm (value
, 1) == FAIL
)
18043 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18045 _("invalid literal constant: pool needs to be closer"));
18047 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18052 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18053 newval
&= 0xff7ff0f0;
18054 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18055 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18058 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18059 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18060 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18061 _("bad immediate value for offset (%ld)"), (long) value
);
18064 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18066 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18069 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18070 /* This is a complicated relocation used for all varieties of Thumb32
18071 load/store instruction with immediate offset:
18073 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18074 *4, optional writeback(W)
18075 (doubleword load/store)
18077 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18078 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18079 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18080 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18081 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18083 Uppercase letters indicate bits that are already encoded at
18084 this point. Lowercase letters are our problem. For the
18085 second block of instructions, the secondary opcode nybble
18086 (bits 8..11) is present, and bit 23 is zero, even if this is
18087 a PC-relative operation. */
18088 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18090 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18092 if ((newval
& 0xf0000000) == 0xe0000000)
18094 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18096 newval
|= (1 << 23);
18099 if (value
% 4 != 0)
18101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18102 _("offset not a multiple of 4"));
18108 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18109 _("offset out of range"));
18114 else if ((newval
& 0x000f0000) == 0x000f0000)
18116 /* PC-relative, 12-bit offset. */
18118 newval
|= (1 << 23);
18123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18124 _("offset out of range"));
18129 else if ((newval
& 0x00000100) == 0x00000100)
18131 /* Writeback: 8-bit, +/- offset. */
18133 newval
|= (1 << 9);
18138 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18139 _("offset out of range"));
18144 else if ((newval
& 0x00000f00) == 0x00000e00)
18146 /* T-instruction: positive 8-bit offset. */
18147 if (value
< 0 || value
> 0xff)
18149 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18150 _("offset out of range"));
18158 /* Positive 12-bit or negative 8-bit offset. */
18162 newval
|= (1 << 23);
18172 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18173 _("offset out of range"));
18180 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18181 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18184 case BFD_RELOC_ARM_SHIFT_IMM
:
18185 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18186 if (((unsigned long) value
) > 32
18188 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18191 _("shift expression is too large"));
18196 /* Shifts of zero must be done as lsl. */
18198 else if (value
== 32)
18200 newval
&= 0xfffff07f;
18201 newval
|= (value
& 0x1f) << 7;
18202 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18205 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18206 case BFD_RELOC_ARM_T32_ADD_IMM
:
18207 case BFD_RELOC_ARM_T32_IMM12
:
18208 case BFD_RELOC_ARM_T32_ADD_PC12
:
18209 /* We claim that this fixup has been processed here,
18210 even if in fact we generate an error because we do
18211 not have a reloc for it, so tc_gen_reloc will reject it. */
18215 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18218 _("undefined symbol %s used as an immediate value"),
18219 S_GET_NAME (fixP
->fx_addsy
));
18223 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18225 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18228 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18229 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18231 newimm
= encode_thumb32_immediate (value
);
18232 if (newimm
== (unsigned int) FAIL
)
18233 newimm
= thumb32_negate_data_op (&newval
, value
);
18235 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18236 && newimm
== (unsigned int) FAIL
)
18238 /* Turn add/sum into addw/subw. */
18239 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18240 newval
= (newval
& 0xfeffffff) | 0x02000000;
18242 /* 12 bit immediate for addw/subw. */
18246 newval
^= 0x00a00000;
18249 newimm
= (unsigned int) FAIL
;
18254 if (newimm
== (unsigned int)FAIL
)
18256 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18257 _("invalid constant (%lx) after fixup"),
18258 (unsigned long) value
);
18262 newval
|= (newimm
& 0x800) << 15;
18263 newval
|= (newimm
& 0x700) << 4;
18264 newval
|= (newimm
& 0x0ff);
18266 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18267 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18270 case BFD_RELOC_ARM_SMC
:
18271 if (((unsigned long) value
) > 0xffff)
18272 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18273 _("invalid smc expression"));
18274 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18275 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18276 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18279 case BFD_RELOC_ARM_SWI
:
18280 if (fixP
->tc_fix_data
!= 0)
18282 if (((unsigned long) value
) > 0xff)
18283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18284 _("invalid swi expression"));
18285 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18287 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18291 if (((unsigned long) value
) > 0x00ffffff)
18292 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18293 _("invalid swi expression"));
18294 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18296 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18300 case BFD_RELOC_ARM_MULTI
:
18301 if (((unsigned long) value
) > 0xffff)
18302 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18303 _("invalid expression in load/store multiple"));
18304 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18305 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18309 case BFD_RELOC_ARM_PCREL_CALL
:
18310 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18311 if ((newval
& 0xf0000000) == 0xf0000000)
18315 goto arm_branch_common
;
18317 case BFD_RELOC_ARM_PCREL_JUMP
:
18318 case BFD_RELOC_ARM_PLT32
:
18320 case BFD_RELOC_ARM_PCREL_BRANCH
:
18322 goto arm_branch_common
;
18324 case BFD_RELOC_ARM_PCREL_BLX
:
18327 /* We are going to store value (shifted right by two) in the
18328 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18329 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18330 also be be clear. */
18332 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18333 _("misaligned branch destination"));
18334 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18335 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18337 _("branch out of range"));
18339 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18341 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18342 newval
|= (value
>> 2) & 0x00ffffff;
18343 /* Set the H bit on BLX instructions. */
18347 newval
|= 0x01000000;
18349 newval
&= ~0x01000000;
18351 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18355 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18356 /* CBZ can only branch forward. */
18358 /* Attempts to use CBZ to branch to the next instruction
18359 (which, strictly speaking, are prohibited) will be turned into
18362 FIXME: It may be better to remove the instruction completely and
18363 perform relaxation. */
18366 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18367 newval
= 0xbf00; /* NOP encoding T1 */
18368 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18373 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18374 _("branch out of range"));
18376 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18378 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18379 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
18380 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18385 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
18386 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
18387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18388 _("branch out of range"));
18390 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18392 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18393 newval
|= (value
& 0x1ff) >> 1;
18394 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18398 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
18399 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
18400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18401 _("branch out of range"));
18403 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18405 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18406 newval
|= (value
& 0xfff) >> 1;
18407 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18411 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18412 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
18413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18414 _("conditional branch out of range"));
18416 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18419 addressT S
, J1
, J2
, lo
, hi
;
18421 S
= (value
& 0x00100000) >> 20;
18422 J2
= (value
& 0x00080000) >> 19;
18423 J1
= (value
& 0x00040000) >> 18;
18424 hi
= (value
& 0x0003f000) >> 12;
18425 lo
= (value
& 0x00000ffe) >> 1;
18427 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18428 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18429 newval
|= (S
<< 10) | hi
;
18430 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
18431 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18432 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18436 case BFD_RELOC_THUMB_PCREL_BLX
:
18437 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18438 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
18439 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18440 _("branch out of range"));
18442 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
18443 /* For a BLX instruction, make sure that the relocation is rounded up
18444 to a word boundary. This follows the semantics of the instruction
18445 which specifies that bit 1 of the target address will come from bit
18446 1 of the base address. */
18447 value
= (value
+ 1) & ~ 1;
18449 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18453 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18454 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18455 newval
|= (value
& 0x7fffff) >> 12;
18456 newval2
|= (value
& 0xfff) >> 1;
18457 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18458 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18462 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18463 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
18464 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18465 _("branch out of range"));
18467 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18470 addressT S
, I1
, I2
, lo
, hi
;
18472 S
= (value
& 0x01000000) >> 24;
18473 I1
= (value
& 0x00800000) >> 23;
18474 I2
= (value
& 0x00400000) >> 22;
18475 hi
= (value
& 0x003ff000) >> 12;
18476 lo
= (value
& 0x00000ffe) >> 1;
18481 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18482 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18483 newval
|= (S
<< 10) | hi
;
18484 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
18485 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18486 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
18491 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18492 md_number_to_chars (buf
, value
, 1);
18496 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18497 md_number_to_chars (buf
, value
, 2);
18501 case BFD_RELOC_ARM_TLS_GD32
:
18502 case BFD_RELOC_ARM_TLS_LE32
:
18503 case BFD_RELOC_ARM_TLS_IE32
:
18504 case BFD_RELOC_ARM_TLS_LDM32
:
18505 case BFD_RELOC_ARM_TLS_LDO32
:
18506 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
18509 case BFD_RELOC_ARM_GOT32
:
18510 case BFD_RELOC_ARM_GOTOFF
:
18511 case BFD_RELOC_ARM_TARGET2
:
18512 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18513 md_number_to_chars (buf
, 0, 4);
18517 case BFD_RELOC_RVA
:
18519 case BFD_RELOC_ARM_TARGET1
:
18520 case BFD_RELOC_ARM_ROSEGREL32
:
18521 case BFD_RELOC_ARM_SBREL32
:
18522 case BFD_RELOC_32_PCREL
:
18524 case BFD_RELOC_32_SECREL
:
18526 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18528 /* For WinCE we only do this for pcrel fixups. */
18529 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
18531 md_number_to_chars (buf
, value
, 4);
18535 case BFD_RELOC_ARM_PREL31
:
18536 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18538 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
18539 if ((value
^ (value
>> 1)) & 0x40000000)
18541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18542 _("rel31 relocation overflow"));
18544 newval
|= value
& 0x7fffffff;
18545 md_number_to_chars (buf
, newval
, 4);
18550 case BFD_RELOC_ARM_CP_OFF_IMM
:
18551 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18552 if (value
< -1023 || value
> 1023 || (value
& 3))
18553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18554 _("co-processor offset out of range"));
18559 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18560 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18561 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18563 newval
= get_thumb32_insn (buf
);
18564 newval
&= 0xff7fff00;
18565 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18566 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18567 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18568 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18570 put_thumb32_insn (buf
, newval
);
18573 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18574 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18575 if (value
< -255 || value
> 255)
18576 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18577 _("co-processor offset out of range"));
18579 goto cp_off_common
;
18581 case BFD_RELOC_ARM_THUMB_OFFSET
:
18582 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18583 /* Exactly what ranges, and where the offset is inserted depends
18584 on the type of instruction, we can establish this from the
18586 switch (newval
>> 12)
18588 case 4: /* PC load. */
18589 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18590 forced to zero for these loads; md_pcrel_from has already
18591 compensated for this. */
18593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18594 _("invalid offset, target not word aligned (0x%08lX)"),
18595 (((unsigned long) fixP
->fx_frag
->fr_address
18596 + (unsigned long) fixP
->fx_where
) & ~3)
18597 + (unsigned long) value
);
18599 if (value
& ~0x3fc)
18600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18601 _("invalid offset, value too big (0x%08lX)"),
18604 newval
|= value
>> 2;
18607 case 9: /* SP load/store. */
18608 if (value
& ~0x3fc)
18609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18610 _("invalid offset, value too big (0x%08lX)"),
18612 newval
|= value
>> 2;
18615 case 6: /* Word load/store. */
18617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18618 _("invalid offset, value too big (0x%08lX)"),
18620 newval
|= value
<< 4; /* 6 - 2. */
18623 case 7: /* Byte load/store. */
18625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18626 _("invalid offset, value too big (0x%08lX)"),
18628 newval
|= value
<< 6;
18631 case 8: /* Halfword load/store. */
18633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18634 _("invalid offset, value too big (0x%08lX)"),
18636 newval
|= value
<< 5; /* 6 - 1. */
18640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18641 "Unable to process relocation for thumb opcode: %lx",
18642 (unsigned long) newval
);
18645 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18648 case BFD_RELOC_ARM_THUMB_ADD
:
18649 /* This is a complicated relocation, since we use it for all of
18650 the following immediate relocations:
18654 9bit ADD/SUB SP word-aligned
18655 10bit ADD PC/SP word-aligned
18657 The type of instruction being processed is encoded in the
18664 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18666 int rd
= (newval
>> 4) & 0xf;
18667 int rs
= newval
& 0xf;
18668 int subtract
= !!(newval
& 0x8000);
18670 /* Check for HI regs, only very restricted cases allowed:
18671 Adjusting SP, and using PC or SP to get an address. */
18672 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18673 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18675 _("invalid Hi register with immediate"));
18677 /* If value is negative, choose the opposite instruction. */
18681 subtract
= !subtract
;
18683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18684 _("immediate value out of range"));
18689 if (value
& ~0x1fc)
18690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18691 _("invalid immediate for stack address calculation"));
18692 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18693 newval
|= value
>> 2;
18695 else if (rs
== REG_PC
|| rs
== REG_SP
)
18697 if (subtract
|| value
& ~0x3fc)
18698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18699 _("invalid immediate for address calculation (value = 0x%08lX)"),
18700 (unsigned long) value
);
18701 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18703 newval
|= value
>> 2;
18708 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18709 _("immediate value out of range"));
18710 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18711 newval
|= (rd
<< 8) | value
;
18716 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18717 _("immediate value out of range"));
18718 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18719 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18722 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18725 case BFD_RELOC_ARM_THUMB_IMM
:
18726 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18727 if (value
< 0 || value
> 255)
18728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18729 _("invalid immediate: %ld is out of range"),
18732 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18735 case BFD_RELOC_ARM_THUMB_SHIFT
:
18736 /* 5bit shift value (0..32). LSL cannot take 32. */
18737 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18738 temp
= newval
& 0xf800;
18739 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18740 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18741 _("invalid shift value: %ld"), (long) value
);
18742 /* Shifts of zero must be encoded as LSL. */
18744 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18745 /* Shifts of 32 are encoded as zero. */
18746 else if (value
== 32)
18748 newval
|= value
<< 6;
18749 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18752 case BFD_RELOC_VTABLE_INHERIT
:
18753 case BFD_RELOC_VTABLE_ENTRY
:
18757 case BFD_RELOC_ARM_MOVW
:
18758 case BFD_RELOC_ARM_MOVT
:
18759 case BFD_RELOC_ARM_THUMB_MOVW
:
18760 case BFD_RELOC_ARM_THUMB_MOVT
:
18761 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18763 /* REL format relocations are limited to a 16-bit addend. */
18764 if (!fixP
->fx_done
)
18766 if (value
< -0x1000 || value
> 0xffff)
18767 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18768 _("offset out of range"));
18770 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18771 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18776 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18777 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18779 newval
= get_thumb32_insn (buf
);
18780 newval
&= 0xfbf08f00;
18781 newval
|= (value
& 0xf000) << 4;
18782 newval
|= (value
& 0x0800) << 15;
18783 newval
|= (value
& 0x0700) << 4;
18784 newval
|= (value
& 0x00ff);
18785 put_thumb32_insn (buf
, newval
);
18789 newval
= md_chars_to_number (buf
, 4);
18790 newval
&= 0xfff0f000;
18791 newval
|= value
& 0x0fff;
18792 newval
|= (value
& 0xf000) << 4;
18793 md_number_to_chars (buf
, newval
, 4);
18798 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18799 case BFD_RELOC_ARM_ALU_PC_G0
:
18800 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18801 case BFD_RELOC_ARM_ALU_PC_G1
:
18802 case BFD_RELOC_ARM_ALU_PC_G2
:
18803 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18804 case BFD_RELOC_ARM_ALU_SB_G0
:
18805 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18806 case BFD_RELOC_ARM_ALU_SB_G1
:
18807 case BFD_RELOC_ARM_ALU_SB_G2
:
18808 assert (!fixP
->fx_done
);
18809 if (!seg
->use_rela_p
)
18812 bfd_vma encoded_addend
;
18813 bfd_vma addend_abs
= abs (value
);
18815 /* Check that the absolute value of the addend can be
18816 expressed as an 8-bit constant plus a rotation. */
18817 encoded_addend
= encode_arm_immediate (addend_abs
);
18818 if (encoded_addend
== (unsigned int) FAIL
)
18819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18820 _("the offset 0x%08lX is not representable"),
18821 (unsigned long) addend_abs
);
18823 /* Extract the instruction. */
18824 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18826 /* If the addend is positive, use an ADD instruction.
18827 Otherwise use a SUB. Take care not to destroy the S bit. */
18828 insn
&= 0xff1fffff;
18834 /* Place the encoded addend into the first 12 bits of the
18836 insn
&= 0xfffff000;
18837 insn
|= encoded_addend
;
18839 /* Update the instruction. */
18840 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18844 case BFD_RELOC_ARM_LDR_PC_G0
:
18845 case BFD_RELOC_ARM_LDR_PC_G1
:
18846 case BFD_RELOC_ARM_LDR_PC_G2
:
18847 case BFD_RELOC_ARM_LDR_SB_G0
:
18848 case BFD_RELOC_ARM_LDR_SB_G1
:
18849 case BFD_RELOC_ARM_LDR_SB_G2
:
18850 assert (!fixP
->fx_done
);
18851 if (!seg
->use_rela_p
)
18854 bfd_vma addend_abs
= abs (value
);
18856 /* Check that the absolute value of the addend can be
18857 encoded in 12 bits. */
18858 if (addend_abs
>= 0x1000)
18859 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18860 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18861 (unsigned long) addend_abs
);
18863 /* Extract the instruction. */
18864 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18866 /* If the addend is negative, clear bit 23 of the instruction.
18867 Otherwise set it. */
18869 insn
&= ~(1 << 23);
18873 /* Place the absolute value of the addend into the first 12 bits
18874 of the instruction. */
18875 insn
&= 0xfffff000;
18876 insn
|= addend_abs
;
18878 /* Update the instruction. */
18879 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18883 case BFD_RELOC_ARM_LDRS_PC_G0
:
18884 case BFD_RELOC_ARM_LDRS_PC_G1
:
18885 case BFD_RELOC_ARM_LDRS_PC_G2
:
18886 case BFD_RELOC_ARM_LDRS_SB_G0
:
18887 case BFD_RELOC_ARM_LDRS_SB_G1
:
18888 case BFD_RELOC_ARM_LDRS_SB_G2
:
18889 assert (!fixP
->fx_done
);
18890 if (!seg
->use_rela_p
)
18893 bfd_vma addend_abs
= abs (value
);
18895 /* Check that the absolute value of the addend can be
18896 encoded in 8 bits. */
18897 if (addend_abs
>= 0x100)
18898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18899 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18900 (unsigned long) addend_abs
);
18902 /* Extract the instruction. */
18903 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18905 /* If the addend is negative, clear bit 23 of the instruction.
18906 Otherwise set it. */
18908 insn
&= ~(1 << 23);
18912 /* Place the first four bits of the absolute value of the addend
18913 into the first 4 bits of the instruction, and the remaining
18914 four into bits 8 .. 11. */
18915 insn
&= 0xfffff0f0;
18916 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18918 /* Update the instruction. */
18919 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18923 case BFD_RELOC_ARM_LDC_PC_G0
:
18924 case BFD_RELOC_ARM_LDC_PC_G1
:
18925 case BFD_RELOC_ARM_LDC_PC_G2
:
18926 case BFD_RELOC_ARM_LDC_SB_G0
:
18927 case BFD_RELOC_ARM_LDC_SB_G1
:
18928 case BFD_RELOC_ARM_LDC_SB_G2
:
18929 assert (!fixP
->fx_done
);
18930 if (!seg
->use_rela_p
)
18933 bfd_vma addend_abs
= abs (value
);
18935 /* Check that the absolute value of the addend is a multiple of
18936 four and, when divided by four, fits in 8 bits. */
18937 if (addend_abs
& 0x3)
18938 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18939 _("bad offset 0x%08lX (must be word-aligned)"),
18940 (unsigned long) addend_abs
);
18942 if ((addend_abs
>> 2) > 0xff)
18943 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18944 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18945 (unsigned long) addend_abs
);
18947 /* Extract the instruction. */
18948 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18950 /* If the addend is negative, clear bit 23 of the instruction.
18951 Otherwise set it. */
18953 insn
&= ~(1 << 23);
18957 /* Place the addend (divided by four) into the first eight
18958 bits of the instruction. */
18959 insn
&= 0xfffffff0;
18960 insn
|= addend_abs
>> 2;
18962 /* Update the instruction. */
18963 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18967 case BFD_RELOC_UNUSED
:
18969 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18970 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18974 /* Translate internal representation of relocation info to BFD target
18978 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18981 bfd_reloc_code_real_type code
;
18983 reloc
= xmalloc (sizeof (arelent
));
18985 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18986 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18987 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18989 if (fixp
->fx_pcrel
)
18991 if (section
->use_rela_p
)
18992 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18994 fixp
->fx_offset
= reloc
->address
;
18996 reloc
->addend
= fixp
->fx_offset
;
18998 switch (fixp
->fx_r_type
)
19001 if (fixp
->fx_pcrel
)
19003 code
= BFD_RELOC_8_PCREL
;
19008 if (fixp
->fx_pcrel
)
19010 code
= BFD_RELOC_16_PCREL
;
19015 if (fixp
->fx_pcrel
)
19017 code
= BFD_RELOC_32_PCREL
;
19021 case BFD_RELOC_ARM_MOVW
:
19022 if (fixp
->fx_pcrel
)
19024 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19028 case BFD_RELOC_ARM_MOVT
:
19029 if (fixp
->fx_pcrel
)
19031 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19035 case BFD_RELOC_ARM_THUMB_MOVW
:
19036 if (fixp
->fx_pcrel
)
19038 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19042 case BFD_RELOC_ARM_THUMB_MOVT
:
19043 if (fixp
->fx_pcrel
)
19045 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19049 case BFD_RELOC_NONE
:
19050 case BFD_RELOC_ARM_PCREL_BRANCH
:
19051 case BFD_RELOC_ARM_PCREL_BLX
:
19052 case BFD_RELOC_RVA
:
19053 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19054 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19055 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19056 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19057 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19058 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19059 case BFD_RELOC_THUMB_PCREL_BLX
:
19060 case BFD_RELOC_VTABLE_ENTRY
:
19061 case BFD_RELOC_VTABLE_INHERIT
:
19063 case BFD_RELOC_32_SECREL
:
19065 code
= fixp
->fx_r_type
;
19068 case BFD_RELOC_ARM_LITERAL
:
19069 case BFD_RELOC_ARM_HWLITERAL
:
19070 /* If this is called then the a literal has
19071 been referenced across a section boundary. */
19072 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19073 _("literal referenced across section boundary"));
19077 case BFD_RELOC_ARM_GOT32
:
19078 case BFD_RELOC_ARM_GOTOFF
:
19079 case BFD_RELOC_ARM_PLT32
:
19080 case BFD_RELOC_ARM_TARGET1
:
19081 case BFD_RELOC_ARM_ROSEGREL32
:
19082 case BFD_RELOC_ARM_SBREL32
:
19083 case BFD_RELOC_ARM_PREL31
:
19084 case BFD_RELOC_ARM_TARGET2
:
19085 case BFD_RELOC_ARM_TLS_LE32
:
19086 case BFD_RELOC_ARM_TLS_LDO32
:
19087 case BFD_RELOC_ARM_PCREL_CALL
:
19088 case BFD_RELOC_ARM_PCREL_JUMP
:
19089 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19090 case BFD_RELOC_ARM_ALU_PC_G0
:
19091 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19092 case BFD_RELOC_ARM_ALU_PC_G1
:
19093 case BFD_RELOC_ARM_ALU_PC_G2
:
19094 case BFD_RELOC_ARM_LDR_PC_G0
:
19095 case BFD_RELOC_ARM_LDR_PC_G1
:
19096 case BFD_RELOC_ARM_LDR_PC_G2
:
19097 case BFD_RELOC_ARM_LDRS_PC_G0
:
19098 case BFD_RELOC_ARM_LDRS_PC_G1
:
19099 case BFD_RELOC_ARM_LDRS_PC_G2
:
19100 case BFD_RELOC_ARM_LDC_PC_G0
:
19101 case BFD_RELOC_ARM_LDC_PC_G1
:
19102 case BFD_RELOC_ARM_LDC_PC_G2
:
19103 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19104 case BFD_RELOC_ARM_ALU_SB_G0
:
19105 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19106 case BFD_RELOC_ARM_ALU_SB_G1
:
19107 case BFD_RELOC_ARM_ALU_SB_G2
:
19108 case BFD_RELOC_ARM_LDR_SB_G0
:
19109 case BFD_RELOC_ARM_LDR_SB_G1
:
19110 case BFD_RELOC_ARM_LDR_SB_G2
:
19111 case BFD_RELOC_ARM_LDRS_SB_G0
:
19112 case BFD_RELOC_ARM_LDRS_SB_G1
:
19113 case BFD_RELOC_ARM_LDRS_SB_G2
:
19114 case BFD_RELOC_ARM_LDC_SB_G0
:
19115 case BFD_RELOC_ARM_LDC_SB_G1
:
19116 case BFD_RELOC_ARM_LDC_SB_G2
:
19117 code
= fixp
->fx_r_type
;
19120 case BFD_RELOC_ARM_TLS_GD32
:
19121 case BFD_RELOC_ARM_TLS_IE32
:
19122 case BFD_RELOC_ARM_TLS_LDM32
:
19123 /* BFD will include the symbol's address in the addend.
19124 But we don't want that, so subtract it out again here. */
19125 if (!S_IS_COMMON (fixp
->fx_addsy
))
19126 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19127 code
= fixp
->fx_r_type
;
19131 case BFD_RELOC_ARM_IMMEDIATE
:
19132 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19133 _("internal relocation (type: IMMEDIATE) not fixed up"));
19136 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19137 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19138 _("ADRL used for a symbol not defined in the same file"));
19141 case BFD_RELOC_ARM_OFFSET_IMM
:
19142 if (section
->use_rela_p
)
19144 code
= fixp
->fx_r_type
;
19148 if (fixp
->fx_addsy
!= NULL
19149 && !S_IS_DEFINED (fixp
->fx_addsy
)
19150 && S_IS_LOCAL (fixp
->fx_addsy
))
19152 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19153 _("undefined local label `%s'"),
19154 S_GET_NAME (fixp
->fx_addsy
));
19158 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19159 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19166 switch (fixp
->fx_r_type
)
19168 case BFD_RELOC_NONE
: type
= "NONE"; break;
19169 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19170 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19171 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19172 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19173 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19174 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19175 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19176 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19177 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19178 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19179 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19180 default: type
= _("<unknown>"); break;
19182 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19183 _("cannot represent %s relocation in this object file format"),
19190 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19192 && fixp
->fx_addsy
== GOT_symbol
)
19194 code
= BFD_RELOC_ARM_GOTPC
;
19195 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19199 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19201 if (reloc
->howto
== NULL
)
19203 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19204 _("cannot represent %s relocation in this object file format"),
19205 bfd_get_reloc_code_name (code
));
19209 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19210 vtable entry to be used in the relocation's section offset. */
19211 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19212 reloc
->address
= fixp
->fx_offset
;
19217 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19220 cons_fix_new_arm (fragS
* frag
,
19225 bfd_reloc_code_real_type type
;
19229 FIXME: @@ Should look at CPU word size. */
19233 type
= BFD_RELOC_8
;
19236 type
= BFD_RELOC_16
;
19240 type
= BFD_RELOC_32
;
19243 type
= BFD_RELOC_64
;
19248 if (exp
->X_op
== O_secrel
)
19250 exp
->X_op
= O_symbol
;
19251 type
= BFD_RELOC_32_SECREL
;
19255 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19258 #if defined OBJ_COFF || defined OBJ_ELF
19260 arm_validate_fix (fixS
* fixP
)
19262 /* If the destination of the branch is a defined symbol which does not have
19263 the THUMB_FUNC attribute, then we must be calling a function which has
19264 the (interfacearm) attribute. We look for the Thumb entry point to that
19265 function and change the branch to refer to that function instead. */
19266 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19267 && fixP
->fx_addsy
!= NULL
19268 && S_IS_DEFINED (fixP
->fx_addsy
)
19269 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19271 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19277 arm_force_relocation (struct fix
* fixp
)
19279 #if defined (OBJ_COFF) && defined (TE_PE)
19280 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19284 /* Resolve these relocations even if the symbol is extern or weak. */
19285 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19286 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19287 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19288 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19289 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19290 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19291 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19294 /* Always leave these relocations for the linker. */
19295 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19296 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19297 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19300 /* Always generate relocations against function symbols. */
19301 if (fixp
->fx_r_type
== BFD_RELOC_32
19303 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19306 return generic_force_reloc (fixp
);
19309 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19310 /* Relocations against function names must be left unadjusted,
19311 so that the linker can use this information to generate interworking
19312 stubs. The MIPS version of this function
19313 also prevents relocations that are mips-16 specific, but I do not
19314 know why it does this.
19317 There is one other problem that ought to be addressed here, but
19318 which currently is not: Taking the address of a label (rather
19319 than a function) and then later jumping to that address. Such
19320 addresses also ought to have their bottom bit set (assuming that
19321 they reside in Thumb code), but at the moment they will not. */
19324 arm_fix_adjustable (fixS
* fixP
)
19326 if (fixP
->fx_addsy
== NULL
)
19329 /* Preserve relocations against symbols with function type. */
19330 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19333 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19334 && fixP
->fx_subsy
== NULL
)
19337 /* We need the symbol name for the VTABLE entries. */
19338 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19339 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19342 /* Don't allow symbols to be discarded on GOT related relocs. */
19343 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19344 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19345 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19346 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19347 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19348 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19349 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19350 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19351 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19354 /* Similarly for group relocations. */
19355 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19356 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19357 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19362 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
19367 elf32_arm_target_format (void)
19370 return (target_big_endian
19371 ? "elf32-bigarm-symbian"
19372 : "elf32-littlearm-symbian");
19373 #elif defined (TE_VXWORKS)
19374 return (target_big_endian
19375 ? "elf32-bigarm-vxworks"
19376 : "elf32-littlearm-vxworks");
19378 if (target_big_endian
)
19379 return "elf32-bigarm";
19381 return "elf32-littlearm";
19386 armelf_frob_symbol (symbolS
* symp
,
19389 elf_frob_symbol (symp
, puntp
);
19393 /* MD interface: Finalization. */
19395 /* A good place to do this, although this was probably not intended
19396 for this kind of use. We need to dump the literal pool before
19397 references are made to a null symbol pointer. */
19402 literal_pool
* pool
;
19404 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
19406 /* Put it at the end of the relevant section. */
19407 subseg_set (pool
->section
, pool
->sub_section
);
19409 arm_elf_change_section ();
19415 /* Adjust the symbol table. This marks Thumb symbols as distinct from
19419 arm_adjust_symtab (void)
19424 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19426 if (ARM_IS_THUMB (sym
))
19428 if (THUMB_IS_FUNC (sym
))
19430 /* Mark the symbol as a Thumb function. */
19431 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
19432 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
19433 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
19435 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
19436 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
19438 as_bad (_("%s: unexpected function type: %d"),
19439 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
19441 else switch (S_GET_STORAGE_CLASS (sym
))
19444 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
19447 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
19450 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
19458 if (ARM_IS_INTERWORK (sym
))
19459 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
19466 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
19468 if (ARM_IS_THUMB (sym
))
19470 elf_symbol_type
* elf_sym
;
19472 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
19473 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
19475 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
19476 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
19478 /* If it's a .thumb_func, declare it as so,
19479 otherwise tag label as .code 16. */
19480 if (THUMB_IS_FUNC (sym
))
19481 elf_sym
->internal_elf_sym
.st_info
=
19482 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
19483 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
19484 elf_sym
->internal_elf_sym
.st_info
=
19485 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
19492 /* MD interface: Initialization. */
19495 set_constant_flonums (void)
19499 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
19500 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
19504 /* Auto-select Thumb mode if it's the only available instruction set for the
19505 given architecture. */
19508 autoselect_thumb_from_cpu_variant (void)
19510 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
19511 opcode_select (16);
19520 if ( (arm_ops_hsh
= hash_new ()) == NULL
19521 || (arm_cond_hsh
= hash_new ()) == NULL
19522 || (arm_shift_hsh
= hash_new ()) == NULL
19523 || (arm_psr_hsh
= hash_new ()) == NULL
19524 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
19525 || (arm_reg_hsh
= hash_new ()) == NULL
19526 || (arm_reloc_hsh
= hash_new ()) == NULL
19527 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
19528 as_fatal (_("virtual memory exhausted"));
19530 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
19531 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
19532 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
19533 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
19534 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
19535 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
19536 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
19537 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19538 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19539 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19540 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19541 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19543 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19545 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19546 (PTR
) (barrier_opt_names
+ i
));
19548 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19549 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19552 set_constant_flonums ();
19554 /* Set the cpu variant based on the command-line options. We prefer
19555 -mcpu= over -march= if both are set (as for GCC); and we prefer
19556 -mfpu= over any other way of setting the floating point unit.
19557 Use of legacy options with new options are faulted. */
19560 if (mcpu_cpu_opt
|| march_cpu_opt
)
19561 as_bad (_("use of old and new-style options to set CPU type"));
19563 mcpu_cpu_opt
= legacy_cpu
;
19565 else if (!mcpu_cpu_opt
)
19566 mcpu_cpu_opt
= march_cpu_opt
;
19571 as_bad (_("use of old and new-style options to set FPU type"));
19573 mfpu_opt
= legacy_fpu
;
19575 else if (!mfpu_opt
)
19577 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19578 /* Some environments specify a default FPU. If they don't, infer it
19579 from the processor. */
19581 mfpu_opt
= mcpu_fpu_opt
;
19583 mfpu_opt
= march_fpu_opt
;
19585 mfpu_opt
= &fpu_default
;
19591 if (mcpu_cpu_opt
!= NULL
)
19592 mfpu_opt
= &fpu_default
;
19593 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19594 mfpu_opt
= &fpu_arch_vfp_v2
;
19596 mfpu_opt
= &fpu_arch_fpa
;
19602 mcpu_cpu_opt
= &cpu_default
;
19603 selected_cpu
= cpu_default
;
19607 selected_cpu
= *mcpu_cpu_opt
;
19609 mcpu_cpu_opt
= &arm_arch_any
;
19612 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19614 autoselect_thumb_from_cpu_variant ();
19616 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19618 #if defined OBJ_COFF || defined OBJ_ELF
19620 unsigned int flags
= 0;
19622 #if defined OBJ_ELF
19623 flags
= meabi_flags
;
19625 switch (meabi_flags
)
19627 case EF_ARM_EABI_UNKNOWN
:
19629 /* Set the flags in the private structure. */
19630 if (uses_apcs_26
) flags
|= F_APCS26
;
19631 if (support_interwork
) flags
|= F_INTERWORK
;
19632 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19633 if (pic_code
) flags
|= F_PIC
;
19634 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19635 flags
|= F_SOFT_FLOAT
;
19637 switch (mfloat_abi_opt
)
19639 case ARM_FLOAT_ABI_SOFT
:
19640 case ARM_FLOAT_ABI_SOFTFP
:
19641 flags
|= F_SOFT_FLOAT
;
19644 case ARM_FLOAT_ABI_HARD
:
19645 if (flags
& F_SOFT_FLOAT
)
19646 as_bad (_("hard-float conflicts with specified fpu"));
19650 /* Using pure-endian doubles (even if soft-float). */
19651 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19652 flags
|= F_VFP_FLOAT
;
19654 #if defined OBJ_ELF
19655 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19656 flags
|= EF_ARM_MAVERICK_FLOAT
;
19659 case EF_ARM_EABI_VER4
:
19660 case EF_ARM_EABI_VER5
:
19661 /* No additional flags to set. */
19668 bfd_set_private_flags (stdoutput
, flags
);
19670 /* We have run out flags in the COFF header to encode the
19671 status of ATPCS support, so instead we create a dummy,
19672 empty, debug section called .arm.atpcs. */
19677 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19681 bfd_set_section_flags
19682 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19683 bfd_set_section_size (stdoutput
, sec
, 0);
19684 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19690 /* Record the CPU type as well. */
19691 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
19692 mach
= bfd_mach_arm_iWMMXt2
;
19693 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19694 mach
= bfd_mach_arm_iWMMXt
;
19695 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19696 mach
= bfd_mach_arm_XScale
;
19697 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19698 mach
= bfd_mach_arm_ep9312
;
19699 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19700 mach
= bfd_mach_arm_5TE
;
19701 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19703 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19704 mach
= bfd_mach_arm_5T
;
19706 mach
= bfd_mach_arm_5
;
19708 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19710 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19711 mach
= bfd_mach_arm_4T
;
19713 mach
= bfd_mach_arm_4
;
19715 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19716 mach
= bfd_mach_arm_3M
;
19717 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19718 mach
= bfd_mach_arm_3
;
19719 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19720 mach
= bfd_mach_arm_2a
;
19721 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19722 mach
= bfd_mach_arm_2
;
19724 mach
= bfd_mach_arm_unknown
;
19726 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19729 /* Command line processing. */
19732 Invocation line includes a switch not recognized by the base assembler.
19733 See if it's a processor-specific option.
19735 This routine is somewhat complicated by the need for backwards
19736 compatibility (since older releases of gcc can't be changed).
19737 The new options try to make the interface as compatible as
19740 New options (supported) are:
19742 -mcpu=<cpu name> Assemble for selected processor
19743 -march=<architecture name> Assemble for selected architecture
19744 -mfpu=<fpu architecture> Assemble for selected FPU.
19745 -EB/-mbig-endian Big-endian
19746 -EL/-mlittle-endian Little-endian
19747 -k Generate PIC code
19748 -mthumb Start in Thumb mode
19749 -mthumb-interwork Code supports ARM/Thumb interworking
19751 For now we will also provide support for:
19753 -mapcs-32 32-bit Program counter
19754 -mapcs-26 26-bit Program counter
19755 -macps-float Floats passed in FP registers
19756 -mapcs-reentrant Reentrant code
19758 (sometime these will probably be replaced with -mapcs=<list of options>
19759 and -matpcs=<list of options>)
19761 The remaining options are only supported for back-wards compatibility.
19762 Cpu variants, the arm part is optional:
19763 -m[arm]1 Currently not supported.
19764 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19765 -m[arm]3 Arm 3 processor
19766 -m[arm]6[xx], Arm 6 processors
19767 -m[arm]7[xx][t][[d]m] Arm 7 processors
19768 -m[arm]8[10] Arm 8 processors
19769 -m[arm]9[20][tdmi] Arm 9 processors
19770 -mstrongarm[110[0]] StrongARM processors
19771 -mxscale XScale processors
19772 -m[arm]v[2345[t[e]]] Arm architectures
19773 -mall All (except the ARM1)
19775 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19776 -mfpe-old (No float load/store multiples)
19777 -mvfpxd VFP Single precision
19779 -mno-fpu Disable all floating point instructions
19781 The following CPU names are recognized:
19782 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19783 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19784 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19785 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19786 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19787 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19788 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19792 const char * md_shortopts
= "m:k";
19794 #ifdef ARM_BI_ENDIAN
19795 #define OPTION_EB (OPTION_MD_BASE + 0)
19796 #define OPTION_EL (OPTION_MD_BASE + 1)
19798 #if TARGET_BYTES_BIG_ENDIAN
19799 #define OPTION_EB (OPTION_MD_BASE + 0)
19801 #define OPTION_EL (OPTION_MD_BASE + 1)
19805 struct option md_longopts
[] =
19808 {"EB", no_argument
, NULL
, OPTION_EB
},
19811 {"EL", no_argument
, NULL
, OPTION_EL
},
19813 {NULL
, no_argument
, NULL
, 0}
19816 size_t md_longopts_size
= sizeof (md_longopts
);
19818 struct arm_option_table
19820 char *option
; /* Option name to match. */
19821 char *help
; /* Help information. */
19822 int *var
; /* Variable to change. */
19823 int value
; /* What to change it to. */
19824 char *deprecated
; /* If non-null, print this message. */
19827 struct arm_option_table arm_opts
[] =
19829 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19830 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19831 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19832 &support_interwork
, 1, NULL
},
19833 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19834 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19835 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19837 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19838 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19839 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19840 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19843 /* These are recognized by the assembler, but have no affect on code. */
19844 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19845 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19846 {NULL
, NULL
, NULL
, 0, NULL
}
19849 struct arm_legacy_option_table
19851 char *option
; /* Option name to match. */
19852 const arm_feature_set
**var
; /* Variable to change. */
19853 const arm_feature_set value
; /* What to change it to. */
19854 char *deprecated
; /* If non-null, print this message. */
19857 const struct arm_legacy_option_table arm_legacy_opts
[] =
19859 /* DON'T add any new processors to this list -- we want the whole list
19860 to go away... Add them to the processors table instead. */
19861 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19862 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19863 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19864 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19865 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19866 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19867 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19868 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19869 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19870 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19871 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19872 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19873 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19874 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19875 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19876 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19877 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19878 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19879 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19880 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19881 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19882 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19883 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19884 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19885 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19886 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19887 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19888 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19889 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19890 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19891 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19892 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19893 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19894 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19895 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19896 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19897 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19898 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19899 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19900 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19901 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19902 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19903 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19904 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19905 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19906 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19907 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19908 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19909 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19910 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19911 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19912 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19913 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19914 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19915 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19916 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19917 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19918 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19919 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19920 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19921 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19922 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19923 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19924 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19925 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19926 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19927 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19928 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19929 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19930 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19931 N_("use -mcpu=strongarm110")},
19932 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19933 N_("use -mcpu=strongarm1100")},
19934 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19935 N_("use -mcpu=strongarm1110")},
19936 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19937 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19938 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19940 /* Architecture variants -- don't add any more to this list either. */
19941 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19942 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19943 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19944 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19945 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19946 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19947 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19948 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19949 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19950 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19951 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19952 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19953 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19954 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19955 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19956 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19957 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19958 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19960 /* Floating point variants -- don't add any more to this list either. */
19961 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19962 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19963 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19964 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19965 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19967 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19970 struct arm_cpu_option_table
19973 const arm_feature_set value
;
19974 /* For some CPUs we assume an FPU unless the user explicitly sets
19976 const arm_feature_set default_fpu
;
19977 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19979 const char *canonical_name
;
19982 /* This list should, at a minimum, contain all the cpu names
19983 recognized by GCC. */
19984 static const struct arm_cpu_option_table arm_cpus
[] =
19986 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19987 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19988 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19989 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19990 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19991 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19992 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19993 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19994 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19995 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19996 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19997 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19998 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19999 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20000 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20001 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20002 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20003 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20004 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20005 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20006 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20007 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20008 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20009 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20010 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20011 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20012 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20013 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20014 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20015 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20016 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20017 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20018 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20019 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20020 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20021 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20022 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20023 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20024 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20025 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20026 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20027 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20028 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20029 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20030 /* For V5 or later processors we default to using VFP; but the user
20031 should really set the FPU type explicitly. */
20032 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20033 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20034 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20035 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20036 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20037 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20038 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20039 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20040 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20041 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20042 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20043 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20044 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20045 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20046 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20047 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20048 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20049 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20050 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20051 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20052 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20053 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20054 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20055 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20056 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20057 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20058 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20059 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20060 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20061 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20062 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20063 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20064 | FPU_NEON_EXT_V1
),
20066 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20067 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20068 /* ??? XSCALE is really an architecture. */
20069 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20070 /* ??? iwmmxt is not a processor. */
20071 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20072 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20073 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20075 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20076 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20079 struct arm_arch_option_table
20082 const arm_feature_set value
;
20083 const arm_feature_set default_fpu
;
20086 /* This list should, at a minimum, contain all the architecture names
20087 recognized by GCC. */
20088 static const struct arm_arch_option_table arm_archs
[] =
20090 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20091 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20092 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20093 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20094 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20095 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20096 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20097 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20098 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20099 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20100 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20101 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20102 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20103 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20104 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20105 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20106 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20107 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20108 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20109 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20110 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20111 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20112 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20113 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20114 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20115 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20116 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20117 /* The official spelling of the ARMv7 profile variants is the dashed form.
20118 Accept the non-dashed form for compatibility with old toolchains. */
20119 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20120 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20121 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20122 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20123 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20124 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20125 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20126 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20127 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20128 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20131 /* ISA extensions in the co-processor space. */
20132 struct arm_option_cpu_value_table
20135 const arm_feature_set value
;
20138 static const struct arm_option_cpu_value_table arm_extensions
[] =
20140 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20141 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20142 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20143 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20144 {NULL
, ARM_ARCH_NONE
}
20147 /* This list should, at a minimum, contain all the fpu names
20148 recognized by GCC. */
20149 static const struct arm_option_cpu_value_table arm_fpus
[] =
20151 {"softfpa", FPU_NONE
},
20152 {"fpe", FPU_ARCH_FPE
},
20153 {"fpe2", FPU_ARCH_FPE
},
20154 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20155 {"fpa", FPU_ARCH_FPA
},
20156 {"fpa10", FPU_ARCH_FPA
},
20157 {"fpa11", FPU_ARCH_FPA
},
20158 {"arm7500fe", FPU_ARCH_FPA
},
20159 {"softvfp", FPU_ARCH_VFP
},
20160 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20161 {"vfp", FPU_ARCH_VFP_V2
},
20162 {"vfp9", FPU_ARCH_VFP_V2
},
20163 {"vfp3", FPU_ARCH_VFP_V3
},
20164 {"vfp10", FPU_ARCH_VFP_V2
},
20165 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20166 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20167 {"arm1020t", FPU_ARCH_VFP_V1
},
20168 {"arm1020e", FPU_ARCH_VFP_V2
},
20169 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20170 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20171 {"maverick", FPU_ARCH_MAVERICK
},
20172 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20173 {NULL
, ARM_ARCH_NONE
}
20176 struct arm_option_value_table
20182 static const struct arm_option_value_table arm_float_abis
[] =
20184 {"hard", ARM_FLOAT_ABI_HARD
},
20185 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20186 {"soft", ARM_FLOAT_ABI_SOFT
},
20191 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20192 static const struct arm_option_value_table arm_eabis
[] =
20194 {"gnu", EF_ARM_EABI_UNKNOWN
},
20195 {"4", EF_ARM_EABI_VER4
},
20196 {"5", EF_ARM_EABI_VER5
},
20201 struct arm_long_option_table
20203 char * option
; /* Substring to match. */
20204 char * help
; /* Help information. */
20205 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20206 char * deprecated
; /* If non-null, print this message. */
20210 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20212 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20214 /* Copy the feature set, so that we can modify it. */
20215 *ext_set
= **opt_p
;
20218 while (str
!= NULL
&& *str
!= 0)
20220 const struct arm_option_cpu_value_table
* opt
;
20226 as_bad (_("invalid architectural extension"));
20231 ext
= strchr (str
, '+');
20234 optlen
= ext
- str
;
20236 optlen
= strlen (str
);
20240 as_bad (_("missing architectural extension"));
20244 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20245 if (strncmp (opt
->name
, str
, optlen
) == 0)
20247 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20251 if (opt
->name
== NULL
)
20253 as_bad (_("unknown architectural extension `%s'"), str
);
20264 arm_parse_cpu (char * str
)
20266 const struct arm_cpu_option_table
* opt
;
20267 char * ext
= strchr (str
, '+');
20271 optlen
= ext
- str
;
20273 optlen
= strlen (str
);
20277 as_bad (_("missing cpu name `%s'"), str
);
20281 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20282 if (strncmp (opt
->name
, str
, optlen
) == 0)
20284 mcpu_cpu_opt
= &opt
->value
;
20285 mcpu_fpu_opt
= &opt
->default_fpu
;
20286 if (opt
->canonical_name
)
20287 strcpy (selected_cpu_name
, opt
->canonical_name
);
20291 for (i
= 0; i
< optlen
; i
++)
20292 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20293 selected_cpu_name
[i
] = 0;
20297 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20302 as_bad (_("unknown cpu `%s'"), str
);
20307 arm_parse_arch (char * str
)
20309 const struct arm_arch_option_table
*opt
;
20310 char *ext
= strchr (str
, '+');
20314 optlen
= ext
- str
;
20316 optlen
= strlen (str
);
20320 as_bad (_("missing architecture name `%s'"), str
);
20324 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20325 if (streq (opt
->name
, str
))
20327 march_cpu_opt
= &opt
->value
;
20328 march_fpu_opt
= &opt
->default_fpu
;
20329 strcpy (selected_cpu_name
, opt
->name
);
20332 return arm_parse_extension (ext
, &march_cpu_opt
);
20337 as_bad (_("unknown architecture `%s'\n"), str
);
20342 arm_parse_fpu (char * str
)
20344 const struct arm_option_cpu_value_table
* opt
;
20346 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20347 if (streq (opt
->name
, str
))
20349 mfpu_opt
= &opt
->value
;
20353 as_bad (_("unknown floating point format `%s'\n"), str
);
20358 arm_parse_float_abi (char * str
)
20360 const struct arm_option_value_table
* opt
;
20362 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
20363 if (streq (opt
->name
, str
))
20365 mfloat_abi_opt
= opt
->value
;
20369 as_bad (_("unknown floating point abi `%s'\n"), str
);
20375 arm_parse_eabi (char * str
)
20377 const struct arm_option_value_table
*opt
;
20379 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
20380 if (streq (opt
->name
, str
))
20382 meabi_flags
= opt
->value
;
20385 as_bad (_("unknown EABI `%s'\n"), str
);
20390 struct arm_long_option_table arm_long_opts
[] =
20392 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
20393 arm_parse_cpu
, NULL
},
20394 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
20395 arm_parse_arch
, NULL
},
20396 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
20397 arm_parse_fpu
, NULL
},
20398 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
20399 arm_parse_float_abi
, NULL
},
20401 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
20402 arm_parse_eabi
, NULL
},
20404 {NULL
, NULL
, 0, NULL
}
20408 md_parse_option (int c
, char * arg
)
20410 struct arm_option_table
*opt
;
20411 const struct arm_legacy_option_table
*fopt
;
20412 struct arm_long_option_table
*lopt
;
20418 target_big_endian
= 1;
20424 target_big_endian
= 0;
20429 /* Listing option. Just ignore these, we don't support additional
20434 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20436 if (c
== opt
->option
[0]
20437 && ((arg
== NULL
&& opt
->option
[1] == 0)
20438 || streq (arg
, opt
->option
+ 1)))
20440 #if WARN_DEPRECATED
20441 /* If the option is deprecated, tell the user. */
20442 if (opt
->deprecated
!= NULL
)
20443 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20444 arg
? arg
: "", _(opt
->deprecated
));
20447 if (opt
->var
!= NULL
)
20448 *opt
->var
= opt
->value
;
20454 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
20456 if (c
== fopt
->option
[0]
20457 && ((arg
== NULL
&& fopt
->option
[1] == 0)
20458 || streq (arg
, fopt
->option
+ 1)))
20460 #if WARN_DEPRECATED
20461 /* If the option is deprecated, tell the user. */
20462 if (fopt
->deprecated
!= NULL
)
20463 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
20464 arg
? arg
: "", _(fopt
->deprecated
));
20467 if (fopt
->var
!= NULL
)
20468 *fopt
->var
= &fopt
->value
;
20474 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20476 /* These options are expected to have an argument. */
20477 if (c
== lopt
->option
[0]
20479 && strncmp (arg
, lopt
->option
+ 1,
20480 strlen (lopt
->option
+ 1)) == 0)
20482 #if WARN_DEPRECATED
20483 /* If the option is deprecated, tell the user. */
20484 if (lopt
->deprecated
!= NULL
)
20485 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
20486 _(lopt
->deprecated
));
20489 /* Call the sup-option parser. */
20490 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
20501 md_show_usage (FILE * fp
)
20503 struct arm_option_table
*opt
;
20504 struct arm_long_option_table
*lopt
;
20506 fprintf (fp
, _(" ARM-specific assembler options:\n"));
20508 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
20509 if (opt
->help
!= NULL
)
20510 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
20512 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
20513 if (lopt
->help
!= NULL
)
20514 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
20518 -EB assemble code for a big-endian cpu\n"));
20523 -EL assemble code for a little-endian cpu\n"));
20532 arm_feature_set flags
;
20533 } cpu_arch_ver_table
;
20535 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
20536 least features first. */
20537 static const cpu_arch_ver_table cpu_arch_ver
[] =
20542 {4, ARM_ARCH_V5TE
},
20543 {5, ARM_ARCH_V5TEJ
},
20547 {9, ARM_ARCH_V6T2
},
20548 {10, ARM_ARCH_V7A
},
20549 {10, ARM_ARCH_V7R
},
20550 {10, ARM_ARCH_V7M
},
20554 /* Set the public EABI object attributes. */
20556 aeabi_set_public_attributes (void)
20559 arm_feature_set flags
;
20560 arm_feature_set tmp
;
20561 const cpu_arch_ver_table
*p
;
20563 /* Choose the architecture based on the capabilities of the requested cpu
20564 (if any) and/or the instructions actually used. */
20565 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20566 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20567 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20568 /*Allow the user to override the reported architecture. */
20571 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
20572 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
20577 for (p
= cpu_arch_ver
; p
->val
; p
++)
20579 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20582 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20586 /* Tag_CPU_name. */
20587 if (selected_cpu_name
[0])
20591 p
= selected_cpu_name
;
20592 if (strncmp (p
, "armv", 4) == 0)
20597 for (i
= 0; p
[i
]; i
++)
20598 p
[i
] = TOUPPER (p
[i
]);
20600 bfd_elf_add_proc_attr_string (stdoutput
, 5, p
);
20602 /* Tag_CPU_arch. */
20603 bfd_elf_add_proc_attr_int (stdoutput
, 6, arch
);
20604 /* Tag_CPU_arch_profile. */
20605 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20606 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'A');
20607 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20608 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'R');
20609 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20610 bfd_elf_add_proc_attr_int (stdoutput
, 7, 'M');
20611 /* Tag_ARM_ISA_use. */
20612 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20613 bfd_elf_add_proc_attr_int (stdoutput
, 8, 1);
20614 /* Tag_THUMB_ISA_use. */
20615 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20616 bfd_elf_add_proc_attr_int (stdoutput
, 9,
20617 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20618 /* Tag_VFP_arch. */
20619 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20620 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20621 bfd_elf_add_proc_attr_int (stdoutput
, 10, 3);
20622 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20623 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20624 bfd_elf_add_proc_attr_int (stdoutput
, 10, 2);
20625 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20626 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20627 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20628 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20629 bfd_elf_add_proc_attr_int (stdoutput
, 10, 1);
20630 /* Tag_WMMX_arch. */
20631 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20632 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20633 bfd_elf_add_proc_attr_int (stdoutput
, 11, 1);
20634 /* Tag_NEON_arch. */
20635 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20636 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20637 bfd_elf_add_proc_attr_int (stdoutput
, 12, 1);
20640 /* Add the default contents for the .ARM.attributes section. */
20644 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20647 aeabi_set_public_attributes ();
20649 #endif /* OBJ_ELF */
20652 /* Parse a .cpu directive. */
20655 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20657 const struct arm_cpu_option_table
*opt
;
20661 name
= input_line_pointer
;
20662 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20663 input_line_pointer
++;
20664 saved_char
= *input_line_pointer
;
20665 *input_line_pointer
= 0;
20667 /* Skip the first "all" entry. */
20668 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20669 if (streq (opt
->name
, name
))
20671 mcpu_cpu_opt
= &opt
->value
;
20672 selected_cpu
= opt
->value
;
20673 if (opt
->canonical_name
)
20674 strcpy (selected_cpu_name
, opt
->canonical_name
);
20678 for (i
= 0; opt
->name
[i
]; i
++)
20679 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20680 selected_cpu_name
[i
] = 0;
20682 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20683 *input_line_pointer
= saved_char
;
20684 demand_empty_rest_of_line ();
20687 as_bad (_("unknown cpu `%s'"), name
);
20688 *input_line_pointer
= saved_char
;
20689 ignore_rest_of_line ();
20693 /* Parse a .arch directive. */
20696 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20698 const struct arm_arch_option_table
*opt
;
20702 name
= input_line_pointer
;
20703 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20704 input_line_pointer
++;
20705 saved_char
= *input_line_pointer
;
20706 *input_line_pointer
= 0;
20708 /* Skip the first "all" entry. */
20709 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20710 if (streq (opt
->name
, name
))
20712 mcpu_cpu_opt
= &opt
->value
;
20713 selected_cpu
= opt
->value
;
20714 strcpy (selected_cpu_name
, opt
->name
);
20715 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20716 *input_line_pointer
= saved_char
;
20717 demand_empty_rest_of_line ();
20721 as_bad (_("unknown architecture `%s'\n"), name
);
20722 *input_line_pointer
= saved_char
;
20723 ignore_rest_of_line ();
20727 /* Parse a .object_arch directive. */
20730 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
20732 const struct arm_arch_option_table
*opt
;
20736 name
= input_line_pointer
;
20737 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20738 input_line_pointer
++;
20739 saved_char
= *input_line_pointer
;
20740 *input_line_pointer
= 0;
20742 /* Skip the first "all" entry. */
20743 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20744 if (streq (opt
->name
, name
))
20746 object_arch
= &opt
->value
;
20747 *input_line_pointer
= saved_char
;
20748 demand_empty_rest_of_line ();
20752 as_bad (_("unknown architecture `%s'\n"), name
);
20753 *input_line_pointer
= saved_char
;
20754 ignore_rest_of_line ();
20758 /* Parse a .fpu directive. */
20761 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20763 const struct arm_option_cpu_value_table
*opt
;
20767 name
= input_line_pointer
;
20768 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
20769 input_line_pointer
++;
20770 saved_char
= *input_line_pointer
;
20771 *input_line_pointer
= 0;
20773 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20774 if (streq (opt
->name
, name
))
20776 mfpu_opt
= &opt
->value
;
20777 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20778 *input_line_pointer
= saved_char
;
20779 demand_empty_rest_of_line ();
20783 as_bad (_("unknown floating point format `%s'\n"), name
);
20784 *input_line_pointer
= saved_char
;
20785 ignore_rest_of_line ();
20788 /* Copy symbol information. */
20790 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
20792 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);